1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.503581 # Number of seconds simulated
4sim_ticks 2503580880500 # Number of ticks simulated
5final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 80550 # Simulator instruction rate (inst/s)
8host_op_rate 104045 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3392180683 # Simulator tick rate (ticks/s)
10host_mem_usage 382816 # Number of bytes of host memory used
11host_seconds 738.04 # Real time elapsed on the host
12sim_insts 59449329 # Number of instructions simulated
13sim_ops 76789886 # Number of ops (including micro ops) simulated
14system.nvmem.bytes_read 64 # Number of bytes read from this memory
15system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
16system.nvmem.bytes_written 0 # Number of bytes written to this memory
17system.nvmem.num_reads 1 # Number of read requests responded to by this memory
18system.nvmem.num_writes 0 # Number of write requests responded to by this memory
19system.nvmem.num_other 0 # Number of other requests responded to by this memory
20system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
21system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
22system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
23system.physmem.bytes_read 130729872 # Number of bytes read from this memory
24system.physmem.bytes_inst_read 1100224 # Number of instructions bytes read from this memory
25system.physmem.bytes_written 9585224 # Number of bytes written to this memory
26system.physmem.num_reads 15117120 # Number of read requests responded to by this memory
27system.physmem.num_writes 856661 # Number of write requests responded to by this memory
28system.physmem.num_other 0 # Number of other requests responded to by this memory
29system.physmem.bw_read 52217155 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read 439460 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write 3828606 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total 56045761 # Total bandwidth to/from this memory (bytes/s)
33system.l2c.replacements 119505 # number of replacements
34system.l2c.tagsinuse 25834.929390 # Cycle average of tags in use
35system.l2c.total_refs 1795685 # Total number of references to valid blocks.
36system.l2c.sampled_refs 150314 # Sample count of references to valid blocks.
37system.l2c.avg_refs 11.946226 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 14304.535648 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu.dtb.walker 48.618373 # Average occupied blocks per requestor
41system.l2c.occ_blocks::cpu.itb.walker 3.761343 # Average occupied blocks per requestor
42system.l2c.occ_blocks::cpu.inst 6047.704729 # Average occupied blocks per requestor
43system.l2c.occ_blocks::cpu.data 5430.309296 # Average occupied blocks per requestor
44system.l2c.occ_percent::writebacks 0.218270 # Average percentage of cache occupancy
45system.l2c.occ_percent::cpu.dtb.walker 0.000742 # Average percentage of cache occupancy
46system.l2c.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy
47system.l2c.occ_percent::cpu.inst 0.092281 # Average percentage of cache occupancy
48system.l2c.occ_percent::cpu.data 0.082860 # Average percentage of cache occupancy
49system.l2c.occ_percent::total 0.394210 # Average percentage of cache occupancy
50system.l2c.ReadReq_hits::cpu.dtb.walker 143695 # number of ReadReq hits
51system.l2c.ReadReq_hits::cpu.itb.walker 9582 # number of ReadReq hits
52system.l2c.ReadReq_hits::cpu.inst 973305 # number of ReadReq hits
53system.l2c.ReadReq_hits::cpu.data 376230 # number of ReadReq hits
54system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits
55system.l2c.Writeback_hits::writebacks 630148 # number of Writeback hits
56system.l2c.Writeback_hits::total 630148 # number of Writeback hits
57system.l2c.UpgradeReq_hits::cpu.data 47 # number of UpgradeReq hits
58system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits
59system.l2c.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits
60system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits
61system.l2c.ReadExReq_hits::cpu.data 105970 # number of ReadExReq hits
62system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits
63system.l2c.demand_hits::cpu.dtb.walker 143695 # number of demand (read+write) hits
64system.l2c.demand_hits::cpu.itb.walker 9582 # number of demand (read+write) hits
65system.l2c.demand_hits::cpu.inst 973305 # number of demand (read+write) hits
66system.l2c.demand_hits::cpu.data 482200 # number of demand (read+write) hits
67system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits
68system.l2c.overall_hits::cpu.dtb.walker 143695 # number of overall hits
69system.l2c.overall_hits::cpu.itb.walker 9582 # number of overall hits
70system.l2c.overall_hits::cpu.inst 973305 # number of overall hits
71system.l2c.overall_hits::cpu.data 482200 # number of overall hits
72system.l2c.overall_hits::total 1608782 # number of overall hits
73system.l2c.ReadReq_misses::cpu.dtb.walker 134 # number of ReadReq misses
74system.l2c.ReadReq_misses::cpu.itb.walker 16 # number of ReadReq misses
75system.l2c.ReadReq_misses::cpu.inst 17088 # number of ReadReq misses
76system.l2c.ReadReq_misses::cpu.data 19000 # number of ReadReq misses
77system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses
78system.l2c.UpgradeReq_misses::cpu.data 3252 # number of UpgradeReq misses
79system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses
80system.l2c.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
81system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
82system.l2c.ReadExReq_misses::cpu.data 140397 # number of ReadExReq misses
83system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses
84system.l2c.demand_misses::cpu.dtb.walker 134 # number of demand (read+write) misses
85system.l2c.demand_misses::cpu.itb.walker 16 # number of demand (read+write) misses
86system.l2c.demand_misses::cpu.inst 17088 # number of demand (read+write) misses
87system.l2c.demand_misses::cpu.data 159397 # number of demand (read+write) misses
88system.l2c.demand_misses::total 176635 # number of demand (read+write) misses
89system.l2c.overall_misses::cpu.dtb.walker 134 # number of overall misses
90system.l2c.overall_misses::cpu.itb.walker 16 # number of overall misses
91system.l2c.overall_misses::cpu.inst 17088 # number of overall misses
92system.l2c.overall_misses::cpu.data 159397 # number of overall misses
93system.l2c.overall_misses::total 176635 # number of overall misses
94system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7004000 # number of ReadReq miss cycles
95system.l2c.ReadReq_miss_latency::cpu.itb.walker 843500 # number of ReadReq miss cycles
96system.l2c.ReadReq_miss_latency::cpu.inst 894670500 # number of ReadReq miss cycles
97system.l2c.ReadReq_miss_latency::cpu.data 993024500 # number of ReadReq miss cycles
98system.l2c.ReadReq_miss_latency::total 1895542500 # number of ReadReq miss cycles
99system.l2c.UpgradeReq_miss_latency::cpu.data 1059500 # number of UpgradeReq miss cycles
100system.l2c.UpgradeReq_miss_latency::total 1059500 # number of UpgradeReq miss cycles
101system.l2c.ReadExReq_miss_latency::cpu.data 7383005500 # number of ReadExReq miss cycles
102system.l2c.ReadExReq_miss_latency::total 7383005500 # number of ReadExReq miss cycles
103system.l2c.demand_miss_latency::cpu.dtb.walker 7004000 # number of demand (read+write) miss cycles
104system.l2c.demand_miss_latency::cpu.itb.walker 843500 # number of demand (read+write) miss cycles
105system.l2c.demand_miss_latency::cpu.inst 894670500 # number of demand (read+write) miss cycles
106system.l2c.demand_miss_latency::cpu.data 8376030000 # number of demand (read+write) miss cycles
107system.l2c.demand_miss_latency::total 9278548000 # number of demand (read+write) miss cycles
108system.l2c.overall_miss_latency::cpu.dtb.walker 7004000 # number of overall miss cycles
109system.l2c.overall_miss_latency::cpu.itb.walker 843500 # number of overall miss cycles
110system.l2c.overall_miss_latency::cpu.inst 894670500 # number of overall miss cycles
111system.l2c.overall_miss_latency::cpu.data 8376030000 # number of overall miss cycles
112system.l2c.overall_miss_latency::total 9278548000 # number of overall miss cycles
113system.l2c.ReadReq_accesses::cpu.dtb.walker 143829 # number of ReadReq accesses(hits+misses)
114system.l2c.ReadReq_accesses::cpu.itb.walker 9598 # number of ReadReq accesses(hits+misses)
115system.l2c.ReadReq_accesses::cpu.inst 990393 # number of ReadReq accesses(hits+misses)
116system.l2c.ReadReq_accesses::cpu.data 395230 # number of ReadReq accesses(hits+misses)
117system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses)
118system.l2c.Writeback_accesses::writebacks 630148 # number of Writeback accesses(hits+misses)
119system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses)
120system.l2c.UpgradeReq_accesses::cpu.data 3299 # number of UpgradeReq accesses(hits+misses)
121system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses)
122system.l2c.SCUpgradeReq_accesses::cpu.data 21 # number of SCUpgradeReq accesses(hits+misses)
123system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses)
124system.l2c.ReadExReq_accesses::cpu.data 246367 # number of ReadExReq accesses(hits+misses)
125system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses)
126system.l2c.demand_accesses::cpu.dtb.walker 143829 # number of demand (read+write) accesses
127system.l2c.demand_accesses::cpu.itb.walker 9598 # number of demand (read+write) accesses
128system.l2c.demand_accesses::cpu.inst 990393 # number of demand (read+write) accesses
129system.l2c.demand_accesses::cpu.data 641597 # number of demand (read+write) accesses
130system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses
131system.l2c.overall_accesses::cpu.dtb.walker 143829 # number of overall (read+write) accesses
132system.l2c.overall_accesses::cpu.itb.walker 9598 # number of overall (read+write) accesses
133system.l2c.overall_accesses::cpu.inst 990393 # number of overall (read+write) accesses
134system.l2c.overall_accesses::cpu.data 641597 # number of overall (read+write) accesses
135system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses
136system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000932 # miss rate for ReadReq accesses
137system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses
138system.l2c.ReadReq_miss_rate::cpu.inst 0.017254 # miss rate for ReadReq accesses
139system.l2c.ReadReq_miss_rate::cpu.data 0.048073 # miss rate for ReadReq accesses
140system.l2c.UpgradeReq_miss_rate::cpu.data 0.985753 # miss rate for UpgradeReq accesses
141system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.190476 # miss rate for SCUpgradeReq accesses
142system.l2c.ReadExReq_miss_rate::cpu.data 0.569869 # miss rate for ReadExReq accesses
143system.l2c.demand_miss_rate::cpu.dtb.walker 0.000932 # miss rate for demand accesses
144system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses
145system.l2c.demand_miss_rate::cpu.inst 0.017254 # miss rate for demand accesses
146system.l2c.demand_miss_rate::cpu.data 0.248438 # miss rate for demand accesses
147system.l2c.overall_miss_rate::cpu.dtb.walker 0.000932 # miss rate for overall accesses
148system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses
149system.l2c.overall_miss_rate::cpu.inst 0.017254 # miss rate for overall accesses
150system.l2c.overall_miss_rate::cpu.data 0.248438 # miss rate for overall accesses
151system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52268.656716 # average ReadReq miss latency
152system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52718.750000 # average ReadReq miss latency
153system.l2c.ReadReq_avg_miss_latency::cpu.inst 52356.653792 # average ReadReq miss latency
154system.l2c.ReadReq_avg_miss_latency::cpu.data 52264.447368 # average ReadReq miss latency
155system.l2c.UpgradeReq_avg_miss_latency::cpu.data 325.799508 # average UpgradeReq miss latency
156system.l2c.ReadExReq_avg_miss_latency::cpu.data 52586.632905 # average ReadExReq miss latency
157system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency
158system.l2c.demand_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency
159system.l2c.demand_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency
160system.l2c.demand_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency
161system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency
162system.l2c.overall_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency
163system.l2c.overall_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency
164system.l2c.overall_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency
165system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
166system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
167system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
168system.l2c.blocked::no_targets 0 # number of cycles access was blocked
169system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
170system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
171system.l2c.fast_writes 0 # number of fast writes performed
172system.l2c.cache_copies 0 # number of cache copies performed
173system.l2c.writebacks::writebacks 102643 # number of writebacks
174system.l2c.writebacks::total 102643 # number of writebacks
175system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
176system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
177system.l2c.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
178system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
179system.l2c.demand_mshr_hits::cpu.data 80 # number of demand (read+write) MSHR hits
180system.l2c.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
181system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
182system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits
183system.l2c.overall_mshr_hits::total 94 # number of overall MSHR hits
184system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 134 # number of ReadReq MSHR misses
185system.l2c.ReadReq_mshr_misses::cpu.itb.walker 16 # number of ReadReq MSHR misses
186system.l2c.ReadReq_mshr_misses::cpu.inst 17074 # number of ReadReq MSHR misses
187system.l2c.ReadReq_mshr_misses::cpu.data 18920 # number of ReadReq MSHR misses
188system.l2c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses
189system.l2c.UpgradeReq_mshr_misses::cpu.data 3252 # number of UpgradeReq MSHR misses
190system.l2c.UpgradeReq_mshr_misses::total 3252 # number of UpgradeReq MSHR misses
191system.l2c.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
192system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
193system.l2c.ReadExReq_mshr_misses::cpu.data 140397 # number of ReadExReq MSHR misses
194system.l2c.ReadExReq_mshr_misses::total 140397 # number of ReadExReq MSHR misses
195system.l2c.demand_mshr_misses::cpu.dtb.walker 134 # number of demand (read+write) MSHR misses
196system.l2c.demand_mshr_misses::cpu.itb.walker 16 # number of demand (read+write) MSHR misses
197system.l2c.demand_mshr_misses::cpu.inst 17074 # number of demand (read+write) MSHR misses
198system.l2c.demand_mshr_misses::cpu.data 159317 # number of demand (read+write) MSHR misses
199system.l2c.demand_mshr_misses::total 176541 # number of demand (read+write) MSHR misses
200system.l2c.overall_mshr_misses::cpu.dtb.walker 134 # number of overall MSHR misses
201system.l2c.overall_mshr_misses::cpu.itb.walker 16 # number of overall MSHR misses
202system.l2c.overall_mshr_misses::cpu.inst 17074 # number of overall MSHR misses
203system.l2c.overall_mshr_misses::cpu.data 159317 # number of overall MSHR misses
204system.l2c.overall_mshr_misses::total 176541 # number of overall MSHR misses
205system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5376000 # number of ReadReq MSHR miss cycles
206system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 651000 # number of ReadReq MSHR miss cycles
207system.l2c.ReadReq_mshr_miss_latency::cpu.inst 685402500 # number of ReadReq MSHR miss cycles
208system.l2c.ReadReq_mshr_miss_latency::cpu.data 759038500 # number of ReadReq MSHR miss cycles
209system.l2c.ReadReq_mshr_miss_latency::total 1450468000 # number of ReadReq MSHR miss cycles
210system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 131324500 # number of UpgradeReq MSHR miss cycles
211system.l2c.UpgradeReq_mshr_miss_latency::total 131324500 # number of UpgradeReq MSHR miss cycles
212system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 160000 # number of SCUpgradeReq MSHR miss cycles
213system.l2c.SCUpgradeReq_mshr_miss_latency::total 160000 # number of SCUpgradeReq MSHR miss cycles
214system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639183500 # number of ReadExReq MSHR miss cycles
215system.l2c.ReadExReq_mshr_miss_latency::total 5639183500 # number of ReadExReq MSHR miss cycles
216system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5376000 # number of demand (read+write) MSHR miss cycles
217system.l2c.demand_mshr_miss_latency::cpu.itb.walker 651000 # number of demand (read+write) MSHR miss cycles
218system.l2c.demand_mshr_miss_latency::cpu.inst 685402500 # number of demand (read+write) MSHR miss cycles
219system.l2c.demand_mshr_miss_latency::cpu.data 6398222000 # number of demand (read+write) MSHR miss cycles
220system.l2c.demand_mshr_miss_latency::total 7089651500 # number of demand (read+write) MSHR miss cycles
221system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5376000 # number of overall MSHR miss cycles
222system.l2c.overall_mshr_miss_latency::cpu.itb.walker 651000 # number of overall MSHR miss cycles
223system.l2c.overall_mshr_miss_latency::cpu.inst 685402500 # number of overall MSHR miss cycles
224system.l2c.overall_mshr_miss_latency::cpu.data 6398222000 # number of overall MSHR miss cycles
225system.l2c.overall_mshr_miss_latency::total 7089651500 # number of overall MSHR miss cycles
226system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 4738500 # number of ReadReq MSHR uncacheable cycles
227system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765344000 # number of ReadReq MSHR uncacheable cycles
228system.l2c.ReadReq_mshr_uncacheable_latency::total 131770082500 # number of ReadReq MSHR uncacheable cycles
229system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32364127897 # number of WriteReq MSHR uncacheable cycles
230system.l2c.WriteReq_mshr_uncacheable_latency::total 32364127897 # number of WriteReq MSHR uncacheable cycles
231system.l2c.overall_mshr_uncacheable_latency::cpu.inst 4738500 # number of overall MSHR uncacheable cycles
232system.l2c.overall_mshr_uncacheable_latency::cpu.data 164129471897 # number of overall MSHR uncacheable cycles
233system.l2c.overall_mshr_uncacheable_latency::total 164134210397 # number of overall MSHR uncacheable cycles
234system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for ReadReq accesses
235system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses
236system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for ReadReq accesses
237system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.047871 # mshr miss rate for ReadReq accesses
238system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985753 # mshr miss rate for UpgradeReq accesses
239system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.190476 # mshr miss rate for SCUpgradeReq accesses
240system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569869 # mshr miss rate for ReadExReq accesses
241system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for demand accesses
242system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses
243system.l2c.demand_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for demand accesses
244system.l2c.demand_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for demand accesses
245system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for overall accesses
246system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses
247system.l2c.overall_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for overall accesses
248system.l2c.overall_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for overall accesses
249system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average ReadReq mshr miss latency
250system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average ReadReq mshr miss latency
251system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.053766 # average ReadReq mshr miss latency
252system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40118.313953 # average ReadReq mshr miss latency
253system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40382.687577 # average UpgradeReq mshr miss latency
254system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
255system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891 # average ReadExReq mshr miss latency
256system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency
257system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency
258system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency
259system.l2c.demand_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency
260system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency
261system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency
262system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency
263system.l2c.overall_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency
264system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
265system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
266system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
267system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
268system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
269system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
270system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
271system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
272system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
273system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
274system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
275system.cf0.dma_write_txs 0 # Number of DMA write transactions.
276system.cpu.dtb.inst_hits 0 # ITB inst hits
277system.cpu.dtb.inst_misses 0 # ITB inst misses
278system.cpu.dtb.read_hits 52219999 # DTB read hits
279system.cpu.dtb.read_misses 90279 # DTB read misses
280system.cpu.dtb.write_hits 11976179 # DTB write hits
281system.cpu.dtb.write_misses 25577 # DTB write misses
282system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
283system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
284system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
285system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
286system.cpu.dtb.flush_entries 4346 # Number of entries that have been flushed from TLB
287system.cpu.dtb.align_faults 6089 # Number of TLB faults due to alignment restrictions
288system.cpu.dtb.prefetch_faults 654 # Number of TLB faults due to prefetch
289system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
290system.cpu.dtb.perms_faults 2193 # Number of TLB faults due to permissions restrictions
291system.cpu.dtb.read_accesses 52310278 # DTB read accesses
292system.cpu.dtb.write_accesses 12001756 # DTB write accesses
293system.cpu.dtb.inst_accesses 0 # ITB inst accesses
294system.cpu.dtb.hits 64196178 # DTB hits
295system.cpu.dtb.misses 115856 # DTB misses
296system.cpu.dtb.accesses 64312034 # DTB accesses
297system.cpu.itb.inst_hits 14123674 # ITB inst hits
298system.cpu.itb.inst_misses 9885 # ITB inst misses
299system.cpu.itb.read_hits 0 # DTB read hits
300system.cpu.itb.read_misses 0 # DTB read misses
301system.cpu.itb.write_hits 0 # DTB write hits
302system.cpu.itb.write_misses 0 # DTB write misses
303system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
304system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
305system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
306system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
307system.cpu.itb.flush_entries 2599 # Number of entries that have been flushed from TLB
308system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
309system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
310system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
311system.cpu.itb.perms_faults 7902 # Number of TLB faults due to permissions restrictions
312system.cpu.itb.read_accesses 0 # DTB read accesses
313system.cpu.itb.write_accesses 0 # DTB write accesses
314system.cpu.itb.inst_accesses 14133559 # ITB inst accesses
315system.cpu.itb.hits 14123674 # DTB hits
316system.cpu.itb.misses 9885 # DTB misses
317system.cpu.itb.accesses 14133559 # DTB accesses
318system.cpu.numCycles 415943429 # number of cpu cycles simulated
319system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
320system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
321system.cpu.BPredUnit.lookups 16201364 # Number of BP lookups
322system.cpu.BPredUnit.condPredicted 12549421 # Number of conditional branches predicted
323system.cpu.BPredUnit.condIncorrect 1109380 # Number of conditional branches incorrect
324system.cpu.BPredUnit.BTBLookups 13917593 # Number of BTB lookups
325system.cpu.BPredUnit.BTBHits 10243002 # Number of BTB hits
326system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
327system.cpu.BPredUnit.usedRAS 1423675 # Number of times the RAS was used to get a target.
328system.cpu.BPredUnit.RASInCorrect 227604 # Number of incorrect RAS predictions.
329system.cpu.fetch.icacheStallCycles 32912368 # Number of cycles fetch is stalled on an Icache miss
330system.cpu.fetch.Insts 104836271 # Number of instructions fetch has processed
331system.cpu.fetch.Branches 16201364 # Number of branches that fetch encountered
332system.cpu.fetch.predictedBranches 11666677 # Number of branches that fetch has predicted taken
333system.cpu.fetch.Cycles 24487466 # Number of cycles fetch has run and was not squashing or blocked
334system.cpu.fetch.SquashCycles 7079059 # Number of cycles fetch has spent squashing
335system.cpu.fetch.TlbCycles 131458 # Number of cycles fetch has spent waiting for tlb
336system.cpu.fetch.BlockedCycles 92859775 # Number of cycles fetch has spent blocked
337system.cpu.fetch.MiscStallCycles 2945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
338system.cpu.fetch.PendingTrapStallCycles 145565 # Number of stall cycles due to pending traps
339system.cpu.fetch.PendingQuiesceStallCycles 217503 # Number of stall cycles due to pending quiesce instructions
340system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR
341system.cpu.fetch.CacheLines 14115008 # Number of cache lines fetched
342system.cpu.fetch.IcacheSquashes 1041610 # Number of outstanding Icache misses that were squashed
343system.cpu.fetch.ItlbSquashes 4861 # Number of outstanding ITLB misses that were squashed
344system.cpu.fetch.rateDist::samples 155569254 # Number of instructions fetched each cycle (Total)
345system.cpu.fetch.rateDist::mean 0.838536 # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::stdev 2.184070 # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::0 131107551 84.28% 84.28% # Number of instructions fetched each cycle (Total)
349system.cpu.fetch.rateDist::1 1739904 1.12% 85.39% # Number of instructions fetched each cycle (Total)
350system.cpu.fetch.rateDist::2 2616632 1.68% 87.08% # Number of instructions fetched each cycle (Total)
351system.cpu.fetch.rateDist::3 3657999 2.35% 89.43% # Number of instructions fetched each cycle (Total)
352system.cpu.fetch.rateDist::4 2164577 1.39% 90.82% # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.rateDist::5 1434404 0.92% 91.74% # Number of instructions fetched each cycle (Total)
354system.cpu.fetch.rateDist::6 2630326 1.69% 93.43% # Number of instructions fetched each cycle (Total)
355system.cpu.fetch.rateDist::7 851935 0.55% 93.98% # Number of instructions fetched each cycle (Total)
356system.cpu.fetch.rateDist::8 9365926 6.02% 100.00% # Number of instructions fetched each cycle (Total)
357system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::total 155569254 # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.branchRate 0.038951 # Number of branch fetches per cycle
362system.cpu.fetch.rate 0.252045 # Number of inst fetches per cycle
363system.cpu.decode.IdleCycles 35134284 # Number of cycles decode is idle
364system.cpu.decode.BlockedCycles 92713878 # Number of cycles decode is blocked
365system.cpu.decode.RunCycles 21991115 # Number of cycles decode is running
366system.cpu.decode.UnblockCycles 1092987 # Number of cycles decode is unblocking
367system.cpu.decode.SquashCycles 4636990 # Number of cycles decode is squashing
368system.cpu.decode.BranchResolved 2313958 # Number of times decode resolved a branch
369system.cpu.decode.BranchMispred 177730 # Number of times decode detected a branch misprediction
370system.cpu.decode.DecodedInsts 122065816 # Number of instructions handled by decode
371system.cpu.decode.SquashedInsts 573184 # Number of squashed instructions handled by decode
372system.cpu.rename.SquashCycles 4636990 # Number of cycles rename is squashing
373system.cpu.rename.IdleCycles 37283411 # Number of cycles rename is idle
374system.cpu.rename.BlockCycles 36813700 # Number of cycles rename is blocking
375system.cpu.rename.serializeStallCycles 49928995 # count of cycles rename stalled for serializing inst
376system.cpu.rename.RunCycles 20929371 # Number of cycles rename is running
377system.cpu.rename.UnblockCycles 5976787 # Number of cycles rename is unblocking
378system.cpu.rename.RenamedInsts 113968448 # Number of instructions processed by rename
379system.cpu.rename.ROBFullEvents 4165 # Number of times rename has blocked due to ROB full
380system.cpu.rename.IQFullEvents 915244 # Number of times rename has blocked due to IQ full
381system.cpu.rename.LSQFullEvents 3983499 # Number of times rename has blocked due to LSQ full
382system.cpu.rename.FullRegisterEvents 42655 # Number of times there has been no free registers
383system.cpu.rename.RenamedOperands 118524115 # Number of destination operands rename has renamed
384system.cpu.rename.RenameLookups 524000264 # Number of register rename lookups that rename has made
385system.cpu.rename.int_rename_lookups 523903687 # Number of integer rename lookups
386system.cpu.rename.fp_rename_lookups 96577 # Number of floating rename lookups
387system.cpu.rename.CommittedMaps 77492548 # Number of HB maps that are committed
388system.cpu.rename.UndoneMaps 41031566 # Number of HB maps that are undone due to squashing
389system.cpu.rename.serializingInsts 1204512 # count of serializing insts renamed
390system.cpu.rename.tempSerializingInsts 1098851 # count of temporary serializing insts renamed
391system.cpu.rename.skidInsts 12310506 # count of insts added to the skid buffer
392system.cpu.memDep0.insertedLoads 21988549 # Number of loads inserted to the mem dependence unit.
393system.cpu.memDep0.insertedStores 14164932 # Number of stores inserted to the mem dependence unit.
394system.cpu.memDep0.conflictingLoads 1902928 # Number of conflicting loads.
395system.cpu.memDep0.conflictingStores 2266136 # Number of conflicting stores.
396system.cpu.iq.iqInstsAdded 102902284 # Number of instructions added to the IQ (excludes non-spec)
397system.cpu.iq.iqNonSpecInstsAdded 1875395 # Number of non-speculative instructions added to the IQ
398system.cpu.iq.iqInstsIssued 126904684 # Number of instructions issued
399system.cpu.iq.iqSquashedInstsIssued 253228 # Number of squashed instructions issued
400system.cpu.iq.iqSquashedInstsExamined 27017748 # Number of squashed instructions iterated over during squash; mainly for profiling
401system.cpu.iq.iqSquashedOperandsExamined 72978464 # Number of squashed operands that are examined and possibly removed from graph
402system.cpu.iq.iqSquashedNonSpecRemoved 375688 # Number of squashed non-spec instructions that were removed
403system.cpu.iq.issued_per_cycle::samples 155569254 # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::mean 0.815744 # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::stdev 1.505343 # Number of insts issued each cycle
406system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
407system.cpu.iq.issued_per_cycle::0 108923700 70.02% 70.02% # Number of insts issued each cycle
408system.cpu.iq.issued_per_cycle::1 15131938 9.73% 79.74% # Number of insts issued each cycle
409system.cpu.iq.issued_per_cycle::2 7543329 4.85% 84.59% # Number of insts issued each cycle
410system.cpu.iq.issued_per_cycle::3 6524442 4.19% 88.79% # Number of insts issued each cycle
411system.cpu.iq.issued_per_cycle::4 12759852 8.20% 96.99% # Number of insts issued each cycle
412system.cpu.iq.issued_per_cycle::5 2730334 1.76% 98.74% # Number of insts issued each cycle
413system.cpu.iq.issued_per_cycle::6 1400610 0.90% 99.64% # Number of insts issued each cycle
414system.cpu.iq.issued_per_cycle::7 422368 0.27% 99.91% # Number of insts issued each cycle
415system.cpu.iq.issued_per_cycle::8 132681 0.09% 100.00% # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::total 155569254 # Number of insts issued each cycle
420system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
421system.cpu.iq.fu_full::IntAlu 45526 0.51% 0.51% # attempts to use FU when none available
422system.cpu.iq.fu_full::IntMult 7 0.00% 0.51% # attempts to use FU when none available
423system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available
424system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available
425system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available
426system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available
427system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available
428system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available
429system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available
450system.cpu.iq.fu_full::MemRead 8417505 94.61% 95.12% # attempts to use FU when none available
451system.cpu.iq.fu_full::MemWrite 433723 4.88% 100.00% # attempts to use FU when none available
452system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
453system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
454system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
455system.cpu.iq.FU_type_0::IntAlu 60099266 47.36% 47.44% # Type of FU issued
456system.cpu.iq.FU_type_0::IntMult 96421 0.08% 47.52% # Type of FU issued
457system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued
458system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued
459system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued
460system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued
461system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued
462system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued
463system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 47.52% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.52% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued
476system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued
477system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued
478system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued
479system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued
480system.cpu.iq.FU_type_0::SimdFloatMisc 2248 0.00% 47.52% # Type of FU issued
481system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
482system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued
483system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
484system.cpu.iq.FU_type_0::MemRead 53941927 42.51% 90.03% # Type of FU issued
485system.cpu.iq.FU_type_0::MemWrite 12658279 9.97% 100.00% # Type of FU issued
486system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
487system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
488system.cpu.iq.FU_type_0::total 126904684 # Type of FU issued
489system.cpu.iq.rate 0.305101 # Inst issue rate
490system.cpu.iq.fu_busy_cnt 8896761 # FU busy when requested
491system.cpu.iq.fu_busy_rate 0.070106 # FU busy rate (busy events/executed inst)
492system.cpu.iq.int_inst_queue_reads 418619840 # Number of integer instruction queue reads
493system.cpu.iq.int_inst_queue_writes 131813494 # Number of integer instruction queue writes
494system.cpu.iq.int_inst_queue_wakeup_accesses 87332577 # Number of integer instruction queue wakeup accesses
495system.cpu.iq.fp_inst_queue_reads 23940 # Number of floating instruction queue reads
496system.cpu.iq.fp_inst_queue_writes 13540 # Number of floating instruction queue writes
497system.cpu.iq.fp_inst_queue_wakeup_accesses 10418 # Number of floating instruction queue wakeup accesses
498system.cpu.iq.int_alu_accesses 135682181 # Number of integer alu accesses
499system.cpu.iq.fp_alu_accesses 12734 # Number of floating point alu accesses
500system.cpu.iew.lsq.thread0.forwLoads 614286 # Number of loads that had data forwarded from stores
501system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
502system.cpu.iew.lsq.thread0.squashedLoads 6307786 # Number of loads squashed
503system.cpu.iew.lsq.thread0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed
504system.cpu.iew.lsq.thread0.memOrderViolation 32675 # Number of memory ordering violations
505system.cpu.iew.lsq.thread0.squashedStores 2385852 # Number of stores squashed
506system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
507system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
508system.cpu.iew.lsq.thread0.rescheduledLoads 34061916 # Number of loads that were rescheduled
509system.cpu.iew.lsq.thread0.cacheBlocked 1151020 # Number of times an access to memory failed due to the cache being blocked
510system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
511system.cpu.iew.iewSquashCycles 4636990 # Number of cycles IEW is squashing
512system.cpu.iew.iewBlockCycles 28345844 # Number of cycles IEW is blocking
513system.cpu.iew.iewUnblockCycles 418518 # Number of cycles IEW is unblocking
514system.cpu.iew.iewDispatchedInsts 104992332 # Number of instructions dispatched to IQ
515system.cpu.iew.iewDispSquashedInsts 473238 # Number of squashed instructions skipped by dispatch
516system.cpu.iew.iewDispLoadInsts 21988549 # Number of dispatched load instructions
517system.cpu.iew.iewDispStoreInsts 14164932 # Number of dispatched store instructions
518system.cpu.iew.iewDispNonSpecInsts 1227782 # Number of dispatched non-speculative instructions
519system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall
520system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall
521system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations
522system.cpu.iew.predictedTakenIncorrect 852504 # Number of branches that were predicted taken incorrectly
523system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly
524system.cpu.iew.branchMispredicts 1109319 # Number of branch mispredicts detected at execute
525system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions
526system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed
527system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute
528system.cpu.iew.exec_swp 0 # number of swp insts executed
529system.cpu.iew.exec_nop 214653 # number of nop insts executed
530system.cpu.iew.exec_refs 65406640 # number of memory reference insts executed
531system.cpu.iew.exec_branches 11708135 # Number of branches executed
532system.cpu.iew.exec_stores 12489378 # Number of stores executed
533system.cpu.iew.exec_rate 0.296843 # Inst execution rate
534system.cpu.iew.wb_sent 121811310 # cumulative count of insts sent to commit
535system.cpu.iew.wb_count 87342995 # cumulative count of insts written-back
536system.cpu.iew.wb_producers 47060292 # num instructions producing a value
537system.cpu.iew.wb_consumers 86666260 # num instructions consuming a value
538system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
539system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle
540system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back
541system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
542system.cpu.commit.commitCommittedInsts 59599710 # The number of committed instructions
543system.cpu.commit.commitCommittedOps 76940267 # The number of committed instructions
544system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit
545system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards
546system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted
547system.cpu.commit.committed_per_cycle::samples 151014616 # Number of insts commited each cycle
548system.cpu.commit.committed_per_cycle::mean 0.509489 # Number of insts commited each cycle
549system.cpu.commit.committed_per_cycle::stdev 1.459114 # Number of insts commited each cycle
550system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
551system.cpu.commit.committed_per_cycle::0 122165210 80.90% 80.90% # Number of insts commited each cycle
552system.cpu.commit.committed_per_cycle::1 14833013 9.82% 90.72% # Number of insts commited each cycle
553system.cpu.commit.committed_per_cycle::2 4110348 2.72% 93.44% # Number of insts commited each cycle
554system.cpu.commit.committed_per_cycle::3 2186082 1.45% 94.89% # Number of insts commited each cycle
555system.cpu.commit.committed_per_cycle::4 1788351 1.18% 96.07% # Number of insts commited each cycle
556system.cpu.commit.committed_per_cycle::5 1361296 0.90% 96.97% # Number of insts commited each cycle
557system.cpu.commit.committed_per_cycle::6 1264343 0.84% 97.81% # Number of insts commited each cycle
558system.cpu.commit.committed_per_cycle::7 665414 0.44% 98.25% # Number of insts commited each cycle
559system.cpu.commit.committed_per_cycle::8 2640559 1.75% 100.00% # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
562system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
563system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle
564system.cpu.commit.committedInsts 59599710 # Number of instructions committed
565system.cpu.commit.committedOps 76940267 # Number of ops (including micro ops) committed
566system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
567system.cpu.commit.refs 27459843 # Number of memory references committed
568system.cpu.commit.loads 15680763 # Number of loads committed
569system.cpu.commit.membars 413065 # Number of memory barriers committed
570system.cpu.commit.branches 9891047 # Number of branches committed
571system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
572system.cpu.commit.int_insts 68493330 # Number of committed integer instructions.
573system.cpu.commit.function_calls 995601 # Number of function calls committed.
574system.cpu.commit.bw_lim_events 2640559 # number cycles where commit BW limit reached
575system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
576system.cpu.rob.rob_reads 251393815 # The number of ROB reads
577system.cpu.rob.rob_writes 214319630 # The number of ROB writes
578system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself
579system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling
580system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
581system.cpu.committedInsts 59449329 # Number of Instructions Simulated
582system.cpu.committedOps 76789886 # Number of Ops (including micro ops) Simulated
583system.cpu.committedInsts_total 59449329 # Number of Instructions Simulated
584system.cpu.cpi 6.996604 # CPI: Cycles Per Instruction
585system.cpu.cpi_total 6.996604 # CPI: Total CPI of All Threads
586system.cpu.ipc 0.142926 # IPC: Instructions Per Cycle
587system.cpu.ipc_total 0.142926 # IPC: Total IPC of All Threads
588system.cpu.int_regfile_reads 559798057 # number of integer regfile reads
589system.cpu.int_regfile_writes 89741069 # number of integer regfile writes
590system.cpu.fp_regfile_reads 8257 # number of floating regfile reads
591system.cpu.fp_regfile_writes 2814 # number of floating regfile writes
592system.cpu.misc_regfile_reads 137366935 # number of misc regfile reads
593system.cpu.misc_regfile_writes 912292 # number of misc regfile writes
594system.cpu.icache.replacements 991177 # number of replacements
595system.cpu.icache.tagsinuse 511.615293 # Cycle average of tags in use
596system.cpu.icache.total_refs 13035657 # Total number of references to valid blocks.
597system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks.
598system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks.
599system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit.
600system.cpu.icache.occ_blocks::cpu.inst 511.615293 # Average occupied blocks per requestor
601system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
602system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
603system.cpu.icache.ReadReq_hits::cpu.inst 13035657 # number of ReadReq hits
604system.cpu.icache.ReadReq_hits::total 13035657 # number of ReadReq hits
605system.cpu.icache.demand_hits::cpu.inst 13035657 # number of demand (read+write) hits
606system.cpu.icache.demand_hits::total 13035657 # number of demand (read+write) hits
607system.cpu.icache.overall_hits::cpu.inst 13035657 # number of overall hits
608system.cpu.icache.overall_hits::total 13035657 # number of overall hits
609system.cpu.icache.ReadReq_misses::cpu.inst 1079227 # number of ReadReq misses
610system.cpu.icache.ReadReq_misses::total 1079227 # number of ReadReq misses
611system.cpu.icache.demand_misses::cpu.inst 1079227 # number of demand (read+write) misses
612system.cpu.icache.demand_misses::total 1079227 # number of demand (read+write) misses
613system.cpu.icache.overall_misses::cpu.inst 1079227 # number of overall misses
614system.cpu.icache.overall_misses::total 1079227 # number of overall misses
615system.cpu.icache.ReadReq_miss_latency::cpu.inst 15906225491 # number of ReadReq miss cycles
616system.cpu.icache.ReadReq_miss_latency::total 15906225491 # number of ReadReq miss cycles
617system.cpu.icache.demand_miss_latency::cpu.inst 15906225491 # number of demand (read+write) miss cycles
618system.cpu.icache.demand_miss_latency::total 15906225491 # number of demand (read+write) miss cycles
619system.cpu.icache.overall_miss_latency::cpu.inst 15906225491 # number of overall miss cycles
620system.cpu.icache.overall_miss_latency::total 15906225491 # number of overall miss cycles
621system.cpu.icache.ReadReq_accesses::cpu.inst 14114884 # number of ReadReq accesses(hits+misses)
622system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses)
623system.cpu.icache.demand_accesses::cpu.inst 14114884 # number of demand (read+write) accesses
624system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses
625system.cpu.icache.overall_accesses::cpu.inst 14114884 # number of overall (read+write) accesses
626system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses
627system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076460 # miss rate for ReadReq accesses
628system.cpu.icache.demand_miss_rate::cpu.inst 0.076460 # miss rate for demand accesses
629system.cpu.icache.overall_miss_rate::cpu.inst 0.076460 # miss rate for overall accesses
630system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14738.535536 # average ReadReq miss latency
631system.cpu.icache.demand_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency
632system.cpu.icache.overall_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency
633system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked
634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
635system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked
636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
637system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475 # average number of cycles each access was blocked
638system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
639system.cpu.icache.fast_writes 0 # number of fast writes performed
640system.cpu.icache.cache_copies 0 # number of cache copies performed
641system.cpu.icache.writebacks::writebacks 57255 # number of writebacks
642system.cpu.icache.writebacks::total 57255 # number of writebacks
643system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87505 # number of ReadReq MSHR hits
644system.cpu.icache.ReadReq_mshr_hits::total 87505 # number of ReadReq MSHR hits
645system.cpu.icache.demand_mshr_hits::cpu.inst 87505 # number of demand (read+write) MSHR hits
646system.cpu.icache.demand_mshr_hits::total 87505 # number of demand (read+write) MSHR hits
647system.cpu.icache.overall_mshr_hits::cpu.inst 87505 # number of overall MSHR hits
648system.cpu.icache.overall_mshr_hits::total 87505 # number of overall MSHR hits
649system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991722 # number of ReadReq MSHR misses
650system.cpu.icache.ReadReq_mshr_misses::total 991722 # number of ReadReq MSHR misses
651system.cpu.icache.demand_mshr_misses::cpu.inst 991722 # number of demand (read+write) MSHR misses
652system.cpu.icache.demand_mshr_misses::total 991722 # number of demand (read+write) MSHR misses
653system.cpu.icache.overall_mshr_misses::cpu.inst 991722 # number of overall MSHR misses
654system.cpu.icache.overall_mshr_misses::total 991722 # number of overall MSHR misses
655system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11850340996 # number of ReadReq MSHR miss cycles
656system.cpu.icache.ReadReq_mshr_miss_latency::total 11850340996 # number of ReadReq MSHR miss cycles
657system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11850340996 # number of demand (read+write) MSHR miss cycles
658system.cpu.icache.demand_mshr_miss_latency::total 11850340996 # number of demand (read+write) MSHR miss cycles
659system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11850340996 # number of overall MSHR miss cycles
660system.cpu.icache.overall_mshr_miss_latency::total 11850340996 # number of overall MSHR miss cycles
661system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6359500 # number of ReadReq MSHR uncacheable cycles
662system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6359500 # number of ReadReq MSHR uncacheable cycles
663system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6359500 # number of overall MSHR uncacheable cycles
664system.cpu.icache.overall_mshr_uncacheable_latency::total 6359500 # number of overall MSHR uncacheable cycles
665system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for ReadReq accesses
666system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for demand accesses
667system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for overall accesses
668system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11949.256945 # average ReadReq mshr miss latency
669system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency
670system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency
671system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
672system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
673system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
674system.cpu.dcache.replacements 643728 # number of replacements
675system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use
676system.cpu.dcache.total_refs 22270301 # Total number of references to valid blocks.
677system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks.
678system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks.
679system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit.
680system.cpu.dcache.occ_blocks::cpu.data 511.991681 # Average occupied blocks per requestor
681system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
682system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
683system.cpu.dcache.ReadReq_hits::cpu.data 14416609 # number of ReadReq hits
684system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits
685system.cpu.dcache.WriteReq_hits::cpu.data 7264899 # number of WriteReq hits
686system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits
687system.cpu.dcache.LoadLockedReq_hits::cpu.data 299899 # number of LoadLockedReq hits
688system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits
689system.cpu.dcache.StoreCondReq_hits::cpu.data 285488 # number of StoreCondReq hits
690system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits
691system.cpu.dcache.demand_hits::cpu.data 21681508 # number of demand (read+write) hits
692system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits
693system.cpu.dcache.overall_hits::cpu.data 21681508 # number of overall hits
694system.cpu.dcache.overall_hits::total 21681508 # number of overall hits
695system.cpu.dcache.ReadReq_misses::cpu.data 722544 # number of ReadReq misses
696system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses
697system.cpu.dcache.WriteReq_misses::cpu.data 2966373 # number of WriteReq misses
698system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses
699system.cpu.dcache.LoadLockedReq_misses::cpu.data 13502 # number of LoadLockedReq misses
700system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses
701system.cpu.dcache.StoreCondReq_misses::cpu.data 21 # number of StoreCondReq misses
702system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses
703system.cpu.dcache.demand_misses::cpu.data 3688917 # number of demand (read+write) misses
704system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses
705system.cpu.dcache.overall_misses::cpu.data 3688917 # number of overall misses
706system.cpu.dcache.overall_misses::total 3688917 # number of overall misses
707system.cpu.dcache.ReadReq_miss_latency::cpu.data 10864923000 # number of ReadReq miss cycles
708system.cpu.dcache.ReadReq_miss_latency::total 10864923000 # number of ReadReq miss cycles
709system.cpu.dcache.WriteReq_miss_latency::cpu.data 110367485740 # number of WriteReq miss cycles
710system.cpu.dcache.WriteReq_miss_latency::total 110367485740 # number of WriteReq miss cycles
711system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 219139000 # number of LoadLockedReq miss cycles
712system.cpu.dcache.LoadLockedReq_miss_latency::total 219139000 # number of LoadLockedReq miss cycles
713system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 467500 # number of StoreCondReq miss cycles
714system.cpu.dcache.StoreCondReq_miss_latency::total 467500 # number of StoreCondReq miss cycles
715system.cpu.dcache.demand_miss_latency::cpu.data 121232408740 # number of demand (read+write) miss cycles
716system.cpu.dcache.demand_miss_latency::total 121232408740 # number of demand (read+write) miss cycles
717system.cpu.dcache.overall_miss_latency::cpu.data 121232408740 # number of overall miss cycles
718system.cpu.dcache.overall_miss_latency::total 121232408740 # number of overall miss cycles
719system.cpu.dcache.ReadReq_accesses::cpu.data 15139153 # number of ReadReq accesses(hits+misses)
720system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses)
721system.cpu.dcache.WriteReq_accesses::cpu.data 10231272 # number of WriteReq accesses(hits+misses)
722system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses)
723system.cpu.dcache.LoadLockedReq_accesses::cpu.data 313401 # number of LoadLockedReq accesses(hits+misses)
724system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses)
725system.cpu.dcache.StoreCondReq_accesses::cpu.data 285509 # number of StoreCondReq accesses(hits+misses)
726system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses)
727system.cpu.dcache.demand_accesses::cpu.data 25370425 # number of demand (read+write) accesses
728system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses
729system.cpu.dcache.overall_accesses::cpu.data 25370425 # number of overall (read+write) accesses
730system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses
731system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047727 # miss rate for ReadReq accesses
732system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289932 # miss rate for WriteReq accesses
733system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043082 # miss rate for LoadLockedReq accesses
734system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000074 # miss rate for StoreCondReq accesses
735system.cpu.dcache.demand_miss_rate::cpu.data 0.145402 # miss rate for demand accesses
736system.cpu.dcache.overall_miss_rate::cpu.data 0.145402 # miss rate for overall accesses
737system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15037.039959 # average ReadReq miss latency
738system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37206.206280 # average WriteReq miss latency
739system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16230.114057 # average LoadLockedReq miss latency
740system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22261.904762 # average StoreCondReq miss latency
741system.cpu.dcache.demand_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency
742system.cpu.dcache.overall_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency
743system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked
744system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked
745system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked
746system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked
747system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950 # average number of cycles each access was blocked
748system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked
749system.cpu.dcache.fast_writes 0 # number of fast writes performed
750system.cpu.dcache.cache_copies 0 # number of cache copies performed
751system.cpu.dcache.writebacks::writebacks 572893 # number of writebacks
752system.cpu.dcache.writebacks::total 572893 # number of writebacks
753system.cpu.dcache.ReadReq_mshr_hits::cpu.data 336628 # number of ReadReq MSHR hits
754system.cpu.dcache.ReadReq_mshr_hits::total 336628 # number of ReadReq MSHR hits
755system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716799 # number of WriteReq MSHR hits
756system.cpu.dcache.WriteReq_mshr_hits::total 2716799 # number of WriteReq MSHR hits
757system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits
758system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits
759system.cpu.dcache.demand_mshr_hits::cpu.data 3053427 # number of demand (read+write) MSHR hits
760system.cpu.dcache.demand_mshr_hits::total 3053427 # number of demand (read+write) MSHR hits
761system.cpu.dcache.overall_mshr_hits::cpu.data 3053427 # number of overall MSHR hits
762system.cpu.dcache.overall_mshr_hits::total 3053427 # number of overall MSHR hits
763system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385916 # number of ReadReq MSHR misses
764system.cpu.dcache.ReadReq_mshr_misses::total 385916 # number of ReadReq MSHR misses
765system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249574 # number of WriteReq MSHR misses
766system.cpu.dcache.WriteReq_mshr_misses::total 249574 # number of WriteReq MSHR misses
767system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12049 # number of LoadLockedReq MSHR misses
768system.cpu.dcache.LoadLockedReq_mshr_misses::total 12049 # number of LoadLockedReq MSHR misses
769system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 21 # number of StoreCondReq MSHR misses
770system.cpu.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses
771system.cpu.dcache.demand_mshr_misses::cpu.data 635490 # number of demand (read+write) MSHR misses
772system.cpu.dcache.demand_mshr_misses::total 635490 # number of demand (read+write) MSHR misses
773system.cpu.dcache.overall_mshr_misses::cpu.data 635490 # number of overall MSHR misses
774system.cpu.dcache.overall_mshr_misses::total 635490 # number of overall MSHR misses
775system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5245615500 # number of ReadReq MSHR miss cycles
776system.cpu.dcache.ReadReq_mshr_miss_latency::total 5245615500 # number of ReadReq MSHR miss cycles
777system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926036935 # number of WriteReq MSHR miss cycles
778system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926036935 # number of WriteReq MSHR miss cycles
779system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 161663500 # number of LoadLockedReq MSHR miss cycles
780system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 161663500 # number of LoadLockedReq MSHR miss cycles
781system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 398500 # number of StoreCondReq MSHR miss cycles
782system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 398500 # number of StoreCondReq MSHR miss cycles
783system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14171652435 # number of demand (read+write) MSHR miss cycles
784system.cpu.dcache.demand_mshr_miss_latency::total 14171652435 # number of demand (read+write) MSHR miss cycles
785system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14171652435 # number of overall MSHR miss cycles
786system.cpu.dcache.overall_mshr_miss_latency::total 14171652435 # number of overall MSHR miss cycles
787system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000 # number of ReadReq MSHR uncacheable cycles
788system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000 # number of ReadReq MSHR uncacheable cycles
789system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42287348315 # number of WriteReq MSHR uncacheable cycles
790system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42287348315 # number of WriteReq MSHR uncacheable cycles
791system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315 # number of overall MSHR uncacheable cycles
792system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315 # number of overall MSHR uncacheable cycles
793system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025491 # mshr miss rate for ReadReq accesses
794system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024393 # mshr miss rate for WriteReq accesses
795system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038446 # mshr miss rate for LoadLockedReq accesses
796system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for StoreCondReq accesses
797system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for demand accesses
798system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for overall accesses
799system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444 # average ReadReq mshr miss latency
800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456 # average WriteReq mshr miss latency
801system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550 # average LoadLockedReq mshr miss latency
802system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476 # average StoreCondReq mshr miss latency
803system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency
804system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency
805system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
806system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
807system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
808system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
809system.iocache.replacements 0 # number of replacements
810system.iocache.tagsinuse 0 # Cycle average of tags in use
811system.iocache.total_refs 0 # Total number of references to valid blocks.
812system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
813system.iocache.avg_refs no_value # Average number of references to valid blocks.
814system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
815system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
816system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
817system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
818system.iocache.blocked::no_targets 0 # number of cycles access was blocked
819system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
820system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
821system.iocache.fast_writes 0 # number of fast writes performed
822system.iocache.cache_copies 0 # number of cache copies performed
823system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of ReadReq MSHR uncacheable cycles
824system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543 # number of ReadReq MSHR uncacheable cycles
825system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of overall MSHR uncacheable cycles
826system.iocache.overall_mshr_uncacheable_latency::total 1307927966543 # number of overall MSHR uncacheable cycles
827system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
828system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
829system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
830system.cpu.kern.inst.arm 0 # number of arm instructions executed
831system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed
832
833---------- End Simulation Statistics ----------