1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.827546 # Number of seconds simulated
4sim_ticks 2827546300000 # Number of ticks simulated
5final_tick 2827546300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 101558 # Simulator instruction rate (inst/s)
8host_op_rate 123188 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2538650252 # Simulator tick rate (ticks/s)
10host_mem_usage 576848 # Number of bytes of host memory used
11host_seconds 1113.80 # Real time elapsed on the host
12sim_insts 113115023 # Number of instructions simulated
13sim_ops 137206411 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1322768 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 9763816 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 11089336 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1322768 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1322768 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 8388544 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
26system.physmem.bytes_written::total 8406068 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 22916 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 153080 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 176039 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 131071 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 135452 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 467815 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 3453106 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 3921894 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 467815 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 467815 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 2966722 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 6198 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2972920 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 2966722 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 467815 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 3459303 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 6894813 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 176040 # Number of read requests accepted
55system.physmem.writeReqs 135452 # Number of write requests accepted
56system.physmem.readBursts 176040 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 135452 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 11255936 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue
60system.physmem.bytesWritten 8418624 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 11089400 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 8406068 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 40804 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 11283 # Per bank write bursts
67system.physmem.perBankRdBursts::1 10909 # Per bank write bursts
68system.physmem.perBankRdBursts::2 10879 # Per bank write bursts
69system.physmem.perBankRdBursts::3 10544 # Per bank write bursts
70system.physmem.perBankRdBursts::4 14049 # Per bank write bursts
71system.physmem.perBankRdBursts::5 11359 # Per bank write bursts
72system.physmem.perBankRdBursts::6 11255 # Per bank write bursts
73system.physmem.perBankRdBursts::7 11497 # Per bank write bursts
74system.physmem.perBankRdBursts::8 10572 # Per bank write bursts
75system.physmem.perBankRdBursts::9 11295 # Per bank write bursts
76system.physmem.perBankRdBursts::10 10218 # Per bank write bursts
77system.physmem.perBankRdBursts::11 9589 # Per bank write bursts
78system.physmem.perBankRdBursts::12 9979 # Per bank write bursts
79system.physmem.perBankRdBursts::13 10701 # Per bank write bursts
80system.physmem.perBankRdBursts::14 10842 # Per bank write bursts
81system.physmem.perBankRdBursts::15 10903 # Per bank write bursts
82system.physmem.perBankWrBursts::0 8346 # Per bank write bursts
83system.physmem.perBankWrBursts::1 8306 # Per bank write bursts
84system.physmem.perBankWrBursts::2 8514 # Per bank write bursts
85system.physmem.perBankWrBursts::3 8219 # Per bank write bursts
86system.physmem.perBankWrBursts::4 8602 # Per bank write bursts
87system.physmem.perBankWrBursts::5 8561 # Per bank write bursts
88system.physmem.perBankWrBursts::6 8053 # Per bank write bursts
89system.physmem.perBankWrBursts::7 8529 # Per bank write bursts
90system.physmem.perBankWrBursts::8 8073 # Per bank write bursts
91system.physmem.perBankWrBursts::9 8804 # Per bank write bursts
92system.physmem.perBankWrBursts::10 7852 # Per bank write bursts
93system.physmem.perBankWrBursts::11 7407 # Per bank write bursts
94system.physmem.perBankWrBursts::12 7747 # Per bank write bursts
95system.physmem.perBankWrBursts::13 8181 # Per bank write bursts
96system.physmem.perBankWrBursts::14 8268 # Per bank write bursts
97system.physmem.perBankWrBursts::15 8079 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
100system.physmem.totGap 2827546089000 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 542 # Read request sizes (log2)
104system.physmem.readPktSize::3 14 # Read request sizes (log2)
105system.physmem.readPktSize::4 2997 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 172487 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 4381 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 131071 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 154804 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 17996 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 2231 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 828 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see

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154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 2191 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 2635 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 6262 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 6796 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 6764 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 6983 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 6948 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 8242 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 8550 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 9754 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 9146 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 8859 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 8201 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 8147 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 7161 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 6942 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 296 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 114 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 12 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 65199 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 301.760702 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 178.342640 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 324.505125 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 24507 37.59% 37.59% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 15999 24.54% 62.13% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 6852 10.51% 72.64% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3716 5.70% 78.34% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2634 4.04% 82.38% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1687 2.59% 84.96% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1128 1.73% 86.69% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1089 1.67% 88.36% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 7587 11.64% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 65199 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 6653 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 26.433789 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 560.061521 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-2047 6652 99.98% 99.98% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::total 6653 # Reads before turning the bus around for writes
231system.physmem.wrPerTurnAround::samples 6653 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::mean 19.771682 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::gmean 18.345316 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::stdev 11.497785 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::16-19 5824 87.54% 87.54% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::20-23 71 1.07% 88.61% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-27 181 2.72% 91.33% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28-31 53 0.80% 92.12% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-35 64 0.96% 93.09% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::36-39 178 2.68% 95.76% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::40-43 29 0.44% 96.20% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::44-47 6 0.09% 96.29% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::48-51 9 0.14% 96.42% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::52-55 9 0.14% 96.56% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::56-59 8 0.12% 96.68% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::60-63 6 0.09% 96.77% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::64-67 170 2.56% 99.32% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::68-71 4 0.06% 99.38% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::72-75 6 0.09% 99.47% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::76-79 8 0.12% 99.59% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::80-83 2 0.03% 99.62% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.64% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::100-103 4 0.06% 99.73% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::104-107 1 0.02% 99.74% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::120-123 1 0.02% 99.76% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::124-127 1 0.02% 99.77% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::128-131 11 0.17% 99.94% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::total 6653 # Writes before turning the bus around for reads
263system.physmem.totQLat 2123501000 # Total ticks spent queuing
264system.physmem.totMemAccLat 5421138500 # Total ticks spent from burst creation until serviced by the DRAM
265system.physmem.totBusLat 879370000 # Total ticks spent in databus transfers
266system.physmem.avgQLat 12073.99 # Average queueing delay per DRAM burst
267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
268system.physmem.avgMemAccLat 30823.99 # Average memory access latency per DRAM burst
269system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
270system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s
271system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
272system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s
273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
274system.physmem.busUtil 0.05 # Data bus utilization in percentage
275system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
276system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
277system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
278system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing
279system.physmem.readRowHits 144861 # Number of row buffer hits during reads
280system.physmem.writeRowHits 97354 # Number of row buffer hits during writes
281system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads
282system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes
283system.physmem.avgGap 9077427.64 # Average gap between requests
284system.physmem.pageHitRate 78.78 # Row buffer hit rate, read and write combined
285system.physmem_0.actEnergy 255989160 # Energy for activate commands per rank (pJ)
286system.physmem_0.preEnergy 139676625 # Energy for precharge commands per rank (pJ)
287system.physmem_0.readEnergy 715845000 # Energy for read commands per rank (pJ)
288system.physmem_0.writeEnergy 435002400 # Energy for write commands per rank (pJ)
289system.physmem_0.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ)
290system.physmem_0.actBackEnergy 81048006450 # Energy for active background per rank (pJ)
291system.physmem_0.preBackEnergy 1625432730750 # Energy for precharge background per rank (pJ)
292system.physmem_0.totalEnergy 1892708780145 # Total energy per rank (pJ)
293system.physmem_0.averagePower 669.382186 # Core power per rank (mW)
294system.physmem_0.memoryStateTime::IDLE 2703925000250 # Time in different power states
295system.physmem_0.memoryStateTime::REF 94417960000 # Time in different power states
296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
297system.physmem_0.memoryStateTime::ACT 29202842250 # Time in different power states
298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
299system.physmem_1.actEnergy 236915280 # Energy for activate commands per rank (pJ)
300system.physmem_1.preEnergy 129269250 # Energy for precharge commands per rank (pJ)
301system.physmem_1.readEnergy 655964400 # Energy for read commands per rank (pJ)
302system.physmem_1.writeEnergy 417383280 # Energy for write commands per rank (pJ)
303system.physmem_1.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ)
304system.physmem_1.actBackEnergy 80055144540 # Energy for active background per rank (pJ)
305system.physmem_1.preBackEnergy 1626303662250 # Energy for precharge background per rank (pJ)
306system.physmem_1.totalEnergy 1892479868760 # Total energy per rank (pJ)
307system.physmem_1.averagePower 669.301228 # Core power per rank (mW)
308system.physmem_1.memoryStateTime::IDLE 2705388162750 # Time in different power states
309system.physmem_1.memoryStateTime::REF 94417960000 # Time in different power states
310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
311system.physmem_1.memoryStateTime::ACT 27740163750 # Time in different power states
312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
313system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
314system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
315system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
316system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
317system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
318system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
319system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
320system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
321system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
322system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
323system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
324system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
325system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
326system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
327system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
328system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
329system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
330system.cf0.dma_write_txs 631 # Number of DMA write transactions.
331system.cpu.branchPred.lookups 46902830 # Number of BP lookups
332system.cpu.branchPred.condPredicted 24030897 # Number of conditional branches predicted
333system.cpu.branchPred.condIncorrect 1232795 # Number of conditional branches incorrect
334system.cpu.branchPred.BTBLookups 29532360 # Number of BTB lookups
335system.cpu.branchPred.BTBHits 21346058 # Number of BTB hits
336system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
337system.cpu.branchPred.BTBHitPct 72.280231 # BTB Hit Percentage
338system.cpu.branchPred.usedRAS 11742213 # Number of times the RAS was used to get a target.
339system.cpu.branchPred.RASInCorrect 33846 # Number of incorrect RAS predictions.
340system.cpu_clk_domain.clock 500 # Clock period in ticks
341system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

362system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
363system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
364system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
365system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
366system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
367system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
368system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
369system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
370system.cpu.dtb.walker.walks 72877 # Table walker walks requested
371system.cpu.dtb.walker.walksShort 72877 # Table walker walks initiated with short descriptors
372system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29786 # Level at which table walker walks with short descriptors terminate
373system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22407 # Level at which table walker walks with short descriptors terminate
374system.cpu.dtb.walker.walksSquashedBefore 20684 # Table walks squashed before starting
375system.cpu.dtb.walker.walkWaitTime::samples 52193 # Table walker wait (enqueue to first request) latency
376system.cpu.dtb.walker.walkWaitTime::mean 427.193302 # Table walker wait (enqueue to first request) latency
377system.cpu.dtb.walker.walkWaitTime::stdev 2519.151181 # Table walker wait (enqueue to first request) latency
378system.cpu.dtb.walker.walkWaitTime::0-4095 50372 96.51% 96.51% # Table walker wait (enqueue to first request) latency
379system.cpu.dtb.walker.walkWaitTime::4096-8191 577 1.11% 97.62% # Table walker wait (enqueue to first request) latency
380system.cpu.dtb.walker.walkWaitTime::8192-12287 541 1.04% 98.65% # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::12288-16383 349 0.67% 99.32% # Table walker wait (enqueue to first request) latency
382system.cpu.dtb.walker.walkWaitTime::16384-20479 64 0.12% 99.44% # Table walker wait (enqueue to first request) latency
383system.cpu.dtb.walker.walkWaitTime::20480-24575 245 0.47% 99.91% # Table walker wait (enqueue to first request) latency
384system.cpu.dtb.walker.walkWaitTime::24576-28671 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency
385system.cpu.dtb.walker.walkWaitTime::28672-32767 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency
386system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
387system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
388system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
389system.cpu.dtb.walker.walkWaitTime::45056-49151 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
390system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
391system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
392system.cpu.dtb.walker.walkWaitTime::total 52193 # Table walker wait (enqueue to first request) latency
393system.cpu.dtb.walker.walkCompletionTime::samples 18420 # Table walker service (enqueue to completion) latency
394system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955 # Table walker service (enqueue to completion) latency
395system.cpu.dtb.walker.walkCompletionTime::gmean 9894.996282 # Table walker service (enqueue to completion) latency
396system.cpu.dtb.walker.walkCompletionTime::stdev 7919.116299 # Table walker service (enqueue to completion) latency
397system.cpu.dtb.walker.walkCompletionTime::0-16383 13659 74.15% 74.15% # Table walker service (enqueue to completion) latency
398system.cpu.dtb.walker.walkCompletionTime::16384-32767 4520 24.54% 98.69% # Table walker service (enqueue to completion) latency
399system.cpu.dtb.walker.walkCompletionTime::32768-49151 229 1.24% 99.93% # Table walker service (enqueue to completion) latency
400system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.96% # Table walker service (enqueue to completion) latency
401system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
402system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency
403system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
404system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
405system.cpu.dtb.walker.walkCompletionTime::total 18420 # Table walker service (enqueue to completion) latency
406system.cpu.dtb.walker.walksPending::samples 117420807224 # Table walker pending requests distribution
407system.cpu.dtb.walker.walksPending::mean 0.629573 # Table walker pending requests distribution
408system.cpu.dtb.walker.walksPending::stdev 0.491742 # Table walker pending requests distribution
409system.cpu.dtb.walker.walksPending::0-1 117361135224 99.95% 99.95% # Table walker pending requests distribution
410system.cpu.dtb.walker.walksPending::2-3 40228000 0.03% 99.98% # Table walker pending requests distribution
411system.cpu.dtb.walker.walksPending::4-5 8514000 0.01% 99.99% # Table walker pending requests distribution
412system.cpu.dtb.walker.walksPending::6-7 6836000 0.01% 100.00% # Table walker pending requests distribution
413system.cpu.dtb.walker.walksPending::8-9 1132500 0.00% 100.00% # Table walker pending requests distribution
414system.cpu.dtb.walker.walksPending::10-11 742000 0.00% 100.00% # Table walker pending requests distribution
415system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution
416system.cpu.dtb.walker.walksPending::14-15 806000 0.00% 100.00% # Table walker pending requests distribution
417system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
418system.cpu.dtb.walker.walksPending::total 117420807224 # Table walker pending requests distribution
419system.cpu.dtb.walker.walkPageSizes::4K 6507 81.76% 81.76% # Table walker page sizes translated
420system.cpu.dtb.walker.walkPageSizes::1M 1452 18.24% 100.00% # Table walker page sizes translated
421system.cpu.dtb.walker.walkPageSizes::total 7959 # Table walker page sizes translated
422system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72877 # Table walker requests started/completed, data/inst
423system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
424system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72877 # Table walker requests started/completed, data/inst
425system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7959 # Table walker requests started/completed, data/inst
426system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
427system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7959 # Table walker requests started/completed, data/inst
428system.cpu.dtb.walker.walkRequestOrigin::total 80836 # Table walker requests started/completed, data/inst
429system.cpu.dtb.inst_hits 0 # ITB inst hits
430system.cpu.dtb.inst_misses 0 # ITB inst misses
431system.cpu.dtb.read_hits 25454298 # DTB read hits
432system.cpu.dtb.read_misses 62609 # DTB read misses
433system.cpu.dtb.write_hits 19910353 # DTB write hits
434system.cpu.dtb.write_misses 10268 # DTB write misses
435system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
436system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
437system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
438system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
439system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB
440system.cpu.dtb.align_faults 354 # Number of TLB faults due to alignment restrictions
441system.cpu.dtb.prefetch_faults 2301 # Number of TLB faults due to prefetch
442system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
443system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions
444system.cpu.dtb.read_accesses 25516907 # DTB read accesses
445system.cpu.dtb.write_accesses 19920621 # DTB write accesses
446system.cpu.dtb.inst_accesses 0 # ITB inst accesses
447system.cpu.dtb.hits 45364651 # DTB hits
448system.cpu.dtb.misses 72877 # DTB misses
449system.cpu.dtb.accesses 45437528 # DTB accesses
450system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

471system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
472system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
473system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
474system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
475system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
476system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
477system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
478system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
479system.cpu.itb.walker.walks 11947 # Table walker walks requested
480system.cpu.itb.walker.walksShort 11947 # Table walker walks initiated with short descriptors
481system.cpu.itb.walker.walksShortTerminationLevel::Level1 3916 # Level at which table walker walks with short descriptors terminate
482system.cpu.itb.walker.walksShortTerminationLevel::Level2 7772 # Level at which table walker walks with short descriptors terminate
483system.cpu.itb.walker.walksSquashedBefore 259 # Table walks squashed before starting
484system.cpu.itb.walker.walkWaitTime::samples 11688 # Table walker wait (enqueue to first request) latency
485system.cpu.itb.walker.walkWaitTime::mean 646.175565 # Table walker wait (enqueue to first request) latency
486system.cpu.itb.walker.walkWaitTime::stdev 3062.873414 # Table walker wait (enqueue to first request) latency
487system.cpu.itb.walker.walkWaitTime::0-8191 11278 96.49% 96.49% # Table walker wait (enqueue to first request) latency
488system.cpu.itb.walker.walkWaitTime::8192-16383 250 2.14% 98.63% # Table walker wait (enqueue to first request) latency
489system.cpu.itb.walker.walkWaitTime::16384-24575 145 1.24% 99.87% # Table walker wait (enqueue to first request) latency
490system.cpu.itb.walker.walkWaitTime::24576-32767 11 0.09% 99.97% # Table walker wait (enqueue to first request) latency
491system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
492system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
493system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
494system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
495system.cpu.itb.walker.walkWaitTime::total 11688 # Table walker wait (enqueue to first request) latency
496system.cpu.itb.walker.walkCompletionTime::samples 3588 # Table walker service (enqueue to completion) latency
497system.cpu.itb.walker.walkCompletionTime::mean 13165.830546 # Table walker service (enqueue to completion) latency
498system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149 # Table walker service (enqueue to completion) latency
499system.cpu.itb.walker.walkCompletionTime::stdev 7878.482425 # Table walker service (enqueue to completion) latency
500system.cpu.itb.walker.walkCompletionTime::0-8191 1266 35.28% 35.28% # Table walker service (enqueue to completion) latency
501system.cpu.itb.walker.walkCompletionTime::8192-16383 1353 37.71% 72.99% # Table walker service (enqueue to completion) latency
502system.cpu.itb.walker.walkCompletionTime::16384-24575 898 25.03% 98.02% # Table walker service (enqueue to completion) latency
503system.cpu.itb.walker.walkCompletionTime::24576-32767 28 0.78% 98.80% # Table walker service (enqueue to completion) latency
504system.cpu.itb.walker.walkCompletionTime::32768-40959 19 0.53% 99.33% # Table walker service (enqueue to completion) latency
505system.cpu.itb.walker.walkCompletionTime::40960-49151 22 0.61% 99.94% # Table walker service (enqueue to completion) latency
506system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
507system.cpu.itb.walker.walkCompletionTime::total 3588 # Table walker service (enqueue to completion) latency
508system.cpu.itb.walker.walksPending::samples 22931465712 # Table walker pending requests distribution
509system.cpu.itb.walker.walksPending::mean 0.972560 # Table walker pending requests distribution
510system.cpu.itb.walker.walksPending::stdev 0.163591 # Table walker pending requests distribution
511system.cpu.itb.walker.walksPending::0 629948000 2.75% 2.75% # Table walker pending requests distribution
512system.cpu.itb.walker.walksPending::1 22300919212 97.25% 100.00% # Table walker pending requests distribution
513system.cpu.itb.walker.walksPending::2 517500 0.00% 100.00% # Table walker pending requests distribution
514system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution
515system.cpu.itb.walker.walksPending::4 34500 0.00% 100.00% # Table walker pending requests distribution
516system.cpu.itb.walker.walksPending::total 22931465712 # Table walker pending requests distribution
517system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated
518system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated
519system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated
520system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
521system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11947 # Table walker requests started/completed, data/inst
522system.cpu.itb.walker.walkRequestOrigin_Requested::total 11947 # Table walker requests started/completed, data/inst
523system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
524system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst
525system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst
526system.cpu.itb.walker.walkRequestOrigin::total 15276 # Table walker requests started/completed, data/inst
527system.cpu.itb.inst_hits 66251443 # ITB inst hits
528system.cpu.itb.inst_misses 11947 # ITB inst misses
529system.cpu.itb.read_hits 0 # DTB read hits
530system.cpu.itb.read_misses 0 # DTB read misses
531system.cpu.itb.write_hits 0 # DTB write hits
532system.cpu.itb.write_misses 0 # DTB write misses
533system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
534system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
535system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
536system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
537system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB
538system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
539system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
540system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
541system.cpu.itb.perms_faults 2204 # Number of TLB faults due to permissions restrictions
542system.cpu.itb.read_accesses 0 # DTB read accesses
543system.cpu.itb.write_accesses 0 # DTB write accesses
544system.cpu.itb.inst_accesses 66263390 # ITB inst accesses
545system.cpu.itb.hits 66251443 # DTB hits
546system.cpu.itb.misses 11947 # DTB misses
547system.cpu.itb.accesses 66263390 # DTB accesses
548system.cpu.numCycles 263015768 # number of cpu cycles simulated
549system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
550system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
551system.cpu.fetch.icacheStallCycles 104824855 # Number of cycles fetch is stalled on an Icache miss
552system.cpu.fetch.Insts 184645834 # Number of instructions fetch has processed
553system.cpu.fetch.Branches 46902830 # Number of branches that fetch encountered
554system.cpu.fetch.predictedBranches 33088271 # Number of branches that fetch has predicted taken
555system.cpu.fetch.Cycles 147851260 # Number of cycles fetch has run and was not squashing or blocked
556system.cpu.fetch.SquashCycles 6154028 # Number of cycles fetch has spent squashing
557system.cpu.fetch.TlbCycles 194015 # Number of cycles fetch has spent waiting for tlb
558system.cpu.fetch.MiscStallCycles 8214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
559system.cpu.fetch.PendingTrapStallCycles 337761 # Number of stall cycles due to pending traps
560system.cpu.fetch.PendingQuiesceStallCycles 519343 # Number of stall cycles due to pending quiesce instructions
561system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR
562system.cpu.fetch.CacheLines 66251613 # Number of cache lines fetched
563system.cpu.fetch.IcacheSquashes 1117287 # Number of outstanding Icache misses that were squashed
564system.cpu.fetch.ItlbSquashes 5276 # Number of outstanding ITLB misses that were squashed
565system.cpu.fetch.rateDist::samples 256812577 # Number of instructions fetched each cycle (Total)
566system.cpu.fetch.rateDist::mean 0.876982 # Number of instructions fetched each cycle (Total)
567system.cpu.fetch.rateDist::stdev 1.234768 # Number of instructions fetched each cycle (Total)
568system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
569system.cpu.fetch.rateDist::0 157563978 61.35% 61.35% # Number of instructions fetched each cycle (Total)
570system.cpu.fetch.rateDist::1 29227624 11.38% 72.73% # Number of instructions fetched each cycle (Total)
571system.cpu.fetch.rateDist::2 14070468 5.48% 78.21% # Number of instructions fetched each cycle (Total)
572system.cpu.fetch.rateDist::3 55950507 21.79% 100.00% # Number of instructions fetched each cycle (Total)
573system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
574system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
575system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
576system.cpu.fetch.rateDist::total 256812577 # Number of instructions fetched each cycle (Total)
577system.cpu.fetch.branchRate 0.178327 # Number of branch fetches per cycle
578system.cpu.fetch.rate 0.702033 # Number of inst fetches per cycle
579system.cpu.decode.IdleCycles 77991094 # Number of cycles decode is idle
580system.cpu.decode.BlockedCycles 107772330 # Number of cycles decode is blocked
581system.cpu.decode.RunCycles 64608850 # Number of cycles decode is running
582system.cpu.decode.UnblockCycles 3840943 # Number of cycles decode is unblocking
583system.cpu.decode.SquashCycles 2599360 # Number of cycles decode is squashing
584system.cpu.decode.BranchResolved 3422500 # Number of times decode resolved a branch
585system.cpu.decode.BranchMispred 485951 # Number of times decode detected a branch misprediction
586system.cpu.decode.DecodedInsts 157387425 # Number of instructions handled by decode
587system.cpu.decode.SquashedInsts 3689294 # Number of squashed instructions handled by decode
588system.cpu.rename.SquashCycles 2599360 # Number of cycles rename is squashing
589system.cpu.rename.IdleCycles 83831420 # Number of cycles rename is idle
590system.cpu.rename.BlockCycles 10325294 # Number of cycles rename is blocking
591system.cpu.rename.serializeStallCycles 74929297 # count of cycles rename stalled for serializing inst
592system.cpu.rename.RunCycles 62613486 # Number of cycles rename is running
593system.cpu.rename.UnblockCycles 22513720 # Number of cycles rename is unblocking
594system.cpu.rename.RenamedInsts 146758942 # Number of instructions processed by rename
595system.cpu.rename.SquashedInsts 947731 # Number of squashed instructions processed by rename
596system.cpu.rename.ROBFullEvents 441861 # Number of times rename has blocked due to ROB full
597system.cpu.rename.IQFullEvents 64728 # Number of times rename has blocked due to IQ full
598system.cpu.rename.LQFullEvents 18116 # Number of times rename has blocked due to LQ full
599system.cpu.rename.SQFullEvents 19773665 # Number of times rename has blocked due to SQ full
600system.cpu.rename.RenamedOperands 150448126 # Number of destination operands rename has renamed
601system.cpu.rename.RenameLookups 678536041 # Number of register rename lookups that rename has made
602system.cpu.rename.int_rename_lookups 164391886 # Number of integer rename lookups
603system.cpu.rename.fp_rename_lookups 10952 # Number of floating rename lookups
604system.cpu.rename.CommittedMaps 141768145 # Number of HB maps that are committed
605system.cpu.rename.UndoneMaps 8679978 # Number of HB maps that are undone due to squashing
606system.cpu.rename.serializingInsts 2842610 # count of serializing insts renamed
607system.cpu.rename.tempSerializingInsts 2646257 # count of temporary serializing insts renamed
608system.cpu.rename.skidInsts 13861181 # count of insts added to the skid buffer
609system.cpu.memDep0.insertedLoads 26401367 # Number of loads inserted to the mem dependence unit.
610system.cpu.memDep0.insertedStores 21296245 # Number of stores inserted to the mem dependence unit.
611system.cpu.memDep0.conflictingLoads 1688204 # Number of conflicting loads.
612system.cpu.memDep0.conflictingStores 2197018 # Number of conflicting stores.
613system.cpu.iq.iqInstsAdded 143495141 # Number of instructions added to the IQ (excludes non-spec)
614system.cpu.iq.iqNonSpecInstsAdded 2119201 # Number of non-speculative instructions added to the IQ
615system.cpu.iq.iqInstsIssued 143282260 # Number of instructions issued
616system.cpu.iq.iqSquashedInstsIssued 272024 # Number of squashed instructions issued
617system.cpu.iq.iqSquashedInstsExamined 8407927 # Number of squashed instructions iterated over during squash; mainly for profiling
618system.cpu.iq.iqSquashedOperandsExamined 14689646 # Number of squashed operands that are examined and possibly removed from graph
619system.cpu.iq.iqSquashedNonSpecRemoved 125355 # Number of squashed non-spec instructions that were removed
620system.cpu.iq.issued_per_cycle::samples 256812577 # Number of insts issued each cycle
621system.cpu.iq.issued_per_cycle::mean 0.557925 # Number of insts issued each cycle
622system.cpu.iq.issued_per_cycle::stdev 0.879880 # Number of insts issued each cycle
623system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
624system.cpu.iq.issued_per_cycle::0 168546355 65.63% 65.63% # Number of insts issued each cycle
625system.cpu.iq.issued_per_cycle::1 45160300 17.58% 83.22% # Number of insts issued each cycle
626system.cpu.iq.issued_per_cycle::2 32009606 12.46% 95.68% # Number of insts issued each cycle
627system.cpu.iq.issued_per_cycle::3 10282549 4.00% 99.68% # Number of insts issued each cycle
628system.cpu.iq.issued_per_cycle::4 813734 0.32% 100.00% # Number of insts issued each cycle
629system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
630system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
631system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
632system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
633system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
634system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
635system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
636system.cpu.iq.issued_per_cycle::total 256812577 # Number of insts issued each cycle
637system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
638system.cpu.iq.fu_full::IntAlu 7349115 32.77% 32.77% # attempts to use FU when none available
639system.cpu.iq.fu_full::IntMult 31 0.00% 32.77% # attempts to use FU when none available
640system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available
641system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available
642system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available
643system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available
644system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available
645system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available
646system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
647system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available
648system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available
649system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available
650system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available
651system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available
652system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available
653system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available
654system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available
655system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available
656system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available
657system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available
658system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available
659system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available
660system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available
661system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available
662system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available
663system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available
664system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available
665system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
666system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
667system.cpu.iq.fu_full::MemRead 5633990 25.12% 57.89% # attempts to use FU when none available
668system.cpu.iq.fu_full::MemWrite 9444813 42.11% 100.00% # attempts to use FU when none available
669system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
670system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
671system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
672system.cpu.iq.FU_type_0::IntAlu 95970305 66.98% 66.98% # Type of FU issued
673system.cpu.iq.FU_type_0::IntMult 114498 0.08% 67.06% # Type of FU issued
674system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
675system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
676system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
677system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
678system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
679system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
680system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
681system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued

--- 7 unchanged lines hidden (view full) ---

689system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
690system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
691system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
692system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
693system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
694system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
695system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
696system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
697system.cpu.iq.FU_type_0::SimdFloatMisc 8584 0.01% 67.07% # Type of FU issued
698system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
699system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
700system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
701system.cpu.iq.FU_type_0::MemRead 26184358 18.27% 85.34% # Type of FU issued
702system.cpu.iq.FU_type_0::MemWrite 21002178 14.66% 100.00% # Type of FU issued
703system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
704system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
705system.cpu.iq.FU_type_0::total 143282260 # Type of FU issued
706system.cpu.iq.rate 0.544767 # Inst issue rate
707system.cpu.iq.fu_busy_cnt 22427949 # FU busy when requested
708system.cpu.iq.fu_busy_rate 0.156530 # FU busy rate (busy events/executed inst)
709system.cpu.iq.int_inst_queue_reads 566041717 # Number of integer instruction queue reads
710system.cpu.iq.int_inst_queue_writes 154027392 # Number of integer instruction queue writes
711system.cpu.iq.int_inst_queue_wakeup_accesses 140167901 # Number of integer instruction queue wakeup accesses
712system.cpu.iq.fp_inst_queue_reads 35353 # Number of floating instruction queue reads
713system.cpu.iq.fp_inst_queue_writes 13184 # Number of floating instruction queue writes
714system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
715system.cpu.iq.int_alu_accesses 165684822 # Number of integer alu accesses
716system.cpu.iq.fp_alu_accesses 23050 # Number of floating point alu accesses
717system.cpu.iew.lsq.thread0.forwLoads 323667 # Number of loads that had data forwarded from stores
718system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
719system.cpu.iew.lsq.thread0.squashedLoads 1493736 # Number of loads squashed
720system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed
721system.cpu.iew.lsq.thread0.memOrderViolation 18344 # Number of memory ordering violations
722system.cpu.iew.lsq.thread0.squashedStores 705002 # Number of stores squashed
723system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
724system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
725system.cpu.iew.lsq.thread0.rescheduledLoads 87759 # Number of loads that were rescheduled
726system.cpu.iew.lsq.thread0.cacheBlocked 6780 # Number of times an access to memory failed due to the cache being blocked
727system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
728system.cpu.iew.iewSquashCycles 2599360 # Number of cycles IEW is squashing
729system.cpu.iew.iewBlockCycles 993976 # Number of cycles IEW is blocking
730system.cpu.iew.iewUnblockCycles 306451 # Number of cycles IEW is unblocking
731system.cpu.iew.iewDispatchedInsts 145815403 # Number of instructions dispatched to IQ
732system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
733system.cpu.iew.iewDispLoadInsts 26401367 # Number of dispatched load instructions
734system.cpu.iew.iewDispStoreInsts 21296245 # Number of dispatched store instructions
735system.cpu.iew.iewDispNonSpecInsts 1095018 # Number of dispatched non-speculative instructions
736system.cpu.iew.iewIQFullEvents 17939 # Number of times the IQ has become full, causing a stall
737system.cpu.iew.iewLSQFullEvents 271517 # Number of times the LSQ has become full, causing a stall
738system.cpu.iew.memOrderViolationEvents 18344 # Number of memory order violations
739system.cpu.iew.predictedTakenIncorrect 317394 # Number of branches that were predicted taken incorrectly
740system.cpu.iew.predictedNotTakenIncorrect 471153 # Number of branches that were predicted not taken incorrectly
741system.cpu.iew.branchMispredicts 788547 # Number of branch mispredicts detected at execute
742system.cpu.iew.iewExecutedInsts 142337327 # Number of executed instructions
743system.cpu.iew.iewExecLoadInsts 25781702 # Number of load instructions executed
744system.cpu.iew.iewExecSquashedInsts 872174 # Number of squashed instructions skipped in execute
745system.cpu.iew.exec_swp 0 # number of swp insts executed
746system.cpu.iew.exec_nop 201061 # number of nop insts executed
747system.cpu.iew.exec_refs 46654499 # number of memory reference insts executed
748system.cpu.iew.exec_branches 26517785 # Number of branches executed
749system.cpu.iew.exec_stores 20872797 # Number of stores executed
750system.cpu.iew.exec_rate 0.541174 # Inst execution rate
751system.cpu.iew.wb_sent 141950761 # cumulative count of insts sent to commit
752system.cpu.iew.wb_count 140179331 # cumulative count of insts written-back
753system.cpu.iew.wb_producers 63256602 # num instructions producing a value
754system.cpu.iew.wb_consumers 95788019 # num instructions consuming a value
755system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
756system.cpu.iew.wb_rate 0.532969 # insts written-back per cycle
757system.cpu.iew.wb_fanout 0.660381 # average fanout of values written-back
758system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
759system.cpu.commit.commitSquashedInsts 7614067 # The number of squashed insts skipped by commit
760system.cpu.commit.commitNonSpecStalls 1993846 # The number of times commit has been forced to stall to communicate backwards
761system.cpu.commit.branchMispredicts 755141 # The number of times a branch was mispredicted
762system.cpu.commit.committed_per_cycle::samples 253876624 # Number of insts commited each cycle
763system.cpu.commit.committed_per_cycle::mean 0.541055 # Number of insts commited each cycle
764system.cpu.commit.committed_per_cycle::stdev 1.141749 # Number of insts commited each cycle
765system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
766system.cpu.commit.committed_per_cycle::0 180454723 71.08% 71.08% # Number of insts commited each cycle
767system.cpu.commit.committed_per_cycle::1 43255238 17.04% 88.12% # Number of insts commited each cycle
768system.cpu.commit.committed_per_cycle::2 15471181 6.09% 94.21% # Number of insts commited each cycle
769system.cpu.commit.committed_per_cycle::3 4380130 1.73% 95.94% # Number of insts commited each cycle
770system.cpu.commit.committed_per_cycle::4 6364867 2.51% 98.44% # Number of insts commited each cycle
771system.cpu.commit.committed_per_cycle::5 1673276 0.66% 99.10% # Number of insts commited each cycle
772system.cpu.commit.committed_per_cycle::6 800938 0.32% 99.42% # Number of insts commited each cycle
773system.cpu.commit.committed_per_cycle::7 418318 0.16% 99.58% # Number of insts commited each cycle
774system.cpu.commit.committed_per_cycle::8 1057953 0.42% 100.00% # Number of insts commited each cycle
775system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
776system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
777system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
778system.cpu.commit.committed_per_cycle::total 253876624 # Number of insts commited each cycle
779system.cpu.commit.committedInsts 113269928 # Number of instructions committed
780system.cpu.commit.committedOps 137361316 # Number of ops (including micro ops) committed
781system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
782system.cpu.commit.refs 45498874 # Number of memory references committed
783system.cpu.commit.loads 24907631 # Number of loads committed
784system.cpu.commit.membars 814016 # Number of memory barriers committed
785system.cpu.commit.branches 26032948 # Number of branches committed
786system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
787system.cpu.commit.int_insts 120189151 # Number of committed integer instructions.
788system.cpu.commit.function_calls 4888294 # Number of function calls committed.
789system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
790system.cpu.commit.op_class_0::IntAlu 91740391 66.79% 66.79% # Class of committed instruction
791system.cpu.commit.op_class_0::IntMult 113468 0.08% 66.87% # Class of committed instruction
792system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
793system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
794system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
795system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
796system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
797system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
798system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
799system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction

--- 7 unchanged lines hidden (view full) ---

807system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
808system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
809system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
810system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
811system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
812system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
813system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
814system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
815system.cpu.commit.op_class_0::SimdFloatMisc 8583 0.01% 66.88% # Class of committed instruction
816system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
817system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
818system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
819system.cpu.commit.op_class_0::MemRead 24907631 18.13% 85.01% # Class of committed instruction
820system.cpu.commit.op_class_0::MemWrite 20591243 14.99% 100.00% # Class of committed instruction
821system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
822system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
823system.cpu.commit.op_class_0::total 137361316 # Class of committed instruction
824system.cpu.commit.bw_lim_events 1057953 # number cycles where commit BW limit reached
825system.cpu.rob.rob_reads 375595727 # The number of ROB reads
826system.cpu.rob.rob_writes 292884314 # The number of ROB writes
827system.cpu.timesIdled 891951 # Number of times that the entire CPU went into an idle state and unscheduled itself
828system.cpu.idleCycles 6203191 # Total number of cycles that the CPU has spent unscheduled due to idling
829system.cpu.quiesceCycles 5392076833 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
830system.cpu.committedInsts 113115023 # Number of Instructions Simulated
831system.cpu.committedOps 137206411 # Number of Ops (including micro ops) Simulated
832system.cpu.cpi 2.325206 # CPI: Cycles Per Instruction
833system.cpu.cpi_total 2.325206 # CPI: Total CPI of All Threads
834system.cpu.ipc 0.430069 # IPC: Instructions Per Cycle
835system.cpu.ipc_total 0.430069 # IPC: Total IPC of All Threads
836system.cpu.int_regfile_reads 155781292 # number of integer regfile reads
837system.cpu.int_regfile_writes 88602572 # number of integer regfile writes
838system.cpu.fp_regfile_reads 9590 # number of floating regfile reads
839system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
840system.cpu.cc_regfile_reads 502823661 # number of cc regfile reads
841system.cpu.cc_regfile_writes 53168068 # number of cc regfile writes
842system.cpu.misc_regfile_reads 334407132 # number of misc regfile reads
843system.cpu.misc_regfile_writes 1519751 # number of misc regfile writes
844system.cpu.dcache.tags.replacements 839265 # number of replacements
845system.cpu.dcache.tags.tagsinuse 511.954798 # Cycle average of tags in use
846system.cpu.dcache.tags.total_refs 40095385 # Total number of references to valid blocks.
847system.cpu.dcache.tags.sampled_refs 839777 # Sample count of references to valid blocks.
848system.cpu.dcache.tags.avg_refs 47.745276 # Average number of references to valid blocks.
849system.cpu.dcache.tags.warmup_cycle 267431500 # Cycle when the warmup percentage was hit.
850system.cpu.dcache.tags.occ_blocks::cpu.data 511.954798 # Average occupied blocks per requestor
851system.cpu.dcache.tags.occ_percent::cpu.data 0.999912 # Average percentage of cache occupancy
852system.cpu.dcache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy
853system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
854system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
855system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
856system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
857system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
858system.cpu.dcache.tags.tag_accesses 179307579 # Number of tag accesses
859system.cpu.dcache.tags.data_accesses 179307579 # Number of data accesses
860system.cpu.dcache.ReadReq_hits::cpu.data 23304230 # number of ReadReq hits
861system.cpu.dcache.ReadReq_hits::total 23304230 # number of ReadReq hits
862system.cpu.dcache.WriteReq_hits::cpu.data 15542006 # number of WriteReq hits
863system.cpu.dcache.WriteReq_hits::total 15542006 # number of WriteReq hits
864system.cpu.dcache.SoftPFReq_hits::cpu.data 345703 # number of SoftPFReq hits
865system.cpu.dcache.SoftPFReq_hits::total 345703 # number of SoftPFReq hits
866system.cpu.dcache.LoadLockedReq_hits::cpu.data 441081 # number of LoadLockedReq hits
867system.cpu.dcache.LoadLockedReq_hits::total 441081 # number of LoadLockedReq hits
868system.cpu.dcache.StoreCondReq_hits::cpu.data 459484 # number of StoreCondReq hits
869system.cpu.dcache.StoreCondReq_hits::total 459484 # number of StoreCondReq hits
870system.cpu.dcache.demand_hits::cpu.data 38846236 # number of demand (read+write) hits
871system.cpu.dcache.demand_hits::total 38846236 # number of demand (read+write) hits
872system.cpu.dcache.overall_hits::cpu.data 39191939 # number of overall hits
873system.cpu.dcache.overall_hits::total 39191939 # number of overall hits
874system.cpu.dcache.ReadReq_misses::cpu.data 710133 # number of ReadReq misses
875system.cpu.dcache.ReadReq_misses::total 710133 # number of ReadReq misses
876system.cpu.dcache.WriteReq_misses::cpu.data 3609878 # number of WriteReq misses
877system.cpu.dcache.WriteReq_misses::total 3609878 # number of WriteReq misses
878system.cpu.dcache.SoftPFReq_misses::cpu.data 177558 # number of SoftPFReq misses
879system.cpu.dcache.SoftPFReq_misses::total 177558 # number of SoftPFReq misses
880system.cpu.dcache.LoadLockedReq_misses::cpu.data 26867 # number of LoadLockedReq misses
881system.cpu.dcache.LoadLockedReq_misses::total 26867 # number of LoadLockedReq misses
882system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
883system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
884system.cpu.dcache.demand_misses::cpu.data 4320011 # number of demand (read+write) misses
885system.cpu.dcache.demand_misses::total 4320011 # number of demand (read+write) misses
886system.cpu.dcache.overall_misses::cpu.data 4497569 # number of overall misses
887system.cpu.dcache.overall_misses::total 4497569 # number of overall misses
888system.cpu.dcache.ReadReq_miss_latency::cpu.data 10292232000 # number of ReadReq miss cycles
889system.cpu.dcache.ReadReq_miss_latency::total 10292232000 # number of ReadReq miss cycles
890system.cpu.dcache.WriteReq_miss_latency::cpu.data 148465108677 # number of WriteReq miss cycles
891system.cpu.dcache.WriteReq_miss_latency::total 148465108677 # number of WriteReq miss cycles
892system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365302500 # number of LoadLockedReq miss cycles
893system.cpu.dcache.LoadLockedReq_miss_latency::total 365302500 # number of LoadLockedReq miss cycles
894system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
895system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
896system.cpu.dcache.demand_miss_latency::cpu.data 158757340677 # number of demand (read+write) miss cycles
897system.cpu.dcache.demand_miss_latency::total 158757340677 # number of demand (read+write) miss cycles
898system.cpu.dcache.overall_miss_latency::cpu.data 158757340677 # number of overall miss cycles
899system.cpu.dcache.overall_miss_latency::total 158757340677 # number of overall miss cycles
900system.cpu.dcache.ReadReq_accesses::cpu.data 24014363 # number of ReadReq accesses(hits+misses)
901system.cpu.dcache.ReadReq_accesses::total 24014363 # number of ReadReq accesses(hits+misses)
902system.cpu.dcache.WriteReq_accesses::cpu.data 19151884 # number of WriteReq accesses(hits+misses)
903system.cpu.dcache.WriteReq_accesses::total 19151884 # number of WriteReq accesses(hits+misses)
904system.cpu.dcache.SoftPFReq_accesses::cpu.data 523261 # number of SoftPFReq accesses(hits+misses)
905system.cpu.dcache.SoftPFReq_accesses::total 523261 # number of SoftPFReq accesses(hits+misses)
906system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467948 # number of LoadLockedReq accesses(hits+misses)
907system.cpu.dcache.LoadLockedReq_accesses::total 467948 # number of LoadLockedReq accesses(hits+misses)
908system.cpu.dcache.StoreCondReq_accesses::cpu.data 459489 # number of StoreCondReq accesses(hits+misses)
909system.cpu.dcache.StoreCondReq_accesses::total 459489 # number of StoreCondReq accesses(hits+misses)
910system.cpu.dcache.demand_accesses::cpu.data 43166247 # number of demand (read+write) accesses
911system.cpu.dcache.demand_accesses::total 43166247 # number of demand (read+write) accesses
912system.cpu.dcache.overall_accesses::cpu.data 43689508 # number of overall (read+write) accesses
913system.cpu.dcache.overall_accesses::total 43689508 # number of overall (read+write) accesses
914system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses
915system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses
916system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188487 # miss rate for WriteReq accesses
917system.cpu.dcache.WriteReq_miss_rate::total 0.188487 # miss rate for WriteReq accesses
918system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339330 # miss rate for SoftPFReq accesses
919system.cpu.dcache.SoftPFReq_miss_rate::total 0.339330 # miss rate for SoftPFReq accesses
920system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057414 # miss rate for LoadLockedReq accesses
921system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057414 # miss rate for LoadLockedReq accesses
922system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
923system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
924system.cpu.dcache.demand_miss_rate::cpu.data 0.100078 # miss rate for demand accesses
925system.cpu.dcache.demand_miss_rate::total 0.100078 # miss rate for demand accesses
926system.cpu.dcache.overall_miss_rate::cpu.data 0.102944 # miss rate for overall accesses
927system.cpu.dcache.overall_miss_rate::total 0.102944 # miss rate for overall accesses
928system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14493.386450 # average ReadReq miss latency
929system.cpu.dcache.ReadReq_avg_miss_latency::total 14493.386450 # average ReadReq miss latency
930system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41127.458789 # average WriteReq miss latency
931system.cpu.dcache.WriteReq_avg_miss_latency::total 41127.458789 # average WriteReq miss latency
932system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13596.698552 # average LoadLockedReq miss latency
933system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13596.698552 # average LoadLockedReq miss latency
934system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
935system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
936system.cpu.dcache.demand_avg_miss_latency::cpu.data 36749.290841 # average overall miss latency
937system.cpu.dcache.demand_avg_miss_latency::total 36749.290841 # average overall miss latency
938system.cpu.dcache.overall_avg_miss_latency::cpu.data 35298.478062 # average overall miss latency
939system.cpu.dcache.overall_avg_miss_latency::total 35298.478062 # average overall miss latency
940system.cpu.dcache.blocked_cycles::no_mshrs 590707 # number of cycles access was blocked
941system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
942system.cpu.dcache.blocked::no_mshrs 7439 # number of cycles access was blocked
943system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
944system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.406775 # average number of cycles each access was blocked
945system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
946system.cpu.dcache.fast_writes 0 # number of fast writes performed
947system.cpu.dcache.cache_copies 0 # number of cache copies performed
948system.cpu.dcache.writebacks::writebacks 696043 # number of writebacks
949system.cpu.dcache.writebacks::total 696043 # number of writebacks
950system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295841 # number of ReadReq MSHR hits
951system.cpu.dcache.ReadReq_mshr_hits::total 295841 # number of ReadReq MSHR hits
952system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309634 # number of WriteReq MSHR hits
953system.cpu.dcache.WriteReq_mshr_hits::total 3309634 # number of WriteReq MSHR hits
954system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18475 # number of LoadLockedReq MSHR hits
955system.cpu.dcache.LoadLockedReq_mshr_hits::total 18475 # number of LoadLockedReq MSHR hits
956system.cpu.dcache.demand_mshr_hits::cpu.data 3605475 # number of demand (read+write) MSHR hits
957system.cpu.dcache.demand_mshr_hits::total 3605475 # number of demand (read+write) MSHR hits
958system.cpu.dcache.overall_mshr_hits::cpu.data 3605475 # number of overall MSHR hits
959system.cpu.dcache.overall_mshr_hits::total 3605475 # number of overall MSHR hits
960system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414292 # number of ReadReq MSHR misses
961system.cpu.dcache.ReadReq_mshr_misses::total 414292 # number of ReadReq MSHR misses
962system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300244 # number of WriteReq MSHR misses
963system.cpu.dcache.WriteReq_mshr_misses::total 300244 # number of WriteReq MSHR misses
964system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119628 # number of SoftPFReq MSHR misses
965system.cpu.dcache.SoftPFReq_mshr_misses::total 119628 # number of SoftPFReq MSHR misses
966system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8392 # number of LoadLockedReq MSHR misses
967system.cpu.dcache.LoadLockedReq_mshr_misses::total 8392 # number of LoadLockedReq MSHR misses
968system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
969system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
970system.cpu.dcache.demand_mshr_misses::cpu.data 714536 # number of demand (read+write) MSHR misses
971system.cpu.dcache.demand_mshr_misses::total 714536 # number of demand (read+write) MSHR misses
972system.cpu.dcache.overall_mshr_misses::cpu.data 834164 # number of overall MSHR misses
973system.cpu.dcache.overall_mshr_misses::total 834164 # number of overall MSHR misses
974system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
975system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
976system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
977system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
978system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
979system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
980system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5857375000 # number of ReadReq MSHR miss cycles
981system.cpu.dcache.ReadReq_mshr_miss_latency::total 5857375000 # number of ReadReq MSHR miss cycles
982system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13373750471 # number of WriteReq MSHR miss cycles
983system.cpu.dcache.WriteReq_mshr_miss_latency::total 13373750471 # number of WriteReq MSHR miss cycles
984system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1627994000 # number of SoftPFReq MSHR miss cycles
985system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1627994000 # number of SoftPFReq MSHR miss cycles
986system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 128038500 # number of LoadLockedReq MSHR miss cycles
987system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128038500 # number of LoadLockedReq MSHR miss cycles
988system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 204000 # number of StoreCondReq MSHR miss cycles
989system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 204000 # number of StoreCondReq MSHR miss cycles
990system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19231125471 # number of demand (read+write) MSHR miss cycles
991system.cpu.dcache.demand_mshr_miss_latency::total 19231125471 # number of demand (read+write) MSHR miss cycles
992system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20859119471 # number of overall MSHR miss cycles
993system.cpu.dcache.overall_mshr_miss_latency::total 20859119471 # number of overall MSHR miss cycles
994system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5908113500 # number of ReadReq MSHR uncacheable cycles
995system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5908113500 # number of ReadReq MSHR uncacheable cycles
996system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4570874950 # number of WriteReq MSHR uncacheable cycles
997system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4570874950 # number of WriteReq MSHR uncacheable cycles
998system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10478988450 # number of overall MSHR uncacheable cycles
999system.cpu.dcache.overall_mshr_uncacheable_latency::total 10478988450 # number of overall MSHR uncacheable cycles
1000system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017252 # mshr miss rate for ReadReq accesses
1001system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017252 # mshr miss rate for ReadReq accesses
1002system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015677 # mshr miss rate for WriteReq accesses
1003system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015677 # mshr miss rate for WriteReq accesses
1004system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228620 # mshr miss rate for SoftPFReq accesses
1005system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228620 # mshr miss rate for SoftPFReq accesses
1006system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017934 # mshr miss rate for LoadLockedReq accesses
1007system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017934 # mshr miss rate for LoadLockedReq accesses
1008system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
1009system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
1010system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016553 # mshr miss rate for demand accesses
1011system.cpu.dcache.demand_mshr_miss_rate::total 0.016553 # mshr miss rate for demand accesses
1012system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019093 # mshr miss rate for overall accesses
1013system.cpu.dcache.overall_mshr_miss_rate::total 0.019093 # mshr miss rate for overall accesses
1014system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868 # average ReadReq mshr miss latency
1015system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868 # average ReadReq mshr miss latency
1016system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979 # average WriteReq mshr miss latency
1017system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979 # average WriteReq mshr miss latency
1018system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959 # average SoftPFReq mshr miss latency
1019system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959 # average SoftPFReq mshr miss latency
1020system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247 # average LoadLockedReq mshr miss latency
1021system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247 # average LoadLockedReq mshr miss latency
1022system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40800 # average StoreCondReq mshr miss latency
1023system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40800 # average StoreCondReq mshr miss latency
1024system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943 # average overall mshr miss latency
1025system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943 # average overall mshr miss latency
1026system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367 # average overall mshr miss latency
1027system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367 # average overall mshr miss latency
1028system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215 # average ReadReq mshr uncacheable latency
1029system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215 # average ReadReq mshr uncacheable latency
1030system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535 # average WriteReq mshr uncacheable latency
1031system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535 # average WriteReq mshr uncacheable latency
1032system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009 # average overall mshr uncacheable latency
1033system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009 # average overall mshr uncacheable latency
1034system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1035system.cpu.icache.tags.replacements 1891955 # number of replacements
1036system.cpu.icache.tags.tagsinuse 511.348314 # Cycle average of tags in use
1037system.cpu.icache.tags.total_refs 64263909 # Total number of references to valid blocks.
1038system.cpu.icache.tags.sampled_refs 1892467 # Sample count of references to valid blocks.
1039system.cpu.icache.tags.avg_refs 33.957744 # Average number of references to valid blocks.
1040system.cpu.icache.tags.warmup_cycle 13555622500 # Cycle when the warmup percentage was hit.
1041system.cpu.icache.tags.occ_blocks::cpu.inst 511.348314 # Average occupied blocks per requestor
1042system.cpu.icache.tags.occ_percent::cpu.inst 0.998727 # Average percentage of cache occupancy
1043system.cpu.icache.tags.occ_percent::total 0.998727 # Average percentage of cache occupancy
1044system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1045system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
1046system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
1047system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
1048system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
1049system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1050system.cpu.icache.tags.tag_accesses 68141093 # Number of tag accesses
1051system.cpu.icache.tags.data_accesses 68141093 # Number of data accesses
1052system.cpu.icache.ReadReq_hits::cpu.inst 64263909 # number of ReadReq hits
1053system.cpu.icache.ReadReq_hits::total 64263909 # number of ReadReq hits
1054system.cpu.icache.demand_hits::cpu.inst 64263909 # number of demand (read+write) hits
1055system.cpu.icache.demand_hits::total 64263909 # number of demand (read+write) hits
1056system.cpu.icache.overall_hits::cpu.inst 64263909 # number of overall hits
1057system.cpu.icache.overall_hits::total 64263909 # number of overall hits
1058system.cpu.icache.ReadReq_misses::cpu.inst 1984699 # number of ReadReq misses
1059system.cpu.icache.ReadReq_misses::total 1984699 # number of ReadReq misses
1060system.cpu.icache.demand_misses::cpu.inst 1984699 # number of demand (read+write) misses
1061system.cpu.icache.demand_misses::total 1984699 # number of demand (read+write) misses
1062system.cpu.icache.overall_misses::cpu.inst 1984699 # number of overall misses
1063system.cpu.icache.overall_misses::total 1984699 # number of overall misses
1064system.cpu.icache.ReadReq_miss_latency::cpu.inst 26888996997 # number of ReadReq miss cycles
1065system.cpu.icache.ReadReq_miss_latency::total 26888996997 # number of ReadReq miss cycles
1066system.cpu.icache.demand_miss_latency::cpu.inst 26888996997 # number of demand (read+write) miss cycles
1067system.cpu.icache.demand_miss_latency::total 26888996997 # number of demand (read+write) miss cycles
1068system.cpu.icache.overall_miss_latency::cpu.inst 26888996997 # number of overall miss cycles
1069system.cpu.icache.overall_miss_latency::total 26888996997 # number of overall miss cycles
1070system.cpu.icache.ReadReq_accesses::cpu.inst 66248608 # number of ReadReq accesses(hits+misses)
1071system.cpu.icache.ReadReq_accesses::total 66248608 # number of ReadReq accesses(hits+misses)
1072system.cpu.icache.demand_accesses::cpu.inst 66248608 # number of demand (read+write) accesses
1073system.cpu.icache.demand_accesses::total 66248608 # number of demand (read+write) accesses
1074system.cpu.icache.overall_accesses::cpu.inst 66248608 # number of overall (read+write) accesses
1075system.cpu.icache.overall_accesses::total 66248608 # number of overall (read+write) accesses
1076system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029958 # miss rate for ReadReq accesses
1077system.cpu.icache.ReadReq_miss_rate::total 0.029958 # miss rate for ReadReq accesses
1078system.cpu.icache.demand_miss_rate::cpu.inst 0.029958 # miss rate for demand accesses
1079system.cpu.icache.demand_miss_rate::total 0.029958 # miss rate for demand accesses
1080system.cpu.icache.overall_miss_rate::cpu.inst 0.029958 # miss rate for overall accesses
1081system.cpu.icache.overall_miss_rate::total 0.029958 # miss rate for overall accesses
1082system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609 # average ReadReq miss latency
1083system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609 # average ReadReq miss latency
1084system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency
1085system.cpu.icache.demand_avg_miss_latency::total 13548.148609 # average overall miss latency
1086system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency
1087system.cpu.icache.overall_avg_miss_latency::total 13548.148609 # average overall miss latency
1088system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked
1089system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1090system.cpu.icache.blocked::no_mshrs 127 # number of cycles access was blocked
1091system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1092system.cpu.icache.avg_blocked_cycles::no_mshrs 19.748031 # average number of cycles each access was blocked
1093system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1094system.cpu.icache.fast_writes 0 # number of fast writes performed
1095system.cpu.icache.cache_copies 0 # number of cache copies performed
1096system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92212 # number of ReadReq MSHR hits
1097system.cpu.icache.ReadReq_mshr_hits::total 92212 # number of ReadReq MSHR hits
1098system.cpu.icache.demand_mshr_hits::cpu.inst 92212 # number of demand (read+write) MSHR hits
1099system.cpu.icache.demand_mshr_hits::total 92212 # number of demand (read+write) MSHR hits
1100system.cpu.icache.overall_mshr_hits::cpu.inst 92212 # number of overall MSHR hits
1101system.cpu.icache.overall_mshr_hits::total 92212 # number of overall MSHR hits
1102system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1892487 # number of ReadReq MSHR misses
1103system.cpu.icache.ReadReq_mshr_misses::total 1892487 # number of ReadReq MSHR misses
1104system.cpu.icache.demand_mshr_misses::cpu.inst 1892487 # number of demand (read+write) MSHR misses
1105system.cpu.icache.demand_mshr_misses::total 1892487 # number of demand (read+write) MSHR misses
1106system.cpu.icache.overall_mshr_misses::cpu.inst 1892487 # number of overall MSHR misses
1107system.cpu.icache.overall_mshr_misses::total 1892487 # number of overall MSHR misses
1108system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable
1109system.cpu.icache.ReadReq_mshr_uncacheable::total 3005 # number of ReadReq MSHR uncacheable
1110system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses
1111system.cpu.icache.overall_mshr_uncacheable_misses::total 3005 # number of overall MSHR uncacheable misses
1112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24145787497 # number of ReadReq MSHR miss cycles
1113system.cpu.icache.ReadReq_mshr_miss_latency::total 24145787497 # number of ReadReq MSHR miss cycles
1114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24145787497 # number of demand (read+write) MSHR miss cycles
1115system.cpu.icache.demand_mshr_miss_latency::total 24145787497 # number of demand (read+write) MSHR miss cycles
1116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24145787497 # number of overall MSHR miss cycles
1117system.cpu.icache.overall_mshr_miss_latency::total 24145787497 # number of overall MSHR miss cycles
1118system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225776500 # number of ReadReq MSHR uncacheable cycles
1119system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225776500 # number of ReadReq MSHR uncacheable cycles
1120system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225776500 # number of overall MSHR uncacheable cycles
1121system.cpu.icache.overall_mshr_uncacheable_latency::total 225776500 # number of overall MSHR uncacheable cycles
1122system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for ReadReq accesses
1123system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028566 # mshr miss rate for ReadReq accesses
1124system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for demand accesses
1125system.cpu.icache.demand_mshr_miss_rate::total 0.028566 # mshr miss rate for demand accesses
1126system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for overall accesses
1127system.cpu.icache.overall_mshr_miss_rate::total 0.028566 # mshr miss rate for overall accesses
1128system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12758.760032 # average ReadReq mshr miss latency
1129system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12758.760032 # average ReadReq mshr miss latency
1130system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency
1131system.cpu.icache.demand_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency
1132system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency
1133system.cpu.icache.overall_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency
1134system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average ReadReq mshr uncacheable latency
1135system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75133.610649 # average ReadReq mshr uncacheable latency
1136system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average overall mshr uncacheable latency
1137system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75133.610649 # average overall mshr uncacheable latency
1138system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1139system.cpu.l2cache.tags.replacements 103023 # number of replacements
1140system.cpu.l2cache.tags.tagsinuse 65070.034194 # Cycle average of tags in use
1141system.cpu.l2cache.tags.total_refs 5007824 # Total number of references to valid blocks.
1142system.cpu.l2cache.tags.sampled_refs 168222 # Sample count of references to valid blocks.
1143system.cpu.l2cache.tags.avg_refs 29.769138 # Average number of references to valid blocks.
1144system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1145system.cpu.l2cache.tags.occ_blocks::writebacks 49133.665655 # Average occupied blocks per requestor
1146system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.985449 # Average occupied blocks per requestor
1147system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797952 # Average occupied blocks per requestor
1148system.cpu.l2cache.tags.occ_blocks::cpu.inst 10208.479538 # Average occupied blocks per requestor
1149system.cpu.l2cache.tags.occ_blocks::cpu.data 5712.105601 # Average occupied blocks per requestor
1150system.cpu.l2cache.tags.occ_percent::writebacks 0.749720 # Average percentage of cache occupancy
1151system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000198 # Average percentage of cache occupancy
1152system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy
1153system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155769 # Average percentage of cache occupancy
1154system.cpu.l2cache.tags.occ_percent::cpu.data 0.087160 # Average percentage of cache occupancy
1155system.cpu.l2cache.tags.occ_percent::total 0.992890 # Average percentage of cache occupancy
1156system.cpu.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id
1157system.cpu.l2cache.tags.occ_task_id_blocks::1024 65182 # Occupied blocks per task id
1158system.cpu.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
1159system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
1160system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
1161system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id
1162system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6860 # Occupied blocks per task id
1163system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55225 # Occupied blocks per task id
1164system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000259 # Percentage of cache occupancy per task id
1165system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994598 # Percentage of cache occupancy per task id
1166system.cpu.l2cache.tags.tag_accesses 44376961 # Number of tag accesses
1167system.cpu.l2cache.tags.data_accesses 44376961 # Number of data accesses
1168system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56023 # number of ReadReq hits
1169system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12549 # number of ReadReq hits
1170system.cpu.l2cache.ReadReq_hits::total 68572 # number of ReadReq hits
1171system.cpu.l2cache.Writeback_hits::writebacks 696043 # number of Writeback hits
1172system.cpu.l2cache.Writeback_hits::total 696043 # number of Writeback hits
1173system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits
1174system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits
1175system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
1176system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
1177system.cpu.l2cache.ReadExReq_hits::cpu.data 157187 # number of ReadExReq hits
1178system.cpu.l2cache.ReadExReq_hits::total 157187 # number of ReadExReq hits
1179system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1872509 # number of ReadCleanReq hits
1180system.cpu.l2cache.ReadCleanReq_hits::total 1872509 # number of ReadCleanReq hits
1181system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527843 # number of ReadSharedReq hits
1182system.cpu.l2cache.ReadSharedReq_hits::total 527843 # number of ReadSharedReq hits
1183system.cpu.l2cache.demand_hits::cpu.dtb.walker 56023 # number of demand (read+write) hits
1184system.cpu.l2cache.demand_hits::cpu.itb.walker 12549 # number of demand (read+write) hits
1185system.cpu.l2cache.demand_hits::cpu.inst 1872509 # number of demand (read+write) hits
1186system.cpu.l2cache.demand_hits::cpu.data 685030 # number of demand (read+write) hits
1187system.cpu.l2cache.demand_hits::total 2626111 # number of demand (read+write) hits
1188system.cpu.l2cache.overall_hits::cpu.dtb.walker 56023 # number of overall hits
1189system.cpu.l2cache.overall_hits::cpu.itb.walker 12549 # number of overall hits
1190system.cpu.l2cache.overall_hits::cpu.inst 1872509 # number of overall hits
1191system.cpu.l2cache.overall_hits::cpu.data 685030 # number of overall hits
1192system.cpu.l2cache.overall_hits::total 2626111 # number of overall hits
1193system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
1194system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
1195system.cpu.l2cache.ReadReq_misses::total 28 # number of ReadReq misses
1196system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses
1197system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses
1198system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
1199system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
1200system.cpu.l2cache.ReadExReq_misses::cpu.data 140423 # number of ReadExReq misses
1201system.cpu.l2cache.ReadExReq_misses::total 140423 # number of ReadExReq misses
1202system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19944 # number of ReadCleanReq misses
1203system.cpu.l2cache.ReadCleanReq_misses::total 19944 # number of ReadCleanReq misses
1204system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14346 # number of ReadSharedReq misses
1205system.cpu.l2cache.ReadSharedReq_misses::total 14346 # number of ReadSharedReq misses
1206system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
1207system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1208system.cpu.l2cache.demand_misses::cpu.inst 19944 # number of demand (read+write) misses
1209system.cpu.l2cache.demand_misses::cpu.data 154769 # number of demand (read+write) misses
1210system.cpu.l2cache.demand_misses::total 174741 # number of demand (read+write) misses
1211system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
1212system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1213system.cpu.l2cache.overall_misses::cpu.inst 19944 # number of overall misses
1214system.cpu.l2cache.overall_misses::cpu.data 154769 # number of overall misses
1215system.cpu.l2cache.overall_misses::total 174741 # number of overall misses
1216system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1844500 # number of ReadReq miss cycles
1217system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 579500 # number of ReadReq miss cycles
1218system.cpu.l2cache.ReadReq_miss_latency::total 2424000 # number of ReadReq miss cycles
1219system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 955000 # number of UpgradeReq miss cycles
1220system.cpu.l2cache.UpgradeReq_miss_latency::total 955000 # number of UpgradeReq miss cycles
1221system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
1222system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
1223system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11187095500 # number of ReadExReq miss cycles
1224system.cpu.l2cache.ReadExReq_miss_latency::total 11187095500 # number of ReadExReq miss cycles
1225system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1623118000 # number of ReadCleanReq miss cycles
1226system.cpu.l2cache.ReadCleanReq_miss_latency::total 1623118000 # number of ReadCleanReq miss cycles
1227system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1226117500 # number of ReadSharedReq miss cycles
1228system.cpu.l2cache.ReadSharedReq_miss_latency::total 1226117500 # number of ReadSharedReq miss cycles
1229system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1844500 # number of demand (read+write) miss cycles
1230system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 579500 # number of demand (read+write) miss cycles
1231system.cpu.l2cache.demand_miss_latency::cpu.inst 1623118000 # number of demand (read+write) miss cycles
1232system.cpu.l2cache.demand_miss_latency::cpu.data 12413213000 # number of demand (read+write) miss cycles
1233system.cpu.l2cache.demand_miss_latency::total 14038755000 # number of demand (read+write) miss cycles
1234system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1844500 # number of overall miss cycles
1235system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 579500 # number of overall miss cycles
1236system.cpu.l2cache.overall_miss_latency::cpu.inst 1623118000 # number of overall miss cycles
1237system.cpu.l2cache.overall_miss_latency::cpu.data 12413213000 # number of overall miss cycles
1238system.cpu.l2cache.overall_miss_latency::total 14038755000 # number of overall miss cycles
1239system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56044 # number of ReadReq accesses(hits+misses)
1240system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12556 # number of ReadReq accesses(hits+misses)
1241system.cpu.l2cache.ReadReq_accesses::total 68600 # number of ReadReq accesses(hits+misses)
1242system.cpu.l2cache.Writeback_accesses::writebacks 696043 # number of Writeback accesses(hits+misses)
1243system.cpu.l2cache.Writeback_accesses::total 696043 # number of Writeback accesses(hits+misses)
1244system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2757 # number of UpgradeReq accesses(hits+misses)
1245system.cpu.l2cache.UpgradeReq_accesses::total 2757 # number of UpgradeReq accesses(hits+misses)
1246system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
1247system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
1248system.cpu.l2cache.ReadExReq_accesses::cpu.data 297610 # number of ReadExReq accesses(hits+misses)
1249system.cpu.l2cache.ReadExReq_accesses::total 297610 # number of ReadExReq accesses(hits+misses)
1250system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1892453 # number of ReadCleanReq accesses(hits+misses)
1251system.cpu.l2cache.ReadCleanReq_accesses::total 1892453 # number of ReadCleanReq accesses(hits+misses)
1252system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542189 # number of ReadSharedReq accesses(hits+misses)
1253system.cpu.l2cache.ReadSharedReq_accesses::total 542189 # number of ReadSharedReq accesses(hits+misses)
1254system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56044 # number of demand (read+write) accesses
1255system.cpu.l2cache.demand_accesses::cpu.itb.walker 12556 # number of demand (read+write) accesses
1256system.cpu.l2cache.demand_accesses::cpu.inst 1892453 # number of demand (read+write) accesses
1257system.cpu.l2cache.demand_accesses::cpu.data 839799 # number of demand (read+write) accesses
1258system.cpu.l2cache.demand_accesses::total 2800852 # number of demand (read+write) accesses
1259system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56044 # number of overall (read+write) accesses
1260system.cpu.l2cache.overall_accesses::cpu.itb.walker 12556 # number of overall (read+write) accesses
1261system.cpu.l2cache.overall_accesses::cpu.inst 1892453 # number of overall (read+write) accesses
1262system.cpu.l2cache.overall_accesses::cpu.data 839799 # number of overall (read+write) accesses
1263system.cpu.l2cache.overall_accesses::total 2800852 # number of overall (read+write) accesses
1264system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses
1265system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000558 # miss rate for ReadReq accesses
1266system.cpu.l2cache.ReadReq_miss_rate::total 0.000408 # miss rate for ReadReq accesses
1267system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986942 # miss rate for UpgradeReq accesses
1268system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986942 # miss rate for UpgradeReq accesses
1269system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
1270system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
1271system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471836 # miss rate for ReadExReq accesses
1272system.cpu.l2cache.ReadExReq_miss_rate::total 0.471836 # miss rate for ReadExReq accesses
1273system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadCleanReq accesses
1274system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010539 # miss rate for ReadCleanReq accesses
1275system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026459 # miss rate for ReadSharedReq accesses
1276system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026459 # miss rate for ReadSharedReq accesses
1277system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses
1278system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000558 # miss rate for demand accesses
1279system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses
1280system.cpu.l2cache.demand_miss_rate::cpu.data 0.184293 # miss rate for demand accesses
1281system.cpu.l2cache.demand_miss_rate::total 0.062389 # miss rate for demand accesses
1282system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses
1283system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000558 # miss rate for overall accesses
1284system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses
1285system.cpu.l2cache.overall_miss_rate::cpu.data 0.184293 # miss rate for overall accesses
1286system.cpu.l2cache.overall_miss_rate::total 0.062389 # miss rate for overall accesses
1287system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87833.333333 # average ReadReq miss latency
1288system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82785.714286 # average ReadReq miss latency
1289system.cpu.l2cache.ReadReq_avg_miss_latency::total 86571.428571 # average ReadReq miss latency
1290system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 350.973907 # average UpgradeReq miss latency
1291system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 350.973907 # average UpgradeReq miss latency
1292system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
1293system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
1294system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79667.116498 # average ReadExReq miss latency
1295system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79667.116498 # average ReadExReq miss latency
1296system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81383.774569 # average ReadCleanReq miss latency
1297system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81383.774569 # average ReadCleanReq miss latency
1298system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85467.551931 # average ReadSharedReq miss latency
1299system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85467.551931 # average ReadSharedReq miss latency
1300system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency
1301system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency
1302system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency
1303system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency
1304system.cpu.l2cache.demand_avg_miss_latency::total 80340.360877 # average overall miss latency
1305system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency
1306system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency
1307system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency
1308system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency
1309system.cpu.l2cache.overall_avg_miss_latency::total 80340.360877 # average overall miss latency
1310system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1311system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1312system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1313system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1314system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1315system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1316system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1317system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1318system.cpu.l2cache.writebacks::writebacks 94881 # number of writebacks
1319system.cpu.l2cache.writebacks::total 94881 # number of writebacks
1320system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 22 # number of ReadCleanReq MSHR hits
1321system.cpu.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits
1322system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits
1323system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits
1324system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
1325system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits
1326system.cpu.l2cache.demand_mshr_hits::total 133 # number of demand (read+write) MSHR hits
1327system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
1328system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits
1329system.cpu.l2cache.overall_mshr_hits::total 133 # number of overall MSHR hits
1330system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
1331system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1332system.cpu.l2cache.ReadReq_mshr_misses::total 28 # number of ReadReq MSHR misses
1333system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses
1334system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses
1335system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1336system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1337system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140423 # number of ReadExReq MSHR misses
1338system.cpu.l2cache.ReadExReq_mshr_misses::total 140423 # number of ReadExReq MSHR misses
1339system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19922 # number of ReadCleanReq MSHR misses
1340system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19922 # number of ReadCleanReq MSHR misses
1341system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14235 # number of ReadSharedReq MSHR misses
1342system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14235 # number of ReadSharedReq MSHR misses
1343system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
1344system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1345system.cpu.l2cache.demand_mshr_misses::cpu.inst 19922 # number of demand (read+write) MSHR misses
1346system.cpu.l2cache.demand_mshr_misses::cpu.data 154658 # number of demand (read+write) MSHR misses
1347system.cpu.l2cache.demand_mshr_misses::total 174608 # number of demand (read+write) MSHR misses
1348system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses
1349system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1350system.cpu.l2cache.overall_mshr_misses::cpu.inst 19922 # number of overall MSHR misses
1351system.cpu.l2cache.overall_mshr_misses::cpu.data 154658 # number of overall MSHR misses
1352system.cpu.l2cache.overall_mshr_misses::total 174608 # number of overall MSHR misses
1353system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable
1354system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
1355system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable
1356system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
1357system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
1358system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses
1359system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
1360system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61716 # number of overall MSHR uncacheable misses
1361system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1634500 # number of ReadReq MSHR miss cycles
1362system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 509500 # number of ReadReq MSHR miss cycles
1363system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2144000 # number of ReadReq MSHR miss cycles
1364system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 56503000 # number of UpgradeReq MSHR miss cycles
1365system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 56503000 # number of UpgradeReq MSHR miss cycles
1366system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 145000 # number of SCUpgradeReq MSHR miss cycles
1367system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 145000 # number of SCUpgradeReq MSHR miss cycles
1368system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9782865500 # number of ReadExReq MSHR miss cycles
1369system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9782865500 # number of ReadExReq MSHR miss cycles
1370system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1422648500 # number of ReadCleanReq MSHR miss cycles
1371system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1422648500 # number of ReadCleanReq MSHR miss cycles
1372system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1076334500 # number of ReadSharedReq MSHR miss cycles
1373system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1076334500 # number of ReadSharedReq MSHR miss cycles
1374system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1634500 # number of demand (read+write) MSHR miss cycles
1375system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 509500 # number of demand (read+write) MSHR miss cycles
1376system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1422648500 # number of demand (read+write) MSHR miss cycles
1377system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10859200000 # number of demand (read+write) MSHR miss cycles
1378system.cpu.l2cache.demand_mshr_miss_latency::total 12283992500 # number of demand (read+write) MSHR miss cycles
1379system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1634500 # number of overall MSHR miss cycles
1380system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 509500 # number of overall MSHR miss cycles
1381system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1422648500 # number of overall MSHR miss cycles
1382system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10859200000 # number of overall MSHR miss cycles
1383system.cpu.l2cache.overall_mshr_miss_latency::total 12283992500 # number of overall MSHR miss cycles
1384system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 188213500 # number of ReadReq MSHR uncacheable cycles
1385system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5519024000 # number of ReadReq MSHR uncacheable cycles
1386system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5707237500 # number of ReadReq MSHR uncacheable cycles
1387system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4252080000 # number of WriteReq MSHR uncacheable cycles
1388system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4252080000 # number of WriteReq MSHR uncacheable cycles
1389system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 188213500 # number of overall MSHR uncacheable cycles
1390system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771104000 # number of overall MSHR uncacheable cycles
1391system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9959317500 # number of overall MSHR uncacheable cycles
1392system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
1393system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for ReadReq accesses
1394system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000408 # mshr miss rate for ReadReq accesses
1395system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986942 # mshr miss rate for UpgradeReq accesses
1396system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986942 # mshr miss rate for UpgradeReq accesses
1397system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
1398system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
1399system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471836 # mshr miss rate for ReadExReq accesses
1400system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471836 # mshr miss rate for ReadExReq accesses
1401system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for ReadCleanReq accesses
1402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadCleanReq accesses
1403system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026255 # mshr miss rate for ReadSharedReq accesses
1404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026255 # mshr miss rate for ReadSharedReq accesses
1405system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses
1406system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for demand accesses
1407system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for demand accesses
1408system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for demand accesses
1409system.cpu.l2cache.demand_mshr_miss_rate::total 0.062341 # mshr miss rate for demand accesses
1410system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses
1411system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for overall accesses
1412system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for overall accesses
1413system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for overall accesses
1414system.cpu.l2cache.overall_mshr_miss_rate::total 0.062341 # mshr miss rate for overall accesses
1415system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average ReadReq mshr miss latency
1416system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average ReadReq mshr miss latency
1417system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76571.428571 # average ReadReq mshr miss latency
1418system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20765.527380 # average UpgradeReq mshr miss latency
1419system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20765.527380 # average UpgradeReq mshr miss latency
1420system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72500 # average SCUpgradeReq mshr miss latency
1421system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72500 # average SCUpgradeReq mshr miss latency
1422system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69667.116498 # average ReadExReq mshr miss latency
1423system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69667.116498 # average ReadExReq mshr miss latency
1424system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71410.927618 # average ReadCleanReq mshr miss latency
1425system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71410.927618 # average ReadCleanReq mshr miss latency
1426system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75611.837021 # average ReadSharedReq mshr miss latency
1427system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75611.837021 # average ReadSharedReq mshr miss latency
1428system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency
1429system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency
1430system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency
1431system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency
1432system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency
1433system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency
1434system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency
1435system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency
1436system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency
1437system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency
1438system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average ReadReq mshr uncacheable latency
1439system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177306.646962 # average ReadReq mshr uncacheable latency
1440system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 167210.755303 # average ReadReq mshr uncacheable latency
1441system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154150.232019 # average WriteReq mshr uncacheable latency
1442system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154150.232019 # average WriteReq mshr uncacheable latency
1443system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average overall mshr uncacheable latency
1444system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166427.143125 # average overall mshr uncacheable latency
1445system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161373.347268 # average overall mshr uncacheable latency
1446system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1447system.cpu.toL2Bus.trans_dist::ReadReq 128192 # Transaction distribution
1448system.cpu.toL2Bus.trans_dist::ReadResp 2563081 # Transaction distribution
1449system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
1450system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
1451system.cpu.toL2Bus.trans_dist::Writeback 827115 # Transaction distribution
1452system.cpu.toL2Bus.trans_dist::CleanEvict 1997055 # Transaction distribution
1453system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution
1454system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
1455system.cpu.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution
1456system.cpu.toL2Bus.trans_dist::ReadExReq 297610 # Transaction distribution
1457system.cpu.toL2Bus.trans_dist::ReadExResp 297610 # Transaction distribution
1458system.cpu.toL2Bus.trans_dist::ReadCleanReq 1892487 # Transaction distribution
1459system.cpu.toL2Bus.trans_dist::ReadSharedReq 542422 # Transaction distribution
1460system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1461system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5643819 # Packet count per connected master and slave (bytes)
1462system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2634611 # Packet count per connected master and slave (bytes)
1463system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32016 # Packet count per connected master and slave (bytes)
1464system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130644 # Packet count per connected master and slave (bytes)
1465system.cpu.toL2Bus.pkt_count::total 8441090 # Packet count per connected master and slave (bytes)
1466system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121164944 # Cumulative packet size per connected master and slave (bytes)
1467system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98490717 # Cumulative packet size per connected master and slave (bytes)
1468system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50224 # Cumulative packet size per connected master and slave (bytes)
1469system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224176 # Cumulative packet size per connected master and slave (bytes)
1470system.cpu.toL2Bus.pkt_size::total 219930061 # Cumulative packet size per connected master and slave (bytes)
1471system.cpu.toL2Bus.snoops 201613 # Total snoops (count)
1472system.cpu.toL2Bus.snoop_fanout::samples 5797948 # Request fanout histogram
1473system.cpu.toL2Bus.snoop_fanout::mean 1.046562 # Request fanout histogram
1474system.cpu.toL2Bus.snoop_fanout::stdev 0.210699 # Request fanout histogram
1475system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1476system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1477system.cpu.toL2Bus.snoop_fanout::1 5527984 95.34% 95.34% # Request fanout histogram
1478system.cpu.toL2Bus.snoop_fanout::2 269964 4.66% 100.00% # Request fanout histogram
1479system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1480system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1481system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1482system.cpu.toL2Bus.snoop_fanout::total 5797948 # Request fanout histogram
1483system.cpu.toL2Bus.reqLayer0.occupancy 3520857499 # Layer occupancy (ticks)
1484system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1485system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
1486system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1487system.cpu.toL2Bus.respLayer0.occupancy 2842352755 # Layer occupancy (ticks)
1488system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1489system.cpu.toL2Bus.respLayer1.occupancy 1306164667 # Layer occupancy (ticks)
1490system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1491system.cpu.toL2Bus.respLayer2.occupancy 19466986 # Layer occupancy (ticks)
1492system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1493system.cpu.toL2Bus.respLayer3.occupancy 74632435 # Layer occupancy (ticks)
1494system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1495system.iobus.trans_dist::ReadReq 30182 # Transaction distribution
1496system.iobus.trans_dist::ReadResp 30182 # Transaction distribution
1497system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1498system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1499system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1500system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1501system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1502system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1503system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1504system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)

--- 8 unchanged lines hidden (view full) ---

1513system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1514system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1515system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1516system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1517system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1518system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1519system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1520system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1521system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes)
1522system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes)
1523system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes)
1524system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1525system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1526system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1527system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1528system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1529system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1530system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1531system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)

--- 6 unchanged lines hidden (view full) ---

1538system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1539system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1540system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1541system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
1542system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1543system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
1544system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1545system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1546system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes)
1547system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes)
1548system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes)
1549system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
1550system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1551system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
1552system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1553system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
1554system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1555system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
1556system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)

--- 24 unchanged lines hidden (view full) ---

1581system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
1582system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1583system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
1584system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1585system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
1586system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1587system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
1588system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1589system.iobus.reqLayer27.occupancy 187477456 # Layer occupancy (ticks)
1590system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1591system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1592system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1593system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1594system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1595system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks)
1596system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1597system.iocache.tags.replacements 36423 # number of replacements
1598system.iocache.tags.tagsinuse 1.000222 # Cycle average of tags in use
1599system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1600system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
1601system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1602system.iocache.tags.warmup_cycle 252500924000 # Cycle when the warmup percentage was hit.
1603system.iocache.tags.occ_blocks::realview.ide 1.000222 # Average occupied blocks per requestor
1604system.iocache.tags.occ_percent::realview.ide 0.062514 # Average percentage of cache occupancy
1605system.iocache.tags.occ_percent::total 0.062514 # Average percentage of cache occupancy
1606system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1607system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1608system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1609system.iocache.tags.tag_accesses 328113 # Number of tag accesses
1610system.iocache.tags.data_accesses 328113 # Number of data accesses
1611system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses
1612system.iocache.ReadReq_misses::total 233 # number of ReadReq misses
1613system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1614system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1615system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses
1616system.iocache.demand_misses::total 233 # number of demand (read+write) misses
1617system.iocache.overall_misses::realview.ide 233 # number of overall misses
1618system.iocache.overall_misses::total 233 # number of overall misses
1619system.iocache.ReadReq_miss_latency::realview.ide 28674877 # number of ReadReq miss cycles
1620system.iocache.ReadReq_miss_latency::total 28674877 # number of ReadReq miss cycles
1621system.iocache.WriteLineReq_miss_latency::realview.ide 4272498579 # number of WriteLineReq miss cycles
1622system.iocache.WriteLineReq_miss_latency::total 4272498579 # number of WriteLineReq miss cycles
1623system.iocache.demand_miss_latency::realview.ide 28674877 # number of demand (read+write) miss cycles
1624system.iocache.demand_miss_latency::total 28674877 # number of demand (read+write) miss cycles
1625system.iocache.overall_miss_latency::realview.ide 28674877 # number of overall miss cycles
1626system.iocache.overall_miss_latency::total 28674877 # number of overall miss cycles
1627system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses)
1628system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses)
1629system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1630system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1631system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses
1632system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses
1633system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses
1634system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses
1635system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1636system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1637system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1638system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1639system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1640system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1641system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1642system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1643system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631 # average ReadReq miss latency
1644system.iocache.ReadReq_avg_miss_latency::total 123068.141631 # average ReadReq miss latency
1645system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966 # average WriteLineReq miss latency
1646system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966 # average WriteLineReq miss latency
1647system.iocache.demand_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency
1648system.iocache.demand_avg_miss_latency::total 123068.141631 # average overall miss latency
1649system.iocache.overall_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency
1650system.iocache.overall_avg_miss_latency::total 123068.141631 # average overall miss latency
1651system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1652system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1653system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1654system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1655system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1656system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1657system.iocache.fast_writes 0 # number of fast writes performed
1658system.iocache.cache_copies 0 # number of cache copies performed
1659system.iocache.writebacks::writebacks 36190 # number of writebacks
1660system.iocache.writebacks::total 36190 # number of writebacks
1661system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses
1662system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses
1663system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1664system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1665system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses
1666system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses
1667system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses
1668system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses
1669system.iocache.ReadReq_mshr_miss_latency::realview.ide 17024877 # number of ReadReq MSHR miss cycles
1670system.iocache.ReadReq_mshr_miss_latency::total 17024877 # number of ReadReq MSHR miss cycles
1671system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2461298579 # number of WriteLineReq MSHR miss cycles
1672system.iocache.WriteLineReq_mshr_miss_latency::total 2461298579 # number of WriteLineReq MSHR miss cycles
1673system.iocache.demand_mshr_miss_latency::realview.ide 17024877 # number of demand (read+write) MSHR miss cycles
1674system.iocache.demand_mshr_miss_latency::total 17024877 # number of demand (read+write) MSHR miss cycles
1675system.iocache.overall_mshr_miss_latency::realview.ide 17024877 # number of overall MSHR miss cycles
1676system.iocache.overall_mshr_miss_latency::total 17024877 # number of overall MSHR miss cycles
1677system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1678system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1679system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1680system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1681system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1682system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1683system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1684system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1685system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631 # average ReadReq mshr miss latency
1686system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631 # average ReadReq mshr miss latency
1687system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966 # average WriteLineReq mshr miss latency
1688system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966 # average WriteLineReq mshr miss latency
1689system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency
1690system.iocache.demand_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency
1691system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency
1692system.iocache.overall_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency
1693system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1694system.membus.trans_dist::ReadReq 34132 # Transaction distribution
1695system.membus.trans_dist::ReadResp 68549 # Transaction distribution
1696system.membus.trans_dist::WriteReq 27584 # Transaction distribution
1697system.membus.trans_dist::WriteResp 27584 # Transaction distribution
1698system.membus.trans_dist::Writeback 131071 # Transaction distribution
1699system.membus.trans_dist::CleanEvict 8154 # Transaction distribution
1700system.membus.trans_dist::UpgradeReq 4580 # Transaction distribution
1701system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1702system.membus.trans_dist::UpgradeResp 4582 # Transaction distribution
1703system.membus.trans_dist::ReadExReq 138564 # Transaction distribution
1704system.membus.trans_dist::ReadExResp 138564 # Transaction distribution
1705system.membus.trans_dist::ReadSharedReq 34418 # Transaction distribution
1706system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
1707system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
1708system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1709system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
1710system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
1711system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473273 # Packet count per connected master and slave (bytes)
1712system.membus.pkt_count_system.cpu.l2cache.mem_side::total 580837 # Packet count per connected master and slave (bytes)
1713system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108898 # Packet count per connected master and slave (bytes)
1714system.membus.pkt_count_system.iocache.mem_side::total 108898 # Packet count per connected master and slave (bytes)
1715system.membus.pkt_count::total 689735 # Packet count per connected master and slave (bytes)
1716system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1717system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
1718system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
1719system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17178284 # Cumulative packet size per connected master and slave (bytes)
1720system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17341677 # Cumulative packet size per connected master and slave (bytes)
1721system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1722system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
1723system.membus.pkt_size::total 19658797 # Cumulative packet size per connected master and slave (bytes)
1724system.membus.snoops 497 # Total snoops (count)
1725system.membus.snoop_fanout::samples 414951 # Request fanout histogram
1726system.membus.snoop_fanout::mean 1 # Request fanout histogram
1727system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1728system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1729system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1730system.membus.snoop_fanout::1 414951 100.00% 100.00% # Request fanout histogram
1731system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1732system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1733system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1734system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1735system.membus.snoop_fanout::total 414951 # Request fanout histogram
1736system.membus.reqLayer0.occupancy 83605000 # Layer occupancy (ticks)
1737system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1738system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
1739system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1740system.membus.reqLayer2.occupancy 1746000 # Layer occupancy (ticks)
1741system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1742system.membus.reqLayer5.occupancy 911806448 # Layer occupancy (ticks)
1743system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1744system.membus.respLayer2.occupancy 1019741659 # Layer occupancy (ticks)
1745system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1746system.membus.respLayer3.occupancy 64533936 # Layer occupancy (ticks)
1747system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1748system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1749system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1750system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1751system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1752system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1753system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1754system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

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1771system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1772system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1773system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1774system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1775system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1776system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1777system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1778system.realview.ethernet.droppedPackets 0 # number of packets dropped
1779system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
1780system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
1781system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
1782system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
1783system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
1784system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
1785system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
1786system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
1787system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
1788system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
1789system.cpu.kern.inst.arm 0 # number of arm instructions executed
1790system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
1791
1792---------- End Simulation Statistics ----------