1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.542157 # Number of seconds simulated
4sim_ticks 2542156879500 # Number of ticks simulated
5final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 53387 # Simulator instruction rate (inst/s)
8host_op_rate 64319 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2250271387 # Simulator tick rate (ticks/s)
10host_mem_usage 465820 # Number of bytes of host memory used
11host_seconds 1129.71 # Real time elapsed on the host
12sim_insts 60311972 # Number of instructions simulated
13sim_ops 72661518 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory
21system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
26system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory
27system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory
36system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 15295608 # Number of read requests accepted
55system.physmem.writeReqs 812506 # Number of write requests accepted
56system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue
60system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 955787 # Per bank write bursts
67system.physmem.perBankRdBursts::1 955478 # Per bank write bursts
68system.physmem.perBankRdBursts::2 953511 # Per bank write bursts
69system.physmem.perBankRdBursts::3 951566 # Per bank write bursts
70system.physmem.perBankRdBursts::4 958612 # Per bank write bursts
71system.physmem.perBankRdBursts::5 955530 # Per bank write bursts
72system.physmem.perBankRdBursts::6 953056 # Per bank write bursts
73system.physmem.perBankRdBursts::7 951020 # Per bank write bursts
74system.physmem.perBankRdBursts::8 956158 # Per bank write bursts
75system.physmem.perBankRdBursts::9 955874 # Per bank write bursts
76system.physmem.perBankRdBursts::10 952686 # Per bank write bursts
77system.physmem.perBankRdBursts::11 950200 # Per bank write bursts
78system.physmem.perBankRdBursts::12 956166 # Per bank write bursts
79system.physmem.perBankRdBursts::13 955918 # Per bank write bursts
80system.physmem.perBankRdBursts::14 953812 # Per bank write bursts
81system.physmem.perBankRdBursts::15 951254 # Per bank write bursts
82system.physmem.perBankWrBursts::0 6556 # Per bank write bursts
83system.physmem.perBankWrBursts::1 6344 # Per bank write bursts
84system.physmem.perBankWrBursts::2 6481 # Per bank write bursts
85system.physmem.perBankWrBursts::3 6512 # Per bank write bursts
86system.physmem.perBankWrBursts::4 6422 # Per bank write bursts
87system.physmem.perBankWrBursts::5 6709 # Per bank write bursts
88system.physmem.perBankWrBursts::6 6691 # Per bank write bursts
89system.physmem.perBankWrBursts::7 6631 # Per bank write bursts
90system.physmem.perBankWrBursts::8 6968 # Per bank write bursts
91system.physmem.perBankWrBursts::9 6764 # Per bank write bursts
92system.physmem.perBankWrBursts::10 6424 # Per bank write bursts
93system.physmem.perBankWrBursts::11 6068 # Per bank write bursts
94system.physmem.perBankWrBursts::12 7033 # Per bank write bursts
95system.physmem.perBankWrBursts::13 6638 # Per bank write bursts
96system.physmem.perBankWrBursts::14 6915 # Per bank write bursts
97system.physmem.perBankWrBursts::15 6799 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
100system.physmem.totGap 2542155562500 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 18 # Read request sizes (log2)
104system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
105system.physmem.readPktSize::4 3351 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 153413 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 754018 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 58488 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
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154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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201system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes
233system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads
251system.physmem.totQLat 395458190750 # Total ticks spent queuing
252system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM
253system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers
254system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst
255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
256system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst
257system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s
258system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s
259system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s
260system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s
261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
262system.physmem.busUtil 3.02 # Data bus utilization in percentage
263system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
264system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
265system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing
266system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing
267system.physmem.readRowHits 14271218 # Number of row buffer hits during reads
268system.physmem.writeRowHits 90719 # Number of row buffer hits during writes
269system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
270system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes
271system.physmem.avgGap 157818.32 # Average gap between requests
272system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
273system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states
274system.physmem.memoryStateTime::REF 84888180000 # Time in different power states
275system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
276system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states
277system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
278system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ)
279system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ)
280system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ)
281system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ)
282system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ)
283system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ)
284system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ)
285system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ)
286system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ)
287system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ)
288system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ)
289system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ)
290system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ)
291system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ)
292system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ)
293system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ)
294system.physmem.averagePower::0 698.235540 # Core power per rank (mW)
295system.physmem.averagePower::1 698.237375 # Core power per rank (mW)
296system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory
297system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory
298system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory
299system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory
300system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory
301system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory
302system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s)
303system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s)
304system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s)
305system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s)
306system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s)
307system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s)
308system.membus.trans_dist::ReadReq 16348037 # Transaction distribution
309system.membus.trans_dist::ReadResp 16348037 # Transaction distribution
310system.membus.trans_dist::WriteReq 763357 # Transaction distribution
311system.membus.trans_dist::WriteResp 763357 # Transaction distribution
312system.membus.trans_dist::Writeback 58488 # Transaction distribution
313system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution
314system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution
315system.membus.trans_dist::ReadExReq 131654 # Transaction distribution
316system.membus.trans_dist::ReadExResp 131654 # Transaction distribution
317system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes)
318system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes)
319system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
320system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
321system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes)
322system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes)
323system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
324system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
325system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes)
326system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
327system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
328system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
329system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
330system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes)
331system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes)
332system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
333system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
334system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes)
335system.membus.snoops 0 # Total snoops (count)
336system.membus.snoop_fanout::samples 216513 # Request fanout histogram
337system.membus.snoop_fanout::mean 1 # Request fanout histogram
338system.membus.snoop_fanout::stdev 0 # Request fanout histogram
339system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
340system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
341system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram
342system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
343system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
344system.membus.snoop_fanout::min_value 1 # Request fanout histogram
345system.membus.snoop_fanout::max_value 1 # Request fanout histogram
346system.membus.snoop_fanout::total 216513 # Request fanout histogram
347system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks)
348system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
349system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks)
350system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
351system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks)
352system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
353system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
354system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
355system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks)
356system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
357system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks)
358system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
359system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks)
360system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
361system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
362system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
363system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
364system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
365system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
366system.cf0.dma_write_txs 0 # Number of DMA write transactions.
367system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution
368system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution
369system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
370system.iobus.trans_dist::WriteResp 8176 # Transaction distribution
371system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
372system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
373system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes)
374system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes)
375system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
376system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
377system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
378system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
379system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
380system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
381system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
382system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
383system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
384system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
385system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
386system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
387system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
388system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
389system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
390system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
391system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
392system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
393system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
394system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes)
395system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
396system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
397system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes)
398system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
399system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
400system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
401system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
402system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
403system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
404system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
405system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
406system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
407system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
408system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
409system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
410system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
411system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
412system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
413system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
414system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
415system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
416system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
417system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
418system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
419system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
420system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
421system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
422system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
423system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
424system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
425system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
426system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
427system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
428system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
429system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks)
430system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
431system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks)
432system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
433system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
434system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
435system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
436system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
437system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
438system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
439system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
440system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
441system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
442system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
443system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
444system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
445system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
446system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
447system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
448system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
449system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
450system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
451system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
452system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
453system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
454system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
455system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
456system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
457system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
458system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
459system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
460system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
461system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
462system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
463system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
464system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
465system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
466system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
467system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
468system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
469system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
470system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
471system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
472system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
473system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks)
474system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
475system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks)
476system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
477system.cpu_clk_domain.clock 500 # Clock period in ticks
478system.cpu.branchPred.lookups 13200672 # Number of BP lookups
479system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted
480system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect
481system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups
482system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits
483system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
484system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage
485system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target.
486system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions.
487system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
488system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
489system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
490system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
491system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
492system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
493system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
494system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

502system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
503system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
504system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
505system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
506system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
507system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
508system.cpu.dtb.inst_hits 0 # ITB inst hits
509system.cpu.dtb.inst_misses 0 # ITB inst misses
510system.cpu.dtb.read_hits 31644036 # DTB read hits
511system.cpu.dtb.read_misses 39518 # DTB read misses
512system.cpu.dtb.write_hits 11381434 # DTB write hits
513system.cpu.dtb.write_misses 10146 # DTB write misses
514system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
515system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
516system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
517system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
518system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB
519system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
520system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
521system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
522system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions
523system.cpu.dtb.read_accesses 31683554 # DTB read accesses
524system.cpu.dtb.write_accesses 11391580 # DTB write accesses
525system.cpu.dtb.inst_accesses 0 # ITB inst accesses
526system.cpu.dtb.hits 43025470 # DTB hits
527system.cpu.dtb.misses 49664 # DTB misses
528system.cpu.dtb.accesses 43075134 # DTB accesses
529system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
530system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
531system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
532system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
533system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
534system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
535system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
536system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

542system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
543system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
544system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
545system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
546system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
547system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
548system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
549system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
550system.cpu.itb.inst_hits 24158829 # ITB inst hits
551system.cpu.itb.inst_misses 10513 # ITB inst misses
552system.cpu.itb.read_hits 0 # DTB read hits
553system.cpu.itb.read_misses 0 # DTB read misses
554system.cpu.itb.write_hits 0 # DTB write hits
555system.cpu.itb.write_misses 0 # DTB write misses
556system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
557system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
558system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
559system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
560system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB
561system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
562system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
563system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
564system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions
565system.cpu.itb.read_accesses 0 # DTB read accesses
566system.cpu.itb.write_accesses 0 # DTB write accesses
567system.cpu.itb.inst_accesses 24169342 # ITB inst accesses
568system.cpu.itb.hits 24158829 # DTB hits
569system.cpu.itb.misses 10513 # DTB misses
570system.cpu.itb.accesses 24169342 # DTB accesses
571system.cpu.numCycles 499362415 # number of cpu cycles simulated
572system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
573system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
574system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss
575system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed
576system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered
577system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken
578system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked
579system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing
580system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb
581system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
582system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps
583system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions
584system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
585system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched
586system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed
587system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed
588system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total)
589system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total)
590system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total)
591system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
592system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total)
593system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total)
594system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total)
595system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total)
596system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
597system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
598system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
599system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total)
600system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle
601system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle
602system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle
603system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked
604system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running
605system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking
606system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing
607system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch
608system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction
609system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode
610system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode
611system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing
612system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle
613system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking
614system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst
615system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running
616system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking
617system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename
618system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename
619system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full
620system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full
621system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full
622system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full
623system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed
624system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made
625system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups
626system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups
627system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed
628system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing
629system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed
630system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed
631system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer
632system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit.
633system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit.
634system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads.
635system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores.
636system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec)
637system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ
638system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued
639system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued
640system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling
641system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph
642system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed
643system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle
644system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle
645system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle
646system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
647system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle
648system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle
649system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle
650system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle
651system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle
652system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle
653system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
654system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
655system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
656system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
657system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
658system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
659system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle
660system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
661system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available
662system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available
663system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available
664system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available
665system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available
666system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available
667system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available
668system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available
669system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
670system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available
671system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available
672system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available
673system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available
674system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available
675system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available
676system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available
677system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available
678system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available
679system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available
680system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available
681system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available
682system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available
683system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available
684system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available
685system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available
686system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available
687system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available
688system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available
689system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
690system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available
691system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available
692system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
693system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
694system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued
695system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued
696system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued
697system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued
698system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued
699system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued
700system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued
701system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued
702system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued
703system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued
704system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued
705system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued
706system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued
707system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued
708system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued
709system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued
710system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued
711system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued
712system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued
713system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued
714system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued
715system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued
716system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued
717system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued
718system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued
719system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued
720system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued
721system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued
722system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued
723system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued
724system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued
725system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued
726system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
727system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
728system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued
729system.cpu.iq.rate 0.188049 # Inst issue rate
730system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested
731system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst)
732system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads
733system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes
734system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses
735system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads
736system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes
737system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses
738system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses
739system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses
740system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores
741system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
742system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed
743system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed
744system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations
745system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed
746system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
747system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
748system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled
749system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked
750system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
751system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing
752system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking
753system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking
754system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ
755system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
756system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions
757system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions
758system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions
759system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall
760system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall
761system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations
762system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly
763system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly
764system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute
765system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions
766system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed
767system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute
768system.cpu.iew.exec_swp 0 # number of swp insts executed
769system.cpu.iew.exec_nop 176011 # number of nop insts executed
770system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed
771system.cpu.iew.exec_branches 10791373 # Number of branches executed
772system.cpu.iew.exec_stores 11888962 # Number of stores executed
773system.cpu.iew.exec_rate 0.186737 # Inst execution rate
774system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit
775system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back
776system.cpu.iew.wb_producers 35461894 # num instructions producing a value
777system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value
778system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
779system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle
780system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back
781system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
782system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit
783system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards
784system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted
785system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle
786system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle
787system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle
788system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
789system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle
790system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle
791system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle
792system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle
793system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle
794system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle
795system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle
796system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle
797system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle
798system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
799system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
800system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
801system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle
802system.cpu.commit.committedInsts 60462353 # Number of instructions committed
803system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed
804system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
805system.cpu.commit.refs 25244590 # Number of memory references committed
806system.cpu.commit.loads 13512938 # Number of loads committed
807system.cpu.commit.membars 403660 # Number of memory barriers committed
808system.cpu.commit.branches 10308077 # Number of branches committed
809system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
810system.cpu.commit.int_insts 64250158 # Number of committed integer instructions.
811system.cpu.commit.function_calls 991634 # Number of function calls committed.
812system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
813system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction
814system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction
815system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction
816system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction
817system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction
818system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction
819system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction
820system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction
821system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction
822system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction
823system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction
824system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction
825system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction
826system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction
827system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction
828system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction
829system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction
830system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction
831system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction
832system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction
833system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction
834system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction
835system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction
836system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction
837system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction
838system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction
839system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction
840system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction
841system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction
842system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction
843system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction
844system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
845system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
846system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction
847system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached
848system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
849system.cpu.rob.rob_reads 568215140 # The number of ROB reads
850system.cpu.rob.rob_writes 154414029 # The number of ROB writes
851system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself
852system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling
853system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
854system.cpu.committedInsts 60311972 # Number of Instructions Simulated
855system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated
856system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction
857system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads
858system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle
859system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads
860system.cpu.int_regfile_reads 109116744 # number of integer regfile reads
861system.cpu.int_regfile_writes 47012206 # number of integer regfile writes
862system.cpu.fp_regfile_reads 8305 # number of floating regfile reads
863system.cpu.fp_regfile_writes 2780 # number of floating regfile writes
864system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads
865system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes
866system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads
867system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes
868system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution
869system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution
870system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
871system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
872system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution
873system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
874system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
875system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution
876system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution
877system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution
878system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes)
879system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes)
880system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes)
881system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes)
882system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes)
883system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes)
884system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes)
885system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes)
886system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes)
887system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes)
888system.cpu.toL2Bus.snoops 26770 # Total snoops (count)
889system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram
890system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
891system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
892system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
893system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
894system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
895system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
896system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
897system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
898system.cpu.toL2Bus.snoop_fanout::5 2266210 100.00% 100.00% # Request fanout histogram
899system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
900system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
901system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
902system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
903system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram
904system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks)
905system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
906system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks)
907system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
908system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks)
909system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
910system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks)
911system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
912system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks)
913system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
914system.cpu.icache.tags.replacements 959838 # number of replacements
915system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use
916system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks.
917system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks.
918system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks.
919system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit.
920system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor
921system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy
922system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy
923system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
924system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
925system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
926system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
927system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
928system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
929system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses
930system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses
931system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits
932system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits
933system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits
934system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits
935system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits
936system.cpu.icache.overall_hits::total 23148830 # number of overall hits
937system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses
938system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses
939system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses
940system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses
941system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses
942system.cpu.icache.overall_misses::total 1005344 # number of overall misses
943system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles
944system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles
945system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles
946system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles
947system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles
948system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles
949system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses)
950system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses)
951system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses
952system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses
953system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses
954system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses
955system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses
956system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses
957system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses
958system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses
959system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses
960system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses
961system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency
962system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency
963system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency
964system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency
965system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency
966system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency
967system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked
968system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
969system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked
970system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
971system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked
972system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
973system.cpu.icache.fast_writes 0 # number of fast writes performed
974system.cpu.icache.cache_copies 0 # number of cache copies performed
975system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits
976system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits
977system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits
978system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits
979system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits
980system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits
981system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses
982system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses
983system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses
984system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses
985system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses
986system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses
987system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles
988system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles
989system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles
990system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles
991system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles
992system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles
993system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles
994system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles
995system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles
996system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles
997system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses
998system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses
999system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses
1000system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses
1001system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses
1002system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses
1003system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency
1004system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency
1005system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency
1006system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency
1007system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency
1008system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency
1009system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1010system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1011system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1012system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1013system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1014system.cpu.l2cache.tags.replacements 63303 # number of replacements
1015system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use
1016system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks.
1017system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks.
1018system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks.
1019system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit.
1020system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor
1021system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor
1022system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor
1023system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor
1024system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor
1025system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy
1026system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy
1027system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
1028system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy
1029system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy
1030system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy
1031system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
1032system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id
1033system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
1034system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
1035system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id
1036system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id
1037system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id
1038system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id
1039system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
1040system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id
1041system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses
1042system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses
1043system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits
1044system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits
1045system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits
1046system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits
1047system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits
1048system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits
1049system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits
1050system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits
1051system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits
1052system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
1053system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
1054system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits
1055system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits
1056system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits
1057system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits
1058system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits
1059system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits
1060system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits
1061system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits
1062system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits
1063system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits
1064system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits
1065system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits
1066system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses
1067system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
1068system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses
1069system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses
1070system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses
1071system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses
1072system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses
1073system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses
1074system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses
1075system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses
1076system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
1077system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses
1078system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses
1079system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses
1080system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses
1081system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
1082system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses
1083system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses
1084system.cpu.l2cache.overall_misses::total 155171 # number of overall misses
1085system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles
1086system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles
1087system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles
1088system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles
1089system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles
1090system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles
1091system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles
1092system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles
1093system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles
1094system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles
1095system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles
1096system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles
1097system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles
1098system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles
1099system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles
1100system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles
1101system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles
1102system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles
1103system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles
1104system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses)
1105system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses)
1106system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses)
1107system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses)
1108system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses)
1109system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses)
1110system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses)
1111system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses)
1112system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses)
1113system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
1114system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
1115system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses)
1116system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses)
1117system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses
1118system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses
1119system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses
1120system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses
1121system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses
1122system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses
1123system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses
1124system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses
1125system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses
1126system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses
1127system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses
1128system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses
1129system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses
1130system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
1131system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses
1132system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses
1133system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses
1134system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses
1135system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses
1136system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses
1137system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses
1138system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses
1139system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses
1140system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses
1141system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses
1142system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses
1143system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses
1144system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses
1145system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses
1146system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency
1147system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency
1148system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency
1149system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency
1150system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency
1151system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency
1152system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency
1153system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency
1154system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency
1155system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency
1156system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency
1157system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency
1158system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency
1159system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency
1160system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency
1161system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency
1162system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency
1163system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency
1164system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency
1165system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1166system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1167system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1168system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1169system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1170system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1171system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1172system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1173system.cpu.l2cache.writebacks::writebacks 58488 # number of writebacks
1174system.cpu.l2cache.writebacks::total 58488 # number of writebacks
1175system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
1176system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
1177system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
1178system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
1179system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
1180system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
1181system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits
1182system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
1183system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
1184system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
1185system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
1186system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits
1187system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses
1188system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
1189system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses
1190system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses
1191system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses
1192system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses
1193system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses
1194system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses
1195system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses
1196system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses
1197system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
1198system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses
1199system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses
1200system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses
1201system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses
1202system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
1203system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses
1204system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses
1205system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses
1206system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles
1207system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles
1208system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles
1209system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles
1210system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles
1211system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles
1212system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles
1213system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles
1214system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles
1215system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles
1216system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles
1217system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles
1218system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles
1219system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles
1220system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles
1221system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles
1222system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles
1223system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles
1224system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles
1225system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles
1226system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles
1227system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles
1228system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles
1229system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles
1230system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles
1231system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles
1232system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles
1233system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses
1234system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses
1235system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses
1236system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses
1237system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses
1238system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses
1239system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses
1240system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses
1241system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses
1242system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses
1243system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses
1244system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses
1245system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses
1246system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses
1247system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses
1248system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses
1249system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses
1250system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses
1251system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses
1252system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency
1253system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency
1254system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency
1255system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency
1256system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency
1257system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency
1258system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency
1259system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency
1260system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency
1261system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency
1262system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency
1263system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency
1264system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency
1265system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency
1266system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency
1267system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency
1268system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency
1269system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency
1270system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency
1271system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1272system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1273system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1274system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1275system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1276system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1277system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1278system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1279system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1280system.cpu.dcache.tags.replacements 633278 # number of replacements
1281system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use
1282system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks.
1283system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks.
1284system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks.
1285system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit.
1286system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor
1287system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy
1288system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy
1289system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1290system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
1291system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
1292system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
1293system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1294system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses
1295system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses
1296system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits
1297system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits
1298system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits
1299system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits
1300system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits
1301system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits
1302system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits
1303system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits
1304system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits
1305system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits
1306system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits
1307system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits
1308system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits
1309system.cpu.dcache.overall_hits::total 18581554 # number of overall hits
1310system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses
1311system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses
1312system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses
1313system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses
1314system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses
1315system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses
1316system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses
1317system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses
1318system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
1319system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
1320system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses
1321system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses
1322system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses
1323system.cpu.dcache.overall_misses::total 3712231 # number of overall misses
1324system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles
1325system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles
1326system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles
1327system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles
1328system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles
1329system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles
1330system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles
1331system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
1332system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles
1333system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles
1334system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles
1335system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles
1336system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses)
1337system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses)
1338system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses)
1339system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses)
1340system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses)
1341system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses)
1342system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses)
1343system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses)
1344system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses)
1345system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses)
1346system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses
1347system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses
1348system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses
1349system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses
1350system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses
1351system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses
1352system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses
1353system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses
1354system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses
1355system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses
1356system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses
1357system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses
1358system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses
1359system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses
1360system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses
1361system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses
1362system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses
1363system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses
1364system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency
1365system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency
1366system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency
1367system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency
1368system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency
1369system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency
1370system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
1371system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
1372system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency
1373system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency
1374system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency
1375system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency
1376system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked
1377system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked
1378system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked
1379system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
1380system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked
1381system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked
1382system.cpu.dcache.fast_writes 0 # number of fast writes performed
1383system.cpu.dcache.cache_copies 0 # number of cache copies performed
1384system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks
1385system.cpu.dcache.writebacks::total 599947 # number of writebacks
1386system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits
1387system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits
1388system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits
1389system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits
1390system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits
1391system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits
1392system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits
1393system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits
1394system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits
1395system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits
1396system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses
1397system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses
1398system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses
1399system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses
1400system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses
1401system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses
1402system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses
1403system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses
1404system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
1405system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
1406system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses
1407system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses
1408system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses
1409system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses
1410system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles
1411system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles
1412system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles
1413system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles
1414system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles
1415system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles
1416system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles
1417system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles
1418system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
1419system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
1420system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles
1421system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles
1422system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles
1423system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles
1424system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles
1425system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles
1426system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles
1427system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles
1428system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles
1429system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles
1430system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses
1431system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses
1432system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses
1433system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses
1434system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses
1435system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses
1436system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses
1437system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses
1438system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses
1439system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
1440system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses
1441system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses
1442system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses
1443system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses
1444system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency
1445system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency
1446system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency
1447system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency
1448system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency
1449system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency
1450system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency
1451system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency
1452system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
1453system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
1454system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency
1455system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency
1456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency
1457system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency
1458system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1459system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1460system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1461system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1462system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1463system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1464system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1465system.iocache.tags.replacements 0 # number of replacements
1466system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
1467system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1468system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
1469system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
1470system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1471system.iocache.tags.tag_accesses 0 # Number of tag accesses
1472system.iocache.tags.data_accesses 0 # Number of data accesses
1473system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1474system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1475system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1476system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1477system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1478system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1479system.iocache.fast_writes 0 # number of fast writes performed
1480system.iocache.cache_copies 0 # number of cache copies performed
1481system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles
1482system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles
1483system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles
1484system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles
1485system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1486system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1487system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1488system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1489system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1490system.cpu.kern.inst.arm 0 # number of arm instructions executed
1491system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed
1492
1493---------- End Simulation Statistics ----------