| config.ini (9924:31ef410b6843) | config.ini (9988:0b2e590c85be) |
|---|---|
| 1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
| 4eventq_index=0 |
|
| 4full_system=true | 5full_system=true |
| 6sim_quantum=0 |
|
| 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain 12atags_addr=256 | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain 14atags_addr=256 |
| 13boot_loader=/dist/m5/system/binaries/boot.arm | 15boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm |
| 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15cache_line_size=64 16clk_domain=system.clk_domain | 16boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 17cache_line_size=64 18clk_domain=system.clk_domain |
| 17dtb_filename=False | 19dtb_filename= |
| 18early_kernel_symbols=false 19enable_context_switch_stats_dump=false | 20early_kernel_symbols=false 21enable_context_switch_stats_dump=false |
| 22eventq_index=0 |
|
| 20flags_addr=268435504 21gic_cpu_addr=520093952 22init_param=0 | 23flags_addr=268435504 24gic_cpu_addr=520093952 25init_param=0 |
| 23kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 | 26kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 |
| 24load_addr_mask=268435455 25machine_type=RealView_PBX 26mem_mode=timing 27mem_ranges=0:134217727 28memories=system.physmem system.realview.nvmem 29multi_proc=true 30num_work_ids=16 31panic_on_oops=true --- 8 unchanged lines hidden (view full) --- 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 | 27load_addr_mask=268435455 28machine_type=RealView_PBX 29mem_mode=timing 30mem_ranges=0:134217727 31memories=system.physmem system.realview.nvmem 32multi_proc=true 33num_work_ids=16 34panic_on_oops=true --- 8 unchanged lines hidden (view full) --- 43work_end_exit_count=0 44work_item_id=-1 45system_port=system.membus.slave[0] 46 47[system.bridge] 48type=Bridge 49clk_domain=system.clk_domain 50delay=50000 |
| 51eventq_index=0 |
|
| 48ranges=268435456:520093695 1073741824:1610612735 49req_size=16 50resp_size=16 51master=system.iobus.slave[0] 52slave=system.membus.master[0] 53 54[system.cf0] 55type=IdeDisk 56children=image 57delay=1000000 58driveID=master | 52ranges=268435456:520093695 1073741824:1610612735 53req_size=16 54resp_size=16 55master=system.iobus.slave[0] 56slave=system.membus.master[0] 57 58[system.cf0] 59type=IdeDisk 60children=image 61delay=1000000 62driveID=master |
| 63eventq_index=0 |
|
| 59image=system.cf0.image 60 61[system.cf0.image] 62type=CowDiskImage 63children=child 64child=system.cf0.image.child | 64image=system.cf0.image 65 66[system.cf0.image] 67type=CowDiskImage 68children=child 69child=system.cf0.image.child |
| 70eventq_index=0 |
|
| 65image_file= 66read_only=false 67table_size=65536 68 69[system.cf0.image.child] 70type=RawDiskImage | 71image_file= 72read_only=false 73table_size=65536 74 75[system.cf0.image.child] 76type=RawDiskImage |
| 71image_file=/dist/m5/system/disks/linux-arm-ael.img | 77eventq_index=0 78image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img |
| 72read_only=true 73 74[system.clk_domain] 75type=SrcClockDomain 76clock=1000 | 79read_only=true 80 81[system.clk_domain] 82type=SrcClockDomain 83clock=1000 |
| 84eventq_index=0 |
|
| 77voltage_domain=system.voltage_domain 78 79[system.cpu] 80type=DerivO3CPU 81children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 82LFSTSize=1024 83LQEntries=32 84LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 100decodeToFetchDelay=1 101decodeToRenameDelay=1 102decodeWidth=8 103dispatchWidth=8 104do_checkpoint_insts=true 105do_quiesce=true 106do_statistics_insts=true 107dtb=system.cpu.dtb | 85voltage_domain=system.voltage_domain 86 87[system.cpu] 88type=DerivO3CPU 89children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 90LFSTSize=1024 91LQEntries=32 92LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 108decodeToFetchDelay=1 109decodeToRenameDelay=1 110decodeWidth=8 111dispatchWidth=8 112do_checkpoint_insts=true 113do_quiesce=true 114do_statistics_insts=true 115dtb=system.cpu.dtb |
| 116eventq_index=0 117fetchBufferSize=64 |
|
| 108fetchToDecodeDelay=1 109fetchTrapLatency=1 110fetchWidth=8 111forwardComSize=5 112fuPool=system.cpu.fuPool 113function_trace=false 114function_trace_start=0 115iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 164 165[system.cpu.branchPred] 166type=BranchPredictor 167BTBEntries=4096 168BTBTagSize=16 169RASSize=16 170choiceCtrBits=2 171choicePredictorSize=8192 | 118fetchToDecodeDelay=1 119fetchTrapLatency=1 120fetchWidth=8 121forwardComSize=5 122fuPool=system.cpu.fuPool 123function_trace=false 124function_trace_start=0 125iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 174 175[system.cpu.branchPred] 176type=BranchPredictor 177BTBEntries=4096 178BTBTagSize=16 179RASSize=16 180choiceCtrBits=2 181choicePredictorSize=8192 |
| 182eventq_index=0 |
|
| 172globalCtrBits=2 173globalPredictorSize=8192 174instShiftAmt=2 175localCtrBits=2 176localHistoryTableSize=2048 177localPredictorSize=2048 178numThreads=1 179predType=tournament 180 181[system.cpu.dcache] 182type=BaseCache 183children=tags 184addr_ranges=0:18446744073709551615 185assoc=4 186clk_domain=system.cpu_clk_domain | 183globalCtrBits=2 184globalPredictorSize=8192 185instShiftAmt=2 186localCtrBits=2 187localHistoryTableSize=2048 188localPredictorSize=2048 189numThreads=1 190predType=tournament 191 192[system.cpu.dcache] 193type=BaseCache 194children=tags 195addr_ranges=0:18446744073709551615 196assoc=4 197clk_domain=system.cpu_clk_domain |
| 198eventq_index=0 |
|
| 187forward_snoops=true 188hit_latency=2 189is_top_level=true 190max_miss_count=0 191mshrs=4 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 --- 6 unchanged lines hidden (view full) --- 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=4 207block_size=64 208clk_domain=system.cpu_clk_domain | 199forward_snoops=true 200hit_latency=2 201is_top_level=true 202max_miss_count=0 203mshrs=4 204prefetch_on_access=false 205prefetcher=Null 206response_latency=2 --- 6 unchanged lines hidden (view full) --- 213cpu_side=system.cpu.dcache_port 214mem_side=system.cpu.toL2Bus.slave[1] 215 216[system.cpu.dcache.tags] 217type=LRU 218assoc=4 219block_size=64 220clk_domain=system.cpu_clk_domain |
| 221eventq_index=0 |
|
| 209hit_latency=2 210size=32768 211 212[system.cpu.dtb] 213type=ArmTLB 214children=walker | 222hit_latency=2 223size=32768 224 225[system.cpu.dtb] 226type=ArmTLB 227children=walker |
| 228eventq_index=0 |
|
| 215size=64 216walker=system.cpu.dtb.walker 217 218[system.cpu.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain | 229size=64 230walker=system.cpu.dtb.walker 231 232[system.cpu.dtb.walker] 233type=ArmTableWalker 234clk_domain=system.cpu_clk_domain |
| 235eventq_index=0 |
|
| 221num_squash_per_cycle=2 222sys=system 223port=system.cpu.toL2Bus.slave[3] 224 225[system.cpu.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 | 236num_squash_per_cycle=2 237sys=system 238port=system.cpu.toL2Bus.slave[3] 239 240[system.cpu.fuPool] 241type=FUPool 242children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 243FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 |
| 244eventq_index=0 |
|
| 229 230[system.cpu.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 | 245 246[system.cpu.fuPool.FUList0] 247type=FUDesc 248children=opList 249count=6 |
| 250eventq_index=0 |
|
| 234opList=system.cpu.fuPool.FUList0.opList 235 236[system.cpu.fuPool.FUList0.opList] 237type=OpDesc | 251opList=system.cpu.fuPool.FUList0.opList 252 253[system.cpu.fuPool.FUList0.opList] 254type=OpDesc |
| 255eventq_index=0 |
|
| 238issueLat=1 239opClass=IntAlu 240opLat=1 241 242[system.cpu.fuPool.FUList1] 243type=FUDesc 244children=opList0 opList1 245count=2 | 256issueLat=1 257opClass=IntAlu 258opLat=1 259 260[system.cpu.fuPool.FUList1] 261type=FUDesc 262children=opList0 opList1 263count=2 |
| 264eventq_index=0 |
|
| 246opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 247 248[system.cpu.fuPool.FUList1.opList0] 249type=OpDesc | 265opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 266 267[system.cpu.fuPool.FUList1.opList0] 268type=OpDesc |
| 269eventq_index=0 |
|
| 250issueLat=1 251opClass=IntMult 252opLat=3 253 254[system.cpu.fuPool.FUList1.opList1] 255type=OpDesc | 270issueLat=1 271opClass=IntMult 272opLat=3 273 274[system.cpu.fuPool.FUList1.opList1] 275type=OpDesc |
| 276eventq_index=0 |
|
| 256issueLat=19 257opClass=IntDiv 258opLat=20 259 260[system.cpu.fuPool.FUList2] 261type=FUDesc 262children=opList0 opList1 opList2 263count=4 | 277issueLat=19 278opClass=IntDiv 279opLat=20 280 281[system.cpu.fuPool.FUList2] 282type=FUDesc 283children=opList0 opList1 opList2 284count=4 |
| 285eventq_index=0 |
|
| 264opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 265 266[system.cpu.fuPool.FUList2.opList0] 267type=OpDesc | 286opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 287 288[system.cpu.fuPool.FUList2.opList0] 289type=OpDesc |
| 290eventq_index=0 |
|
| 268issueLat=1 269opClass=FloatAdd 270opLat=2 271 272[system.cpu.fuPool.FUList2.opList1] 273type=OpDesc | 291issueLat=1 292opClass=FloatAdd 293opLat=2 294 295[system.cpu.fuPool.FUList2.opList1] 296type=OpDesc |
| 297eventq_index=0 |
|
| 274issueLat=1 275opClass=FloatCmp 276opLat=2 277 278[system.cpu.fuPool.FUList2.opList2] 279type=OpDesc | 298issueLat=1 299opClass=FloatCmp 300opLat=2 301 302[system.cpu.fuPool.FUList2.opList2] 303type=OpDesc |
| 304eventq_index=0 |
|
| 280issueLat=1 281opClass=FloatCvt 282opLat=2 283 284[system.cpu.fuPool.FUList3] 285type=FUDesc 286children=opList0 opList1 opList2 287count=2 | 305issueLat=1 306opClass=FloatCvt 307opLat=2 308 309[system.cpu.fuPool.FUList3] 310type=FUDesc 311children=opList0 opList1 opList2 312count=2 |
| 313eventq_index=0 |
|
| 288opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 289 290[system.cpu.fuPool.FUList3.opList0] 291type=OpDesc | 314opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 315 316[system.cpu.fuPool.FUList3.opList0] 317type=OpDesc |
| 318eventq_index=0 |
|
| 292issueLat=1 293opClass=FloatMult 294opLat=4 295 296[system.cpu.fuPool.FUList3.opList1] 297type=OpDesc | 319issueLat=1 320opClass=FloatMult 321opLat=4 322 323[system.cpu.fuPool.FUList3.opList1] 324type=OpDesc |
| 325eventq_index=0 |
|
| 298issueLat=12 299opClass=FloatDiv 300opLat=12 301 302[system.cpu.fuPool.FUList3.opList2] 303type=OpDesc | 326issueLat=12 327opClass=FloatDiv 328opLat=12 329 330[system.cpu.fuPool.FUList3.opList2] 331type=OpDesc |
| 332eventq_index=0 |
|
| 304issueLat=24 305opClass=FloatSqrt 306opLat=24 307 308[system.cpu.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 | 333issueLat=24 334opClass=FloatSqrt 335opLat=24 336 337[system.cpu.fuPool.FUList4] 338type=FUDesc 339children=opList 340count=0 |
| 341eventq_index=0 |
|
| 312opList=system.cpu.fuPool.FUList4.opList 313 314[system.cpu.fuPool.FUList4.opList] 315type=OpDesc | 342opList=system.cpu.fuPool.FUList4.opList 343 344[system.cpu.fuPool.FUList4.opList] 345type=OpDesc |
| 346eventq_index=0 |
|
| 316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 | 347issueLat=1 348opClass=MemRead 349opLat=1 350 351[system.cpu.fuPool.FUList5] 352type=FUDesc 353children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 354count=4 |
| 355eventq_index=0 |
|
| 324opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 325 326[system.cpu.fuPool.FUList5.opList00] 327type=OpDesc | 356opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 357 358[system.cpu.fuPool.FUList5.opList00] 359type=OpDesc |
| 360eventq_index=0 |
|
| 328issueLat=1 329opClass=SimdAdd 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList01] 333type=OpDesc | 361issueLat=1 362opClass=SimdAdd 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList01] 366type=OpDesc |
| 367eventq_index=0 |
|
| 334issueLat=1 335opClass=SimdAddAcc 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList02] 339type=OpDesc | 368issueLat=1 369opClass=SimdAddAcc 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList02] 373type=OpDesc |
| 374eventq_index=0 |
|
| 340issueLat=1 341opClass=SimdAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList03] 345type=OpDesc | 375issueLat=1 376opClass=SimdAlu 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList03] 380type=OpDesc |
| 381eventq_index=0 |
|
| 346issueLat=1 347opClass=SimdCmp 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList04] 351type=OpDesc | 382issueLat=1 383opClass=SimdCmp 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList04] 387type=OpDesc |
| 388eventq_index=0 |
|
| 352issueLat=1 353opClass=SimdCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList05] 357type=OpDesc | 389issueLat=1 390opClass=SimdCvt 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList05] 394type=OpDesc |
| 395eventq_index=0 |
|
| 358issueLat=1 359opClass=SimdMisc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList06] 363type=OpDesc | 396issueLat=1 397opClass=SimdMisc 398opLat=1 399 400[system.cpu.fuPool.FUList5.opList06] 401type=OpDesc |
| 402eventq_index=0 |
|
| 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList07] 369type=OpDesc | 403issueLat=1 404opClass=SimdMult 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList07] 408type=OpDesc |
| 409eventq_index=0 |
|
| 370issueLat=1 371opClass=SimdMultAcc 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList08] 375type=OpDesc | 410issueLat=1 411opClass=SimdMultAcc 412opLat=1 413 414[system.cpu.fuPool.FUList5.opList08] 415type=OpDesc |
| 416eventq_index=0 |
|
| 376issueLat=1 377opClass=SimdShift 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList09] 381type=OpDesc | 417issueLat=1 418opClass=SimdShift 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList09] 422type=OpDesc |
| 423eventq_index=0 |
|
| 382issueLat=1 383opClass=SimdShiftAcc 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList10] 387type=OpDesc | 424issueLat=1 425opClass=SimdShiftAcc 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList10] 429type=OpDesc |
| 430eventq_index=0 |
|
| 388issueLat=1 389opClass=SimdSqrt 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList11] 393type=OpDesc | 431issueLat=1 432opClass=SimdSqrt 433opLat=1 434 435[system.cpu.fuPool.FUList5.opList11] 436type=OpDesc |
| 437eventq_index=0 |
|
| 394issueLat=1 395opClass=SimdFloatAdd 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList12] 399type=OpDesc | 438issueLat=1 439opClass=SimdFloatAdd 440opLat=1 441 442[system.cpu.fuPool.FUList5.opList12] 443type=OpDesc |
| 444eventq_index=0 |
|
| 400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc | 445issueLat=1 446opClass=SimdFloatAlu 447opLat=1 448 449[system.cpu.fuPool.FUList5.opList13] 450type=OpDesc |
| 451eventq_index=0 |
|
| 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList14] 411type=OpDesc | 452issueLat=1 453opClass=SimdFloatCmp 454opLat=1 455 456[system.cpu.fuPool.FUList5.opList14] 457type=OpDesc |
| 458eventq_index=0 |
|
| 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList15] 417type=OpDesc | 459issueLat=1 460opClass=SimdFloatCvt 461opLat=1 462 463[system.cpu.fuPool.FUList5.opList15] 464type=OpDesc |
| 465eventq_index=0 |
|
| 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList16] 423type=OpDesc | 466issueLat=1 467opClass=SimdFloatDiv 468opLat=1 469 470[system.cpu.fuPool.FUList5.opList16] 471type=OpDesc |
| 472eventq_index=0 |
|
| 424issueLat=1 425opClass=SimdFloatMisc 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList17] 429type=OpDesc | 473issueLat=1 474opClass=SimdFloatMisc 475opLat=1 476 477[system.cpu.fuPool.FUList5.opList17] 478type=OpDesc |
| 479eventq_index=0 |
|
| 430issueLat=1 431opClass=SimdFloatMult 432opLat=1 433 434[system.cpu.fuPool.FUList5.opList18] 435type=OpDesc | 480issueLat=1 481opClass=SimdFloatMult 482opLat=1 483 484[system.cpu.fuPool.FUList5.opList18] 485type=OpDesc |
| 486eventq_index=0 |
|
| 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu.fuPool.FUList5.opList19] 441type=OpDesc | 487issueLat=1 488opClass=SimdFloatMultAcc 489opLat=1 490 491[system.cpu.fuPool.FUList5.opList19] 492type=OpDesc |
| 493eventq_index=0 |
|
| 442issueLat=1 443opClass=SimdFloatSqrt 444opLat=1 445 446[system.cpu.fuPool.FUList6] 447type=FUDesc 448children=opList 449count=0 | 494issueLat=1 495opClass=SimdFloatSqrt 496opLat=1 497 498[system.cpu.fuPool.FUList6] 499type=FUDesc 500children=opList 501count=0 |
| 502eventq_index=0 |
|
| 450opList=system.cpu.fuPool.FUList6.opList 451 452[system.cpu.fuPool.FUList6.opList] 453type=OpDesc | 503opList=system.cpu.fuPool.FUList6.opList 504 505[system.cpu.fuPool.FUList6.opList] 506type=OpDesc |
| 507eventq_index=0 |
|
| 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu.fuPool.FUList7] 459type=FUDesc 460children=opList0 opList1 461count=4 | 508issueLat=1 509opClass=MemWrite 510opLat=1 511 512[system.cpu.fuPool.FUList7] 513type=FUDesc 514children=opList0 opList1 515count=4 |
| 516eventq_index=0 |
|
| 462opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 463 464[system.cpu.fuPool.FUList7.opList0] 465type=OpDesc | 517opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 518 519[system.cpu.fuPool.FUList7.opList0] 520type=OpDesc |
| 521eventq_index=0 |
|
| 466issueLat=1 467opClass=MemRead 468opLat=1 469 470[system.cpu.fuPool.FUList7.opList1] 471type=OpDesc | 522issueLat=1 523opClass=MemRead 524opLat=1 525 526[system.cpu.fuPool.FUList7.opList1] 527type=OpDesc |
| 528eventq_index=0 |
|
| 472issueLat=1 473opClass=MemWrite 474opLat=1 475 476[system.cpu.fuPool.FUList8] 477type=FUDesc 478children=opList 479count=1 | 529issueLat=1 530opClass=MemWrite 531opLat=1 532 533[system.cpu.fuPool.FUList8] 534type=FUDesc 535children=opList 536count=1 |
| 537eventq_index=0 |
|
| 480opList=system.cpu.fuPool.FUList8.opList 481 482[system.cpu.fuPool.FUList8.opList] 483type=OpDesc | 538opList=system.cpu.fuPool.FUList8.opList 539 540[system.cpu.fuPool.FUList8.opList] 541type=OpDesc |
| 542eventq_index=0 |
|
| 484issueLat=3 485opClass=IprAccess 486opLat=3 487 488[system.cpu.icache] 489type=BaseCache 490children=tags 491addr_ranges=0:18446744073709551615 492assoc=1 493clk_domain=system.cpu_clk_domain | 543issueLat=3 544opClass=IprAccess 545opLat=3 546 547[system.cpu.icache] 548type=BaseCache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=1 552clk_domain=system.cpu_clk_domain |
| 553eventq_index=0 |
|
| 494forward_snoops=true 495hit_latency=2 496is_top_level=true 497max_miss_count=0 498mshrs=4 499prefetch_on_access=false 500prefetcher=Null 501response_latency=2 --- 6 unchanged lines hidden (view full) --- 508cpu_side=system.cpu.icache_port 509mem_side=system.cpu.toL2Bus.slave[0] 510 511[system.cpu.icache.tags] 512type=LRU 513assoc=1 514block_size=64 515clk_domain=system.cpu_clk_domain | 554forward_snoops=true 555hit_latency=2 556is_top_level=true 557max_miss_count=0 558mshrs=4 559prefetch_on_access=false 560prefetcher=Null 561response_latency=2 --- 6 unchanged lines hidden (view full) --- 568cpu_side=system.cpu.icache_port 569mem_side=system.cpu.toL2Bus.slave[0] 570 571[system.cpu.icache.tags] 572type=LRU 573assoc=1 574block_size=64 575clk_domain=system.cpu_clk_domain |
| 576eventq_index=0 |
|
| 516hit_latency=2 517size=32768 518 519[system.cpu.interrupts] 520type=ArmInterrupts | 577hit_latency=2 578size=32768 579 580[system.cpu.interrupts] 581type=ArmInterrupts |
| 582eventq_index=0 |
|
| 521 522[system.cpu.isa] 523type=ArmISA | 583 584[system.cpu.isa] 585type=ArmISA |
| 586eventq_index=0 |
|
| 524fpsid=1090793632 525id_isar0=34607377 526id_isar1=34677009 527id_isar2=555950401 528id_isar3=17899825 529id_isar4=268501314 530id_isar5=0 531id_mmfr0=3 532id_mmfr1=0 533id_mmfr2=19070976 534id_mmfr3=4027589137 535id_pfr0=49 536id_pfr1=1 537midr=890224640 538 539[system.cpu.itb] 540type=ArmTLB 541children=walker | 587fpsid=1090793632 588id_isar0=34607377 589id_isar1=34677009 590id_isar2=555950401 591id_isar3=17899825 592id_isar4=268501314 593id_isar5=0 594id_mmfr0=3 595id_mmfr1=0 596id_mmfr2=19070976 597id_mmfr3=4027589137 598id_pfr0=49 599id_pfr1=1 600midr=890224640 601 602[system.cpu.itb] 603type=ArmTLB 604children=walker |
| 605eventq_index=0 |
|
| 542size=64 543walker=system.cpu.itb.walker 544 545[system.cpu.itb.walker] 546type=ArmTableWalker 547clk_domain=system.cpu_clk_domain | 606size=64 607walker=system.cpu.itb.walker 608 609[system.cpu.itb.walker] 610type=ArmTableWalker 611clk_domain=system.cpu_clk_domain |
| 612eventq_index=0 |
|
| 548num_squash_per_cycle=2 549sys=system 550port=system.cpu.toL2Bus.slave[2] 551 552[system.cpu.l2cache] 553type=BaseCache 554children=tags 555addr_ranges=0:18446744073709551615 556assoc=8 557clk_domain=system.cpu_clk_domain | 613num_squash_per_cycle=2 614sys=system 615port=system.cpu.toL2Bus.slave[2] 616 617[system.cpu.l2cache] 618type=BaseCache 619children=tags 620addr_ranges=0:18446744073709551615 621assoc=8 622clk_domain=system.cpu_clk_domain |
| 623eventq_index=0 |
|
| 558forward_snoops=true 559hit_latency=20 560is_top_level=false 561max_miss_count=0 562mshrs=20 563prefetch_on_access=false 564prefetcher=Null 565response_latency=20 --- 6 unchanged lines hidden (view full) --- 572cpu_side=system.cpu.toL2Bus.master[0] 573mem_side=system.membus.slave[1] 574 575[system.cpu.l2cache.tags] 576type=LRU 577assoc=8 578block_size=64 579clk_domain=system.cpu_clk_domain | 624forward_snoops=true 625hit_latency=20 626is_top_level=false 627max_miss_count=0 628mshrs=20 629prefetch_on_access=false 630prefetcher=Null 631response_latency=20 --- 6 unchanged lines hidden (view full) --- 638cpu_side=system.cpu.toL2Bus.master[0] 639mem_side=system.membus.slave[1] 640 641[system.cpu.l2cache.tags] 642type=LRU 643assoc=8 644block_size=64 645clk_domain=system.cpu_clk_domain |
| 646eventq_index=0 |
|
| 580hit_latency=20 581size=4194304 582 583[system.cpu.toL2Bus] 584type=CoherentBus 585clk_domain=system.cpu_clk_domain | 647hit_latency=20 648size=4194304 649 650[system.cpu.toL2Bus] 651type=CoherentBus 652clk_domain=system.cpu_clk_domain |
| 653eventq_index=0 |
|
| 586header_cycles=1 587system=system 588use_default_range=false 589width=32 590master=system.cpu.l2cache.cpu_side 591slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 592 593[system.cpu.tracer] 594type=ExeTracer | 654header_cycles=1 655system=system 656use_default_range=false 657width=32 658master=system.cpu.l2cache.cpu_side 659slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 660 661[system.cpu.tracer] 662type=ExeTracer |
| 663eventq_index=0 |
|
| 595 596[system.cpu_clk_domain] 597type=SrcClockDomain 598clock=500 | 664 665[system.cpu_clk_domain] 666type=SrcClockDomain 667clock=500 |
| 668eventq_index=0 |
|
| 599voltage_domain=system.voltage_domain 600 601[system.intrctrl] 602type=IntrControl | 669voltage_domain=system.voltage_domain 670 671[system.intrctrl] 672type=IntrControl |
| 673eventq_index=0 |
|
| 603sys=system 604 605[system.iobus] 606type=NoncoherentBus 607clk_domain=system.clk_domain | 674sys=system 675 676[system.iobus] 677type=NoncoherentBus 678clk_domain=system.clk_domain |
| 679eventq_index=0 |
|
| 608header_cycles=1 609use_default_range=false 610width=8 611master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 612slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 613 614[system.iocache] 615type=BaseCache 616children=tags 617addr_ranges=0:134217727 618assoc=8 619clk_domain=system.clk_domain | 680header_cycles=1 681use_default_range=false 682width=8 683master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 684slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 685 686[system.iocache] 687type=BaseCache 688children=tags 689addr_ranges=0:134217727 690assoc=8 691clk_domain=system.clk_domain |
| 692eventq_index=0 |
|
| 620forward_snoops=false 621hit_latency=50 622is_top_level=true 623max_miss_count=0 624mshrs=20 625prefetch_on_access=false 626prefetcher=Null 627response_latency=50 --- 6 unchanged lines hidden (view full) --- 634cpu_side=system.iobus.master[25] 635mem_side=system.membus.slave[2] 636 637[system.iocache.tags] 638type=LRU 639assoc=8 640block_size=64 641clk_domain=system.clk_domain | 693forward_snoops=false 694hit_latency=50 695is_top_level=true 696max_miss_count=0 697mshrs=20 698prefetch_on_access=false 699prefetcher=Null 700response_latency=50 --- 6 unchanged lines hidden (view full) --- 707cpu_side=system.iobus.master[25] 708mem_side=system.membus.slave[2] 709 710[system.iocache.tags] 711type=LRU 712assoc=8 713block_size=64 714clk_domain=system.clk_domain |
| 715eventq_index=0 |
|
| 642hit_latency=50 643size=1024 644 645[system.membus] 646type=CoherentBus 647children=badaddr_responder 648clk_domain=system.clk_domain | 716hit_latency=50 717size=1024 718 719[system.membus] 720type=CoherentBus 721children=badaddr_responder 722clk_domain=system.clk_domain |
| 723eventq_index=0 |
|
| 649header_cycles=1 650system=system 651use_default_range=false 652width=8 653default=system.membus.badaddr_responder.pio 654master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 655slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 656 657[system.membus.badaddr_responder] 658type=IsaFake 659clk_domain=system.clk_domain | 724header_cycles=1 725system=system 726use_default_range=false 727width=8 728default=system.membus.badaddr_responder.pio 729master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 730slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 731 732[system.membus.badaddr_responder] 733type=IsaFake 734clk_domain=system.clk_domain |
| 735eventq_index=0 |
|
| 660fake_mem=false 661pio_addr=0 662pio_latency=100000 663pio_size=8 664ret_bad_addr=true 665ret_data16=65535 666ret_data32=4294967295 667ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 678banks_per_rank=8 679burst_length=8 680channels=1 681clk_domain=system.clk_domain 682conf_table_reported=true 683device_bus_width=8 684device_rowbuffer_size=1024 685devices_per_rank=8 | 736fake_mem=false 737pio_addr=0 738pio_latency=100000 739pio_size=8 740ret_bad_addr=true 741ret_data16=65535 742ret_data32=4294967295 743ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 754banks_per_rank=8 755burst_length=8 756channels=1 757clk_domain=system.clk_domain 758conf_table_reported=true 759device_bus_width=8 760device_rowbuffer_size=1024 761devices_per_rank=8 |
| 762eventq_index=0 |
|
| 686in_addr_map=true 687mem_sched_policy=frfcfs 688null=false 689page_policy=open 690range=0:134217727 691ranks_per_channel=2 692read_buffer_size=32 693static_backend_latency=10000 694static_frontend_latency=10000 695tBURST=5000 696tCL=13750 | 763in_addr_map=true 764mem_sched_policy=frfcfs 765null=false 766page_policy=open 767range=0:134217727 768ranks_per_channel=2 769read_buffer_size=32 770static_backend_latency=10000 771static_frontend_latency=10000 772tBURST=5000 773tCL=13750 |
| 774tRAS=35000 |
|
| 697tRCD=13750 698tREFI=7800000 699tRFC=300000 700tRP=13750 | 775tRCD=13750 776tREFI=7800000 777tRFC=300000 778tRP=13750 |
| 779tRRD=6250 |
|
| 701tWTR=7500 702tXAW=40000 703write_buffer_size=32 | 780tWTR=7500 781tXAW=40000 782write_buffer_size=32 |
| 704write_thresh_perc=70 | 783write_high_thresh_perc=70 784write_low_thresh_perc=0 |
| 705port=system.membus.master[6] 706 707[system.realview] 708type=RealView 709children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake | 785port=system.membus.master[6] 786 787[system.realview] 788type=RealView 789children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake |
| 790eventq_index=0 |
|
| 710intrctrl=system.intrctrl 711max_mem_size=268435456 712mem_start_addr=0 713pci_cfg_base=0 714system=system 715 716[system.realview.a9scu] 717type=A9SCU 718clk_domain=system.clk_domain | 791intrctrl=system.intrctrl 792max_mem_size=268435456 793mem_start_addr=0 794pci_cfg_base=0 795system=system 796 797[system.realview.a9scu] 798type=A9SCU 799clk_domain=system.clk_domain |
| 800eventq_index=0 |
|
| 719pio_addr=520093696 720pio_latency=100000 721system=system 722pio=system.membus.master[4] 723 724[system.realview.aaci_fake] 725type=AmbaFake 726amba_id=0 727clk_domain=system.clk_domain | 801pio_addr=520093696 802pio_latency=100000 803system=system 804pio=system.membus.master[4] 805 806[system.realview.aaci_fake] 807type=AmbaFake 808amba_id=0 809clk_domain=system.clk_domain |
| 810eventq_index=0 |
|
| 728ignore_access=false 729pio_addr=268451840 730pio_latency=100000 731system=system 732pio=system.iobus.master[21] 733 734[system.realview.cf_ctrl] 735type=IdeController --- 12 unchanged lines hidden (view full) --- 748BAR4=1 749BAR4LegacyIO=false 750BAR4Size=16 751BAR5=1 752BAR5LegacyIO=false 753BAR5Size=0 754BIST=0 755CacheLineSize=0 | 811ignore_access=false 812pio_addr=268451840 813pio_latency=100000 814system=system 815pio=system.iobus.master[21] 816 817[system.realview.cf_ctrl] 818type=IdeController --- 12 unchanged lines hidden (view full) --- 831BAR4=1 832BAR4LegacyIO=false 833BAR4Size=16 834BAR5=1 835BAR5LegacyIO=false 836BAR5Size=0 837BIST=0 838CacheLineSize=0 |
| 839CapabilityPtr=0 |
|
| 756CardbusCIS=0 757ClassCode=1 758Command=1 759DeviceID=28945 760ExpansionROM=0 761HeaderType=0 762InterruptLine=31 763InterruptPin=1 764LatencyTimer=0 | 840CardbusCIS=0 841ClassCode=1 842Command=1 843DeviceID=28945 844ExpansionROM=0 845HeaderType=0 846InterruptLine=31 847InterruptPin=1 848LatencyTimer=0 |
| 849MSICAPBaseOffset=0 850MSICAPCapId=0 851MSICAPMaskBits=0 852MSICAPMsgAddr=0 853MSICAPMsgCtrl=0 854MSICAPMsgData=0 855MSICAPMsgUpperAddr=0 856MSICAPNextCapability=0 857MSICAPPendingBits=0 858MSIXCAPBaseOffset=0 859MSIXCAPCapId=0 860MSIXCAPNextCapability=0 861MSIXMsgCtrl=0 862MSIXPbaOffset=0 863MSIXTableOffset=0 |
|
| 765MaximumLatency=0 766MinimumGrant=0 | 864MaximumLatency=0 865MinimumGrant=0 |
| 866PMCAPBaseOffset=0 867PMCAPCapId=0 868PMCAPCapabilities=0 869PMCAPCtrlStatus=0 870PMCAPNextCapability=0 871PXCAPBaseOffset=0 872PXCAPCapId=0 873PXCAPCapabilities=0 874PXCAPDevCap2=0 875PXCAPDevCapabilities=0 876PXCAPDevCtrl=0 877PXCAPDevCtrl2=0 878PXCAPDevStatus=0 879PXCAPLinkCap=0 880PXCAPLinkCtrl=0 881PXCAPLinkStatus=0 882PXCAPNextCapability=0 |
|
| 767ProgIF=133 768Revision=0 769Status=640 770SubClassCode=1 771SubsystemID=0 772SubsystemVendorID=0 773VendorID=32902 774clk_domain=system.clk_domain 775config_latency=20000 776ctrl_offset=2 777disks=system.cf0 | 883ProgIF=133 884Revision=0 885Status=640 886SubClassCode=1 887SubsystemID=0 888SubsystemVendorID=0 889VendorID=32902 890clk_domain=system.clk_domain 891config_latency=20000 892ctrl_offset=2 893disks=system.cf0 |
| 894eventq_index=0 |
|
| 778io_shift=1 779pci_bus=2 780pci_dev=7 781pci_func=0 782pio_latency=30000 783platform=system.realview 784system=system 785config=system.iobus.master[8] 786dma=system.iobus.slave[2] 787pio=system.iobus.master[7] 788 789[system.realview.clcd] 790type=Pl111 791amba_id=1315089 792clk_domain=system.clk_domain | 895io_shift=1 896pci_bus=2 897pci_dev=7 898pci_func=0 899pio_latency=30000 900platform=system.realview 901system=system 902config=system.iobus.master[8] 903dma=system.iobus.slave[2] 904pio=system.iobus.master[7] 905 906[system.realview.clcd] 907type=Pl111 908amba_id=1315089 909clk_domain=system.clk_domain |
| 910enable_capture=true 911eventq_index=0 |
|
| 793gic=system.realview.gic 794int_num=55 795pio_addr=268566528 796pio_latency=10000 797pixel_clock=41667 798system=system 799vnc=system.vncserver 800dma=system.iobus.slave[1] 801pio=system.iobus.master[4] 802 803[system.realview.dmac_fake] 804type=AmbaFake 805amba_id=0 806clk_domain=system.clk_domain | 912gic=system.realview.gic 913int_num=55 914pio_addr=268566528 915pio_latency=10000 916pixel_clock=41667 917system=system 918vnc=system.vncserver 919dma=system.iobus.slave[1] 920pio=system.iobus.master[4] 921 922[system.realview.dmac_fake] 923type=AmbaFake 924amba_id=0 925clk_domain=system.clk_domain |
| 926eventq_index=0 |
|
| 807ignore_access=false 808pio_addr=268632064 809pio_latency=100000 810system=system 811pio=system.iobus.master[9] 812 813[system.realview.flash_fake] 814type=IsaFake 815clk_domain=system.clk_domain | 927ignore_access=false 928pio_addr=268632064 929pio_latency=100000 930system=system 931pio=system.iobus.master[9] 932 933[system.realview.flash_fake] 934type=IsaFake 935clk_domain=system.clk_domain |
| 936eventq_index=0 |
|
| 816fake_mem=true 817pio_addr=1073741824 818pio_latency=100000 819pio_size=536870912 820ret_bad_addr=false 821ret_data16=65535 822ret_data32=4294967295 823ret_data64=18446744073709551615 --- 5 unchanged lines hidden (view full) --- 829 830[system.realview.gic] 831type=Pl390 832clk_domain=system.clk_domain 833cpu_addr=520093952 834cpu_pio_delay=10000 835dist_addr=520097792 836dist_pio_delay=10000 | 937fake_mem=true 938pio_addr=1073741824 939pio_latency=100000 940pio_size=536870912 941ret_bad_addr=false 942ret_data16=65535 943ret_data32=4294967295 944ret_data64=18446744073709551615 --- 5 unchanged lines hidden (view full) --- 950 951[system.realview.gic] 952type=Pl390 953clk_domain=system.clk_domain 954cpu_addr=520093952 955cpu_pio_delay=10000 956dist_addr=520097792 957dist_pio_delay=10000 |
| 958eventq_index=0 |
|
| 837int_latency=10000 838it_lines=128 | 959int_latency=10000 960it_lines=128 |
| 961msix_addr=0 |
|
| 839platform=system.realview 840system=system 841pio=system.membus.master[2] 842 843[system.realview.gpio0_fake] 844type=AmbaFake 845amba_id=0 846clk_domain=system.clk_domain | 962platform=system.realview 963system=system 964pio=system.membus.master[2] 965 966[system.realview.gpio0_fake] 967type=AmbaFake 968amba_id=0 969clk_domain=system.clk_domain |
| 970eventq_index=0 |
|
| 847ignore_access=false 848pio_addr=268513280 849pio_latency=100000 850system=system 851pio=system.iobus.master[16] 852 853[system.realview.gpio1_fake] 854type=AmbaFake 855amba_id=0 856clk_domain=system.clk_domain | 971ignore_access=false 972pio_addr=268513280 973pio_latency=100000 974system=system 975pio=system.iobus.master[16] 976 977[system.realview.gpio1_fake] 978type=AmbaFake 979amba_id=0 980clk_domain=system.clk_domain |
| 981eventq_index=0 |
|
| 857ignore_access=false 858pio_addr=268517376 859pio_latency=100000 860system=system 861pio=system.iobus.master[17] 862 863[system.realview.gpio2_fake] 864type=AmbaFake 865amba_id=0 866clk_domain=system.clk_domain | 982ignore_access=false 983pio_addr=268517376 984pio_latency=100000 985system=system 986pio=system.iobus.master[17] 987 988[system.realview.gpio2_fake] 989type=AmbaFake 990amba_id=0 991clk_domain=system.clk_domain |
| 992eventq_index=0 |
|
| 867ignore_access=false 868pio_addr=268521472 869pio_latency=100000 870system=system 871pio=system.iobus.master[18] 872 873[system.realview.kmi0] 874type=Pl050 875amba_id=1314896 876clk_domain=system.clk_domain | 993ignore_access=false 994pio_addr=268521472 995pio_latency=100000 996system=system 997pio=system.iobus.master[18] 998 999[system.realview.kmi0] 1000type=Pl050 1001amba_id=1314896 1002clk_domain=system.clk_domain |
| 1003eventq_index=0 |
|
| 877gic=system.realview.gic 878int_delay=1000000 879int_num=52 880is_mouse=false 881pio_addr=268460032 882pio_latency=100000 883system=system 884vnc=system.vncserver 885pio=system.iobus.master[5] 886 887[system.realview.kmi1] 888type=Pl050 889amba_id=1314896 890clk_domain=system.clk_domain | 1004gic=system.realview.gic 1005int_delay=1000000 1006int_num=52 1007is_mouse=false 1008pio_addr=268460032 1009pio_latency=100000 1010system=system 1011vnc=system.vncserver 1012pio=system.iobus.master[5] 1013 1014[system.realview.kmi1] 1015type=Pl050 1016amba_id=1314896 1017clk_domain=system.clk_domain |
| 1018eventq_index=0 |
|
| 891gic=system.realview.gic 892int_delay=1000000 893int_num=53 894is_mouse=true 895pio_addr=268464128 896pio_latency=100000 897system=system 898vnc=system.vncserver 899pio=system.iobus.master[6] 900 901[system.realview.l2x0_fake] 902type=IsaFake 903clk_domain=system.clk_domain | 1019gic=system.realview.gic 1020int_delay=1000000 1021int_num=53 1022is_mouse=true 1023pio_addr=268464128 1024pio_latency=100000 1025system=system 1026vnc=system.vncserver 1027pio=system.iobus.master[6] 1028 1029[system.realview.l2x0_fake] 1030type=IsaFake 1031clk_domain=system.clk_domain |
| 1032eventq_index=0 |
|
| 904fake_mem=false 905pio_addr=520101888 906pio_latency=100000 907pio_size=4095 908ret_bad_addr=false 909ret_data16=65535 910ret_data32=4294967295 911ret_data64=18446744073709551615 912ret_data8=255 913system=system 914update_data=false 915warn_access= 916pio=system.membus.master[3] 917 918[system.realview.local_cpu_timer] 919type=CpuLocalTimer 920clk_domain=system.clk_domain | 1033fake_mem=false 1034pio_addr=520101888 1035pio_latency=100000 1036pio_size=4095 1037ret_bad_addr=false 1038ret_data16=65535 1039ret_data32=4294967295 1040ret_data64=18446744073709551615 1041ret_data8=255 1042system=system 1043update_data=false 1044warn_access= 1045pio=system.membus.master[3] 1046 1047[system.realview.local_cpu_timer] 1048type=CpuLocalTimer 1049clk_domain=system.clk_domain |
| 1050eventq_index=0 |
|
| 921gic=system.realview.gic 922int_num_timer=29 923int_num_watchdog=30 924pio_addr=520095232 925pio_latency=100000 926system=system 927pio=system.membus.master[5] 928 929[system.realview.mmc_fake] 930type=AmbaFake 931amba_id=0 932clk_domain=system.clk_domain | 1051gic=system.realview.gic 1052int_num_timer=29 1053int_num_watchdog=30 1054pio_addr=520095232 1055pio_latency=100000 1056system=system 1057pio=system.membus.master[5] 1058 1059[system.realview.mmc_fake] 1060type=AmbaFake 1061amba_id=0 1062clk_domain=system.clk_domain |
| 1063eventq_index=0 |
|
| 933ignore_access=false 934pio_addr=268455936 935pio_latency=100000 936system=system 937pio=system.iobus.master[22] 938 939[system.realview.nvmem] 940type=SimpleMemory 941bandwidth=73.000000 942clk_domain=system.clk_domain 943conf_table_reported=false | 1064ignore_access=false 1065pio_addr=268455936 1066pio_latency=100000 1067system=system 1068pio=system.iobus.master[22] 1069 1070[system.realview.nvmem] 1071type=SimpleMemory 1072bandwidth=73.000000 1073clk_domain=system.clk_domain 1074conf_table_reported=false |
| 1075eventq_index=0 |
|
| 944in_addr_map=true 945latency=30000 946latency_var=0 947null=false 948range=2147483648:2214592511 949port=system.membus.master[1] 950 951[system.realview.realview_io] 952type=RealViewCtrl 953clk_domain=system.clk_domain | 1076in_addr_map=true 1077latency=30000 1078latency_var=0 1079null=false 1080range=2147483648:2214592511 1081port=system.membus.master[1] 1082 1083[system.realview.realview_io] 1084type=RealViewCtrl 1085clk_domain=system.clk_domain |
| 1086eventq_index=0 |
|
| 954idreg=0 955pio_addr=268435456 956pio_latency=100000 957proc_id0=201326592 958proc_id1=201327138 959system=system 960pio=system.iobus.master[1] 961 962[system.realview.rtc] 963type=PL031 964amba_id=3412017 965clk_domain=system.clk_domain | 1087idreg=0 1088pio_addr=268435456 1089pio_latency=100000 1090proc_id0=201326592 1091proc_id1=201327138 1092system=system 1093pio=system.iobus.master[1] 1094 1095[system.realview.rtc] 1096type=PL031 1097amba_id=3412017 1098clk_domain=system.clk_domain |
| 1099eventq_index=0 |
|
| 966gic=system.realview.gic 967int_delay=100000 968int_num=42 969pio_addr=268529664 970pio_latency=100000 971system=system 972time=Thu Jan 1 00:00:00 2009 973pio=system.iobus.master[23] 974 975[system.realview.sci_fake] 976type=AmbaFake 977amba_id=0 978clk_domain=system.clk_domain | 1100gic=system.realview.gic 1101int_delay=100000 1102int_num=42 1103pio_addr=268529664 1104pio_latency=100000 1105system=system 1106time=Thu Jan 1 00:00:00 2009 1107pio=system.iobus.master[23] 1108 1109[system.realview.sci_fake] 1110type=AmbaFake 1111amba_id=0 1112clk_domain=system.clk_domain |
| 1113eventq_index=0 |
|
| 979ignore_access=false 980pio_addr=268492800 981pio_latency=100000 982system=system 983pio=system.iobus.master[20] 984 985[system.realview.smc_fake] 986type=AmbaFake 987amba_id=0 988clk_domain=system.clk_domain | 1114ignore_access=false 1115pio_addr=268492800 1116pio_latency=100000 1117system=system 1118pio=system.iobus.master[20] 1119 1120[system.realview.smc_fake] 1121type=AmbaFake 1122amba_id=0 1123clk_domain=system.clk_domain |
| 1124eventq_index=0 |
|
| 989ignore_access=false 990pio_addr=269357056 991pio_latency=100000 992system=system 993pio=system.iobus.master[13] 994 995[system.realview.sp810_fake] 996type=AmbaFake 997amba_id=0 998clk_domain=system.clk_domain | 1125ignore_access=false 1126pio_addr=269357056 1127pio_latency=100000 1128system=system 1129pio=system.iobus.master[13] 1130 1131[system.realview.sp810_fake] 1132type=AmbaFake 1133amba_id=0 1134clk_domain=system.clk_domain |
| 1135eventq_index=0 |
|
| 999ignore_access=true 1000pio_addr=268439552 1001pio_latency=100000 1002system=system 1003pio=system.iobus.master[14] 1004 1005[system.realview.ssp_fake] 1006type=AmbaFake 1007amba_id=0 1008clk_domain=system.clk_domain | 1136ignore_access=true 1137pio_addr=268439552 1138pio_latency=100000 1139system=system 1140pio=system.iobus.master[14] 1141 1142[system.realview.ssp_fake] 1143type=AmbaFake 1144amba_id=0 1145clk_domain=system.clk_domain |
| 1146eventq_index=0 |
|
| 1009ignore_access=false 1010pio_addr=268488704 1011pio_latency=100000 1012system=system 1013pio=system.iobus.master[19] 1014 1015[system.realview.timer0] 1016type=Sp804 1017amba_id=1316868 1018clk_domain=system.clk_domain 1019clock0=1000000 1020clock1=1000000 | 1147ignore_access=false 1148pio_addr=268488704 1149pio_latency=100000 1150system=system 1151pio=system.iobus.master[19] 1152 1153[system.realview.timer0] 1154type=Sp804 1155amba_id=1316868 1156clk_domain=system.clk_domain 1157clock0=1000000 1158clock1=1000000 |
| 1159eventq_index=0 |
|
| 1021gic=system.realview.gic 1022int_num0=36 1023int_num1=36 1024pio_addr=268505088 1025pio_latency=100000 1026system=system 1027pio=system.iobus.master[2] 1028 1029[system.realview.timer1] 1030type=Sp804 1031amba_id=1316868 1032clk_domain=system.clk_domain 1033clock0=1000000 1034clock1=1000000 | 1160gic=system.realview.gic 1161int_num0=36 1162int_num1=36 1163pio_addr=268505088 1164pio_latency=100000 1165system=system 1166pio=system.iobus.master[2] 1167 1168[system.realview.timer1] 1169type=Sp804 1170amba_id=1316868 1171clk_domain=system.clk_domain 1172clock0=1000000 1173clock1=1000000 |
| 1174eventq_index=0 |
|
| 1035gic=system.realview.gic 1036int_num0=37 1037int_num1=37 1038pio_addr=268509184 1039pio_latency=100000 1040system=system 1041pio=system.iobus.master[3] 1042 1043[system.realview.uart] 1044type=Pl011 1045clk_domain=system.clk_domain 1046end_on_eot=false | 1175gic=system.realview.gic 1176int_num0=37 1177int_num1=37 1178pio_addr=268509184 1179pio_latency=100000 1180system=system 1181pio=system.iobus.master[3] 1182 1183[system.realview.uart] 1184type=Pl011 1185clk_domain=system.clk_domain 1186end_on_eot=false |
| 1187eventq_index=0 |
|
| 1047gic=system.realview.gic 1048int_delay=100000 1049int_num=44 1050pio_addr=268472320 1051pio_latency=100000 1052platform=system.realview 1053system=system 1054terminal=system.terminal 1055pio=system.iobus.master[0] 1056 1057[system.realview.uart1_fake] 1058type=AmbaFake 1059amba_id=0 1060clk_domain=system.clk_domain | 1188gic=system.realview.gic 1189int_delay=100000 1190int_num=44 1191pio_addr=268472320 1192pio_latency=100000 1193platform=system.realview 1194system=system 1195terminal=system.terminal 1196pio=system.iobus.master[0] 1197 1198[system.realview.uart1_fake] 1199type=AmbaFake 1200amba_id=0 1201clk_domain=system.clk_domain |
| 1202eventq_index=0 |
|
| 1061ignore_access=false 1062pio_addr=268476416 1063pio_latency=100000 1064system=system 1065pio=system.iobus.master[10] 1066 1067[system.realview.uart2_fake] 1068type=AmbaFake 1069amba_id=0 1070clk_domain=system.clk_domain | 1203ignore_access=false 1204pio_addr=268476416 1205pio_latency=100000 1206system=system 1207pio=system.iobus.master[10] 1208 1209[system.realview.uart2_fake] 1210type=AmbaFake 1211amba_id=0 1212clk_domain=system.clk_domain |
| 1213eventq_index=0 |
|
| 1071ignore_access=false 1072pio_addr=268480512 1073pio_latency=100000 1074system=system 1075pio=system.iobus.master[11] 1076 1077[system.realview.uart3_fake] 1078type=AmbaFake 1079amba_id=0 1080clk_domain=system.clk_domain | 1214ignore_access=false 1215pio_addr=268480512 1216pio_latency=100000 1217system=system 1218pio=system.iobus.master[11] 1219 1220[system.realview.uart3_fake] 1221type=AmbaFake 1222amba_id=0 1223clk_domain=system.clk_domain |
| 1224eventq_index=0 |
|
| 1081ignore_access=false 1082pio_addr=268484608 1083pio_latency=100000 1084system=system 1085pio=system.iobus.master[12] 1086 1087[system.realview.watchdog_fake] 1088type=AmbaFake 1089amba_id=0 1090clk_domain=system.clk_domain | 1225ignore_access=false 1226pio_addr=268484608 1227pio_latency=100000 1228system=system 1229pio=system.iobus.master[12] 1230 1231[system.realview.watchdog_fake] 1232type=AmbaFake 1233amba_id=0 1234clk_domain=system.clk_domain |
| 1235eventq_index=0 |
|
| 1091ignore_access=false 1092pio_addr=268500992 1093pio_latency=100000 1094system=system 1095pio=system.iobus.master[15] 1096 1097[system.terminal] 1098type=Terminal | 1236ignore_access=false 1237pio_addr=268500992 1238pio_latency=100000 1239system=system 1240pio=system.iobus.master[15] 1241 1242[system.terminal] 1243type=Terminal |
| 1244eventq_index=0 |
|
| 1099intr_control=system.intrctrl 1100number=0 1101output=true 1102port=3456 1103 1104[system.vncserver] 1105type=VncServer | 1245intr_control=system.intrctrl 1246number=0 1247output=true 1248port=3456 1249 1250[system.vncserver] 1251type=VncServer |
| 1252eventq_index=0 |
|
| 1106frame_capture=false 1107number=0 1108port=5900 1109 1110[system.voltage_domain] 1111type=VoltageDomain | 1253frame_capture=false 1254number=0 1255port=5900 1256 1257[system.voltage_domain] 1258type=VoltageDomain |
| 1259eventq_index=0 |
|
| 1112voltage=1.000000 1113 | 1260voltage=1.000000 1261 |