| config.ini (10315:9e02c14446bb) | config.ini (10451:3a87241adfb8) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 87 unchanged lines hidden (view full) --- 96eventq_index=0 97init_perf_level=0 98voltage_domain=system.voltage_domain 99 100[system.cpu] 101type=DerivO3CPU 102children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 103LFSTSize=1024 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 87 unchanged lines hidden (view full) --- 96eventq_index=0 97init_perf_level=0 98voltage_domain=system.voltage_domain 99 100[system.cpu] 101type=DerivO3CPU 102children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 103LFSTSize=1024 |
| 104LQEntries=32 | 104LQEntries=16 |
| 105LSQCheckLoads=true | 105LSQCheckLoads=true |
| 106LSQDepCheckShift=4 107SQEntries=32 | 106LSQDepCheckShift=0 107SQEntries=16 |
| 108SSITSize=1024 109activity=0 110backComSize=5 111branchPred=system.cpu.branchPred 112cachePorts=200 113checker=Null 114clk_domain=system.cpu_clk_domain 115commitToDecodeDelay=1 116commitToFetchDelay=1 117commitToIEWDelay=1 118commitToRenameDelay=1 119commitWidth=8 120cpu_id=0 121decodeToFetchDelay=1 | 108SSITSize=1024 109activity=0 110backComSize=5 111branchPred=system.cpu.branchPred 112cachePorts=200 113checker=Null 114clk_domain=system.cpu_clk_domain 115commitToDecodeDelay=1 116commitToFetchDelay=1 117commitToIEWDelay=1 118commitToRenameDelay=1 119commitWidth=8 120cpu_id=0 121decodeToFetchDelay=1 |
| 122decodeToRenameDelay=1 123decodeWidth=8 124dispatchWidth=8 | 122decodeToRenameDelay=2 123decodeWidth=3 124dispatchWidth=6 |
| 125do_checkpoint_insts=true 126do_quiesce=true 127do_statistics_insts=true 128dstage2_mmu=system.cpu.dstage2_mmu 129dtb=system.cpu.dtb 130eventq_index=0 | 125do_checkpoint_insts=true 126do_quiesce=true 127do_statistics_insts=true 128dstage2_mmu=system.cpu.dstage2_mmu 129dtb=system.cpu.dtb 130eventq_index=0 |
| 131fetchBufferSize=64 132fetchToDecodeDelay=1 | 131fetchBufferSize=16 132fetchQueueSize=32 133fetchToDecodeDelay=3 |
| 133fetchTrapLatency=1 | 134fetchTrapLatency=1 |
| 134fetchWidth=8 | 135fetchWidth=3 |
| 135forwardComSize=5 136fuPool=system.cpu.fuPool 137function_trace=false 138function_trace_start=0 139iewToCommitDelay=1 140iewToDecodeDelay=1 141iewToFetchDelay=1 142iewToRenameDelay=1 143interrupts=system.cpu.interrupts 144isa=system.cpu.isa 145issueToExecuteDelay=1 146issueWidth=8 147istage2_mmu=system.cpu.istage2_mmu 148itb=system.cpu.itb 149max_insts_all_threads=0 150max_insts_any_thread=0 151max_loads_all_threads=0 152max_loads_any_thread=0 153needsTSO=false | 136forwardComSize=5 137fuPool=system.cpu.fuPool 138function_trace=false 139function_trace_start=0 140iewToCommitDelay=1 141iewToDecodeDelay=1 142iewToFetchDelay=1 143iewToRenameDelay=1 144interrupts=system.cpu.interrupts 145isa=system.cpu.isa 146issueToExecuteDelay=1 147issueWidth=8 148istage2_mmu=system.cpu.istage2_mmu 149itb=system.cpu.itb 150max_insts_all_threads=0 151max_insts_any_thread=0 152max_loads_all_threads=0 153max_loads_any_thread=0 154needsTSO=false |
| 154numIQEntries=64 155numPhysCCRegs=0 156numPhysFloatRegs=256 157numPhysIntRegs=256 158numROBEntries=192 | 155numIQEntries=32 156numPhysCCRegs=640 157numPhysFloatRegs=192 158numPhysIntRegs=128 159numROBEntries=40 |
| 159numRobs=1 160numThreads=1 161profile=0 162progress_interval=0 163renameToDecodeDelay=1 164renameToFetchDelay=1 | 160numRobs=1 161numThreads=1 162profile=0 163progress_interval=0 164renameToDecodeDelay=1 165renameToFetchDelay=1 |
| 165renameToIEWDelay=2 | 166renameToIEWDelay=1 |
| 166renameToROBDelay=1 | 167renameToROBDelay=1 |
| 167renameWidth=8 | 168renameWidth=3 |
| 168simpoint_start_insts= 169smtCommitPolicy=RoundRobin 170smtFetchPolicy=SingleThread 171smtIQPolicy=Partitioned 172smtIQThreshold=100 173smtLSQPolicy=Partitioned 174smtLSQThreshold=100 175smtNumFetchingThreads=1 176smtROBPolicy=Partitioned 177smtROBThreshold=100 178socket_id=0 179squashWidth=8 180store_set_clear_period=250000 181switched_out=false 182system=system 183tracer=system.cpu.tracer 184trapLatency=13 | 169simpoint_start_insts= 170smtCommitPolicy=RoundRobin 171smtFetchPolicy=SingleThread 172smtIQPolicy=Partitioned 173smtIQThreshold=100 174smtLSQPolicy=Partitioned 175smtLSQThreshold=100 176smtNumFetchingThreads=1 177smtROBPolicy=Partitioned 178smtROBThreshold=100 179socket_id=0 180squashWidth=8 181store_set_clear_period=250000 182switched_out=false 183system=system 184tracer=system.cpu.tracer 185trapLatency=13 |
| 185wbDepth=1 | |
| 186wbWidth=8 187workload= 188dcache_port=system.cpu.dcache.cpu_side 189icache_port=system.cpu.icache.cpu_side 190 191[system.cpu.branchPred] 192type=BranchPredictor | 186wbWidth=8 187workload= 188dcache_port=system.cpu.dcache.cpu_side 189icache_port=system.cpu.icache.cpu_side 190 191[system.cpu.branchPred] 192type=BranchPredictor |
| 193BTBEntries=4096 194BTBTagSize=16 | 193BTBEntries=2048 194BTBTagSize=18 |
| 195RASSize=16 196choiceCtrBits=2 197choicePredictorSize=8192 198eventq_index=0 199globalCtrBits=2 200globalPredictorSize=8192 201instShiftAmt=2 202localCtrBits=2 203localHistoryTableSize=2048 204localPredictorSize=2048 205numThreads=1 | 195RASSize=16 196choiceCtrBits=2 197choicePredictorSize=8192 198eventq_index=0 199globalCtrBits=2 200globalPredictorSize=8192 201instShiftAmt=2 202localCtrBits=2 203localHistoryTableSize=2048 204localPredictorSize=2048 205numThreads=1 |
| 206predType=tournament | 206predType=bi-mode |
| 207 208[system.cpu.dcache] 209type=BaseCache 210children=tags 211addr_ranges=0:18446744073709551615 212assoc=4 213clk_domain=system.cpu_clk_domain 214eventq_index=0 --- 63 unchanged lines hidden (view full) --- 278eventq_index=0 279is_stage2=false 280num_squash_per_cycle=2 281sys=system 282port=system.cpu.toL2Bus.slave[3] 283 284[system.cpu.fuPool] 285type=FUPool | 207 208[system.cpu.dcache] 209type=BaseCache 210children=tags 211addr_ranges=0:18446744073709551615 212assoc=4 213clk_domain=system.cpu_clk_domain 214eventq_index=0 --- 63 unchanged lines hidden (view full) --- 278eventq_index=0 279is_stage2=false 280num_squash_per_cycle=2 281sys=system 282port=system.cpu.toL2Bus.slave[3] 283 284[system.cpu.fuPool] 285type=FUPool |
| 286children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 287FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 | 286children=FUList0 FUList1 FUList2 FUList3 FUList4 287FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 |
| 288eventq_index=0 289 290[system.cpu.fuPool.FUList0] 291type=FUDesc 292children=opList | 288eventq_index=0 289 290[system.cpu.fuPool.FUList0] 291type=FUDesc 292children=opList |
| 293count=6 | 293count=2 |
| 294eventq_index=0 295opList=system.cpu.fuPool.FUList0.opList 296 297[system.cpu.fuPool.FUList0.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=IntAlu 302opLat=1 303 304[system.cpu.fuPool.FUList1] 305type=FUDesc | 294eventq_index=0 295opList=system.cpu.fuPool.FUList0.opList 296 297[system.cpu.fuPool.FUList0.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=IntAlu 302opLat=1 303 304[system.cpu.fuPool.FUList1] 305type=FUDesc |
| 306children=opList0 opList1 307count=2 | 306children=opList0 opList1 opList2 307count=1 |
| 308eventq_index=0 | 308eventq_index=0 |
| 309opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 | 309opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 |
| 310 311[system.cpu.fuPool.FUList1.opList0] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=IntMult 316opLat=3 317 318[system.cpu.fuPool.FUList1.opList1] 319type=OpDesc 320eventq_index=0 | 310 311[system.cpu.fuPool.FUList1.opList0] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=IntMult 316opLat=3 317 318[system.cpu.fuPool.FUList1.opList1] 319type=OpDesc 320eventq_index=0 |
| 321issueLat=19 | 321issueLat=12 |
| 322opClass=IntDiv | 322opClass=IntDiv |
| 323opLat=20 | 323opLat=12 |
| 324 | 324 |
| 325[system.cpu.fuPool.FUList2] 326type=FUDesc 327children=opList0 opList1 opList2 328count=4 329eventq_index=0 330opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 331 332[system.cpu.fuPool.FUList2.opList0] | 325[system.cpu.fuPool.FUList1.opList2] |
| 333type=OpDesc 334eventq_index=0 335issueLat=1 | 326type=OpDesc 327eventq_index=0 328issueLat=1 |
| 336opClass=FloatAdd 337opLat=2 | 329opClass=IprAccess 330opLat=3 |
| 338 | 331 |
| 339[system.cpu.fuPool.FUList2.opList1] 340type=OpDesc | 332[system.cpu.fuPool.FUList2] 333type=FUDesc 334children=opList 335count=1 |
| 341eventq_index=0 | 336eventq_index=0 |
| 342issueLat=1 343opClass=FloatCmp 344opLat=2 | 337opList=system.cpu.fuPool.FUList2.opList |
| 345 | 338 |
| 346[system.cpu.fuPool.FUList2.opList2] | 339[system.cpu.fuPool.FUList2.opList] |
| 347type=OpDesc 348eventq_index=0 349issueLat=1 | 340type=OpDesc 341eventq_index=0 342issueLat=1 |
| 350opClass=FloatCvt | 343opClass=MemRead |
| 351opLat=2 352 353[system.cpu.fuPool.FUList3] 354type=FUDesc | 344opLat=2 345 346[system.cpu.fuPool.FUList3] 347type=FUDesc |
| 355children=opList0 opList1 opList2 356count=2 | 348children=opList 349count=1 |
| 357eventq_index=0 | 350eventq_index=0 |
| 358opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 | 351opList=system.cpu.fuPool.FUList3.opList |
| 359 | 352 |
| 360[system.cpu.fuPool.FUList3.opList0] | 353[system.cpu.fuPool.FUList3.opList] |
| 361type=OpDesc 362eventq_index=0 363issueLat=1 | 354type=OpDesc 355eventq_index=0 356issueLat=1 |
| 364opClass=FloatMult 365opLat=4 | 357opClass=MemWrite 358opLat=2 |
| 366 | 359 |
| 367[system.cpu.fuPool.FUList3.opList1] 368type=OpDesc 369eventq_index=0 370issueLat=12 371opClass=FloatDiv 372opLat=12 373 374[system.cpu.fuPool.FUList3.opList2] 375type=OpDesc 376eventq_index=0 377issueLat=24 378opClass=FloatSqrt 379opLat=24 380 | |
| 381[system.cpu.fuPool.FUList4] 382type=FUDesc | 360[system.cpu.fuPool.FUList4] 361type=FUDesc |
| 383children=opList 384count=0 | 362children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 363count=2 |
| 385eventq_index=0 | 364eventq_index=0 |
| 386opList=system.cpu.fuPool.FUList4.opList | 365opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 |
| 387 | 366 |
| 388[system.cpu.fuPool.FUList4.opList] | 367[system.cpu.fuPool.FUList4.opList00] |
| 389type=OpDesc 390eventq_index=0 391issueLat=1 | 368type=OpDesc 369eventq_index=0 370issueLat=1 |
| 392opClass=MemRead 393opLat=1 394 395[system.cpu.fuPool.FUList5] 396type=FUDesc 397children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 398count=4 399eventq_index=0 400opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 401 402[system.cpu.fuPool.FUList5.opList00] 403type=OpDesc 404eventq_index=0 405issueLat=1 | |
| 406opClass=SimdAdd | 371opClass=SimdAdd |
| 407opLat=1 | 372opLat=4 |
| 408 | 373 |
| 409[system.cpu.fuPool.FUList5.opList01] | 374[system.cpu.fuPool.FUList4.opList01] |
| 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdAddAcc | 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdAddAcc |
| 414opLat=1 | 379opLat=4 |
| 415 | 380 |
| 416[system.cpu.fuPool.FUList5.opList02] | 381[system.cpu.fuPool.FUList4.opList02] |
| 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdAlu | 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdAlu |
| 421opLat=1 | 386opLat=4 |
| 422 | 387 |
| 423[system.cpu.fuPool.FUList5.opList03] | 388[system.cpu.fuPool.FUList4.opList03] |
| 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdCmp | 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdCmp |
| 428opLat=1 | 393opLat=4 |
| 429 | 394 |
| 430[system.cpu.fuPool.FUList5.opList04] | 395[system.cpu.fuPool.FUList4.opList04] |
| 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdCvt | 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdCvt |
| 435opLat=1 | 400opLat=3 |
| 436 | 401 |
| 437[system.cpu.fuPool.FUList5.opList05] | 402[system.cpu.fuPool.FUList4.opList05] |
| 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdMisc | 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdMisc |
| 442opLat=1 | 407opLat=3 |
| 443 | 408 |
| 444[system.cpu.fuPool.FUList5.opList06] | 409[system.cpu.fuPool.FUList4.opList06] |
| 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdMult | 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdMult |
| 449opLat=1 | 414opLat=5 |
| 450 | 415 |
| 451[system.cpu.fuPool.FUList5.opList07] | 416[system.cpu.fuPool.FUList4.opList07] |
| 452type=OpDesc 453eventq_index=0 454issueLat=1 455opClass=SimdMultAcc | 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdMultAcc |
| 456opLat=1 | 421opLat=5 |
| 457 | 422 |
| 458[system.cpu.fuPool.FUList5.opList08] | 423[system.cpu.fuPool.FUList4.opList08] |
| 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=SimdShift | 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdShift |
| 463opLat=1 | 428opLat=3 |
| 464 | 429 |
| 465[system.cpu.fuPool.FUList5.opList09] | 430[system.cpu.fuPool.FUList4.opList09] |
| 466type=OpDesc 467eventq_index=0 468issueLat=1 469opClass=SimdShiftAcc | 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdShiftAcc |
| 470opLat=1 | 435opLat=3 |
| 471 | 436 |
| 472[system.cpu.fuPool.FUList5.opList10] | 437[system.cpu.fuPool.FUList4.opList10] |
| 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=SimdSqrt | 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdSqrt |
| 477opLat=1 | 442opLat=9 |
| 478 | 443 |
| 479[system.cpu.fuPool.FUList5.opList11] | 444[system.cpu.fuPool.FUList4.opList11] |
| 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=SimdFloatAdd | 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatAdd |
| 484opLat=1 | 449opLat=5 |
| 485 | 450 |
| 486[system.cpu.fuPool.FUList5.opList12] | 451[system.cpu.fuPool.FUList4.opList12] |
| 487type=OpDesc 488eventq_index=0 489issueLat=1 490opClass=SimdFloatAlu | 452type=OpDesc 453eventq_index=0 454issueLat=1 455opClass=SimdFloatAlu |
| 491opLat=1 | 456opLat=5 |
| 492 | 457 |
| 493[system.cpu.fuPool.FUList5.opList13] | 458[system.cpu.fuPool.FUList4.opList13] |
| 494type=OpDesc 495eventq_index=0 496issueLat=1 497opClass=SimdFloatCmp | 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=SimdFloatCmp |
| 498opLat=1 | 463opLat=3 |
| 499 | 464 |
| 500[system.cpu.fuPool.FUList5.opList14] | 465[system.cpu.fuPool.FUList4.opList14] |
| 501type=OpDesc 502eventq_index=0 503issueLat=1 504opClass=SimdFloatCvt | 466type=OpDesc 467eventq_index=0 468issueLat=1 469opClass=SimdFloatCvt |
| 505opLat=1 | 470opLat=3 |
| 506 | 471 |
| 507[system.cpu.fuPool.FUList5.opList15] | 472[system.cpu.fuPool.FUList4.opList15] |
| 508type=OpDesc 509eventq_index=0 510issueLat=1 511opClass=SimdFloatDiv | 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=SimdFloatDiv |
| 512opLat=1 | 477opLat=3 |
| 513 | 478 |
| 514[system.cpu.fuPool.FUList5.opList16] | 479[system.cpu.fuPool.FUList4.opList16] |
| 515type=OpDesc 516eventq_index=0 517issueLat=1 518opClass=SimdFloatMisc | 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=SimdFloatMisc |
| 519opLat=1 | 484opLat=3 |
| 520 | 485 |
| 521[system.cpu.fuPool.FUList5.opList17] | 486[system.cpu.fuPool.FUList4.opList17] |
| 522type=OpDesc 523eventq_index=0 524issueLat=1 525opClass=SimdFloatMult | 487type=OpDesc 488eventq_index=0 489issueLat=1 490opClass=SimdFloatMult |
| 526opLat=1 | 491opLat=3 |
| 527 | 492 |
| 528[system.cpu.fuPool.FUList5.opList18] | 493[system.cpu.fuPool.FUList4.opList18] |
| 529type=OpDesc 530eventq_index=0 531issueLat=1 532opClass=SimdFloatMultAcc 533opLat=1 534 | 494type=OpDesc 495eventq_index=0 496issueLat=1 497opClass=SimdFloatMultAcc 498opLat=1 499 |
| 535[system.cpu.fuPool.FUList5.opList19] | 500[system.cpu.fuPool.FUList4.opList19] |
| 536type=OpDesc 537eventq_index=0 538issueLat=1 539opClass=SimdFloatSqrt | 501type=OpDesc 502eventq_index=0 503issueLat=1 504opClass=SimdFloatSqrt |
| 540opLat=1 | 505opLat=9 |
| 541 | 506 |
| 542[system.cpu.fuPool.FUList6] 543type=FUDesc 544children=opList 545count=0 | 507[system.cpu.fuPool.FUList4.opList20] 508type=OpDesc |
| 546eventq_index=0 | 509eventq_index=0 |
| 547opList=system.cpu.fuPool.FUList6.opList | 510issueLat=1 511opClass=FloatAdd 512opLat=5 |
| 548 | 513 |
| 549[system.cpu.fuPool.FUList6.opList] | 514[system.cpu.fuPool.FUList4.opList21] |
| 550type=OpDesc 551eventq_index=0 552issueLat=1 | 515type=OpDesc 516eventq_index=0 517issueLat=1 |
| 553opClass=MemWrite 554opLat=1 | 518opClass=FloatCmp 519opLat=5 |
| 555 | 520 |
| 556[system.cpu.fuPool.FUList7] 557type=FUDesc 558children=opList0 opList1 559count=4 560eventq_index=0 561opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 562 563[system.cpu.fuPool.FUList7.opList0] | 521[system.cpu.fuPool.FUList4.opList22] |
| 564type=OpDesc 565eventq_index=0 566issueLat=1 | 522type=OpDesc 523eventq_index=0 524issueLat=1 |
| 567opClass=MemRead 568opLat=1 | 525opClass=FloatCvt 526opLat=5 |
| 569 | 527 |
| 570[system.cpu.fuPool.FUList7.opList1] | 528[system.cpu.fuPool.FUList4.opList23] |
| 571type=OpDesc 572eventq_index=0 | 529type=OpDesc 530eventq_index=0 |
| 573issueLat=1 574opClass=MemWrite 575opLat=1 | 531issueLat=9 532opClass=FloatDiv 533opLat=9 |
| 576 | 534 |
| 577[system.cpu.fuPool.FUList8] 578type=FUDesc 579children=opList 580count=1 | 535[system.cpu.fuPool.FUList4.opList24] 536type=OpDesc |
| 581eventq_index=0 | 537eventq_index=0 |
| 582opList=system.cpu.fuPool.FUList8.opList | 538issueLat=33 539opClass=FloatSqrt 540opLat=33 |
| 583 | 541 |
| 584[system.cpu.fuPool.FUList8.opList] | 542[system.cpu.fuPool.FUList4.opList25] |
| 585type=OpDesc 586eventq_index=0 | 543type=OpDesc 544eventq_index=0 |
| 587issueLat=3 588opClass=IprAccess 589opLat=3 | 545issueLat=1 546opClass=FloatMult 547opLat=4 |
| 590 591[system.cpu.icache] 592type=BaseCache 593children=tags 594addr_ranges=0:18446744073709551615 595assoc=1 596clk_domain=system.cpu_clk_domain 597eventq_index=0 --- 130 unchanged lines hidden (view full) --- 728block_size=64 729clk_domain=system.cpu_clk_domain 730eventq_index=0 731hit_latency=20 732sequential_access=false 733size=4194304 734 735[system.cpu.toL2Bus] | 548 549[system.cpu.icache] 550type=BaseCache 551children=tags 552addr_ranges=0:18446744073709551615 553assoc=1 554clk_domain=system.cpu_clk_domain 555eventq_index=0 --- 130 unchanged lines hidden (view full) --- 686block_size=64 687clk_domain=system.cpu_clk_domain 688eventq_index=0 689hit_latency=20 690sequential_access=false 691size=4194304 692 693[system.cpu.toL2Bus] |
| 736type=CoherentBus | 694type=CoherentXBar |
| 737clk_domain=system.cpu_clk_domain 738eventq_index=0 739header_cycles=1 | 695clk_domain=system.cpu_clk_domain 696eventq_index=0 697header_cycles=1 |
| 698snoop_filter=Null |
|
| 740system=system 741use_default_range=false 742width=32 743master=system.cpu.l2cache.cpu_side 744slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 745 746[system.cpu.tracer] 747type=ExeTracer --- 16 unchanged lines hidden (view full) --- 764transition_latency=100000000 765 766[system.intrctrl] 767type=IntrControl 768eventq_index=0 769sys=system 770 771[system.iobus] | 699system=system 700use_default_range=false 701width=32 702master=system.cpu.l2cache.cpu_side 703slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 704 705[system.cpu.tracer] 706type=ExeTracer --- 16 unchanged lines hidden (view full) --- 723transition_latency=100000000 724 725[system.intrctrl] 726type=IntrControl 727eventq_index=0 728sys=system 729 730[system.iobus] |
| 772type=NoncoherentBus | 731type=NoncoherentXBar |
| 773clk_domain=system.clk_domain 774eventq_index=0 775header_cycles=1 776use_default_range=false 777width=8 | 732clk_domain=system.clk_domain 733eventq_index=0 734header_cycles=1 735use_default_range=false 736width=8 |
| 778master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side | 737master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side |
| 779slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 780 781[system.iocache] 782type=BaseCache 783children=tags 784addr_ranges=0:134217727 785assoc=8 786clk_domain=system.clk_domain --- 8 unchanged lines hidden (view full) --- 795response_latency=50 796sequential_access=false 797size=1024 798system=system 799tags=system.iocache.tags 800tgts_per_mshr=12 801two_queue=false 802write_buffers=8 | 738slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 739 740[system.iocache] 741type=BaseCache 742children=tags 743addr_ranges=0:134217727 744assoc=8 745clk_domain=system.clk_domain --- 8 unchanged lines hidden (view full) --- 754response_latency=50 755sequential_access=false 756size=1024 757system=system 758tags=system.iocache.tags 759tgts_per_mshr=12 760two_queue=false 761write_buffers=8 |
| 803cpu_side=system.iobus.master[25] | 762cpu_side=system.iobus.master[26] |
| 804mem_side=system.membus.slave[2] 805 806[system.iocache.tags] 807type=LRU 808assoc=8 809block_size=64 810clk_domain=system.clk_domain 811eventq_index=0 812hit_latency=50 813sequential_access=false 814size=1024 815 816[system.membus] | 763mem_side=system.membus.slave[2] 764 765[system.iocache.tags] 766type=LRU 767assoc=8 768block_size=64 769clk_domain=system.clk_domain 770eventq_index=0 771hit_latency=50 772sequential_access=false 773size=1024 774 775[system.membus] |
| 817type=CoherentBus | 776type=CoherentXBar |
| 818children=badaddr_responder 819clk_domain=system.clk_domain 820eventq_index=0 821header_cycles=1 | 777children=badaddr_responder 778clk_domain=system.clk_domain 779eventq_index=0 780header_cycles=1 |
| 781snoop_filter=Null |
|
| 822system=system 823use_default_range=false 824width=8 825default=system.membus.badaddr_responder.pio 826master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 827slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 828 829[system.membus.badaddr_responder] --- 11 unchanged lines hidden (view full) --- 841ret_data8=255 842system=system 843update_data=false 844warn_access=warn 845pio=system.membus.default 846 847[system.physmem] 848type=DRAMCtrl | 782system=system 783use_default_range=false 784width=8 785default=system.membus.badaddr_responder.pio 786master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 787slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 788 789[system.membus.badaddr_responder] --- 11 unchanged lines hidden (view full) --- 801ret_data8=255 802system=system 803update_data=false 804warn_access=warn 805pio=system.membus.default 806 807[system.physmem] 808type=DRAMCtrl |
| 809IDD0=0.075000 810IDD02=0.000000 811IDD2N=0.050000 812IDD2N2=0.000000 813IDD2P0=0.000000 814IDD2P02=0.000000 815IDD2P1=0.000000 816IDD2P12=0.000000 817IDD3N=0.057000 818IDD3N2=0.000000 819IDD3P0=0.000000 820IDD3P02=0.000000 821IDD3P1=0.000000 822IDD3P12=0.000000 823IDD4R=0.187000 824IDD4R2=0.000000 825IDD4W=0.165000 826IDD4W2=0.000000 827IDD5=0.220000 828IDD52=0.000000 829IDD6=0.000000 830IDD62=0.000000 831VDD=1.500000 832VDD2=0.000000 |
|
| 849activation_limit=4 850addr_mapping=RoRaBaChCo | 833activation_limit=4 834addr_mapping=RoRaBaChCo |
| 835bank_groups_per_rank=0 |
|
| 851banks_per_rank=8 852burst_length=8 853channels=1 854clk_domain=system.clk_domain 855conf_table_reported=true 856device_bus_width=8 857device_rowbuffer_size=1024 858devices_per_rank=8 | 836banks_per_rank=8 837burst_length=8 838channels=1 839clk_domain=system.clk_domain 840conf_table_reported=true 841device_bus_width=8 842device_rowbuffer_size=1024 843devices_per_rank=8 |
| 844dll=true |
|
| 859eventq_index=0 860in_addr_map=true 861max_accesses_per_row=16 862mem_sched_policy=frfcfs 863min_writes_per_switch=16 864null=false 865page_policy=open_adaptive 866range=0:134217727 867ranks_per_channel=2 868read_buffer_size=32 869static_backend_latency=10000 870static_frontend_latency=10000 871tBURST=5000 | 845eventq_index=0 846in_addr_map=true 847max_accesses_per_row=16 848mem_sched_policy=frfcfs 849min_writes_per_switch=16 850null=false 851page_policy=open_adaptive 852range=0:134217727 853ranks_per_channel=2 854read_buffer_size=32 855static_backend_latency=10000 856static_frontend_latency=10000 857tBURST=5000 |
| 858tCCD_L=0 |
|
| 872tCK=1250 873tCL=13750 | 859tCK=1250 860tCL=13750 |
| 861tCS=2500 |
|
| 874tRAS=35000 875tRCD=13750 876tREFI=7800000 877tRFC=260000 878tRP=13750 879tRRD=6000 | 862tRAS=35000 863tRCD=13750 864tREFI=7800000 865tRFC=260000 866tRP=13750 867tRRD=6000 |
| 868tRRD_L=0 |
|
| 880tRTP=7500 881tRTW=2500 882tWR=15000 883tWTR=7500 884tXAW=30000 | 869tRTP=7500 870tRTW=2500 871tWR=15000 872tWTR=7500 873tXAW=30000 |
| 874tXP=0 875tXPDLL=0 876tXS=0 877tXSDLL=0 |
|
| 885write_buffer_size=64 886write_high_thresh_perc=85 887write_low_thresh_perc=50 888port=system.membus.master[6] 889 890[system.realview] 891type=RealView | 878write_buffer_size=64 879write_high_thresh_perc=85 880write_low_thresh_perc=50 881port=system.membus.master[6] 882 883[system.realview] 884type=RealView |
| 892children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake | 885children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake |
| 893eventq_index=0 894intrctrl=system.intrctrl | 886eventq_index=0 887intrctrl=system.intrctrl |
| 895max_mem_size=268435456 896mem_start_addr=0 | |
| 897pci_cfg_base=0 | 888pci_cfg_base=0 |
| 889pci_cfg_gen_offsets=false 890pci_io_base=0 |
|
| 898system=system 899 900[system.realview.a9scu] 901type=A9SCU 902clk_domain=system.clk_domain 903eventq_index=0 904pio_addr=520093696 905pio_latency=100000 --- 38 unchanged lines hidden (view full) --- 944ClassCode=1 945Command=1 946DeviceID=28945 947ExpansionROM=0 948HeaderType=0 949InterruptLine=31 950InterruptPin=1 951LatencyTimer=0 | 891system=system 892 893[system.realview.a9scu] 894type=A9SCU 895clk_domain=system.clk_domain 896eventq_index=0 897pio_addr=520093696 898pio_latency=100000 --- 38 unchanged lines hidden (view full) --- 937ClassCode=1 938Command=1 939DeviceID=28945 940ExpansionROM=0 941HeaderType=0 942InterruptLine=31 943InterruptPin=1 944LatencyTimer=0 |
| 945LegacyIOBase=0 |
|
| 952MSICAPBaseOffset=0 953MSICAPCapId=0 954MSICAPMaskBits=0 955MSICAPMsgAddr=0 956MSICAPMsgCtrl=0 957MSICAPMsgData=0 958MSICAPMsgUpperAddr=0 959MSICAPNextCapability=0 --- 68 unchanged lines hidden (view full) --- 1028clk_domain=system.clk_domain 1029eventq_index=0 1030ignore_access=false 1031pio_addr=268632064 1032pio_latency=100000 1033system=system 1034pio=system.iobus.master[9] 1035 | 946MSICAPBaseOffset=0 947MSICAPCapId=0 948MSICAPMaskBits=0 949MSICAPMsgAddr=0 950MSICAPMsgCtrl=0 951MSICAPMsgData=0 952MSICAPMsgUpperAddr=0 953MSICAPNextCapability=0 --- 68 unchanged lines hidden (view full) --- 1022clk_domain=system.clk_domain 1023eventq_index=0 1024ignore_access=false 1025pio_addr=268632064 1026pio_latency=100000 1027system=system 1028pio=system.iobus.master[9] 1029 |
| 1030[system.realview.energy_ctrl] 1031type=EnergyCtrl 1032clk_domain=system.clk_domain 1033dvfs_handler=system.dvfs_handler 1034eventq_index=0 1035pio_addr=268496896 1036pio_latency=100000 1037system=system 1038pio=system.iobus.master[25] 1039 |
|
| 1036[system.realview.flash_fake] 1037type=IsaFake 1038clk_domain=system.clk_domain 1039eventq_index=0 1040fake_mem=true 1041pio_addr=1073741824 1042pio_latency=100000 1043pio_size=536870912 --- 321 unchanged lines hidden --- | 1040[system.realview.flash_fake] 1041type=IsaFake 1042clk_domain=system.clk_domain 1043eventq_index=0 1044fake_mem=true 1045pio_addr=1073741824 1046pio_latency=100000 1047pio_size=536870912 --- 321 unchanged lines hidden --- |