11c11
< children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
---
> children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
15c15
< clock=1
---
> clock=1000
17a18
> enable_context_switch_stats_dump=false
26d26
< midr_regval=890224640
42c42
< clock=1
---
> clock=1000
72c72
< children=dcache dtb fuPool icache interrupts itb tracer
---
> children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
119a120
> isa=system.cpu.isa
171c172
< clock=1
---
> clock=500
174c175
< hit_latency=1000
---
> hit_latency=2
182c183
< response_latency=1000
---
> response_latency=2
191c192
< mem_side=system.toL2Bus.slave[1]
---
> mem_side=system.cpu.toL2Bus.slave[1]
201c202
< clock=1
---
> clock=500
204c205
< port=system.toL2Bus.slave[3]
---
> port=system.cpu.toL2Bus.slave[3]
474c475
< clock=1
---
> clock=500
477c478
< hit_latency=1000
---
> hit_latency=2
485c486
< response_latency=1000
---
> response_latency=2
494c495
< mem_side=system.toL2Bus.slave[0]
---
> mem_side=system.cpu.toL2Bus.slave[0]
498a500,516
> [system.cpu.isa]
> type=ArmISA
> fpsid=1090793632
> id_isar0=34607377
> id_isar1=34677009
> id_isar2=555950401
> id_isar3=17899825
> id_isar4=268501314
> id_isar5=0
> id_mmfr0=3
> id_mmfr1=0
> id_mmfr2=19070976
> id_mmfr3=4027589137
> id_pfr0=49
> id_pfr1=1
> midr=890224640
>
507c525
< clock=1
---
> clock=500
510c528
< port=system.toL2Bus.slave[2]
---
> port=system.cpu.toL2Bus.slave[2]
511a530,566
> [system.cpu.l2cache]
> type=BaseCache
> addr_ranges=0:18446744073709551615
> assoc=8
> block_size=64
> clock=500
> forward_snoops=true
> hash_delay=1
> hit_latency=20
> is_top_level=false
> max_miss_count=0
> mshrs=20
> prefetch_on_access=false
> prefetcher=Null
> prioritizeRequests=false
> repl=Null
> response_latency=20
> size=4194304
> subblock_size=0
> system=system
> tgts_per_mshr=12
> trace_addr=0
> two_queue=false
> write_buffers=8
> cpu_side=system.cpu.toL2Bus.master[0]
> mem_side=system.membus.slave[2]
>
> [system.cpu.toL2Bus]
> type=CoherentBus
> block_size=64
> clock=500
> header_cycles=1
> use_default_range=false
> width=32
> master=system.cpu.l2cache.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
>
534c589
< clock=1
---
> clock=1000
537,538c592,593
< hit_latency=50000
< is_top_level=false
---
> hit_latency=50
> is_top_level=true
545c600
< response_latency=50000
---
> response_latency=50
556,582d610
< [system.l2c]
< type=BaseCache
< addr_ranges=0:18446744073709551615
< assoc=8
< block_size=64
< clock=1
< forward_snoops=true
< hash_delay=1
< hit_latency=10000
< is_top_level=false
< max_miss_count=0
< mshrs=92
< prefetch_on_access=false
< prefetcher=Null
< prioritizeRequests=false
< repl=Null
< response_latency=10000
< size=4194304
< subblock_size=0
< system=system
< tgts_per_mshr=16
< trace_addr=0
< two_queue=false
< write_buffers=8
< cpu_side=system.toL2Bus.master[0]
< mem_side=system.membus.slave[2]
<
593c621
< slave=system.system_port system.iocache.mem_side system.l2c.mem_side
---
> slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
597c625
< clock=1
---
> clock=1000
613,615c641,644
< type=SimpleMemory
< bandwidth=73.000000
< clock=1
---
> type=SimpleDRAM
> addr_mapping=openmap
> banks_per_rank=8
> clock=1000
618,619c647,648
< latency=30000
< latency_var=0
---
> lines_per_rowbuffer=64
> mem_sched_policy=fcfs
620a650
> page_policy=open
621a652,662
> ranks_per_channel=2
> read_buffer_size=32
> tBURST=4000
> tCL=14000
> tRCD=14000
> tREFI=7800000
> tRFC=300000
> tRP=14000
> tWTR=1000
> write_buffer_size=32
> write_thresh_perc=70
636c677
< clock=1
---
> clock=1000
645c686
< clock=1
---
> clock=1000
692c733
< clock=1
---
> clock=1000
723c764
< clock=1
---
> clock=1000
732c773
< clock=1
---
> clock=1000
749c790
< clock=1
---
> clock=1000
763c804
< clock=1
---
> clock=1000
773c814
< clock=1
---
> clock=1000
783c824
< clock=1
---
> clock=1000
793c834
< clock=1
---
> clock=1000
807c848
< clock=1
---
> clock=1000
820c861
< clock=1
---
> clock=1000
849c890
< clock=1
---
> clock=1000
859c900
< clock=1
---
> clock=1000
871c912
< clock=1
---
> clock=1000
883c924
< clock=1
---
> clock=1000
896c937
< clock=1
---
> clock=1000
906c947
< clock=1
---
> clock=1000
916c957
< clock=1
---
> clock=1000
926c967
< clock=1
---
> clock=1000
936c977
< clock=1
---
> clock=1000
950c991
< clock=1
---
> clock=1000
963c1004
< clock=1
---
> clock=1000
978c1019
< clock=1
---
> clock=1000
988c1029
< clock=1
---
> clock=1000
998c1039
< clock=1
---
> clock=1000
1008c1049
< clock=1
---
> clock=1000
1022,1031d1062
< [system.toL2Bus]
< type=CoherentBus
< block_size=64
< clock=1000
< header_cycles=1
< use_default_range=false
< width=8
< master=system.l2c.cpu_side
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
<