Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

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config.ini (9378:36ed6d4654bb)	config.ini (9449:56610ab73040)
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver 12atags_addr=256	1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver 12atags_addr=256
13boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm	13boot_loader=/gem5/dist/binaries/boot.arm
14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename= 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0	14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename= 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0
22kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8	22kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing	23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing
	26mem_ranges=0:134217727
26memories=system.physmem system.realview.nvmem	27memories=system.physmem system.realview.nvmem
27midr_regval=890224640
28multi_proc=true 29num_work_ids=16 30readfile=tests/halt.sh 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clock=1000 44delay=50000 45ranges=268435456:520093695 1073741824:1610612735 46req_size=16 47resp_size=16 48master=system.iobus.slave[0] 49slave=system.membus.master[0] 50 51[system.cf0] 52type=IdeDisk 53children=image 54delay=1000000 55driveID=master 56image=system.cf0.image 57 58[system.cf0.image] 59type=CowDiskImage 60children=child 61child=system.cf0.image.child 62image_file= 63read_only=false 64table_size=65536 65 66[system.cf0.image.child] 67type=RawDiskImage	28multi_proc=true 29num_work_ids=16 30readfile=tests/halt.sh 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clock=1000 44delay=50000 45ranges=268435456:520093695 1073741824:1610612735 46req_size=16 47resp_size=16 48master=system.iobus.slave[0] 49slave=system.membus.master[0] 50 51[system.cf0] 52type=IdeDisk 53children=image 54delay=1000000 55driveID=master 56image=system.cf0.image 57 58[system.cf0.image] 59type=CowDiskImage 60children=child 61child=system.cf0.image.child 62image_file= 63read_only=false 64table_size=65536 65 66[system.cf0.image.child] 67type=RawDiskImage
68image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img	68image_file=/gem5/dist/disks/linux-arm-ael.img
69read_only=true 70 71[system.cpu] 72type=DerivO3CPU	69read_only=true 70 71[system.cpu] 72type=DerivO3CPU
73children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer	73children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
74BTBEntries=4096 75BTBTagSize=16 76LFSTSize=1024 77LQEntries=32 78LSQCheckLoads=true 79LSQDepCheckShift=4 80RASSize=16 81SQEntries=32 82SSITSize=1024 83activity=0 84backComSize=5 85cachePorts=200 86checker=Null 87choiceCtrBits=2 88choicePredictorSize=8192 89clock=500 90commitToDecodeDelay=1 91commitToFetchDelay=1 92commitToIEWDelay=1 93commitToRenameDelay=1 94commitWidth=8 95cpu_id=0 96decodeToFetchDelay=1 97decodeToRenameDelay=1 98decodeWidth=8	74BTBEntries=4096 75BTBTagSize=16 76LFSTSize=1024 77LQEntries=32 78LSQCheckLoads=true 79LSQDepCheckShift=4 80RASSize=16 81SQEntries=32 82SSITSize=1024 83activity=0 84backComSize=5 85cachePorts=200 86checker=Null 87choiceCtrBits=2 88choicePredictorSize=8192 89clock=500 90commitToDecodeDelay=1 91commitToFetchDelay=1 92commitToIEWDelay=1 93commitToRenameDelay=1 94commitWidth=8 95cpu_id=0 96decodeToFetchDelay=1 97decodeToRenameDelay=1 98decodeWidth=8
99defer_registration=false
100dispatchWidth=8 101do_checkpoint_insts=true 102do_quiesce=true 103do_statistics_insts=true 104dtb=system.cpu.dtb 105fetchToDecodeDelay=1 106fetchTrapLatency=1 107fetchWidth=8 108forwardComSize=5 109fuPool=system.cpu.fuPool 110function_trace=false 111function_trace_start=0 112globalCtrBits=2 113globalHistoryBits=13 114globalPredictorSize=8192 115iewToCommitDelay=1 116iewToDecodeDelay=1 117iewToFetchDelay=1 118iewToRenameDelay=1 119instShiftAmt=2 120interrupts=system.cpu.interrupts	99dispatchWidth=8 100do_checkpoint_insts=true 101do_quiesce=true 102do_statistics_insts=true 103dtb=system.cpu.dtb 104fetchToDecodeDelay=1 105fetchTrapLatency=1 106fetchWidth=8 107forwardComSize=5 108fuPool=system.cpu.fuPool 109function_trace=false 110function_trace_start=0 111globalCtrBits=2 112globalHistoryBits=13 113globalPredictorSize=8192 114iewToCommitDelay=1 115iewToDecodeDelay=1 116iewToFetchDelay=1 117iewToRenameDelay=1 118instShiftAmt=2 119interrupts=system.cpu.interrupts
	120isa=system.cpu.isa
121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu.itb 124localCtrBits=2 125localHistoryBits=11 126localHistoryTableSize=2048 127localPredictorSize=2048 128max_insts_all_threads=0 129max_insts_any_thread=0 130max_loads_all_threads=0 131max_loads_any_thread=0 132needsTSO=false 133numIQEntries=64 134numPhysFloatRegs=256 135numPhysIntRegs=256 136numROBEntries=192 137numRobs=1 138numThreads=1 139predType=tournament 140profile=0 141progress_interval=0 142renameToDecodeDelay=1 143renameToFetchDelay=1 144renameToIEWDelay=2 145renameToROBDelay=1 146renameWidth=8 147smtCommitPolicy=RoundRobin 148smtFetchPolicy=SingleThread 149smtIQPolicy=Partitioned 150smtIQThreshold=100 151smtLSQPolicy=Partitioned 152smtLSQThreshold=100 153smtNumFetchingThreads=1 154smtROBPolicy=Partitioned 155smtROBThreshold=100 156squashWidth=8 157store_set_clear_period=250000	121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu.itb 124localCtrBits=2 125localHistoryBits=11 126localHistoryTableSize=2048 127localPredictorSize=2048 128max_insts_all_threads=0 129max_insts_any_thread=0 130max_loads_all_threads=0 131max_loads_any_thread=0 132needsTSO=false 133numIQEntries=64 134numPhysFloatRegs=256 135numPhysIntRegs=256 136numROBEntries=192 137numRobs=1 138numThreads=1 139predType=tournament 140profile=0 141progress_interval=0 142renameToDecodeDelay=1 143renameToFetchDelay=1 144renameToIEWDelay=2 145renameToROBDelay=1 146renameWidth=8 147smtCommitPolicy=RoundRobin 148smtFetchPolicy=SingleThread 149smtIQPolicy=Partitioned 150smtIQThreshold=100 151smtLSQPolicy=Partitioned 152smtLSQThreshold=100 153smtNumFetchingThreads=1 154smtROBPolicy=Partitioned 155smtROBThreshold=100 156squashWidth=8 157store_set_clear_period=250000
	158switched_out=false
158system=system 159tracer=system.cpu.tracer 160trapLatency=13 161wbDepth=1 162wbWidth=8 163workload= 164dcache_port=system.cpu.dcache.cpu_side 165icache_port=system.cpu.icache.cpu_side 166 167[system.cpu.dcache] 168type=BaseCache 169addr_ranges=0:18446744073709551615 170assoc=4 171block_size=64 172clock=500 173forward_snoops=true	159system=system 160tracer=system.cpu.tracer 161trapLatency=13 162wbDepth=1 163wbWidth=8 164workload= 165dcache_port=system.cpu.dcache.cpu_side 166icache_port=system.cpu.icache.cpu_side 167 168[system.cpu.dcache] 169type=BaseCache 170addr_ranges=0:18446744073709551615 171assoc=4 172block_size=64 173clock=500 174forward_snoops=true
174hash_delay=1
175hit_latency=2 176is_top_level=true 177max_miss_count=0 178mshrs=4 179prefetch_on_access=false 180prefetcher=Null	175hit_latency=2 176is_top_level=true 177max_miss_count=0 178mshrs=4 179prefetch_on_access=false 180prefetcher=Null
181prioritizeRequests=false 182repl=Null
183response_latency=2 184size=32768	181response_latency=2 182size=32768
185subblock_size=0
186system=system 187tgts_per_mshr=20	183system=system 184tgts_per_mshr=20
188trace_addr=0
189two_queue=false 190write_buffers=8 191cpu_side=system.cpu.dcache_port 192mem_side=system.cpu.toL2Bus.slave[1] 193 194[system.cpu.dtb] 195type=ArmTLB 196children=walker 197size=64 198walker=system.cpu.dtb.walker 199 200[system.cpu.dtb.walker] 201type=ArmTableWalker 202clock=500 203num_squash_per_cycle=2 204sys=system 205port=system.cpu.toL2Bus.slave[3] 206 207[system.cpu.fuPool] 208type=FUPool 209children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 210FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 211 212[system.cpu.fuPool.FUList0] 213type=FUDesc 214children=opList 215count=6 216opList=system.cpu.fuPool.FUList0.opList 217 218[system.cpu.fuPool.FUList0.opList] 219type=OpDesc 220issueLat=1 221opClass=IntAlu 222opLat=1 223 224[system.cpu.fuPool.FUList1] 225type=FUDesc 226children=opList0 opList1 227count=2 228opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 229 230[system.cpu.fuPool.FUList1.opList0] 231type=OpDesc 232issueLat=1 233opClass=IntMult 234opLat=3 235 236[system.cpu.fuPool.FUList1.opList1] 237type=OpDesc 238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4 246opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 247 248[system.cpu.fuPool.FUList2.opList0] 249type=OpDesc 250issueLat=1 251opClass=FloatAdd 252opLat=2 253 254[system.cpu.fuPool.FUList2.opList1] 255type=OpDesc 256issueLat=1 257opClass=FloatCmp 258opLat=2 259 260[system.cpu.fuPool.FUList2.opList2] 261type=OpDesc 262issueLat=1 263opClass=FloatCvt 264opLat=2 265 266[system.cpu.fuPool.FUList3] 267type=FUDesc 268children=opList0 opList1 opList2 269count=2 270opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 271 272[system.cpu.fuPool.FUList3.opList0] 273type=OpDesc 274issueLat=1 275opClass=FloatMult 276opLat=4 277 278[system.cpu.fuPool.FUList3.opList1] 279type=OpDesc 280issueLat=12 281opClass=FloatDiv 282opLat=12 283 284[system.cpu.fuPool.FUList3.opList2] 285type=OpDesc 286issueLat=24 287opClass=FloatSqrt 288opLat=24 289 290[system.cpu.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294opList=system.cpu.fuPool.FUList4.opList 295 296[system.cpu.fuPool.FUList4.opList] 297type=OpDesc 298issueLat=1 299opClass=MemRead 300opLat=1 301 302[system.cpu.fuPool.FUList5] 303type=FUDesc 304children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 305count=4 306opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 307 308[system.cpu.fuPool.FUList5.opList00] 309type=OpDesc 310issueLat=1 311opClass=SimdAdd 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList01] 315type=OpDesc 316issueLat=1 317opClass=SimdAddAcc 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList02] 321type=OpDesc 322issueLat=1 323opClass=SimdAlu 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList03] 327type=OpDesc 328issueLat=1 329opClass=SimdCmp 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList04] 333type=OpDesc 334issueLat=1 335opClass=SimdCvt 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList05] 339type=OpDesc 340issueLat=1 341opClass=SimdMisc 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList06] 345type=OpDesc 346issueLat=1 347opClass=SimdMult 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList07] 351type=OpDesc 352issueLat=1 353opClass=SimdMultAcc 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList08] 357type=OpDesc 358issueLat=1 359opClass=SimdShift 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList09] 363type=OpDesc 364issueLat=1 365opClass=SimdShiftAcc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList10] 369type=OpDesc 370issueLat=1 371opClass=SimdSqrt 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList11] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatAdd 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList12] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatAlu 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList13] 387type=OpDesc 388issueLat=1 389opClass=SimdFloatCmp 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList14] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatCvt 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList15] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatDiv 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList16] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatMisc 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList17] 411type=OpDesc 412issueLat=1 413opClass=SimdFloatMult 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList18] 417type=OpDesc 418issueLat=1 419opClass=SimdFloatMultAcc 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList19] 423type=OpDesc 424issueLat=1 425opClass=SimdFloatSqrt 426opLat=1 427 428[system.cpu.fuPool.FUList6] 429type=FUDesc 430children=opList 431count=0 432opList=system.cpu.fuPool.FUList6.opList 433 434[system.cpu.fuPool.FUList6.opList] 435type=OpDesc 436issueLat=1 437opClass=MemWrite 438opLat=1 439 440[system.cpu.fuPool.FUList7] 441type=FUDesc 442children=opList0 opList1 443count=4 444opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 445 446[system.cpu.fuPool.FUList7.opList0] 447type=OpDesc 448issueLat=1 449opClass=MemRead 450opLat=1 451 452[system.cpu.fuPool.FUList7.opList1] 453type=OpDesc 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu.fuPool.FUList8] 459type=FUDesc 460children=opList 461count=1 462opList=system.cpu.fuPool.FUList8.opList 463 464[system.cpu.fuPool.FUList8.opList] 465type=OpDesc 466issueLat=3 467opClass=IprAccess 468opLat=3 469 470[system.cpu.icache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=1 474block_size=64 475clock=500 476forward_snoops=true	185two_queue=false 186write_buffers=8 187cpu_side=system.cpu.dcache_port 188mem_side=system.cpu.toL2Bus.slave[1] 189 190[system.cpu.dtb] 191type=ArmTLB 192children=walker 193size=64 194walker=system.cpu.dtb.walker 195 196[system.cpu.dtb.walker] 197type=ArmTableWalker 198clock=500 199num_squash_per_cycle=2 200sys=system 201port=system.cpu.toL2Bus.slave[3] 202 203[system.cpu.fuPool] 204type=FUPool 205children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 206FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 207 208[system.cpu.fuPool.FUList0] 209type=FUDesc 210children=opList 211count=6 212opList=system.cpu.fuPool.FUList0.opList 213 214[system.cpu.fuPool.FUList0.opList] 215type=OpDesc 216issueLat=1 217opClass=IntAlu 218opLat=1 219 220[system.cpu.fuPool.FUList1] 221type=FUDesc 222children=opList0 opList1 223count=2 224opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 225 226[system.cpu.fuPool.FUList1.opList0] 227type=OpDesc 228issueLat=1 229opClass=IntMult 230opLat=3 231 232[system.cpu.fuPool.FUList1.opList1] 233type=OpDesc 234issueLat=19 235opClass=IntDiv 236opLat=20 237 238[system.cpu.fuPool.FUList2] 239type=FUDesc 240children=opList0 opList1 opList2 241count=4 242opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 243 244[system.cpu.fuPool.FUList2.opList0] 245type=OpDesc 246issueLat=1 247opClass=FloatAdd 248opLat=2 249 250[system.cpu.fuPool.FUList2.opList1] 251type=OpDesc 252issueLat=1 253opClass=FloatCmp 254opLat=2 255 256[system.cpu.fuPool.FUList2.opList2] 257type=OpDesc 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 267 268[system.cpu.fuPool.FUList3.opList0] 269type=OpDesc 270issueLat=1 271opClass=FloatMult 272opLat=4 273 274[system.cpu.fuPool.FUList3.opList1] 275type=OpDesc 276issueLat=12 277opClass=FloatDiv 278opLat=12 279 280[system.cpu.fuPool.FUList3.opList2] 281type=OpDesc 282issueLat=24 283opClass=FloatSqrt 284opLat=24 285 286[system.cpu.fuPool.FUList4] 287type=FUDesc 288children=opList 289count=0 290opList=system.cpu.fuPool.FUList4.opList 291 292[system.cpu.fuPool.FUList4.opList] 293type=OpDesc 294issueLat=1 295opClass=MemRead 296opLat=1 297 298[system.cpu.fuPool.FUList5] 299type=FUDesc 300children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 301count=4 302opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 303 304[system.cpu.fuPool.FUList5.opList00] 305type=OpDesc 306issueLat=1 307opClass=SimdAdd 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList01] 311type=OpDesc 312issueLat=1 313opClass=SimdAddAcc 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList02] 317type=OpDesc 318issueLat=1 319opClass=SimdAlu 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList03] 323type=OpDesc 324issueLat=1 325opClass=SimdCmp 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList04] 329type=OpDesc 330issueLat=1 331opClass=SimdCvt 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList05] 335type=OpDesc 336issueLat=1 337opClass=SimdMisc 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList06] 341type=OpDesc 342issueLat=1 343opClass=SimdMult 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList07] 347type=OpDesc 348issueLat=1 349opClass=SimdMultAcc 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList08] 353type=OpDesc 354issueLat=1 355opClass=SimdShift 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList09] 359type=OpDesc 360issueLat=1 361opClass=SimdShiftAcc 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList10] 365type=OpDesc 366issueLat=1 367opClass=SimdSqrt 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList11] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatAdd 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList12] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatAlu 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList13] 383type=OpDesc 384issueLat=1 385opClass=SimdFloatCmp 386opLat=1 387 388[system.cpu.fuPool.FUList5.opList14] 389type=OpDesc 390issueLat=1 391opClass=SimdFloatCvt 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList15] 395type=OpDesc 396issueLat=1 397opClass=SimdFloatDiv 398opLat=1 399 400[system.cpu.fuPool.FUList5.opList16] 401type=OpDesc 402issueLat=1 403opClass=SimdFloatMisc 404opLat=1 405 406[system.cpu.fuPool.FUList5.opList17] 407type=OpDesc 408issueLat=1 409opClass=SimdFloatMult 410opLat=1 411 412[system.cpu.fuPool.FUList5.opList18] 413type=OpDesc 414issueLat=1 415opClass=SimdFloatMultAcc 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList19] 419type=OpDesc 420issueLat=1 421opClass=SimdFloatSqrt 422opLat=1 423 424[system.cpu.fuPool.FUList6] 425type=FUDesc 426children=opList 427count=0 428opList=system.cpu.fuPool.FUList6.opList 429 430[system.cpu.fuPool.FUList6.opList] 431type=OpDesc 432issueLat=1 433opClass=MemWrite 434opLat=1 435 436[system.cpu.fuPool.FUList7] 437type=FUDesc 438children=opList0 opList1 439count=4 440opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 441 442[system.cpu.fuPool.FUList7.opList0] 443type=OpDesc 444issueLat=1 445opClass=MemRead 446opLat=1 447 448[system.cpu.fuPool.FUList7.opList1] 449type=OpDesc 450issueLat=1 451opClass=MemWrite 452opLat=1 453 454[system.cpu.fuPool.FUList8] 455type=FUDesc 456children=opList 457count=1 458opList=system.cpu.fuPool.FUList8.opList 459 460[system.cpu.fuPool.FUList8.opList] 461type=OpDesc 462issueLat=3 463opClass=IprAccess 464opLat=3 465 466[system.cpu.icache] 467type=BaseCache 468addr_ranges=0:18446744073709551615 469assoc=1 470block_size=64 471clock=500 472forward_snoops=true
477hash_delay=1
478hit_latency=2 479is_top_level=true 480max_miss_count=0 481mshrs=4 482prefetch_on_access=false 483prefetcher=Null	473hit_latency=2 474is_top_level=true 475max_miss_count=0 476mshrs=4 477prefetch_on_access=false 478prefetcher=Null
484prioritizeRequests=false 485repl=Null
486response_latency=2 487size=32768	479response_latency=2 480size=32768
488subblock_size=0
489system=system 490tgts_per_mshr=20	481system=system 482tgts_per_mshr=20
491trace_addr=0
492two_queue=false 493write_buffers=8 494cpu_side=system.cpu.icache_port 495mem_side=system.cpu.toL2Bus.slave[0] 496 497[system.cpu.interrupts] 498type=ArmInterrupts 499	483two_queue=false 484write_buffers=8 485cpu_side=system.cpu.icache_port 486mem_side=system.cpu.toL2Bus.slave[0] 487 488[system.cpu.interrupts] 489type=ArmInterrupts 490
	491[system.cpu.isa] 492type=ArmISA 493fpsid=1090793632 494id_isar0=34607377 495id_isar1=34677009 496id_isar2=555950401 497id_isar3=17899825 498id_isar4=268501314 499id_isar5=0 500id_mmfr0=3 501id_mmfr1=0 502id_mmfr2=19070976 503id_mmfr3=4027589137 504id_pfr0=49 505id_pfr1=1 506midr=890224640 507
500[system.cpu.itb] 501type=ArmTLB 502children=walker 503size=64 504walker=system.cpu.itb.walker 505 506[system.cpu.itb.walker] 507type=ArmTableWalker 508clock=500 509num_squash_per_cycle=2 510sys=system 511port=system.cpu.toL2Bus.slave[2] 512 513[system.cpu.l2cache] 514type=BaseCache 515addr_ranges=0:18446744073709551615 516assoc=8 517block_size=64 518clock=500 519forward_snoops=true	508[system.cpu.itb] 509type=ArmTLB 510children=walker 511size=64 512walker=system.cpu.itb.walker 513 514[system.cpu.itb.walker] 515type=ArmTableWalker 516clock=500 517num_squash_per_cycle=2 518sys=system 519port=system.cpu.toL2Bus.slave[2] 520 521[system.cpu.l2cache] 522type=BaseCache 523addr_ranges=0:18446744073709551615 524assoc=8 525block_size=64 526clock=500 527forward_snoops=true
520hash_delay=1
521hit_latency=20 522is_top_level=false 523max_miss_count=0 524mshrs=20 525prefetch_on_access=false 526prefetcher=Null	528hit_latency=20 529is_top_level=false 530max_miss_count=0 531mshrs=20 532prefetch_on_access=false 533prefetcher=Null
527prioritizeRequests=false 528repl=Null
529response_latency=20 530size=4194304	534response_latency=20 535size=4194304
531subblock_size=0
532system=system 533tgts_per_mshr=12	536system=system 537tgts_per_mshr=12
534trace_addr=0
535two_queue=false 536write_buffers=8 537cpu_side=system.cpu.toL2Bus.master[0]	538two_queue=false 539write_buffers=8 540cpu_side=system.cpu.toL2Bus.master[0]
538mem_side=system.membus.slave[2]	541mem_side=system.membus.slave[1]
539 540[system.cpu.toL2Bus] 541type=CoherentBus 542block_size=64 543clock=500 544header_cycles=1 545use_default_range=false 546width=32 547master=system.cpu.l2cache.cpu_side 548slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 549 550[system.cpu.tracer] 551type=ExeTracer 552 553[system.intrctrl] 554type=IntrControl 555sys=system 556 557[system.iobus] 558type=NoncoherentBus 559block_size=64 560clock=1000 561header_cycles=1 562use_default_range=false 563width=8 564master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 565slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 566 567[system.iocache] 568type=BaseCache	542 543[system.cpu.toL2Bus] 544type=CoherentBus 545block_size=64 546clock=500 547header_cycles=1 548use_default_range=false 549width=32 550master=system.cpu.l2cache.cpu_side 551slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 552 553[system.cpu.tracer] 554type=ExeTracer 555 556[system.intrctrl] 557type=IntrControl 558sys=system 559 560[system.iobus] 561type=NoncoherentBus 562block_size=64 563clock=1000 564header_cycles=1 565use_default_range=false 566width=8 567master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 568slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 569 570[system.iocache] 571type=BaseCache
569addr_ranges=0:268435455	572addr_ranges=0:134217727
570assoc=8 571block_size=64 572clock=1000 573forward_snoops=false	573assoc=8 574block_size=64 575clock=1000 576forward_snoops=false
574hash_delay=1
575hit_latency=50 576is_top_level=true 577max_miss_count=0 578mshrs=20 579prefetch_on_access=false 580prefetcher=Null	577hit_latency=50 578is_top_level=true 579max_miss_count=0 580mshrs=20 581prefetch_on_access=false 582prefetcher=Null
581prioritizeRequests=false 582repl=Null
583response_latency=50 584size=1024	583response_latency=50 584size=1024
585subblock_size=0
586system=system 587tgts_per_mshr=12	585system=system 586tgts_per_mshr=12
588trace_addr=0
589two_queue=false 590write_buffers=8 591cpu_side=system.iobus.master[25]	587two_queue=false 588write_buffers=8 589cpu_side=system.iobus.master[25]
592mem_side=system.membus.slave[1]	590mem_side=system.membus.slave[2]
593 594[system.membus] 595type=CoherentBus 596children=badaddr_responder 597block_size=64 598clock=1000 599header_cycles=1 600use_default_range=false 601width=8 602default=system.membus.badaddr_responder.pio 603master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio	591 592[system.membus] 593type=CoherentBus 594children=badaddr_responder 595block_size=64 596clock=1000 597header_cycles=1 598use_default_range=false 599width=8 600default=system.membus.badaddr_responder.pio 601master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
604slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side	602slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
605 606[system.membus.badaddr_responder] 607type=IsaFake 608clock=1000 609fake_mem=false 610pio_addr=0 611pio_latency=100000 612pio_size=8 613ret_bad_addr=true 614ret_data16=65535 615ret_data32=4294967295 616ret_data64=18446744073709551615 617ret_data8=255 618system=system 619update_data=false 620warn_access=warn 621pio=system.membus.default 622 623[system.physmem] 624type=SimpleDRAM 625addr_mapping=openmap 626banks_per_rank=8 627clock=1000 628conf_table_reported=true 629in_addr_map=true 630lines_per_rowbuffer=64 631mem_sched_policy=fcfs 632null=false 633page_policy=open 634range=0:134217727 635ranks_per_channel=2 636read_buffer_size=32 637tBURST=4000 638tCL=14000 639tRCD=14000 640tREFI=7800000 641tRFC=300000 642tRP=14000 643tWTR=1000 644write_buffer_size=32 645write_thresh_perc=70 646zero=false 647port=system.membus.master[2] 648 649[system.realview] 650type=RealView 651children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 652intrctrl=system.intrctrl 653max_mem_size=268435456 654mem_start_addr=0 655pci_cfg_base=0 656system=system 657 658[system.realview.a9scu] 659type=A9SCU 660clock=1000 661pio_addr=520093696 662pio_latency=100000 663system=system 664pio=system.membus.master[5] 665 666[system.realview.aaci_fake] 667type=AmbaFake 668amba_id=0 669clock=1000 670ignore_access=false 671pio_addr=268451840 672pio_latency=100000 673system=system 674pio=system.iobus.master[21] 675 676[system.realview.cf_ctrl] 677type=IdeController 678BAR0=402653184 679BAR0LegacyIO=true 680BAR0Size=16 681BAR1=402653440 682BAR1LegacyIO=true 683BAR1Size=1 684BAR2=1 685BAR2LegacyIO=false 686BAR2Size=8 687BAR3=1 688BAR3LegacyIO=false 689BAR3Size=4 690BAR4=1 691BAR4LegacyIO=false 692BAR4Size=16 693BAR5=1 694BAR5LegacyIO=false 695BAR5Size=0 696BIST=0 697CacheLineSize=0 698CardbusCIS=0 699ClassCode=1 700Command=1 701DeviceID=28945 702ExpansionROM=0 703HeaderType=0 704InterruptLine=31 705InterruptPin=1 706LatencyTimer=0 707MaximumLatency=0 708MinimumGrant=0 709ProgIF=133 710Revision=0 711Status=640 712SubClassCode=1 713SubsystemID=0 714SubsystemVendorID=0 715VendorID=32902 716clock=1000 717config_latency=20000 718ctrl_offset=2 719disks=system.cf0 720io_shift=1 721pci_bus=2 722pci_dev=7 723pci_func=0 724pio_latency=30000 725platform=system.realview 726system=system 727config=system.iobus.master[8] 728dma=system.iobus.slave[2] 729pio=system.iobus.master[7] 730 731[system.realview.clcd] 732type=Pl111 733amba_id=1315089	603 604[system.membus.badaddr_responder] 605type=IsaFake 606clock=1000 607fake_mem=false 608pio_addr=0 609pio_latency=100000 610pio_size=8 611ret_bad_addr=true 612ret_data16=65535 613ret_data32=4294967295 614ret_data64=18446744073709551615 615ret_data8=255 616system=system 617update_data=false 618warn_access=warn 619pio=system.membus.default 620 621[system.physmem] 622type=SimpleDRAM 623addr_mapping=openmap 624banks_per_rank=8 625clock=1000 626conf_table_reported=true 627in_addr_map=true 628lines_per_rowbuffer=64 629mem_sched_policy=fcfs 630null=false 631page_policy=open 632range=0:134217727 633ranks_per_channel=2 634read_buffer_size=32 635tBURST=4000 636tCL=14000 637tRCD=14000 638tREFI=7800000 639tRFC=300000 640tRP=14000 641tWTR=1000 642write_buffer_size=32 643write_thresh_perc=70 644zero=false 645port=system.membus.master[2] 646 647[system.realview] 648type=RealView 649children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 650intrctrl=system.intrctrl 651max_mem_size=268435456 652mem_start_addr=0 653pci_cfg_base=0 654system=system 655 656[system.realview.a9scu] 657type=A9SCU 658clock=1000 659pio_addr=520093696 660pio_latency=100000 661system=system 662pio=system.membus.master[5] 663 664[system.realview.aaci_fake] 665type=AmbaFake 666amba_id=0 667clock=1000 668ignore_access=false 669pio_addr=268451840 670pio_latency=100000 671system=system 672pio=system.iobus.master[21] 673 674[system.realview.cf_ctrl] 675type=IdeController 676BAR0=402653184 677BAR0LegacyIO=true 678BAR0Size=16 679BAR1=402653440 680BAR1LegacyIO=true 681BAR1Size=1 682BAR2=1 683BAR2LegacyIO=false 684BAR2Size=8 685BAR3=1 686BAR3LegacyIO=false 687BAR3Size=4 688BAR4=1 689BAR4LegacyIO=false 690BAR4Size=16 691BAR5=1 692BAR5LegacyIO=false 693BAR5Size=0 694BIST=0 695CacheLineSize=0 696CardbusCIS=0 697ClassCode=1 698Command=1 699DeviceID=28945 700ExpansionROM=0 701HeaderType=0 702InterruptLine=31 703InterruptPin=1 704LatencyTimer=0 705MaximumLatency=0 706MinimumGrant=0 707ProgIF=133 708Revision=0 709Status=640 710SubClassCode=1 711SubsystemID=0 712SubsystemVendorID=0 713VendorID=32902 714clock=1000 715config_latency=20000 716ctrl_offset=2 717disks=system.cf0 718io_shift=1 719pci_bus=2 720pci_dev=7 721pci_func=0 722pio_latency=30000 723platform=system.realview 724system=system 725config=system.iobus.master[8] 726dma=system.iobus.slave[2] 727pio=system.iobus.master[7] 728 729[system.realview.clcd] 730type=Pl111 731amba_id=1315089
734clock=41667	732clock=1000
735gic=system.realview.gic 736int_num=55 737pio_addr=268566528 738pio_latency=10000	733gic=system.realview.gic 734int_num=55 735pio_addr=268566528 736pio_latency=10000
	737pixel_clock=41667
739system=system 740vnc=system.vncserver 741dma=system.iobus.slave[1] 742pio=system.iobus.master[4] 743 744[system.realview.dmac_fake] 745type=AmbaFake 746amba_id=0 747clock=1000 748ignore_access=false 749pio_addr=268632064 750pio_latency=100000 751system=system 752pio=system.iobus.master[9] 753 754[system.realview.flash_fake] 755type=IsaFake 756clock=1000 757fake_mem=true 758pio_addr=1073741824 759pio_latency=100000 760pio_size=536870912 761ret_bad_addr=false 762ret_data16=65535 763ret_data32=4294967295 764ret_data64=18446744073709551615 765ret_data8=255 766system=system 767update_data=false 768warn_access= 769pio=system.iobus.master[24] 770 771[system.realview.gic] 772type=Gic 773clock=1000 774cpu_addr=520093952 775cpu_pio_delay=10000 776dist_addr=520097792 777dist_pio_delay=10000 778int_latency=10000 779it_lines=128 780platform=system.realview 781system=system 782pio=system.membus.master[3] 783 784[system.realview.gpio0_fake] 785type=AmbaFake 786amba_id=0 787clock=1000 788ignore_access=false 789pio_addr=268513280 790pio_latency=100000 791system=system 792pio=system.iobus.master[16] 793 794[system.realview.gpio1_fake] 795type=AmbaFake 796amba_id=0 797clock=1000 798ignore_access=false 799pio_addr=268517376 800pio_latency=100000 801system=system 802pio=system.iobus.master[17] 803 804[system.realview.gpio2_fake] 805type=AmbaFake 806amba_id=0 807clock=1000 808ignore_access=false 809pio_addr=268521472 810pio_latency=100000 811system=system 812pio=system.iobus.master[18] 813 814[system.realview.kmi0] 815type=Pl050 816amba_id=1314896 817clock=1000 818gic=system.realview.gic 819int_delay=1000000 820int_num=52 821is_mouse=false 822pio_addr=268460032 823pio_latency=100000 824system=system 825vnc=system.vncserver 826pio=system.iobus.master[5] 827 828[system.realview.kmi1] 829type=Pl050 830amba_id=1314896 831clock=1000 832gic=system.realview.gic 833int_delay=1000000 834int_num=53 835is_mouse=true 836pio_addr=268464128 837pio_latency=100000 838system=system 839vnc=system.vncserver 840pio=system.iobus.master[6] 841 842[system.realview.l2x0_fake] 843type=IsaFake 844clock=1000 845fake_mem=false 846pio_addr=520101888 847pio_latency=100000 848pio_size=4095 849ret_bad_addr=false 850ret_data16=65535 851ret_data32=4294967295 852ret_data64=18446744073709551615 853ret_data8=255 854system=system 855update_data=false 856warn_access= 857pio=system.membus.master[4] 858 859[system.realview.local_cpu_timer] 860type=CpuLocalTimer 861clock=1000 862gic=system.realview.gic 863int_num_timer=29 864int_num_watchdog=30 865pio_addr=520095232 866pio_latency=100000 867system=system 868pio=system.membus.master[6] 869 870[system.realview.mmc_fake] 871type=AmbaFake 872amba_id=0 873clock=1000 874ignore_access=false 875pio_addr=268455936 876pio_latency=100000 877system=system 878pio=system.iobus.master[22] 879 880[system.realview.nvmem] 881type=SimpleMemory 882bandwidth=73.000000 883clock=1000 884conf_table_reported=false 885in_addr_map=true 886latency=30000 887latency_var=0 888null=false 889range=2147483648:2214592511 890zero=true 891port=system.membus.master[1] 892 893[system.realview.realview_io] 894type=RealViewCtrl 895clock=1000 896idreg=0 897pio_addr=268435456 898pio_latency=100000 899proc_id0=201326592 900proc_id1=201327138 901system=system 902pio=system.iobus.master[1] 903 904[system.realview.rtc] 905type=PL031 906amba_id=3412017 907clock=1000 908gic=system.realview.gic 909int_delay=100000 910int_num=42 911pio_addr=268529664 912pio_latency=100000 913system=system 914time=Thu Jan 1 00:00:00 2009 915pio=system.iobus.master[23] 916 917[system.realview.sci_fake] 918type=AmbaFake 919amba_id=0 920clock=1000 921ignore_access=false 922pio_addr=268492800 923pio_latency=100000 924system=system 925pio=system.iobus.master[20] 926 927[system.realview.smc_fake] 928type=AmbaFake 929amba_id=0 930clock=1000 931ignore_access=false 932pio_addr=269357056 933pio_latency=100000 934system=system 935pio=system.iobus.master[13] 936 937[system.realview.sp810_fake] 938type=AmbaFake 939amba_id=0 940clock=1000 941ignore_access=true 942pio_addr=268439552 943pio_latency=100000 944system=system 945pio=system.iobus.master[14] 946 947[system.realview.ssp_fake] 948type=AmbaFake 949amba_id=0 950clock=1000 951ignore_access=false 952pio_addr=268488704 953pio_latency=100000 954system=system 955pio=system.iobus.master[19] 956 957[system.realview.timer0] 958type=Sp804 959amba_id=1316868 960clock=1000 961clock0=1000000 962clock1=1000000 963gic=system.realview.gic 964int_num0=36 965int_num1=36 966pio_addr=268505088 967pio_latency=100000 968system=system 969pio=system.iobus.master[2] 970 971[system.realview.timer1] 972type=Sp804 973amba_id=1316868 974clock=1000 975clock0=1000000 976clock1=1000000 977gic=system.realview.gic 978int_num0=37 979int_num1=37 980pio_addr=268509184 981pio_latency=100000 982system=system 983pio=system.iobus.master[3] 984 985[system.realview.uart] 986type=Pl011 987clock=1000 988end_on_eot=false 989gic=system.realview.gic 990int_delay=100000 991int_num=44 992pio_addr=268472320 993pio_latency=100000 994platform=system.realview 995system=system 996terminal=system.terminal 997pio=system.iobus.master[0] 998 999[system.realview.uart1_fake] 1000type=AmbaFake 1001amba_id=0 1002clock=1000 1003ignore_access=false 1004pio_addr=268476416 1005pio_latency=100000 1006system=system 1007pio=system.iobus.master[10] 1008 1009[system.realview.uart2_fake] 1010type=AmbaFake 1011amba_id=0 1012clock=1000 1013ignore_access=false 1014pio_addr=268480512 1015pio_latency=100000 1016system=system 1017pio=system.iobus.master[11] 1018 1019[system.realview.uart3_fake] 1020type=AmbaFake 1021amba_id=0 1022clock=1000 1023ignore_access=false 1024pio_addr=268484608 1025pio_latency=100000 1026system=system 1027pio=system.iobus.master[12] 1028 1029[system.realview.watchdog_fake] 1030type=AmbaFake 1031amba_id=0 1032clock=1000 1033ignore_access=false 1034pio_addr=268500992 1035pio_latency=100000 1036system=system 1037pio=system.iobus.master[15] 1038 1039[system.terminal] 1040type=Terminal 1041intr_control=system.intrctrl 1042number=0 1043output=true 1044port=3456 1045 1046[system.vncserver] 1047type=VncServer 1048frame_capture=false 1049number=0 1050port=5900 1051	738system=system 739vnc=system.vncserver 740dma=system.iobus.slave[1] 741pio=system.iobus.master[4] 742 743[system.realview.dmac_fake] 744type=AmbaFake 745amba_id=0 746clock=1000 747ignore_access=false 748pio_addr=268632064 749pio_latency=100000 750system=system 751pio=system.iobus.master[9] 752 753[system.realview.flash_fake] 754type=IsaFake 755clock=1000 756fake_mem=true 757pio_addr=1073741824 758pio_latency=100000 759pio_size=536870912 760ret_bad_addr=false 761ret_data16=65535 762ret_data32=4294967295 763ret_data64=18446744073709551615 764ret_data8=255 765system=system 766update_data=false 767warn_access= 768pio=system.iobus.master[24] 769 770[system.realview.gic] 771type=Gic 772clock=1000 773cpu_addr=520093952 774cpu_pio_delay=10000 775dist_addr=520097792 776dist_pio_delay=10000 777int_latency=10000 778it_lines=128 779platform=system.realview 780system=system 781pio=system.membus.master[3] 782 783[system.realview.gpio0_fake] 784type=AmbaFake 785amba_id=0 786clock=1000 787ignore_access=false 788pio_addr=268513280 789pio_latency=100000 790system=system 791pio=system.iobus.master[16] 792 793[system.realview.gpio1_fake] 794type=AmbaFake 795amba_id=0 796clock=1000 797ignore_access=false 798pio_addr=268517376 799pio_latency=100000 800system=system 801pio=system.iobus.master[17] 802 803[system.realview.gpio2_fake] 804type=AmbaFake 805amba_id=0 806clock=1000 807ignore_access=false 808pio_addr=268521472 809pio_latency=100000 810system=system 811pio=system.iobus.master[18] 812 813[system.realview.kmi0] 814type=Pl050 815amba_id=1314896 816clock=1000 817gic=system.realview.gic 818int_delay=1000000 819int_num=52 820is_mouse=false 821pio_addr=268460032 822pio_latency=100000 823system=system 824vnc=system.vncserver 825pio=system.iobus.master[5] 826 827[system.realview.kmi1] 828type=Pl050 829amba_id=1314896 830clock=1000 831gic=system.realview.gic 832int_delay=1000000 833int_num=53 834is_mouse=true 835pio_addr=268464128 836pio_latency=100000 837system=system 838vnc=system.vncserver 839pio=system.iobus.master[6] 840 841[system.realview.l2x0_fake] 842type=IsaFake 843clock=1000 844fake_mem=false 845pio_addr=520101888 846pio_latency=100000 847pio_size=4095 848ret_bad_addr=false 849ret_data16=65535 850ret_data32=4294967295 851ret_data64=18446744073709551615 852ret_data8=255 853system=system 854update_data=false 855warn_access= 856pio=system.membus.master[4] 857 858[system.realview.local_cpu_timer] 859type=CpuLocalTimer 860clock=1000 861gic=system.realview.gic 862int_num_timer=29 863int_num_watchdog=30 864pio_addr=520095232 865pio_latency=100000 866system=system 867pio=system.membus.master[6] 868 869[system.realview.mmc_fake] 870type=AmbaFake 871amba_id=0 872clock=1000 873ignore_access=false 874pio_addr=268455936 875pio_latency=100000 876system=system 877pio=system.iobus.master[22] 878 879[system.realview.nvmem] 880type=SimpleMemory 881bandwidth=73.000000 882clock=1000 883conf_table_reported=false 884in_addr_map=true 885latency=30000 886latency_var=0 887null=false 888range=2147483648:2214592511 889zero=true 890port=system.membus.master[1] 891 892[system.realview.realview_io] 893type=RealViewCtrl 894clock=1000 895idreg=0 896pio_addr=268435456 897pio_latency=100000 898proc_id0=201326592 899proc_id1=201327138 900system=system 901pio=system.iobus.master[1] 902 903[system.realview.rtc] 904type=PL031 905amba_id=3412017 906clock=1000 907gic=system.realview.gic 908int_delay=100000 909int_num=42 910pio_addr=268529664 911pio_latency=100000 912system=system 913time=Thu Jan 1 00:00:00 2009 914pio=system.iobus.master[23] 915 916[system.realview.sci_fake] 917type=AmbaFake 918amba_id=0 919clock=1000 920ignore_access=false 921pio_addr=268492800 922pio_latency=100000 923system=system 924pio=system.iobus.master[20] 925 926[system.realview.smc_fake] 927type=AmbaFake 928amba_id=0 929clock=1000 930ignore_access=false 931pio_addr=269357056 932pio_latency=100000 933system=system 934pio=system.iobus.master[13] 935 936[system.realview.sp810_fake] 937type=AmbaFake 938amba_id=0 939clock=1000 940ignore_access=true 941pio_addr=268439552 942pio_latency=100000 943system=system 944pio=system.iobus.master[14] 945 946[system.realview.ssp_fake] 947type=AmbaFake 948amba_id=0 949clock=1000 950ignore_access=false 951pio_addr=268488704 952pio_latency=100000 953system=system 954pio=system.iobus.master[19] 955 956[system.realview.timer0] 957type=Sp804 958amba_id=1316868 959clock=1000 960clock0=1000000 961clock1=1000000 962gic=system.realview.gic 963int_num0=36 964int_num1=36 965pio_addr=268505088 966pio_latency=100000 967system=system 968pio=system.iobus.master[2] 969 970[system.realview.timer1] 971type=Sp804 972amba_id=1316868 973clock=1000 974clock0=1000000 975clock1=1000000 976gic=system.realview.gic 977int_num0=37 978int_num1=37 979pio_addr=268509184 980pio_latency=100000 981system=system 982pio=system.iobus.master[3] 983 984[system.realview.uart] 985type=Pl011 986clock=1000 987end_on_eot=false 988gic=system.realview.gic 989int_delay=100000 990int_num=44 991pio_addr=268472320 992pio_latency=100000 993platform=system.realview 994system=system 995terminal=system.terminal 996pio=system.iobus.master[0] 997 998[system.realview.uart1_fake] 999type=AmbaFake 1000amba_id=0 1001clock=1000 1002ignore_access=false 1003pio_addr=268476416 1004pio_latency=100000 1005system=system 1006pio=system.iobus.master[10] 1007 1008[system.realview.uart2_fake] 1009type=AmbaFake 1010amba_id=0 1011clock=1000 1012ignore_access=false 1013pio_addr=268480512 1014pio_latency=100000 1015system=system 1016pio=system.iobus.master[11] 1017 1018[system.realview.uart3_fake] 1019type=AmbaFake 1020amba_id=0 1021clock=1000 1022ignore_access=false 1023pio_addr=268484608 1024pio_latency=100000 1025system=system 1026pio=system.iobus.master[12] 1027 1028[system.realview.watchdog_fake] 1029type=AmbaFake 1030amba_id=0 1031clock=1000 1032ignore_access=false 1033pio_addr=268500992 1034pio_latency=100000 1035system=system 1036pio=system.iobus.master[15] 1037 1038[system.terminal] 1039type=Terminal 1040intr_control=system.intrctrl 1041number=0 1042output=true 1043port=3456 1044 1045[system.vncserver] 1046type=VncServer 1047frame_capture=false 1048number=0 1049port=5900 1050