| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.104766 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.104766 # Number of seconds simulated |
| 4sim_ticks 1104765949000 # Number of ticks simulated 5final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1104766159000 # Number of ticks simulated 5final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 62642 # Simulator instruction rate (inst/s) 8host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1123477436 # Simulator tick rate (ticks/s) 10host_mem_usage 430892 # Number of bytes of host memory used 11host_seconds 983.35 # Real time elapsed on the host 12sim_insts 61598253 # Number of instructions simulated 13sim_ops 79296895 # Number of ops (including micro ops) simulated | 7host_inst_rate 49697 # Simulator instruction rate (inst/s) 8host_op_rate 63978 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 891289209 # Simulator tick rate (ticks/s) 10host_mem_usage 450492 # Number of bytes of host memory used 11host_seconds 1239.51 # Real time elapsed on the host 12sim_insts 61600257 # Number of instructions simulated 13sim_ops 79301805 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory | 22system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory |
| 23system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory | 23system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory | 29system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory |
| 30system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory | 38system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory |
| 39system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory | 39system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory |
| 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
| 42system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) | 42system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s) |
| 44system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s) |
| 56system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) | 56system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) | 58system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s) |
| 61system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) |
| 63system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s) |
| 69system.physmem.readReqs 6257980 # Number of read requests accepted | 69system.physmem.readReqs 6257980 # Number of read requests accepted |
| 70system.physmem.writeReqs 823531 # Number of write requests accepted | 70system.physmem.writeReqs 823516 # Number of write requests accepted |
| 71system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue | 71system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue |
| 72system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue 73system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM 74system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue 75system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM | 72system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue 73system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM 74system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue 75system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM |
| 76system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side | 76system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side |
| 77system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side 78system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue 79system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one 80system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write 81system.physmem.perBankRdBursts::0 391110 # Per bank write bursts 82system.physmem.perBankRdBursts::1 390863 # Per bank write bursts 83system.physmem.perBankRdBursts::2 386866 # Per bank write bursts 84system.physmem.perBankRdBursts::3 386878 # Per bank write bursts 85system.physmem.perBankRdBursts::4 391778 # Per bank write bursts 86system.physmem.perBankRdBursts::5 391417 # Per bank write bursts 87system.physmem.perBankRdBursts::6 386925 # Per bank write bursts 88system.physmem.perBankRdBursts::7 386783 # Per bank write bursts 89system.physmem.perBankRdBursts::8 391442 # Per bank write bursts 90system.physmem.perBankRdBursts::9 391216 # Per bank write bursts 91system.physmem.perBankRdBursts::10 386574 # Per bank write bursts 92system.physmem.perBankRdBursts::11 385570 # Per bank write bursts 93system.physmem.perBankRdBursts::12 390981 # Per bank write bursts 94system.physmem.perBankRdBursts::13 390596 # Per bank write bursts 95system.physmem.perBankRdBursts::14 386700 # Per bank write bursts 96system.physmem.perBankRdBursts::15 386183 # Per bank write bursts 97system.physmem.perBankWrBursts::0 7188 # Per bank write bursts 98system.physmem.perBankWrBursts::1 7193 # Per bank write bursts 99system.physmem.perBankWrBursts::2 7297 # Per bank write bursts 100system.physmem.perBankWrBursts::3 7231 # Per bank write bursts 101system.physmem.perBankWrBursts::4 7835 # Per bank write bursts 102system.physmem.perBankWrBursts::5 7450 # Per bank write bursts 103system.physmem.perBankWrBursts::6 7370 # Per bank write bursts 104system.physmem.perBankWrBursts::7 7176 # Per bank write bursts 105system.physmem.perBankWrBursts::8 7508 # Per bank write bursts 106system.physmem.perBankWrBursts::9 7517 # Per bank write bursts 107system.physmem.perBankWrBursts::10 6849 # Per bank write bursts 108system.physmem.perBankWrBursts::11 6596 # Per bank write bursts 109system.physmem.perBankWrBursts::12 7160 # Per bank write bursts 110system.physmem.perBankWrBursts::13 6824 # Per bank write bursts 111system.physmem.perBankWrBursts::14 7287 # Per bank write bursts 112system.physmem.perBankWrBursts::15 7185 # Per bank write bursts | 77system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side 78system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue 79system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one 80system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write 81system.physmem.perBankRdBursts::0 391105 # Per bank write bursts 82system.physmem.perBankRdBursts::1 391040 # Per bank write bursts 83system.physmem.perBankRdBursts::2 387008 # Per bank write bursts 84system.physmem.perBankRdBursts::3 386856 # Per bank write bursts 85system.physmem.perBankRdBursts::4 391768 # Per bank write bursts 86system.physmem.perBankRdBursts::5 391357 # Per bank write bursts 87system.physmem.perBankRdBursts::6 387221 # Per bank write bursts 88system.physmem.perBankRdBursts::7 386642 # Per bank write bursts 89system.physmem.perBankRdBursts::8 391438 # Per bank write bursts 90system.physmem.perBankRdBursts::9 391160 # Per bank write bursts 91system.physmem.perBankRdBursts::10 385906 # Per bank write bursts 92system.physmem.perBankRdBursts::11 385319 # Per bank write bursts 93system.physmem.perBankRdBursts::12 390977 # Per bank write bursts 94system.physmem.perBankRdBursts::13 390642 # Per bank write bursts 95system.physmem.perBankRdBursts::14 386557 # Per bank write bursts 96system.physmem.perBankRdBursts::15 386235 # Per bank write bursts 97system.physmem.perBankWrBursts::0 7173 # Per bank write bursts 98system.physmem.perBankWrBursts::1 7194 # Per bank write bursts 99system.physmem.perBankWrBursts::2 7298 # Per bank write bursts 100system.physmem.perBankWrBursts::3 7217 # Per bank write bursts 101system.physmem.perBankWrBursts::4 7815 # Per bank write bursts 102system.physmem.perBankWrBursts::5 7451 # Per bank write bursts 103system.physmem.perBankWrBursts::6 7359 # Per bank write bursts 104system.physmem.perBankWrBursts::7 7185 # Per bank write bursts 105system.physmem.perBankWrBursts::8 7499 # Per bank write bursts 106system.physmem.perBankWrBursts::9 7507 # Per bank write bursts 107system.physmem.perBankWrBursts::10 6838 # Per bank write bursts 108system.physmem.perBankWrBursts::11 6616 # Per bank write bursts 109system.physmem.perBankWrBursts::12 7156 # Per bank write bursts 110system.physmem.perBankWrBursts::13 6834 # Per bank write bursts 111system.physmem.perBankWrBursts::14 7291 # Per bank write bursts 112system.physmem.perBankWrBursts::15 7179 # Per bank write bursts |
| 113system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 114system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 113system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 114system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 115system.physmem.totGap 1104764856500 # Total gap between requests | 115system.physmem.totGap 1104765054500 # Total gap between requests |
| 116system.physmem.readPktSize::0 0 # Read request sizes (log2) 117system.physmem.readPktSize::1 0 # Read request sizes (log2) 118system.physmem.readPktSize::2 105 # Read request sizes (log2) 119system.physmem.readPktSize::3 6094848 # Read request sizes (log2) 120system.physmem.readPktSize::4 0 # Read request sizes (log2) 121system.physmem.readPktSize::5 0 # Read request sizes (log2) 122system.physmem.readPktSize::6 163027 # Read request sizes (log2) 123system.physmem.writePktSize::0 0 # Write request sizes (log2) 124system.physmem.writePktSize::1 0 # Write request sizes (log2) 125system.physmem.writePktSize::2 756836 # Write request sizes (log2) 126system.physmem.writePktSize::3 0 # Write request sizes (log2) 127system.physmem.writePktSize::4 0 # Write request sizes (log2) 128system.physmem.writePktSize::5 0 # Write request sizes (log2) | 116system.physmem.readPktSize::0 0 # Read request sizes (log2) 117system.physmem.readPktSize::1 0 # Read request sizes (log2) 118system.physmem.readPktSize::2 105 # Read request sizes (log2) 119system.physmem.readPktSize::3 6094848 # Read request sizes (log2) 120system.physmem.readPktSize::4 0 # Read request sizes (log2) 121system.physmem.readPktSize::5 0 # Read request sizes (log2) 122system.physmem.readPktSize::6 163027 # Read request sizes (log2) 123system.physmem.writePktSize::0 0 # Write request sizes (log2) 124system.physmem.writePktSize::1 0 # Write request sizes (log2) 125system.physmem.writePktSize::2 756836 # Write request sizes (log2) 126system.physmem.writePktSize::3 0 # Write request sizes (log2) 127system.physmem.writePktSize::4 0 # Write request sizes (log2) 128system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 129system.physmem.writePktSize::6 66695 # Write request sizes (log2) 130system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see | 129system.physmem.writePktSize::6 66680 # Write request sizes (log2) 130system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see |
| 150system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see | 150system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see |
| 151system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see | 151system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see |
| 152system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 152system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see |
| 188system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 188system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 194system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation | 194system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::704-711 556 0.78% 74.50% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-775 523 0.74% 75.24% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::832-839 304 0.43% 75.66% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-903 266 0.38% 76.04% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::960-967 142 0.20% 76.24% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1031 425 0.60% 76.84% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1088-1095 119 0.17% 77.01% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1152-1159 139 0.20% 77.20% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1216-1223 90 0.13% 77.33% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1280-1287 153 0.22% 77.55% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1344-1351 51 0.07% 77.62% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1408-1415 550 0.78% 78.39% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1472-1479 38 0.05% 78.45% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1536-1543 222 0.31% 78.76% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1600-1607 29 0.04% 78.80% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1664-1671 108 0.15% 78.95% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1728-1735 16 0.02% 78.98% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.13% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.17% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1920-1927 57 0.08% 79.25% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1984-1991 19 0.03% 79.28% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2048-2055 237 0.33% 79.61% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2112-2119 12 0.02% 79.63% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2176-2183 45 0.06% 79.69% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2240-2247 10 0.01% 79.71% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2304-2311 54 0.08% 79.78% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2368-2375 16 0.02% 79.81% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2432-2439 29 0.04% 79.85% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2496-2503 2 0.00% 79.85% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2560-2567 27 0.04% 79.89% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2624-2631 2 0.00% 79.89% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2688-2695 17 0.02% 79.92% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2752-2759 5 0.01% 79.92% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2816-2823 28 0.04% 79.96% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2880-2887 7 0.01% 79.97% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2944-2951 22 0.03% 80.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.01% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3072-3079 178 0.25% 80.26% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3136-3143 2 0.00% 80.26% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3200-3207 13 0.02% 80.28% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3264-3271 3 0.00% 80.29% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3328-3335 91 0.13% 80.42% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.42% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3456-3463 20 0.03% 80.45% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.46% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3584-3591 46 0.06% 80.53% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3648-3655 11 0.02% 80.54% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.58% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3776-3783 5 0.01% 80.59% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3840-3847 37 0.05% 80.64% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3904-3911 12 0.02% 80.65% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.68% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4032-4039 12 0.02% 80.70% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4096-4103 201 0.28% 80.98% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4160-4167 6 0.01% 80.99% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4224-4231 17 0.02% 81.01% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4288-4295 8 0.01% 81.02% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4352-4359 92 0.13% 81.15% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4416-4423 19 0.03% 81.18% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4480-4487 20 0.03% 81.21% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4544-4551 13 0.02% 81.23% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4608-4615 19 0.03% 81.25% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4736-4743 6 0.01% 81.27% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.28% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4864-4871 20 0.03% 81.31% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::4992-4999 13 0.02% 81.33% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5056-5063 3 0.00% 81.34% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5120-5127 93 0.13% 81.47% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5184-5191 4 0.01% 81.47% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5248-5255 15 0.02% 81.49% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5312-5319 8 0.01% 81.51% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5376-5383 84 0.12% 81.62% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5440-5447 5 0.01% 81.63% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5504-5511 9 0.01% 81.64% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5568-5575 5 0.01% 81.65% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5632-5639 19 0.03% 81.68% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::5696-5703 2 0.00% 81.68% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::5760-5767 7 0.01% 81.69% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::5824-5831 2 0.00% 81.69% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::5888-5895 138 0.19% 81.89% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::5952-5959 4 0.01% 81.89% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6016-6023 11 0.02% 81.91% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6080-6087 12 0.02% 81.93% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6144-6151 85 0.12% 82.05% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6208-6215 8 0.01% 82.06% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.07% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6336-6343 5 0.01% 82.07% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::6400-6407 96 0.14% 82.21% # Bytes accessed per row activation |
| 297system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation | 298system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation |
| 298system.physmem.bytesPerActivate::6528-6535 11 0.02% 82.23% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::6592-6599 3 0.00% 82.23% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::6656-6663 112 0.16% 82.39% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::6720-6727 9 0.01% 82.40% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::6784-6791 20 0.03% 82.43% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::6848-6855 8 0.01% 82.44% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::6912-6919 28 0.04% 82.48% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.49% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::7040-7047 4 0.01% 82.49% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::7104-7111 2 0.00% 82.50% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::7168-7175 94 0.13% 82.63% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7296-7303 6 0.01% 82.64% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::7360-7367 10 0.01% 82.65% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::7424-7431 92 0.13% 82.78% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::7488-7495 3 0.00% 82.78% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::7552-7559 10 0.01% 82.80% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::7616-7623 3 0.00% 82.80% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::7680-7687 20 0.03% 82.83% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::7744-7751 2 0.00% 82.83% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::7808-7815 2 0.00% 82.84% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::7872-7879 4 0.01% 82.84% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::8000-8007 6 0.01% 82.89% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.90% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::8128-8135 1 0.00% 82.90% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::8192-8199 249 0.35% 83.25% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::8320-8327 1 0.00% 83.26% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::8448-8455 31 0.04% 83.30% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.30% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::8704-8711 16 0.02% 83.32% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::8832-8839 3 0.00% 83.33% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::8896-8903 1 0.00% 83.33% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::8960-8967 75 0.11% 83.43% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.44% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::9216-9223 93 0.13% 83.57% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::9408-9415 1 0.00% 83.57% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::9472-9479 20 0.03% 83.60% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.60% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::9728-9735 102 0.14% 83.74% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.74% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.74% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::9984-9991 14 0.02% 83.76% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.77% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::10240-10247 94 0.13% 83.90% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.90% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::10496-10503 94 0.13% 84.03% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::10752-10759 15 0.02% 84.05% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::10816-10823 1 0.00% 84.06% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::10880-10887 1 0.00% 84.06% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::11008-11015 6 0.01% 84.07% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::11072-11079 2 0.00% 84.07% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.07% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::11264-11271 147 0.21% 84.28% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::11328-11335 3 0.00% 84.28% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.30% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.30% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::11776-11783 1 0.00% 84.31% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::11840-11847 1 0.00% 84.31% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.31% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::12032-12039 79 0.11% 84.42% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.42% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.42% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::12288-12295 162 0.23% 84.65% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.65% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::12544-12551 20 0.03% 84.68% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.68% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::12736-12743 1 0.00% 84.68% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::12800-12807 68 0.10% 84.78% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.78% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::12928-12935 1 0.00% 84.78% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.81% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.81% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::13312-13319 148 0.21% 85.02% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::13440-13447 1 0.00% 85.02% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::13504-13511 1 0.00% 85.02% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::13568-13575 19 0.03% 85.05% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.05% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::13824-13831 18 0.03% 85.07% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::14080-14087 11 0.02% 85.09% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::14336-14343 228 0.32% 85.41% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::14592-14599 27 0.04% 85.45% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::14848-14855 14 0.02% 85.47% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.47% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.47% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::15104-15111 73 0.10% 85.57% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::15168-15175 2 0.00% 85.58% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.58% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::15360-15367 145 0.20% 85.78% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::15616-15623 10 0.01% 85.80% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.80% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::15744-15751 1 0.00% 85.80% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::15872-15879 20 0.03% 85.83% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.83% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::16128-16135 17 0.02% 85.85% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.85% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.85% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::16384-16391 273 0.38% 86.24% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::16448-16455 1 0.00% 86.24% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.24% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.27% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::16704-16711 1 0.00% 86.27% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::16896-16903 21 0.03% 86.30% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::17152-17159 13 0.02% 86.32% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.32% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.32% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::17408-17415 156 0.22% 86.54% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::17472-17479 2 0.00% 86.54% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.54% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::17664-17671 80 0.11% 86.66% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.66% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.66% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::17920-17927 14 0.02% 86.68% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::18176-18183 31 0.04% 86.72% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::18240-18247 2 0.00% 86.73% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.73% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.73% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::18432-18439 219 0.31% 87.04% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::18496-18503 1 0.00% 87.04% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::18688-18695 6 0.01% 87.05% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::18752-18759 1 0.00% 87.05% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::18944-18951 15 0.02% 87.07% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::19008-19015 1 0.00% 87.07% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::19072-19079 4 0.01% 87.08% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::19200-19207 13 0.02% 87.09% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::19264-19271 1 0.00% 87.10% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::19456-19463 140 0.20% 87.29% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.29% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::19648-19655 1 0.00% 87.30% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::19712-19719 17 0.02% 87.32% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::19840-19847 2 0.00% 87.32% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::19968-19975 68 0.10% 87.42% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.42% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::20096-20103 1 0.00% 87.42% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::20224-20231 17 0.02% 87.44% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.45% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.45% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::20480-20487 157 0.22% 87.67% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::20736-20743 82 0.12% 87.78% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::20992-20999 4 0.01% 87.79% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::21248-21255 14 0.02% 87.81% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.81% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::21440-21447 2 0.00% 87.82% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::21504-21511 145 0.20% 88.02% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::21632-21639 1 0.00% 88.02% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::21696-21703 1 0.00% 88.02% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::21760-21767 4 0.01% 88.03% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::21824-21831 1 0.00% 88.03% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::21888-21895 1 0.00% 88.03% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::22016-22023 14 0.02% 88.05% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::22144-22151 2 0.00% 88.05% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::22272-22279 92 0.13% 88.18% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::22400-22407 1 0.00% 88.18% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.19% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::22528-22535 85 0.12% 88.31% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::22784-22791 14 0.02% 88.33% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.33% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::23040-23047 102 0.14% 88.47% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::23104-23111 2 0.00% 88.47% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::23232-23239 1 0.00% 88.48% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.50% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.51% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::23552-23559 91 0.13% 88.63% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.64% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::23744-23751 4 0.01% 88.64% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::23808-23815 75 0.11% 88.75% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::23872-23879 2 0.00% 88.75% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.75% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::24064-24071 21 0.03% 88.78% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::24320-24327 31 0.04% 88.82% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.83% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.83% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::24576-24583 139 0.20% 89.02% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.02% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.02% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::24832-24839 29 0.04% 89.07% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::24896-24903 2 0.00% 89.07% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::25088-25095 18 0.03% 89.09% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::25280-25287 1 0.00% 89.10% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::25344-25351 77 0.11% 89.20% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::25472-25479 2 0.00% 89.21% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::25600-25607 90 0.13% 89.33% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.36% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::26112-26119 104 0.15% 89.51% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::26368-26375 14 0.02% 89.53% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.53% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::26624-26631 87 0.12% 89.65% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::26816-26823 2 0.00% 89.65% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::26880-26887 94 0.13% 89.78% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.80% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.80% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::27264-27271 2 0.00% 89.81% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::27328-27335 1 0.00% 89.81% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::27392-27399 5 0.01% 89.81% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.82% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.82% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::27648-27655 143 0.20% 90.02% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::27776-27783 1 0.00% 90.02% # Bytes accessed per row activation | 299system.physmem.bytesPerActivate::6528-6535 12 0.02% 82.23% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::6592-6599 4 0.01% 82.24% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::6656-6663 80 0.11% 82.35% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::6720-6727 5 0.01% 82.36% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::6784-6791 21 0.03% 82.39% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::6848-6855 6 0.01% 82.39% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::6912-6919 25 0.04% 82.43% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.44% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::7040-7047 3 0.00% 82.44% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::7104-7111 5 0.01% 82.45% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7168-7175 24 0.03% 82.48% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::7296-7303 4 0.01% 82.49% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::7360-7367 11 0.02% 82.50% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::7424-7431 94 0.13% 82.64% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::7488-7495 1 0.00% 82.64% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::7552-7559 12 0.02% 82.65% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::7616-7623 4 0.01% 82.66% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::7680-7687 79 0.11% 82.77% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::7744-7751 3 0.00% 82.77% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::7808-7815 3 0.00% 82.78% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::7872-7879 2 0.00% 82.78% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::7936-7943 32 0.05% 82.83% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::8000-8007 4 0.01% 82.83% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.84% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::8192-8199 266 0.38% 83.22% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.22% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.22% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::8448-8455 25 0.04% 83.26% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::8704-8711 67 0.09% 83.35% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::8768-8775 3 0.00% 83.36% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::8832-8839 1 0.00% 83.36% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::8960-8967 85 0.12% 83.48% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.48% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::9216-9223 19 0.03% 83.51% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.51% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::9344-9351 1 0.00% 83.51% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::9472-9479 13 0.02% 83.53% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::9536-9543 1 0.00% 83.53% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::9728-9735 69 0.10% 83.63% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::9792-9799 1 0.00% 83.63% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::9856-9863 2 0.00% 83.63% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.63% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::9984-9991 92 0.13% 83.76% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.76% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::10240-10247 80 0.11% 83.88% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::10496-10503 87 0.12% 84.00% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::10560-10567 1 0.00% 84.00% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::10624-10631 2 0.00% 84.00% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::10688-10695 1 0.00% 84.01% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::10752-10759 16 0.02% 84.03% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::11008-11015 75 0.11% 84.13% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.13% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::11264-11271 80 0.11% 84.25% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::11328-11335 2 0.00% 84.25% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.25% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.25% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.27% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::11776-11783 10 0.01% 84.29% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::12032-12039 70 0.10% 84.39% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.39% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.39% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.39% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::12288-12295 175 0.25% 84.64% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.64% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::12544-12551 22 0.03% 84.67% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.67% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::12800-12807 37 0.05% 84.72% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.73% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::13056-13063 80 0.11% 84.84% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.84% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::13312-13319 161 0.23% 85.07% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::13568-13575 8 0.01% 85.08% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.08% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::13824-13831 12 0.02% 85.10% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::13888-13895 2 0.00% 85.10% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::13952-13959 2 0.00% 85.10% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::14080-14087 25 0.04% 85.14% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::14144-14151 1 0.00% 85.14% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::14208-14215 1 0.00% 85.14% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::14336-14343 180 0.25% 85.39% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.40% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::14528-14535 1 0.00% 85.40% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::14592-14599 23 0.03% 85.43% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.43% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::14848-14855 2 0.00% 85.43% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.44% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.44% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::15104-15111 22 0.03% 85.47% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.47% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::15360-15367 213 0.30% 85.77% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::15552-15559 1 0.00% 85.77% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::15616-15623 15 0.02% 85.79% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::15680-15687 2 0.00% 85.80% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::15872-15879 5 0.01% 85.80% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::15936-15943 1 0.00% 85.80% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.80% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::16128-16135 4 0.01% 85.81% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::16192-16199 3 0.00% 85.81% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.82% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::16384-16391 278 0.39% 86.21% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.21% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::16640-16647 6 0.01% 86.22% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::16896-16903 6 0.01% 86.23% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::17152-17159 16 0.02% 86.25% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::17216-17223 2 0.00% 86.25% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::17280-17287 4 0.01% 86.26% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::17408-17415 216 0.30% 86.56% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::17600-17607 4 0.01% 86.57% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::17664-17671 28 0.04% 86.61% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::17920-17927 6 0.01% 86.62% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::18112-18119 2 0.00% 86.62% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::18176-18183 20 0.03% 86.65% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.65% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::18432-18439 175 0.25% 86.90% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.90% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::18688-18695 21 0.03% 86.93% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::18752-18759 2 0.00% 86.93% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::18944-18951 11 0.02% 86.94% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.95% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::19200-19207 12 0.02% 86.96% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.97% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::19392-19399 2 0.00% 86.97% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::19456-19463 153 0.22% 87.18% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.19% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::19648-19655 2 0.00% 87.19% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::19712-19719 76 0.11% 87.30% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::19776-19783 4 0.01% 87.30% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::19840-19847 1 0.00% 87.30% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.30% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::19968-19975 33 0.05% 87.35% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::20224-20231 20 0.03% 87.38% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.38% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.38% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.38% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::20480-20487 171 0.24% 87.62% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.63% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::20736-20743 75 0.11% 87.73% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::20928-20935 1 0.00% 87.73% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.75% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.75% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::21248-21255 17 0.02% 87.78% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::21376-21383 3 0.00% 87.78% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::21504-21511 73 0.10% 87.88% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::21568-21575 1 0.00% 87.88% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::21632-21639 1 0.00% 87.89% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.89% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.99% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::21824-21831 2 0.00% 87.99% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::21888-21895 1 0.00% 87.99% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::22016-22023 12 0.02% 88.01% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::22080-22087 1 0.00% 88.01% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::22144-22151 1 0.00% 88.01% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::22208-22215 2 0.00% 88.02% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::22272-22279 88 0.12% 88.14% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.14% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::22528-22535 73 0.10% 88.25% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::22656-22663 3 0.00% 88.25% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::22784-22791 94 0.13% 88.38% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.38% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::23040-23047 67 0.09% 88.48% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::23168-23175 1 0.00% 88.48% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.49% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.50% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::23424-23431 1 0.00% 88.50% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.50% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::23552-23559 18 0.03% 88.52% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::23680-23687 2 0.00% 88.53% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::23744-23751 1 0.00% 88.53% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::23808-23815 82 0.12% 88.64% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::24064-24071 73 0.10% 88.75% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::24320-24327 24 0.03% 88.78% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.78% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.78% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::24576-24583 150 0.21% 88.99% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.00% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.00% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::24832-24839 25 0.04% 89.03% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::24960-24967 1 0.00% 89.03% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::25088-25095 68 0.10% 89.13% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::25344-25351 86 0.12% 89.25% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::25536-25543 1 0.00% 89.25% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::25600-25607 20 0.03% 89.28% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.28% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::25856-25863 14 0.02% 89.30% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::25984-25991 3 0.00% 89.31% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::26048-26055 1 0.00% 89.31% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::26112-26119 69 0.10% 89.40% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.41% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::26240-26247 2 0.00% 89.41% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.41% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::26368-26375 93 0.13% 89.54% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.55% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.55% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::26624-26631 75 0.11% 89.65% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::26688-26695 1 0.00% 89.66% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::26880-26887 84 0.12% 89.77% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::27072-27079 1 0.00% 89.78% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::27136-27143 14 0.02% 89.80% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.80% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::27328-27335 2 0.00% 89.80% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::27392-27399 75 0.11% 89.91% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.91% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::27648-27655 77 0.11% 90.02% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::27712-27719 1 0.00% 90.02% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::27840-27847 1 0.00% 90.02% # Bytes accessed per row activation |
| 495system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation | 504system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation |
| 496system.physmem.bytesPerActivate::27968-27975 2 0.00% 90.04% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::28160-28167 5 0.01% 90.05% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.05% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::28416-28423 82 0.12% 90.17% # Bytes accessed per row activation | 505system.physmem.bytesPerActivate::28032-28039 1 0.00% 90.04% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::28096-28103 1 0.00% 90.04% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::28160-28167 8 0.01% 90.06% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.06% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::28288-28295 1 0.00% 90.06% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::28416-28423 75 0.11% 90.17% # Bytes accessed per row activation |
| 500system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation | 511system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation |
| 501system.physmem.bytesPerActivate::28544-28551 1 0.00% 90.17% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::28672-28679 157 0.22% 90.39% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::28736-28743 2 0.00% 90.40% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.40% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::28864-28871 1 0.00% 90.40% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::28928-28935 22 0.03% 90.43% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::29120-29127 2 0.00% 90.43% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::29184-29191 67 0.09% 90.53% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::29376-29383 1 0.00% 90.53% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::29440-29447 16 0.02% 90.55% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.55% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::29568-29575 3 0.00% 90.56% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::29696-29703 139 0.20% 90.75% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::29824-29831 3 0.00% 90.76% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.77% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::30016-30023 1 0.00% 90.78% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.78% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::30208-30215 17 0.02% 90.80% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::30272-30279 4 0.01% 90.81% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::30464-30471 11 0.02% 90.82% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.83% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.83% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::30720-30727 213 0.30% 91.13% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::30848-30855 2 0.00% 91.13% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::30912-30919 2 0.00% 91.13% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::30976-30983 26 0.04% 91.17% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::31040-31047 1 0.00% 91.17% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.17% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::31232-31239 17 0.02% 91.20% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.20% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::31488-31495 70 0.10% 91.30% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.30% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::31744-31751 147 0.21% 91.51% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.51% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.51% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::32000-32007 14 0.02% 91.53% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::32064-32071 1 0.00% 91.53% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.53% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::32256-32263 20 0.03% 91.56% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.56% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::32384-32391 2 0.00% 91.56% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.56% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::32512-32519 14 0.02% 91.58% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.59% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.59% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::32768-32775 271 0.38% 91.97% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.99% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::33280-33287 20 0.03% 92.02% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::33408-33415 1 0.00% 92.02% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::33536-33543 20 0.03% 92.04% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.05% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.05% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::33728-33735 1 0.00% 92.05% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::33792-33799 153 0.22% 92.27% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::33856-33863 1 0.00% 92.27% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::34048-34055 71 0.10% 92.37% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::34112-34119 1 0.00% 92.37% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.37% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::34304-34311 15 0.02% 92.39% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::34368-34375 1 0.00% 92.40% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::34432-34439 2 0.00% 92.40% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::34560-34567 26 0.04% 92.43% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::34624-34631 2 0.00% 92.44% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::34816-34823 211 0.30% 92.73% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::35072-35079 7 0.01% 92.74% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::35328-35335 15 0.02% 92.76% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.77% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.78% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::35840-35847 136 0.19% 92.98% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.98% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::36096-36103 19 0.03% 93.00% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::36288-36295 1 0.00% 93.01% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::36352-36359 67 0.09% 93.10% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.10% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::36608-36615 18 0.03% 93.13% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::36736-36743 1 0.00% 93.13% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::36864-36871 155 0.22% 93.35% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.46% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::37312-37319 1 0.00% 93.46% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::37376-37383 3 0.00% 93.46% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.46% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::37568-37575 1 0.00% 93.47% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::37632-37639 12 0.02% 93.48% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::37696-37703 1 0.00% 93.48% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::37888-37895 140 0.20% 93.68% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.68% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::38144-38151 3 0.00% 93.69% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::38400-38407 13 0.02% 93.70% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.71% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::38656-38663 93 0.13% 93.84% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::38912-38919 85 0.12% 93.96% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::39168-39175 15 0.02% 93.98% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::39360-39367 2 0.00% 93.98% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::39424-39431 104 0.15% 94.13% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::39616-39623 1 0.00% 94.13% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::39680-39687 19 0.03% 94.15% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::39936-39943 90 0.13% 94.28% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::40192-40199 75 0.11% 94.39% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::40448-40455 16 0.02% 94.41% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::40576-40583 2 0.00% 94.41% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::40704-40711 30 0.04% 94.45% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::40832-40839 1 0.00% 94.45% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::40960-40967 138 0.19% 94.65% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::41216-41223 29 0.04% 94.69% # Bytes accessed per row activation 606system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.69% # Bytes accessed per row activation 607system.physmem.bytesPerActivate::41472-41479 18 0.03% 94.72% # Bytes accessed per row activation 608system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.72% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.72% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.72% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::41728-41735 74 0.10% 94.82% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::41792-41799 2 0.00% 94.83% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::41920-41927 2 0.00% 94.83% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::41984-41991 90 0.13% 94.96% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::42176-42183 1 0.00% 94.96% # Bytes accessed per row activation 616system.physmem.bytesPerActivate::42240-42247 19 0.03% 94.98% # Bytes accessed per row activation 617system.physmem.bytesPerActivate::42496-42503 98 0.14% 95.12% # Bytes accessed per row activation 618system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.12% # Bytes accessed per row activation 619system.physmem.bytesPerActivate::42752-42759 15 0.02% 95.15% # Bytes accessed per row activation | 512system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.17% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::28672-28679 176 0.25% 90.42% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.42% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::28928-28935 20 0.03% 90.45% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::28992-28999 1 0.00% 90.45% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::29056-29063 2 0.00% 90.45% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.45% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::29184-29191 31 0.04% 90.50% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::29248-29255 1 0.00% 90.50% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::29312-29319 2 0.00% 90.50% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::29376-29383 3 0.00% 90.50% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::29440-29447 76 0.11% 90.61% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.61% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::29696-29703 149 0.21% 90.82% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::29824-29831 1 0.00% 90.82% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.83% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.84% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.85% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::30208-30215 7 0.01% 90.86% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.86% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::30464-30471 23 0.03% 90.89% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.89% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.89% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.90% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::30720-30727 175 0.25% 91.14% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::30784-30791 2 0.00% 91.15% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::30912-30919 6 0.01% 91.15% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::30976-30983 19 0.03% 91.18% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.18% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::31232-31239 4 0.01% 91.19% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.19% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::31488-31495 24 0.03% 91.22% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::31616-31623 2 0.00% 91.23% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::31680-31687 1 0.00% 91.23% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::31744-31751 210 0.30% 91.52% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.53% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.53% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.53% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::32000-32007 12 0.02% 91.54% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::32256-32263 5 0.01% 91.55% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.55% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::32512-32519 5 0.01% 91.56% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::32704-32711 2 0.00% 91.56% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::32768-32775 275 0.39% 91.95% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::33024-33031 4 0.01% 91.96% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.96% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::33280-33287 5 0.01% 91.97% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::33408-33415 1 0.00% 91.97% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.97% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::33536-33543 21 0.03% 92.00% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.00% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.00% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::33792-33799 214 0.30% 92.31% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.31% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.31% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::34048-34055 20 0.03% 92.34% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.34% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::34304-34311 2 0.00% 92.34% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::34560-34567 21 0.03% 92.37% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::34816-34823 167 0.24% 92.61% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::35072-35079 18 0.03% 92.63% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::35200-35207 1 0.00% 92.63% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::35328-35335 7 0.01% 92.64% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.65% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::35520-35527 1 0.00% 92.65% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.66% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.67% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::35712-35719 1 0.00% 92.67% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::35840-35847 147 0.21% 92.87% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::35968-35975 1 0.00% 92.88% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.88% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::36096-36103 73 0.10% 92.98% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::36160-36167 1 0.00% 92.98% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.98% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::36352-36359 29 0.04% 93.02% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::36416-36423 1 0.00% 93.03% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.03% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::36608-36615 20 0.03% 93.06% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.06% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::36864-36871 174 0.25% 93.30% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::37120-37127 72 0.10% 93.40% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::37376-37383 7 0.01% 93.41% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::37632-37639 17 0.02% 93.44% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::37696-37703 2 0.00% 93.44% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::37888-37895 76 0.11% 93.55% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::38144-38151 72 0.10% 93.65% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.65% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.67% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.67% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::38656-38663 83 0.12% 93.79% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::38912-38919 77 0.11% 93.89% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::39040-39047 2 0.00% 93.90% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::39168-39175 93 0.13% 94.03% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::39360-39367 1 0.00% 94.03% # Bytes accessed per row activation 606system.physmem.bytesPerActivate::39424-39431 65 0.09% 94.12% # Bytes accessed per row activation 607system.physmem.bytesPerActivate::39552-39559 1 0.00% 94.12% # Bytes accessed per row activation 608system.physmem.bytesPerActivate::39680-39687 10 0.01% 94.14% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::39936-39943 17 0.02% 94.16% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::40000-40007 2 0.00% 94.16% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::40128-40135 1 0.00% 94.17% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::40192-40199 82 0.12% 94.28% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::40256-40263 1 0.00% 94.28% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.38% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.38% # Bytes accessed per row activation 616system.physmem.bytesPerActivate::40704-40711 23 0.03% 94.41% # Bytes accessed per row activation 617system.physmem.bytesPerActivate::40896-40903 1 0.00% 94.41% # Bytes accessed per row activation 618system.physmem.bytesPerActivate::40960-40967 150 0.21% 94.62% # Bytes accessed per row activation 619system.physmem.bytesPerActivate::41024-41031 1 0.00% 94.63% # Bytes accessed per row activation 620system.physmem.bytesPerActivate::41088-41095 1 0.00% 94.63% # Bytes accessed per row activation 621system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.66% # Bytes accessed per row activation 622system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.66% # Bytes accessed per row activation 623system.physmem.bytesPerActivate::41344-41351 2 0.00% 94.66% # Bytes accessed per row activation 624system.physmem.bytesPerActivate::41472-41479 70 0.10% 94.76% # Bytes accessed per row activation 625system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.76% # Bytes accessed per row activation 626system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.77% # Bytes accessed per row activation 627system.physmem.bytesPerActivate::41728-41735 82 0.12% 94.88% # Bytes accessed per row activation 628system.physmem.bytesPerActivate::41792-41799 1 0.00% 94.88% # Bytes accessed per row activation 629system.physmem.bytesPerActivate::41984-41991 16 0.02% 94.90% # Bytes accessed per row activation 630system.physmem.bytesPerActivate::42240-42247 13 0.02% 94.92% # Bytes accessed per row activation 631system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.92% # Bytes accessed per row activation 632system.physmem.bytesPerActivate::42496-42503 66 0.09% 95.02% # Bytes accessed per row activation 633system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.02% # Bytes accessed per row activation 634system.physmem.bytesPerActivate::42752-42759 92 0.13% 95.15% # Bytes accessed per row activation |
| 620system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation | 635system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation |
| 621system.physmem.bytesPerActivate::42880-42887 2 0.00% 95.15% # Bytes accessed per row activation 622system.physmem.bytesPerActivate::43008-43015 82 0.12% 95.26% # Bytes accessed per row activation 623system.physmem.bytesPerActivate::43200-43207 1 0.00% 95.27% # Bytes accessed per row activation 624system.physmem.bytesPerActivate::43264-43271 90 0.13% 95.39% # Bytes accessed per row activation 625system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.39% # Bytes accessed per row activation 626system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.41% # Bytes accessed per row activation 627system.physmem.bytesPerActivate::43712-43719 1 0.00% 95.41% # Bytes accessed per row activation 628system.physmem.bytesPerActivate::43776-43783 4 0.01% 95.42% # Bytes accessed per row activation 629system.physmem.bytesPerActivate::44032-44039 144 0.20% 95.62% # Bytes accessed per row activation 630system.physmem.bytesPerActivate::44096-44103 2 0.00% 95.62% # Bytes accessed per row activation 631system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.64% # Bytes accessed per row activation 632system.physmem.bytesPerActivate::44416-44423 2 0.00% 95.64% # Bytes accessed per row activation 633system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.64% # Bytes accessed per row activation 634system.physmem.bytesPerActivate::44544-44551 5 0.01% 95.65% # Bytes accessed per row activation 635system.physmem.bytesPerActivate::44800-44807 85 0.12% 95.77% # Bytes accessed per row activation 636system.physmem.bytesPerActivate::45056-45063 155 0.22% 95.99% # Bytes accessed per row activation 637system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.99% # Bytes accessed per row activation 638system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.99% # Bytes accessed per row activation 639system.physmem.bytesPerActivate::45312-45319 16 0.02% 96.01% # Bytes accessed per row activation 640system.physmem.bytesPerActivate::45440-45447 1 0.00% 96.02% # Bytes accessed per row activation 641system.physmem.bytesPerActivate::45504-45511 2 0.00% 96.02% # Bytes accessed per row activation 642system.physmem.bytesPerActivate::45568-45575 71 0.10% 96.12% # Bytes accessed per row activation 643system.physmem.bytesPerActivate::45632-45639 2 0.00% 96.12% # Bytes accessed per row activation 644system.physmem.bytesPerActivate::45760-45767 1 0.00% 96.12% # Bytes accessed per row activation 645system.physmem.bytesPerActivate::45824-45831 19 0.03% 96.15% # Bytes accessed per row activation 646system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.15% # Bytes accessed per row activation 647system.physmem.bytesPerActivate::46080-46087 138 0.19% 96.34% # Bytes accessed per row activation 648system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.35% # Bytes accessed per row activation 649system.physmem.bytesPerActivate::46336-46343 14 0.02% 96.37% # Bytes accessed per row activation 650system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.37% # Bytes accessed per row activation 651system.physmem.bytesPerActivate::46592-46599 15 0.02% 96.39% # Bytes accessed per row activation 652system.physmem.bytesPerActivate::46848-46855 10 0.01% 96.40% # Bytes accessed per row activation 653system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.40% # Bytes accessed per row activation 654system.physmem.bytesPerActivate::47104-47111 214 0.30% 96.70% # Bytes accessed per row activation 655system.physmem.bytesPerActivate::47360-47367 31 0.04% 96.75% # Bytes accessed per row activation 656system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.75% # Bytes accessed per row activation 657system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.75% # Bytes accessed per row activation 658system.physmem.bytesPerActivate::47616-47623 15 0.02% 96.77% # Bytes accessed per row activation 659system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.77% # Bytes accessed per row activation 660system.physmem.bytesPerActivate::47872-47879 70 0.10% 96.87% # Bytes accessed per row activation 661system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.87% # Bytes accessed per row activation 662system.physmem.bytesPerActivate::48128-48135 146 0.21% 97.08% # Bytes accessed per row activation 663system.physmem.bytesPerActivate::48384-48391 10 0.01% 97.09% # Bytes accessed per row activation 664system.physmem.bytesPerActivate::48640-48647 20 0.03% 97.12% # Bytes accessed per row activation 665system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.14% # Bytes accessed per row activation 666system.physmem.bytesPerActivate::48832-48839 2 0.00% 97.14% # Bytes accessed per row activation 667system.physmem.bytesPerActivate::48896-48903 13 0.02% 97.16% # Bytes accessed per row activation 668system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.17% # Bytes accessed per row activation 669system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation 670system.physmem.bytesPerActivate::49152-49159 1979 2.78% 99.95% # Bytes accessed per row activation | 636system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.15% # Bytes accessed per row activation 637system.physmem.bytesPerActivate::43008-43015 75 0.11% 95.26% # Bytes accessed per row activation 638system.physmem.bytesPerActivate::43264-43271 86 0.12% 95.38% # Bytes accessed per row activation 639system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.40% # Bytes accessed per row activation 640system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.40% # Bytes accessed per row activation 641system.physmem.bytesPerActivate::43776-43783 74 0.10% 95.50% # Bytes accessed per row activation 642system.physmem.bytesPerActivate::43904-43911 2 0.00% 95.51% # Bytes accessed per row activation 643system.physmem.bytesPerActivate::44032-44039 73 0.10% 95.61% # Bytes accessed per row activation 644system.physmem.bytesPerActivate::44160-44167 3 0.00% 95.61% # Bytes accessed per row activation 645system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.61% # Bytes accessed per row activation 646system.physmem.bytesPerActivate::44288-44295 16 0.02% 95.64% # Bytes accessed per row activation 647system.physmem.bytesPerActivate::44544-44551 9 0.01% 95.65% # Bytes accessed per row activation 648system.physmem.bytesPerActivate::44608-44615 2 0.00% 95.65% # Bytes accessed per row activation 649system.physmem.bytesPerActivate::44800-44807 74 0.10% 95.76% # Bytes accessed per row activation 650system.physmem.bytesPerActivate::44928-44935 4 0.01% 95.76% # Bytes accessed per row activation 651system.physmem.bytesPerActivate::45056-45063 173 0.24% 96.01% # Bytes accessed per row activation 652system.physmem.bytesPerActivate::45120-45127 1 0.00% 96.01% # Bytes accessed per row activation 653system.physmem.bytesPerActivate::45248-45255 1 0.00% 96.01% # Bytes accessed per row activation 654system.physmem.bytesPerActivate::45312-45319 19 0.03% 96.04% # Bytes accessed per row activation 655system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.04% # Bytes accessed per row activation 656system.physmem.bytesPerActivate::45568-45575 34 0.05% 96.09% # Bytes accessed per row activation 657system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation 658system.physmem.bytesPerActivate::45824-45831 76 0.11% 96.20% # Bytes accessed per row activation 659system.physmem.bytesPerActivate::46080-46087 150 0.21% 96.41% # Bytes accessed per row activation 660system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.41% # Bytes accessed per row activation 661system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.41% # Bytes accessed per row activation 662system.physmem.bytesPerActivate::46336-46343 8 0.01% 96.42% # Bytes accessed per row activation 663system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.42% # Bytes accessed per row activation 664system.physmem.bytesPerActivate::46592-46599 9 0.01% 96.44% # Bytes accessed per row activation 665system.physmem.bytesPerActivate::46848-46855 17 0.02% 96.46% # Bytes accessed per row activation 666system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.46% # Bytes accessed per row activation 667system.physmem.bytesPerActivate::47104-47111 174 0.25% 96.71% # Bytes accessed per row activation 668system.physmem.bytesPerActivate::47360-47367 22 0.03% 96.74% # Bytes accessed per row activation 669system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.74% # Bytes accessed per row activation 670system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.74% # Bytes accessed per row activation 671system.physmem.bytesPerActivate::47616-47623 2 0.00% 96.74% # Bytes accessed per row activation 672system.physmem.bytesPerActivate::47744-47751 3 0.00% 96.75% # Bytes accessed per row activation 673system.physmem.bytesPerActivate::47872-47879 21 0.03% 96.78% # Bytes accessed per row activation 674system.physmem.bytesPerActivate::48128-48135 208 0.29% 97.07% # Bytes accessed per row activation 675system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.07% # Bytes accessed per row activation 676system.physmem.bytesPerActivate::48384-48391 12 0.02% 97.09% # Bytes accessed per row activation 677system.physmem.bytesPerActivate::48640-48647 4 0.01% 97.09% # Bytes accessed per row activation 678system.physmem.bytesPerActivate::48768-48775 10 0.01% 97.11% # Bytes accessed per row activation 679system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.11% # Bytes accessed per row activation 680system.physmem.bytesPerActivate::48960-48967 3 0.00% 97.12% # Bytes accessed per row activation 681system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.12% # Bytes accessed per row activation 682system.physmem.bytesPerActivate::49088-49095 3 0.00% 97.13% # Bytes accessed per row activation 683system.physmem.bytesPerActivate::49152-49159 2000 2.82% 99.95% # Bytes accessed per row activation |
| 671system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation | 684system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation |
| 672system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.96% # Bytes accessed per row activation 673system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation | 685system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.95% # Bytes accessed per row activation 686system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.95% # Bytes accessed per row activation 687system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.95% # Bytes accessed per row activation 688system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.96% # Bytes accessed per row activation 689system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.96% # Bytes accessed per row activation |
| 674system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation | 690system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation |
| 691system.physmem.bytesPerActivate::50304-50311 1 0.00% 99.96% # Bytes accessed per row activation |
|
| 675system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation | 692system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation |
| 676system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.96% # Bytes accessed per row activation 677system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.96% # Bytes accessed per row activation | 693system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.97% # Bytes accessed per row activation 694system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.97% # Bytes accessed per row activation 695system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.97% # Bytes accessed per row activation |
| 678system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation | 696system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation |
| 679system.physmem.bytesPerActivate::50880-50887 4 0.01% 99.97% # Bytes accessed per row activation 680system.physmem.bytesPerActivate::50944-50951 3 0.00% 99.98% # Bytes accessed per row activation 681system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.98% # Bytes accessed per row activation 682system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation 683system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.98% # Bytes accessed per row activation 684system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.98% # Bytes accessed per row activation 685system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.99% # Bytes accessed per row activation 686system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation 687system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation 688system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation 689system.physmem.bytesPerActivate::51712-51719 3 0.00% 100.00% # Bytes accessed per row activation | 697system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation 698system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation 699system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.98% # Bytes accessed per row activation 700system.physmem.bytesPerActivate::51456-51463 4 0.01% 99.98% # Bytes accessed per row activation 701system.physmem.bytesPerActivate::51520-51527 2 0.00% 99.99% # Bytes accessed per row activation 702system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation 703system.physmem.bytesPerActivate::51648-51655 1 0.00% 99.99% # Bytes accessed per row activation 704system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation 705system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation 706system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation |
| 690system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation | 707system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation |
| 691system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation 692system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation 693system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation 694system.physmem.totQLat 151840872500 # Total ticks spent queuing 695system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM 696system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers 697system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks 698system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst 699system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst | 708system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation 709system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation 710system.physmem.totQLat 151784626000 # Total ticks spent queuing 711system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM 712system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers 713system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks 714system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst 715system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst |
| 700system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 716system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 701system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst 702system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s | 717system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst 718system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s |
| 703system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s 704system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s 705system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s 706system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 707system.physmem.busUtil 2.87 # Data bus utilization in percentage 708system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads 709system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 710system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing | 719system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s 720system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s 721system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s 722system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 723system.physmem.busUtil 2.87 # Data bus utilization in percentage 724system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads 725system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 726system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing |
| 711system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing 712system.physmem.readRowHits 6168484 # Number of row buffer hits during reads 713system.physmem.writeRowHits 97939 # Number of row buffer hits during writes | 727system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing 728system.physmem.readRowHits 6167948 # Number of row buffer hits during reads 729system.physmem.writeRowHits 98004 # Number of row buffer hits during writes |
| 714system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads | 730system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads |
| 715system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes 716system.physmem.avgGap 156006.94 # Average gap between requests | 731system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes 732system.physmem.avgGap 156007.30 # Average gap between requests |
| 717system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined | 733system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined |
| 718system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state | 734system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state |
| 719system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 720system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 721system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 722system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 723system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 724system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 725system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 726system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 727system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 728system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 729system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 730system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 731system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 732system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 733system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 734system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 735system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 736system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) | 735system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 736system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 737system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 738system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 739system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 740system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 741system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 742system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 743system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 744system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 745system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 746system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 747system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 748system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 749system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 750system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 751system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 752system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) |
| 737system.membus.throughput 62369736 # Throughput (bytes/s) 738system.membus.trans_dist::ReadReq 7306752 # Transaction distribution 739system.membus.trans_dist::ReadResp 7306752 # Transaction distribution 740system.membus.trans_dist::WriteReq 767894 # Transaction distribution 741system.membus.trans_dist::WriteResp 767894 # Transaction distribution 742system.membus.trans_dist::Writeback 66695 # Transaction distribution 743system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution 744system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution 745system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution 746system.membus.trans_dist::ReadExReq 138070 # Transaction distribution 747system.membus.trans_dist::ReadExResp 137680 # Transaction distribution 748system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) | 753system.membus.throughput 62368825 # Throughput (bytes/s) 754system.membus.trans_dist::ReadReq 7306736 # Transaction distribution 755system.membus.trans_dist::ReadResp 7306736 # Transaction distribution 756system.membus.trans_dist::WriteReq 767886 # Transaction distribution 757system.membus.trans_dist::WriteResp 767886 # Transaction distribution 758system.membus.trans_dist::Writeback 66680 # Transaction distribution 759system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution 760system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution 761system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution 762system.membus.trans_dist::ReadExReq 138080 # Transaction distribution 763system.membus.trans_dist::ReadExResp 137692 # Transaction distribution 764system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes) |
| 749system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) | 765system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) |
| 750system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) | 766system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes) |
| 751system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 752system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) | 767system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 768system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) |
| 753system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) 754system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) | 769system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes) 770system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes) |
| 755system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) 756system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) | 771system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) 772system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) |
| 757system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) 758system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) | 773system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes) 774system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes) |
| 759system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) | 775system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) |
| 760system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) | 776system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes) |
| 761system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 762system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) | 777system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 778system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) |
| 763system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) 764system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) | 779system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes) 780system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes) |
| 765system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) 766system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) | 781system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) 782system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) |
| 767system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) 768system.membus.data_through_bus 68903961 # Total data (bytes) | 783system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes) 784system.membus.data_through_bus 68902967 # Total data (bytes) |
| 769system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 785system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 770system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) | 786system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks) |
| 771system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 772system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) 773system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 787system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 788system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) 789system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 774system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) | 790system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks) |
| 775system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 776system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 777system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 791system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 792system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 793system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 778system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) | 794system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks) |
| 779system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 795system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 780system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) | 796system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks) |
| 781system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) | 797system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) |
| 782system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) | 798system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks) |
| 783system.membus.respLayer1.utilization 0.4 # Layer utilization (%) | 799system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 784system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) | 800system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) |
| 785system.membus.respLayer2.utilization 1.2 # Layer utilization (%) 786system.l2c.tags.replacements 72740 # number of replacements | 801system.membus.respLayer2.utilization 1.2 # Layer utilization (%) 802system.l2c.tags.replacements 72740 # number of replacements |
| 787system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use 788system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. | 803system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use 804system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. |
| 789system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. | 805system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. |
| 790system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. | 806system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks. |
| 791system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 807system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 792system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor 793system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor 794system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor 795system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor 796system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor 797system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor 798system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor 799system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor 800system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy 801system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy 802system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 803system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy 804system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy 805system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy 806system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy 807system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy 808system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy 809system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits 810system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits 811system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits 812system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits 813system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits 814system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits 815system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits 816system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits 817system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits 818system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits 819system.l2c.Writeback_hits::total 581386 # number of Writeback hits 820system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits 821system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits 822system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits 823system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits 824system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits 825system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits 826system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits 827system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits 828system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits 829system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits 830system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits 831system.l2c.demand_hits::cpu0.inst 386342 # number of demand (read+write) hits 832system.l2c.demand_hits::cpu0.data 214931 # number of demand (read+write) hits 833system.l2c.demand_hits::cpu1.dtb.walker 30647 # number of demand (read+write) hits 834system.l2c.demand_hits::cpu1.itb.walker 5089 # number of demand (read+write) hits 835system.l2c.demand_hits::cpu1.inst 590258 # number of demand (read+write) hits 836system.l2c.demand_hits::cpu1.data 257042 # number of demand (read+write) hits 837system.l2c.demand_hits::total 1510732 # number of demand (read+write) hits 838system.l2c.overall_hits::cpu0.dtb.walker 22065 # number of overall hits 839system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits 840system.l2c.overall_hits::cpu0.inst 386342 # number of overall hits 841system.l2c.overall_hits::cpu0.data 214931 # number of overall hits 842system.l2c.overall_hits::cpu1.dtb.walker 30647 # number of overall hits 843system.l2c.overall_hits::cpu1.itb.walker 5089 # number of overall hits 844system.l2c.overall_hits::cpu1.inst 590258 # number of overall hits 845system.l2c.overall_hits::cpu1.data 257042 # number of overall hits 846system.l2c.overall_hits::total 1510732 # number of overall hits | 808system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor 809system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor 810system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor 811system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor 812system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor 813system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.504423 # Average occupied blocks per requestor 814system.l2c.tags.occ_blocks::cpu1.inst 3702.179063 # Average occupied blocks per requestor 815system.l2c.tags.occ_blocks::cpu1.data 3777.323870 # Average occupied blocks per requestor 816system.l2c.tags.occ_percent::writebacks 0.603002 # Average percentage of cache occupancy 817system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy 818system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 819system.l2c.tags.occ_percent::cpu0.inst 0.061282 # Average percentage of cache occupancy 820system.l2c.tags.occ_percent::cpu0.data 0.043216 # Average percentage of cache occupancy 821system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 # Average percentage of cache occupancy 822system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy 823system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy 824system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy 825system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits 826system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits 827system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits 828system.l2c.ReadReq_hits::cpu0.data 166544 # number of ReadReq hits 829system.l2c.ReadReq_hits::cpu1.dtb.walker 31083 # number of ReadReq hits 830system.l2c.ReadReq_hits::cpu1.itb.walker 5052 # number of ReadReq hits 831system.l2c.ReadReq_hits::cpu1.inst 589425 # number of ReadReq hits 832system.l2c.ReadReq_hits::cpu1.data 198327 # number of ReadReq hits 833system.l2c.ReadReq_hits::total 1402653 # number of ReadReq hits 834system.l2c.Writeback_hits::writebacks 581363 # number of Writeback hits 835system.l2c.Writeback_hits::total 581363 # number of Writeback hits 836system.l2c.UpgradeReq_hits::cpu0.data 1344 # number of UpgradeReq hits 837system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits 838system.l2c.UpgradeReq_hits::total 2082 # number of UpgradeReq hits 839system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits 840system.l2c.SCUpgradeReq_hits::cpu1.data 140 # number of SCUpgradeReq hits 841system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits 842system.l2c.ReadExReq_hits::cpu0.data 48345 # number of ReadExReq hits 843system.l2c.ReadExReq_hits::cpu1.data 58632 # number of ReadExReq hits 844system.l2c.ReadExReq_hits::total 106977 # number of ReadExReq hits 845system.l2c.demand_hits::cpu0.dtb.walker 22002 # number of demand (read+write) hits 846system.l2c.demand_hits::cpu0.itb.walker 4348 # number of demand (read+write) hits 847system.l2c.demand_hits::cpu0.inst 385872 # number of demand (read+write) hits 848system.l2c.demand_hits::cpu0.data 214889 # number of demand (read+write) hits 849system.l2c.demand_hits::cpu1.dtb.walker 31083 # number of demand (read+write) hits 850system.l2c.demand_hits::cpu1.itb.walker 5052 # number of demand (read+write) hits 851system.l2c.demand_hits::cpu1.inst 589425 # number of demand (read+write) hits 852system.l2c.demand_hits::cpu1.data 256959 # number of demand (read+write) hits 853system.l2c.demand_hits::total 1509630 # number of demand (read+write) hits 854system.l2c.overall_hits::cpu0.dtb.walker 22002 # number of overall hits 855system.l2c.overall_hits::cpu0.itb.walker 4348 # number of overall hits 856system.l2c.overall_hits::cpu0.inst 385872 # number of overall hits 857system.l2c.overall_hits::cpu0.data 214889 # number of overall hits 858system.l2c.overall_hits::cpu1.dtb.walker 31083 # number of overall hits 859system.l2c.overall_hits::cpu1.itb.walker 5052 # number of overall hits 860system.l2c.overall_hits::cpu1.inst 589425 # number of overall hits 861system.l2c.overall_hits::cpu1.data 256959 # number of overall hits 862system.l2c.overall_hits::total 1509630 # number of overall hits |
| 847system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses 848system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses | 863system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses 864system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses |
| 849system.l2c.ReadReq_misses::cpu0.inst 6260 # number of ReadReq misses 850system.l2c.ReadReq_misses::cpu0.data 6384 # number of ReadReq misses 851system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses 852system.l2c.ReadReq_misses::cpu1.inst 6325 # number of ReadReq misses 853system.l2c.ReadReq_misses::cpu1.data 6267 # number of ReadReq misses 854system.l2c.ReadReq_misses::total 25263 # number of ReadReq misses 855system.l2c.UpgradeReq_misses::cpu0.data 5164 # number of UpgradeReq misses 856system.l2c.UpgradeReq_misses::cpu1.data 3801 # number of UpgradeReq misses 857system.l2c.UpgradeReq_misses::total 8965 # number of UpgradeReq misses 858system.l2c.SCUpgradeReq_misses::cpu0.data 637 # number of SCUpgradeReq misses 859system.l2c.SCUpgradeReq_misses::cpu1.data 413 # number of SCUpgradeReq misses 860system.l2c.SCUpgradeReq_misses::total 1050 # number of SCUpgradeReq misses 861system.l2c.ReadExReq_misses::cpu0.data 63263 # number of ReadExReq misses 862system.l2c.ReadExReq_misses::cpu1.data 77007 # number of ReadExReq misses 863system.l2c.ReadExReq_misses::total 140270 # number of ReadExReq misses | 865system.l2c.ReadReq_misses::cpu0.inst 6278 # number of ReadReq misses 866system.l2c.ReadReq_misses::cpu0.data 6388 # number of ReadReq misses 867system.l2c.ReadReq_misses::cpu1.dtb.walker 13 # number of ReadReq misses 868system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses 869system.l2c.ReadReq_misses::cpu1.data 6245 # number of ReadReq misses 870system.l2c.ReadReq_misses::total 25248 # number of ReadReq misses 871system.l2c.UpgradeReq_misses::cpu0.data 5144 # number of UpgradeReq misses 872system.l2c.UpgradeReq_misses::cpu1.data 3776 # number of UpgradeReq misses 873system.l2c.UpgradeReq_misses::total 8920 # number of UpgradeReq misses 874system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses 875system.l2c.SCUpgradeReq_misses::cpu1.data 420 # number of SCUpgradeReq misses 876system.l2c.SCUpgradeReq_misses::total 1053 # number of SCUpgradeReq misses 877system.l2c.ReadExReq_misses::cpu0.data 63281 # number of ReadExReq misses 878system.l2c.ReadExReq_misses::cpu1.data 77008 # number of ReadExReq misses 879system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses |
| 864system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses 865system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses | 880system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses 881system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses |
| 866system.l2c.demand_misses::cpu0.inst 6260 # number of demand (read+write) misses 867system.l2c.demand_misses::cpu0.data 69647 # number of demand (read+write) misses 868system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses 869system.l2c.demand_misses::cpu1.inst 6325 # number of demand (read+write) misses 870system.l2c.demand_misses::cpu1.data 83274 # number of demand (read+write) misses 871system.l2c.demand_misses::total 165533 # number of demand (read+write) misses | 882system.l2c.demand_misses::cpu0.inst 6278 # number of demand (read+write) misses 883system.l2c.demand_misses::cpu0.data 69669 # number of demand (read+write) misses 884system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses 885system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses 886system.l2c.demand_misses::cpu1.data 83253 # number of demand (read+write) misses 887system.l2c.demand_misses::total 165537 # number of demand (read+write) misses |
| 872system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses 873system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses | 888system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses 889system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses |
| 874system.l2c.overall_misses::cpu0.inst 6260 # number of overall misses 875system.l2c.overall_misses::cpu0.data 69647 # number of overall misses 876system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses 877system.l2c.overall_misses::cpu1.inst 6325 # number of overall misses 878system.l2c.overall_misses::cpu1.data 83274 # number of overall misses 879system.l2c.overall_misses::total 165533 # number of overall misses 880system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1016250 # number of ReadReq miss cycles 881system.l2c.ReadReq_miss_latency::cpu0.itb.walker 477500 # number of ReadReq miss cycles 882system.l2c.ReadReq_miss_latency::cpu0.inst 449841750 # number of ReadReq miss cycles 883system.l2c.ReadReq_miss_latency::cpu0.data 482248247 # number of ReadReq miss cycles 884system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 862750 # number of ReadReq miss cycles 885system.l2c.ReadReq_miss_latency::cpu1.inst 476239250 # number of ReadReq miss cycles 886system.l2c.ReadReq_miss_latency::cpu1.data 488675250 # number of ReadReq miss cycles 887system.l2c.ReadReq_miss_latency::total 1899360997 # number of ReadReq miss cycles 888system.l2c.UpgradeReq_miss_latency::cpu0.data 8963096 # number of UpgradeReq miss cycles 889system.l2c.UpgradeReq_miss_latency::cpu1.data 12325976 # number of UpgradeReq miss cycles 890system.l2c.UpgradeReq_miss_latency::total 21289072 # number of UpgradeReq miss cycles 891system.l2c.SCUpgradeReq_miss_latency::cpu0.data 488979 # number of SCUpgradeReq miss cycles 892system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2955872 # number of SCUpgradeReq miss cycles 893system.l2c.SCUpgradeReq_miss_latency::total 3444851 # number of SCUpgradeReq miss cycles 894system.l2c.ReadExReq_miss_latency::cpu0.data 4446470608 # number of ReadExReq miss cycles 895system.l2c.ReadExReq_miss_latency::cpu1.data 6273738055 # number of ReadExReq miss cycles 896system.l2c.ReadExReq_miss_latency::total 10720208663 # number of ReadExReq miss cycles 897system.l2c.demand_miss_latency::cpu0.dtb.walker 1016250 # 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miss rate for overall accesses 999system.l2c.overall_miss_rate::total 0.098818 # miss rate for overall accesses 1000system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average ReadReq miss latency 1001system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 77500 # average ReadReq miss latency 1002system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73230.288308 # average ReadReq miss latency 1003system.l2c.ReadReq_avg_miss_latency::cpu0.data 75048.175955 # average ReadReq miss latency 1004system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 98442.307692 # average ReadReq miss latency 1005system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75450.697527 # average ReadReq miss latency 1006system.l2c.ReadReq_avg_miss_latency::cpu1.data 77715.092074 # average ReadReq miss latency 1007system.l2c.ReadReq_avg_miss_latency::total 75371.405577 # average ReadReq miss latency 1008system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1738.354588 # average UpgradeReq miss latency 1009system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3236.621028 # average UpgradeReq miss latency 1010system.l2c.UpgradeReq_avg_miss_latency::total 2372.598318 # average UpgradeReq miss latency 1011system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 698.232227 # average SCUpgradeReq miss latency 1012system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7030.652381 # average SCUpgradeReq miss latency 1013system.l2c.SCUpgradeReq_avg_miss_latency::total 3223.983856 # average SCUpgradeReq miss latency 1014system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69918.484126 # average ReadExReq miss latency 1015system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81388.233197 # average ReadExReq miss latency 1016system.l2c.ReadExReq_avg_miss_latency::total 76214.504744 # average ReadExReq miss latency 1017system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average overall miss latency 1018system.l2c.demand_avg_miss_latency::cpu0.itb.walker 77500 # average overall miss latency 1019system.l2c.demand_avg_miss_latency::cpu0.inst 73230.288308 # average overall miss latency 1020system.l2c.demand_avg_miss_latency::cpu0.data 70388.829207 # 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average overall miss latency 1032system.l2c.overall_avg_miss_latency::total 76085.913747 # average overall miss latency |
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number of overall MSHR miss cycles 1120system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of overall MSHR miss cycles 1121system.l2c.overall_mshr_miss_latency::cpu1.inst 396299500 # number of overall MSHR miss cycles 1122system.l2c.overall_mshr_miss_latency::cpu1.data 5714736184 # number of overall MSHR miss cycles 1123system.l2c.overall_mshr_miss_latency::total 10521689078 # number of overall MSHR miss cycles |
| 1108system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6382249 # number of ReadReq MSHR uncacheable cycles | 1124system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6382249 # number of ReadReq MSHR uncacheable cycles |
| 1109system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399939239 # number of ReadReq MSHR uncacheable cycles | 1125system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399518741 # number of ReadReq MSHR uncacheable cycles |
| 1110system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2397749 # number of ReadReq MSHR uncacheable cycles | 1126system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2397749 # number of ReadReq MSHR uncacheable cycles |
| 1111system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603749244 # number of ReadReq MSHR uncacheable cycles 1112system.l2c.ReadReq_mshr_uncacheable_latency::total 167012468481 # number of ReadReq MSHR uncacheable cycles 1113system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1006407999 # number of WriteReq MSHR uncacheable cycles 1114system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16511968075 # number of WriteReq MSHR uncacheable cycles 1115system.l2c.WriteReq_mshr_uncacheable_latency::total 17518376074 # number of WriteReq MSHR uncacheable cycles | 1127system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603727234 # number of ReadReq MSHR uncacheable cycles 1128system.l2c.ReadReq_mshr_uncacheable_latency::total 167012025973 # number of ReadReq MSHR uncacheable cycles 1129system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1005734999 # number of WriteReq MSHR uncacheable cycles 1130system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16506425201 # number of WriteReq MSHR uncacheable cycles 1131system.l2c.WriteReq_mshr_uncacheable_latency::total 17512160200 # number of WriteReq MSHR uncacheable cycles |
| 1116system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6382249 # number of overall MSHR uncacheable cycles | 1132system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6382249 # number of overall MSHR uncacheable cycles |
| 1117system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406347238 # number of overall MSHR uncacheable cycles | 1133system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13405253740 # number of overall MSHR uncacheable cycles |
| 1118system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2397749 # number of overall MSHR uncacheable cycles | 1134system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2397749 # number of overall MSHR uncacheable cycles |
| 1119system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171115717319 # number of overall MSHR uncacheable cycles 1120system.l2c.overall_mshr_uncacheable_latency::total 184530844555 # number of overall MSHR uncacheable cycles 1121system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for ReadReq accesses 1122system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for ReadReq accesses 1123system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for ReadReq accesses 1124system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036677 # mshr miss rate for ReadReq accesses 1125system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for ReadReq accesses 1126system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for ReadReq accesses 1127system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030489 # mshr miss rate for ReadReq accesses 1128system.l2c.ReadReq_mshr_miss_rate::total 0.017624 # mshr miss rate for ReadReq accesses 1129system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.794706 # mshr miss rate for UpgradeReq accesses 1130system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835201 # mshr miss rate for UpgradeReq accesses 1131system.l2c.UpgradeReq_mshr_miss_rate::total 0.811386 # mshr miss rate for UpgradeReq accesses 1132system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769324 # mshr miss rate for SCUpgradeReq accesses 1133system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750909 # mshr miss rate for SCUpgradeReq accesses 1134system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.761974 # mshr miss rate for SCUpgradeReq accesses 1135system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566974 # mshr miss rate for ReadExReq accesses 1136system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567689 # mshr miss rate for ReadExReq accesses 1137system.l2c.ReadExReq_mshr_miss_rate::total 0.567366 # mshr miss rate for ReadExReq accesses 1138system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for demand accesses 1139system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for demand accesses 1140system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for demand accesses 1141system.l2c.demand_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for demand accesses 1142system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for demand accesses 1143system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for demand accesses 1144system.l2c.demand_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for demand accesses 1145system.l2c.demand_mshr_miss_rate::total 0.098705 # mshr miss rate for demand accesses 1146system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for overall accesses 1147system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for overall accesses 1148system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for overall accesses 1149system.l2c.overall_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for overall accesses 1150system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for overall accesses 1151system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for overall accesses 1152system.l2c.overall_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for overall accesses 1153system.l2c.overall_mshr_miss_rate::total 0.098705 # mshr miss rate for overall accesses 1154system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average ReadReq mshr miss latency 1155system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average ReadReq mshr miss latency 1156system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average ReadReq mshr miss latency 1157system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522 # average ReadReq mshr miss latency 1158system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average ReadReq mshr miss latency 1159system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average ReadReq mshr miss latency 1160system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603 # average ReadReq mshr miss latency 1161system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512 # average ReadReq mshr miss latency 1162system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283 # average UpgradeReq mshr miss latency 1163system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917 # average UpgradeReq mshr miss latency 1164system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688 # average UpgradeReq mshr miss latency 1165system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730 # average SCUpgradeReq mshr miss latency 1166system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625 # average SCUpgradeReq mshr miss latency 1167system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429 # average SCUpgradeReq mshr miss latency 1168system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497 # average ReadExReq mshr miss latency 1169system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151 # average ReadExReq mshr miss latency 1170system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618 # average ReadExReq mshr miss latency 1171system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency 1172system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency 1173system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency 1174system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency 1175system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency 1176system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency 1177system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency 1178system.l2c.demand_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency 1179system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency 1180system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency 1181system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency 1182system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency 1183system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency 1184system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency 1185system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency 1186system.l2c.overall_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency | 1135system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171110152435 # number of overall MSHR uncacheable cycles 1136system.l2c.overall_mshr_uncacheable_latency::total 184524186173 # number of overall MSHR uncacheable cycles 1137system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses 1138system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for ReadReq accesses 1139system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for ReadReq accesses 1140system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036720 # mshr miss rate for ReadReq accesses 1141system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for ReadReq accesses 1142system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for ReadReq accesses 1143system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030405 # mshr miss rate for ReadReq accesses 1144system.l2c.ReadReq_mshr_miss_rate::total 0.017630 # mshr miss rate for ReadReq accesses 1145system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.792848 # mshr miss rate for UpgradeReq accesses 1146system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836509 # mshr miss rate for UpgradeReq accesses 1147system.l2c.UpgradeReq_mshr_miss_rate::total 0.810762 # mshr miss rate for UpgradeReq accesses 1148system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756272 # mshr miss rate for SCUpgradeReq accesses 1149system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses 1150system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753758 # mshr miss rate for SCUpgradeReq accesses 1151system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566902 # mshr miss rate for ReadExReq accesses 1152system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567738 # mshr miss rate for ReadExReq accesses 1153system.l2c.ReadExReq_mshr_miss_rate::total 0.567361 # mshr miss rate for ReadExReq accesses 1154system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for demand accesses 1155system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for demand accesses 1156system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for demand accesses 1157system.l2c.demand_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for demand accesses 1158system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for demand accesses 1159system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for demand accesses 1160system.l2c.demand_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for demand accesses 1161system.l2c.demand_mshr_miss_rate::total 0.098774 # mshr miss rate for demand accesses 1162system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for overall accesses 1163system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for overall accesses 1164system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for overall accesses 1165system.l2c.overall_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for overall accesses 1166system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for overall accesses 1167system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for overall accesses 1168system.l2c.overall_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for overall accesses 1169system.l2c.overall_mshr_miss_rate::total 0.098774 # mshr miss rate for overall accesses 1170system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average ReadReq mshr miss latency 1171system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average ReadReq mshr miss latency 1172system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average ReadReq mshr miss latency 1173system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62578.188661 # average ReadReq mshr miss latency 1174system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average ReadReq mshr miss latency 1175system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average ReadReq mshr miss latency 1176system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.487138 # average ReadReq mshr miss latency 1177system.l2c.ReadReq_avg_mshr_miss_latency::total 62839.467228 # average ReadReq mshr miss latency 1178system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.691291 # average UpgradeReq mshr miss latency 1179system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10093.271186 # average UpgradeReq mshr miss latency 1180system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10051.992377 # average UpgradeReq mshr miss latency 1181system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.216430 # average SCUpgradeReq mshr miss latency 1182system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10048.609524 # average SCUpgradeReq mshr miss latency 1183system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10028.535613 # average SCUpgradeReq mshr miss latency 1184system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57372.440322 # average ReadExReq mshr miss latency 1185system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68943.264778 # average ReadExReq mshr miss latency 1186system.l2c.ReadExReq_avg_mshr_miss_latency::total 63723.943645 # average ReadExReq mshr miss latency 1187system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency 1188system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency 1189system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency 1190system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency 1191system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency 1192system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency 1193system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency 1194system.l2c.demand_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency 1195system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency 1196system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency 1197system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency 1198system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency 1199system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency 1200system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency 1201system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency 1202system.l2c.overall_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency |
| 1187system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1188system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1189system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1190system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1191system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1192system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1193system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1194system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1199system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1200system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1201system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1202system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1203system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1204system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1205system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1206system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 1203system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1205system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1206system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1207system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1208system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1209system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1210system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1215system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1216system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1217system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1218system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1219system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1220system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1221system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1222system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 1207system.toL2Bus.throughput 136691596 # Throughput (bytes/s) 1208system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution 1209system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution 1210system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution 1211system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution 1212system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution 1213system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution 1214system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution 1215system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution 1216system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution 1217system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution 1218system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) 1219system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) 1220system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) 1221system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) 1222system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) 1223system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) 1224system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) 1225system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) 1226system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) 1227system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) 1228system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) 1229system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) 1230system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) 1231system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) 1232system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) 1233system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) 1234system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) 1235system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) 1236system.toL2Bus.data_through_bus 146211713 # Total data (bytes) 1237system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) 1238system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) | 1223system.toL2Bus.throughput 136617428 # Throughput (bytes/s) 1224system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution 1225system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution 1226system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution 1227system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution 1228system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution 1229system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution 1230system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution 1231system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution 1232system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution 1233system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution 1234system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes) 1235system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes) 1236system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes) 1237system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes) 1238system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes) 1239system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes) 1240system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes) 1241system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes) 1242system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes) 1243system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes) 1244system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes) 1245system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes) 1246system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes) 1247system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes) 1248system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes) 1249system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes) 1250system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes) 1251system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes) 1252system.toL2Bus.data_through_bus 146120255 # Total data (bytes) 1253system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes) 1254system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks) |
| 1239system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) | 1255system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) |
| 1240system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) | 1256system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks) |
| 1241system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) | 1257system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1242system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) | 1258system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks) |
| 1243system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1259system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1244system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) | 1260system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks) |
| 1245system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1261system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1246system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) | 1262system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks) |
| 1247system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1263system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1248system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) | 1264system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks) |
| 1249system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) | 1265system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) |
| 1250system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) | 1266system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks) |
| 1251system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) | 1267system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) |
| 1252system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) | 1268system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks) |
| 1253system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) | 1269system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) |
| 1254system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) | 1270system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks) |
| 1255system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) | 1271system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) |
| 1256system.iobus.throughput 46298101 # Throughput (bytes/s) 1257system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution 1258system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution 1259system.iobus.trans_dist::WriteReq 7950 # Transaction distribution 1260system.iobus.trans_dist::WriteResp 7950 # Transaction distribution 1261system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) | 1272system.iobus.throughput 46298079 # Throughput (bytes/s) 1273system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution 1274system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution 1275system.iobus.trans_dist::WriteReq 7945 # Transaction distribution 1276system.iobus.trans_dist::WriteResp 7945 # Transaction distribution 1277system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes) |
| 1262system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) 1263system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1264system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) 1265system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1266system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1267system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) 1268system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1269system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1276system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1277system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1278system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1279system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1280system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1281system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1282system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1283system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 1278system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) 1279system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1280system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) 1281system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1282system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1283system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) 1284system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1285system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1292system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1293system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1294system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1295system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1296system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1297system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1298system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1299system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 1284system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) | 1300system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes) |
| 1285system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) 1286system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) | 1301system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) 1302system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) |
| 1287system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) 1288system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) | 1303system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes) 1304system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes) |
| 1289system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) 1290system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1291system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) 1292system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1293system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1294system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) 1295system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1296system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1303system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1304system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1305system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1306system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1307system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1308system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1309system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1310system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1305system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) 1306system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1307system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) 1308system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1309system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1310system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) 1311system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1312system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1319system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1320system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1321system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1322system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1323system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1324system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1325system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1326system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 1311system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) | 1327system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes) |
| 1312system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) 1313system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) | 1328system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) 1329system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) |
| 1314system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) 1315system.iobus.data_through_bus 51148565 # Total data (bytes) 1316system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) | 1330system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes) 1331system.iobus.data_through_bus 51148551 # Total data (bytes) 1332system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks) |
| 1317system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1318system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) 1319system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1320system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1321system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1322system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks) 1323system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1324system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) --- 31 unchanged lines hidden (view full) --- 1356system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1357system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1358system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1359system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1360system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1361system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1362system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) 1363system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) | 1333system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1334system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) 1335system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1336system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1337system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1338system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks) 1339system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1340system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) --- 31 unchanged lines hidden (view full) --- 1372system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1373system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1374system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1375system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1376system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1377system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1378system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) 1379system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) |
| 1364system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) | 1380system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks) |
| 1365system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) | 1381system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1366system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) | 1382system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks) |
| 1367system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) | 1383system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) |
| 1368system.cpu0.branchPred.lookups 6002691 # Number of BP lookups 1369system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted 1370system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect 1371system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups 1372system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits | 1384system.cpu0.branchPred.lookups 5998612 # Number of BP lookups 1385system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted 1386system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect 1387system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups 1388system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits |
| 1373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1389system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1374system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage 1375system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. 1376system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. | 1390system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage 1391system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target. 1392system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions. |
| 1377system.cpu0.dtb.inst_hits 0 # ITB inst hits 1378system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1393system.cpu0.dtb.inst_hits 0 # ITB inst hits 1394system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1379system.cpu0.dtb.read_hits 8905508 # DTB read hits 1380system.cpu0.dtb.read_misses 28991 # DTB read misses 1381system.cpu0.dtb.write_hits 5140500 # DTB write hits 1382system.cpu0.dtb.write_misses 5723 # DTB write misses | 1395system.cpu0.dtb.read_hits 8906772 # DTB read hits 1396system.cpu0.dtb.read_misses 28714 # DTB read misses 1397system.cpu0.dtb.write_hits 5141355 # DTB write hits 1398system.cpu0.dtb.write_misses 5491 # DTB write misses |
| 1383system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1384system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1385system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1386system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1399system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1400system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1401system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1402system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1387system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB 1388system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions 1389system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch | 1403system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB 1404system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions 1405system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch |
| 1390system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1406system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1391system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions 1392system.cpu0.dtb.read_accesses 8934499 # DTB read accesses 1393system.cpu0.dtb.write_accesses 5146223 # DTB write accesses | 1407system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions 1408system.cpu0.dtb.read_accesses 8935486 # DTB read accesses 1409system.cpu0.dtb.write_accesses 5146846 # DTB write accesses |
| 1394system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1410system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1395system.cpu0.dtb.hits 14046008 # DTB hits 1396system.cpu0.dtb.misses 34714 # DTB misses 1397system.cpu0.dtb.accesses 14080722 # DTB accesses 1398system.cpu0.itb.inst_hits 4219281 # ITB inst hits 1399system.cpu0.itb.inst_misses 5089 # ITB inst misses | 1411system.cpu0.dtb.hits 14048127 # DTB hits 1412system.cpu0.dtb.misses 34205 # DTB misses 1413system.cpu0.dtb.accesses 14082332 # DTB accesses 1414system.cpu0.itb.inst_hits 4217878 # ITB inst hits 1415system.cpu0.itb.inst_misses 5102 # ITB inst misses |
| 1400system.cpu0.itb.read_hits 0 # DTB read hits 1401system.cpu0.itb.read_misses 0 # DTB read misses 1402system.cpu0.itb.write_hits 0 # DTB write hits 1403system.cpu0.itb.write_misses 0 # DTB write misses 1404system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1405system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1406system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1407system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1416system.cpu0.itb.read_hits 0 # DTB read hits 1417system.cpu0.itb.read_misses 0 # DTB read misses 1418system.cpu0.itb.write_hits 0 # DTB write hits 1419system.cpu0.itb.write_misses 0 # DTB write misses 1420system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1421system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1422system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1423system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1408system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB | 1424system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB |
| 1409system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1410system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1411system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1425system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1426system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1427system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1412system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions | 1428system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions |
| 1413system.cpu0.itb.read_accesses 0 # DTB read accesses 1414system.cpu0.itb.write_accesses 0 # DTB write accesses | 1429system.cpu0.itb.read_accesses 0 # DTB read accesses 1430system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1415system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses 1416system.cpu0.itb.hits 4219281 # DTB hits 1417system.cpu0.itb.misses 5089 # DTB misses 1418system.cpu0.itb.accesses 4224370 # DTB accesses 1419system.cpu0.numCycles 69432037 # number of cpu cycles simulated | 1431system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses 1432system.cpu0.itb.hits 4217878 # DTB hits 1433system.cpu0.itb.misses 5102 # DTB misses 1434system.cpu0.itb.accesses 4222980 # DTB accesses 1435system.cpu0.numCycles 69399845 # number of cpu cycles simulated |
| 1420system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1421system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1436system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1437system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1422system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss 1423system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed 1424system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered 1425system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken 1426system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked 1427system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing 1428system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb 1429system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked 1430system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1431system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps 1432system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions 1433system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR 1434system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched 1435system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed 1436system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed 1437system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) 1438system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) 1439system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) | 1438system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss 1439system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed 1440system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered 1441system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken 1442system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked 1443system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing 1444system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb 1445system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked 1446system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1447system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps 1448system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions 1449system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR 1450system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched 1451system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed 1452system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed 1453system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total) 1454system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total) 1455system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total) |
| 1440system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1456system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1441system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) 1442system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) 1443system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) 1444system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) 1445system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) 1446system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) 1447system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) 1448system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) 1449system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) | 1457system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total) 1458system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total) 1459system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total) 1460system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total) 1461system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total) 1462system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total) 1463system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total) 1464system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total) 1465system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total) |
| 1450system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1451system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1452system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1466system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1467system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1468system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1453system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) 1454system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle 1455system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle 1456system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle 1457system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked 1458system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running 1459system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking 1460system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing 1461system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch 1462system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction 1463system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode 1464system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode 1465system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing 1466system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle 1467system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking 1468system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst 1469system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running 1470system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking 1471system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename 1472system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full 1473system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full 1474system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full 1475system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers 1476system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed 1477system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made 1478system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups 1479system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups 1480system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed 1481system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing 1482system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed 1483system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed 1484system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer 1485system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. 1486system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. 1487system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. 1488system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. 1489system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) 1490system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ 1491system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued 1492system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued 1493system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling 1494system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph 1495system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed 1496system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle 1497system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle 1498system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle | 1469system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total) 1470system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle 1471system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle 1472system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle 1473system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked 1474system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running 1475system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking 1476system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing 1477system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch 1478system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction 1479system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode 1480system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode 1481system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing 1482system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle 1483system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking 1484system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst 1485system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running 1486system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking 1487system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename 1488system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full 1489system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full 1490system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full 1491system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers 1492system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed 1493system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made 1494system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups 1495system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups 1496system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed 1497system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing 1498system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed 1499system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed 1500system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer 1501system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit. 1502system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit. 1503system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads. 1504system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores. 1505system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec) 1506system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ 1507system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued 1508system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued 1509system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling 1510system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph 1511system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed 1512system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle 1513system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle 1514system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle |
| 1499system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1515system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1500system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle 1501system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle 1502system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle 1503system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle 1504system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle 1505system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle 1506system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle 1507system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle 1508system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle | 1516system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle 1517system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle 1518system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle 1519system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle 1520system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle 1521system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle 1522system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle 1523system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle 1524system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle |
| 1509system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1510system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1511system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1525system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1526system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1527system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1512system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle | 1528system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle |
| 1513system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1529system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1514system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available 1515system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available 1516system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 1517system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 1518system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 1519system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 1520system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 1521system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 1522system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 1523system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 1524system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 1525system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 1526system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 1527system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 1528system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 1529system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 1530system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 1531system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 1532system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 1533system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 1534system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 1535system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 1536system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 1537system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 1538system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 1539system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 1540system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 1541system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 1542system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 1543system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available 1544system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available | 1530system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available 1531system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available 1532system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available 1533system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available 1534system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available 1535system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available 1536system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available 1537system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available 1538system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available 1539system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available 1540system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available 1541system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available 1542system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available 1543system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available 1544system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available 1545system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available 1546system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available 1547system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available 1548system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available 1549system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available 1550system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available 1551system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available 1552system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available 1553system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available 1554system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available 1555system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available 1556system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available 1557system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available 1558system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available 1559system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available 1560system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available |
| 1545system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1546system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1561system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1562system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1547system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued 1548system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued 1549system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued 1550system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued 1551system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued 1552system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued 1553system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued 1554system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued 1555system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued 1556system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued 1557system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued 1558system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued 1559system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued 1560system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued 1561system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued 1562system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued 1563system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued 1564system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued 1565system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued 1566system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued 1567system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued 1568system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued 1569system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued 1570system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued 1571system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued 1572system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued | 1563system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued 1564system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued 1565system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued 1566system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued 1567system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued 1568system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued 1569system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued 1570system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued 1571system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued 1572system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued 1573system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued 1574system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued 1575system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued 1576system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued 1577system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued 1578system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued 1579system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued 1580system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued 1581system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued 1582system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued 1583system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued 1584system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued 1585system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued 1586system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued 1587system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued 1588system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued |
| 1573system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued 1574system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued | 1589system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued 1590system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued |
| 1575system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued | 1591system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued |
| 1576system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued | 1592system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued |
| 1577system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued 1578system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued | 1593system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued 1594system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued |
| 1579system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1580system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1595system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1596system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1581system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued 1582system.cpu0.iq.rate 0.536304 # Inst issue rate 1583system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested 1584system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) 1585system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads 1586system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes 1587system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses 1588system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads 1589system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes 1590system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses 1591system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses 1592system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses 1593system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores | 1597system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued 1598system.cpu0.iq.rate 0.536728 # Inst issue rate 1599system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested 1600system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst) 1601system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads 1602system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes 1603system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses 1604system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads 1605system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes 1606system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses 1607system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses 1608system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses 1609system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores |
| 1594system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1610system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1595system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed 1596system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed 1597system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations 1598system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed | 1611system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed 1612system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed 1613system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations 1614system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed |
| 1599system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1600system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1615system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1616system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1601system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled 1602system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked | 1617system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled 1618system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked |
| 1603system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1619system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1604system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing 1605system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking 1606system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking 1607system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ 1608system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch 1609system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions 1610system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions 1611system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions 1612system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall 1613system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall 1614system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations 1615system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly 1616system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly 1617system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute 1618system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions 1619system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed 1620system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute | 1620system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing 1621system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking 1622system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking 1623system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ 1624system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch 1625system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions 1626system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions 1627system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions 1628system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall 1629system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall 1630system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations 1631system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly 1632system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly 1633system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute 1634system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions 1635system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed 1636system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute |
| 1621system.cpu0.iew.exec_swp 0 # number of swp insts executed | 1637system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 1622system.cpu0.iew.exec_nop 117808 # number of nop insts executed 1623system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed 1624system.cpu0.iew.exec_branches 4853789 # Number of branches executed 1625system.cpu0.iew.exec_stores 5400460 # Number of stores executed 1626system.cpu0.iew.exec_rate 0.530865 # Inst execution rate 1627system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit 1628system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back 1629system.cpu0.iew.wb_producers 18306413 # num instructions producing a value 1630system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value | 1638system.cpu0.iew.exec_nop 117147 # number of nop insts executed 1639system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed 1640system.cpu0.iew.exec_branches 4855012 # Number of branches executed 1641system.cpu0.iew.exec_stores 5401246 # Number of stores executed 1642system.cpu0.iew.exec_rate 0.531281 # Inst execution rate 1643system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit 1644system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back 1645system.cpu0.iew.wb_producers 18314277 # num instructions producing a value 1646system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value |
| 1631system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1647system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1632system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle 1633system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back | 1648system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle 1649system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back |
| 1634system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1650system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1635system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit 1636system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards 1637system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted 1638system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle 1639system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle 1640system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle | 1651system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit 1652system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards 1653system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted 1654system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle 1655system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle 1656system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle |
| 1641system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1657system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1642system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle 1643system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle 1644system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle 1645system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle 1646system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle 1647system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle 1648system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle 1649system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle 1650system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle | 1658system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle 1659system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle 1660system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle 1661system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle 1662system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle 1663system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle 1664system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle 1665system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle 1666system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle |
| 1651system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1652system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1653system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1667system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1668system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1669system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1654system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle 1655system.cpu0.commit.committedInsts 23683551 # Number of instructions committed 1656system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed | 1670system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle 1671system.cpu0.commit.committedInsts 23685352 # Number of instructions committed 1672system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed |
| 1657system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 1673system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 1658system.cpu0.commit.refs 11428643 # Number of memory references committed 1659system.cpu0.commit.loads 6277598 # Number of loads committed 1660system.cpu0.commit.membars 229694 # Number of memory barriers committed 1661system.cpu0.commit.branches 4245889 # Number of branches committed | 1674system.cpu0.commit.refs 11431143 # Number of memory references committed 1675system.cpu0.commit.loads 6279002 # Number of loads committed 1676system.cpu0.commit.membars 229688 # Number of memory barriers committed 1677system.cpu0.commit.branches 4246153 # Number of branches committed |
| 1662system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. | 1678system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. |
| 1663system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. 1664system.cpu0.commit.function_calls 489416 # Number of function calls committed. 1665system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached | 1679system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions. 1680system.cpu0.commit.function_calls 489419 # Number of function calls committed. 1681system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached |
| 1666system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 1682system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1667system.cpu0.rob.rob_reads 75750709 # The number of ROB reads 1668system.cpu0.rob.rob_writes 75732466 # The number of ROB writes 1669system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself 1670system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling 1671system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1672system.cpu0.committedInsts 23602809 # Number of Instructions Simulated 1673system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated 1674system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated 1675system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction 1676system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads 1677system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle 1678system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads 1679system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads 1680system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes 1681system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads 1682system.cpu0.fp_regfile_writes 886 # number of floating regfile writes 1683system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads 1684system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes 1685system.cpu0.icache.tags.replacements 392605 # number of replacements 1686system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use 1687system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. 1688system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. 1689system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. 1690system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. 1691system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor 1692system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy 1693system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy 1694system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits 1695system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits 1696system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits 1697system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits 1698system.cpu0.icache.overall_hits::cpu0.inst 3793600 # number of overall hits 1699system.cpu0.icache.overall_hits::total 3793600 # number of overall hits 1700system.cpu0.icache.ReadReq_misses::cpu0.inst 423979 # number of ReadReq misses 1701system.cpu0.icache.ReadReq_misses::total 423979 # number of ReadReq misses 1702system.cpu0.icache.demand_misses::cpu0.inst 423979 # number of demand (read+write) misses 1703system.cpu0.icache.demand_misses::total 423979 # number of demand (read+write) misses 1704system.cpu0.icache.overall_misses::cpu0.inst 423979 # number of overall misses 1705system.cpu0.icache.overall_misses::total 423979 # number of overall misses 1706system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5892352014 # number of ReadReq miss cycles 1707system.cpu0.icache.ReadReq_miss_latency::total 5892352014 # number of ReadReq miss cycles 1708system.cpu0.icache.demand_miss_latency::cpu0.inst 5892352014 # number of demand (read+write) miss cycles 1709system.cpu0.icache.demand_miss_latency::total 5892352014 # number of demand (read+write) miss cycles 1710system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles 1711system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles 1712system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) 1713system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) 1714system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses 1715system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses 1716system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses 1717system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses 1718system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses 1719system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses 1720system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses 1721system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses 1722system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses 1723system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses 1724system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency 1725system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency 1726system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency 1727system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency 1728system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency 1729system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency 1730system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked | 1683system.cpu0.rob.rob_reads 75718589 # The number of ROB reads 1684system.cpu0.rob.rob_writes 75736714 # The number of ROB writes 1685system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself 1686system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling 1687system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1688system.cpu0.committedInsts 23604610 # Number of Instructions Simulated 1689system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated 1690system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated 1691system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction 1692system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads 1693system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle 1694system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads 1695system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads 1696system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes 1697system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads 1698system.cpu0.fp_regfile_writes 904 # number of floating regfile writes 1699system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads 1700system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes 1701system.cpu0.icache.tags.replacements 392190 # number of replacements 1702system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use 1703system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. 1704system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks. 1705system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks. 1706system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit. 1707system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor 1708system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy 1709system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy 1710system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits 1711system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits 1712system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits 1713system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits 1714system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits 1715system.cpu0.icache.overall_hits::total 3792228 # number of overall hits 1716system.cpu0.icache.ReadReq_misses::cpu0.inst 423961 # number of ReadReq misses 1717system.cpu0.icache.ReadReq_misses::total 423961 # number of ReadReq misses 1718system.cpu0.icache.demand_misses::cpu0.inst 423961 # number of demand (read+write) misses 1719system.cpu0.icache.demand_misses::total 423961 # number of demand (read+write) misses 1720system.cpu0.icache.overall_misses::cpu0.inst 423961 # number of overall misses 1721system.cpu0.icache.overall_misses::total 423961 # number of overall misses 1722system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5895815248 # number of ReadReq miss cycles 1723system.cpu0.icache.ReadReq_miss_latency::total 5895815248 # number of ReadReq miss cycles 1724system.cpu0.icache.demand_miss_latency::cpu0.inst 5895815248 # number of demand (read+write) miss cycles 1725system.cpu0.icache.demand_miss_latency::total 5895815248 # number of demand (read+write) miss cycles 1726system.cpu0.icache.overall_miss_latency::cpu0.inst 5895815248 # number of overall miss cycles 1727system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles 1728system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses) 1729system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses) 1730system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses 1731system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses 1732system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses 1733system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses 1734system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses 1735system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses 1736system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses 1737system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses 1738system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses 1739system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses 1740system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13906.503777 # average ReadReq miss latency 1741system.cpu0.icache.ReadReq_avg_miss_latency::total 13906.503777 # average ReadReq miss latency 1742system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency 1743system.cpu0.icache.demand_avg_miss_latency::total 13906.503777 # average overall miss latency 1744system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency 1745system.cpu0.icache.overall_avg_miss_latency::total 13906.503777 # average overall miss latency 1746system.cpu0.icache.blocked_cycles::no_mshrs 3717 # number of cycles access was blocked |
| 1731system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1747system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1732system.cpu0.icache.blocked::no_mshrs 164 # number of cycles access was blocked | 1748system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked |
| 1733system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 1749system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1734system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.182927 # average number of cycles each access was blocked | 1750system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.362069 # average number of cycles each access was blocked |
| 1735system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1736system.cpu0.icache.fast_writes 0 # number of fast writes performed 1737system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1751system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1752system.cpu0.icache.fast_writes 0 # number of fast writes performed 1753system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1738system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30839 # number of ReadReq MSHR hits 1739system.cpu0.icache.ReadReq_mshr_hits::total 30839 # number of ReadReq MSHR hits 1740system.cpu0.icache.demand_mshr_hits::cpu0.inst 30839 # number of demand (read+write) MSHR hits 1741system.cpu0.icache.demand_mshr_hits::total 30839 # number of demand (read+write) MSHR hits 1742system.cpu0.icache.overall_mshr_hits::cpu0.inst 30839 # number of overall MSHR hits 1743system.cpu0.icache.overall_mshr_hits::total 30839 # number of overall MSHR hits 1744system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393140 # number of ReadReq MSHR misses 1745system.cpu0.icache.ReadReq_mshr_misses::total 393140 # number of ReadReq MSHR misses 1746system.cpu0.icache.demand_mshr_misses::cpu0.inst 393140 # number of demand (read+write) MSHR misses 1747system.cpu0.icache.demand_mshr_misses::total 393140 # number of demand (read+write) MSHR misses 1748system.cpu0.icache.overall_mshr_misses::cpu0.inst 393140 # number of overall MSHR misses 1749system.cpu0.icache.overall_mshr_misses::total 393140 # number of overall MSHR misses 1750system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4794002596 # number of ReadReq MSHR miss cycles 1751system.cpu0.icache.ReadReq_mshr_miss_latency::total 4794002596 # number of ReadReq MSHR miss cycles 1752system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4794002596 # number of demand (read+write) MSHR miss cycles 1753system.cpu0.icache.demand_mshr_miss_latency::total 4794002596 # number of demand (read+write) MSHR miss cycles 1754system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4794002596 # number of overall MSHR miss cycles 1755system.cpu0.icache.overall_mshr_miss_latency::total 4794002596 # number of overall MSHR miss cycles 1756system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923000 # number of ReadReq MSHR uncacheable cycles 1757system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923000 # number of ReadReq MSHR uncacheable cycles 1758system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923000 # number of overall MSHR uncacheable cycles 1759system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923000 # number of overall MSHR uncacheable cycles 1760system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for ReadReq accesses 1761system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093215 # mshr miss rate for ReadReq accesses 1762system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for demand accesses 1763system.cpu0.icache.demand_mshr_miss_rate::total 0.093215 # mshr miss rate for demand accesses 1764system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for overall accesses 1765system.cpu0.icache.overall_mshr_miss_rate::total 0.093215 # mshr miss rate for overall accesses 1766system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average ReadReq mshr miss latency 1767system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12194.135921 # average ReadReq mshr miss latency 1768system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency 1769system.cpu0.icache.demand_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency 1770system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency 1771system.cpu0.icache.overall_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency | 1754system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31238 # number of ReadReq MSHR hits 1755system.cpu0.icache.ReadReq_mshr_hits::total 31238 # number of ReadReq MSHR hits 1756system.cpu0.icache.demand_mshr_hits::cpu0.inst 31238 # number of demand (read+write) MSHR hits 1757system.cpu0.icache.demand_mshr_hits::total 31238 # number of demand (read+write) MSHR hits 1758system.cpu0.icache.overall_mshr_hits::cpu0.inst 31238 # number of overall MSHR hits 1759system.cpu0.icache.overall_mshr_hits::total 31238 # number of overall MSHR hits 1760system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392723 # number of ReadReq MSHR misses 1761system.cpu0.icache.ReadReq_mshr_misses::total 392723 # number of ReadReq MSHR misses 1762system.cpu0.icache.demand_mshr_misses::cpu0.inst 392723 # number of demand (read+write) MSHR misses 1763system.cpu0.icache.demand_mshr_misses::total 392723 # number of demand (read+write) MSHR misses 1764system.cpu0.icache.overall_mshr_misses::cpu0.inst 392723 # number of overall MSHR misses 1765system.cpu0.icache.overall_mshr_misses::total 392723 # number of overall MSHR misses 1766system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4798060362 # number of ReadReq MSHR miss cycles 1767system.cpu0.icache.ReadReq_mshr_miss_latency::total 4798060362 # number of ReadReq MSHR miss cycles 1768system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4798060362 # number of demand (read+write) MSHR miss cycles 1769system.cpu0.icache.demand_mshr_miss_latency::total 4798060362 # number of demand (read+write) MSHR miss cycles 1770system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4798060362 # number of overall MSHR miss cycles 1771system.cpu0.icache.overall_mshr_miss_latency::total 4798060362 # number of overall MSHR miss cycles 1772system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923500 # number of ReadReq MSHR uncacheable cycles 1773system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923500 # number of ReadReq MSHR uncacheable cycles 1774system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923500 # number of overall MSHR uncacheable cycles 1775system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923500 # number of overall MSHR uncacheable cycles 1776system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for ReadReq accesses 1777system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093146 # mshr miss rate for ReadReq accesses 1778system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for demand accesses 1779system.cpu0.icache.demand_mshr_miss_rate::total 0.093146 # mshr miss rate for demand accesses 1780system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for overall accesses 1781system.cpu0.icache.overall_mshr_miss_rate::total 0.093146 # mshr miss rate for overall accesses 1782system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average ReadReq mshr miss latency 1783system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.416250 # average ReadReq mshr miss latency 1784system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency 1785system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency 1786system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency 1787system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency |
| 1772system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1773system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1774system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1775system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1776system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1788system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1789system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1790system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1791system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1792system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1777system.cpu0.dcache.tags.replacements 276287 # number of replacements 1778system.cpu0.dcache.tags.tagsinuse 459.684046 # Cycle average of tags in use 1779system.cpu0.dcache.tags.total_refs 9258198 # Total number of references to valid blocks. 1780system.cpu0.dcache.tags.sampled_refs 276799 # Sample count of references to valid blocks. 1781system.cpu0.dcache.tags.avg_refs 33.447368 # Average number of references to valid blocks. | 1793system.cpu0.dcache.tags.replacements 276315 # number of replacements 1794system.cpu0.dcache.tags.tagsinuse 459.475838 # Cycle average of tags in use 1795system.cpu0.dcache.tags.total_refs 9261350 # Total number of references to valid blocks. 1796system.cpu0.dcache.tags.sampled_refs 276827 # Sample count of references to valid blocks. 1797system.cpu0.dcache.tags.avg_refs 33.455371 # Average number of references to valid blocks. |
| 1782system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. | 1798system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. |
| 1783system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.684046 # Average occupied blocks per requestor 1784system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897820 # Average percentage of cache occupancy 1785system.cpu0.dcache.tags.occ_percent::total 0.897820 # Average percentage of cache occupancy 1786system.cpu0.dcache.ReadReq_hits::cpu0.data 5778274 # number of ReadReq hits 1787system.cpu0.dcache.ReadReq_hits::total 5778274 # number of ReadReq hits 1788system.cpu0.dcache.WriteReq_hits::cpu0.data 3158747 # number of WriteReq hits 1789system.cpu0.dcache.WriteReq_hits::total 3158747 # number of WriteReq hits 1790system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139141 # number of LoadLockedReq hits 1791system.cpu0.dcache.LoadLockedReq_hits::total 139141 # number of LoadLockedReq hits 1792system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137092 # number of StoreCondReq hits 1793system.cpu0.dcache.StoreCondReq_hits::total 137092 # number of StoreCondReq hits 1794system.cpu0.dcache.demand_hits::cpu0.data 8937021 # number of demand (read+write) hits 1795system.cpu0.dcache.demand_hits::total 8937021 # number of demand (read+write) hits 1796system.cpu0.dcache.overall_hits::cpu0.data 8937021 # number of overall hits 1797system.cpu0.dcache.overall_hits::total 8937021 # number of overall hits 1798system.cpu0.dcache.ReadReq_misses::cpu0.data 392090 # number of ReadReq misses 1799system.cpu0.dcache.ReadReq_misses::total 392090 # number of ReadReq misses 1800system.cpu0.dcache.WriteReq_misses::cpu0.data 1584925 # number of WriteReq misses 1801system.cpu0.dcache.WriteReq_misses::total 1584925 # number of WriteReq misses 1802system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8730 # number of LoadLockedReq misses 1803system.cpu0.dcache.LoadLockedReq_misses::total 8730 # number of LoadLockedReq misses 1804system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7451 # number of StoreCondReq misses 1805system.cpu0.dcache.StoreCondReq_misses::total 7451 # number of StoreCondReq misses 1806system.cpu0.dcache.demand_misses::cpu0.data 1977015 # number of demand (read+write) misses 1807system.cpu0.dcache.demand_misses::total 1977015 # number of demand (read+write) misses 1808system.cpu0.dcache.overall_misses::cpu0.data 1977015 # number of overall misses 1809system.cpu0.dcache.overall_misses::total 1977015 # number of overall misses 1810system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5539255201 # number of ReadReq miss cycles 1811system.cpu0.dcache.ReadReq_miss_latency::total 5539255201 # number of ReadReq miss cycles 1812system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79907349135 # number of WriteReq miss cycles 1813system.cpu0.dcache.WriteReq_miss_latency::total 79907349135 # number of WriteReq miss cycles 1814system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90050735 # number of LoadLockedReq miss cycles 1815system.cpu0.dcache.LoadLockedReq_miss_latency::total 90050735 # number of LoadLockedReq miss cycles 1816system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45818635 # number of StoreCondReq miss cycles 1817system.cpu0.dcache.StoreCondReq_miss_latency::total 45818635 # number of StoreCondReq miss cycles 1818system.cpu0.dcache.demand_miss_latency::cpu0.data 85446604336 # number of demand (read+write) miss cycles 1819system.cpu0.dcache.demand_miss_latency::total 85446604336 # number of demand (read+write) miss cycles 1820system.cpu0.dcache.overall_miss_latency::cpu0.data 85446604336 # number of overall miss cycles 1821system.cpu0.dcache.overall_miss_latency::total 85446604336 # number of overall miss cycles 1822system.cpu0.dcache.ReadReq_accesses::cpu0.data 6170364 # number of ReadReq accesses(hits+misses) 1823system.cpu0.dcache.ReadReq_accesses::total 6170364 # number of ReadReq accesses(hits+misses) 1824system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743672 # number of WriteReq accesses(hits+misses) 1825system.cpu0.dcache.WriteReq_accesses::total 4743672 # number of WriteReq accesses(hits+misses) 1826system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147871 # number of LoadLockedReq accesses(hits+misses) 1827system.cpu0.dcache.LoadLockedReq_accesses::total 147871 # number of LoadLockedReq accesses(hits+misses) 1828system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144543 # number of StoreCondReq accesses(hits+misses) 1829system.cpu0.dcache.StoreCondReq_accesses::total 144543 # number of StoreCondReq accesses(hits+misses) 1830system.cpu0.dcache.demand_accesses::cpu0.data 10914036 # number of demand (read+write) accesses 1831system.cpu0.dcache.demand_accesses::total 10914036 # number of demand (read+write) accesses 1832system.cpu0.dcache.overall_accesses::cpu0.data 10914036 # number of overall (read+write) accesses 1833system.cpu0.dcache.overall_accesses::total 10914036 # number of overall (read+write) accesses 1834system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063544 # miss rate for ReadReq accesses 1835system.cpu0.dcache.ReadReq_miss_rate::total 0.063544 # miss rate for ReadReq accesses 1836system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334114 # miss rate for WriteReq accesses 1837system.cpu0.dcache.WriteReq_miss_rate::total 0.334114 # miss rate for WriteReq accesses 1838system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059038 # miss rate for LoadLockedReq accesses 1839system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059038 # miss rate for LoadLockedReq accesses 1840system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051549 # miss rate for StoreCondReq accesses 1841system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051549 # miss rate for StoreCondReq accesses 1842system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181144 # miss rate for demand accesses 1843system.cpu0.dcache.demand_miss_rate::total 0.181144 # miss rate for demand accesses 1844system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181144 # miss rate for overall accesses 1845system.cpu0.dcache.overall_miss_rate::total 0.181144 # miss rate for overall accesses 1846system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14127.509503 # average ReadReq miss latency 1847system.cpu0.dcache.ReadReq_avg_miss_latency::total 14127.509503 # average ReadReq miss latency 1848system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50417.116983 # average WriteReq miss latency 1849system.cpu0.dcache.WriteReq_avg_miss_latency::total 50417.116983 # average WriteReq miss latency 1850system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10315.089920 # average LoadLockedReq miss latency 1851system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10315.089920 # average LoadLockedReq miss latency 1852system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6149.326936 # average StoreCondReq miss latency 1853system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6149.326936 # average StoreCondReq miss latency 1854system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency 1855system.cpu0.dcache.demand_avg_miss_latency::total 43220.008111 # average overall miss latency 1856system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency 1857system.cpu0.dcache.overall_avg_miss_latency::total 43220.008111 # average overall miss latency 1858system.cpu0.dcache.blocked_cycles::no_mshrs 9481 # number of cycles access was blocked 1859system.cpu0.dcache.blocked_cycles::no_targets 10276 # number of cycles access was blocked 1860system.cpu0.dcache.blocked::no_mshrs 609 # number of cycles access was blocked 1861system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked 1862system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.568144 # average number of cycles each access was blocked 1863system.cpu0.dcache.avg_blocked_cycles::no_targets 78.442748 # average number of cycles each access was blocked | 1799system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor 1800system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy 1801system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy 1802system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits 1803system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits 1804system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits 1805system.cpu0.dcache.WriteReq_hits::total 3158881 # number of WriteReq hits 1806system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139214 # number of LoadLockedReq hits 1807system.cpu0.dcache.LoadLockedReq_hits::total 139214 # number of LoadLockedReq hits 1808system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137082 # number of StoreCondReq hits 1809system.cpu0.dcache.StoreCondReq_hits::total 137082 # number of StoreCondReq hits 1810system.cpu0.dcache.demand_hits::cpu0.data 8940115 # number of demand (read+write) hits 1811system.cpu0.dcache.demand_hits::total 8940115 # number of demand (read+write) hits 1812system.cpu0.dcache.overall_hits::cpu0.data 8940115 # number of overall hits 1813system.cpu0.dcache.overall_hits::total 8940115 # number of overall hits 1814system.cpu0.dcache.ReadReq_misses::cpu0.data 391237 # number of ReadReq misses 1815system.cpu0.dcache.ReadReq_misses::total 391237 # number of ReadReq misses 1816system.cpu0.dcache.WriteReq_misses::cpu0.data 1585894 # number of WriteReq misses 1817system.cpu0.dcache.WriteReq_misses::total 1585894 # number of WriteReq misses 1818system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8707 # number of LoadLockedReq misses 1819system.cpu0.dcache.LoadLockedReq_misses::total 8707 # number of LoadLockedReq misses 1820system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses 1821system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses 1822system.cpu0.dcache.demand_misses::cpu0.data 1977131 # number of demand (read+write) misses 1823system.cpu0.dcache.demand_misses::total 1977131 # number of demand (read+write) misses 1824system.cpu0.dcache.overall_misses::cpu0.data 1977131 # number of overall misses 1825system.cpu0.dcache.overall_misses::total 1977131 # number of overall misses 1826system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519617945 # number of ReadReq miss cycles 1827system.cpu0.dcache.ReadReq_miss_latency::total 5519617945 # number of ReadReq miss cycles 1828system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79664471073 # number of WriteReq miss cycles 1829system.cpu0.dcache.WriteReq_miss_latency::total 79664471073 # number of WriteReq miss cycles 1830system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90084987 # number of LoadLockedReq miss cycles 1831system.cpu0.dcache.LoadLockedReq_miss_latency::total 90084987 # number of LoadLockedReq miss cycles 1832system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45897132 # number of StoreCondReq miss cycles 1833system.cpu0.dcache.StoreCondReq_miss_latency::total 45897132 # number of StoreCondReq miss cycles 1834system.cpu0.dcache.demand_miss_latency::cpu0.data 85184089018 # number of demand (read+write) miss cycles 1835system.cpu0.dcache.demand_miss_latency::total 85184089018 # number of demand (read+write) miss cycles 1836system.cpu0.dcache.overall_miss_latency::cpu0.data 85184089018 # number of overall miss cycles 1837system.cpu0.dcache.overall_miss_latency::total 85184089018 # number of overall miss cycles 1838system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172471 # number of ReadReq accesses(hits+misses) 1839system.cpu0.dcache.ReadReq_accesses::total 6172471 # number of ReadReq accesses(hits+misses) 1840system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744775 # number of WriteReq accesses(hits+misses) 1841system.cpu0.dcache.WriteReq_accesses::total 4744775 # number of WriteReq accesses(hits+misses) 1842system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147921 # number of LoadLockedReq accesses(hits+misses) 1843system.cpu0.dcache.LoadLockedReq_accesses::total 147921 # number of LoadLockedReq accesses(hits+misses) 1844system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144548 # number of StoreCondReq accesses(hits+misses) 1845system.cpu0.dcache.StoreCondReq_accesses::total 144548 # number of StoreCondReq accesses(hits+misses) 1846system.cpu0.dcache.demand_accesses::cpu0.data 10917246 # number of demand (read+write) accesses 1847system.cpu0.dcache.demand_accesses::total 10917246 # number of demand (read+write) accesses 1848system.cpu0.dcache.overall_accesses::cpu0.data 10917246 # number of overall (read+write) accesses 1849system.cpu0.dcache.overall_accesses::total 10917246 # number of overall (read+write) accesses 1850system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063384 # miss rate for ReadReq accesses 1851system.cpu0.dcache.ReadReq_miss_rate::total 0.063384 # miss rate for ReadReq accesses 1852system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334240 # miss rate for WriteReq accesses 1853system.cpu0.dcache.WriteReq_miss_rate::total 0.334240 # miss rate for WriteReq accesses 1854system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.058863 # miss rate for LoadLockedReq accesses 1855system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058863 # miss rate for LoadLockedReq accesses 1856system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051651 # miss rate for StoreCondReq accesses 1857system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051651 # miss rate for StoreCondReq accesses 1858system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181102 # miss rate for demand accesses 1859system.cpu0.dcache.demand_miss_rate::total 0.181102 # miss rate for demand accesses 1860system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181102 # miss rate for overall accesses 1861system.cpu0.dcache.overall_miss_rate::total 0.181102 # miss rate for overall accesses 1862system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14108.118468 # average ReadReq miss latency 1863system.cpu0.dcache.ReadReq_avg_miss_latency::total 14108.118468 # average ReadReq miss latency 1864system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50233.162540 # average WriteReq miss latency 1865system.cpu0.dcache.WriteReq_avg_miss_latency::total 50233.162540 # average WriteReq miss latency 1866system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency 1867system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency 1868system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency 1869system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency 1870system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency 1871system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency 1872system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency 1873system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency 1874system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked 1875system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked 1876system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked 1877system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked 1878system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked 1879system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked |
| 1864system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1865system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1880system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1881system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1866system.cpu0.dcache.writebacks::writebacks 256484 # number of writebacks 1867system.cpu0.dcache.writebacks::total 256484 # number of writebacks 1868system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203289 # number of ReadReq MSHR hits 1869system.cpu0.dcache.ReadReq_mshr_hits::total 203289 # number of ReadReq MSHR hits 1870system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454440 # number of WriteReq MSHR hits 1871system.cpu0.dcache.WriteReq_mshr_hits::total 1454440 # number of WriteReq MSHR hits 1872system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 445 # number of LoadLockedReq MSHR hits 1873system.cpu0.dcache.LoadLockedReq_mshr_hits::total 445 # number of LoadLockedReq MSHR hits 1874system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657729 # number of demand (read+write) MSHR hits 1875system.cpu0.dcache.demand_mshr_hits::total 1657729 # number of demand (read+write) MSHR hits 1876system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657729 # number of overall MSHR hits 1877system.cpu0.dcache.overall_mshr_hits::total 1657729 # number of overall MSHR hits 1878system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188801 # number of ReadReq MSHR misses 1879system.cpu0.dcache.ReadReq_mshr_misses::total 188801 # number of ReadReq MSHR misses 1880system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130485 # number of WriteReq MSHR misses 1881system.cpu0.dcache.WriteReq_mshr_misses::total 130485 # number of WriteReq MSHR misses 1882system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8285 # number of LoadLockedReq MSHR misses 1883system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8285 # number of LoadLockedReq MSHR misses 1884system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7449 # number of StoreCondReq MSHR misses 1885system.cpu0.dcache.StoreCondReq_mshr_misses::total 7449 # number of StoreCondReq MSHR misses 1886system.cpu0.dcache.demand_mshr_misses::cpu0.data 319286 # number of demand (read+write) MSHR misses 1887system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses 1888system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses 1889system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses 1890system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles 1891system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles 1892system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles 1893system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles 1894system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles 1895system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles 1896system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30919365 # number of StoreCondReq MSHR miss cycles 1897system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30919365 # number of StoreCondReq MSHR miss cycles 1898system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7730077043 # number of demand (read+write) MSHR miss cycles 1899system.cpu0.dcache.demand_mshr_miss_latency::total 7730077043 # number of demand (read+write) MSHR miss cycles 1900system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7730077043 # number of overall MSHR miss cycles 1901system.cpu0.dcache.overall_mshr_miss_latency::total 7730077043 # number of overall MSHR miss cycles 1902system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504888791 # number of ReadReq MSHR uncacheable cycles 1903system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504888791 # number of ReadReq MSHR uncacheable cycles 1904system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131913883 # number of WriteReq MSHR uncacheable cycles 1905system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131913883 # number of WriteReq MSHR uncacheable cycles 1906system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636802674 # number of overall MSHR uncacheable cycles 1907system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636802674 # number of overall MSHR uncacheable cycles 1908system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030598 # mshr miss rate for ReadReq accesses 1909system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030598 # mshr miss rate for ReadReq accesses | 1882system.cpu0.dcache.writebacks::writebacks 256502 # number of writebacks 1883system.cpu0.dcache.writebacks::total 256502 # number of writebacks 1884system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202469 # number of ReadReq MSHR hits 1885system.cpu0.dcache.ReadReq_mshr_hits::total 202469 # number of ReadReq MSHR hits 1886system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455378 # number of WriteReq MSHR hits 1887system.cpu0.dcache.WriteReq_mshr_hits::total 1455378 # number of WriteReq MSHR hits 1888system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits 1889system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits 1890system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657847 # number of demand (read+write) MSHR hits 1891system.cpu0.dcache.demand_mshr_hits::total 1657847 # number of demand (read+write) MSHR hits 1892system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657847 # number of overall MSHR hits 1893system.cpu0.dcache.overall_mshr_hits::total 1657847 # number of overall MSHR hits 1894system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188768 # number of ReadReq MSHR misses 1895system.cpu0.dcache.ReadReq_mshr_misses::total 188768 # number of ReadReq MSHR misses 1896system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130516 # number of WriteReq MSHR misses 1897system.cpu0.dcache.WriteReq_mshr_misses::total 130516 # number of WriteReq MSHR misses 1898system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8280 # number of LoadLockedReq MSHR misses 1899system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8280 # number of LoadLockedReq MSHR misses 1900system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7466 # number of StoreCondReq MSHR misses 1901system.cpu0.dcache.StoreCondReq_mshr_misses::total 7466 # number of StoreCondReq MSHR misses 1902system.cpu0.dcache.demand_mshr_misses::cpu0.data 319284 # number of demand (read+write) MSHR misses 1903system.cpu0.dcache.demand_mshr_misses::total 319284 # number of demand (read+write) MSHR misses 1904system.cpu0.dcache.overall_mshr_misses::cpu0.data 319284 # number of overall MSHR misses 1905system.cpu0.dcache.overall_mshr_misses::total 319284 # number of overall MSHR misses 1906system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2415025620 # number of ReadReq MSHR miss cycles 1907system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2415025620 # number of ReadReq MSHR miss cycles 1908system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5290299960 # number of WriteReq MSHR miss cycles 1909system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5290299960 # number of WriteReq MSHR miss cycles 1910system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68915513 # number of LoadLockedReq MSHR miss cycles 1911system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68915513 # number of LoadLockedReq MSHR miss cycles 1912system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30963868 # number of StoreCondReq MSHR miss cycles 1913system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30963868 # number of StoreCondReq MSHR miss cycles 1914system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7705325580 # number of demand (read+write) MSHR miss cycles 1915system.cpu0.dcache.demand_mshr_miss_latency::total 7705325580 # number of demand (read+write) MSHR miss cycles 1916system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7705325580 # number of overall MSHR miss cycles 1917system.cpu0.dcache.overall_mshr_miss_latency::total 7705325580 # number of overall MSHR miss cycles 1918system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504357282 # number of ReadReq MSHR uncacheable cycles 1919system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504357282 # number of ReadReq MSHR uncacheable cycles 1920system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131166881 # number of WriteReq MSHR uncacheable cycles 1921system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131166881 # number of WriteReq MSHR uncacheable cycles 1922system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14635524163 # number of overall MSHR uncacheable cycles 1923system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14635524163 # number of overall MSHR uncacheable cycles 1924system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030582 # mshr miss rate for ReadReq accesses 1925system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030582 # mshr miss rate for ReadReq accesses |
| 1910system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses 1911system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses | 1926system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses 1927system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses |
| 1912system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses 1913system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses 1914system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses 1915system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses 1916system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses 1917system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses 1918system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses 1919system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses 1920system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency 1921system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency 1922system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency 1923system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency 1924system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency 1925system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency 1926system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency 1927system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency 1928system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency 1929system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency 1930system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency 1931system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency | 1928system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses 1929system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses 1930system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses 1931system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses 1932system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses 1933system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses 1934system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses 1935system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses 1936system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency 1937system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency 1938system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency 1939system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency 1940system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency 1941system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency 1942system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency 1943system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency 1944system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency 1945system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency 1946system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency 1947system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency |
| 1932system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1933system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1934system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1935system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1936system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1937system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1938system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1948system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1949system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1950system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1951system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1952system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1953system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1954system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1939system.cpu1.branchPred.lookups 8781819 # Number of BP lookups 1940system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted 1941system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect 1942system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups 1943system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits | 1955system.cpu1.branchPred.lookups 8777296 # Number of BP lookups 1956system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted 1957system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect 1958system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups 1959system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits |
| 1944system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1960system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1945system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage 1946system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. 1947system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. | 1961system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage 1962system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target. 1963system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions. |
| 1948system.cpu1.dtb.inst_hits 0 # ITB inst hits 1949system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1964system.cpu1.dtb.inst_hits 0 # ITB inst hits 1965system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1950system.cpu1.dtb.read_hits 42694682 # DTB read hits 1951system.cpu1.dtb.read_misses 36199 # DTB read misses 1952system.cpu1.dtb.write_hits 6825983 # DTB write hits 1953system.cpu1.dtb.write_misses 10603 # DTB write misses | 1966system.cpu1.dtb.read_hits 42697243 # DTB read hits 1967system.cpu1.dtb.read_misses 36228 # DTB read misses 1968system.cpu1.dtb.write_hits 6821056 # DTB write hits 1969system.cpu1.dtb.write_misses 10680 # DTB write misses |
| 1954system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1955system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1956system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1957system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1970system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1971system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1972system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1973system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1958system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB 1959system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions 1960system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch | 1974system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB 1975system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions 1976system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch |
| 1961system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1977system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1962system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions 1963system.cpu1.dtb.read_accesses 42730881 # DTB read accesses 1964system.cpu1.dtb.write_accesses 6836586 # DTB write accesses | 1978system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions 1979system.cpu1.dtb.read_accesses 42733471 # DTB read accesses 1980system.cpu1.dtb.write_accesses 6831736 # DTB write accesses |
| 1965system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1981system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1966system.cpu1.dtb.hits 49520665 # DTB hits 1967system.cpu1.dtb.misses 46802 # DTB misses 1968system.cpu1.dtb.accesses 49567467 # DTB accesses 1969system.cpu1.itb.inst_hits 7578103 # ITB inst hits 1970system.cpu1.itb.inst_misses 5415 # ITB inst misses | 1982system.cpu1.dtb.hits 49518299 # DTB hits 1983system.cpu1.dtb.misses 46908 # DTB misses 1984system.cpu1.dtb.accesses 49565207 # DTB accesses 1985system.cpu1.itb.inst_hits 7578630 # ITB inst hits 1986system.cpu1.itb.inst_misses 5358 # ITB inst misses |
| 1971system.cpu1.itb.read_hits 0 # DTB read hits 1972system.cpu1.itb.read_misses 0 # DTB read misses 1973system.cpu1.itb.write_hits 0 # DTB write hits 1974system.cpu1.itb.write_misses 0 # DTB write misses 1975system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1976system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1977system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1978system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1987system.cpu1.itb.read_hits 0 # DTB read hits 1988system.cpu1.itb.read_misses 0 # DTB read misses 1989system.cpu1.itb.write_hits 0 # DTB write hits 1990system.cpu1.itb.write_misses 0 # DTB write misses 1991system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1992system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1993system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1994system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1979system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB | 1995system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB |
| 1980system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1981system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1982system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1996system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1997system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1998system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1983system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions | 1999system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions |
| 1984system.cpu1.itb.read_accesses 0 # DTB read accesses 1985system.cpu1.itb.write_accesses 0 # DTB write accesses | 2000system.cpu1.itb.read_accesses 0 # DTB read accesses 2001system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1986system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses 1987system.cpu1.itb.hits 7578103 # DTB hits 1988system.cpu1.itb.misses 5415 # DTB misses 1989system.cpu1.itb.accesses 7583518 # DTB accesses 1990system.cpu1.numCycles 409882606 # number of cpu cycles simulated | 2002system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses 2003system.cpu1.itb.hits 7578630 # DTB hits 2004system.cpu1.itb.misses 5358 # DTB misses 2005system.cpu1.itb.accesses 7583988 # DTB accesses 2006system.cpu1.numCycles 409868912 # number of cpu cycles simulated |
| 1991system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1992system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 2007system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2008system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1993system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss 1994system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed 1995system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered 1996system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken 1997system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked 1998system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing 1999system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb 2000system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked 2001system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2002system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps 2003system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions 2004system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR 2005system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched 2006system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed 2007system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed 2008system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) 2009system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) 2010system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) | 2009system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss 2010system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed 2011system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered 2012system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken 2013system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked 2014system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing 2015system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb 2016system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked 2017system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2018system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps 2019system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions 2020system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR 2021system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched 2022system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed 2023system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed 2024system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total) 2025system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total) 2026system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total) |
| 2011system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 2027system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 2012system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) 2013system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) 2014system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) 2015system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) 2016system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) 2017system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) 2018system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) 2019system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) 2020system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) | 2028system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total) 2029system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total) 2030system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total) 2031system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total) 2032system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total) 2033system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total) 2034system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total) 2035system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total) 2036system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total) |
| 2021system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2022system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2023system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 2037system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2038system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2039system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 2024system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) 2025system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle 2026system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle 2027system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle 2028system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked 2029system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running 2030system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking 2031system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing 2032system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch 2033system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction 2034system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode 2035system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode 2036system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing 2037system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle 2038system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking 2039system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst 2040system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running 2041system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking 2042system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename 2043system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full 2044system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full 2045system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full 2046system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers 2047system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed 2048system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made 2049system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups 2050system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups 2051system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed 2052system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing 2053system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed 2054system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed 2055system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer 2056system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. 2057system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. 2058system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. 2059system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. 2060system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) 2061system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ 2062system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued 2063system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued 2064system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling 2065system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph 2066system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed 2067system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle 2068system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle 2069system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle | 2040system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total) 2041system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle 2042system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle 2043system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle 2044system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked 2045system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running 2046system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking 2047system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing 2048system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch 2049system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction 2050system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode 2051system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode 2052system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing 2053system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle 2054system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking 2055system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst 2056system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running 2057system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking 2058system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename 2059system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full 2060system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full 2061system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full 2062system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers 2063system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed 2064system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made 2065system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups 2066system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups 2067system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed 2068system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing 2069system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed 2070system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed 2071system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer 2072system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit. 2073system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit. 2074system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads. 2075system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores. 2076system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec) 2077system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ 2078system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued 2079system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued 2080system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling 2081system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph 2082system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed 2083system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle 2084system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle 2085system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle |
| 2070system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 2086system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 2071system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle 2072system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle 2073system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle 2074system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle 2075system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle 2076system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle 2077system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle 2078system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle 2079system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle | 2087system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle 2088system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle 2089system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle 2090system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle 2091system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle 2092system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle 2093system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle 2094system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle 2095system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle |
| 2080system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2081system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2082system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 2096system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2097system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2098system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 2083system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle | 2099system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle |
| 2084system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 2100system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 2085system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available 2086system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available | 2101system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available 2102system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available |
| 2087system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 2088system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 2089system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2090system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2091system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 2092system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2093system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 2094system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 2106system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 2107system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2108system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2109system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2110system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 2111system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 2112system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 2113system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available | 2103system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 2104system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 2105system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2106system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2107system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 2108system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2109system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 2110system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 2122system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 2123system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2124system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2125system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2126system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 2127system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 2128system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 2129system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available |
| 2114system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available 2115system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available | 2130system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available 2131system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available |
| 2116system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2117system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2118system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued | 2132system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2133system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2134system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued |
| 2119system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued 2120system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued | 2135system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued 2136system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued |
| 2121system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued 2122system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued 2123system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued 2124system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued 2125system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued 2126system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued 2127system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued 2128system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued 2129system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued 2130system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued 2131system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued 2132system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued | 2137system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued 2138system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued 2139system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued 2140system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued 2141system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued 2142system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued 2143system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued 2144system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued 2145system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued 2146system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued 2147system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued 2148system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued |
| 2133system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued | 2149system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued |
| 2134system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued 2135system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued | 2150system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued 2151system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued |
| 2136system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued 2137system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued | 2152system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued 2153system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued |
| 2138system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued 2139system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued 2140system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued 2141system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued 2142system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued 2143system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued | 2154system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued 2155system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued 2156system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued 2157system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued 2158system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued 2159system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued |
| 2144system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued 2145system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued 2146system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued 2147system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued 2148system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued 2149system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued | 2160system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued 2161system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued 2162system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued 2163system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued 2164system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued 2165system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued |
| 2150system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2151system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2166system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2167system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2152system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued 2153system.cpu1.iq.rate 0.214022 # Inst issue rate 2154system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested 2155system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) 2156system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads 2157system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes 2158system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses 2159system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads 2160system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes 2161system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses 2162system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses 2163system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses 2164system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores | 2168system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued 2169system.cpu1.iq.rate 0.214000 # Inst issue rate 2170system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested 2171system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst) 2172system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads 2173system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes 2174system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses 2175system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads 2176system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes 2177system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses 2178system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses 2179system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses 2180system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores |
| 2165system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2181system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2166system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed 2167system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed 2168system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations 2169system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed | 2182system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed 2183system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed 2184system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations 2185system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed |
| 2170system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2171system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2186system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2187system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2172system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled 2173system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked | 2188system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled 2189system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked |
| 2174system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2190system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2175system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing 2176system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking 2177system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking 2178system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ 2179system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch 2180system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions 2181system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions 2182system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions 2183system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall 2184system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall 2185system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations 2186system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly 2187system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly 2188system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute 2189system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions 2190system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed 2191system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute | 2191system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing 2192system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking 2193system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking 2194system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ 2195system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch 2196system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions 2197system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions 2198system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions 2199system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall 2200system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall 2201system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations 2202system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly 2203system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly 2204system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute 2205system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions 2206system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed 2207system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute |
| 2192system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2208system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2193system.cpu1.iew.exec_nop 104661 # number of nop insts executed 2194system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed 2195system.cpu1.iew.exec_branches 6911907 # Number of branches executed 2196system.cpu1.iew.exec_stores 7112224 # Number of stores executed 2197system.cpu1.iew.exec_rate 0.209814 # Inst execution rate 2198system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit 2199system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back 2200system.cpu1.iew.wb_producers 29713379 # num instructions producing a value 2201system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value | 2209system.cpu1.iew.exec_nop 104468 # number of nop insts executed 2210system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed 2211system.cpu1.iew.exec_branches 6912361 # Number of branches executed 2212system.cpu1.iew.exec_stores 7107436 # Number of stores executed 2213system.cpu1.iew.exec_rate 0.209797 # Inst execution rate 2214system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit 2215system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back 2216system.cpu1.iew.wb_producers 29705560 # num instructions producing a value 2217system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value |
| 2202system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2218system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2203system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle 2204system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back | 2219system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle 2220system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back |
| 2205system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2221system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2206system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit 2207system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards 2208system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted 2209system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle 2210system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle 2211system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle | 2222system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit 2223system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards 2224system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted 2225system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle 2226system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle 2227system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle |
| 2212system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2228system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2213system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle 2214system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle 2215system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle 2216system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle 2217system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle 2218system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle 2219system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle 2220system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle 2221system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle | 2229system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle 2230system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle 2231system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle 2232system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle 2233system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle 2234system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle 2235system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle 2236system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle 2237system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle |
| 2222system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2223system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2224system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2238system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2239system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2240system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2225system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle 2226system.cpu1.commit.committedInsts 38065083 # Number of instructions committed 2227system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed | 2241system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle 2242system.cpu1.commit.committedInsts 38065286 # Number of instructions committed 2243system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed |
| 2228system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2244system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2229system.cpu1.commit.refs 16595520 # Number of memory references committed 2230system.cpu1.commit.loads 9755460 # Number of loads committed | 2245system.cpu1.commit.refs 16595591 # Number of memory references committed 2246system.cpu1.commit.loads 9755506 # Number of loads committed |
| 2231system.cpu1.commit.membars 190120 # Number of memory barriers committed | 2247system.cpu1.commit.membars 190120 # Number of memory barriers committed |
| 2232system.cpu1.commit.branches 5967695 # Number of branches committed | 2248system.cpu1.commit.branches 5967745 # Number of branches committed |
| 2233system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. | 2249system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. |
| 2234system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. 2235system.cpu1.commit.function_calls 534629 # Number of function calls committed. 2236system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached | 2250system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions. 2251system.cpu1.commit.function_calls 534627 # Number of function calls committed. 2252system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached |
| 2237system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 2253system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2238system.cpu1.rob.rob_reads 170710273 # The number of ROB reads 2239system.cpu1.rob.rob_writes 125186848 # The number of ROB writes 2240system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself 2241system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling 2242system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2243system.cpu1.committedInsts 37995444 # Number of Instructions Simulated 2244system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated 2245system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated 2246system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction 2247system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads 2248system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle 2249system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads 2250system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads 2251system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes 2252system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads 2253system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes 2254system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads 2255system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes 2256system.cpu1.icache.tags.replacements 596659 # number of replacements 2257system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use 2258system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. 2259system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. 2260system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. 2261system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. 2262system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor 2263system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy 2264system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy 2265system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits 2266system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits 2267system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits 2268system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits 2269system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits 2270system.cpu1.icache.overall_hits::total 6934084 # number of overall hits 2271system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses 2272system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses 2273system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses 2274system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses 2275system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses 2276system.cpu1.icache.overall_misses::total 642197 # number of overall misses 2277system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles 2278system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles 2279system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles 2280system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles 2281system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles 2282system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles 2283system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) 2284system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) 2285system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses 2286system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses 2287system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses 2288system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses 2289system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses 2290system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses 2291system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084764 # miss rate for demand accesses 2292system.cpu1.icache.demand_miss_rate::total 0.084764 # miss rate for demand accesses 2293system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084764 # miss rate for overall accesses 2294system.cpu1.icache.overall_miss_rate::total 0.084764 # miss rate for overall accesses 2295system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612 # average ReadReq miss latency 2296system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612 # average ReadReq miss latency 2297system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency 2298system.cpu1.icache.demand_avg_miss_latency::total 13573.558612 # average overall miss latency 2299system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency 2300system.cpu1.icache.overall_avg_miss_latency::total 13573.558612 # average overall miss latency 2301system.cpu1.icache.blocked_cycles::no_mshrs 3156 # number of cycles access was blocked | 2254system.cpu1.rob.rob_reads 170668638 # The number of ROB reads 2255system.cpu1.rob.rob_writes 125130415 # The number of ROB writes 2256system.cpu1.timesIdled 1414400 # Number of times that the entire CPU went into an idle state and unscheduled itself 2257system.cpu1.idleCycles 295624990 # Total number of cycles that the CPU has spent unscheduled due to idling 2258system.cpu1.quiesceCycles 1799026779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2259system.cpu1.committedInsts 37995647 # Number of Instructions Simulated 2260system.cpu1.committedOps 48086899 # Number of Ops (including micro ops) Simulated 2261system.cpu1.committedInsts_total 37995647 # Number of Instructions Simulated 2262system.cpu1.cpi 10.787260 # CPI: Cycles Per Instruction 2263system.cpu1.cpi_total 10.787260 # CPI: Total CPI of All Threads 2264system.cpu1.ipc 0.092702 # IPC: Instructions Per Cycle 2265system.cpu1.ipc_total 0.092702 # IPC: Total IPC of All Threads 2266system.cpu1.int_regfile_reads 384897666 # number of integer regfile reads 2267system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes 2268system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads 2269system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes 2270system.cpu1.misc_regfile_reads 18454230 # number of misc regfile reads 2271system.cpu1.misc_regfile_writes 405462 # number of misc regfile writes 2272system.cpu1.icache.tags.replacements 595825 # number of replacements 2273system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use 2274system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks. 2275system.cpu1.icache.tags.sampled_refs 596337 # Sample count of references to valid blocks. 2276system.cpu1.icache.tags.avg_refs 11.630199 # Average number of references to valid blocks. 2277system.cpu1.icache.tags.warmup_cycle 74918873000 # Cycle when the warmup percentage was hit. 2278system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor 2279system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy 2280system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy 2281system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits 2282system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits 2283system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits 2284system.cpu1.icache.demand_hits::total 6935518 # number of demand (read+write) hits 2285system.cpu1.icache.overall_hits::cpu1.inst 6935518 # number of overall hits 2286system.cpu1.icache.overall_hits::total 6935518 # number of overall hits 2287system.cpu1.icache.ReadReq_misses::cpu1.inst 641267 # number of ReadReq misses 2288system.cpu1.icache.ReadReq_misses::total 641267 # number of ReadReq misses 2289system.cpu1.icache.demand_misses::cpu1.inst 641267 # number of demand (read+write) misses 2290system.cpu1.icache.demand_misses::total 641267 # number of demand (read+write) misses 2291system.cpu1.icache.overall_misses::cpu1.inst 641267 # number of overall misses 2292system.cpu1.icache.overall_misses::total 641267 # number of overall misses 2293system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8704460293 # number of ReadReq miss cycles 2294system.cpu1.icache.ReadReq_miss_latency::total 8704460293 # number of ReadReq miss cycles 2295system.cpu1.icache.demand_miss_latency::cpu1.inst 8704460293 # number of demand (read+write) miss cycles 2296system.cpu1.icache.demand_miss_latency::total 8704460293 # number of demand (read+write) miss cycles 2297system.cpu1.icache.overall_miss_latency::cpu1.inst 8704460293 # number of overall miss cycles 2298system.cpu1.icache.overall_miss_latency::total 8704460293 # number of overall miss cycles 2299system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576785 # number of ReadReq accesses(hits+misses) 2300system.cpu1.icache.ReadReq_accesses::total 7576785 # number of ReadReq accesses(hits+misses) 2301system.cpu1.icache.demand_accesses::cpu1.inst 7576785 # number of demand (read+write) accesses 2302system.cpu1.icache.demand_accesses::total 7576785 # number of demand (read+write) accesses 2303system.cpu1.icache.overall_accesses::cpu1.inst 7576785 # number of overall (read+write) accesses 2304system.cpu1.icache.overall_accesses::total 7576785 # number of overall (read+write) accesses 2305system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084636 # miss rate for ReadReq accesses 2306system.cpu1.icache.ReadReq_miss_rate::total 0.084636 # miss rate for ReadReq accesses 2307system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084636 # miss rate for demand accesses 2308system.cpu1.icache.demand_miss_rate::total 0.084636 # miss rate for demand accesses 2309system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084636 # miss rate for overall accesses 2310system.cpu1.icache.overall_miss_rate::total 0.084636 # miss rate for overall accesses 2311system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.847232 # average ReadReq miss latency 2312system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.847232 # average ReadReq miss latency 2313system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency 2314system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency 2315system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency 2316system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency 2317system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked |
| 2302system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2318system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2303system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked | 2319system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked |
| 2304system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 2320system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 2305system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked | 2321system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked |
| 2306system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2307system.cpu1.icache.fast_writes 0 # number of fast writes performed 2308system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2322system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2323system.cpu1.icache.fast_writes 0 # number of fast writes performed 2324system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2309system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits 2310system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits 2311system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits 2312system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits 2313system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits 2314system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits 2315system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses 2316system.cpu1.icache.ReadReq_mshr_misses::total 597210 # number of ReadReq MSHR misses 2317system.cpu1.icache.demand_mshr_misses::cpu1.inst 597210 # number of demand (read+write) MSHR misses 2318system.cpu1.icache.demand_mshr_misses::total 597210 # number of demand (read+write) MSHR misses 2319system.cpu1.icache.overall_mshr_misses::cpu1.inst 597210 # number of overall MSHR misses 2320system.cpu1.icache.overall_mshr_misses::total 597210 # number of overall MSHR misses 2321system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7115046481 # number of ReadReq MSHR miss cycles 2322system.cpu1.icache.ReadReq_mshr_miss_latency::total 7115046481 # number of ReadReq MSHR miss cycles 2323system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7115046481 # number of demand (read+write) MSHR miss cycles 2324system.cpu1.icache.demand_mshr_miss_latency::total 7115046481 # number of demand (read+write) MSHR miss cycles 2325system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7115046481 # number of overall MSHR miss cycles 2326system.cpu1.icache.overall_mshr_miss_latency::total 7115046481 # number of overall MSHR miss cycles | 2325system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44906 # number of ReadReq MSHR hits 2326system.cpu1.icache.ReadReq_mshr_hits::total 44906 # number of ReadReq MSHR hits 2327system.cpu1.icache.demand_mshr_hits::cpu1.inst 44906 # number of demand (read+write) MSHR hits 2328system.cpu1.icache.demand_mshr_hits::total 44906 # number of demand (read+write) MSHR hits 2329system.cpu1.icache.overall_mshr_hits::cpu1.inst 44906 # number of overall MSHR hits 2330system.cpu1.icache.overall_mshr_hits::total 44906 # number of overall MSHR hits 2331system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596361 # number of ReadReq MSHR misses 2332system.cpu1.icache.ReadReq_mshr_misses::total 596361 # number of ReadReq MSHR misses 2333system.cpu1.icache.demand_mshr_misses::cpu1.inst 596361 # number of demand (read+write) MSHR misses 2334system.cpu1.icache.demand_mshr_misses::total 596361 # number of demand (read+write) MSHR misses 2335system.cpu1.icache.overall_mshr_misses::cpu1.inst 596361 # number of overall MSHR misses 2336system.cpu1.icache.overall_mshr_misses::total 596361 # number of overall MSHR misses 2337system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7105400062 # number of ReadReq MSHR miss cycles 2338system.cpu1.icache.ReadReq_mshr_miss_latency::total 7105400062 # number of ReadReq MSHR miss cycles 2339system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7105400062 # number of demand (read+write) MSHR miss cycles 2340system.cpu1.icache.demand_mshr_miss_latency::total 7105400062 # number of demand (read+write) MSHR miss cycles 2341system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7105400062 # number of overall MSHR miss cycles 2342system.cpu1.icache.overall_mshr_miss_latency::total 7105400062 # number of overall MSHR miss cycles |
| 2327system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles 2328system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles 2329system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles 2330system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles | 2343system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles 2344system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles 2345system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles 2346system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles |
| 2331system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for ReadReq accesses 2332system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078826 # mshr miss rate for ReadReq accesses 2333system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for demand accesses 2334system.cpu1.icache.demand_mshr_miss_rate::total 0.078826 # mshr miss rate for demand accesses 2335system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for overall accesses 2336system.cpu1.icache.overall_mshr_miss_rate::total 0.078826 # mshr miss rate for overall accesses 2337system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average ReadReq mshr miss latency 2338system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018 # average ReadReq mshr miss latency 2339system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency 2340system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency 2341system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency 2342system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency | 2347system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for ReadReq accesses 2348system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078709 # mshr miss rate for ReadReq accesses 2349system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for demand accesses 2350system.cpu1.icache.demand_mshr_miss_rate::total 0.078709 # mshr miss rate for demand accesses 2351system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for overall accesses 2352system.cpu1.icache.overall_mshr_miss_rate::total 0.078709 # mshr miss rate for overall accesses 2353system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average ReadReq mshr miss latency 2354system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.595458 # average ReadReq mshr miss latency 2355system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency 2356system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency 2357system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency 2358system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency |
| 2343system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2344system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2345system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2346system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2347system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2359system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2360system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2361system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2362system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2363system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2348system.cpu1.dcache.tags.replacements 360813 # number of replacements 2349system.cpu1.dcache.tags.tagsinuse 473.792536 # Cycle average of tags in use 2350system.cpu1.dcache.tags.total_refs 12672687 # Total number of references to valid blocks. 2351system.cpu1.dcache.tags.sampled_refs 361164 # Sample count of references to valid blocks. 2352system.cpu1.dcache.tags.avg_refs 35.088456 # Average number of references to valid blocks. 2353system.cpu1.dcache.tags.warmup_cycle 70971728000 # Cycle when the warmup percentage was hit. 2354system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.792536 # Average occupied blocks per requestor 2355system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925376 # Average percentage of cache occupancy 2356system.cpu1.dcache.tags.occ_percent::total 0.925376 # Average percentage of cache occupancy 2357system.cpu1.dcache.ReadReq_hits::cpu1.data 8306232 # number of ReadReq hits 2358system.cpu1.dcache.ReadReq_hits::total 8306232 # number of ReadReq hits 2359system.cpu1.dcache.WriteReq_hits::cpu1.data 4138701 # number of WriteReq hits 2360system.cpu1.dcache.WriteReq_hits::total 4138701 # number of WriteReq hits 2361system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97355 # number of LoadLockedReq hits 2362system.cpu1.dcache.LoadLockedReq_hits::total 97355 # number of LoadLockedReq hits 2363system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94895 # number of StoreCondReq hits 2364system.cpu1.dcache.StoreCondReq_hits::total 94895 # number of StoreCondReq hits 2365system.cpu1.dcache.demand_hits::cpu1.data 12444933 # number of demand (read+write) hits 2366system.cpu1.dcache.demand_hits::total 12444933 # number of demand (read+write) hits 2367system.cpu1.dcache.overall_hits::cpu1.data 12444933 # number of overall hits 2368system.cpu1.dcache.overall_hits::total 12444933 # number of overall hits 2369system.cpu1.dcache.ReadReq_misses::cpu1.data 398716 # number of ReadReq misses 2370system.cpu1.dcache.ReadReq_misses::total 398716 # number of ReadReq misses 2371system.cpu1.dcache.WriteReq_misses::cpu1.data 1557859 # number of WriteReq misses 2372system.cpu1.dcache.WriteReq_misses::total 1557859 # number of WriteReq misses 2373system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses 2374system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses 2375system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10575 # number of StoreCondReq misses 2376system.cpu1.dcache.StoreCondReq_misses::total 10575 # number of StoreCondReq misses 2377system.cpu1.dcache.demand_misses::cpu1.data 1956575 # number of demand (read+write) misses 2378system.cpu1.dcache.demand_misses::total 1956575 # number of demand (read+write) misses 2379system.cpu1.dcache.overall_misses::cpu1.data 1956575 # number of overall misses 2380system.cpu1.dcache.overall_misses::total 1956575 # number of overall misses 2381system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6078170016 # number of ReadReq miss cycles 2382system.cpu1.dcache.ReadReq_miss_latency::total 6078170016 # number of ReadReq miss cycles 2383system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80199088679 # number of WriteReq miss cycles 2384system.cpu1.dcache.WriteReq_miss_latency::total 80199088679 # number of WriteReq miss cycles 2385system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128606244 # number of LoadLockedReq miss cycles 2386system.cpu1.dcache.LoadLockedReq_miss_latency::total 128606244 # number of LoadLockedReq miss cycles 2387system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52837907 # number of StoreCondReq miss cycles 2388system.cpu1.dcache.StoreCondReq_miss_latency::total 52837907 # number of StoreCondReq miss cycles 2389system.cpu1.dcache.demand_miss_latency::cpu1.data 86277258695 # number of demand (read+write) miss cycles 2390system.cpu1.dcache.demand_miss_latency::total 86277258695 # number of demand (read+write) miss cycles 2391system.cpu1.dcache.overall_miss_latency::cpu1.data 86277258695 # number of overall miss cycles 2392system.cpu1.dcache.overall_miss_latency::total 86277258695 # number of overall miss cycles 2393system.cpu1.dcache.ReadReq_accesses::cpu1.data 8704948 # number of ReadReq accesses(hits+misses) 2394system.cpu1.dcache.ReadReq_accesses::total 8704948 # number of ReadReq accesses(hits+misses) 2395system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696560 # number of WriteReq accesses(hits+misses) 2396system.cpu1.dcache.WriteReq_accesses::total 5696560 # number of WriteReq accesses(hits+misses) 2397system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111292 # number of LoadLockedReq accesses(hits+misses) 2398system.cpu1.dcache.LoadLockedReq_accesses::total 111292 # number of LoadLockedReq accesses(hits+misses) 2399system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105470 # number of StoreCondReq accesses(hits+misses) 2400system.cpu1.dcache.StoreCondReq_accesses::total 105470 # number of StoreCondReq accesses(hits+misses) 2401system.cpu1.dcache.demand_accesses::cpu1.data 14401508 # number of demand (read+write) accesses 2402system.cpu1.dcache.demand_accesses::total 14401508 # number of demand (read+write) accesses 2403system.cpu1.dcache.overall_accesses::cpu1.data 14401508 # number of overall (read+write) accesses 2404system.cpu1.dcache.overall_accesses::total 14401508 # number of overall (read+write) accesses 2405system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045803 # miss rate for ReadReq accesses 2406system.cpu1.dcache.ReadReq_miss_rate::total 0.045803 # miss rate for ReadReq accesses 2407system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273474 # miss rate for WriteReq accesses 2408system.cpu1.dcache.WriteReq_miss_rate::total 0.273474 # miss rate for WriteReq accesses 2409system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125229 # miss rate for LoadLockedReq accesses 2410system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125229 # miss rate for LoadLockedReq accesses 2411system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100265 # miss rate for StoreCondReq accesses 2412system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100265 # miss rate for StoreCondReq accesses 2413system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135859 # miss rate for demand accesses 2414system.cpu1.dcache.demand_miss_rate::total 0.135859 # miss rate for demand accesses 2415system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135859 # miss rate for overall accesses 2416system.cpu1.dcache.overall_miss_rate::total 0.135859 # miss rate for overall accesses 2417system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434 # average ReadReq miss latency 2418system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434 # average ReadReq miss latency 2419system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677 # average WriteReq miss latency 2420system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677 # average WriteReq miss latency 2421system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9227.684868 # average LoadLockedReq miss latency 2422system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9227.684868 # average LoadLockedReq miss latency 2423system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 4996.492388 # average StoreCondReq miss latency 2424system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4996.492388 # average StoreCondReq miss latency 2425system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency 2426system.cpu1.dcache.demand_avg_miss_latency::total 44096.065162 # average overall miss latency 2427system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency 2428system.cpu1.dcache.overall_avg_miss_latency::total 44096.065162 # average overall miss latency 2429system.cpu1.dcache.blocked_cycles::no_mshrs 31164 # number of cycles access was blocked 2430system.cpu1.dcache.blocked_cycles::no_targets 18449 # number of cycles access was blocked 2431system.cpu1.dcache.blocked::no_mshrs 3306 # number of cycles access was blocked 2432system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked 2433system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.426497 # average number of cycles each access was blocked 2434system.cpu1.dcache.avg_blocked_cycles::no_targets 111.138554 # average number of cycles each access was blocked | 2364system.cpu1.dcache.tags.replacements 360794 # number of replacements 2365system.cpu1.dcache.tags.tagsinuse 473.291027 # Cycle average of tags in use 2366system.cpu1.dcache.tags.total_refs 12676660 # Total number of references to valid blocks. 2367system.cpu1.dcache.tags.sampled_refs 361148 # Sample count of references to valid blocks. 2368system.cpu1.dcache.tags.avg_refs 35.101011 # Average number of references to valid blocks. 2369system.cpu1.dcache.tags.warmup_cycle 70967078000 # Cycle when the warmup percentage was hit. 2370system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.291027 # Average occupied blocks per requestor 2371system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924397 # Average percentage of cache occupancy 2372system.cpu1.dcache.tags.occ_percent::total 0.924397 # Average percentage of cache occupancy 2373system.cpu1.dcache.ReadReq_hits::cpu1.data 8309635 # number of ReadReq hits 2374system.cpu1.dcache.ReadReq_hits::total 8309635 # number of ReadReq hits 2375system.cpu1.dcache.WriteReq_hits::cpu1.data 4139080 # number of WriteReq hits 2376system.cpu1.dcache.WriteReq_hits::total 4139080 # number of WriteReq hits 2377system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97568 # number of LoadLockedReq hits 2378system.cpu1.dcache.LoadLockedReq_hits::total 97568 # number of LoadLockedReq hits 2379system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94890 # number of StoreCondReq hits 2380system.cpu1.dcache.StoreCondReq_hits::total 94890 # number of StoreCondReq hits 2381system.cpu1.dcache.demand_hits::cpu1.data 12448715 # number of demand (read+write) hits 2382system.cpu1.dcache.demand_hits::total 12448715 # number of demand (read+write) hits 2383system.cpu1.dcache.overall_hits::cpu1.data 12448715 # number of overall hits 2384system.cpu1.dcache.overall_hits::total 12448715 # number of overall hits 2385system.cpu1.dcache.ReadReq_misses::cpu1.data 397211 # number of ReadReq misses 2386system.cpu1.dcache.ReadReq_misses::total 397211 # number of ReadReq misses 2387system.cpu1.dcache.WriteReq_misses::cpu1.data 1557491 # number of WriteReq misses 2388system.cpu1.dcache.WriteReq_misses::total 1557491 # number of WriteReq misses 2389system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13987 # number of LoadLockedReq misses 2390system.cpu1.dcache.LoadLockedReq_misses::total 13987 # number of LoadLockedReq misses 2391system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10584 # number of StoreCondReq misses 2392system.cpu1.dcache.StoreCondReq_misses::total 10584 # number of StoreCondReq misses 2393system.cpu1.dcache.demand_misses::cpu1.data 1954702 # number of demand (read+write) misses 2394system.cpu1.dcache.demand_misses::total 1954702 # number of demand (read+write) misses 2395system.cpu1.dcache.overall_misses::cpu1.data 1954702 # number of overall misses 2396system.cpu1.dcache.overall_misses::total 1954702 # number of overall misses 2397system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6036826508 # number of ReadReq miss cycles 2398system.cpu1.dcache.ReadReq_miss_latency::total 6036826508 # number of ReadReq miss cycles 2399system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80166814063 # number of WriteReq miss cycles 2400system.cpu1.dcache.WriteReq_miss_latency::total 80166814063 # number of WriteReq miss cycles 2401system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129072992 # number of LoadLockedReq miss cycles 2402system.cpu1.dcache.LoadLockedReq_miss_latency::total 129072992 # number of LoadLockedReq miss cycles 2403system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53027415 # number of StoreCondReq miss cycles 2404system.cpu1.dcache.StoreCondReq_miss_latency::total 53027415 # number of StoreCondReq miss cycles 2405system.cpu1.dcache.demand_miss_latency::cpu1.data 86203640571 # number of demand (read+write) miss cycles 2406system.cpu1.dcache.demand_miss_latency::total 86203640571 # number of demand (read+write) miss cycles 2407system.cpu1.dcache.overall_miss_latency::cpu1.data 86203640571 # number of overall miss cycles 2408system.cpu1.dcache.overall_miss_latency::total 86203640571 # number of overall miss cycles 2409system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706846 # number of ReadReq accesses(hits+misses) 2410system.cpu1.dcache.ReadReq_accesses::total 8706846 # number of ReadReq accesses(hits+misses) 2411system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696571 # number of WriteReq accesses(hits+misses) 2412system.cpu1.dcache.WriteReq_accesses::total 5696571 # number of WriteReq accesses(hits+misses) 2413system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111555 # number of LoadLockedReq accesses(hits+misses) 2414system.cpu1.dcache.LoadLockedReq_accesses::total 111555 # number of LoadLockedReq accesses(hits+misses) 2415system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105474 # number of StoreCondReq accesses(hits+misses) 2416system.cpu1.dcache.StoreCondReq_accesses::total 105474 # number of StoreCondReq accesses(hits+misses) 2417system.cpu1.dcache.demand_accesses::cpu1.data 14403417 # number of demand (read+write) accesses 2418system.cpu1.dcache.demand_accesses::total 14403417 # number of demand (read+write) accesses 2419system.cpu1.dcache.overall_accesses::cpu1.data 14403417 # number of overall (read+write) accesses 2420system.cpu1.dcache.overall_accesses::total 14403417 # number of overall (read+write) accesses 2421system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045621 # miss rate for ReadReq accesses 2422system.cpu1.dcache.ReadReq_miss_rate::total 0.045621 # miss rate for ReadReq accesses 2423system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273409 # miss rate for WriteReq accesses 2424system.cpu1.dcache.WriteReq_miss_rate::total 0.273409 # miss rate for WriteReq accesses 2425system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125382 # miss rate for LoadLockedReq accesses 2426system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125382 # miss rate for LoadLockedReq accesses 2427system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100347 # miss rate for StoreCondReq accesses 2428system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100347 # miss rate for StoreCondReq accesses 2429system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses 2430system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses 2431system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses 2432system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses 2433system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15198.034566 # average ReadReq miss latency 2434system.cpu1.dcache.ReadReq_avg_miss_latency::total 15198.034566 # average ReadReq miss latency 2435system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51471.767133 # average WriteReq miss latency 2436system.cpu1.dcache.WriteReq_avg_miss_latency::total 51471.767133 # average WriteReq miss latency 2437system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9228.068349 # average LoadLockedReq miss latency 2438system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9228.068349 # average LoadLockedReq miss latency 2439system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5010.148810 # average StoreCondReq miss latency 2440system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5010.148810 # average StoreCondReq miss latency 2441system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency 2442system.cpu1.dcache.demand_avg_miss_latency::total 44100.656044 # average overall miss latency 2443system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency 2444system.cpu1.dcache.overall_avg_miss_latency::total 44100.656044 # average overall miss latency 2445system.cpu1.dcache.blocked_cycles::no_mshrs 29197 # number of cycles access was blocked 2446system.cpu1.dcache.blocked_cycles::no_targets 19426 # number of cycles access was blocked 2447system.cpu1.dcache.blocked::no_mshrs 3289 # number of cycles access was blocked 2448system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked 2449system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.877166 # average number of cycles each access was blocked 2450system.cpu1.dcache.avg_blocked_cycles::no_targets 115.630952 # average number of cycles each access was blocked |
| 2435system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2436system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2451system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2452system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2437system.cpu1.dcache.writebacks::writebacks 324902 # number of writebacks 2438system.cpu1.dcache.writebacks::total 324902 # number of writebacks 2439system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170345 # number of ReadReq MSHR hits 2440system.cpu1.dcache.ReadReq_mshr_hits::total 170345 # number of ReadReq MSHR hits 2441system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396167 # number of WriteReq MSHR hits 2442system.cpu1.dcache.WriteReq_mshr_hits::total 1396167 # number of WriteReq MSHR hits 2443system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1435 # number of LoadLockedReq MSHR hits 2444system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1435 # number of LoadLockedReq MSHR hits 2445system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566512 # number of demand (read+write) MSHR hits 2446system.cpu1.dcache.demand_mshr_hits::total 1566512 # number of demand (read+write) MSHR hits 2447system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566512 # number of overall MSHR hits 2448system.cpu1.dcache.overall_mshr_hits::total 1566512 # number of overall MSHR hits 2449system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228371 # number of ReadReq MSHR misses 2450system.cpu1.dcache.ReadReq_mshr_misses::total 228371 # number of ReadReq MSHR misses 2451system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161692 # number of WriteReq MSHR misses 2452system.cpu1.dcache.WriteReq_mshr_misses::total 161692 # number of WriteReq MSHR misses 2453system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12502 # number of LoadLockedReq MSHR misses 2454system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12502 # number of LoadLockedReq MSHR misses 2455system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10574 # number of StoreCondReq MSHR misses 2456system.cpu1.dcache.StoreCondReq_mshr_misses::total 10574 # number of StoreCondReq MSHR misses 2457system.cpu1.dcache.demand_mshr_misses::cpu1.data 390063 # number of demand (read+write) MSHR misses 2458system.cpu1.dcache.demand_mshr_misses::total 390063 # number of demand (read+write) MSHR misses 2459system.cpu1.dcache.overall_mshr_misses::cpu1.data 390063 # number of overall MSHR misses 2460system.cpu1.dcache.overall_mshr_misses::total 390063 # number of overall MSHR misses 2461system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2847018297 # number of ReadReq MSHR miss cycles 2462system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2847018297 # number of ReadReq MSHR miss cycles 2463system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7247965426 # number of WriteReq MSHR miss cycles 2464system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7247965426 # number of WriteReq MSHR miss cycles 2465system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87929505 # number of LoadLockedReq MSHR miss cycles 2466system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87929505 # number of LoadLockedReq MSHR miss cycles 2467system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31688093 # number of StoreCondReq MSHR miss cycles 2468system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31688093 # number of StoreCondReq MSHR miss cycles 2469system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10094983723 # number of demand (read+write) MSHR miss cycles 2470system.cpu1.dcache.demand_mshr_miss_latency::total 10094983723 # number of demand (read+write) MSHR miss cycles 2471system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10094983723 # number of overall MSHR miss cycles 2472system.cpu1.dcache.overall_mshr_miss_latency::total 10094983723 # number of overall MSHR miss cycles 2473system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261 # number of ReadReq MSHR uncacheable cycles 2474system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261 # number of ReadReq MSHR uncacheable cycles 2475system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25838951416 # number of WriteReq MSHR uncacheable cycles 2476system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25838951416 # number of WriteReq MSHR uncacheable cycles 2477system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677 # number of overall MSHR uncacheable cycles 2478system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677 # number of overall MSHR uncacheable cycles 2479system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for ReadReq accesses 2480system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses 2481system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses 2482system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses 2483system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses 2484system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses 2485system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses 2486system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses 2487system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses 2488system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses 2489system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for overall accesses 2490system.cpu1.dcache.overall_mshr_miss_rate::total 0.027085 # mshr miss rate for overall accesses 2491system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731 # average ReadReq mshr miss latency 2492system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731 # average ReadReq mshr miss latency 2493system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589 # average WriteReq mshr miss latency 2494system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589 # average WriteReq mshr miss latency 2495system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7033.235082 # average LoadLockedReq mshr miss latency 2496system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7033.235082 # average LoadLockedReq mshr miss latency 2497system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 2996.793361 # average StoreCondReq mshr miss latency 2498system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2996.793361 # average StoreCondReq mshr miss latency 2499system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency 2500system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency 2501system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency 2502system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency | 2453system.cpu1.dcache.writebacks::writebacks 324862 # number of writebacks 2454system.cpu1.dcache.writebacks::total 324862 # number of writebacks 2455system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168849 # number of ReadReq MSHR hits 2456system.cpu1.dcache.ReadReq_mshr_hits::total 168849 # number of ReadReq MSHR hits 2457system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395866 # number of WriteReq MSHR hits 2458system.cpu1.dcache.WriteReq_mshr_hits::total 1395866 # number of WriteReq MSHR hits 2459system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits 2460system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits 2461system.cpu1.dcache.demand_mshr_hits::cpu1.data 1564715 # number of demand (read+write) MSHR hits 2462system.cpu1.dcache.demand_mshr_hits::total 1564715 # number of demand (read+write) MSHR hits 2463system.cpu1.dcache.overall_mshr_hits::cpu1.data 1564715 # number of overall MSHR hits 2464system.cpu1.dcache.overall_mshr_hits::total 1564715 # number of overall MSHR hits 2465system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228362 # number of ReadReq MSHR misses 2466system.cpu1.dcache.ReadReq_mshr_misses::total 228362 # number of ReadReq MSHR misses 2467system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161625 # number of WriteReq MSHR misses 2468system.cpu1.dcache.WriteReq_mshr_misses::total 161625 # number of WriteReq MSHR misses 2469system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12531 # number of LoadLockedReq MSHR misses 2470system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12531 # number of LoadLockedReq MSHR misses 2471system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10581 # number of StoreCondReq MSHR misses 2472system.cpu1.dcache.StoreCondReq_mshr_misses::total 10581 # number of StoreCondReq MSHR misses 2473system.cpu1.dcache.demand_mshr_misses::cpu1.data 389987 # number of demand (read+write) MSHR misses 2474system.cpu1.dcache.demand_mshr_misses::total 389987 # number of demand (read+write) MSHR misses 2475system.cpu1.dcache.overall_mshr_misses::cpu1.data 389987 # number of overall MSHR misses 2476system.cpu1.dcache.overall_mshr_misses::total 389987 # number of overall MSHR misses 2477system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2843265804 # number of ReadReq MSHR miss cycles 2478system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2843265804 # number of ReadReq MSHR miss cycles 2479system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7240277216 # number of WriteReq MSHR miss cycles 2480system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles 2481system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles 2482system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles 2483system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles 2484system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles 2485system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles 2486system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles 2487system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles 2488system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles 2489system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles 2490system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles 2491system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles 2492system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles 2493system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles 2494system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles 2495system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses 2496system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses 2497system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses 2498system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses 2499system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses 2500system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses 2501system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses 2502system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses 2503system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses 2504system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses 2505system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses 2506system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses 2507system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency 2508system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency 2509system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency 2510system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency 2511system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency 2512system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency 2513system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency 2514system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency 2515system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency 2516system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency 2517system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency 2518system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency |
| 2503system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2504system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2505system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2506system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2507system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2508system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2509system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2510system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 2516system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2517system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2518system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2519system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2520system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2521system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2522system.iocache.fast_writes 0 # number of fast writes performed 2523system.iocache.cache_copies 0 # number of cache copies performed | 2519system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2520system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2521system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2522system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2523system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2524system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2525system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2526system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 2532system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2533system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2534system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2535system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2536system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2537system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2538system.iocache.fast_writes 0 # number of fast writes performed 2539system.iocache.cache_copies 0 # number of cache copies performed |
| 2524system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles 2525system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles 2526system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles 2527system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles | 2540system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles 2541system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles 2542system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles 2543system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles |
| 2528system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2529system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2530system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2531system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2532system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2533system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 2544system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2545system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2546system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2547system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2548system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2549system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 2534system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed | 2550system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed |
| 2535system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 2551system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 2536system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed | 2552system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed |
| 2537 2538---------- End Simulation Statistics ---------- | 2553 2554---------- End Simulation Statistics ---------- |