| stats.txt (9661:18755c467503) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.102954 # Number of seconds simulated 4sim_ticks 1102954033500 # Number of ticks simulated 5final_tick 1102954033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.613797 # Number of seconds simulated 4sim_ticks 2613796876500 # Number of ticks simulated 5final_tick 2613796876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 66183 # Simulator instruction rate (inst/s) 8host_op_rate 85190 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1185337549 # Simulator tick rate (ticks/s) 10host_mem_usage 402972 # Number of bytes of host memory used 11host_seconds 930.50 # Real time elapsed on the host 12sim_insts 61582952 # Number of instructions simulated 13sim_ops 79269552 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory | 7host_inst_rate 54493 # Simulator instruction rate (inst/s) 8host_op_rate 70162 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2268463215 # Simulator tick rate (ticks/s) 10host_mem_usage 404628 # Number of bytes of host memory used 11host_seconds 1152.23 # Real time elapsed on the host 12sim_insts 62788171 # Number of instructions simulated 13sim_ops 80843130 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 410112 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4380532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 404608 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5226032 # Number of bytes read from this memory 22system.physmem.bytes_read::total 59181988 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 410112 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 404608 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 814720 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4260416 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4352820 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 426432 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5278640 # Number of bytes read from this memory 22system.physmem.bytes_read::total 131565412 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 426432 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 821440 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4275200 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory | 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory |
| 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7287760 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory | 28system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory | 31system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6408 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68518 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6322 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 81683 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6257809 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66569 # Number of write requests responded to by this memory | 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68085 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6663 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 82505 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 15302272 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66800 # Number of write requests responded to by this memory |
| 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory | 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory |
| 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 823405 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 44207449 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 371831 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3971636 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 928 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 366840 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4738214 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 53657710 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 371831 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 366840 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 738671 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3862732 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2729347 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6607492 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3862732 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 44207449 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 371831 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3987049 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 928 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 366840 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 7467561 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 60265202 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6257809 # Total number of read requests seen 70system.physmem.writeReqs 823405 # Total number of write requests seen 71system.physmem.cpureqs 242034 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 400499776 # Total number of bytes read from memory 73system.physmem.bytesWritten 52697920 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 59181988 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7287760 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 12609 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 391396 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 391210 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 390867 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 391605 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 391533 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 390879 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 390924 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 391633 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 391393 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 390703 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 390862 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 391239 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 391232 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 390529 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 390469 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 391266 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 51407 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51229 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51679 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51546 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 50964 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51667 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 52037 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51503 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51884 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51249 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51170 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51891 # Track writes on a per bank basis | 41system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 824084 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 46335096 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 269 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 151124 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 1665325 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 163147 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2019530 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 50334979 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 151124 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 163147 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 314271 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 1635628 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 6504 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 1152399 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2794531 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1635628 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46335096 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 269 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 151124 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 1671828 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 163147 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 3171928 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 53129510 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 15302272 # Total number of read requests seen 70system.physmem.writeReqs 824084 # Total number of write requests seen 71system.physmem.cpureqs 244248 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 979345408 # Total number of bytes read from memory 73system.physmem.bytesWritten 52741376 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 131565412 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7304336 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 446 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 14097 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 956408 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 956129 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 956336 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 956715 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 957144 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 956669 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 956165 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 955908 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 956711 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 956880 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 955935 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 955453 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 956251 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 956326 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 956540 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 956256 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 49946 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 49763 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 51937 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 52171 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 52441 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 51960 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 51720 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51713 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51876 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 52086 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51258 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 50919 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51540 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51490 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51756 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51508 # Track writes on a per bank basis |
| 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 111system.physmem.numWrRetry 32620 # Number of times wr buffer was full causing retry 112system.physmem.totGap 1102952897500 # Total gap between requests | 111system.physmem.numWrRetry 32582 # Number of times wr buffer was full causing retry 112system.physmem.totGap 2613795718500 # Total gap between requests |
| 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 105 # Categorize read packet sizes | 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 105 # Categorize read packet sizes |
| 116system.physmem.readPktSize::3 6094848 # Categorize read packet sizes | 116system.physmem.readPktSize::3 15138816 # Categorize read packet sizes |
| 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes | 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 119system.physmem.readPktSize::6 162856 # Categorize read packet sizes | 119system.physmem.readPktSize::6 163351 # Categorize read packet sizes |
| 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes | 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes |
| 122system.physmem.writePktSize::2 756836 # Categorize write packet sizes | 122system.physmem.writePktSize::2 757284 # Categorize write packet sizes |
| 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes | 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 126system.physmem.writePktSize::6 66569 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 493795 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 430407 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 391611 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1441549 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 1086056 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1098465 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 1064627 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 26919 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 24797 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 44432 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 63777 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 44227 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 12032 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 15214 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 7879 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see | 126system.physmem.writePktSize::6 66800 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 1071823 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 1000587 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 1004460 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 3729147 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 2791599 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 2788638 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 2744704 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 17899 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 15634 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 28056 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 40361 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 27838 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 10343 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 10275 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 13794 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 6509 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 126 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see |
| 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::0 2891 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 2958 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 3001 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 3064 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 3113 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 3141 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 3167 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 35800 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 35800 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 35800 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 35800 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 35800 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 35800 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 35800 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 32910 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 32843 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 32800 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 32757 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 32737 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 32712 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 32659 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 32633 # What write queue length does an incoming req see 191system.physmem.totQLat 199184958750 # Total cycles spent in queuing delays 192system.physmem.totMemAccLat 239005190000 # Sum of mem lat for all requests 193system.physmem.totBusLat 31288700000 # Total cycles spent in databus access 194system.physmem.totBankLat 8531531250 # Total cycles spent in bank access 195system.physmem.avgQLat 31830.17 # Average queueing delay per request 196system.physmem.avgBankLat 1363.36 # Average bank access latency per request | 159system.physmem.wrQLenPdf::0 2919 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 2991 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 3038 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 3106 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 3132 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 3153 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 3186 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 3211 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 3225 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 35830 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 35830 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 35830 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 35830 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 35830 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 35830 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 35830 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 35830 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 35829 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 35829 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 35829 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 35829 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 35829 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 35829 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 32911 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 32792 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 32724 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 32698 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 32677 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 32644 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 32619 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 32605 # What write queue length does an incoming req see 191system.physmem.bytesPerActivate::samples 48021 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::mean 21491.760022 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::gmean 1412.636943 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::stdev 31347.507834 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::64-95 10706 22.29% 22.29% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::128-159 4255 8.86% 31.16% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::192-223 2654 5.53% 36.68% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-287 2034 4.24% 40.92% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::320-351 1364 2.84% 43.76% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-415 1232 2.57% 46.32% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::448-479 971 2.02% 48.35% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-543 916 1.91% 50.25% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::576-607 629 1.31% 51.56% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::640-671 621 1.29% 52.86% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::704-735 497 1.03% 53.89% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-799 447 0.93% 54.82% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::832-863 308 0.64% 55.46% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-927 288 0.60% 56.06% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::960-991 206 0.43% 56.49% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1024-1055 291 0.61% 57.10% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1088-1119 124 0.26% 57.36% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1152-1183 166 0.35% 57.70% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1216-1247 102 0.21% 57.91% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1280-1311 142 0.30% 58.21% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1344-1375 76 0.16% 58.37% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1408-1439 430 0.90% 59.26% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1472-1503 2116 4.41% 63.67% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1536-1567 511 1.06% 64.73% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1600-1631 96 0.20% 64.93% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1664-1695 187 0.39% 65.32% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1728-1759 61 0.13% 65.45% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1792-1823 129 0.27% 65.72% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1856-1887 42 0.09% 65.81% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1920-1951 82 0.17% 65.98% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1984-2015 32 0.07% 66.04% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2048-2079 81 0.17% 66.21% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2112-2143 30 0.06% 66.28% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::2176-2207 40 0.08% 66.36% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2240-2271 20 0.04% 66.40% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2304-2335 38 0.08% 66.48% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2368-2399 8 0.02% 66.50% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2432-2463 24 0.05% 66.55% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2496-2527 13 0.03% 66.57% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2560-2591 21 0.04% 66.62% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2624-2655 4 0.01% 66.63% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2688-2719 15 0.03% 66.66% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2752-2783 7 0.01% 66.67% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2816-2847 25 0.05% 66.72% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2880-2911 10 0.02% 66.74% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2944-2975 14 0.03% 66.77% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3008-3039 5 0.01% 66.78% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3072-3103 16 0.03% 66.82% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3136-3167 3 0.01% 66.82% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3200-3231 10 0.02% 66.84% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3264-3295 6 0.01% 66.86% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3328-3359 12 0.02% 66.88% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3392-3423 3 0.01% 66.89% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3456-3487 12 0.02% 66.91% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3520-3551 7 0.01% 66.93% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3584-3615 8 0.02% 66.94% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3648-3679 5 0.01% 66.95% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3712-3743 6 0.01% 66.97% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3776-3807 4 0.01% 66.97% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3840-3871 10 0.02% 67.00% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3904-3935 8 0.02% 67.01% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3968-3999 9 0.02% 67.03% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4032-4063 7 0.01% 67.05% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4096-4127 36 0.07% 67.12% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4160-4191 3 0.01% 67.13% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4224-4255 8 0.02% 67.14% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4288-4319 3 0.01% 67.15% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4352-4383 8 0.02% 67.17% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4416-4447 1 0.00% 67.17% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4480-4511 7 0.01% 67.18% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4544-4575 4 0.01% 67.19% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4672-4703 1 0.00% 67.19% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4736-4767 1 0.00% 67.20% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4800-4831 5 0.01% 67.21% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4864-4895 4 0.01% 67.21% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4928-4959 2 0.00% 67.22% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4992-5023 3 0.01% 67.22% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::5056-5087 3 0.01% 67.23% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5120-5151 10 0.02% 67.25% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::5184-5215 3 0.01% 67.26% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::5248-5279 3 0.01% 67.26% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5312-5343 2 0.00% 67.27% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5376-5407 1 0.00% 67.27% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5440-5471 1 0.00% 67.27% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5504-5535 2 0.00% 67.28% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5568-5599 3 0.01% 67.28% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5632-5663 4 0.01% 67.29% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5760-5791 2 0.00% 67.30% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5888-5919 5 0.01% 67.31% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5952-5983 2 0.00% 67.31% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::6016-6047 1 0.00% 67.31% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6080-6111 1 0.00% 67.31% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6144-6175 7 0.01% 67.33% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6208-6239 1 0.00% 67.33% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6272-6303 4 0.01% 67.34% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6336-6367 2 0.00% 67.34% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6400-6431 2 0.00% 67.35% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6464-6495 1 0.00% 67.35% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6528-6559 3 0.01% 67.36% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6656-6687 1 0.00% 67.36% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6720-6751 2 0.00% 67.36% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6784-6815 13 0.03% 67.39% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::6848-6879 2 0.00% 67.39% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::6912-6943 6 0.01% 67.41% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::6976-7007 1 0.00% 67.41% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7040-7071 3 0.01% 67.41% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7168-7199 5 0.01% 67.42% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7232-7263 3 0.01% 67.43% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::7424-7455 2 0.00% 67.44% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::7552-7583 6 0.01% 67.45% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::7616-7647 1 0.00% 67.45% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::7680-7711 4 0.01% 67.46% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::7744-7775 1 0.00% 67.46% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::7808-7839 4 0.01% 67.47% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7872-7903 3 0.01% 67.47% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::7936-7967 6 0.01% 67.49% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::8000-8031 1 0.00% 67.49% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::8064-8095 6 0.01% 67.50% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::8128-8159 4 0.01% 67.51% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::8192-8223 320 0.67% 68.18% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::8448-8479 2 0.00% 68.18% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::8704-8735 3 0.01% 68.19% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::8960-8991 2 0.00% 68.19% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::9408-9439 1 0.00% 68.19% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::9472-9503 3 0.01% 68.20% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::9728-9759 1 0.00% 68.20% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::9920-9951 1 0.00% 68.20% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10240-10271 16 0.03% 68.24% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10432-10463 1 0.00% 68.24% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10752-10783 1 0.00% 68.24% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::11264-11295 4 0.01% 68.25% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::11328-11359 1 0.00% 68.25% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11520-11551 1 0.00% 68.25% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11776-11807 1 0.00% 68.26% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::12288-12319 1 0.00% 68.26% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::12544-12575 1 0.00% 68.26% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::12864-12895 1 0.00% 68.26% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::12928-12959 1 0.00% 68.26% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::13056-13087 1 0.00% 68.27% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::13312-13343 2 0.00% 68.27% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::13824-13855 1 0.00% 68.27% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::14080-14111 1 0.00% 68.27% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::14336-14367 1 0.00% 68.28% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::14592-14623 2 0.00% 68.28% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::14848-14879 2 0.00% 68.28% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::15168-15199 1 0.00% 68.29% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15360-15391 2 0.00% 68.29% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::15424-15455 1 0.00% 68.29% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::16128-16159 2 0.00% 68.30% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::16384-16415 2 0.00% 68.30% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::16640-16671 1 0.00% 68.30% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::16896-16927 2 0.00% 68.31% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::17152-17183 1 0.00% 68.31% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::17216-17247 1 0.00% 68.31% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::17408-17439 1 0.00% 68.31% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::17792-17823 1 0.00% 68.32% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::17856-17887 1 0.00% 68.32% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::17920-17951 1 0.00% 68.32% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::18432-18463 1 0.00% 68.32% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::18688-18719 1 0.00% 68.32% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::19072-19103 1 0.00% 68.33% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::19200-19231 1 0.00% 68.33% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::19456-19487 3 0.01% 68.33% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::19968-19999 1 0.00% 68.34% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::20224-20255 1 0.00% 68.34% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::20480-20511 15 0.03% 68.37% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::20608-20639 1 0.00% 68.37% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::21504-21535 4 0.01% 68.38% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::22272-22303 2 0.00% 68.38% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::22528-22559 1 0.00% 68.39% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::22784-22815 3 0.01% 68.39% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::23040-23071 3 0.01% 68.40% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::23360-23391 1 0.00% 68.40% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::23552-23583 3 0.01% 68.41% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::23872-23903 1 0.00% 68.41% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::24064-24095 2 0.00% 68.41% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::24320-24351 1 0.00% 68.42% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::24576-24607 3 0.01% 68.42% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::24832-24863 2 0.00% 68.43% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::25088-25119 1 0.00% 68.43% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::25600-25631 2 0.00% 68.43% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::25856-25887 1 0.00% 68.43% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::25920-25951 1 0.00% 68.44% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::26112-26143 2 0.00% 68.44% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::26368-26399 2 0.00% 68.45% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::26624-26655 2 0.00% 68.45% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::27136-27167 1 0.00% 68.45% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::27392-27423 2 0.00% 68.46% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::27584-27615 1 0.00% 68.46% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::27648-27679 3 0.01% 68.46% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::27904-27935 1 0.00% 68.47% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::28160-28191 1 0.00% 68.47% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::28416-28447 1 0.00% 68.47% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::28672-28703 2 0.00% 68.47% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::28928-28959 4 0.01% 68.48% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::29184-29215 1 0.00% 68.48% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::29440-29471 2 0.00% 68.49% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::29952-29983 1 0.00% 68.49% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::30208-30239 2 0.00% 68.50% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::30720-30751 7 0.01% 68.51% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::31232-31263 1 0.00% 68.51% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::31488-31519 1 0.00% 68.51% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::31744-31775 3 0.01% 68.52% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::32256-32287 1 0.00% 68.52% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::32512-32543 3 0.01% 68.53% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::33024-33055 3 0.01% 68.53% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::33280-33311 2 0.00% 68.54% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::33728-33759 1 0.00% 68.54% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::33792-33823 55 0.11% 68.66% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::33984-34015 1 0.00% 68.66% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::34048-34079 1 0.00% 68.66% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::34816-34847 2 0.00% 68.66% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::35328-35359 1 0.00% 68.67% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::35840-35871 1 0.00% 68.67% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::35968-35999 1 0.00% 68.67% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::36096-36127 2 0.00% 68.67% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::36480-36511 1 0.00% 68.68% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::36608-36639 1 0.00% 68.68% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::38144-38175 1 0.00% 68.68% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::39168-39199 1 0.00% 68.68% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::39232-39263 1 0.00% 68.68% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::39616-39647 1 0.00% 68.69% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::40384-40415 1 0.00% 68.69% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::41216-41247 2 0.00% 68.69% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::41984-42015 2 0.00% 68.70% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::42240-42271 1 0.00% 68.70% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::42688-42719 1 0.00% 68.70% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::42752-42783 1 0.00% 68.70% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::43008-43039 1 0.00% 68.71% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::44032-44063 3 0.01% 68.71% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::44416-44447 1 0.00% 68.71% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::44672-44703 1 0.00% 68.72% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::46592-46623 1 0.00% 68.72% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::46912-46943 1 0.00% 68.72% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::46976-47007 1 0.00% 68.72% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::48640-48671 1 0.00% 68.72% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::48896-48927 1 0.00% 68.73% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::49408-49439 2 0.00% 68.73% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::50688-50719 1 0.00% 68.73% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::50880-50911 1 0.00% 68.73% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::51200-51231 2 0.00% 68.74% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::52224-52255 2 0.00% 68.74% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::52608-52639 1 0.00% 68.74% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::53248-53279 1 0.00% 68.75% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::54784-54815 1 0.00% 68.75% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::55296-55327 1 0.00% 68.75% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::55616-55647 1 0.00% 68.75% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::56064-56095 1 0.00% 68.76% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::56832-56863 1 0.00% 68.76% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::57088-57119 2 0.00% 68.76% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::58112-58143 1 0.00% 68.76% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::59584-59615 1 0.00% 68.77% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::59648-59679 1 0.00% 68.77% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::59840-59871 1 0.00% 68.77% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::60416-60447 1 0.00% 68.77% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::61184-61215 1 0.00% 68.77% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::61568-61599 1 0.00% 68.78% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::61952-61983 1 0.00% 68.78% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::62976-63007 1 0.00% 68.78% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::63488-63519 1 0.00% 68.78% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::64064-64095 1 0.00% 68.78% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::64512-64543 1 0.00% 68.79% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::65024-65055 25 0.05% 68.84% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::65088-65119 6 0.01% 68.85% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::65152-65183 7 0.01% 68.87% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::65280-65311 19 0.04% 68.91% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::65408-65439 7 0.01% 68.92% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::65472-65503 18 0.04% 68.96% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::65536-65567 14562 30.32% 99.28% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::97536-97567 1 0.00% 99.28% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::103680-103711 1 0.00% 99.29% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.29% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::130176-130207 1 0.00% 99.29% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::130624-130655 1 0.00% 99.29% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::130688-130719 1 0.00% 99.29% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::131072-131103 321 0.67% 99.96% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::131328-131359 1 0.00% 99.97% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::132096-132127 2 0.00% 99.97% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::140032-140063 1 0.00% 99.98% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::162560-162591 1 0.00% 99.98% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::182528-182559 1 0.00% 99.98% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::total 48021 # Bytes accessed per row activation 482system.physmem.totQLat 359781455750 # Total cycles spent in queuing delays 483system.physmem.totMemAccLat 452374882000 # Sum of mem lat for all requests 484system.physmem.totBusLat 76509130000 # Total cycles spent in databus access 485system.physmem.totBankLat 16084296250 # Total cycles spent in bank access 486system.physmem.avgQLat 23512.32 # Average queueing delay per request 487system.physmem.avgBankLat 1051.14 # Average bank access latency per request |
| 197system.physmem.avgBusLat 5000.00 # Average bus latency per request | 488system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 198system.physmem.avgMemAccLat 38193.53 # Average memory access latency 199system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s 200system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s 201system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s 202system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s | 489system.physmem.avgMemAccLat 29563.46 # Average memory access latency 490system.physmem.avgRdBW 374.68 # Average achieved read bandwidth in MB/s 491system.physmem.avgWrBW 20.18 # Average achieved write bandwidth in MB/s 492system.physmem.avgConsumedRdBW 50.33 # Average consumed read bandwidth in MB/s 493system.physmem.avgConsumedWrBW 2.79 # Average consumed write bandwidth in MB/s |
| 203system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 494system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 204system.physmem.busUtil 3.21 # Data bus utilization in percentage 205system.physmem.avgRdQLen 0.22 # Average read queue length over time 206system.physmem.avgWrQLen 10.07 # Average write queue length over time 207system.physmem.readRowHits 6213915 # Number of row buffer hits during reads 208system.physmem.writeRowHits 799980 # Number of row buffer hits during writes 209system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads 210system.physmem.writeRowHitRate 97.16 # Row buffer hit rate for writes 211system.physmem.avgGap 155757.60 # Average gap between requests | 495system.physmem.busUtil 3.08 # Data bus utilization in percentage 496system.physmem.avgRdQLen 0.17 # Average read queue length over time 497system.physmem.avgWrQLen 13.40 # Average write queue length over time 498system.physmem.readRowHits 15272830 # Number of row buffer hits during reads 499system.physmem.writeRowHits 805042 # Number of row buffer hits during writes 500system.physmem.readRowHitRate 99.81 # Row buffer hit rate for reads 501system.physmem.writeRowHitRate 97.69 # Row buffer hit rate for writes 502system.physmem.avgGap 162082.23 # Average gap between requests |
| 212system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 213system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 214system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 215system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 216system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 217system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 218system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 219system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 220system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory | 503system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 504system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 505system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 506system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 507system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 508system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 509system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 510system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 511system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory |
| 221system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 222system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 223system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 224system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 225system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 228system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 229system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) 230system.l2c.replacements 72561 # number of replacements 231system.l2c.tagsinuse 53740.730134 # Cycle average of tags in use 232system.l2c.total_refs 1839807 # Total number of references to valid blocks. 233system.l2c.sampled_refs 137757 # Sample count of references to valid blocks. 234system.l2c.avg_refs 13.355452 # Average number of references to valid blocks. | 512system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) 513system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 514system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) 515system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) 516system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 517system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) 518system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) 519system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 520system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) 521system.membus.throughput 54057191 # Throughput (bytes/s) 522system.membus.trans_dist::ReadReq 16352590 # Transaction distribution 523system.membus.trans_dist::ReadResp 16352590 # Transaction distribution 524system.membus.trans_dist::WriteReq 769166 # Transaction distribution 525system.membus.trans_dist::WriteResp 769166 # Transaction distribution 526system.membus.trans_dist::Writeback 66800 # Transaction distribution 527system.membus.trans_dist::UpgradeReq 35679 # Transaction distribution 528system.membus.trans_dist::SCUpgradeReq 18283 # Transaction distribution 529system.membus.trans_dist::UpgradeResp 14097 # Transaction distribution 530system.membus.trans_dist::ReadExReq 138270 # Transaction distribution 531system.membus.trans_dist::ReadExResp 137887 # Transaction distribution 532system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) 533system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 534system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976722 # Packet count per connected master and slave (bytes) 535system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) 536system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 537system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) 538system.membus.pkt_count_system.l2c.mem_side::total 4376896 # Packet count per connected master and slave (bytes) 539system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 540system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 541system.membus.pkt_count::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) 542system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 543system.membus.pkt_count::system.physmem.port 32254354 # Packet count per connected master and slave (bytes) 544system.membus.pkt_count::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) 545system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 546system.membus.pkt_count::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) 547system.membus.pkt_count::total 34654528 # Packet count per connected master and slave (bytes) 548system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) 549system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 550system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17759220 # Cumulative packet size per connected master and slave (bytes) 551system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) 552system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 553system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) 554system.membus.tot_pkt_size_system.l2c.mem_side::total 20183988 # Cumulative packet size per connected master and slave (bytes) 555system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 556system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 557system.membus.tot_pkt_size::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) 558system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 559system.membus.tot_pkt_size::system.physmem.port 138869748 # Cumulative packet size per connected master and slave (bytes) 560system.membus.tot_pkt_size::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) 561system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 562system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) 563system.membus.tot_pkt_size::total 141294516 # Cumulative packet size per connected master and slave (bytes) 564system.membus.data_through_bus 141294516 # Total data (bytes) 565system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 566system.membus.reqLayer0.occupancy 1493240500 # Layer occupancy (ticks) 567system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 568system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 569system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 570system.membus.reqLayer2.occupancy 17657749750 # Layer occupancy (ticks) 571system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) 572system.membus.reqLayer3.occupancy 11792000 # Layer occupancy (ticks) 573system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 574system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) 575system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 576system.membus.reqLayer6.occupancy 1805500 # Layer occupancy (ticks) 577system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) 578system.membus.respLayer1.occupancy 4833822840 # Layer occupancy (ticks) 579system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 580system.membus.respLayer2.occupancy 34180950731 # Layer occupancy (ticks) 581system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 582system.l2c.replacements 73069 # number of replacements 583system.l2c.tagsinuse 53059.477869 # Cycle average of tags in use 584system.l2c.total_refs 1873536 # Total number of references to valid blocks. 585system.l2c.sampled_refs 138222 # Sample count of references to valid blocks. 586system.l2c.avg_refs 13.554543 # Average number of references to valid blocks. |
| 235system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 587system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 236system.l2c.occ_blocks::writebacks 39373.368087 # Average occupied blocks per requestor 237system.l2c.occ_blocks::cpu0.dtb.walker 3.826392 # Average occupied blocks per requestor 238system.l2c.occ_blocks::cpu0.itb.walker 0.258184 # Average occupied blocks per requestor 239system.l2c.occ_blocks::cpu0.inst 4017.777159 # Average occupied blocks per requestor 240system.l2c.occ_blocks::cpu0.data 2831.337785 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu1.dtb.walker 9.908379 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu1.inst 3708.426786 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu1.data 3795.827361 # Average occupied blocks per requestor 244system.l2c.occ_percent::writebacks 0.600790 # Average percentage of cache occupancy 245system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy 246system.l2c.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 247system.l2c.occ_percent::cpu0.inst 0.061306 # Average percentage of cache occupancy 248system.l2c.occ_percent::cpu0.data 0.043203 # Average percentage of cache occupancy 249system.l2c.occ_percent::cpu1.dtb.walker 0.000151 # Average percentage of cache occupancy 250system.l2c.occ_percent::cpu1.inst 0.056586 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu1.data 0.057920 # Average percentage of cache occupancy 252system.l2c.occ_percent::total 0.820018 # Average percentage of cache occupancy 253system.l2c.ReadReq_hits::cpu0.dtb.walker 21639 # number of ReadReq hits 254system.l2c.ReadReq_hits::cpu0.itb.walker 4056 # number of ReadReq hits 255system.l2c.ReadReq_hits::cpu0.inst 386080 # number of ReadReq hits 256system.l2c.ReadReq_hits::cpu0.data 166672 # number of ReadReq hits 257system.l2c.ReadReq_hits::cpu1.dtb.walker 30823 # number of ReadReq hits 258system.l2c.ReadReq_hits::cpu1.itb.walker 4930 # number of ReadReq hits 259system.l2c.ReadReq_hits::cpu1.inst 589304 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu1.data 198131 # number of ReadReq hits 261system.l2c.ReadReq_hits::total 1401635 # number of ReadReq hits 262system.l2c.Writeback_hits::writebacks 581048 # number of Writeback hits 263system.l2c.Writeback_hits::total 581048 # number of Writeback hits 264system.l2c.UpgradeReq_hits::cpu0.data 1122 # number of UpgradeReq hits 265system.l2c.UpgradeReq_hits::cpu1.data 742 # number of UpgradeReq hits 266system.l2c.UpgradeReq_hits::total 1864 # number of UpgradeReq hits 267system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits 268system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits 269system.l2c.SCUpgradeReq_hits::total 337 # number of SCUpgradeReq hits 270system.l2c.ReadExReq_hits::cpu0.data 48001 # number of ReadExReq hits 271system.l2c.ReadExReq_hits::cpu1.data 58894 # number of ReadExReq hits 272system.l2c.ReadExReq_hits::total 106895 # number of ReadExReq hits 273system.l2c.demand_hits::cpu0.dtb.walker 21639 # number of demand (read+write) hits 274system.l2c.demand_hits::cpu0.itb.walker 4056 # number of demand (read+write) hits 275system.l2c.demand_hits::cpu0.inst 386080 # number of demand (read+write) hits 276system.l2c.demand_hits::cpu0.data 214673 # number of demand (read+write) hits 277system.l2c.demand_hits::cpu1.dtb.walker 30823 # number of demand (read+write) hits 278system.l2c.demand_hits::cpu1.itb.walker 4930 # number of demand (read+write) hits 279system.l2c.demand_hits::cpu1.inst 589304 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu1.data 257025 # number of demand (read+write) hits 281system.l2c.demand_hits::total 1508530 # number of demand (read+write) hits 282system.l2c.overall_hits::cpu0.dtb.walker 21639 # number of overall hits 283system.l2c.overall_hits::cpu0.itb.walker 4056 # number of overall hits 284system.l2c.overall_hits::cpu0.inst 386080 # number of overall hits 285system.l2c.overall_hits::cpu0.data 214673 # number of overall hits 286system.l2c.overall_hits::cpu1.dtb.walker 30823 # number of overall hits 287system.l2c.overall_hits::cpu1.itb.walker 4930 # number of overall hits 288system.l2c.overall_hits::cpu1.inst 589304 # number of overall hits 289system.l2c.overall_hits::cpu1.data 257025 # number of overall hits 290system.l2c.overall_hits::total 1508530 # number of overall hits | 588system.l2c.occ_blocks::writebacks 37743.094868 # Average occupied blocks per requestor 589system.l2c.occ_blocks::cpu0.dtb.walker 4.500926 # Average occupied blocks per requestor 590system.l2c.occ_blocks::cpu0.itb.walker 0.000358 # Average occupied blocks per requestor 591system.l2c.occ_blocks::cpu0.inst 4196.922721 # Average occupied blocks per requestor 592system.l2c.occ_blocks::cpu0.data 2968.415869 # Average occupied blocks per requestor 593system.l2c.occ_blocks::cpu1.dtb.walker 13.090066 # Average occupied blocks per requestor 594system.l2c.occ_blocks::cpu1.inst 4030.052193 # Average occupied blocks per requestor 595system.l2c.occ_blocks::cpu1.data 4103.400867 # Average occupied blocks per requestor 596system.l2c.occ_percent::writebacks 0.575914 # Average percentage of cache occupancy 597system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy 598system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 599system.l2c.occ_percent::cpu0.inst 0.064040 # Average percentage of cache occupancy 600system.l2c.occ_percent::cpu0.data 0.045294 # Average percentage of cache occupancy 601system.l2c.occ_percent::cpu1.dtb.walker 0.000200 # Average percentage of cache occupancy 602system.l2c.occ_percent::cpu1.inst 0.061494 # Average percentage of cache occupancy 603system.l2c.occ_percent::cpu1.data 0.062613 # Average percentage of cache occupancy 604system.l2c.occ_percent::total 0.809623 # Average percentage of cache occupancy 605system.l2c.ReadReq_hits::cpu0.dtb.walker 23020 # number of ReadReq hits 606system.l2c.ReadReq_hits::cpu0.itb.walker 4625 # number of ReadReq hits 607system.l2c.ReadReq_hits::cpu0.inst 393598 # number of ReadReq hits 608system.l2c.ReadReq_hits::cpu0.data 165506 # number of ReadReq hits 609system.l2c.ReadReq_hits::cpu1.dtb.walker 32735 # number of ReadReq hits 610system.l2c.ReadReq_hits::cpu1.itb.walker 5728 # number of ReadReq hits 611system.l2c.ReadReq_hits::cpu1.inst 607995 # number of ReadReq hits 612system.l2c.ReadReq_hits::cpu1.data 201851 # number of ReadReq hits 613system.l2c.ReadReq_hits::total 1435058 # number of ReadReq hits 614system.l2c.Writeback_hits::writebacks 583280 # number of Writeback hits 615system.l2c.Writeback_hits::total 583280 # number of Writeback hits 616system.l2c.UpgradeReq_hits::cpu0.data 1128 # number of UpgradeReq hits 617system.l2c.UpgradeReq_hits::cpu1.data 710 # number of UpgradeReq hits 618system.l2c.UpgradeReq_hits::total 1838 # number of UpgradeReq hits 619system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits 620system.l2c.SCUpgradeReq_hits::cpu1.data 170 # number of SCUpgradeReq hits 621system.l2c.SCUpgradeReq_hits::total 374 # number of SCUpgradeReq hits 622system.l2c.ReadExReq_hits::cpu0.data 48355 # number of ReadExReq hits 623system.l2c.ReadExReq_hits::cpu1.data 58837 # number of ReadExReq hits 624system.l2c.ReadExReq_hits::total 107192 # number of ReadExReq hits 625system.l2c.demand_hits::cpu0.dtb.walker 23020 # number of demand (read+write) hits 626system.l2c.demand_hits::cpu0.itb.walker 4625 # number of demand (read+write) hits 627system.l2c.demand_hits::cpu0.inst 393598 # number of demand (read+write) hits 628system.l2c.demand_hits::cpu0.data 213861 # number of demand (read+write) hits 629system.l2c.demand_hits::cpu1.dtb.walker 32735 # number of demand (read+write) hits 630system.l2c.demand_hits::cpu1.itb.walker 5728 # number of demand (read+write) hits 631system.l2c.demand_hits::cpu1.inst 607995 # number of demand (read+write) hits 632system.l2c.demand_hits::cpu1.data 260688 # number of demand (read+write) hits 633system.l2c.demand_hits::total 1542250 # number of demand (read+write) hits 634system.l2c.overall_hits::cpu0.dtb.walker 23020 # number of overall hits 635system.l2c.overall_hits::cpu0.itb.walker 4625 # number of overall hits 636system.l2c.overall_hits::cpu0.inst 393598 # number of overall hits 637system.l2c.overall_hits::cpu0.data 213861 # number of overall hits 638system.l2c.overall_hits::cpu1.dtb.walker 32735 # number of overall hits 639system.l2c.overall_hits::cpu1.itb.walker 5728 # number of overall hits 640system.l2c.overall_hits::cpu1.inst 607995 # number of overall hits 641system.l2c.overall_hits::cpu1.data 260688 # number of overall hits 642system.l2c.overall_hits::total 1542250 # number of overall hits |
| 291system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses | 643system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses |
| 292system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 293system.l2c.ReadReq_misses::cpu0.inst 6288 # number of ReadReq misses 294system.l2c.ReadReq_misses::cpu0.data 6413 # number of ReadReq misses 295system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses 296system.l2c.ReadReq_misses::cpu1.inst 6286 # number of ReadReq misses 297system.l2c.ReadReq_misses::cpu1.data 6293 # number of ReadReq misses 298system.l2c.ReadReq_misses::total 25310 # number of ReadReq misses 299system.l2c.UpgradeReq_misses::cpu0.data 5149 # number of UpgradeReq misses 300system.l2c.UpgradeReq_misses::cpu1.data 3783 # number of UpgradeReq misses 301system.l2c.UpgradeReq_misses::total 8932 # number of UpgradeReq misses 302system.l2c.SCUpgradeReq_misses::cpu0.data 648 # number of SCUpgradeReq misses 303system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses 304system.l2c.SCUpgradeReq_misses::total 1064 # number of SCUpgradeReq misses 305system.l2c.ReadExReq_misses::cpu0.data 63471 # number of ReadExReq misses 306system.l2c.ReadExReq_misses::cpu1.data 76594 # number of ReadExReq misses 307system.l2c.ReadExReq_misses::total 140065 # number of ReadExReq misses | 644system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 645system.l2c.ReadReq_misses::cpu0.inst 6054 # number of ReadReq misses 646system.l2c.ReadReq_misses::cpu0.data 6310 # number of ReadReq misses 647system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses 648system.l2c.ReadReq_misses::cpu1.inst 6631 # number of ReadReq misses 649system.l2c.ReadReq_misses::cpu1.data 6355 # number of ReadReq misses 650system.l2c.ReadReq_misses::total 25381 # number of ReadReq misses 651system.l2c.UpgradeReq_misses::cpu0.data 5662 # number of UpgradeReq misses 652system.l2c.UpgradeReq_misses::cpu1.data 4388 # number of UpgradeReq misses 653system.l2c.UpgradeReq_misses::total 10050 # number of UpgradeReq misses 654system.l2c.SCUpgradeReq_misses::cpu0.data 778 # number of SCUpgradeReq misses 655system.l2c.SCUpgradeReq_misses::cpu1.data 584 # number of SCUpgradeReq misses 656system.l2c.SCUpgradeReq_misses::total 1362 # number of SCUpgradeReq misses 657system.l2c.ReadExReq_misses::cpu0.data 63189 # number of ReadExReq misses 658system.l2c.ReadExReq_misses::cpu1.data 77383 # number of ReadExReq misses 659system.l2c.ReadExReq_misses::total 140572 # number of ReadExReq misses |
| 308system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses | 660system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses |
| 309system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 310system.l2c.demand_misses::cpu0.inst 6288 # number of demand (read+write) misses 311system.l2c.demand_misses::cpu0.data 69884 # number of demand (read+write) misses 312system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses 313system.l2c.demand_misses::cpu1.inst 6286 # number of demand (read+write) misses 314system.l2c.demand_misses::cpu1.data 82887 # number of demand (read+write) misses 315system.l2c.demand_misses::total 165375 # number of demand (read+write) misses | 661system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 662system.l2c.demand_misses::cpu0.inst 6054 # number of demand (read+write) misses 663system.l2c.demand_misses::cpu0.data 69499 # number of demand (read+write) misses 664system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses 665system.l2c.demand_misses::cpu1.inst 6631 # number of demand (read+write) misses 666system.l2c.demand_misses::cpu1.data 83738 # number of demand (read+write) misses 667system.l2c.demand_misses::total 165953 # number of demand (read+write) misses |
| 316system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses | 668system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses |
| 317system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 318system.l2c.overall_misses::cpu0.inst 6288 # number of overall misses 319system.l2c.overall_misses::cpu0.data 69884 # number of overall misses 320system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses 321system.l2c.overall_misses::cpu1.inst 6286 # number of overall misses 322system.l2c.overall_misses::cpu1.data 82887 # number of overall misses 323system.l2c.overall_misses::total 165375 # number of overall misses 324system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 728500 # number of ReadReq miss cycles 325system.l2c.ReadReq_miss_latency::cpu0.itb.walker 187000 # number of ReadReq miss cycles 326system.l2c.ReadReq_miss_latency::cpu0.inst 351113000 # number of ReadReq miss cycles 327system.l2c.ReadReq_miss_latency::cpu0.data 364719994 # number of ReadReq miss cycles 328system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1085000 # number of ReadReq miss cycles 329system.l2c.ReadReq_miss_latency::cpu1.inst 375250500 # number of ReadReq miss cycles 330system.l2c.ReadReq_miss_latency::cpu1.data 394358500 # number of ReadReq miss cycles 331system.l2c.ReadReq_miss_latency::total 1487442494 # number of ReadReq miss cycles 332system.l2c.UpgradeReq_miss_latency::cpu0.data 8752489 # number of UpgradeReq miss cycles 333system.l2c.UpgradeReq_miss_latency::cpu1.data 11759000 # number of UpgradeReq miss cycles 334system.l2c.UpgradeReq_miss_latency::total 20511489 # number of UpgradeReq miss cycles 335system.l2c.SCUpgradeReq_miss_latency::cpu0.data 635500 # number of SCUpgradeReq miss cycles 336system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2909999 # number of SCUpgradeReq miss cycles 337system.l2c.SCUpgradeReq_miss_latency::total 3545499 # number of SCUpgradeReq miss cycles 338system.l2c.ReadExReq_miss_latency::cpu0.data 3160530987 # number of ReadExReq miss cycles 339system.l2c.ReadExReq_miss_latency::cpu1.data 4109769495 # number of ReadExReq miss cycles 340system.l2c.ReadExReq_miss_latency::total 7270300482 # number of ReadExReq miss cycles 341system.l2c.demand_miss_latency::cpu0.dtb.walker 728500 # number of demand (read+write) miss cycles 342system.l2c.demand_miss_latency::cpu0.itb.walker 187000 # number of demand (read+write) miss cycles 343system.l2c.demand_miss_latency::cpu0.inst 351113000 # number of demand (read+write) miss cycles 344system.l2c.demand_miss_latency::cpu0.data 3525250981 # number of demand (read+write) miss cycles 345system.l2c.demand_miss_latency::cpu1.dtb.walker 1085000 # number of demand (read+write) miss cycles 346system.l2c.demand_miss_latency::cpu1.inst 375250500 # number of demand (read+write) miss cycles 347system.l2c.demand_miss_latency::cpu1.data 4504127995 # number of demand (read+write) miss cycles 348system.l2c.demand_miss_latency::total 8757742976 # number of demand (read+write) miss cycles 349system.l2c.overall_miss_latency::cpu0.dtb.walker 728500 # number of overall miss cycles 350system.l2c.overall_miss_latency::cpu0.itb.walker 187000 # number of overall miss cycles 351system.l2c.overall_miss_latency::cpu0.inst 351113000 # number of overall miss cycles 352system.l2c.overall_miss_latency::cpu0.data 3525250981 # number of overall miss cycles 353system.l2c.overall_miss_latency::cpu1.dtb.walker 1085000 # number of overall miss cycles 354system.l2c.overall_miss_latency::cpu1.inst 375250500 # number of overall miss cycles 355system.l2c.overall_miss_latency::cpu1.data 4504127995 # number of overall miss cycles 356system.l2c.overall_miss_latency::total 8757742976 # number of overall miss cycles 357system.l2c.ReadReq_accesses::cpu0.dtb.walker 21650 # number of ReadReq accesses(hits+misses) 358system.l2c.ReadReq_accesses::cpu0.itb.walker 4059 # number of ReadReq accesses(hits+misses) 359system.l2c.ReadReq_accesses::cpu0.inst 392368 # number of ReadReq accesses(hits+misses) 360system.l2c.ReadReq_accesses::cpu0.data 173085 # number of ReadReq accesses(hits+misses) 361system.l2c.ReadReq_accesses::cpu1.dtb.walker 30839 # number of ReadReq accesses(hits+misses) 362system.l2c.ReadReq_accesses::cpu1.itb.walker 4930 # number of ReadReq accesses(hits+misses) 363system.l2c.ReadReq_accesses::cpu1.inst 595590 # number of ReadReq accesses(hits+misses) 364system.l2c.ReadReq_accesses::cpu1.data 204424 # number of ReadReq accesses(hits+misses) 365system.l2c.ReadReq_accesses::total 1426945 # number of ReadReq accesses(hits+misses) 366system.l2c.Writeback_accesses::writebacks 581048 # number of Writeback accesses(hits+misses) 367system.l2c.Writeback_accesses::total 581048 # number of Writeback accesses(hits+misses) 368system.l2c.UpgradeReq_accesses::cpu0.data 6271 # number of UpgradeReq accesses(hits+misses) 369system.l2c.UpgradeReq_accesses::cpu1.data 4525 # number of UpgradeReq accesses(hits+misses) 370system.l2c.UpgradeReq_accesses::total 10796 # number of UpgradeReq accesses(hits+misses) 371system.l2c.SCUpgradeReq_accesses::cpu0.data 839 # number of SCUpgradeReq accesses(hits+misses) 372system.l2c.SCUpgradeReq_accesses::cpu1.data 562 # number of SCUpgradeReq accesses(hits+misses) 373system.l2c.SCUpgradeReq_accesses::total 1401 # number of SCUpgradeReq accesses(hits+misses) 374system.l2c.ReadExReq_accesses::cpu0.data 111472 # number of ReadExReq accesses(hits+misses) 375system.l2c.ReadExReq_accesses::cpu1.data 135488 # number of ReadExReq accesses(hits+misses) 376system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses) 377system.l2c.demand_accesses::cpu0.dtb.walker 21650 # number of demand (read+write) accesses 378system.l2c.demand_accesses::cpu0.itb.walker 4059 # number of demand (read+write) accesses 379system.l2c.demand_accesses::cpu0.inst 392368 # number of demand (read+write) accesses 380system.l2c.demand_accesses::cpu0.data 284557 # number of demand (read+write) accesses 381system.l2c.demand_accesses::cpu1.dtb.walker 30839 # number of demand (read+write) accesses 382system.l2c.demand_accesses::cpu1.itb.walker 4930 # number of demand (read+write) accesses 383system.l2c.demand_accesses::cpu1.inst 595590 # number of demand (read+write) accesses 384system.l2c.demand_accesses::cpu1.data 339912 # number of demand (read+write) accesses 385system.l2c.demand_accesses::total 1673905 # number of demand (read+write) accesses 386system.l2c.overall_accesses::cpu0.dtb.walker 21650 # number of overall (read+write) accesses 387system.l2c.overall_accesses::cpu0.itb.walker 4059 # number of overall (read+write) accesses 388system.l2c.overall_accesses::cpu0.inst 392368 # number of overall (read+write) accesses 389system.l2c.overall_accesses::cpu0.data 284557 # number of overall (read+write) accesses 390system.l2c.overall_accesses::cpu1.dtb.walker 30839 # number of overall (read+write) accesses 391system.l2c.overall_accesses::cpu1.itb.walker 4930 # number of overall (read+write) accesses 392system.l2c.overall_accesses::cpu1.inst 595590 # number of overall (read+write) accesses 393system.l2c.overall_accesses::cpu1.data 339912 # number of overall (read+write) accesses 394system.l2c.overall_accesses::total 1673905 # number of overall (read+write) accesses 395system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000508 # miss rate for ReadReq accesses 396system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000739 # miss rate for ReadReq accesses 397system.l2c.ReadReq_miss_rate::cpu0.inst 0.016026 # miss rate for ReadReq accesses 398system.l2c.ReadReq_miss_rate::cpu0.data 0.037051 # miss rate for ReadReq accesses 399system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000519 # miss rate for ReadReq accesses 400system.l2c.ReadReq_miss_rate::cpu1.inst 0.010554 # miss rate for ReadReq accesses 401system.l2c.ReadReq_miss_rate::cpu1.data 0.030784 # miss rate for ReadReq accesses 402system.l2c.ReadReq_miss_rate::total 0.017737 # miss rate for ReadReq accesses 403system.l2c.UpgradeReq_miss_rate::cpu0.data 0.821081 # miss rate for UpgradeReq accesses 404system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836022 # miss rate for UpgradeReq accesses 405system.l2c.UpgradeReq_miss_rate::total 0.827343 # miss rate for UpgradeReq accesses 406system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772348 # miss rate for SCUpgradeReq accesses 407system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.740214 # miss rate for SCUpgradeReq accesses 408system.l2c.SCUpgradeReq_miss_rate::total 0.759458 # miss rate for SCUpgradeReq accesses 409system.l2c.ReadExReq_miss_rate::cpu0.data 0.569390 # miss rate for ReadExReq accesses 410system.l2c.ReadExReq_miss_rate::cpu1.data 0.565319 # miss rate for ReadExReq accesses 411system.l2c.ReadExReq_miss_rate::total 0.567157 # miss rate for ReadExReq accesses 412system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000508 # miss rate for demand accesses 413system.l2c.demand_miss_rate::cpu0.itb.walker 0.000739 # miss rate for demand accesses 414system.l2c.demand_miss_rate::cpu0.inst 0.016026 # miss rate for demand accesses 415system.l2c.demand_miss_rate::cpu0.data 0.245589 # miss rate for demand accesses 416system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000519 # miss rate for demand accesses 417system.l2c.demand_miss_rate::cpu1.inst 0.010554 # miss rate for demand accesses 418system.l2c.demand_miss_rate::cpu1.data 0.243848 # miss rate for demand accesses 419system.l2c.demand_miss_rate::total 0.098796 # miss rate for demand accesses 420system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000508 # miss rate for overall accesses 421system.l2c.overall_miss_rate::cpu0.itb.walker 0.000739 # miss rate for overall accesses 422system.l2c.overall_miss_rate::cpu0.inst 0.016026 # miss rate for overall accesses 423system.l2c.overall_miss_rate::cpu0.data 0.245589 # miss rate for overall accesses 424system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000519 # miss rate for overall accesses 425system.l2c.overall_miss_rate::cpu1.inst 0.010554 # miss rate for overall accesses 426system.l2c.overall_miss_rate::cpu1.data 0.243848 # miss rate for overall accesses 427system.l2c.overall_miss_rate::total 0.098796 # miss rate for overall accesses 428system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average ReadReq miss latency 429system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 62333.333333 # average ReadReq miss latency 430system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55838.581425 # average ReadReq miss latency 431system.l2c.ReadReq_avg_miss_latency::cpu0.data 56871.977857 # average ReadReq miss latency 432system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 67812.500000 # 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average overall miss latency 455system.l2c.overall_avg_miss_latency::cpu0.inst 55838.581425 # average overall miss latency 456system.l2c.overall_avg_miss_latency::cpu0.data 50444.321747 # average overall miss latency 457system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 67812.500000 # average overall miss latency 458system.l2c.overall_avg_miss_latency::cpu1.inst 59696.229717 # average overall miss latency 459system.l2c.overall_avg_miss_latency::cpu1.data 54340.584108 # average overall miss latency 460system.l2c.overall_avg_miss_latency::total 52956.873627 # average overall miss latency | 669system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 670system.l2c.overall_misses::cpu0.inst 6054 # number of overall misses 671system.l2c.overall_misses::cpu0.data 69499 # number of overall misses 672system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses 673system.l2c.overall_misses::cpu1.inst 6631 # number of overall misses 674system.l2c.overall_misses::cpu1.data 83738 # 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miss rate for ReadReq accesses 754system.l2c.ReadReq_miss_rate::total 0.017379 # miss rate for ReadReq accesses 755system.l2c.UpgradeReq_miss_rate::cpu0.data 0.833873 # miss rate for UpgradeReq accesses 756system.l2c.UpgradeReq_miss_rate::cpu1.data 0.860730 # miss rate for UpgradeReq accesses 757system.l2c.UpgradeReq_miss_rate::total 0.845390 # miss rate for UpgradeReq accesses 758system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.792261 # miss rate for SCUpgradeReq accesses 759system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.774536 # miss rate for SCUpgradeReq accesses 760system.l2c.SCUpgradeReq_miss_rate::total 0.784562 # miss rate for SCUpgradeReq accesses 761system.l2c.ReadExReq_miss_rate::cpu0.data 0.566494 # miss rate for ReadExReq accesses 762system.l2c.ReadExReq_miss_rate::cpu1.data 0.568074 # miss rate for ReadExReq accesses 763system.l2c.ReadExReq_miss_rate::total 0.567362 # miss rate for ReadExReq accesses 764system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000478 # miss rate for demand accesses 765system.l2c.demand_miss_rate::cpu0.itb.walker 0.000432 # miss rate for demand accesses 766system.l2c.demand_miss_rate::cpu0.inst 0.015148 # miss rate for demand accesses 767system.l2c.demand_miss_rate::cpu0.data 0.245268 # miss rate for demand accesses 768system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for demand accesses 769system.l2c.demand_miss_rate::cpu1.inst 0.010789 # miss rate for demand accesses 770system.l2c.demand_miss_rate::cpu1.data 0.243123 # miss rate for demand accesses 771system.l2c.demand_miss_rate::total 0.097151 # miss rate for demand accesses 772system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000478 # miss rate for overall accesses 773system.l2c.overall_miss_rate::cpu0.itb.walker 0.000432 # miss rate for overall accesses 774system.l2c.overall_miss_rate::cpu0.inst 0.015148 # miss rate for overall accesses 775system.l2c.overall_miss_rate::cpu0.data 0.245268 # miss rate for overall accesses 776system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for overall accesses 777system.l2c.overall_miss_rate::cpu1.inst 0.010789 # miss rate for overall accesses 778system.l2c.overall_miss_rate::cpu1.data 0.243123 # miss rate for overall accesses 779system.l2c.overall_miss_rate::total 0.097151 # miss rate for overall accesses 780system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81227.272727 # average ReadReq miss latency 781system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65000 # average ReadReq miss latency 782system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73144.862901 # average ReadReq miss latency 783system.l2c.ReadReq_avg_miss_latency::cpu0.data 73497.463550 # average ReadReq miss latency 784system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85166.666667 # average ReadReq miss latency 785system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76967.501131 # average ReadReq miss latency 786system.l2c.ReadReq_avg_miss_latency::cpu1.data 79110.542565 # average ReadReq miss latency 787system.l2c.ReadReq_avg_miss_latency::total 75736.318230 # average ReadReq miss latency 788system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1543.002649 # average UpgradeReq miss latency 789system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2751.595032 # average UpgradeReq miss latency 790system.l2c.UpgradeReq_avg_miss_latency::total 2070.694527 # average UpgradeReq miss latency 791system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 758.997429 # average SCUpgradeReq miss latency 792system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5028.250000 # average SCUpgradeReq miss latency 793system.l2c.SCUpgradeReq_avg_miss_latency::total 2589.572687 # average SCUpgradeReq miss latency 794system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67116.135593 # average ReadExReq miss latency 795system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71324.838737 # average ReadExReq miss latency 796system.l2c.ReadExReq_avg_miss_latency::total 69432.970207 # average ReadExReq miss latency 797system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81227.272727 # average overall miss latency 798system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65000 # average overall miss latency 799system.l2c.demand_avg_miss_latency::cpu0.inst 73144.862901 # average overall miss latency 800system.l2c.demand_avg_miss_latency::cpu0.data 67695.513417 # average overall miss latency 801system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85166.666667 # average overall miss latency 802system.l2c.demand_avg_miss_latency::cpu1.inst 76967.501131 # average overall miss latency 803system.l2c.demand_avg_miss_latency::cpu1.data 71915.707254 # average overall miss latency 804system.l2c.demand_avg_miss_latency::total 70397.009882 # average overall miss latency 805system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81227.272727 # average overall miss latency 806system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65000 # average overall miss latency 807system.l2c.overall_avg_miss_latency::cpu0.inst 73144.862901 # average overall miss latency 808system.l2c.overall_avg_miss_latency::cpu0.data 67695.513417 # average overall miss latency 809system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85166.666667 # average overall miss latency 810system.l2c.overall_avg_miss_latency::cpu1.inst 76967.501131 # average overall miss latency 811system.l2c.overall_avg_miss_latency::cpu1.data 71915.707254 # average overall miss latency 812system.l2c.overall_avg_miss_latency::total 70397.009882 # average overall miss latency |
| 461system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 464system.l2c.blocked::no_targets 0 # number of cycles access was blocked 465system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 467system.l2c.fast_writes 0 # number of fast writes performed 468system.l2c.cache_copies 0 # number of cache copies performed | 813system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 816system.l2c.blocked::no_targets 0 # number of cycles access was blocked 817system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.l2c.fast_writes 0 # number of fast writes performed 820system.l2c.cache_copies 0 # number of cache copies performed |
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number of ReadReq MSHR uncacheable cycles 554system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1838032 # number of ReadReq MSHR uncacheable cycles 555system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667146747 # number of ReadReq MSHR uncacheable cycles 556system.l2c.ReadReq_mshr_uncacheable_latency::total 167080901160 # number of ReadReq MSHR uncacheable cycles 557system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050375737 # number of WriteReq MSHR uncacheable cycles 558system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25934678687 # number of WriteReq MSHR uncacheable cycles 559system.l2c.WriteReq_mshr_uncacheable_latency::total 26985054424 # number of WriteReq MSHR uncacheable cycles 560system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5286835 # number of overall MSHR uncacheable cycles 561system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13457005283 # number of overall MSHR uncacheable cycles 562system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1838032 # 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mshr miss rate for overall accesses 594system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000519 # mshr miss rate for overall accesses 595system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010542 # mshr miss rate for overall accesses 596system.l2c.overall_mshr_miss_rate::cpu1.data 0.243778 # mshr miss rate for overall accesses 597system.l2c.overall_mshr_miss_rate::total 0.098752 # mshr miss rate for overall accesses 598system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency 599system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency 600system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average ReadReq mshr miss latency 601system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44454.161725 # average ReadReq mshr miss latency 602system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average ReadReq mshr miss latency 603system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average ReadReq mshr miss latency 604system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50145.589408 # average ReadReq mshr miss latency 605system.l2c.ReadReq_avg_mshr_miss_latency::total 46316.033088 # average ReadReq mshr miss latency 606system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.000583 # average UpgradeReq mshr miss latency 607system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10167.910124 # average UpgradeReq mshr miss latency 608system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10103.974474 # average UpgradeReq mshr miss latency 609system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.495370 # average SCUpgradeReq mshr miss latency 610system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.055288 # average SCUpgradeReq mshr miss latency 611system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10061.593985 # average SCUpgradeReq mshr miss latency 612system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37401.096989 # average ReadExReq mshr miss latency 613system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41147.448442 # average ReadExReq mshr miss latency 614system.l2c.ReadExReq_avg_mshr_miss_latency::total 39449.774697 # average ReadExReq mshr miss latency 615system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency 616system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency 617system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average overall mshr miss latency 618system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38044.845918 # average overall mshr miss latency 619system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average overall mshr miss latency 620system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average overall mshr miss latency 621system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41828.202768 # average overall mshr miss latency 622system.l2c.demand_avg_mshr_miss_latency::total 40498.025444 # average overall mshr miss latency 623system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency 624system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency 625system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average overall mshr miss latency 626system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38044.845918 # average overall mshr miss latency 627system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average overall mshr miss latency 628system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average overall mshr miss latency 629system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41828.202768 # average overall mshr miss latency 630system.l2c.overall_avg_mshr_miss_latency::total 40498.025444 # average overall mshr miss latency | 864system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 865system.l2c.overall_mshr_misses::cpu0.inst 6051 # number of overall MSHR misses 866system.l2c.overall_mshr_misses::cpu0.data 69459 # number of overall MSHR misses 867system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses 868system.l2c.overall_mshr_misses::cpu1.inst 6623 # number of overall MSHR misses 869system.l2c.overall_mshr_misses::cpu1.data 83711 # number of overall MSHR misses 870system.l2c.overall_mshr_misses::total 165875 # number of overall MSHR misses 871system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 756250 # number of ReadReq MSHR miss cycles 872system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles 873system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 367361750 # number of ReadReq MSHR miss cycles 874system.l2c.ReadReq_mshr_miss_latency::cpu0.data 383110245 # number of ReadReq MSHR miss cycles 875system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1310500 # number of ReadReq MSHR miss cycles 876system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 427493250 # number of ReadReq MSHR miss cycles 877system.l2c.ReadReq_mshr_miss_latency::cpu1.data 422235748 # number of ReadReq MSHR miss cycles 878system.l2c.ReadReq_mshr_miss_latency::total 1602373493 # number of ReadReq MSHR miss cycles 879system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 56779102 # number of UpgradeReq MSHR miss cycles 880system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44007360 # number of UpgradeReq MSHR miss cycles 881system.l2c.UpgradeReq_mshr_miss_latency::total 100786462 # number of UpgradeReq MSHR miss cycles 882system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7817273 # number of SCUpgradeReq MSHR miss cycles 883system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5858578 # number of SCUpgradeReq MSHR miss cycles 884system.l2c.SCUpgradeReq_mshr_miss_latency::total 13675851 # number of SCUpgradeReq MSHR miss cycles 885system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3454122942 # number of ReadExReq MSHR miss cycles 886system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4550846228 # number of ReadExReq MSHR miss cycles 887system.l2c.ReadExReq_mshr_miss_latency::total 8004969170 # number of ReadExReq MSHR miss cycles 888system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 756250 # number of demand (read+write) MSHR miss cycles 889system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles 890system.l2c.demand_mshr_miss_latency::cpu0.inst 367361750 # number of demand (read+write) MSHR miss cycles 891system.l2c.demand_mshr_miss_latency::cpu0.data 3837233187 # number of demand (read+write) MSHR miss cycles 892system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1310500 # number of demand (read+write) MSHR miss cycles 893system.l2c.demand_mshr_miss_latency::cpu1.inst 427493250 # number of demand (read+write) MSHR miss cycles 894system.l2c.demand_mshr_miss_latency::cpu1.data 4973081976 # number of demand (read+write) MSHR miss cycles 895system.l2c.demand_mshr_miss_latency::total 9607342663 # number of demand (read+write) MSHR miss cycles 896system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 756250 # number of overall MSHR miss cycles 897system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles 898system.l2c.overall_mshr_miss_latency::cpu0.inst 367361750 # number of overall MSHR miss cycles 899system.l2c.overall_mshr_miss_latency::cpu0.data 3837233187 # number of overall MSHR miss cycles 900system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1310500 # number of overall MSHR miss cycles 901system.l2c.overall_mshr_miss_latency::cpu1.inst 427493250 # number of overall MSHR miss cycles 902system.l2c.overall_mshr_miss_latency::cpu1.data 4973081976 # number of overall MSHR miss cycles 903system.l2c.overall_mshr_miss_latency::total 9607342663 # number of overall MSHR miss cycles 904system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7164750 # number of ReadReq MSHR uncacheable cycles 905system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12331011486 # number of ReadReq MSHR uncacheable cycles 906system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2446749 # number of ReadReq MSHR uncacheable cycles 907system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154885786239 # number of ReadReq MSHR uncacheable cycles 908system.l2c.ReadReq_mshr_uncacheable_latency::total 167226409224 # number of ReadReq MSHR uncacheable cycles 909system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1118932750 # number of WriteReq MSHR uncacheable cycles 910system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25567445102 # number of WriteReq MSHR uncacheable cycles 911system.l2c.WriteReq_mshr_uncacheable_latency::total 26686377852 # number of WriteReq MSHR uncacheable cycles 912system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7164750 # number of overall MSHR uncacheable cycles 913system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13449944236 # number of overall MSHR uncacheable cycles 914system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2446749 # number of overall MSHR uncacheable cycles 915system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180453231341 # number of overall MSHR uncacheable cycles 916system.l2c.overall_mshr_uncacheable_latency::total 193912787076 # number of overall MSHR uncacheable cycles 917system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for ReadReq accesses 918system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for ReadReq accesses 919system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for ReadReq accesses 920system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036493 # mshr miss rate for ReadReq accesses 921system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses 922system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for ReadReq accesses 923system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030393 # mshr miss rate for ReadReq accesses 924system.l2c.ReadReq_mshr_miss_rate::total 0.017326 # mshr miss rate for ReadReq accesses 925system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.833873 # mshr miss rate for UpgradeReq accesses 926system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860730 # mshr miss rate for UpgradeReq accesses 927system.l2c.UpgradeReq_mshr_miss_rate::total 0.845390 # mshr miss rate for UpgradeReq accesses 928system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.792261 # mshr miss rate for SCUpgradeReq accesses 929system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.774536 # mshr miss rate for SCUpgradeReq accesses 930system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784562 # mshr miss rate for SCUpgradeReq accesses 931system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566494 # mshr miss rate for ReadExReq accesses 932system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.568074 # mshr miss rate for ReadExReq accesses 933system.l2c.ReadExReq_mshr_miss_rate::total 0.567362 # mshr miss rate for ReadExReq accesses 934system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for demand accesses 935system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for demand accesses 936system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for demand accesses 937system.l2c.demand_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for demand accesses 938system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses 939system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for demand accesses 940system.l2c.demand_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for demand accesses 941system.l2c.demand_mshr_miss_rate::total 0.097105 # mshr miss rate for demand accesses 942system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for overall accesses 943system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for overall accesses 944system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for overall accesses 945system.l2c.overall_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for overall accesses 946system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses 947system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses 948system.l2c.overall_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for overall accesses 949system.l2c.overall_mshr_miss_rate::total 0.097105 # mshr miss rate for overall accesses 950system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average ReadReq mshr miss latency 951system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency 952system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average ReadReq mshr miss latency 953system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61102.112440 # average ReadReq mshr miss latency 954system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average ReadReq mshr miss latency 955system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average ReadReq mshr miss latency 956system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66724.991783 # average ReadReq mshr miss latency 957system.l2c.ReadReq_avg_mshr_miss_latency::total 63327.411493 # average ReadReq mshr miss latency 958system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.099965 # average UpgradeReq mshr miss latency 959system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.024613 # average UpgradeReq mshr miss latency 960system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.503682 # average UpgradeReq mshr miss latency 961system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.908740 # average SCUpgradeReq mshr miss latency 962system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.811644 # average SCUpgradeReq mshr miss latency 963system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.006608 # average SCUpgradeReq mshr miss latency 964system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54663.358211 # average ReadExReq mshr miss latency 965system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58809.379683 # average ReadExReq mshr miss latency 966system.l2c.ReadExReq_avg_mshr_miss_latency::total 56945.687406 # average ReadExReq mshr miss latency 967system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency 968system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency 969system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency 970system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency 971system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency 972system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency 973system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency 974system.l2c.demand_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency 975system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency 976system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency 977system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency 978system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency 979system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency 980system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency 981system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency 982system.l2c.overall_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency |
| 631system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 632system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 633system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 634system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 635system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 636system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 637system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 638system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 643system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 644system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 645system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 646system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 647system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 648system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 649system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 650system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 983system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 984system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 985system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 986system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 987system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 988system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 989system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 990system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 995system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 996system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 997system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 998system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 999system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1000system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1001system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1002system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 651system.cpu0.branchPred.lookups 5994746 # Number of BP lookups 652system.cpu0.branchPred.condPredicted 4572445 # Number of conditional branches predicted 653system.cpu0.branchPred.condIncorrect 294986 # Number of conditional branches incorrect 654system.cpu0.branchPred.BTBLookups 3765254 # Number of BTB lookups 655system.cpu0.branchPred.BTBHits 2911375 # Number of BTB hits | 1003system.toL2Bus.throughput 58542991 # Throughput (bytes/s) 1004system.toL2Bus.trans_dist::ReadReq 2739841 # Transaction distribution 1005system.toL2Bus.trans_dist::ReadResp 2739840 # Transaction distribution 1006system.toL2Bus.trans_dist::WriteReq 769166 # Transaction distribution 1007system.toL2Bus.trans_dist::WriteResp 769166 # Transaction distribution 1008system.toL2Bus.trans_dist::Writeback 583280 # Transaction distribution 1009system.toL2Bus.trans_dist::UpgradeReq 34832 # Transaction distribution 1010system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution 1011system.toL2Bus.trans_dist::UpgradeResp 53489 # Transaction distribution 1012system.toL2Bus.trans_dist::ReadExReq 259511 # Transaction distribution 1013system.toL2Bus.trans_dist::ReadExResp 259511 # Transaction distribution 1014system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 800088 # Packet count per connected master and slave (bytes) 1015system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073172 # Packet count per connected master and slave (bytes) 1016system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13793 # Packet count per connected master and slave (bytes) 1017system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 57051 # Packet count per connected master and slave (bytes) 1018system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1229933 # Packet count per connected master and slave (bytes) 1019system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4820895 # Packet count per connected master and slave (bytes) 1020system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 15468 # Packet count per connected master and slave (bytes) 1021system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 74350 # Packet count per connected master and slave (bytes) 1022system.toL2Bus.pkt_count 8084750 # Packet count per connected master and slave (bytes) 1023system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25585472 # Cumulative packet size per connected master and slave (bytes) 1024system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34695904 # Cumulative packet size per connected master and slave (bytes) 1025system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 18508 # Cumulative packet size per connected master and slave (bytes) 1026system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 92124 # Cumulative packet size per connected master and slave (bytes) 1027system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 39339008 # Cumulative packet size per connected master and slave (bytes) 1028system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 48266196 # Cumulative packet size per connected master and slave (bytes) 1029system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 22912 # Cumulative packet size per connected master and slave (bytes) 1030system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 131012 # Cumulative packet size per connected master and slave (bytes) 1031system.toL2Bus.tot_pkt_size 148151136 # Cumulative packet size per connected master and slave (bytes) 1032system.toL2Bus.data_through_bus 148151136 # Total data (bytes) 1033system.toL2Bus.snoop_data_through_bus 4868352 # Total snoop data (bytes) 1034system.toL2Bus.reqLayer0.occupancy 4921338984 # Layer occupancy (ticks) 1035system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1036system.toL2Bus.respLayer0.occupancy 1802175919 # Layer occupancy (ticks) 1037system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1038system.toL2Bus.respLayer1.occupancy 1506283904 # Layer occupancy (ticks) 1039system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1040system.toL2Bus.respLayer2.occupancy 9191448 # Layer occupancy (ticks) 1041system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1042system.toL2Bus.respLayer3.occupancy 34164696 # Layer occupancy (ticks) 1043system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1044system.toL2Bus.respLayer4.occupancy 2769642515 # Layer occupancy (ticks) 1045system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) 1046system.toL2Bus.respLayer5.occupancy 3249270250 # Layer occupancy (ticks) 1047system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%) 1048system.toL2Bus.respLayer6.occupancy 9767440 # Layer occupancy (ticks) 1049system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) 1050system.toL2Bus.respLayer7.occupancy 41898883 # Layer occupancy (ticks) 1051system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) 1052system.iobus.throughput 47250451 # Throughput (bytes/s) 1053system.iobus.trans_dist::ReadReq 16322888 # Transaction distribution 1054system.iobus.trans_dist::ReadResp 16322888 # Transaction distribution 1055system.iobus.trans_dist::WriteReq 8066 # Transaction distribution 1056system.iobus.trans_dist::WriteResp 8066 # Transaction distribution 1057system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) 1058system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) 1059system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1060system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) 1061system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1062system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1063system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) 1064system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1065system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1066system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1067system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1068system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1069system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1070system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1071system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1072system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1073system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1074system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1075system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1076system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1077system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1078system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1079system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1080system.iobus.pkt_count_system.bridge.master::total 2384276 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) 1085system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1086system.iobus.pkt_count::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) 1087system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1088system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1093system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1094system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1096system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1098system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1100system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1104system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1105system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1106system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 1107system.iobus.pkt_count::total 32661908 # Packet count per connected master and slave (bytes) 1108system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1131system.iobus.tot_pkt_size_system.bridge.master::total 2392552 # Cumulative packet size per connected master and slave (bytes) 1132system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 1133system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 1134system.iobus.tot_pkt_size::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) 1135system.iobus.tot_pkt_size::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) 1136system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1137system.iobus.tot_pkt_size::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 1138system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1139system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1140system.iobus.tot_pkt_size::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) 1141system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1142system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1143system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1145system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 1158system.iobus.tot_pkt_size::total 123503080 # Cumulative packet size per connected master and slave (bytes) 1159system.iobus.data_through_bus 123503080 # Total data (bytes) 1160system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) 1161system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1162system.iobus.reqLayer1.occupancy 4430000 # Layer occupancy (ticks) 1163system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1164system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1165system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1166system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) 1167system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1168system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1169system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1170system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1171system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1172system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) 1173system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1174system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 1175system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1176system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1177system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1178system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1179system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1180system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 1181system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1182system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 1183system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1184system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1185system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1186system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1187system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1188system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1189system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1190system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 1191system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1192system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1193system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1194system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1195system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1196system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 1197system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1198system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1199system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1201system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1203system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1205system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 1207system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 1208system.iobus.respLayer0.occupancy 2376210000 # Layer occupancy (ticks) 1209system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 1210system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) 1211system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) 1212system.cpu0.branchPred.lookups 6073314 # Number of BP lookups 1213system.cpu0.branchPred.condPredicted 4627623 # Number of conditional branches predicted 1214system.cpu0.branchPred.condIncorrect 295826 # Number of conditional branches incorrect 1215system.cpu0.branchPred.BTBLookups 3795187 # Number of BTB lookups 1216system.cpu0.branchPred.BTBHits 2949225 # Number of BTB hits |
| 656system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1217system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 657system.cpu0.branchPred.BTBHitPct 77.322141 # BTB Hit Percentage 658system.cpu0.branchPred.usedRAS 671631 # Number of times the RAS was used to get a target. 659system.cpu0.branchPred.RASInCorrect 28577 # Number of incorrect RAS predictions. | 1218system.cpu0.branchPred.BTBHitPct 77.709610 # BTB Hit Percentage 1219system.cpu0.branchPred.usedRAS 683153 # Number of times the RAS was used to get a target. 1220system.cpu0.branchPred.RASInCorrect 28183 # Number of incorrect RAS predictions. |
| 660system.cpu0.dtb.inst_hits 0 # ITB inst hits 661system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1221system.cpu0.dtb.inst_hits 0 # ITB inst hits 1222system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 662system.cpu0.dtb.read_hits 8900432 # DTB read hits 663system.cpu0.dtb.read_misses 28720 # DTB read misses 664system.cpu0.dtb.write_hits 5136537 # DTB write hits 665system.cpu0.dtb.write_misses 5640 # DTB write misses | 1223system.cpu0.dtb.read_hits 8970256 # DTB read hits 1224system.cpu0.dtb.read_misses 29375 # DTB read misses 1225system.cpu0.dtb.write_hits 5214738 # DTB write hits 1226system.cpu0.dtb.write_misses 5731 # DTB write misses |
| 666system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 667system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 668system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 669system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1227system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1228system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1229system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1230system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 670system.cpu0.dtb.flush_entries 1815 # Number of entries that have been flushed from TLB 671system.cpu0.dtb.align_faults 1027 # Number of TLB faults due to alignment restrictions 672system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch | 1231system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB 1232system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions 1233system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch |
| 673system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1234system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 674system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions 675system.cpu0.dtb.read_accesses 8929152 # DTB read accesses 676system.cpu0.dtb.write_accesses 5142177 # DTB write accesses | 1235system.cpu0.dtb.perms_faults 591 # Number of TLB faults due to permissions restrictions 1236system.cpu0.dtb.read_accesses 8999631 # DTB read accesses 1237system.cpu0.dtb.write_accesses 5220469 # DTB write accesses |
| 677system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1238system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 678system.cpu0.dtb.hits 14036969 # DTB hits 679system.cpu0.dtb.misses 34360 # DTB misses 680system.cpu0.dtb.accesses 14071329 # DTB accesses 681system.cpu0.itb.inst_hits 4213831 # ITB inst hits 682system.cpu0.itb.inst_misses 5055 # ITB inst misses | 1239system.cpu0.dtb.hits 14184994 # DTB hits 1240system.cpu0.dtb.misses 35106 # DTB misses 1241system.cpu0.dtb.accesses 14220100 # DTB accesses 1242system.cpu0.itb.inst_hits 4276462 # ITB inst hits 1243system.cpu0.itb.inst_misses 5070 # ITB inst misses |
| 683system.cpu0.itb.read_hits 0 # DTB read hits 684system.cpu0.itb.read_misses 0 # DTB read misses 685system.cpu0.itb.write_hits 0 # DTB write hits 686system.cpu0.itb.write_misses 0 # DTB write misses 687system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 688system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 689system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 690system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1244system.cpu0.itb.read_hits 0 # DTB read hits 1245system.cpu0.itb.read_misses 0 # DTB read misses 1246system.cpu0.itb.write_hits 0 # DTB write hits 1247system.cpu0.itb.write_misses 0 # DTB write misses 1248system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1249system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1250system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1251system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 691system.cpu0.itb.flush_entries 1341 # Number of entries that have been flushed from TLB | 1252system.cpu0.itb.flush_entries 1351 # Number of entries that have been flushed from TLB |
| 692system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 693system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 694system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1253system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1254system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1255system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 695system.cpu0.itb.perms_faults 1480 # Number of TLB faults due to permissions restrictions | 1256system.cpu0.itb.perms_faults 1356 # Number of TLB faults due to permissions restrictions |
| 696system.cpu0.itb.read_accesses 0 # DTB read accesses 697system.cpu0.itb.write_accesses 0 # DTB write accesses | 1257system.cpu0.itb.read_accesses 0 # DTB read accesses 1258system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 698system.cpu0.itb.inst_accesses 4218886 # ITB inst accesses 699system.cpu0.itb.hits 4213831 # DTB hits 700system.cpu0.itb.misses 5055 # DTB misses 701system.cpu0.itb.accesses 4218886 # DTB accesses 702system.cpu0.numCycles 67827180 # number of cpu cycles simulated | 1259system.cpu0.itb.inst_accesses 4281532 # ITB inst accesses 1260system.cpu0.itb.hits 4276462 # DTB hits 1261system.cpu0.itb.misses 5070 # DTB misses 1262system.cpu0.itb.accesses 4281532 # DTB accesses 1263system.cpu0.numCycles 69613456 # number of cpu cycles simulated |
| 703system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 704system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1264system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1265system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 705system.cpu0.fetch.icacheStallCycles 11769589 # Number of cycles fetch is stalled on an Icache miss 706system.cpu0.fetch.Insts 31997398 # Number of instructions fetch has processed 707system.cpu0.fetch.Branches 5994746 # Number of branches that fetch encountered 708system.cpu0.fetch.predictedBranches 3583006 # Number of branches that fetch has predicted taken 709system.cpu0.fetch.Cycles 7510057 # Number of cycles fetch has run and was not squashing or blocked 710system.cpu0.fetch.SquashCycles 1450935 # Number of cycles fetch has spent squashing 711system.cpu0.fetch.TlbCycles 59891 # Number of cycles fetch has spent waiting for tlb 712system.cpu0.fetch.BlockedCycles 19410639 # Number of cycles fetch has spent blocked 713system.cpu0.fetch.MiscStallCycles 4833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 714system.cpu0.fetch.PendingTrapStallCycles 47194 # Number of stall cycles due to pending traps 715system.cpu0.fetch.PendingQuiesceStallCycles 1299057 # Number of stall cycles due to pending quiesce instructions 716system.cpu0.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR 717system.cpu0.fetch.CacheLines 4212263 # Number of cache lines fetched 718system.cpu0.fetch.IcacheSquashes 157193 # Number of outstanding Icache misses that were squashed 719system.cpu0.fetch.ItlbSquashes 2052 # Number of outstanding ITLB misses that were squashed 720system.cpu0.fetch.rateDist::samples 41143300 # Number of instructions fetched each cycle (Total) 721system.cpu0.fetch.rateDist::mean 1.004817 # Number of instructions fetched each cycle (Total) 722system.cpu0.fetch.rateDist::stdev 2.385260 # Number of instructions fetched each cycle (Total) | 1266system.cpu0.fetch.icacheStallCycles 11926468 # Number of cycles fetch is stalled on an Icache miss 1267system.cpu0.fetch.Insts 32461716 # Number of instructions fetch has processed 1268system.cpu0.fetch.Branches 6073314 # Number of branches that fetch encountered 1269system.cpu0.fetch.predictedBranches 3632378 # Number of branches that fetch has predicted taken 1270system.cpu0.fetch.Cycles 7613392 # Number of cycles fetch has run and was not squashing or blocked 1271system.cpu0.fetch.SquashCycles 1460130 # Number of cycles fetch has spent squashing 1272system.cpu0.fetch.TlbCycles 63151 # Number of cycles fetch has spent waiting for tlb 1273system.cpu0.fetch.BlockedCycles 20074417 # Number of cycles fetch has spent blocked 1274system.cpu0.fetch.MiscStallCycles 5834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1275system.cpu0.fetch.PendingTrapStallCycles 46093 # Number of stall cycles due to pending traps 1276system.cpu0.fetch.PendingQuiesceStallCycles 1371911 # Number of stall cycles due to pending quiesce instructions 1277system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR 1278system.cpu0.fetch.CacheLines 4274981 # Number of cache lines fetched 1279system.cpu0.fetch.IcacheSquashes 157877 # Number of outstanding Icache misses that were squashed 1280system.cpu0.fetch.ItlbSquashes 2111 # Number of outstanding ITLB misses that were squashed 1281system.cpu0.fetch.rateDist::samples 42149460 # Number of instructions fetched each cycle (Total) 1282system.cpu0.fetch.rateDist::mean 0.995068 # Number of instructions fetched each cycle (Total) 1283system.cpu0.fetch.rateDist::stdev 2.376418 # Number of instructions fetched each cycle (Total) |
| 723system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1284system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 724system.cpu0.fetch.rateDist::0 33640645 81.76% 81.76% # Number of instructions fetched each cycle (Total) 725system.cpu0.fetch.rateDist::1 563027 1.37% 83.13% # Number of instructions fetched each cycle (Total) 726system.cpu0.fetch.rateDist::2 816788 1.99% 85.12% # Number of instructions fetched each cycle (Total) 727system.cpu0.fetch.rateDist::3 677485 1.65% 86.76% # Number of instructions fetched each cycle (Total) 728system.cpu0.fetch.rateDist::4 772099 1.88% 88.64% # Number of instructions fetched each cycle (Total) 729system.cpu0.fetch.rateDist::5 558236 1.36% 90.00% # Number of instructions fetched each cycle (Total) 730system.cpu0.fetch.rateDist::6 667723 1.62% 91.62% # Number of instructions fetched each cycle (Total) 731system.cpu0.fetch.rateDist::7 351865 0.86% 92.48% # Number of instructions fetched each cycle (Total) 732system.cpu0.fetch.rateDist::8 3095432 7.52% 100.00% # Number of instructions fetched each cycle (Total) | 1285system.cpu0.fetch.rateDist::0 34543319 81.95% 81.95% # Number of instructions fetched each cycle (Total) 1286system.cpu0.fetch.rateDist::1 572779 1.36% 83.31% # Number of instructions fetched each cycle (Total) 1287system.cpu0.fetch.rateDist::2 825233 1.96% 85.27% # Number of instructions fetched each cycle (Total) 1288system.cpu0.fetch.rateDist::3 684006 1.62% 86.89% # Number of instructions fetched each cycle (Total) 1289system.cpu0.fetch.rateDist::4 778589 1.85% 88.74% # Number of instructions fetched each cycle (Total) 1290system.cpu0.fetch.rateDist::5 565339 1.34% 90.08% # Number of instructions fetched each cycle (Total) 1291system.cpu0.fetch.rateDist::6 679715 1.61% 91.70% # Number of instructions fetched each cycle (Total) 1292system.cpu0.fetch.rateDist::7 356870 0.85% 92.54% # Number of instructions fetched each cycle (Total) 1293system.cpu0.fetch.rateDist::8 3143610 7.46% 100.00% # Number of instructions fetched each cycle (Total) |
| 733system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 734system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 735system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1294system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1295system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1296system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 736system.cpu0.fetch.rateDist::total 41143300 # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.branchRate 0.088383 # Number of branch fetches per cycle 738system.cpu0.fetch.rate 0.471749 # Number of inst fetches per cycle 739system.cpu0.decode.IdleCycles 12271204 # Number of cycles decode is idle 740system.cpu0.decode.BlockedCycles 20567331 # Number of cycles decode is blocked 741system.cpu0.decode.RunCycles 6814121 # Number of cycles decode is running 742system.cpu0.decode.UnblockCycles 512354 # Number of cycles decode is unblocking 743system.cpu0.decode.SquashCycles 978290 # Number of cycles decode is squashing 744system.cpu0.decode.BranchResolved 934838 # Number of times decode resolved a branch 745system.cpu0.decode.BranchMispred 64553 # Number of times decode detected a branch misprediction 746system.cpu0.decode.DecodedInsts 39983053 # Number of instructions handled by decode 747system.cpu0.decode.SquashedInsts 212073 # Number of squashed instructions handled by decode 748system.cpu0.rename.SquashCycles 978290 # Number of cycles rename is squashing 749system.cpu0.rename.IdleCycles 12839379 # Number of cycles rename is idle 750system.cpu0.rename.BlockCycles 5742381 # Number of cycles rename is blocking 751system.cpu0.rename.serializeStallCycles 12712172 # count of cycles rename stalled for serializing inst 752system.cpu0.rename.RunCycles 6708467 # Number of cycles rename is running 753system.cpu0.rename.UnblockCycles 2162611 # Number of cycles rename is unblocking 754system.cpu0.rename.RenamedInsts 38883586 # Number of instructions processed by rename 755system.cpu0.rename.ROBFullEvents 1814 # Number of times rename has blocked due to ROB full 756system.cpu0.rename.IQFullEvents 436137 # Number of times rename has blocked due to IQ full 757system.cpu0.rename.LSQFullEvents 1233923 # Number of times rename has blocked due to LSQ full 758system.cpu0.rename.FullRegisterEvents 17 # Number of times there has been no free registers 759system.cpu0.rename.RenamedOperands 39230664 # Number of destination operands rename has renamed 760system.cpu0.rename.RenameLookups 175613245 # Number of register rename lookups that rename has made 761system.cpu0.rename.int_rename_lookups 175579140 # Number of integer rename lookups 762system.cpu0.rename.fp_rename_lookups 34105 # Number of floating rename lookups 763system.cpu0.rename.CommittedMaps 30916187 # Number of HB maps that are committed 764system.cpu0.rename.UndoneMaps 8314476 # Number of HB maps that are undone due to squashing 765system.cpu0.rename.serializingInsts 411042 # count of serializing insts renamed 766system.cpu0.rename.tempSerializingInsts 370243 # count of temporary serializing insts renamed 767system.cpu0.rename.skidInsts 5355635 # count of insts added to the skid buffer 768system.cpu0.memDep0.insertedLoads 7643947 # Number of loads inserted to the mem dependence unit. 769system.cpu0.memDep0.insertedStores 5684540 # Number of stores inserted to the mem dependence unit. 770system.cpu0.memDep0.conflictingLoads 1124242 # Number of conflicting loads. 771system.cpu0.memDep0.conflictingStores 1215247 # Number of conflicting stores. 772system.cpu0.iq.iqInstsAdded 36809311 # Number of instructions added to the IQ (excludes non-spec) 773system.cpu0.iq.iqNonSpecInstsAdded 895353 # Number of non-speculative instructions added to the IQ 774system.cpu0.iq.iqInstsIssued 37222613 # Number of instructions issued 775system.cpu0.iq.iqSquashedInstsIssued 81088 # Number of squashed instructions issued 776system.cpu0.iq.iqSquashedInstsExamined 6285112 # Number of squashed instructions iterated over during squash; mainly for profiling 777system.cpu0.iq.iqSquashedOperandsExamined 13160919 # Number of squashed operands that are examined and possibly removed from graph 778system.cpu0.iq.iqSquashedNonSpecRemoved 256794 # Number of squashed non-spec instructions that were removed 779system.cpu0.iq.issued_per_cycle::samples 41143300 # Number of insts issued each cycle 780system.cpu0.iq.issued_per_cycle::mean 0.904707 # Number of insts issued each cycle 781system.cpu0.iq.issued_per_cycle::stdev 1.513127 # Number of insts issued each cycle | 1297system.cpu0.fetch.rateDist::total 42149460 # Number of instructions fetched each cycle (Total) 1298system.cpu0.fetch.branchRate 0.087243 # Number of branch fetches per cycle 1299system.cpu0.fetch.rate 0.466314 # Number of inst fetches per cycle 1300system.cpu0.decode.IdleCycles 12452855 # Number of cycles decode is idle 1301system.cpu0.decode.BlockedCycles 21284567 # Number of cycles decode is blocked 1302system.cpu0.decode.RunCycles 6905227 # Number of cycles decode is running 1303system.cpu0.decode.UnblockCycles 522550 # Number of cycles decode is unblocking 1304system.cpu0.decode.SquashCycles 984261 # Number of cycles decode is squashing 1305system.cpu0.decode.BranchResolved 948796 # Number of times decode resolved a branch 1306system.cpu0.decode.BranchMispred 64785 # Number of times decode detected a branch misprediction 1307system.cpu0.decode.DecodedInsts 40574738 # Number of instructions handled by decode 1308system.cpu0.decode.SquashedInsts 212216 # Number of squashed instructions handled by decode 1309system.cpu0.rename.SquashCycles 984261 # Number of cycles rename is squashing 1310system.cpu0.rename.IdleCycles 13028707 # Number of cycles rename is idle 1311system.cpu0.rename.BlockCycles 5941224 # Number of cycles rename is blocking 1312system.cpu0.rename.serializeStallCycles 13201317 # count of cycles rename stalled for serializing inst 1313system.cpu0.rename.RunCycles 6800913 # Number of cycles rename is running 1314system.cpu0.rename.UnblockCycles 2193038 # Number of cycles rename is unblocking 1315system.cpu0.rename.RenamedInsts 39456506 # Number of instructions processed by rename 1316system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full 1317system.cpu0.rename.IQFullEvents 442978 # Number of times rename has blocked due to IQ full 1318system.cpu0.rename.LSQFullEvents 1248488 # Number of times rename has blocked due to LSQ full 1319system.cpu0.rename.FullRegisterEvents 66 # Number of times there has been no free registers 1320system.cpu0.rename.RenamedOperands 39834265 # Number of destination operands rename has renamed 1321system.cpu0.rename.RenameLookups 178291734 # Number of register rename lookups that rename has made 1322system.cpu0.rename.int_rename_lookups 178257443 # Number of integer rename lookups 1323system.cpu0.rename.fp_rename_lookups 34291 # Number of floating rename lookups 1324system.cpu0.rename.CommittedMaps 31450110 # Number of HB maps that are committed 1325system.cpu0.rename.UndoneMaps 8384154 # Number of HB maps that are undone due to squashing 1326system.cpu0.rename.serializingInsts 420012 # count of serializing insts renamed 1327system.cpu0.rename.tempSerializingInsts 376763 # count of temporary serializing insts renamed 1328system.cpu0.rename.skidInsts 5452877 # count of insts added to the skid buffer 1329system.cpu0.memDep0.insertedLoads 7762434 # Number of loads inserted to the mem dependence unit. 1330system.cpu0.memDep0.insertedStores 5776236 # Number of stores inserted to the mem dependence unit. 1331system.cpu0.memDep0.conflictingLoads 1132872 # Number of conflicting loads. 1332system.cpu0.memDep0.conflictingStores 1233884 # Number of conflicting stores. 1333system.cpu0.iq.iqInstsAdded 37360552 # Number of instructions added to the IQ (excludes non-spec) 1334system.cpu0.iq.iqNonSpecInstsAdded 904892 # Number of non-speculative instructions added to the IQ 1335system.cpu0.iq.iqInstsIssued 37716432 # Number of instructions issued 1336system.cpu0.iq.iqSquashedInstsIssued 82271 # Number of squashed instructions issued 1337system.cpu0.iq.iqSquashedInstsExamined 6323448 # Number of squashed instructions iterated over during squash; mainly for profiling 1338system.cpu0.iq.iqSquashedOperandsExamined 13282471 # Number of squashed operands that are examined and possibly removed from graph 1339system.cpu0.iq.iqSquashedNonSpecRemoved 257104 # Number of squashed non-spec instructions that were removed 1340system.cpu0.iq.issued_per_cycle::samples 42149460 # Number of insts issued each cycle 1341system.cpu0.iq.issued_per_cycle::mean 0.894826 # Number of insts issued each cycle 1342system.cpu0.iq.issued_per_cycle::stdev 1.507768 # Number of insts issued each cycle |
| 782system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1343system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 783system.cpu0.iq.issued_per_cycle::0 26016757 63.23% 63.23% # Number of insts issued each cycle 784system.cpu0.iq.issued_per_cycle::1 5731331 13.93% 77.16% # Number of insts issued each cycle 785system.cpu0.iq.issued_per_cycle::2 3155319 7.67% 84.83% # Number of insts issued each cycle 786system.cpu0.iq.issued_per_cycle::3 2471251 6.01% 90.84% # Number of insts issued each cycle 787system.cpu0.iq.issued_per_cycle::4 2103314 5.11% 95.95% # Number of insts issued each cycle 788system.cpu0.iq.issued_per_cycle::5 932641 2.27% 98.22% # Number of insts issued each cycle 789system.cpu0.iq.issued_per_cycle::6 493188 1.20% 99.42% # Number of insts issued each cycle 790system.cpu0.iq.issued_per_cycle::7 184690 0.45% 99.87% # Number of insts issued each cycle 791system.cpu0.iq.issued_per_cycle::8 54809 0.13% 100.00% # Number of insts issued each cycle | 1344system.cpu0.iq.issued_per_cycle::0 26809075 63.60% 63.60% # Number of insts issued each cycle 1345system.cpu0.iq.issued_per_cycle::1 5821539 13.81% 77.42% # Number of insts issued each cycle 1346system.cpu0.iq.issued_per_cycle::2 3209963 7.62% 85.03% # Number of insts issued each cycle 1347system.cpu0.iq.issued_per_cycle::3 2497911 5.93% 90.96% # Number of insts issued each cycle 1348system.cpu0.iq.issued_per_cycle::4 2123670 5.04% 96.00% # Number of insts issued each cycle 1349system.cpu0.iq.issued_per_cycle::5 939017 2.23% 98.22% # Number of insts issued each cycle 1350system.cpu0.iq.issued_per_cycle::6 502938 1.19% 99.42% # Number of insts issued each cycle 1351system.cpu0.iq.issued_per_cycle::7 188935 0.45% 99.87% # Number of insts issued each cycle 1352system.cpu0.iq.issued_per_cycle::8 56412 0.13% 100.00% # Number of insts issued each cycle |
| 792system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 793system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 794system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1353system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1354system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1355system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 795system.cpu0.iq.issued_per_cycle::total 41143300 # Number of insts issued each cycle | 1356system.cpu0.iq.issued_per_cycle::total 42149460 # Number of insts issued each cycle |
| 796system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1357system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 797system.cpu0.iq.fu_full::IntAlu 26572 2.49% 2.49% # attempts to use FU when none available 798system.cpu0.iq.fu_full::IntMult 453 0.04% 2.53% # attempts to use FU when none available 799system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available 800system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available 801system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available 802system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available 803system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available 804system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available 805system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available 806system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available 807system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available 808system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available 809system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available 810system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available 811system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available 812system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available 813system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available 814system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available 815system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available 816system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available 817system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available 818system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available 819system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available 820system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available 821system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available 822system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available 823system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available 824system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available 825system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available 826system.cpu0.iq.fu_full::MemRead 841830 78.79% 81.32% # attempts to use FU when none available 827system.cpu0.iq.fu_full::MemWrite 199561 18.68% 100.00% # attempts to use FU when none available | 1358system.cpu0.iq.fu_full::IntAlu 27471 2.55% 2.55% # attempts to use FU when none available 1359system.cpu0.iq.fu_full::IntMult 463 0.04% 2.60% # attempts to use FU when none available 1360system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available 1361system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available 1362system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available 1363system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available 1364system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available 1365system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available 1366system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available 1367system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available 1368system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available 1369system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available 1370system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available 1371system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available 1372system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available 1373system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available 1374system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available 1375system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available 1376system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available 1377system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available 1378system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available 1379system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available 1380system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available 1381system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available 1382system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available 1383system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available 1384system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available 1385system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available 1386system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available 1387system.cpu0.iq.fu_full::MemRead 839894 78.10% 80.70% # attempts to use FU when none available 1388system.cpu0.iq.fu_full::MemWrite 207538 19.30% 100.00% # attempts to use FU when none available |
| 828system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 829system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1389system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1390system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 830system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued 831system.cpu0.iq.FU_type_0::IntAlu 22321556 59.97% 60.11% # Type of FU issued 832system.cpu0.iq.FU_type_0::IntMult 46948 0.13% 60.23% # Type of FU issued 833system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued 834system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued 835system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued 836system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued 837system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued 838system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued 839system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued 840system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued 841system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued 842system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued 843system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued 844system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued 845system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.23% # Type of FU issued 846system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued 847system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued 848system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued 849system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued 850system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued 851system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued 852system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued 853system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued 854system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued 856system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Type of FU issued 857system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued 858system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued 859system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued 860system.cpu0.iq.FU_type_0::MemRead 9357811 25.14% 85.38% # Type of FU issued 861system.cpu0.iq.FU_type_0::MemWrite 5443427 14.62% 100.00% # Type of FU issued | 1391system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued 1392system.cpu0.iq.FU_type_0::IntAlu 22648900 60.05% 60.19% # Type of FU issued 1393system.cpu0.iq.FU_type_0::IntMult 47937 0.13% 60.32% # Type of FU issued 1394system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued 1395system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued 1396system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued 1397system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued 1398system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued 1399system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued 1400system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued 1401system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued 1402system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued 1403system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued 1404system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued 1405system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued 1406system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued 1407system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued 1408system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued 1409system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued 1410system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.32% # Type of FU issued 1411system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued 1412system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued 1413system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued 1414system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued 1415system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued 1416system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued 1417system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued 1418system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued 1419system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.32% # Type of FU issued 1420system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued 1421system.cpu0.iq.FU_type_0::MemRead 9431477 25.01% 85.32% # Type of FU issued 1422system.cpu0.iq.FU_type_0::MemWrite 5535066 14.68% 100.00% # Type of FU issued |
| 862system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 863system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1423system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1424system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 864system.cpu0.iq.FU_type_0::total 37222613 # Type of FU issued 865system.cpu0.iq.rate 0.548786 # Inst issue rate 866system.cpu0.iq.fu_busy_cnt 1068416 # FU busy when requested 867system.cpu0.iq.fu_busy_rate 0.028703 # FU busy rate (busy events/executed inst) 868system.cpu0.iq.int_inst_queue_reads 116763775 # Number of integer instruction queue reads 869system.cpu0.iq.int_inst_queue_writes 43997708 # Number of integer instruction queue writes 870system.cpu0.iq.int_inst_queue_wakeup_accesses 34321266 # Number of integer instruction queue wakeup accesses 871system.cpu0.iq.fp_inst_queue_reads 8390 # Number of floating instruction queue reads 872system.cpu0.iq.fp_inst_queue_writes 4632 # Number of floating instruction queue writes 873system.cpu0.iq.fp_inst_queue_wakeup_accesses 3861 # Number of floating instruction queue wakeup accesses 874system.cpu0.iq.int_alu_accesses 38234480 # Number of integer alu accesses 875system.cpu0.iq.fp_alu_accesses 4400 # Number of floating point alu accesses 876system.cpu0.iew.lsq.thread0.forwLoads 306660 # Number of loads that had data forwarded from stores | 1425system.cpu0.iq.FU_type_0::total 37716432 # Type of FU issued 1426system.cpu0.iq.rate 0.541798 # Inst issue rate 1427system.cpu0.iq.fu_busy_cnt 1075366 # FU busy when requested 1428system.cpu0.iq.fu_busy_rate 0.028512 # FU busy rate (busy events/executed inst) 1429system.cpu0.iq.int_inst_queue_reads 118766388 # Number of integer instruction queue reads 1430system.cpu0.iq.int_inst_queue_writes 44596758 # Number of integer instruction queue writes 1431system.cpu0.iq.int_inst_queue_wakeup_accesses 34851054 # Number of integer instruction queue wakeup accesses 1432system.cpu0.iq.fp_inst_queue_reads 8389 # Number of floating instruction queue reads 1433system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes 1434system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses 1435system.cpu0.iq.int_alu_accesses 38735073 # Number of integer alu accesses 1436system.cpu0.iq.fp_alu_accesses 4381 # Number of floating point alu accesses 1437system.cpu0.iew.lsq.thread0.forwLoads 316422 # Number of loads that had data forwarded from stores |
| 877system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1438system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 878system.cpu0.iew.lsq.thread0.squashedLoads 1372064 # Number of loads squashed 879system.cpu0.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed 880system.cpu0.iew.lsq.thread0.memOrderViolation 13106 # Number of memory ordering violations 881system.cpu0.iew.lsq.thread0.squashedStores 537968 # Number of stores squashed | 1439system.cpu0.iew.lsq.thread0.squashedLoads 1379018 # Number of loads squashed 1440system.cpu0.iew.lsq.thread0.ignoredResponses 2578 # Number of memory responses ignored because the instruction is squashed 1441system.cpu0.iew.lsq.thread0.memOrderViolation 13049 # Number of memory ordering violations 1442system.cpu0.iew.lsq.thread0.squashedStores 541624 # Number of stores squashed |
| 882system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 883system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1443system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1444system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 884system.cpu0.iew.lsq.thread0.rescheduledLoads 2192754 # Number of loads that were rescheduled 885system.cpu0.iew.lsq.thread0.cacheBlocked 5299 # Number of times an access to memory failed due to the cache being blocked | 1445system.cpu0.iew.lsq.thread0.rescheduledLoads 2149592 # Number of loads that were rescheduled 1446system.cpu0.iew.lsq.thread0.cacheBlocked 6129 # Number of times an access to memory failed due to the cache being blocked |
| 886system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1447system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 887system.cpu0.iew.iewSquashCycles 978290 # Number of cycles IEW is squashing 888system.cpu0.iew.iewBlockCycles 4120588 # Number of cycles IEW is blocking 889system.cpu0.iew.iewUnblockCycles 98455 # Number of cycles IEW is unblocking 890system.cpu0.iew.iewDispatchedInsts 37822346 # Number of instructions dispatched to IQ 891system.cpu0.iew.iewDispSquashedInsts 84553 # Number of squashed instructions skipped by dispatch 892system.cpu0.iew.iewDispLoadInsts 7643947 # Number of dispatched load instructions 893system.cpu0.iew.iewDispStoreInsts 5684540 # Number of dispatched store instructions 894system.cpu0.iew.iewDispNonSpecInsts 571228 # Number of dispatched non-speculative instructions 895system.cpu0.iew.iewIQFullEvents 39920 # Number of times the IQ has become full, causing a stall 896system.cpu0.iew.iewLSQFullEvents 2911 # Number of times the LSQ has become full, causing a stall 897system.cpu0.iew.memOrderViolationEvents 13106 # Number of memory order violations 898system.cpu0.iew.predictedTakenIncorrect 150072 # Number of branches that were predicted taken incorrectly 899system.cpu0.iew.predictedNotTakenIncorrect 117309 # Number of branches that were predicted not taken incorrectly 900system.cpu0.iew.branchMispredicts 267381 # Number of branch mispredicts detected at execute 901system.cpu0.iew.iewExecutedInsts 36846322 # Number of executed instructions 902system.cpu0.iew.iewExecLoadInsts 9215739 # Number of load instructions executed 903system.cpu0.iew.iewExecSquashedInsts 376291 # Number of squashed instructions skipped in execute | 1448system.cpu0.iew.iewSquashCycles 984261 # Number of cycles IEW is squashing 1449system.cpu0.iew.iewBlockCycles 4297602 # Number of cycles IEW is blocking 1450system.cpu0.iew.iewUnblockCycles 105996 # Number of cycles IEW is unblocking 1451system.cpu0.iew.iewDispatchedInsts 38383622 # Number of instructions dispatched to IQ 1452system.cpu0.iew.iewDispSquashedInsts 87186 # Number of squashed instructions skipped by dispatch 1453system.cpu0.iew.iewDispLoadInsts 7762434 # Number of dispatched load instructions 1454system.cpu0.iew.iewDispStoreInsts 5776236 # Number of dispatched store instructions 1455system.cpu0.iew.iewDispNonSpecInsts 577553 # Number of dispatched non-speculative instructions 1456system.cpu0.iew.iewIQFullEvents 40750 # Number of times the IQ has become full, causing a stall 1457system.cpu0.iew.iewLSQFullEvents 2975 # Number of times the LSQ has become full, causing a stall 1458system.cpu0.iew.memOrderViolationEvents 13049 # Number of memory order violations 1459system.cpu0.iew.predictedTakenIncorrect 150118 # Number of branches that were predicted taken incorrectly 1460system.cpu0.iew.predictedNotTakenIncorrect 117853 # Number of branches that were predicted not taken incorrectly 1461system.cpu0.iew.branchMispredicts 267971 # Number of branch mispredicts detected at execute 1462system.cpu0.iew.iewExecutedInsts 37335026 # Number of executed instructions 1463system.cpu0.iew.iewExecLoadInsts 9287293 # Number of load instructions executed 1464system.cpu0.iew.iewExecSquashedInsts 381406 # Number of squashed instructions skipped in execute |
| 904system.cpu0.iew.exec_swp 0 # number of swp insts executed | 1465system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 905system.cpu0.iew.exec_nop 117682 # number of nop insts executed 906system.cpu0.iew.exec_refs 14611771 # number of memory reference insts executed 907system.cpu0.iew.exec_branches 4852307 # Number of branches executed 908system.cpu0.iew.exec_stores 5396032 # Number of stores executed 909system.cpu0.iew.exec_rate 0.543238 # Inst execution rate 910system.cpu0.iew.wb_sent 36653422 # cumulative count of insts sent to commit 911system.cpu0.iew.wb_count 34325127 # cumulative count of insts written-back 912system.cpu0.iew.wb_producers 18280728 # num instructions producing a value 913system.cpu0.iew.wb_consumers 35164479 # num instructions consuming a value | 1466system.cpu0.iew.exec_nop 118178 # number of nop insts executed 1467system.cpu0.iew.exec_refs 14774953 # number of memory reference insts executed 1468system.cpu0.iew.exec_branches 4916788 # Number of branches executed 1469system.cpu0.iew.exec_stores 5487660 # Number of stores executed 1470system.cpu0.iew.exec_rate 0.536319 # Inst execution rate 1471system.cpu0.iew.wb_sent 37140556 # cumulative count of insts sent to commit 1472system.cpu0.iew.wb_count 34854926 # cumulative count of insts written-back 1473system.cpu0.iew.wb_producers 18563816 # num instructions producing a value 1474system.cpu0.iew.wb_consumers 35689656 # num instructions consuming a value |
| 914system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1475system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 915system.cpu0.iew.wb_rate 0.506067 # insts written-back per cycle 916system.cpu0.iew.wb_fanout 0.519863 # average fanout of values written-back | 1476system.cpu0.iew.wb_rate 0.500692 # insts written-back per cycle 1477system.cpu0.iew.wb_fanout 0.520146 # average fanout of values written-back |
| 917system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1478system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 918system.cpu0.commit.commitSquashedInsts 6092264 # The number of squashed insts skipped by commit 919system.cpu0.commit.commitNonSpecStalls 638559 # The number of times commit has been forced to stall to communicate backwards 920system.cpu0.commit.branchMispredicts 231469 # The number of times a branch was mispredicted 921system.cpu0.commit.committed_per_cycle::samples 40165010 # Number of insts commited each cycle 922system.cpu0.commit.committed_per_cycle::mean 0.778528 # Number of insts commited each cycle 923system.cpu0.commit.committed_per_cycle::stdev 1.739872 # Number of insts commited each cycle | 1479system.cpu0.commit.commitSquashedInsts 6130188 # The number of squashed insts skipped by commit 1480system.cpu0.commit.commitNonSpecStalls 647788 # The number of times commit has been forced to stall to communicate backwards 1481system.cpu0.commit.branchMispredicts 232202 # The number of times a branch was mispredicted 1482system.cpu0.commit.committed_per_cycle::samples 41165199 # Number of insts commited each cycle 1483system.cpu0.commit.committed_per_cycle::mean 0.772263 # Number of insts commited each cycle 1484system.cpu0.commit.committed_per_cycle::stdev 1.733134 # Number of insts commited each cycle |
| 924system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1485system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 925system.cpu0.commit.committed_per_cycle::0 28490647 70.93% 70.93% # Number of insts commited each cycle 926system.cpu0.commit.committed_per_cycle::1 5723698 14.25% 85.18% # Number of insts commited each cycle 927system.cpu0.commit.committed_per_cycle::2 1913208 4.76% 89.95% # Number of insts commited each cycle 928system.cpu0.commit.committed_per_cycle::3 977623 2.43% 92.38% # Number of insts commited each cycle 929system.cpu0.commit.committed_per_cycle::4 784001 1.95% 94.33% # Number of insts commited each cycle 930system.cpu0.commit.committed_per_cycle::5 521196 1.30% 95.63% # Number of insts commited each cycle 931system.cpu0.commit.committed_per_cycle::6 385694 0.96% 96.59% # Number of insts commited each cycle 932system.cpu0.commit.committed_per_cycle::7 221095 0.55% 97.14% # Number of insts commited each cycle 933system.cpu0.commit.committed_per_cycle::8 1147848 2.86% 100.00% # Number of insts commited each cycle | 1486system.cpu0.commit.committed_per_cycle::0 29286812 71.14% 71.14% # Number of insts commited each cycle 1487system.cpu0.commit.committed_per_cycle::1 5810011 14.11% 85.26% # Number of insts commited each cycle 1488system.cpu0.commit.committed_per_cycle::2 1968218 4.78% 90.04% # Number of insts commited each cycle 1489system.cpu0.commit.committed_per_cycle::3 996844 2.42% 92.46% # Number of insts commited each cycle 1490system.cpu0.commit.committed_per_cycle::4 804428 1.95% 94.42% # Number of insts commited each cycle 1491system.cpu0.commit.committed_per_cycle::5 515457 1.25% 95.67% # Number of insts commited each cycle 1492system.cpu0.commit.committed_per_cycle::6 392582 0.95% 96.62% # Number of insts commited each cycle 1493system.cpu0.commit.committed_per_cycle::7 223885 0.54% 97.17% # Number of insts commited each cycle 1494system.cpu0.commit.committed_per_cycle::8 1166962 2.83% 100.00% # Number of insts commited each cycle |
| 934system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 935system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 936system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1495system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1496system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1497system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 937system.cpu0.commit.committed_per_cycle::total 40165010 # Number of insts commited each cycle 938system.cpu0.commit.committedInsts 23670535 # Number of instructions committed 939system.cpu0.commit.committedOps 31269580 # Number of ops (including micro ops) committed | 1498system.cpu0.commit.committed_per_cycle::total 41165199 # Number of insts commited each cycle 1499system.cpu0.commit.committedInsts 24069809 # Number of instructions committed 1500system.cpu0.commit.committedOps 31790359 # Number of ops (including micro ops) committed |
| 940system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 1501system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 941system.cpu0.commit.refs 11418455 # Number of memory references committed 942system.cpu0.commit.loads 6271883 # Number of loads committed 943system.cpu0.commit.membars 229601 # Number of memory barriers committed 944system.cpu0.commit.branches 4243632 # Number of branches committed | 1502system.cpu0.commit.refs 11618028 # Number of memory references committed 1503system.cpu0.commit.loads 6383416 # Number of loads committed 1504system.cpu0.commit.membars 231880 # Number of memory barriers committed 1505system.cpu0.commit.branches 4307208 # Number of branches committed |
| 945system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. | 1506system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. |
| 946system.cpu0.commit.int_insts 27627385 # Number of committed integer instructions. 947system.cpu0.commit.function_calls 489162 # Number of function calls committed. 948system.cpu0.commit.bw_lim_events 1147848 # number cycles where commit BW limit reached | 1507system.cpu0.commit.int_insts 28099612 # Number of committed integer instructions. 1508system.cpu0.commit.function_calls 498731 # Number of function calls committed. 1509system.cpu0.commit.bw_lim_events 1166962 # number cycles where commit BW limit reached |
| 949system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 1510system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 950system.cpu0.rob.rob_reads 75528065 # The number of ROB reads 951system.cpu0.rob.rob_writes 75703855 # The number of ROB writes 952system.cpu0.timesIdled 360661 # Number of times that the entire CPU went into an idle state and unscheduled itself 953system.cpu0.idleCycles 26683880 # Total number of cycles that the CPU has spent unscheduled due to idling 954system.cpu0.quiesceCycles 2138039181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 955system.cpu0.committedInsts 23589793 # Number of Instructions Simulated 956system.cpu0.committedOps 31188838 # Number of Ops (including micro ops) Simulated 957system.cpu0.committedInsts_total 23589793 # Number of Instructions Simulated 958system.cpu0.cpi 2.875277 # CPI: Cycles Per Instruction 959system.cpu0.cpi_total 2.875277 # CPI: Total CPI of All Threads 960system.cpu0.ipc 0.347793 # IPC: Instructions Per Cycle 961system.cpu0.ipc_total 0.347793 # IPC: Total IPC of All Threads 962system.cpu0.int_regfile_reads 171736211 # number of integer regfile reads 963system.cpu0.int_regfile_writes 34071636 # number of integer regfile writes 964system.cpu0.fp_regfile_reads 3249 # number of floating regfile reads 965system.cpu0.fp_regfile_writes 898 # number of floating regfile writes 966system.cpu0.misc_regfile_reads 12999243 # number of misc regfile reads 967system.cpu0.misc_regfile_writes 450984 # number of misc regfile writes 968system.cpu0.icache.replacements 392403 # number of replacements 969system.cpu0.icache.tagsinuse 511.011252 # Cycle average of tags in use 970system.cpu0.icache.total_refs 3789022 # Total number of references to valid blocks. 971system.cpu0.icache.sampled_refs 392915 # Sample count of references to valid blocks. 972system.cpu0.icache.avg_refs 9.643363 # Average number of references to valid blocks. 973system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. 974system.cpu0.icache.occ_blocks::cpu0.inst 511.011252 # Average occupied blocks per requestor 975system.cpu0.icache.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy 976system.cpu0.icache.occ_percent::total 0.998069 # Average percentage of cache occupancy 977system.cpu0.icache.ReadReq_hits::cpu0.inst 3789022 # number of ReadReq hits 978system.cpu0.icache.ReadReq_hits::total 3789022 # number of ReadReq hits 979system.cpu0.icache.demand_hits::cpu0.inst 3789022 # number of demand (read+write) hits 980system.cpu0.icache.demand_hits::total 3789022 # number of demand (read+write) hits 981system.cpu0.icache.overall_hits::cpu0.inst 3789022 # number of overall hits 982system.cpu0.icache.overall_hits::total 3789022 # number of overall hits 983system.cpu0.icache.ReadReq_misses::cpu0.inst 423106 # number of ReadReq misses 984system.cpu0.icache.ReadReq_misses::total 423106 # number of ReadReq misses 985system.cpu0.icache.demand_misses::cpu0.inst 423106 # number of demand (read+write) misses 986system.cpu0.icache.demand_misses::total 423106 # number of demand (read+write) misses 987system.cpu0.icache.overall_misses::cpu0.inst 423106 # number of overall misses 988system.cpu0.icache.overall_misses::total 423106 # number of overall misses 989system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5802286496 # number of ReadReq miss cycles 990system.cpu0.icache.ReadReq_miss_latency::total 5802286496 # number of ReadReq miss cycles 991system.cpu0.icache.demand_miss_latency::cpu0.inst 5802286496 # number of demand (read+write) miss cycles 992system.cpu0.icache.demand_miss_latency::total 5802286496 # number of demand (read+write) miss cycles 993system.cpu0.icache.overall_miss_latency::cpu0.inst 5802286496 # number of overall miss cycles 994system.cpu0.icache.overall_miss_latency::total 5802286496 # number of overall miss cycles 995system.cpu0.icache.ReadReq_accesses::cpu0.inst 4212128 # number of ReadReq accesses(hits+misses) 996system.cpu0.icache.ReadReq_accesses::total 4212128 # number of ReadReq accesses(hits+misses) 997system.cpu0.icache.demand_accesses::cpu0.inst 4212128 # number of demand (read+write) accesses 998system.cpu0.icache.demand_accesses::total 4212128 # number of demand (read+write) accesses 999system.cpu0.icache.overall_accesses::cpu0.inst 4212128 # number of overall (read+write) accesses 1000system.cpu0.icache.overall_accesses::total 4212128 # number of overall (read+write) accesses 1001system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100449 # miss rate for ReadReq accesses 1002system.cpu0.icache.ReadReq_miss_rate::total 0.100449 # miss rate for ReadReq accesses 1003system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100449 # miss rate for demand accesses 1004system.cpu0.icache.demand_miss_rate::total 0.100449 # miss rate for demand accesses 1005system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100449 # miss rate for overall accesses 1006system.cpu0.icache.overall_miss_rate::total 0.100449 # miss rate for overall accesses 1007system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13713.552859 # average ReadReq miss latency 1008system.cpu0.icache.ReadReq_avg_miss_latency::total 13713.552859 # average ReadReq miss latency 1009system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency 1010system.cpu0.icache.demand_avg_miss_latency::total 13713.552859 # average overall miss latency 1011system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency 1012system.cpu0.icache.overall_avg_miss_latency::total 13713.552859 # average overall miss latency 1013system.cpu0.icache.blocked_cycles::no_mshrs 4195 # number of cycles access was blocked | 1511system.cpu0.rob.rob_reads 77052413 # The number of ROB reads 1512system.cpu0.rob.rob_writes 76827079 # The number of ROB writes 1513system.cpu0.timesIdled 370271 # Number of times that the entire CPU went into an idle state and unscheduled itself 1514system.cpu0.idleCycles 27463996 # Total number of cycles that the CPU has spent unscheduled due to idling 1515system.cpu0.quiesceCycles 5157937915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1516system.cpu0.committedInsts 23989067 # Number of Instructions Simulated 1517system.cpu0.committedOps 31709617 # Number of Ops (including micro ops) Simulated 1518system.cpu0.committedInsts_total 23989067 # Number of Instructions Simulated 1519system.cpu0.cpi 2.901883 # CPI: Cycles Per Instruction 1520system.cpu0.cpi_total 2.901883 # CPI: Total CPI of All Threads 1521system.cpu0.ipc 0.344604 # IPC: Instructions Per Cycle 1522system.cpu0.ipc_total 0.344604 # IPC: Total IPC of All Threads 1523system.cpu0.int_regfile_reads 174143996 # number of integer regfile reads 1524system.cpu0.int_regfile_writes 34604534 # number of integer regfile writes 1525system.cpu0.fp_regfile_reads 3264 # number of floating regfile reads 1526system.cpu0.fp_regfile_writes 896 # number of floating regfile writes 1527system.cpu0.misc_regfile_reads 13203658 # number of misc regfile reads 1528system.cpu0.misc_regfile_writes 457594 # number of misc regfile writes 1529system.cpu0.icache.replacements 399659 # number of replacements 1530system.cpu0.icache.tagsinuse 511.575445 # Cycle average of tags in use 1531system.cpu0.icache.total_refs 3842942 # Total number of references to valid blocks. 1532system.cpu0.icache.sampled_refs 400171 # Sample count of references to valid blocks. 1533system.cpu0.icache.avg_refs 9.603250 # Average number of references to valid blocks. 1534system.cpu0.icache.warmup_cycle 6980726000 # Cycle when the warmup percentage was hit. 1535system.cpu0.icache.occ_blocks::cpu0.inst 511.575445 # Average occupied blocks per requestor 1536system.cpu0.icache.occ_percent::cpu0.inst 0.999171 # Average percentage of cache occupancy 1537system.cpu0.icache.occ_percent::total 0.999171 # Average percentage of cache occupancy 1538system.cpu0.icache.ReadReq_hits::cpu0.inst 3842942 # number of ReadReq hits 1539system.cpu0.icache.ReadReq_hits::total 3842942 # number of ReadReq hits 1540system.cpu0.icache.demand_hits::cpu0.inst 3842942 # number of demand (read+write) hits 1541system.cpu0.icache.demand_hits::total 3842942 # number of demand (read+write) hits 1542system.cpu0.icache.overall_hits::cpu0.inst 3842942 # number of overall hits 1543system.cpu0.icache.overall_hits::total 3842942 # number of overall hits 1544system.cpu0.icache.ReadReq_misses::cpu0.inst 431911 # number of ReadReq misses 1545system.cpu0.icache.ReadReq_misses::total 431911 # number of ReadReq misses 1546system.cpu0.icache.demand_misses::cpu0.inst 431911 # number of demand (read+write) misses 1547system.cpu0.icache.demand_misses::total 431911 # number of demand (read+write) misses 1548system.cpu0.icache.overall_misses::cpu0.inst 431911 # number of overall misses 1549system.cpu0.icache.overall_misses::total 431911 # number of overall misses 1550system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969636493 # number of ReadReq miss cycles 1551system.cpu0.icache.ReadReq_miss_latency::total 5969636493 # number of ReadReq miss cycles 1552system.cpu0.icache.demand_miss_latency::cpu0.inst 5969636493 # number of demand (read+write) miss cycles 1553system.cpu0.icache.demand_miss_latency::total 5969636493 # number of demand (read+write) miss cycles 1554system.cpu0.icache.overall_miss_latency::cpu0.inst 5969636493 # number of overall miss cycles 1555system.cpu0.icache.overall_miss_latency::total 5969636493 # number of overall miss cycles 1556system.cpu0.icache.ReadReq_accesses::cpu0.inst 4274853 # number of ReadReq accesses(hits+misses) 1557system.cpu0.icache.ReadReq_accesses::total 4274853 # number of ReadReq accesses(hits+misses) 1558system.cpu0.icache.demand_accesses::cpu0.inst 4274853 # number of demand (read+write) accesses 1559system.cpu0.icache.demand_accesses::total 4274853 # number of demand (read+write) accesses 1560system.cpu0.icache.overall_accesses::cpu0.inst 4274853 # number of overall (read+write) accesses 1561system.cpu0.icache.overall_accesses::total 4274853 # number of overall (read+write) accesses 1562system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.101035 # miss rate for ReadReq accesses 1563system.cpu0.icache.ReadReq_miss_rate::total 0.101035 # miss rate for ReadReq accesses 1564system.cpu0.icache.demand_miss_rate::cpu0.inst 0.101035 # miss rate for demand accesses 1565system.cpu0.icache.demand_miss_rate::total 0.101035 # miss rate for demand accesses 1566system.cpu0.icache.overall_miss_rate::cpu0.inst 0.101035 # miss rate for overall accesses 1567system.cpu0.icache.overall_miss_rate::total 0.101035 # miss rate for overall accesses 1568system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.450468 # average ReadReq miss latency 1569system.cpu0.icache.ReadReq_avg_miss_latency::total 13821.450468 # average ReadReq miss latency 1570system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency 1571system.cpu0.icache.demand_avg_miss_latency::total 13821.450468 # average overall miss latency 1572system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency 1573system.cpu0.icache.overall_avg_miss_latency::total 13821.450468 # average overall miss latency 1574system.cpu0.icache.blocked_cycles::no_mshrs 3644 # number of cycles access was blocked |
| 1014system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1575system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1015system.cpu0.icache.blocked::no_mshrs 183 # number of cycles access was blocked | 1576system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked |
| 1016system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 1577system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1017system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.923497 # average number of cycles each access was blocked | 1578system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.942529 # average number of cycles each access was blocked |
| 1018system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1019system.cpu0.icache.fast_writes 0 # number of fast writes performed 1020system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1579system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1580system.cpu0.icache.fast_writes 0 # number of fast writes performed 1581system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1021system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30174 # number of ReadReq MSHR hits 1022system.cpu0.icache.ReadReq_mshr_hits::total 30174 # number of ReadReq MSHR hits 1023system.cpu0.icache.demand_mshr_hits::cpu0.inst 30174 # number of demand (read+write) MSHR hits 1024system.cpu0.icache.demand_mshr_hits::total 30174 # number of demand (read+write) MSHR hits 1025system.cpu0.icache.overall_mshr_hits::cpu0.inst 30174 # number of overall MSHR hits 1026system.cpu0.icache.overall_mshr_hits::total 30174 # number of overall MSHR hits 1027system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392932 # number of ReadReq MSHR misses 1028system.cpu0.icache.ReadReq_mshr_misses::total 392932 # number of ReadReq MSHR misses 1029system.cpu0.icache.demand_mshr_misses::cpu0.inst 392932 # number of demand (read+write) MSHR misses 1030system.cpu0.icache.demand_mshr_misses::total 392932 # number of demand (read+write) MSHR misses 1031system.cpu0.icache.overall_mshr_misses::cpu0.inst 392932 # number of overall MSHR misses 1032system.cpu0.icache.overall_mshr_misses::total 392932 # number of overall MSHR misses 1033system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4748967496 # number of ReadReq MSHR miss cycles 1034system.cpu0.icache.ReadReq_mshr_miss_latency::total 4748967496 # number of ReadReq MSHR miss cycles 1035system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4748967496 # number of demand (read+write) MSHR miss cycles 1036system.cpu0.icache.demand_mshr_miss_latency::total 4748967496 # number of demand (read+write) MSHR miss cycles 1037system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4748967496 # number of overall MSHR miss cycles 1038system.cpu0.icache.overall_mshr_miss_latency::total 4748967496 # number of overall MSHR miss cycles 1039system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles 1040system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles 1041system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles 1042system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles 1043system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for ReadReq accesses 1044system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093286 # mshr miss rate for ReadReq accesses 1045system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for demand accesses 1046system.cpu0.icache.demand_mshr_miss_rate::total 0.093286 # mshr miss rate for demand accesses 1047system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for overall accesses 1048system.cpu0.icache.overall_mshr_miss_rate::total 0.093286 # mshr miss rate for overall accesses 1049system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average ReadReq mshr miss latency 1050system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12085.977971 # average ReadReq mshr miss latency 1051system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency 1052system.cpu0.icache.demand_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency 1053system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency 1054system.cpu0.icache.overall_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency | 1582system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31718 # number of ReadReq MSHR hits 1583system.cpu0.icache.ReadReq_mshr_hits::total 31718 # number of ReadReq MSHR hits 1584system.cpu0.icache.demand_mshr_hits::cpu0.inst 31718 # number of demand (read+write) MSHR hits 1585system.cpu0.icache.demand_mshr_hits::total 31718 # number of demand (read+write) MSHR hits 1586system.cpu0.icache.overall_mshr_hits::cpu0.inst 31718 # number of overall MSHR hits 1587system.cpu0.icache.overall_mshr_hits::total 31718 # number of overall MSHR hits 1588system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400193 # number of ReadReq MSHR misses 1589system.cpu0.icache.ReadReq_mshr_misses::total 400193 # number of ReadReq MSHR misses 1590system.cpu0.icache.demand_mshr_misses::cpu0.inst 400193 # number of demand (read+write) MSHR misses 1591system.cpu0.icache.demand_mshr_misses::total 400193 # number of demand (read+write) MSHR misses 1592system.cpu0.icache.overall_mshr_misses::cpu0.inst 400193 # number of overall MSHR misses 1593system.cpu0.icache.overall_mshr_misses::total 400193 # number of overall MSHR misses 1594system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4864756575 # number of ReadReq MSHR miss cycles 1595system.cpu0.icache.ReadReq_mshr_miss_latency::total 4864756575 # number of ReadReq MSHR miss cycles 1596system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4864756575 # number of demand (read+write) MSHR miss cycles 1597system.cpu0.icache.demand_mshr_miss_latency::total 4864756575 # number of demand (read+write) MSHR miss cycles 1598system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4864756575 # number of overall MSHR miss cycles 1599system.cpu0.icache.overall_mshr_miss_latency::total 4864756575 # number of overall MSHR miss cycles 1600system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9682500 # number of ReadReq MSHR uncacheable cycles 1601system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9682500 # number of ReadReq MSHR uncacheable cycles 1602system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9682500 # number of overall MSHR uncacheable cycles 1603system.cpu0.icache.overall_mshr_uncacheable_latency::total 9682500 # number of overall MSHR uncacheable cycles 1604system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for ReadReq accesses 1605system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093616 # mshr miss rate for ReadReq accesses 1606system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for demand accesses 1607system.cpu0.icache.demand_mshr_miss_rate::total 0.093616 # mshr miss rate for demand accesses 1608system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for overall accesses 1609system.cpu0.icache.overall_mshr_miss_rate::total 0.093616 # mshr miss rate for overall accesses 1610system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average ReadReq mshr miss latency 1611system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12156.026155 # average ReadReq mshr miss latency 1612system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency 1613system.cpu0.icache.demand_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency 1614system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency 1615system.cpu0.icache.overall_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency |
| 1055system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1056system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1057system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1058system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1059system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1616system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1617system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1618system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1619system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1620system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1060system.cpu0.dcache.replacements 275974 # number of replacements 1061system.cpu0.dcache.tagsinuse 462.017037 # Cycle average of tags in use 1062system.cpu0.dcache.total_refs 9251393 # Total number of references to valid blocks. 1063system.cpu0.dcache.sampled_refs 276486 # Sample count of references to valid blocks. 1064system.cpu0.dcache.avg_refs 33.460620 # Average number of references to valid blocks. 1065system.cpu0.dcache.warmup_cycle 43505000 # Cycle when the warmup percentage was hit. 1066system.cpu0.dcache.occ_blocks::cpu0.data 462.017037 # Average occupied blocks per requestor 1067system.cpu0.dcache.occ_percent::cpu0.data 0.902377 # Average percentage of cache occupancy 1068system.cpu0.dcache.occ_percent::total 0.902377 # Average percentage of cache occupancy 1069system.cpu0.dcache.ReadReq_hits::cpu0.data 5774321 # number of ReadReq hits 1070system.cpu0.dcache.ReadReq_hits::total 5774321 # number of ReadReq hits 1071system.cpu0.dcache.WriteReq_hits::cpu0.data 3157289 # number of WriteReq hits 1072system.cpu0.dcache.WriteReq_hits::total 3157289 # number of WriteReq hits 1073system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139126 # number of LoadLockedReq hits 1074system.cpu0.dcache.LoadLockedReq_hits::total 139126 # number of LoadLockedReq hits 1075system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137035 # number of StoreCondReq hits 1076system.cpu0.dcache.StoreCondReq_hits::total 137035 # number of StoreCondReq hits 1077system.cpu0.dcache.demand_hits::cpu0.data 8931610 # number of demand (read+write) hits 1078system.cpu0.dcache.demand_hits::total 8931610 # number of demand (read+write) hits 1079system.cpu0.dcache.overall_hits::cpu0.data 8931610 # number of overall hits 1080system.cpu0.dcache.overall_hits::total 8931610 # number of overall hits 1081system.cpu0.dcache.ReadReq_misses::cpu0.data 392659 # number of ReadReq misses 1082system.cpu0.dcache.ReadReq_misses::total 392659 # number of ReadReq misses 1083system.cpu0.dcache.WriteReq_misses::cpu0.data 1582356 # number of WriteReq misses 1084system.cpu0.dcache.WriteReq_misses::total 1582356 # number of WriteReq misses 1085system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8783 # number of LoadLockedReq misses 1086system.cpu0.dcache.LoadLockedReq_misses::total 8783 # number of LoadLockedReq misses 1087system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7478 # number of StoreCondReq misses 1088system.cpu0.dcache.StoreCondReq_misses::total 7478 # number of StoreCondReq misses 1089system.cpu0.dcache.demand_misses::cpu0.data 1975015 # number of demand (read+write) misses 1090system.cpu0.dcache.demand_misses::total 1975015 # number of demand (read+write) misses 1091system.cpu0.dcache.overall_misses::cpu0.data 1975015 # number of overall misses 1092system.cpu0.dcache.overall_misses::total 1975015 # number of overall misses 1093system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5465751000 # number of ReadReq miss cycles 1094system.cpu0.dcache.ReadReq_miss_latency::total 5465751000 # number of ReadReq miss cycles 1095system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60871178363 # number of WriteReq miss cycles 1096system.cpu0.dcache.WriteReq_miss_latency::total 60871178363 # number of WriteReq miss cycles 1097system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88481000 # number of LoadLockedReq miss cycles 1098system.cpu0.dcache.LoadLockedReq_miss_latency::total 88481000 # number of LoadLockedReq miss cycles 1099system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46675000 # number of StoreCondReq miss cycles 1100system.cpu0.dcache.StoreCondReq_miss_latency::total 46675000 # number of StoreCondReq miss cycles 1101system.cpu0.dcache.demand_miss_latency::cpu0.data 66336929363 # number of demand (read+write) miss cycles 1102system.cpu0.dcache.demand_miss_latency::total 66336929363 # number of demand (read+write) miss cycles 1103system.cpu0.dcache.overall_miss_latency::cpu0.data 66336929363 # number of overall miss cycles 1104system.cpu0.dcache.overall_miss_latency::total 66336929363 # number of overall miss cycles 1105system.cpu0.dcache.ReadReq_accesses::cpu0.data 6166980 # number of ReadReq accesses(hits+misses) 1106system.cpu0.dcache.ReadReq_accesses::total 6166980 # number of ReadReq accesses(hits+misses) 1107system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739645 # number of WriteReq accesses(hits+misses) 1108system.cpu0.dcache.WriteReq_accesses::total 4739645 # number of WriteReq accesses(hits+misses) 1109system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147909 # number of LoadLockedReq accesses(hits+misses) 1110system.cpu0.dcache.LoadLockedReq_accesses::total 147909 # number of LoadLockedReq accesses(hits+misses) 1111system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144513 # number of StoreCondReq accesses(hits+misses) 1112system.cpu0.dcache.StoreCondReq_accesses::total 144513 # number of StoreCondReq accesses(hits+misses) 1113system.cpu0.dcache.demand_accesses::cpu0.data 10906625 # number of demand (read+write) accesses 1114system.cpu0.dcache.demand_accesses::total 10906625 # number of demand (read+write) accesses 1115system.cpu0.dcache.overall_accesses::cpu0.data 10906625 # number of overall (read+write) accesses 1116system.cpu0.dcache.overall_accesses::total 10906625 # number of overall (read+write) accesses 1117system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063671 # miss rate for ReadReq accesses 1118system.cpu0.dcache.ReadReq_miss_rate::total 0.063671 # miss rate for ReadReq accesses 1119system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333855 # miss rate for WriteReq accesses 1120system.cpu0.dcache.WriteReq_miss_rate::total 0.333855 # miss rate for WriteReq accesses 1121system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059381 # miss rate for LoadLockedReq accesses 1122system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059381 # miss rate for LoadLockedReq accesses 1123system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051746 # miss rate for StoreCondReq accesses 1124system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051746 # miss rate for StoreCondReq accesses 1125system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181084 # miss rate for demand accesses 1126system.cpu0.dcache.demand_miss_rate::total 0.181084 # miss rate for demand accesses 1127system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181084 # miss rate for overall accesses 1128system.cpu0.dcache.overall_miss_rate::total 0.181084 # miss rate for overall accesses 1129system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13919.841389 # average ReadReq miss latency 1130system.cpu0.dcache.ReadReq_avg_miss_latency::total 13919.841389 # average ReadReq miss latency 1131system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.700067 # average WriteReq miss latency 1132system.cpu0.dcache.WriteReq_avg_miss_latency::total 38468.700067 # average WriteReq miss latency 1133system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10074.120460 # average LoadLockedReq miss latency 1134system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10074.120460 # average LoadLockedReq miss latency 1135system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6241.642150 # average StoreCondReq miss latency 1136system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6241.642150 # average StoreCondReq miss latency 1137system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency 1138system.cpu0.dcache.demand_avg_miss_latency::total 33588.063566 # average overall miss latency 1139system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency 1140system.cpu0.dcache.overall_avg_miss_latency::total 33588.063566 # average overall miss latency 1141system.cpu0.dcache.blocked_cycles::no_mshrs 8548 # number of cycles access was blocked 1142system.cpu0.dcache.blocked_cycles::no_targets 2163 # number of cycles access was blocked 1143system.cpu0.dcache.blocked::no_mshrs 649 # number of cycles access was blocked 1144system.cpu0.dcache.blocked::no_targets 77 # number of cycles access was blocked 1145system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.171032 # average number of cycles each access was blocked 1146system.cpu0.dcache.avg_blocked_cycles::no_targets 28.090909 # average number of cycles each access was blocked | 1621system.cpu0.dcache.replacements 275313 # number of replacements 1622system.cpu0.dcache.tagsinuse 479.702966 # Cycle average of tags in use 1623system.cpu0.dcache.total_refs 9426114 # Total number of references to valid blocks. 1624system.cpu0.dcache.sampled_refs 275825 # Sample count of references to valid blocks. 1625system.cpu0.dcache.avg_refs 34.174255 # Average number of references to valid blocks. 1626system.cpu0.dcache.warmup_cycle 49336000 # Cycle when the warmup percentage was hit. 1627system.cpu0.dcache.occ_blocks::cpu0.data 479.702966 # Average occupied blocks per requestor 1628system.cpu0.dcache.occ_percent::cpu0.data 0.936920 # Average percentage of cache occupancy 1629system.cpu0.dcache.occ_percent::total 0.936920 # Average percentage of cache occupancy 1630system.cpu0.dcache.ReadReq_hits::cpu0.data 5876643 # number of ReadReq hits 1631system.cpu0.dcache.ReadReq_hits::total 5876643 # number of ReadReq hits 1632system.cpu0.dcache.WriteReq_hits::cpu0.data 3228072 # number of WriteReq hits 1633system.cpu0.dcache.WriteReq_hits::total 3228072 # number of WriteReq hits 1634system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139641 # number of LoadLockedReq hits 1635system.cpu0.dcache.LoadLockedReq_hits::total 139641 # number of LoadLockedReq hits 1636system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137200 # number of StoreCondReq hits 1637system.cpu0.dcache.StoreCondReq_hits::total 137200 # number of StoreCondReq hits 1638system.cpu0.dcache.demand_hits::cpu0.data 9104715 # number of demand (read+write) hits 1639system.cpu0.dcache.demand_hits::total 9104715 # number of demand (read+write) hits 1640system.cpu0.dcache.overall_hits::cpu0.data 9104715 # number of overall hits 1641system.cpu0.dcache.overall_hits::total 9104715 # number of overall hits 1642system.cpu0.dcache.ReadReq_misses::cpu0.data 392586 # number of ReadReq misses 1643system.cpu0.dcache.ReadReq_misses::total 392586 # number of ReadReq misses 1644system.cpu0.dcache.WriteReq_misses::cpu0.data 1585207 # number of WriteReq misses 1645system.cpu0.dcache.WriteReq_misses::total 1585207 # number of WriteReq misses 1646system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8832 # number of LoadLockedReq misses 1647system.cpu0.dcache.LoadLockedReq_misses::total 8832 # number of LoadLockedReq misses 1648system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7754 # number of StoreCondReq misses 1649system.cpu0.dcache.StoreCondReq_misses::total 7754 # number of StoreCondReq misses 1650system.cpu0.dcache.demand_misses::cpu0.data 1977793 # number of demand (read+write) misses 1651system.cpu0.dcache.demand_misses::total 1977793 # number of demand (read+write) misses 1652system.cpu0.dcache.overall_misses::cpu0.data 1977793 # number of overall misses 1653system.cpu0.dcache.overall_misses::total 1977793 # number of overall misses 1654system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5514730000 # number of ReadReq miss cycles 1655system.cpu0.dcache.ReadReq_miss_latency::total 5514730000 # number of ReadReq miss cycles 1656system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76877974883 # number of WriteReq miss cycles 1657system.cpu0.dcache.WriteReq_miss_latency::total 76877974883 # number of WriteReq miss cycles 1658system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 89351500 # number of LoadLockedReq miss cycles 1659system.cpu0.dcache.LoadLockedReq_miss_latency::total 89351500 # number of LoadLockedReq miss cycles 1660system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49685500 # number of StoreCondReq miss cycles 1661system.cpu0.dcache.StoreCondReq_miss_latency::total 49685500 # number of StoreCondReq miss cycles 1662system.cpu0.dcache.demand_miss_latency::cpu0.data 82392704883 # number of demand (read+write) miss cycles 1663system.cpu0.dcache.demand_miss_latency::total 82392704883 # number of demand (read+write) miss cycles 1664system.cpu0.dcache.overall_miss_latency::cpu0.data 82392704883 # number of overall miss cycles 1665system.cpu0.dcache.overall_miss_latency::total 82392704883 # number of overall miss cycles 1666system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269229 # number of ReadReq accesses(hits+misses) 1667system.cpu0.dcache.ReadReq_accesses::total 6269229 # number of ReadReq accesses(hits+misses) 1668system.cpu0.dcache.WriteReq_accesses::cpu0.data 4813279 # number of WriteReq accesses(hits+misses) 1669system.cpu0.dcache.WriteReq_accesses::total 4813279 # number of WriteReq accesses(hits+misses) 1670system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148473 # number of LoadLockedReq accesses(hits+misses) 1671system.cpu0.dcache.LoadLockedReq_accesses::total 148473 # number of LoadLockedReq accesses(hits+misses) 1672system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144954 # number of StoreCondReq accesses(hits+misses) 1673system.cpu0.dcache.StoreCondReq_accesses::total 144954 # number of StoreCondReq accesses(hits+misses) 1674system.cpu0.dcache.demand_accesses::cpu0.data 11082508 # number of demand (read+write) accesses 1675system.cpu0.dcache.demand_accesses::total 11082508 # number of demand (read+write) accesses 1676system.cpu0.dcache.overall_accesses::cpu0.data 11082508 # number of overall (read+write) accesses 1677system.cpu0.dcache.overall_accesses::total 11082508 # number of overall (read+write) accesses 1678system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062621 # miss rate for ReadReq accesses 1679system.cpu0.dcache.ReadReq_miss_rate::total 0.062621 # miss rate for ReadReq accesses 1680system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329340 # miss rate for WriteReq accesses 1681system.cpu0.dcache.WriteReq_miss_rate::total 0.329340 # miss rate for WriteReq accesses 1682system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059486 # miss rate for LoadLockedReq accesses 1683system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059486 # miss rate for LoadLockedReq accesses 1684system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053493 # miss rate for StoreCondReq accesses 1685system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053493 # miss rate for StoreCondReq accesses 1686system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178461 # miss rate for demand accesses 1687system.cpu0.dcache.demand_miss_rate::total 0.178461 # miss rate for demand accesses 1688system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178461 # miss rate for overall accesses 1689system.cpu0.dcache.overall_miss_rate::total 0.178461 # miss rate for overall accesses 1690system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14047.189660 # average ReadReq miss latency 1691system.cpu0.dcache.ReadReq_avg_miss_latency::total 14047.189660 # average ReadReq miss latency 1692system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48497.120492 # average WriteReq miss latency 1693system.cpu0.dcache.WriteReq_avg_miss_latency::total 48497.120492 # average WriteReq miss latency 1694system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10116.791214 # average LoadLockedReq miss latency 1695system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10116.791214 # average LoadLockedReq miss latency 1696system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6407.725045 # average StoreCondReq miss latency 1697system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6407.725045 # average StoreCondReq miss latency 1698system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency 1699system.cpu0.dcache.demand_avg_miss_latency::total 41658.912173 # average overall miss latency 1700system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency 1701system.cpu0.dcache.overall_avg_miss_latency::total 41658.912173 # average overall miss latency 1702system.cpu0.dcache.blocked_cycles::no_mshrs 10507 # number of cycles access was blocked 1703system.cpu0.dcache.blocked_cycles::no_targets 10018 # number of cycles access was blocked 1704system.cpu0.dcache.blocked::no_mshrs 605 # number of cycles access was blocked 1705system.cpu0.dcache.blocked::no_targets 134 # number of cycles access was blocked 1706system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.366942 # average number of cycles each access was blocked 1707system.cpu0.dcache.avg_blocked_cycles::no_targets 74.761194 # average number of cycles each access was blocked |
| 1147system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1148system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1708system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1709system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1149system.cpu0.dcache.writebacks::writebacks 256417 # number of writebacks 1150system.cpu0.dcache.writebacks::total 256417 # number of writebacks 1151system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203981 # number of ReadReq MSHR hits 1152system.cpu0.dcache.ReadReq_mshr_hits::total 203981 # number of ReadReq MSHR hits 1153system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452148 # number of WriteReq MSHR hits 1154system.cpu0.dcache.WriteReq_mshr_hits::total 1452148 # number of WriteReq MSHR hits 1155system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 473 # number of LoadLockedReq MSHR hits 1156system.cpu0.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits 1157system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656129 # number of demand (read+write) MSHR hits 1158system.cpu0.dcache.demand_mshr_hits::total 1656129 # number of demand (read+write) MSHR hits 1159system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656129 # number of overall MSHR hits 1160system.cpu0.dcache.overall_mshr_hits::total 1656129 # number of overall MSHR hits 1161system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188678 # number of ReadReq MSHR misses 1162system.cpu0.dcache.ReadReq_mshr_misses::total 188678 # number of ReadReq MSHR misses 1163system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130208 # number of WriteReq MSHR misses 1164system.cpu0.dcache.WriteReq_mshr_misses::total 130208 # number of WriteReq MSHR misses 1165system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses 1166system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses 1167system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7477 # number of StoreCondReq MSHR misses 1168system.cpu0.dcache.StoreCondReq_mshr_misses::total 7477 # number of StoreCondReq MSHR misses 1169system.cpu0.dcache.demand_mshr_misses::cpu0.data 318886 # number of demand (read+write) MSHR misses 1170system.cpu0.dcache.demand_mshr_misses::total 318886 # number of demand (read+write) MSHR misses 1171system.cpu0.dcache.overall_mshr_misses::cpu0.data 318886 # number of overall MSHR misses 1172system.cpu0.dcache.overall_mshr_misses::total 318886 # number of overall MSHR misses 1173system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371660000 # number of ReadReq MSHR miss cycles 1174system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371660000 # number of ReadReq MSHR miss cycles 1175system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4050141991 # number of WriteReq MSHR miss cycles 1176system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4050141991 # number of WriteReq MSHR miss cycles 1177system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66675500 # number of LoadLockedReq MSHR miss cycles 1178system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66675500 # number of LoadLockedReq MSHR miss cycles 1179system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31721000 # number of StoreCondReq MSHR miss cycles 1180system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31721000 # number of StoreCondReq MSHR miss cycles 1181system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6421801991 # number of demand (read+write) MSHR miss cycles 1182system.cpu0.dcache.demand_mshr_miss_latency::total 6421801991 # number of demand (read+write) MSHR miss cycles 1183system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6421801991 # number of overall MSHR miss cycles 1184system.cpu0.dcache.overall_mshr_miss_latency::total 6421801991 # number of overall MSHR miss cycles 1185system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513534500 # number of ReadReq MSHR uncacheable cycles 1186system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513534500 # number of ReadReq MSHR uncacheable cycles 1187system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180320378 # number of WriteReq MSHR uncacheable cycles 1188system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180320378 # number of WriteReq MSHR uncacheable cycles 1189system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693854878 # number of overall MSHR uncacheable cycles 1190system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693854878 # number of overall MSHR uncacheable cycles 1191system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030595 # mshr miss rate for ReadReq accesses 1192system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030595 # mshr miss rate for ReadReq accesses 1193system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027472 # mshr miss rate for WriteReq accesses 1194system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027472 # mshr miss rate for WriteReq accesses 1195system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056183 # mshr miss rate for LoadLockedReq accesses 1196system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056183 # mshr miss rate for LoadLockedReq accesses 1197system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051739 # mshr miss rate for StoreCondReq accesses 1198system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051739 # mshr miss rate for StoreCondReq accesses 1199system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for demand accesses 1200system.cpu0.dcache.demand_mshr_miss_rate::total 0.029238 # mshr miss rate for demand accesses 1201system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for overall accesses 1202system.cpu0.dcache.overall_mshr_miss_rate::total 0.029238 # mshr miss rate for overall accesses 1203system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12569.880961 # average ReadReq mshr miss latency 1204system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12569.880961 # average ReadReq mshr miss latency 1205system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31105.170120 # average WriteReq mshr miss latency 1206system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31105.170120 # average WriteReq mshr miss latency 1207system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8023.525872 # average LoadLockedReq mshr miss latency 1208system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8023.525872 # average LoadLockedReq mshr miss latency 1209system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4242.476929 # average StoreCondReq mshr miss latency 1210system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4242.476929 # average StoreCondReq mshr miss latency 1211system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency 1212system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency 1213system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency 1214system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency | 1710system.cpu0.dcache.writebacks::writebacks 255296 # number of writebacks 1711system.cpu0.dcache.writebacks::total 255296 # number of writebacks 1712system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203565 # number of ReadReq MSHR hits 1713system.cpu0.dcache.ReadReq_mshr_hits::total 203565 # number of ReadReq MSHR hits 1714system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454109 # number of WriteReq MSHR hits 1715system.cpu0.dcache.WriteReq_mshr_hits::total 1454109 # number of WriteReq MSHR hits 1716system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 475 # number of LoadLockedReq MSHR hits 1717system.cpu0.dcache.LoadLockedReq_mshr_hits::total 475 # number of LoadLockedReq MSHR hits 1718system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657674 # number of demand (read+write) MSHR hits 1719system.cpu0.dcache.demand_mshr_hits::total 1657674 # number of demand (read+write) MSHR hits 1720system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657674 # number of overall MSHR hits 1721system.cpu0.dcache.overall_mshr_hits::total 1657674 # number of overall MSHR hits 1722system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189021 # number of ReadReq MSHR misses 1723system.cpu0.dcache.ReadReq_mshr_misses::total 189021 # number of ReadReq MSHR misses 1724system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131098 # number of WriteReq MSHR misses 1725system.cpu0.dcache.WriteReq_mshr_misses::total 131098 # number of WriteReq MSHR misses 1726system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8357 # number of LoadLockedReq MSHR misses 1727system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8357 # number of LoadLockedReq MSHR misses 1728system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7751 # number of StoreCondReq MSHR misses 1729system.cpu0.dcache.StoreCondReq_mshr_misses::total 7751 # number of StoreCondReq MSHR misses 1730system.cpu0.dcache.demand_mshr_misses::cpu0.data 320119 # number of demand (read+write) MSHR misses 1731system.cpu0.dcache.demand_mshr_misses::total 320119 # number of demand (read+write) MSHR misses 1732system.cpu0.dcache.overall_mshr_misses::cpu0.data 320119 # number of overall MSHR misses 1733system.cpu0.dcache.overall_mshr_misses::total 320119 # number of overall MSHR misses 1734system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2392342380 # number of ReadReq MSHR miss cycles 1735system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2392342380 # number of ReadReq MSHR miss cycles 1736system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5118910660 # number of WriteReq MSHR miss cycles 1737system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5118910660 # number of WriteReq MSHR miss cycles 1738system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67659513 # number of LoadLockedReq MSHR miss cycles 1739system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67659513 # number of LoadLockedReq MSHR miss cycles 1740system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34183001 # number of StoreCondReq MSHR miss cycles 1741system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34183001 # number of StoreCondReq MSHR miss cycles 1742system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7511253040 # number of demand (read+write) MSHR miss cycles 1743system.cpu0.dcache.demand_mshr_miss_latency::total 7511253040 # number of demand (read+write) MSHR miss cycles 1744system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7511253040 # number of overall MSHR miss cycles 1745system.cpu0.dcache.overall_mshr_miss_latency::total 7511253040 # number of overall MSHR miss cycles 1746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13429863028 # number of ReadReq MSHR uncacheable cycles 1747system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13429863028 # number of ReadReq MSHR uncacheable cycles 1748system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251424879 # number of WriteReq MSHR uncacheable cycles 1749system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251424879 # number of WriteReq MSHR uncacheable cycles 1750system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14681287907 # number of overall MSHR uncacheable cycles 1751system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14681287907 # number of overall MSHR uncacheable cycles 1752system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030151 # mshr miss rate for ReadReq accesses 1753system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030151 # mshr miss rate for ReadReq accesses 1754system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027237 # mshr miss rate for WriteReq accesses 1755system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027237 # mshr miss rate for WriteReq accesses 1756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056286 # mshr miss rate for LoadLockedReq accesses 1757system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056286 # mshr miss rate for LoadLockedReq accesses 1758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053472 # mshr miss rate for StoreCondReq accesses 1759system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053472 # mshr miss rate for StoreCondReq accesses 1760system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for demand accesses 1761system.cpu0.dcache.demand_mshr_miss_rate::total 0.028885 # mshr miss rate for demand accesses 1762system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for overall accesses 1763system.cpu0.dcache.overall_mshr_miss_rate::total 0.028885 # mshr miss rate for overall accesses 1764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12656.489914 # average ReadReq mshr miss latency 1765system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12656.489914 # average ReadReq mshr miss latency 1766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39046.443577 # average WriteReq mshr miss latency 1767system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39046.443577 # average WriteReq mshr miss latency 1768system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8096.148498 # average LoadLockedReq mshr miss latency 1769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8096.148498 # average LoadLockedReq mshr miss latency 1770system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4410.140756 # average StoreCondReq mshr miss latency 1771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4410.140756 # average StoreCondReq mshr miss latency 1772system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency 1773system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency 1774system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency 1775system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency |
| 1215system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1216system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1217system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1218system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1219system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1220system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1221system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1777system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1779system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1782system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1222system.cpu1.branchPred.lookups 9076266 # Number of BP lookups 1223system.cpu1.branchPred.condPredicted 7463483 # Number of conditional branches predicted 1224system.cpu1.branchPred.condIncorrect 407973 # Number of conditional branches incorrect 1225system.cpu1.branchPred.BTBLookups 6084116 # Number of BTB lookups 1226system.cpu1.branchPred.BTBHits 5247879 # Number of BTB hits | 1783system.cpu1.branchPred.lookups 9253585 # Number of BP lookups 1784system.cpu1.branchPred.condPredicted 7592303 # Number of conditional branches predicted 1785system.cpu1.branchPred.condIncorrect 416171 # Number of conditional branches incorrect 1786system.cpu1.branchPred.BTBLookups 6192388 # Number of BTB lookups 1787system.cpu1.branchPred.BTBHits 5325484 # Number of BTB hits |
| 1227system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1788system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1228system.cpu1.branchPred.BTBHitPct 86.255407 # BTB Hit Percentage 1229system.cpu1.branchPred.usedRAS 773475 # Number of times the RAS was used to get a target. 1230system.cpu1.branchPred.RASInCorrect 42302 # Number of incorrect RAS predictions. | 1789system.cpu1.branchPred.BTBHitPct 86.000490 # BTB Hit Percentage 1790system.cpu1.branchPred.usedRAS 798470 # Number of times the RAS was used to get a target. 1791system.cpu1.branchPred.RASInCorrect 43798 # Number of incorrect RAS predictions. |
| 1231system.cpu1.dtb.inst_hits 0 # ITB inst hits 1232system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1792system.cpu1.dtb.inst_hits 0 # ITB inst hits 1793system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1233system.cpu1.dtb.read_hits 42903620 # DTB read hits 1234system.cpu1.dtb.read_misses 37068 # DTB read misses 1235system.cpu1.dtb.write_hits 6823215 # DTB write hits 1236system.cpu1.dtb.write_misses 10679 # DTB write misses | 1794system.cpu1.dtb.read_hits 43179554 # DTB read hits 1795system.cpu1.dtb.read_misses 37431 # DTB read misses 1796system.cpu1.dtb.write_hits 6972554 # DTB write hits 1797system.cpu1.dtb.write_misses 10848 # DTB write misses |
| 1237system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1238system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1239system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1240system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1798system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1799system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1800system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1801system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1241system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB 1242system.cpu1.dtb.align_faults 2777 # Number of TLB faults due to alignment restrictions 1243system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch | 1802system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB 1803system.cpu1.dtb.align_faults 2926 # Number of TLB faults due to alignment restrictions 1804system.cpu1.dtb.prefetch_faults 258 # Number of TLB faults due to prefetch |
| 1244system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1805system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1245system.cpu1.dtb.perms_faults 663 # Number of TLB faults due to permissions restrictions 1246system.cpu1.dtb.read_accesses 42940688 # DTB read accesses 1247system.cpu1.dtb.write_accesses 6833894 # DTB write accesses | 1806system.cpu1.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions 1807system.cpu1.dtb.read_accesses 43216985 # DTB read accesses 1808system.cpu1.dtb.write_accesses 6983402 # DTB write accesses |
| 1248system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1809system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1249system.cpu1.dtb.hits 49726835 # DTB hits 1250system.cpu1.dtb.misses 47747 # DTB misses 1251system.cpu1.dtb.accesses 49774582 # DTB accesses 1252system.cpu1.itb.inst_hits 8394995 # ITB inst hits 1253system.cpu1.itb.inst_misses 5378 # ITB inst misses | 1810system.cpu1.dtb.hits 50152108 # DTB hits 1811system.cpu1.dtb.misses 48279 # DTB misses 1812system.cpu1.dtb.accesses 50200387 # DTB accesses 1813system.cpu1.itb.inst_hits 8467709 # ITB inst hits 1814system.cpu1.itb.inst_misses 5542 # ITB inst misses |
| 1254system.cpu1.itb.read_hits 0 # DTB read hits 1255system.cpu1.itb.read_misses 0 # DTB read misses 1256system.cpu1.itb.write_hits 0 # DTB write hits 1257system.cpu1.itb.write_misses 0 # DTB write misses 1258system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1259system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1260system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1261system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1815system.cpu1.itb.read_hits 0 # DTB read hits 1816system.cpu1.itb.read_misses 0 # DTB read misses 1817system.cpu1.itb.write_hits 0 # DTB write hits 1818system.cpu1.itb.write_misses 0 # DTB write misses 1819system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1820system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1821system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1822system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1262system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB | 1823system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB |
| 1263system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1264system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1265system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1824system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1825system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1826system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1266system.cpu1.itb.perms_faults 1500 # Number of TLB faults due to permissions restrictions | 1827system.cpu1.itb.perms_faults 1492 # Number of TLB faults due to permissions restrictions |
| 1267system.cpu1.itb.read_accesses 0 # DTB read accesses 1268system.cpu1.itb.write_accesses 0 # DTB write accesses | 1828system.cpu1.itb.read_accesses 0 # DTB read accesses 1829system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1269system.cpu1.itb.inst_accesses 8400373 # ITB inst accesses 1270system.cpu1.itb.hits 8394995 # DTB hits 1271system.cpu1.itb.misses 5378 # DTB misses 1272system.cpu1.itb.accesses 8400373 # DTB accesses 1273system.cpu1.numCycles 408777731 # number of cpu cycles simulated | 1830system.cpu1.itb.inst_accesses 8473251 # ITB inst accesses 1831system.cpu1.itb.hits 8467709 # DTB hits 1832system.cpu1.itb.misses 5542 # DTB misses 1833system.cpu1.itb.accesses 8473251 # DTB accesses 1834system.cpu1.numCycles 412553366 # number of cpu cycles simulated |
| 1274system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1275system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1835system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1836system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1276system.cpu1.fetch.icacheStallCycles 19817241 # Number of cycles fetch is stalled on an Icache miss 1277system.cpu1.fetch.Insts 66077936 # Number of instructions fetch has processed 1278system.cpu1.fetch.Branches 9076266 # Number of branches that fetch encountered 1279system.cpu1.fetch.predictedBranches 6021354 # Number of branches that fetch has predicted taken 1280system.cpu1.fetch.Cycles 14149044 # Number of cycles fetch has run and was not squashing or blocked 1281system.cpu1.fetch.SquashCycles 3958978 # Number of cycles fetch has spent squashing 1282system.cpu1.fetch.TlbCycles 63415 # Number of cycles fetch has spent waiting for tlb 1283system.cpu1.fetch.BlockedCycles 75978247 # Number of cycles fetch has spent blocked 1284system.cpu1.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1285system.cpu1.fetch.PendingTrapStallCycles 42826 # Number of stall cycles due to pending traps 1286system.cpu1.fetch.PendingQuiesceStallCycles 1407438 # Number of stall cycles due to pending quiesce instructions 1287system.cpu1.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR 1288system.cpu1.fetch.CacheLines 8393192 # Number of cache lines fetched 1289system.cpu1.fetch.IcacheSquashes 739597 # Number of outstanding Icache misses that were squashed 1290system.cpu1.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed 1291system.cpu1.fetch.rateDist::samples 114161892 # Number of instructions fetched each cycle (Total) 1292system.cpu1.fetch.rateDist::mean 0.700766 # Number of instructions fetched each cycle (Total) 1293system.cpu1.fetch.rateDist::stdev 2.044841 # Number of instructions fetched each cycle (Total) | 1837system.cpu1.fetch.icacheStallCycles 20142179 # Number of cycles fetch is stalled on an Icache miss 1838system.cpu1.fetch.Insts 67124404 # Number of instructions fetch has processed 1839system.cpu1.fetch.Branches 9253585 # Number of branches that fetch encountered 1840system.cpu1.fetch.predictedBranches 6123954 # Number of branches that fetch has predicted taken 1841system.cpu1.fetch.Cycles 14367636 # Number of cycles fetch has run and was not squashing or blocked 1842system.cpu1.fetch.SquashCycles 3996679 # Number of cycles fetch has spent squashing 1843system.cpu1.fetch.TlbCycles 69030 # Number of cycles fetch has spent waiting for tlb 1844system.cpu1.fetch.BlockedCycles 77666254 # Number of cycles fetch has spent blocked 1845system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1846system.cpu1.fetch.PendingTrapStallCycles 41513 # Number of stall cycles due to pending traps 1847system.cpu1.fetch.PendingQuiesceStallCycles 1490350 # Number of stall cycles due to pending quiesce instructions 1848system.cpu1.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR 1849system.cpu1.fetch.CacheLines 8465907 # Number of cache lines fetched 1850system.cpu1.fetch.IcacheSquashes 710561 # Number of outstanding Icache misses that were squashed 1851system.cpu1.fetch.ItlbSquashes 2899 # Number of outstanding ITLB misses that were squashed 1852system.cpu1.fetch.rateDist::samples 116503477 # Number of instructions fetched each cycle (Total) 1853system.cpu1.fetch.rateDist::mean 0.698188 # Number of instructions fetched each cycle (Total) 1854system.cpu1.fetch.rateDist::stdev 2.043258 # Number of instructions fetched each cycle (Total) |
| 1294system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1855system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1295system.cpu1.fetch.rateDist::0 100020305 87.61% 87.61% # Number of instructions fetched each cycle (Total) 1296system.cpu1.fetch.rateDist::1 795953 0.70% 88.31% # Number of instructions fetched each cycle (Total) 1297system.cpu1.fetch.rateDist::2 939001 0.82% 89.13% # Number of instructions fetched each cycle (Total) 1298system.cpu1.fetch.rateDist::3 1889167 1.65% 90.79% # Number of instructions fetched each cycle (Total) 1299system.cpu1.fetch.rateDist::4 1518004 1.33% 92.12% # Number of instructions fetched each cycle (Total) 1300system.cpu1.fetch.rateDist::5 578108 0.51% 92.62% # Number of instructions fetched each cycle (Total) 1301system.cpu1.fetch.rateDist::6 2132011 1.87% 94.49% # Number of instructions fetched each cycle (Total) 1302system.cpu1.fetch.rateDist::7 410005 0.36% 94.85% # Number of instructions fetched each cycle (Total) 1303system.cpu1.fetch.rateDist::8 5879338 5.15% 100.00% # Number of instructions fetched each cycle (Total) | 1856system.cpu1.fetch.rateDist::0 102143196 87.67% 87.67% # Number of instructions fetched each cycle (Total) 1857system.cpu1.fetch.rateDist::1 814134 0.70% 88.37% # Number of instructions fetched each cycle (Total) 1858system.cpu1.fetch.rateDist::2 962782 0.83% 89.20% # Number of instructions fetched each cycle (Total) 1859system.cpu1.fetch.rateDist::3 1912655 1.64% 90.84% # Number of instructions fetched each cycle (Total) 1860system.cpu1.fetch.rateDist::4 1508621 1.29% 92.14% # Number of instructions fetched each cycle (Total) 1861system.cpu1.fetch.rateDist::5 586161 0.50% 92.64% # Number of instructions fetched each cycle (Total) 1862system.cpu1.fetch.rateDist::6 2143967 1.84% 94.48% # Number of instructions fetched each cycle (Total) 1863system.cpu1.fetch.rateDist::7 421141 0.36% 94.84% # Number of instructions fetched each cycle (Total) 1864system.cpu1.fetch.rateDist::8 6010820 5.16% 100.00% # Number of instructions fetched each cycle (Total) |
| 1304system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1305system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1306system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1865system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1866system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1867system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1307system.cpu1.fetch.rateDist::total 114161892 # Number of instructions fetched each cycle (Total) 1308system.cpu1.fetch.branchRate 0.022203 # Number of branch fetches per cycle 1309system.cpu1.fetch.rate 0.161648 # Number of inst fetches per cycle 1310system.cpu1.decode.IdleCycles 21336269 # Number of cycles decode is idle 1311system.cpu1.decode.BlockedCycles 76905312 # Number of cycles decode is blocked 1312system.cpu1.decode.RunCycles 12792890 # Number of cycles decode is running 1313system.cpu1.decode.UnblockCycles 524784 # Number of cycles decode is unblocking 1314system.cpu1.decode.SquashCycles 2602637 # Number of cycles decode is squashing 1315system.cpu1.decode.BranchResolved 1103950 # Number of times decode resolved a branch 1316system.cpu1.decode.BranchMispred 97871 # Number of times decode detected a branch misprediction 1317system.cpu1.decode.DecodedInsts 75228090 # Number of instructions handled by decode 1318system.cpu1.decode.SquashedInsts 324995 # Number of squashed instructions handled by decode 1319system.cpu1.rename.SquashCycles 2602637 # Number of cycles rename is squashing 1320system.cpu1.rename.IdleCycles 22719770 # Number of cycles rename is idle 1321system.cpu1.rename.BlockCycles 31941572 # Number of cycles rename is blocking 1322system.cpu1.rename.serializeStallCycles 40729697 # count of cycles rename stalled for serializing inst 1323system.cpu1.rename.RunCycles 11839035 # Number of cycles rename is running 1324system.cpu1.rename.UnblockCycles 4329181 # Number of cycles rename is unblocking 1325system.cpu1.rename.RenamedInsts 69767929 # Number of instructions processed by rename 1326system.cpu1.rename.ROBFullEvents 18791 # Number of times rename has blocked due to ROB full 1327system.cpu1.rename.IQFullEvents 669754 # Number of times rename has blocked due to IQ full 1328system.cpu1.rename.LSQFullEvents 3086107 # Number of times rename has blocked due to LSQ full 1329system.cpu1.rename.FullRegisterEvents 334 # Number of times there has been no free registers 1330system.cpu1.rename.RenamedOperands 73761871 # Number of destination operands rename has renamed 1331system.cpu1.rename.RenameLookups 321211401 # Number of register rename lookups that rename has made 1332system.cpu1.rename.int_rename_lookups 321151882 # Number of integer rename lookups 1333system.cpu1.rename.fp_rename_lookups 59519 # Number of floating rename lookups 1334system.cpu1.rename.CommittedMaps 49052831 # Number of HB maps that are committed 1335system.cpu1.rename.UndoneMaps 24709040 # Number of HB maps that are undone due to squashing 1336system.cpu1.rename.serializingInsts 445091 # count of serializing insts renamed 1337system.cpu1.rename.tempSerializingInsts 388163 # count of temporary serializing insts renamed 1338system.cpu1.rename.skidInsts 7873081 # count of insts added to the skid buffer 1339system.cpu1.memDep0.insertedLoads 13208830 # Number of loads inserted to the mem dependence unit. 1340system.cpu1.memDep0.insertedStores 8144792 # Number of stores inserted to the mem dependence unit. 1341system.cpu1.memDep0.conflictingLoads 1029727 # Number of conflicting loads. 1342system.cpu1.memDep0.conflictingStores 1553546 # Number of conflicting stores. 1343system.cpu1.iq.iqInstsAdded 63522315 # Number of instructions added to the IQ (excludes non-spec) 1344system.cpu1.iq.iqNonSpecInstsAdded 1158429 # Number of non-speculative instructions added to the IQ 1345system.cpu1.iq.iqInstsIssued 89134167 # Number of instructions issued 1346system.cpu1.iq.iqSquashedInstsIssued 94409 # Number of squashed instructions issued 1347system.cpu1.iq.iqSquashedInstsExamined 16267434 # Number of squashed instructions iterated over during squash; mainly for profiling 1348system.cpu1.iq.iqSquashedOperandsExamined 45777798 # Number of squashed operands that are examined and possibly removed from graph 1349system.cpu1.iq.iqSquashedNonSpecRemoved 277724 # Number of squashed non-spec instructions that were removed 1350system.cpu1.iq.issued_per_cycle::samples 114161892 # Number of insts issued each cycle 1351system.cpu1.iq.issued_per_cycle::mean 0.780770 # Number of insts issued each cycle 1352system.cpu1.iq.issued_per_cycle::stdev 1.519105 # Number of insts issued each cycle | 1868system.cpu1.fetch.rateDist::total 116503477 # Number of instructions fetched each cycle (Total) 1869system.cpu1.fetch.branchRate 0.022430 # Number of branch fetches per cycle 1870system.cpu1.fetch.rate 0.162705 # Number of inst fetches per cycle 1871system.cpu1.decode.IdleCycles 21695015 # Number of cycles decode is idle 1872system.cpu1.decode.BlockedCycles 78657608 # Number of cycles decode is blocked 1873system.cpu1.decode.RunCycles 12988209 # Number of cycles decode is running 1874system.cpu1.decode.UnblockCycles 540911 # Number of cycles decode is unblocking 1875system.cpu1.decode.SquashCycles 2621734 # Number of cycles decode is squashing 1876system.cpu1.decode.BranchResolved 1137928 # Number of times decode resolved a branch 1877system.cpu1.decode.BranchMispred 100371 # Number of times decode detected a branch misprediction 1878system.cpu1.decode.DecodedInsts 76331637 # Number of instructions handled by decode 1879system.cpu1.decode.SquashedInsts 334218 # Number of squashed instructions handled by decode 1880system.cpu1.rename.SquashCycles 2621734 # Number of cycles rename is squashing 1881system.cpu1.rename.IdleCycles 23056356 # Number of cycles rename is idle 1882system.cpu1.rename.BlockCycles 33279261 # Number of cycles rename is blocking 1883system.cpu1.rename.serializeStallCycles 41089956 # count of cycles rename stalled for serializing inst 1884system.cpu1.rename.RunCycles 12073504 # Number of cycles rename is running 1885system.cpu1.rename.UnblockCycles 4382666 # Number of cycles rename is unblocking 1886system.cpu1.rename.RenamedInsts 71129037 # Number of instructions processed by rename 1887system.cpu1.rename.ROBFullEvents 18835 # Number of times rename has blocked due to ROB full 1888system.cpu1.rename.IQFullEvents 684998 # Number of times rename has blocked due to IQ full 1889system.cpu1.rename.LSQFullEvents 3107715 # Number of times rename has blocked due to LSQ full 1890system.cpu1.rename.FullRegisterEvents 374 # Number of times there has been no free registers 1891system.cpu1.rename.RenamedOperands 75211284 # Number of destination operands rename has renamed 1892system.cpu1.rename.RenameLookups 327489941 # Number of register rename lookups that rename has made 1893system.cpu1.rename.int_rename_lookups 327430919 # Number of integer rename lookups 1894system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups 1895system.cpu1.rename.CommittedMaps 50108296 # Number of HB maps that are committed 1896system.cpu1.rename.UndoneMaps 25102988 # Number of HB maps that are undone due to squashing 1897system.cpu1.rename.serializingInsts 461152 # count of serializing insts renamed 1898system.cpu1.rename.tempSerializingInsts 401338 # count of temporary serializing insts renamed 1899system.cpu1.rename.skidInsts 8025308 # count of insts added to the skid buffer 1900system.cpu1.memDep0.insertedLoads 13414582 # Number of loads inserted to the mem dependence unit. 1901system.cpu1.memDep0.insertedStores 8304810 # Number of stores inserted to the mem dependence unit. 1902system.cpu1.memDep0.conflictingLoads 1056481 # Number of conflicting loads. 1903system.cpu1.memDep0.conflictingStores 1432553 # Number of conflicting stores. 1904system.cpu1.iq.iqInstsAdded 64611179 # Number of instructions added to the IQ (excludes non-spec) 1905system.cpu1.iq.iqNonSpecInstsAdded 1174620 # Number of non-speculative instructions added to the IQ 1906system.cpu1.iq.iqInstsIssued 90302569 # Number of instructions issued 1907system.cpu1.iq.iqSquashedInstsIssued 94169 # Number of squashed instructions issued 1908system.cpu1.iq.iqSquashedInstsExamined 16313013 # Number of squashed instructions iterated over during squash; mainly for profiling 1909system.cpu1.iq.iqSquashedOperandsExamined 45540722 # Number of squashed operands that are examined and possibly removed from graph 1910system.cpu1.iq.iqSquashedNonSpecRemoved 275640 # Number of squashed non-spec instructions that were removed 1911system.cpu1.iq.issued_per_cycle::samples 116503477 # Number of insts issued each cycle 1912system.cpu1.iq.issued_per_cycle::mean 0.775106 # Number of insts issued each cycle 1913system.cpu1.iq.issued_per_cycle::stdev 1.513735 # Number of insts issued each cycle |
| 1353system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1914system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1354system.cpu1.iq.issued_per_cycle::0 83758719 73.37% 73.37% # Number of insts issued each cycle 1355system.cpu1.iq.issued_per_cycle::1 8417078 7.37% 80.74% # Number of insts issued each cycle 1356system.cpu1.iq.issued_per_cycle::2 4293584 3.76% 84.50% # Number of insts issued each cycle 1357system.cpu1.iq.issued_per_cycle::3 3776789 3.31% 87.81% # Number of insts issued each cycle 1358system.cpu1.iq.issued_per_cycle::4 10574202 9.26% 97.07% # Number of insts issued each cycle 1359system.cpu1.iq.issued_per_cycle::5 1966117 1.72% 98.80% # Number of insts issued each cycle 1360system.cpu1.iq.issued_per_cycle::6 1029866 0.90% 99.70% # Number of insts issued each cycle 1361system.cpu1.iq.issued_per_cycle::7 271331 0.24% 99.93% # Number of insts issued each cycle 1362system.cpu1.iq.issued_per_cycle::8 74206 0.07% 100.00% # Number of insts issued each cycle | 1915system.cpu1.iq.issued_per_cycle::0 85607171 73.48% 73.48% # Number of insts issued each cycle 1916system.cpu1.iq.issued_per_cycle::1 8609069 7.39% 80.87% # Number of insts issued each cycle 1917system.cpu1.iq.issued_per_cycle::2 4398916 3.78% 84.65% # Number of insts issued each cycle 1918system.cpu1.iq.issued_per_cycle::3 3887525 3.34% 87.98% # Number of insts issued each cycle 1919system.cpu1.iq.issued_per_cycle::4 10612061 9.11% 97.09% # Number of insts issued each cycle 1920system.cpu1.iq.issued_per_cycle::5 1964931 1.69% 98.78% # Number of insts issued each cycle 1921system.cpu1.iq.issued_per_cycle::6 1085414 0.93% 99.71% # Number of insts issued each cycle 1922system.cpu1.iq.issued_per_cycle::7 259410 0.22% 99.93% # Number of insts issued each cycle 1923system.cpu1.iq.issued_per_cycle::8 78980 0.07% 100.00% # Number of insts issued each cycle |
| 1363system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1364system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1365system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1924system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1925system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1926system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1366system.cpu1.iq.issued_per_cycle::total 114161892 # Number of insts issued each cycle | 1927system.cpu1.iq.issued_per_cycle::total 116503477 # Number of insts issued each cycle |
| 1367system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1928system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1368system.cpu1.iq.fu_full::IntAlu 32060 0.41% 0.41% # attempts to use FU when none available 1369system.cpu1.iq.fu_full::IntMult 998 0.01% 0.42% # attempts to use FU when none available | 1929system.cpu1.iq.fu_full::IntAlu 32357 0.41% 0.41% # attempts to use FU when none available 1930system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available |
| 1370system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 1371system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 1372system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1373system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1374system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 1375system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1376system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 1377system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 1389system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 1390system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1391system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1392system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1393system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 1394system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 1395system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 1396system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available | 1931system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 1932system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 1933system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1934system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1935system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 1936system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1937system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 1938system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 1950system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 1951system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1952system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1953system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1954system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 1955system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 1956system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 1957system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available |
| 1397system.cpu1.iq.fu_full::MemRead 7549280 95.84% 96.26% # attempts to use FU when none available 1398system.cpu1.iq.fu_full::MemWrite 294896 3.74% 100.00% # attempts to use FU when none available | 1958system.cpu1.iq.fu_full::MemRead 7572484 95.70% 96.12% # attempts to use FU when none available 1959system.cpu1.iq.fu_full::MemWrite 307046 3.88% 100.00% # attempts to use FU when none available |
| 1399system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1400system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1401system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued | 1960system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1961system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1962system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued |
| 1402system.cpu1.iq.FU_type_0::IntAlu 37620086 42.21% 42.56% # Type of FU issued 1403system.cpu1.iq.FU_type_0::IntMult 59138 0.07% 42.62% # Type of FU issued 1404system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued 1405system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued 1406system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued 1407system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued 1408system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued 1409system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued 1410system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued 1411system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued 1412system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued 1413system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued 1414system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued 1415system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued 1416system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.62% # Type of FU issued 1417system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued 1418system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued 1419system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued 1420system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.62% # Type of FU issued 1421system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued 1422system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued 1423system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued 1424system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued 1425system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued 1426system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued 1427system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued 1428system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued 1429system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.63% # Type of FU issued 1430system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued 1431system.cpu1.iq.FU_type_0::MemRead 43968936 49.33% 91.96% # Type of FU issued 1432system.cpu1.iq.FU_type_0::MemWrite 7170532 8.04% 100.00% # Type of FU issued | 1963system.cpu1.iq.FU_type_0::IntAlu 38359652 42.48% 42.83% # Type of FU issued 1964system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.89% # Type of FU issued 1965system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.89% # Type of FU issued 1966system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.89% # Type of FU issued 1967system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.89% # Type of FU issued 1968system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.89% # Type of FU issued 1969system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.89% # Type of FU issued 1970system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.89% # Type of FU issued 1971system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.89% # Type of FU issued 1972system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.89% # Type of FU issued 1973system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.89% # Type of FU issued 1974system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.89% # Type of FU issued 1975system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.89% # Type of FU issued 1976system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.89% # Type of FU issued 1977system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 42.89% # Type of FU issued 1978system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.89% # Type of FU issued 1979system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.89% # Type of FU issued 1980system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.89% # Type of FU issued 1981system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.89% # Type of FU issued 1982system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.89% # Type of FU issued 1983system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.89% # Type of FU issued 1984system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.89% # Type of FU issued 1985system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.89% # Type of FU issued 1986system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.89% # Type of FU issued 1987system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.89% # Type of FU issued 1988system.cpu1.iq.FU_type_0::SimdFloatMisc 1701 0.00% 42.90% # Type of FU issued 1989system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.90% # Type of FU issued 1990system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.90% # Type of FU issued 1991system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.90% # Type of FU issued 1992system.cpu1.iq.FU_type_0::MemRead 44223929 48.97% 91.87% # Type of FU issued 1993system.cpu1.iq.FU_type_0::MemWrite 7342124 8.13% 100.00% # Type of FU issued |
| 1433system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1434system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1994system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1995system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1435system.cpu1.iq.FU_type_0::total 89134167 # Type of FU issued 1436system.cpu1.iq.rate 0.218050 # Inst issue rate 1437system.cpu1.iq.fu_busy_cnt 7877234 # FU busy when requested 1438system.cpu1.iq.fu_busy_rate 0.088375 # FU busy rate (busy events/executed inst) 1439system.cpu1.iq.int_inst_queue_reads 300434418 # Number of integer instruction queue reads 1440system.cpu1.iq.int_inst_queue_writes 80956642 # Number of integer instruction queue writes 1441system.cpu1.iq.int_inst_queue_wakeup_accesses 53641825 # Number of integer instruction queue wakeup accesses 1442system.cpu1.iq.fp_inst_queue_reads 15018 # Number of floating instruction queue reads 1443system.cpu1.iq.fp_inst_queue_writes 8136 # Number of floating instruction queue writes 1444system.cpu1.iq.fp_inst_queue_wakeup_accesses 6869 # Number of floating instruction queue wakeup accesses 1445system.cpu1.iq.int_alu_accesses 96689561 # Number of integer alu accesses 1446system.cpu1.iq.fp_alu_accesses 7908 # Number of floating point alu accesses 1447system.cpu1.iew.lsq.thread0.forwLoads 342287 # Number of loads that had data forwarded from stores | 1996system.cpu1.iq.FU_type_0::total 90302569 # Type of FU issued 1997system.cpu1.iq.rate 0.218887 # Inst issue rate 1998system.cpu1.iq.fu_busy_cnt 7912883 # FU busy when requested 1999system.cpu1.iq.fu_busy_rate 0.087626 # FU busy rate (busy events/executed inst) 2000system.cpu1.iq.int_inst_queue_reads 305148356 # Number of integer instruction queue reads 2001system.cpu1.iq.int_inst_queue_writes 82107584 # Number of integer instruction queue writes 2002system.cpu1.iq.int_inst_queue_wakeup_accesses 54845197 # Number of integer instruction queue wakeup accesses 2003system.cpu1.iq.fp_inst_queue_reads 15407 # Number of floating instruction queue reads 2004system.cpu1.iq.fp_inst_queue_writes 8039 # Number of floating instruction queue writes 2005system.cpu1.iq.fp_inst_queue_wakeup_accesses 6808 # Number of floating instruction queue wakeup accesses 2006system.cpu1.iq.int_alu_accesses 97893314 # Number of integer alu accesses 2007system.cpu1.iq.fp_alu_accesses 8206 # Number of floating point alu accesses 2008system.cpu1.iew.lsq.thread0.forwLoads 355446 # Number of loads that had data forwarded from stores |
| 1448system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2009system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1449system.cpu1.iew.lsq.thread0.squashedLoads 3455090 # Number of loads squashed 1450system.cpu1.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed 1451system.cpu1.iew.lsq.thread0.memOrderViolation 17135 # Number of memory ordering violations 1452system.cpu1.iew.lsq.thread0.squashedStores 1305851 # Number of stores squashed | 2010system.cpu1.iew.lsq.thread0.squashedLoads 3436601 # Number of loads squashed 2011system.cpu1.iew.lsq.thread0.ignoredResponses 3841 # Number of memory responses ignored because the instruction is squashed 2012system.cpu1.iew.lsq.thread0.memOrderViolation 17378 # Number of memory ordering violations 2013system.cpu1.iew.lsq.thread0.squashedStores 1303587 # Number of stores squashed |
| 1453system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1454system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2014system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2015system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1455system.cpu1.iew.lsq.thread0.rescheduledLoads 31905929 # Number of loads that were rescheduled 1456system.cpu1.iew.lsq.thread0.cacheBlocked 888458 # Number of times an access to memory failed due to the cache being blocked | 2016system.cpu1.iew.lsq.thread0.rescheduledLoads 31958921 # Number of loads that were rescheduled 2017system.cpu1.iew.lsq.thread0.cacheBlocked 917809 # Number of times an access to memory failed due to the cache being blocked |
| 1457system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2018system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1458system.cpu1.iew.iewSquashCycles 2602637 # Number of cycles IEW is squashing 1459system.cpu1.iew.iewBlockCycles 24185109 # Number of cycles IEW is blocking 1460system.cpu1.iew.iewUnblockCycles 359685 # Number of cycles IEW is unblocking 1461system.cpu1.iew.iewDispatchedInsts 64785366 # Number of instructions dispatched to IQ 1462system.cpu1.iew.iewDispSquashedInsts 111899 # Number of squashed instructions skipped by dispatch 1463system.cpu1.iew.iewDispLoadInsts 13208830 # Number of dispatched load instructions 1464system.cpu1.iew.iewDispStoreInsts 8144792 # Number of dispatched store instructions 1465system.cpu1.iew.iewDispNonSpecInsts 869085 # Number of dispatched non-speculative instructions 1466system.cpu1.iew.iewIQFullEvents 64974 # Number of times the IQ has become full, causing a stall 1467system.cpu1.iew.iewLSQFullEvents 3561 # Number of times the LSQ has become full, causing a stall 1468system.cpu1.iew.memOrderViolationEvents 17135 # Number of memory order violations 1469system.cpu1.iew.predictedTakenIncorrect 202123 # Number of branches that were predicted taken incorrectly 1470system.cpu1.iew.predictedNotTakenIncorrect 154728 # Number of branches that were predicted not taken incorrectly 1471system.cpu1.iew.branchMispredicts 356851 # Number of branch mispredicts detected at execute 1472system.cpu1.iew.iewExecutedInsts 86703480 # Number of executed instructions 1473system.cpu1.iew.iewExecLoadInsts 43273897 # Number of load instructions executed 1474system.cpu1.iew.iewExecSquashedInsts 2430687 # Number of squashed instructions skipped in execute | 2019system.cpu1.iew.iewSquashCycles 2621734 # Number of cycles IEW is squashing 2020system.cpu1.iew.iewBlockCycles 25482277 # Number of cycles IEW is blocking 2021system.cpu1.iew.iewUnblockCycles 363023 # Number of cycles IEW is unblocking 2022system.cpu1.iew.iewDispatchedInsts 65889169 # Number of instructions dispatched to IQ 2023system.cpu1.iew.iewDispSquashedInsts 115264 # Number of squashed instructions skipped by dispatch 2024system.cpu1.iew.iewDispLoadInsts 13414582 # Number of dispatched load instructions 2025system.cpu1.iew.iewDispStoreInsts 8304810 # Number of dispatched store instructions 2026system.cpu1.iew.iewDispNonSpecInsts 878172 # Number of dispatched non-speculative instructions 2027system.cpu1.iew.iewIQFullEvents 66494 # Number of times the IQ has become full, causing a stall 2028system.cpu1.iew.iewLSQFullEvents 3874 # Number of times the LSQ has become full, causing a stall 2029system.cpu1.iew.memOrderViolationEvents 17378 # Number of memory order violations 2030system.cpu1.iew.predictedTakenIncorrect 205598 # Number of branches that were predicted taken incorrectly 2031system.cpu1.iew.predictedNotTakenIncorrect 157346 # Number of branches that were predicted not taken incorrectly 2032system.cpu1.iew.branchMispredicts 362944 # Number of branch mispredicts detected at execute 2033system.cpu1.iew.iewExecutedInsts 87965313 # Number of executed instructions 2034system.cpu1.iew.iewExecLoadInsts 43561744 # Number of load instructions executed 2035system.cpu1.iew.iewExecSquashedInsts 2337256 # Number of squashed instructions skipped in execute |
| 1475system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2036system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1476system.cpu1.iew.exec_nop 104622 # number of nop insts executed 1477system.cpu1.iew.exec_refs 50383100 # number of memory reference insts executed 1478system.cpu1.iew.exec_branches 6997981 # Number of branches executed 1479system.cpu1.iew.exec_stores 7109203 # Number of stores executed 1480system.cpu1.iew.exec_rate 0.212104 # Inst execution rate 1481system.cpu1.iew.wb_sent 85724428 # cumulative count of insts sent to commit 1482system.cpu1.iew.wb_count 53648694 # cumulative count of insts written-back 1483system.cpu1.iew.wb_producers 29926721 # num instructions producing a value 1484system.cpu1.iew.wb_consumers 53389506 # num instructions consuming a value | 2037system.cpu1.iew.exec_nop 103370 # number of nop insts executed 2038system.cpu1.iew.exec_refs 50840273 # number of memory reference insts executed 2039system.cpu1.iew.exec_branches 7156944 # Number of branches executed 2040system.cpu1.iew.exec_stores 7278529 # Number of stores executed 2041system.cpu1.iew.exec_rate 0.213222 # Inst execution rate 2042system.cpu1.iew.wb_sent 86983330 # cumulative count of insts sent to commit 2043system.cpu1.iew.wb_count 54852005 # cumulative count of insts written-back 2044system.cpu1.iew.wb_producers 30529736 # num instructions producing a value 2045system.cpu1.iew.wb_consumers 54511543 # num instructions consuming a value |
| 1485system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2046system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1486system.cpu1.iew.wb_rate 0.131242 # insts written-back per cycle 1487system.cpu1.iew.wb_fanout 0.560536 # average fanout of values written-back | 2047system.cpu1.iew.wb_rate 0.132957 # insts written-back per cycle 2048system.cpu1.iew.wb_fanout 0.560060 # average fanout of values written-back |
| 1488system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2049system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1489system.cpu1.commit.commitSquashedInsts 16147511 # The number of squashed insts skipped by commit 1490system.cpu1.commit.commitNonSpecStalls 880705 # The number of times commit has been forced to stall to communicate backwards 1491system.cpu1.commit.branchMispredicts 311675 # The number of times a branch was mispredicted 1492system.cpu1.commit.committed_per_cycle::samples 111559255 # Number of insts commited each cycle 1493system.cpu1.commit.committed_per_cycle::mean 0.431612 # Number of insts commited each cycle 1494system.cpu1.commit.committed_per_cycle::stdev 1.399673 # Number of insts commited each cycle | 2050system.cpu1.commit.commitSquashedInsts 16208484 # The number of squashed insts skipped by commit 2051system.cpu1.commit.commitNonSpecStalls 898980 # The number of times commit has been forced to stall to communicate backwards 2052system.cpu1.commit.branchMispredicts 317402 # The number of times a branch was mispredicted 2053system.cpu1.commit.committed_per_cycle::samples 113881743 # Number of insts commited each cycle 2054system.cpu1.commit.committed_per_cycle::mean 0.432055 # Number of insts commited each cycle 2055system.cpu1.commit.committed_per_cycle::stdev 1.398122 # Number of insts commited each cycle |
| 1495system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2056system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1496system.cpu1.commit.committed_per_cycle::0 94810700 84.99% 84.99% # Number of insts commited each cycle 1497system.cpu1.commit.committed_per_cycle::1 8240774 7.39% 92.37% # Number of insts commited each cycle 1498system.cpu1.commit.committed_per_cycle::2 2114811 1.90% 94.27% # Number of insts commited each cycle 1499system.cpu1.commit.committed_per_cycle::3 1254575 1.12% 95.39% # Number of insts commited each cycle 1500system.cpu1.commit.committed_per_cycle::4 1245157 1.12% 96.51% # Number of insts commited each cycle 1501system.cpu1.commit.committed_per_cycle::5 568382 0.51% 97.02% # Number of insts commited each cycle 1502system.cpu1.commit.committed_per_cycle::6 999815 0.90% 97.92% # Number of insts commited each cycle 1503system.cpu1.commit.committed_per_cycle::7 505524 0.45% 98.37% # Number of insts commited each cycle 1504system.cpu1.commit.committed_per_cycle::8 1819517 1.63% 100.00% # Number of insts commited each cycle | 2057system.cpu1.commit.committed_per_cycle::0 96739305 84.95% 84.95% # Number of insts commited each cycle 2058system.cpu1.commit.committed_per_cycle::1 8399776 7.38% 92.32% # Number of insts commited each cycle 2059system.cpu1.commit.committed_per_cycle::2 2206670 1.94% 94.26% # Number of insts commited each cycle 2060system.cpu1.commit.committed_per_cycle::3 1295256 1.14% 95.40% # Number of insts commited each cycle 2061system.cpu1.commit.committed_per_cycle::4 1289720 1.13% 96.53% # Number of insts commited each cycle 2062system.cpu1.commit.committed_per_cycle::5 586162 0.51% 97.05% # Number of insts commited each cycle 2063system.cpu1.commit.committed_per_cycle::6 954092 0.84% 97.88% # Number of insts commited each cycle 2064system.cpu1.commit.committed_per_cycle::7 596070 0.52% 98.41% # Number of insts commited each cycle 2065system.cpu1.commit.committed_per_cycle::8 1814692 1.59% 100.00% # Number of insts commited each cycle |
| 1505system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1506system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1507system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2066system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2067system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2068system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1508system.cpu1.commit.committed_per_cycle::total 111559255 # Number of insts commited each cycle 1509system.cpu1.commit.committedInsts 38062798 # Number of instructions committed 1510system.cpu1.commit.committedOps 48150353 # Number of ops (including micro ops) committed | 2069system.cpu1.commit.committed_per_cycle::total 113881743 # Number of insts commited each cycle 2070system.cpu1.commit.committedInsts 38868743 # Number of instructions committed 2071system.cpu1.commit.committedOps 49203152 # Number of ops (including micro ops) committed |
| 1511system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2072system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1512system.cpu1.commit.refs 16592681 # Number of memory references committed 1513system.cpu1.commit.loads 9753740 # Number of loads committed 1514system.cpu1.commit.membars 190132 # Number of memory barriers committed 1515system.cpu1.commit.branches 5967363 # Number of branches committed 1516system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. 1517system.cpu1.commit.int_insts 42685619 # Number of committed integer instructions. 1518system.cpu1.commit.function_calls 534609 # Number of function calls committed. 1519system.cpu1.commit.bw_lim_events 1819517 # number cycles where commit BW limit reached | 2073system.cpu1.commit.refs 16979204 # Number of memory references committed 2074system.cpu1.commit.loads 9977981 # Number of loads committed 2075system.cpu1.commit.membars 195491 # Number of memory barriers committed 2076system.cpu1.commit.branches 6119212 # Number of branches committed 2077system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 2078system.cpu1.commit.int_insts 43616743 # Number of committed integer instructions. 2079system.cpu1.commit.function_calls 553203 # Number of function calls committed. 2080system.cpu1.commit.bw_lim_events 1814692 # number cycles where commit BW limit reached |
| 1520system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 2081system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1521system.cpu1.rob.rob_reads 172993511 # The number of ROB reads 1522system.cpu1.rob.rob_writes 131291211 # The number of ROB writes 1523system.cpu1.timesIdled 1408204 # Number of times that the entire CPU went into an idle state and unscheduled itself 1524system.cpu1.idleCycles 294615839 # Total number of cycles that the CPU has spent unscheduled due to idling 1525system.cpu1.quiesceCycles 1796493799 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1526system.cpu1.committedInsts 37993159 # Number of Instructions Simulated 1527system.cpu1.committedOps 48080714 # Number of Ops (including micro ops) Simulated 1528system.cpu1.committedInsts_total 37993159 # Number of Instructions Simulated 1529system.cpu1.cpi 10.759246 # CPI: Cycles Per Instruction 1530system.cpu1.cpi_total 10.759246 # CPI: Total CPI of All Threads 1531system.cpu1.ipc 0.092943 # IPC: Instructions Per Cycle 1532system.cpu1.ipc_total 0.092943 # IPC: Total IPC of All Threads 1533system.cpu1.int_regfile_reads 387964882 # number of integer regfile reads 1534system.cpu1.int_regfile_writes 56217113 # number of integer regfile writes 1535system.cpu1.fp_regfile_reads 4997 # number of floating regfile reads 1536system.cpu1.fp_regfile_writes 2346 # number of floating regfile writes 1537system.cpu1.misc_regfile_reads 18468785 # number of misc regfile reads 1538system.cpu1.misc_regfile_writes 405479 # number of misc regfile writes 1539system.cpu1.icache.replacements 595625 # number of replacements 1540system.cpu1.icache.tagsinuse 480.695488 # Cycle average of tags in use 1541system.cpu1.icache.total_refs 7752260 # Total number of references to valid blocks. 1542system.cpu1.icache.sampled_refs 596137 # Sample count of references to valid blocks. 1543system.cpu1.icache.avg_refs 13.004158 # Average number of references to valid blocks. 1544system.cpu1.icache.warmup_cycle 74233129000 # Cycle when the warmup percentage was hit. 1545system.cpu1.icache.occ_blocks::cpu1.inst 480.695488 # Average occupied blocks per requestor 1546system.cpu1.icache.occ_percent::cpu1.inst 0.938858 # Average percentage of cache occupancy 1547system.cpu1.icache.occ_percent::total 0.938858 # Average percentage of cache occupancy 1548system.cpu1.icache.ReadReq_hits::cpu1.inst 7752260 # number of ReadReq hits 1549system.cpu1.icache.ReadReq_hits::total 7752260 # number of ReadReq hits 1550system.cpu1.icache.demand_hits::cpu1.inst 7752260 # number of demand (read+write) hits 1551system.cpu1.icache.demand_hits::total 7752260 # number of demand (read+write) hits 1552system.cpu1.icache.overall_hits::cpu1.inst 7752260 # number of overall hits 1553system.cpu1.icache.overall_hits::total 7752260 # number of overall hits 1554system.cpu1.icache.ReadReq_misses::cpu1.inst 640881 # number of ReadReq misses 1555system.cpu1.icache.ReadReq_misses::total 640881 # number of ReadReq misses 1556system.cpu1.icache.demand_misses::cpu1.inst 640881 # number of demand (read+write) misses 1557system.cpu1.icache.demand_misses::total 640881 # number of demand (read+write) misses 1558system.cpu1.icache.overall_misses::cpu1.inst 640881 # number of overall misses 1559system.cpu1.icache.overall_misses::total 640881 # number of overall misses 1560system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8621805995 # number of ReadReq miss cycles 1561system.cpu1.icache.ReadReq_miss_latency::total 8621805995 # number of ReadReq miss cycles 1562system.cpu1.icache.demand_miss_latency::cpu1.inst 8621805995 # number of demand (read+write) miss cycles 1563system.cpu1.icache.demand_miss_latency::total 8621805995 # number of demand (read+write) miss cycles 1564system.cpu1.icache.overall_miss_latency::cpu1.inst 8621805995 # number of overall miss cycles 1565system.cpu1.icache.overall_miss_latency::total 8621805995 # number of overall miss cycles 1566system.cpu1.icache.ReadReq_accesses::cpu1.inst 8393141 # number of ReadReq accesses(hits+misses) 1567system.cpu1.icache.ReadReq_accesses::total 8393141 # number of ReadReq accesses(hits+misses) 1568system.cpu1.icache.demand_accesses::cpu1.inst 8393141 # number of demand (read+write) accesses 1569system.cpu1.icache.demand_accesses::total 8393141 # number of demand (read+write) accesses 1570system.cpu1.icache.overall_accesses::cpu1.inst 8393141 # number of overall (read+write) accesses 1571system.cpu1.icache.overall_accesses::total 8393141 # number of overall (read+write) accesses 1572system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076358 # miss rate for ReadReq accesses 1573system.cpu1.icache.ReadReq_miss_rate::total 0.076358 # miss rate for ReadReq accesses 1574system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076358 # miss rate for demand accesses 1575system.cpu1.icache.demand_miss_rate::total 0.076358 # miss rate for demand accesses 1576system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076358 # miss rate for overall accesses 1577system.cpu1.icache.overall_miss_rate::total 0.076358 # miss rate for overall accesses 1578system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.052899 # average ReadReq miss latency 1579system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.052899 # average ReadReq miss latency 1580system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.052899 # average overall miss latency 1581system.cpu1.icache.demand_avg_miss_latency::total 13453.052899 # average overall miss latency 1582system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.052899 # average overall miss latency 1583system.cpu1.icache.overall_avg_miss_latency::total 13453.052899 # average overall miss latency 1584system.cpu1.icache.blocked_cycles::no_mshrs 2044 # number of cycles access was blocked | 2082system.cpu1.rob.rob_reads 176412864 # The number of ROB reads 2083system.cpu1.rob.rob_writes 133542996 # The number of ROB writes 2084system.cpu1.timesIdled 1428534 # Number of times that the entire CPU went into an idle state and unscheduled itself 2085system.cpu1.idleCycles 296049889 # Total number of cycles that the CPU has spent unscheduled due to idling 2086system.cpu1.quiesceCycles 4814402067 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2087system.cpu1.committedInsts 38799104 # Number of Instructions Simulated 2088system.cpu1.committedOps 49133513 # Number of Ops (including micro ops) Simulated 2089system.cpu1.committedInsts_total 38799104 # Number of Instructions Simulated 2090system.cpu1.cpi 10.633064 # CPI: Cycles Per Instruction 2091system.cpu1.cpi_total 10.633064 # CPI: Total CPI of All Threads 2092system.cpu1.ipc 0.094046 # IPC: Instructions Per Cycle 2093system.cpu1.ipc_total 0.094046 # IPC: Total IPC of All Threads 2094system.cpu1.int_regfile_reads 393827212 # number of integer regfile reads 2095system.cpu1.int_regfile_writes 57409312 # number of integer regfile writes 2096system.cpu1.fp_regfile_reads 5077 # number of floating regfile reads 2097system.cpu1.fp_regfile_writes 2342 # number of floating regfile writes 2098system.cpu1.misc_regfile_reads 18946986 # number of misc regfile reads 2099system.cpu1.misc_regfile_writes 419134 # number of misc regfile writes 2100system.cpu1.icache.replacements 614670 # number of replacements 2101system.cpu1.icache.tagsinuse 498.803951 # Cycle average of tags in use 2102system.cpu1.icache.total_refs 7804426 # Total number of references to valid blocks. 2103system.cpu1.icache.sampled_refs 615182 # Sample count of references to valid blocks. 2104system.cpu1.icache.avg_refs 12.686369 # Average number of references to valid blocks. 2105system.cpu1.icache.warmup_cycle 74831061000 # Cycle when the warmup percentage was hit. 2106system.cpu1.icache.occ_blocks::cpu1.inst 498.803951 # Average occupied blocks per requestor 2107system.cpu1.icache.occ_percent::cpu1.inst 0.974226 # Average percentage of cache occupancy 2108system.cpu1.icache.occ_percent::total 0.974226 # Average percentage of cache occupancy 2109system.cpu1.icache.ReadReq_hits::cpu1.inst 7804426 # number of ReadReq hits 2110system.cpu1.icache.ReadReq_hits::total 7804426 # number of ReadReq hits 2111system.cpu1.icache.demand_hits::cpu1.inst 7804426 # number of demand (read+write) hits 2112system.cpu1.icache.demand_hits::total 7804426 # number of demand (read+write) hits 2113system.cpu1.icache.overall_hits::cpu1.inst 7804426 # number of overall hits 2114system.cpu1.icache.overall_hits::total 7804426 # number of overall hits 2115system.cpu1.icache.ReadReq_misses::cpu1.inst 661434 # number of ReadReq misses 2116system.cpu1.icache.ReadReq_misses::total 661434 # number of ReadReq misses 2117system.cpu1.icache.demand_misses::cpu1.inst 661434 # number of demand (read+write) misses 2118system.cpu1.icache.demand_misses::total 661434 # number of demand (read+write) misses 2119system.cpu1.icache.overall_misses::cpu1.inst 661434 # number of overall misses 2120system.cpu1.icache.overall_misses::total 661434 # number of overall misses 2121system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8993382992 # number of ReadReq miss cycles 2122system.cpu1.icache.ReadReq_miss_latency::total 8993382992 # number of ReadReq miss cycles 2123system.cpu1.icache.demand_miss_latency::cpu1.inst 8993382992 # number of demand (read+write) miss cycles 2124system.cpu1.icache.demand_miss_latency::total 8993382992 # number of demand (read+write) miss cycles 2125system.cpu1.icache.overall_miss_latency::cpu1.inst 8993382992 # number of overall miss cycles 2126system.cpu1.icache.overall_miss_latency::total 8993382992 # number of overall miss cycles 2127system.cpu1.icache.ReadReq_accesses::cpu1.inst 8465860 # number of ReadReq accesses(hits+misses) 2128system.cpu1.icache.ReadReq_accesses::total 8465860 # number of ReadReq accesses(hits+misses) 2129system.cpu1.icache.demand_accesses::cpu1.inst 8465860 # number of demand (read+write) accesses 2130system.cpu1.icache.demand_accesses::total 8465860 # number of demand (read+write) accesses 2131system.cpu1.icache.overall_accesses::cpu1.inst 8465860 # number of overall (read+write) accesses 2132system.cpu1.icache.overall_accesses::total 8465860 # number of overall (read+write) accesses 2133system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078130 # miss rate for ReadReq accesses 2134system.cpu1.icache.ReadReq_miss_rate::total 0.078130 # miss rate for ReadReq accesses 2135system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078130 # miss rate for demand accesses 2136system.cpu1.icache.demand_miss_rate::total 0.078130 # miss rate for demand accesses 2137system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078130 # miss rate for overall accesses 2138system.cpu1.icache.overall_miss_rate::total 0.078130 # miss rate for overall accesses 2139system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.795738 # average ReadReq miss latency 2140system.cpu1.icache.ReadReq_avg_miss_latency::total 13596.795738 # average ReadReq miss latency 2141system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency 2142system.cpu1.icache.demand_avg_miss_latency::total 13596.795738 # average overall miss latency 2143system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency 2144system.cpu1.icache.overall_avg_miss_latency::total 13596.795738 # average overall miss latency 2145system.cpu1.icache.blocked_cycles::no_mshrs 3054 # number of cycles access was blocked |
| 1585system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2146system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1586system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked | 2147system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked |
| 1587system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 2148system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1588system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.883721 # average number of cycles each access was blocked | 2149system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.897561 # average number of cycles each access was blocked |
| 1589system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1590system.cpu1.icache.fast_writes 0 # number of fast writes performed 1591system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2150system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2151system.cpu1.icache.fast_writes 0 # number of fast writes performed 2152system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1592system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44715 # number of ReadReq MSHR hits 1593system.cpu1.icache.ReadReq_mshr_hits::total 44715 # number of ReadReq MSHR hits 1594system.cpu1.icache.demand_mshr_hits::cpu1.inst 44715 # number of demand (read+write) MSHR hits 1595system.cpu1.icache.demand_mshr_hits::total 44715 # number of demand (read+write) MSHR hits 1596system.cpu1.icache.overall_mshr_hits::cpu1.inst 44715 # number of overall MSHR hits 1597system.cpu1.icache.overall_mshr_hits::total 44715 # number of overall MSHR hits 1598system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596166 # number of ReadReq MSHR misses 1599system.cpu1.icache.ReadReq_mshr_misses::total 596166 # number of ReadReq MSHR misses 1600system.cpu1.icache.demand_mshr_misses::cpu1.inst 596166 # number of demand (read+write) MSHR misses 1601system.cpu1.icache.demand_mshr_misses::total 596166 # number of demand (read+write) MSHR misses 1602system.cpu1.icache.overall_mshr_misses::cpu1.inst 596166 # number of overall MSHR misses 1603system.cpu1.icache.overall_mshr_misses::total 596166 # number of overall MSHR misses 1604system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7061200496 # number of ReadReq MSHR miss cycles 1605system.cpu1.icache.ReadReq_mshr_miss_latency::total 7061200496 # number of ReadReq MSHR miss cycles 1606system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7061200496 # number of demand (read+write) MSHR miss cycles 1607system.cpu1.icache.demand_mshr_miss_latency::total 7061200496 # number of demand (read+write) MSHR miss cycles 1608system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7061200496 # number of overall MSHR miss cycles 1609system.cpu1.icache.overall_mshr_miss_latency::total 7061200496 # number of overall MSHR miss cycles 1610system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2836500 # number of ReadReq MSHR uncacheable cycles 1611system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2836500 # number of ReadReq MSHR uncacheable cycles 1612system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2836500 # number of overall MSHR uncacheable cycles 1613system.cpu1.icache.overall_mshr_uncacheable_latency::total 2836500 # number of overall MSHR uncacheable cycles 1614system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for ReadReq accesses 1615system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071030 # mshr miss rate for ReadReq accesses 1616system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for demand accesses 1617system.cpu1.icache.demand_mshr_miss_rate::total 0.071030 # mshr miss rate for demand accesses 1618system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for overall accesses 1619system.cpu1.icache.overall_mshr_miss_rate::total 0.071030 # mshr miss rate for overall accesses 1620system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average ReadReq mshr miss latency 1621system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.352908 # average ReadReq mshr miss latency 1622system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average overall mshr miss latency 1623system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.352908 # average overall mshr miss latency 1624system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average overall mshr miss latency 1625system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.352908 # average overall mshr miss latency | 2153system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46219 # number of ReadReq MSHR hits 2154system.cpu1.icache.ReadReq_mshr_hits::total 46219 # number of ReadReq MSHR hits 2155system.cpu1.icache.demand_mshr_hits::cpu1.inst 46219 # number of demand (read+write) MSHR hits 2156system.cpu1.icache.demand_mshr_hits::total 46219 # number of demand (read+write) MSHR hits 2157system.cpu1.icache.overall_mshr_hits::cpu1.inst 46219 # number of overall MSHR hits 2158system.cpu1.icache.overall_mshr_hits::total 46219 # number of overall MSHR hits 2159system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615215 # number of ReadReq MSHR misses 2160system.cpu1.icache.ReadReq_mshr_misses::total 615215 # number of ReadReq MSHR misses 2161system.cpu1.icache.demand_mshr_misses::cpu1.inst 615215 # number of demand (read+write) MSHR misses 2162system.cpu1.icache.demand_mshr_misses::total 615215 # number of demand (read+write) MSHR misses 2163system.cpu1.icache.overall_mshr_misses::cpu1.inst 615215 # number of overall MSHR misses 2164system.cpu1.icache.overall_mshr_misses::total 615215 # number of overall MSHR misses 2165system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7348125977 # number of ReadReq MSHR miss cycles 2166system.cpu1.icache.ReadReq_mshr_miss_latency::total 7348125977 # number of ReadReq MSHR miss cycles 2167system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7348125977 # number of demand (read+write) MSHR miss cycles 2168system.cpu1.icache.demand_mshr_miss_latency::total 7348125977 # number of demand (read+write) MSHR miss cycles 2169system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7348125977 # number of overall MSHR miss cycles 2170system.cpu1.icache.overall_mshr_miss_latency::total 7348125977 # number of overall MSHR miss cycles 2171system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3395500 # number of ReadReq MSHR uncacheable cycles 2172system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3395500 # number of ReadReq MSHR uncacheable cycles 2173system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3395500 # number of overall MSHR uncacheable cycles 2174system.cpu1.icache.overall_mshr_uncacheable_latency::total 3395500 # number of overall MSHR uncacheable cycles 2175system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for ReadReq accesses 2176system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.072670 # mshr miss rate for ReadReq accesses 2177system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for demand accesses 2178system.cpu1.icache.demand_mshr_miss_rate::total 0.072670 # mshr miss rate for demand accesses 2179system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for overall accesses 2180system.cpu1.icache.overall_mshr_miss_rate::total 0.072670 # mshr miss rate for overall accesses 2181system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average ReadReq mshr miss latency 2182system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11943.996777 # average ReadReq mshr miss latency 2183system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average overall mshr miss latency 2184system.cpu1.icache.demand_avg_mshr_miss_latency::total 11943.996777 # average overall mshr miss latency 2185system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average overall mshr miss latency 2186system.cpu1.icache.overall_avg_mshr_miss_latency::total 11943.996777 # average overall mshr miss latency |
| 1626system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1627system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1628system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1629system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1630system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2187system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2188system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2189system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2190system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2191system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1631system.cpu1.dcache.replacements 360596 # number of replacements 1632system.cpu1.dcache.tagsinuse 474.658932 # Cycle average of tags in use 1633system.cpu1.dcache.total_refs 12676805 # Total number of references to valid blocks. 1634system.cpu1.dcache.sampled_refs 360947 # Sample count of references to valid blocks. 1635system.cpu1.dcache.avg_refs 35.120960 # Average number of references to valid blocks. 1636system.cpu1.dcache.warmup_cycle 70362477000 # Cycle when the warmup percentage was hit. 1637system.cpu1.dcache.occ_blocks::cpu1.data 474.658932 # Average occupied blocks per requestor 1638system.cpu1.dcache.occ_percent::cpu1.data 0.927068 # Average percentage of cache occupancy 1639system.cpu1.dcache.occ_percent::total 0.927068 # Average percentage of cache occupancy 1640system.cpu1.dcache.ReadReq_hits::cpu1.data 8309067 # number of ReadReq hits 1641system.cpu1.dcache.ReadReq_hits::total 8309067 # number of ReadReq hits 1642system.cpu1.dcache.WriteReq_hits::cpu1.data 4139347 # number of WriteReq hits 1643system.cpu1.dcache.WriteReq_hits::total 4139347 # number of WriteReq hits 1644system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97521 # number of LoadLockedReq hits 1645system.cpu1.dcache.LoadLockedReq_hits::total 97521 # number of LoadLockedReq hits 1646system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94873 # number of StoreCondReq hits 1647system.cpu1.dcache.StoreCondReq_hits::total 94873 # number of StoreCondReq hits 1648system.cpu1.dcache.demand_hits::cpu1.data 12448414 # number of demand (read+write) hits 1649system.cpu1.dcache.demand_hits::total 12448414 # number of demand (read+write) hits 1650system.cpu1.dcache.overall_hits::cpu1.data 12448414 # number of overall hits 1651system.cpu1.dcache.overall_hits::total 12448414 # number of overall hits 1652system.cpu1.dcache.ReadReq_misses::cpu1.data 400056 # number of ReadReq misses 1653system.cpu1.dcache.ReadReq_misses::total 400056 # number of ReadReq misses 1654system.cpu1.dcache.WriteReq_misses::cpu1.data 1556122 # number of WriteReq misses 1655system.cpu1.dcache.WriteReq_misses::total 1556122 # number of WriteReq misses 1656system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13956 # number of LoadLockedReq misses 1657system.cpu1.dcache.LoadLockedReq_misses::total 13956 # number of LoadLockedReq misses 1658system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10608 # number of StoreCondReq misses 1659system.cpu1.dcache.StoreCondReq_misses::total 10608 # number of StoreCondReq misses 1660system.cpu1.dcache.demand_misses::cpu1.data 1956178 # number of demand (read+write) misses 1661system.cpu1.dcache.demand_misses::total 1956178 # number of demand (read+write) misses 1662system.cpu1.dcache.overall_misses::cpu1.data 1956178 # number of overall misses 1663system.cpu1.dcache.overall_misses::total 1956178 # number of overall misses 1664system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6114203000 # number of ReadReq miss cycles 1665system.cpu1.dcache.ReadReq_miss_latency::total 6114203000 # number of ReadReq miss cycles 1666system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61457337496 # number of WriteReq miss cycles 1667system.cpu1.dcache.WriteReq_miss_latency::total 61457337496 # number of WriteReq miss cycles 1668system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 130378000 # number of LoadLockedReq miss cycles 1669system.cpu1.dcache.LoadLockedReq_miss_latency::total 130378000 # number of LoadLockedReq miss cycles 1670system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53868000 # number of StoreCondReq miss cycles 1671system.cpu1.dcache.StoreCondReq_miss_latency::total 53868000 # number of StoreCondReq miss cycles 1672system.cpu1.dcache.demand_miss_latency::cpu1.data 67571540496 # number of demand (read+write) miss cycles 1673system.cpu1.dcache.demand_miss_latency::total 67571540496 # number of demand (read+write) miss cycles 1674system.cpu1.dcache.overall_miss_latency::cpu1.data 67571540496 # number of overall miss cycles 1675system.cpu1.dcache.overall_miss_latency::total 67571540496 # number of overall miss cycles 1676system.cpu1.dcache.ReadReq_accesses::cpu1.data 8709123 # number of ReadReq accesses(hits+misses) 1677system.cpu1.dcache.ReadReq_accesses::total 8709123 # number of ReadReq accesses(hits+misses) 1678system.cpu1.dcache.WriteReq_accesses::cpu1.data 5695469 # number of WriteReq accesses(hits+misses) 1679system.cpu1.dcache.WriteReq_accesses::total 5695469 # number of WriteReq accesses(hits+misses) 1680system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111477 # number of LoadLockedReq accesses(hits+misses) 1681system.cpu1.dcache.LoadLockedReq_accesses::total 111477 # number of LoadLockedReq accesses(hits+misses) 1682system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105481 # number of StoreCondReq accesses(hits+misses) 1683system.cpu1.dcache.StoreCondReq_accesses::total 105481 # number of StoreCondReq accesses(hits+misses) 1684system.cpu1.dcache.demand_accesses::cpu1.data 14404592 # number of demand (read+write) accesses 1685system.cpu1.dcache.demand_accesses::total 14404592 # number of demand (read+write) accesses 1686system.cpu1.dcache.overall_accesses::cpu1.data 14404592 # number of overall (read+write) accesses 1687system.cpu1.dcache.overall_accesses::total 14404592 # number of overall (read+write) accesses 1688system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045935 # miss rate for ReadReq accesses 1689system.cpu1.dcache.ReadReq_miss_rate::total 0.045935 # miss rate for ReadReq accesses 1690system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273221 # miss rate for WriteReq accesses 1691system.cpu1.dcache.WriteReq_miss_rate::total 0.273221 # miss rate for WriteReq accesses 1692system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125192 # miss rate for LoadLockedReq accesses 1693system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125192 # miss rate for LoadLockedReq accesses 1694system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100568 # miss rate for StoreCondReq accesses 1695system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100568 # miss rate for StoreCondReq accesses 1696system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135802 # miss rate for demand accesses 1697system.cpu1.dcache.demand_miss_rate::total 0.135802 # miss rate for demand accesses 1698system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135802 # miss rate for overall accesses 1699system.cpu1.dcache.overall_miss_rate::total 0.135802 # miss rate for overall accesses 1700system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15283.367829 # average ReadReq miss latency 1701system.cpu1.dcache.ReadReq_avg_miss_latency::total 15283.367829 # average ReadReq miss latency 1702system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39493.906966 # average WriteReq miss latency 1703system.cpu1.dcache.WriteReq_avg_miss_latency::total 39493.906966 # average WriteReq miss latency 1704system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9342.075093 # average LoadLockedReq miss latency 1705system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9342.075093 # average LoadLockedReq miss latency 1706system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5078.054299 # average StoreCondReq miss latency 1707system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5078.054299 # average StoreCondReq miss latency 1708system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34542.633899 # average overall miss latency 1709system.cpu1.dcache.demand_avg_miss_latency::total 34542.633899 # average overall miss latency 1710system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34542.633899 # average overall miss latency 1711system.cpu1.dcache.overall_avg_miss_latency::total 34542.633899 # average overall miss latency 1712system.cpu1.dcache.blocked_cycles::no_mshrs 26379 # number of cycles access was blocked 1713system.cpu1.dcache.blocked_cycles::no_targets 12882 # number of cycles access was blocked 1714system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked 1715system.cpu1.dcache.blocked::no_targets 156 # number of cycles access was blocked 1716system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.921622 # average number of cycles each access was blocked 1717system.cpu1.dcache.avg_blocked_cycles::no_targets 82.576923 # average number of cycles each access was blocked | 2192system.cpu1.dcache.replacements 363541 # number of replacements 2193system.cpu1.dcache.tagsinuse 487.194544 # Cycle average of tags in use 2194system.cpu1.dcache.total_refs 13012998 # Total number of references to valid blocks. 2195system.cpu1.dcache.sampled_refs 363907 # Sample count of references to valid blocks. 2196system.cpu1.dcache.avg_refs 35.759131 # Average number of references to valid blocks. 2197system.cpu1.dcache.warmup_cycle 70879256000 # Cycle when the warmup percentage was hit. 2198system.cpu1.dcache.occ_blocks::cpu1.data 487.194544 # Average occupied blocks per requestor 2199system.cpu1.dcache.occ_percent::cpu1.data 0.951552 # Average percentage of cache occupancy 2200system.cpu1.dcache.occ_percent::total 0.951552 # Average percentage of cache occupancy 2201system.cpu1.dcache.ReadReq_hits::cpu1.data 8508304 # number of ReadReq hits 2202system.cpu1.dcache.ReadReq_hits::total 8508304 # number of ReadReq hits 2203system.cpu1.dcache.WriteReq_hits::cpu1.data 4270423 # number of WriteReq hits 2204system.cpu1.dcache.WriteReq_hits::total 4270423 # number of WriteReq hits 2205system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99789 # number of LoadLockedReq hits 2206system.cpu1.dcache.LoadLockedReq_hits::total 99789 # number of LoadLockedReq hits 2207system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97069 # number of StoreCondReq hits 2208system.cpu1.dcache.StoreCondReq_hits::total 97069 # number of StoreCondReq hits 2209system.cpu1.dcache.demand_hits::cpu1.data 12778727 # number of demand (read+write) hits 2210system.cpu1.dcache.demand_hits::total 12778727 # number of demand (read+write) hits 2211system.cpu1.dcache.overall_hits::cpu1.data 12778727 # number of overall hits 2212system.cpu1.dcache.overall_hits::total 12778727 # number of overall hits 2213system.cpu1.dcache.ReadReq_misses::cpu1.data 403002 # number of ReadReq misses 2214system.cpu1.dcache.ReadReq_misses::total 403002 # number of ReadReq misses 2215system.cpu1.dcache.WriteReq_misses::cpu1.data 1564321 # number of WriteReq misses 2216system.cpu1.dcache.WriteReq_misses::total 1564321 # number of WriteReq misses 2217system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14195 # number of LoadLockedReq misses 2218system.cpu1.dcache.LoadLockedReq_misses::total 14195 # number of LoadLockedReq misses 2219system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10908 # number of StoreCondReq misses 2220system.cpu1.dcache.StoreCondReq_misses::total 10908 # number of StoreCondReq misses 2221system.cpu1.dcache.demand_misses::cpu1.data 1967323 # number of demand (read+write) misses 2222system.cpu1.dcache.demand_misses::total 1967323 # number of demand (read+write) misses 2223system.cpu1.dcache.overall_misses::cpu1.data 1967323 # number of overall misses 2224system.cpu1.dcache.overall_misses::total 1967323 # number of overall misses 2225system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6229483500 # number of ReadReq miss cycles 2226system.cpu1.dcache.ReadReq_miss_latency::total 6229483500 # number of ReadReq miss cycles 2227system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75673370015 # number of WriteReq miss cycles 2228system.cpu1.dcache.WriteReq_miss_latency::total 75673370015 # number of WriteReq miss cycles 2229system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131282500 # number of LoadLockedReq miss cycles 2230system.cpu1.dcache.LoadLockedReq_miss_latency::total 131282500 # number of LoadLockedReq miss cycles 2231system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57807000 # number of StoreCondReq miss cycles 2232system.cpu1.dcache.StoreCondReq_miss_latency::total 57807000 # number of StoreCondReq miss cycles 2233system.cpu1.dcache.demand_miss_latency::cpu1.data 81902853515 # number of demand (read+write) miss cycles 2234system.cpu1.dcache.demand_miss_latency::total 81902853515 # number of demand (read+write) miss cycles 2235system.cpu1.dcache.overall_miss_latency::cpu1.data 81902853515 # number of overall miss cycles 2236system.cpu1.dcache.overall_miss_latency::total 81902853515 # number of overall miss cycles 2237system.cpu1.dcache.ReadReq_accesses::cpu1.data 8911306 # number of ReadReq accesses(hits+misses) 2238system.cpu1.dcache.ReadReq_accesses::total 8911306 # number of ReadReq accesses(hits+misses) 2239system.cpu1.dcache.WriteReq_accesses::cpu1.data 5834744 # number of WriteReq accesses(hits+misses) 2240system.cpu1.dcache.WriteReq_accesses::total 5834744 # number of WriteReq accesses(hits+misses) 2241system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113984 # number of LoadLockedReq accesses(hits+misses) 2242system.cpu1.dcache.LoadLockedReq_accesses::total 113984 # number of LoadLockedReq accesses(hits+misses) 2243system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107977 # number of StoreCondReq accesses(hits+misses) 2244system.cpu1.dcache.StoreCondReq_accesses::total 107977 # number of StoreCondReq accesses(hits+misses) 2245system.cpu1.dcache.demand_accesses::cpu1.data 14746050 # number of demand (read+write) accesses 2246system.cpu1.dcache.demand_accesses::total 14746050 # number of demand (read+write) accesses 2247system.cpu1.dcache.overall_accesses::cpu1.data 14746050 # number of overall (read+write) accesses 2248system.cpu1.dcache.overall_accesses::total 14746050 # number of overall (read+write) accesses 2249system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045224 # miss rate for ReadReq accesses 2250system.cpu1.dcache.ReadReq_miss_rate::total 0.045224 # miss rate for ReadReq accesses 2251system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268104 # miss rate for WriteReq accesses 2252system.cpu1.dcache.WriteReq_miss_rate::total 0.268104 # miss rate for WriteReq accesses 2253system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124535 # miss rate for LoadLockedReq accesses 2254system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124535 # miss rate for LoadLockedReq accesses 2255system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101022 # miss rate for StoreCondReq accesses 2256system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101022 # miss rate for StoreCondReq accesses 2257system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133414 # miss rate for demand accesses 2258system.cpu1.dcache.demand_miss_rate::total 0.133414 # miss rate for demand accesses 2259system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133414 # miss rate for overall accesses 2260system.cpu1.dcache.overall_miss_rate::total 0.133414 # miss rate for overall accesses 2261system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15457.698721 # average ReadReq miss latency 2262system.cpu1.dcache.ReadReq_avg_miss_latency::total 15457.698721 # average ReadReq miss latency 2263system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48374.579140 # average WriteReq miss latency 2264system.cpu1.dcache.WriteReq_avg_miss_latency::total 48374.579140 # average WriteReq miss latency 2265system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.502994 # average LoadLockedReq miss latency 2266system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.502994 # average LoadLockedReq miss latency 2267system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5299.504950 # average StoreCondReq miss latency 2268system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5299.504950 # average StoreCondReq miss latency 2269system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency 2270system.cpu1.dcache.demand_avg_miss_latency::total 41631.625064 # average overall miss latency 2271system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency 2272system.cpu1.dcache.overall_avg_miss_latency::total 41631.625064 # average overall miss latency 2273system.cpu1.dcache.blocked_cycles::no_mshrs 31799 # number of cycles access was blocked 2274system.cpu1.dcache.blocked_cycles::no_targets 19293 # number of cycles access was blocked 2275system.cpu1.dcache.blocked::no_mshrs 3299 # number of cycles access was blocked 2276system.cpu1.dcache.blocked::no_targets 180 # number of cycles access was blocked 2277system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.638982 # average number of cycles each access was blocked 2278system.cpu1.dcache.avg_blocked_cycles::no_targets 107.183333 # average number of cycles each access was blocked |
| 1718system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1719system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2279system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2280system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1720system.cpu1.dcache.writebacks::writebacks 324632 # number of writebacks 1721system.cpu1.dcache.writebacks::total 324632 # number of writebacks 1722system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171788 # number of ReadReq MSHR hits 1723system.cpu1.dcache.ReadReq_mshr_hits::total 171788 # number of ReadReq MSHR hits 1724system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394549 # number of WriteReq MSHR hits 1725system.cpu1.dcache.WriteReq_mshr_hits::total 1394549 # number of WriteReq MSHR hits 1726system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1443 # number of LoadLockedReq MSHR hits 1727system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1443 # number of LoadLockedReq MSHR hits 1728system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566337 # number of demand (read+write) MSHR hits 1729system.cpu1.dcache.demand_mshr_hits::total 1566337 # number of demand (read+write) MSHR hits 1730system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566337 # number of overall MSHR hits 1731system.cpu1.dcache.overall_mshr_hits::total 1566337 # number of overall MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses 1733system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses 1734system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161573 # number of WriteReq MSHR misses 1735system.cpu1.dcache.WriteReq_mshr_misses::total 161573 # number of WriteReq MSHR misses 1736system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12513 # number of LoadLockedReq MSHR misses 1737system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12513 # number of LoadLockedReq MSHR misses 1738system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10605 # number of StoreCondReq MSHR misses 1739system.cpu1.dcache.StoreCondReq_mshr_misses::total 10605 # number of StoreCondReq MSHR misses 1740system.cpu1.dcache.demand_mshr_misses::cpu1.data 389841 # number of demand (read+write) MSHR misses 1741system.cpu1.dcache.demand_mshr_misses::total 389841 # number of demand (read+write) MSHR misses 1742system.cpu1.dcache.overall_mshr_misses::cpu1.data 389841 # number of overall MSHR misses 1743system.cpu1.dcache.overall_mshr_misses::total 389841 # number of overall MSHR misses 1744system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2854852000 # number of ReadReq MSHR miss cycles 1745system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2854852000 # number of ReadReq MSHR miss cycles 1746system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5117226213 # number of WriteReq MSHR miss cycles 1747system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5117226213 # number of WriteReq MSHR miss cycles 1748system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89555500 # number of LoadLockedReq MSHR miss cycles 1749system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89555500 # number of LoadLockedReq MSHR miss cycles 1750system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32658000 # number of StoreCondReq MSHR miss cycles 1751system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32658000 # number of StoreCondReq MSHR miss cycles 1752system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7972078213 # number of demand (read+write) MSHR miss cycles 1753system.cpu1.dcache.demand_mshr_miss_latency::total 7972078213 # number of demand (read+write) MSHR miss cycles 1754system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7972078213 # number of overall MSHR miss cycles 1755system.cpu1.dcache.overall_mshr_miss_latency::total 7972078213 # number of overall MSHR miss cycles 1756system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989815500 # number of ReadReq MSHR uncacheable cycles 1757system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989815500 # number of ReadReq MSHR uncacheable cycles 1758system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35679552148 # number of WriteReq MSHR uncacheable cycles 1759system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35679552148 # number of WriteReq MSHR uncacheable cycles 1760system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204669367648 # number of overall MSHR uncacheable cycles 1761system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204669367648 # number of overall MSHR uncacheable cycles 1762system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026210 # mshr miss rate for ReadReq accesses 1763system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026210 # mshr miss rate for ReadReq accesses 1764system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses 1765system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses 1766system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112247 # mshr miss rate for LoadLockedReq accesses 1767system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112247 # mshr miss rate for LoadLockedReq accesses 1768system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100539 # mshr miss rate for StoreCondReq accesses 1769system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100539 # mshr miss rate for StoreCondReq accesses 1770system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for demand accesses 1771system.cpu1.dcache.demand_mshr_miss_rate::total 0.027064 # mshr miss rate for demand accesses 1772system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for overall accesses 1773system.cpu1.dcache.overall_mshr_miss_rate::total 0.027064 # mshr miss rate for overall accesses 1774system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12506.579985 # average ReadReq mshr miss latency 1775system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12506.579985 # average ReadReq mshr miss latency 1776system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31671.295408 # average WriteReq mshr miss latency 1777system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31671.295408 # average WriteReq mshr miss latency 1778system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7156.996723 # average LoadLockedReq mshr miss latency 1779system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7156.996723 # average LoadLockedReq mshr miss latency 1780system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3079.490806 # average StoreCondReq mshr miss latency 1781system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3079.490806 # average StoreCondReq mshr miss latency 1782system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency 1783system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency 1784system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency 1785system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency | 2281system.cpu1.dcache.writebacks::writebacks 327984 # number of writebacks 2282system.cpu1.dcache.writebacks::total 327984 # number of writebacks 2283system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171525 # number of ReadReq MSHR hits 2284system.cpu1.dcache.ReadReq_mshr_hits::total 171525 # number of ReadReq MSHR hits 2285system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401265 # number of WriteReq MSHR hits 2286system.cpu1.dcache.WriteReq_mshr_hits::total 1401265 # number of WriteReq MSHR hits 2287system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits 2288system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits 2289system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572790 # number of demand (read+write) MSHR hits 2290system.cpu1.dcache.demand_mshr_hits::total 1572790 # number of demand (read+write) MSHR hits 2291system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572790 # number of overall MSHR hits 2292system.cpu1.dcache.overall_mshr_hits::total 1572790 # number of overall MSHR hits 2293system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231477 # number of ReadReq MSHR misses 2294system.cpu1.dcache.ReadReq_mshr_misses::total 231477 # number of ReadReq MSHR misses 2295system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163056 # number of WriteReq MSHR misses 2296system.cpu1.dcache.WriteReq_mshr_misses::total 163056 # number of WriteReq MSHR misses 2297system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses 2298system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses 2299system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10906 # number of StoreCondReq MSHR misses 2300system.cpu1.dcache.StoreCondReq_mshr_misses::total 10906 # number of StoreCondReq MSHR misses 2301system.cpu1.dcache.demand_mshr_misses::cpu1.data 394533 # number of demand (read+write) MSHR misses 2302system.cpu1.dcache.demand_mshr_misses::total 394533 # number of demand (read+write) MSHR misses 2303system.cpu1.dcache.overall_mshr_misses::cpu1.data 394533 # number of overall MSHR misses 2304system.cpu1.dcache.overall_mshr_misses::total 394533 # number of overall MSHR misses 2305system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2900781135 # number of ReadReq MSHR miss cycles 2306system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2900781135 # number of ReadReq MSHR miss cycles 2307system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6520340298 # number of WriteReq MSHR miss cycles 2308system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6520340298 # number of WriteReq MSHR miss cycles 2309system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90030007 # number of LoadLockedReq MSHR miss cycles 2310system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90030007 # number of LoadLockedReq MSHR miss cycles 2311system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35995000 # number of StoreCondReq MSHR miss cycles 2312system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35995000 # number of StoreCondReq MSHR miss cycles 2313system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9421121433 # number of demand (read+write) MSHR miss cycles 2314system.cpu1.dcache.demand_mshr_miss_latency::total 9421121433 # number of demand (read+write) MSHR miss cycles 2315system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9421121433 # number of overall MSHR miss cycles 2316system.cpu1.dcache.overall_mshr_miss_latency::total 9421121433 # number of overall MSHR miss cycles 2317system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169236235005 # number of ReadReq MSHR uncacheable cycles 2318system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169236235005 # number of ReadReq MSHR uncacheable cycles 2319system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34877229187 # number of WriteReq MSHR uncacheable cycles 2320system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34877229187 # number of WriteReq MSHR uncacheable cycles 2321system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204113464192 # number of overall MSHR uncacheable cycles 2322system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204113464192 # number of overall MSHR uncacheable cycles 2323system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025976 # mshr miss rate for ReadReq accesses 2324system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses 2325system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027946 # mshr miss rate for WriteReq accesses 2326system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027946 # mshr miss rate for WriteReq accesses 2327system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111823 # mshr miss rate for LoadLockedReq accesses 2328system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111823 # mshr miss rate for LoadLockedReq accesses 2329system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101003 # mshr miss rate for StoreCondReq accesses 2330system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101003 # mshr miss rate for StoreCondReq accesses 2331system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for demand accesses 2332system.cpu1.dcache.demand_mshr_miss_rate::total 0.026755 # mshr miss rate for demand accesses 2333system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for overall accesses 2334system.cpu1.dcache.overall_mshr_miss_rate::total 0.026755 # mshr miss rate for overall accesses 2335system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12531.617115 # average ReadReq mshr miss latency 2336system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12531.617115 # average ReadReq mshr miss latency 2337system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39988.349389 # average WriteReq mshr miss latency 2338system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39988.349389 # average WriteReq mshr miss latency 2339system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7063.392986 # average LoadLockedReq mshr miss latency 2340system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7063.392986 # average LoadLockedReq mshr miss latency 2341system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3300.476802 # average StoreCondReq mshr miss latency 2342system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3300.476802 # average StoreCondReq mshr miss latency 2343system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency 2344system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency 2345system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency 2346system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency |
| 1786system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1787system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1788system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1789system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1790system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1791system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1792system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1793system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1799system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1800system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1801system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1802system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1803system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1804system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1805system.iocache.fast_writes 0 # number of fast writes performed 1806system.iocache.cache_copies 0 # number of cache copies performed | 2347system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2348system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2349system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2350system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2351system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2352system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2353system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2354system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 2360system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2361system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2362system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2363system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2364system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2365system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2366system.iocache.fast_writes 0 # number of fast writes performed 2367system.iocache.cache_copies 0 # number of cache copies performed |
| 1807system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540125454155 # number of ReadReq MSHR uncacheable cycles 1808system.iocache.ReadReq_mshr_uncacheable_latency::total 540125454155 # number of ReadReq MSHR uncacheable cycles 1809system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540125454155 # number of overall MSHR uncacheable cycles 1810system.iocache.overall_mshr_uncacheable_latency::total 540125454155 # number of overall MSHR uncacheable cycles | 2368system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of ReadReq MSHR uncacheable cycles 2369system.iocache.ReadReq_mshr_uncacheable_latency::total 1508067529269 # number of ReadReq MSHR uncacheable cycles 2370system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of overall MSHR uncacheable cycles 2371system.iocache.overall_mshr_uncacheable_latency::total 1508067529269 # number of overall MSHR uncacheable cycles |
| 1811system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1812system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1813system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1814system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1815system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1816system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 2372system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2373system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2374system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2375system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2376system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2377system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1817system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed | 2378system.cpu0.kern.inst.quiesce 42383 # number of quiesce instructions executed |
| 1818system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 2379system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1819system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed | 2380system.cpu1.kern.inst.quiesce 50336 # number of quiesce instructions executed |
| 1820 1821---------- End Simulation Statistics ---------- | 2381 2382---------- End Simulation Statistics ---------- |