stats.txt (9536:8149223cd7db) | stats.txt (9568:cd1351d4d850) |
---|---|
1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 1.102937 # Number of seconds simulated 4sim_ticks 1102937390000 # Number of ticks simulated 5final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.102950 # Number of seconds simulated 4sim_ticks 1102950399000 # Number of ticks simulated 5final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 67484 # Simulator instruction rate (inst/s) 8host_op_rate 86868 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1208579190 # Simulator tick rate (ticks/s) 10host_mem_usage 412736 # Number of bytes of host memory used 11host_seconds 912.59 # Real time elapsed on the host 12sim_insts 61585042 # Number of instructions simulated 13sim_ops 79274675 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 57810 # Simulator instruction rate (inst/s) 8host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1035290197 # Simulator tick rate (ticks/s) 10host_mem_usage 414988 # Number of bytes of host memory used 11host_seconds 1065.35 # Real time elapsed on the host 12sim_insts 61588287 # Number of instructions simulated 13sim_ops 79281553 # Number of ops (including micro ops) simulated |
32system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory |
34system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory 40system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory 41system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory 42system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory 44system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory 23system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory |
45system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
47system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory | 30system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory |
48system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 49system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory | 31system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory |
50system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory | 33system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory |
58system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 59system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
60system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) |
62system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) |
63system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s) | 47system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) |
74system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) |
75system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s) | 60system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) |
79system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) | 64system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) |
80system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.readReqs 6257788 # Total number of read requests seen 88system.physmem.writeReqs 823390 # Total number of write requests seen 89system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady 90system.physmem.bytesRead 400498432 # Total number of bytes read from memory 91system.physmem.bytesWritten 52696960 # Total number of bytes written to memory 92system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize() 93system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize() 94system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q 95system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed 96system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis 97system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis 98system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis 99system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis 100system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis 101system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis 102system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis 103system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis 104system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis 105system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis 106system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis 107system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis 108system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis 109system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis 110system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis 111system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis 112system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis 113system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis 114system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis 115system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis 116system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis 117system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis 118system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis 119system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis 120system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis 121system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis 122system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis 123system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis | 65system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.readReqs 6257953 # Total number of read requests seen 74system.physmem.writeReqs 823537 # Total number of write requests seen 75system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady 76system.physmem.bytesRead 400508992 # Total number of bytes read from memory 77system.physmem.bytesWritten 52706368 # Total number of bytes written to memory 78system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() 79system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() 80system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q 81system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed 82system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis 94system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis 95system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis 96system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis 97system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis 98system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis |
124system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis | 110system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis |
125system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis 126system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis 127system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis | 111system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis 112system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis 113system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis |
128system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 114system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
129system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry 130system.physmem.totGap 1102936257500 # Total gap between requests | 115system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry 116system.physmem.totGap 1102949217500 # Total gap between requests |
131system.physmem.readPktSize::0 0 # Categorize read packet sizes 132system.physmem.readPktSize::1 0 # Categorize read packet sizes 133system.physmem.readPktSize::2 105 # Categorize read packet sizes 134system.physmem.readPktSize::3 6094848 # Categorize read packet sizes 135system.physmem.readPktSize::4 0 # Categorize read packet sizes 136system.physmem.readPktSize::5 0 # Categorize read packet sizes | 117system.physmem.readPktSize::0 0 # Categorize read packet sizes 118system.physmem.readPktSize::1 0 # Categorize read packet sizes 119system.physmem.readPktSize::2 105 # Categorize read packet sizes 120system.physmem.readPktSize::3 6094848 # Categorize read packet sizes 121system.physmem.readPktSize::4 0 # Categorize read packet sizes 122system.physmem.readPktSize::5 0 # Categorize read packet sizes |
137system.physmem.readPktSize::6 162835 # Categorize read packet sizes 138system.physmem.readPktSize::7 0 # Categorize read packet sizes 139system.physmem.readPktSize::8 0 # Categorize read packet sizes 140system.physmem.writePktSize::0 0 # categorize write packet sizes 141system.physmem.writePktSize::1 0 # categorize write packet sizes 142system.physmem.writePktSize::2 2999773 # categorize write packet sizes 143system.physmem.writePktSize::3 0 # categorize write packet sizes 144system.physmem.writePktSize::4 0 # categorize write packet sizes 145system.physmem.writePktSize::5 0 # categorize write packet sizes 146system.physmem.writePktSize::6 66554 # categorize write packet sizes 147system.physmem.writePktSize::7 0 # categorize write packet sizes 148system.physmem.writePktSize::8 0 # categorize write packet sizes 149system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 150system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 151system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 152system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 153system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 154system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 155system.physmem.neitherpktsize::6 12623 # categorize neither packet sizes 156system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 157system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 158system.physmem.rdQLenPdf::0 493621 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::1 430392 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::2 391768 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::3 1441431 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::4 1086063 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::5 1098338 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::6 1064335 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::7 26976 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::8 24854 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::9 44565 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::10 63872 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::11 44300 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::12 12061 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::13 11818 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::14 17153 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::15 5993 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see | 123system.physmem.readPktSize::6 163000 # Categorize read packet sizes 124system.physmem.writePktSize::0 0 # Categorize write packet sizes 125system.physmem.writePktSize::1 0 # Categorize write packet sizes 126system.physmem.writePktSize::2 756836 # Categorize write packet sizes 127system.physmem.writePktSize::3 0 # Categorize write packet sizes 128system.physmem.writePktSize::4 0 # Categorize write packet sizes 129system.physmem.writePktSize::5 0 # Categorize write packet sizes 130system.physmem.writePktSize::6 66701 # Categorize write packet sizes 131system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see |
175system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see | 148system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see |
176system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see | 149system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
178system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 187system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 151system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
190system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 191system.physmem.wrQLenPdf::0 2895 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::1 2949 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::2 2985 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::3 3021 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::4 3044 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::5 3067 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::6 3100 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::7 3123 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::8 3149 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::13 35799 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::14 35799 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::15 35799 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::16 35799 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::17 35799 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::18 35799 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::19 35799 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::24 32851 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::25 32815 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::26 32779 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::27 32756 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::28 32733 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::29 32700 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::30 32677 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::31 32651 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 224system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays 225system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests 226system.physmem.totBusLat 31288540000 # Total cycles spent in databus access 227system.physmem.totBankLat 8531820000 # Total cycles spent in bank access 228system.physmem.avgQLat 31828.06 # Average queueing delay per request 229system.physmem.avgBankLat 1363.41 # Average bank access latency per request | 163system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see 195system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays 196system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests 197system.physmem.totBusLat 31289160000 # Total cycles spent in databus access 198system.physmem.totBankLat 8530335000 # Total cycles spent in bank access 199system.physmem.avgQLat 31830.81 # Average queueing delay per request 200system.physmem.avgBankLat 1363.15 # Average bank access latency per request |
230system.physmem.avgBusLat 5000.00 # Average bus latency per request | 201system.physmem.avgBusLat 5000.00 # Average bus latency per request |
231system.physmem.avgMemAccLat 38191.47 # Average memory access latency 232system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s 233system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s 234system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s 235system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s | 202system.physmem.avgMemAccLat 38193.95 # Average memory access latency 203system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s 204system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s 205system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s 206system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s |
236system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 237system.physmem.busUtil 3.21 # Data bus utilization in percentage 238system.physmem.avgRdQLen 0.22 # Average read queue length over time | 207system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 208system.physmem.busUtil 3.21 # Data bus utilization in percentage 209system.physmem.avgRdQLen 0.22 # Average read queue length over time |
239system.physmem.avgWrQLen 10.24 # Average write queue length over time 240system.physmem.readRowHits 6213872 # Number of row buffer hits during reads 241system.physmem.writeRowHits 799892 # Number of row buffer hits during writes | 210system.physmem.avgWrQLen 11.98 # Average write queue length over time 211system.physmem.readRowHits 6213974 # Number of row buffer hits during reads 212system.physmem.writeRowHits 800028 # Number of row buffer hits during writes |
242system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads 243system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes | 213system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads 214system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes |
244system.physmem.avgGap 155756.04 # Average gap between requests 245system.l2c.replacements 72539 # number of replacements 246system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use 247system.l2c.total_refs 1841179 # Total number of references to valid blocks. 248system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. 249system.l2c.avg_refs 13.367838 # Average number of references to valid blocks. | 215system.physmem.avgGap 155751.01 # Average gap between requests 216system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 217system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 218system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 219system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 220system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 221system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 222system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 223system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 224system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 225system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) 228system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) 229system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) 230system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) 231system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) 232system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) 233system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) 234system.l2c.replacements 72704 # number of replacements 235system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use 236system.l2c.total_refs 1840692 # Total number of references to valid blocks. 237system.l2c.sampled_refs 137860 # Sample count of references to valid blocks. 238system.l2c.avg_refs 13.351893 # Average number of references to valid blocks. |
250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 239system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
251system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor 252system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor 253system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor 254system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor 255system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor 256system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor 257system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor 258system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor 259system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy | 240system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor 244system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor 245system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor 246system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor 247system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor 248system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor 249system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy |
260system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy | 250system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy |
261system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 262system.l2c.occ_percent::cpu0.inst 0.061172 # Average percentage of cache occupancy 263system.l2c.occ_percent::cpu0.data 0.042983 # Average percentage of cache occupancy 264system.l2c.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy 265system.l2c.occ_percent::cpu1.inst 0.056720 # Average percentage of cache occupancy 266system.l2c.occ_percent::cpu1.data 0.058048 # Average percentage of cache occupancy 267system.l2c.occ_percent::total 0.820194 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.dtb.walker 21699 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.itb.walker 4247 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu0.inst 385844 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu0.data 166771 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu1.dtb.walker 30512 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu1.itb.walker 5160 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu1.inst 591639 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu1.data 198020 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1403892 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 581178 # number of Writeback hits 278system.l2c.Writeback_hits::total 581178 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 1163 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::cpu1.data 739 # number of UpgradeReq hits 281system.l2c.UpgradeReq_hits::total 1902 # number of UpgradeReq hits 282system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits | 251system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy 252system.l2c.occ_percent::cpu0.inst 0.061165 # Average percentage of cache occupancy 253system.l2c.occ_percent::cpu0.data 0.043063 # Average percentage of cache occupancy 254system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy 255system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 256system.l2c.occ_percent::cpu1.inst 0.056709 # Average percentage of cache occupancy 257system.l2c.occ_percent::cpu1.data 0.058067 # Average percentage of cache occupancy 258system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy 259system.l2c.ReadReq_hits::cpu0.dtb.walker 21930 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu0.itb.walker 4443 # number of ReadReq hits 261system.l2c.ReadReq_hits::cpu0.inst 386616 # number of ReadReq hits 262system.l2c.ReadReq_hits::cpu0.data 166642 # number of ReadReq hits 263system.l2c.ReadReq_hits::cpu1.dtb.walker 30274 # number of ReadReq hits 264system.l2c.ReadReq_hits::cpu1.itb.walker 5231 # number of ReadReq hits 265system.l2c.ReadReq_hits::cpu1.inst 590416 # number of ReadReq hits 266system.l2c.ReadReq_hits::cpu1.data 197851 # number of ReadReq hits 267system.l2c.ReadReq_hits::total 1403403 # number of ReadReq hits 268system.l2c.Writeback_hits::writebacks 581067 # number of Writeback hits 269system.l2c.Writeback_hits::total 581067 # number of Writeback hits 270system.l2c.UpgradeReq_hits::cpu0.data 1230 # number of UpgradeReq hits 271system.l2c.UpgradeReq_hits::cpu1.data 737 # number of UpgradeReq hits 272system.l2c.UpgradeReq_hits::total 1967 # number of UpgradeReq hits 273system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits |
283system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits | 274system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits |
284system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits 285system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits 286system.l2c.ReadExReq_hits::cpu1.data 58985 # number of ReadExReq hits 287system.l2c.ReadExReq_hits::total 107027 # number of ReadExReq hits 288system.l2c.demand_hits::cpu0.dtb.walker 21699 # number of demand (read+write) hits 289system.l2c.demand_hits::cpu0.itb.walker 4247 # number of demand (read+write) hits 290system.l2c.demand_hits::cpu0.inst 385844 # number of demand (read+write) hits 291system.l2c.demand_hits::cpu0.data 214813 # number of demand (read+write) hits 292system.l2c.demand_hits::cpu1.dtb.walker 30512 # number of demand (read+write) hits 293system.l2c.demand_hits::cpu1.itb.walker 5160 # number of demand (read+write) hits 294system.l2c.demand_hits::cpu1.inst 591639 # number of demand (read+write) hits 295system.l2c.demand_hits::cpu1.data 257005 # number of demand (read+write) hits 296system.l2c.demand_hits::total 1510919 # number of demand (read+write) hits 297system.l2c.overall_hits::cpu0.dtb.walker 21699 # number of overall hits 298system.l2c.overall_hits::cpu0.itb.walker 4247 # number of overall hits 299system.l2c.overall_hits::cpu0.inst 385844 # number of overall hits 300system.l2c.overall_hits::cpu0.data 214813 # number of overall hits 301system.l2c.overall_hits::cpu1.dtb.walker 30512 # number of overall hits 302system.l2c.overall_hits::cpu1.itb.walker 5160 # number of overall hits 303system.l2c.overall_hits::cpu1.inst 591639 # number of overall hits 304system.l2c.overall_hits::cpu1.data 257005 # number of overall hits 305system.l2c.overall_hits::total 1510919 # number of overall hits | 275system.l2c.SCUpgradeReq_hits::total 342 # number of SCUpgradeReq hits 276system.l2c.ReadExReq_hits::cpu0.data 48406 # number of ReadExReq hits 277system.l2c.ReadExReq_hits::cpu1.data 58608 # number of ReadExReq hits 278system.l2c.ReadExReq_hits::total 107014 # number of ReadExReq hits 279system.l2c.demand_hits::cpu0.dtb.walker 21930 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu0.itb.walker 4443 # number of demand (read+write) hits 281system.l2c.demand_hits::cpu0.inst 386616 # number of demand (read+write) hits 282system.l2c.demand_hits::cpu0.data 215048 # number of demand (read+write) hits 283system.l2c.demand_hits::cpu1.dtb.walker 30274 # number of demand (read+write) hits 284system.l2c.demand_hits::cpu1.itb.walker 5231 # number of demand (read+write) hits 285system.l2c.demand_hits::cpu1.inst 590416 # number of demand (read+write) hits 286system.l2c.demand_hits::cpu1.data 256459 # number of demand (read+write) hits 287system.l2c.demand_hits::total 1510417 # number of demand (read+write) hits 288system.l2c.overall_hits::cpu0.dtb.walker 21930 # number of overall hits 289system.l2c.overall_hits::cpu0.itb.walker 4443 # number of overall hits 290system.l2c.overall_hits::cpu0.inst 386616 # number of overall hits 291system.l2c.overall_hits::cpu0.data 215048 # number of overall hits 292system.l2c.overall_hits::cpu1.dtb.walker 30274 # number of overall hits 293system.l2c.overall_hits::cpu1.itb.walker 5231 # number of overall hits 294system.l2c.overall_hits::cpu1.inst 590416 # number of overall hits 295system.l2c.overall_hits::cpu1.data 256459 # number of overall hits 296system.l2c.overall_hits::total 1510417 # number of overall hits |
306system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses | 297system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses |
307system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 308system.l2c.ReadReq_misses::cpu0.inst 6268 # number of ReadReq misses 309system.l2c.ReadReq_misses::cpu0.data 6367 # number of ReadReq misses 310system.l2c.ReadReq_misses::cpu1.dtb.walker 20 # number of ReadReq misses 311system.l2c.ReadReq_misses::cpu1.inst 6307 # number of ReadReq misses 312system.l2c.ReadReq_misses::cpu1.data 6294 # number of ReadReq misses 313system.l2c.ReadReq_misses::total 25269 # number of ReadReq misses 314system.l2c.UpgradeReq_misses::cpu0.data 5150 # number of UpgradeReq misses 315system.l2c.UpgradeReq_misses::cpu1.data 3804 # number of UpgradeReq misses 316system.l2c.UpgradeReq_misses::total 8954 # number of UpgradeReq misses 317system.l2c.SCUpgradeReq_misses::cpu0.data 644 # number of SCUpgradeReq misses 318system.l2c.SCUpgradeReq_misses::cpu1.data 418 # number of SCUpgradeReq misses 319system.l2c.SCUpgradeReq_misses::total 1062 # number of SCUpgradeReq misses 320system.l2c.ReadExReq_misses::cpu0.data 63486 # number of ReadExReq misses 321system.l2c.ReadExReq_misses::cpu1.data 76591 # number of ReadExReq misses 322system.l2c.ReadExReq_misses::total 140077 # number of ReadExReq misses | 298system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 299system.l2c.ReadReq_misses::cpu0.inst 6270 # number of ReadReq misses 300system.l2c.ReadReq_misses::cpu0.data 6414 # number of ReadReq misses 301system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses 302system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 303system.l2c.ReadReq_misses::cpu1.inst 6302 # number of ReadReq misses 304system.l2c.ReadReq_misses::cpu1.data 6301 # number of ReadReq misses 305system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses 306system.l2c.UpgradeReq_misses::cpu0.data 5137 # number of UpgradeReq misses 307system.l2c.UpgradeReq_misses::cpu1.data 3774 # number of UpgradeReq misses 308system.l2c.UpgradeReq_misses::total 8911 # number of UpgradeReq misses 309system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses 310system.l2c.SCUpgradeReq_misses::cpu1.data 414 # number of SCUpgradeReq misses 311system.l2c.SCUpgradeReq_misses::total 1055 # number of SCUpgradeReq misses 312system.l2c.ReadExReq_misses::cpu0.data 63277 # number of ReadExReq misses 313system.l2c.ReadExReq_misses::cpu1.data 76923 # number of ReadExReq misses 314system.l2c.ReadExReq_misses::total 140200 # number of ReadExReq misses |
323system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses | 315system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses |
324system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 325system.l2c.demand_misses::cpu0.inst 6268 # number of demand (read+write) misses 326system.l2c.demand_misses::cpu0.data 69853 # number of demand (read+write) misses 327system.l2c.demand_misses::cpu1.dtb.walker 20 # number of demand (read+write) misses 328system.l2c.demand_misses::cpu1.inst 6307 # number of demand (read+write) misses 329system.l2c.demand_misses::cpu1.data 82885 # number of demand (read+write) misses 330system.l2c.demand_misses::total 165346 # number of demand (read+write) misses | 316system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 317system.l2c.demand_misses::cpu0.inst 6270 # number of demand (read+write) misses 318system.l2c.demand_misses::cpu0.data 69691 # number of demand (read+write) misses 319system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses 320system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 321system.l2c.demand_misses::cpu1.inst 6302 # number of demand (read+write) misses 322system.l2c.demand_misses::cpu1.data 83224 # number of demand (read+write) misses 323system.l2c.demand_misses::total 165520 # number of demand (read+write) misses |
331system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses | 324system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses |
332system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 333system.l2c.overall_misses::cpu0.inst 6268 # number of overall misses 334system.l2c.overall_misses::cpu0.data 69853 # number of overall misses 335system.l2c.overall_misses::cpu1.dtb.walker 20 # number of overall misses 336system.l2c.overall_misses::cpu1.inst 6307 # number of overall misses 337system.l2c.overall_misses::cpu1.data 82885 # number of overall misses 338system.l2c.overall_misses::total 165346 # number of overall misses 339system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 727500 # number of ReadReq miss cycles 340system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles 341system.l2c.ReadReq_miss_latency::cpu0.inst 346856000 # number of ReadReq miss cycles 342system.l2c.ReadReq_miss_latency::cpu0.data 362407499 # number of ReadReq miss cycles 343system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1360500 # number of ReadReq miss cycles 344system.l2c.ReadReq_miss_latency::cpu1.inst 380856500 # number of ReadReq miss cycles 345system.l2c.ReadReq_miss_latency::cpu1.data 395446999 # number of ReadReq miss cycles 346system.l2c.ReadReq_miss_latency::total 1487772998 # number of ReadReq miss cycles 347system.l2c.UpgradeReq_miss_latency::cpu0.data 8791989 # number of UpgradeReq miss cycles 348system.l2c.UpgradeReq_miss_latency::cpu1.data 11737000 # number of UpgradeReq miss cycles 349system.l2c.UpgradeReq_miss_latency::total 20528989 # number of UpgradeReq miss cycles 350system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591000 # number of SCUpgradeReq miss cycles 351system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2890499 # number of SCUpgradeReq miss cycles 352system.l2c.SCUpgradeReq_miss_latency::total 3481499 # number of SCUpgradeReq miss cycles 353system.l2c.ReadExReq_miss_latency::cpu0.data 3145264486 # number of ReadExReq miss cycles 354system.l2c.ReadExReq_miss_latency::cpu1.data 4121590993 # number of ReadExReq miss cycles 355system.l2c.ReadExReq_miss_latency::total 7266855479 # number of ReadExReq miss cycles 356system.l2c.demand_miss_latency::cpu0.dtb.walker 727500 # number of demand (read+write) miss cycles 357system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu0.inst 346856000 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::cpu0.data 3507671985 # number of demand (read+write) miss cycles 360system.l2c.demand_miss_latency::cpu1.dtb.walker 1360500 # number of demand (read+write) miss cycles 361system.l2c.demand_miss_latency::cpu1.inst 380856500 # number of demand (read+write) miss cycles 362system.l2c.demand_miss_latency::cpu1.data 4517037992 # number of demand (read+write) miss cycles 363system.l2c.demand_miss_latency::total 8754628477 # number of demand (read+write) miss cycles 364system.l2c.overall_miss_latency::cpu0.dtb.walker 727500 # number of overall miss cycles 365system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles 366system.l2c.overall_miss_latency::cpu0.inst 346856000 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu0.data 3507671985 # number of overall miss cycles 368system.l2c.overall_miss_latency::cpu1.dtb.walker 1360500 # number of overall miss cycles 369system.l2c.overall_miss_latency::cpu1.inst 380856500 # number of overall miss cycles 370system.l2c.overall_miss_latency::cpu1.data 4517037992 # number of overall miss cycles 371system.l2c.overall_miss_latency::total 8754628477 # number of overall miss cycles 372system.l2c.ReadReq_accesses::cpu0.dtb.walker 21710 # number of ReadReq accesses(hits+misses) 373system.l2c.ReadReq_accesses::cpu0.itb.walker 4249 # number of ReadReq accesses(hits+misses) 374system.l2c.ReadReq_accesses::cpu0.inst 392112 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu0.data 173138 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.dtb.walker 30532 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::cpu1.itb.walker 5160 # number of ReadReq accesses(hits+misses) 378system.l2c.ReadReq_accesses::cpu1.inst 597946 # number of ReadReq accesses(hits+misses) 379system.l2c.ReadReq_accesses::cpu1.data 204314 # number of ReadReq accesses(hits+misses) 380system.l2c.ReadReq_accesses::total 1429161 # number of ReadReq accesses(hits+misses) 381system.l2c.Writeback_accesses::writebacks 581178 # number of Writeback accesses(hits+misses) 382system.l2c.Writeback_accesses::total 581178 # number of Writeback accesses(hits+misses) 383system.l2c.UpgradeReq_accesses::cpu0.data 6313 # number of UpgradeReq accesses(hits+misses) 384system.l2c.UpgradeReq_accesses::cpu1.data 4543 # number of UpgradeReq accesses(hits+misses) 385system.l2c.UpgradeReq_accesses::total 10856 # number of UpgradeReq accesses(hits+misses) 386system.l2c.SCUpgradeReq_accesses::cpu0.data 845 # number of SCUpgradeReq accesses(hits+misses) 387system.l2c.SCUpgradeReq_accesses::cpu1.data 561 # number of SCUpgradeReq accesses(hits+misses) 388system.l2c.SCUpgradeReq_accesses::total 1406 # number of SCUpgradeReq accesses(hits+misses) 389system.l2c.ReadExReq_accesses::cpu0.data 111528 # number of ReadExReq accesses(hits+misses) 390system.l2c.ReadExReq_accesses::cpu1.data 135576 # number of ReadExReq accesses(hits+misses) 391system.l2c.ReadExReq_accesses::total 247104 # number of ReadExReq accesses(hits+misses) 392system.l2c.demand_accesses::cpu0.dtb.walker 21710 # number of demand (read+write) accesses 393system.l2c.demand_accesses::cpu0.itb.walker 4249 # number of demand (read+write) accesses 394system.l2c.demand_accesses::cpu0.inst 392112 # number of demand (read+write) accesses 395system.l2c.demand_accesses::cpu0.data 284666 # number of demand (read+write) accesses 396system.l2c.demand_accesses::cpu1.dtb.walker 30532 # number of demand (read+write) accesses 397system.l2c.demand_accesses::cpu1.itb.walker 5160 # number of demand (read+write) accesses 398system.l2c.demand_accesses::cpu1.inst 597946 # number of demand (read+write) accesses 399system.l2c.demand_accesses::cpu1.data 339890 # number of demand (read+write) accesses 400system.l2c.demand_accesses::total 1676265 # number of demand (read+write) accesses 401system.l2c.overall_accesses::cpu0.dtb.walker 21710 # number of overall (read+write) accesses 402system.l2c.overall_accesses::cpu0.itb.walker 4249 # number of overall (read+write) accesses 403system.l2c.overall_accesses::cpu0.inst 392112 # number of overall (read+write) accesses 404system.l2c.overall_accesses::cpu0.data 284666 # number of overall (read+write) accesses 405system.l2c.overall_accesses::cpu1.dtb.walker 30532 # number of overall (read+write) accesses 406system.l2c.overall_accesses::cpu1.itb.walker 5160 # number of overall (read+write) accesses 407system.l2c.overall_accesses::cpu1.inst 597946 # number of overall (read+write) accesses 408system.l2c.overall_accesses::cpu1.data 339890 # number of overall (read+write) accesses 409system.l2c.overall_accesses::total 1676265 # number of overall (read+write) accesses 410system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for ReadReq accesses 411system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000471 # miss rate for ReadReq accesses 412system.l2c.ReadReq_miss_rate::cpu0.inst 0.015985 # miss rate for ReadReq accesses 413system.l2c.ReadReq_miss_rate::cpu0.data 0.036774 # miss rate for ReadReq accesses 414system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for ReadReq accesses 415system.l2c.ReadReq_miss_rate::cpu1.inst 0.010548 # miss rate for ReadReq accesses 416system.l2c.ReadReq_miss_rate::cpu1.data 0.030806 # miss rate for ReadReq accesses 417system.l2c.ReadReq_miss_rate::total 0.017681 # miss rate for ReadReq accesses 418system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815777 # miss rate for UpgradeReq accesses 419system.l2c.UpgradeReq_miss_rate::cpu1.data 0.837332 # miss rate for UpgradeReq accesses 420system.l2c.UpgradeReq_miss_rate::total 0.824797 # miss rate for UpgradeReq accesses 421system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.762130 # miss rate for SCUpgradeReq accesses 422system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.745098 # miss rate for SCUpgradeReq accesses 423system.l2c.SCUpgradeReq_miss_rate::total 0.755334 # miss rate for SCUpgradeReq accesses 424system.l2c.ReadExReq_miss_rate::cpu0.data 0.569238 # miss rate for ReadExReq accesses 425system.l2c.ReadExReq_miss_rate::cpu1.data 0.564930 # miss rate for ReadExReq accesses 426system.l2c.ReadExReq_miss_rate::total 0.566875 # miss rate for ReadExReq accesses 427system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for demand accesses 428system.l2c.demand_miss_rate::cpu0.itb.walker 0.000471 # miss rate for demand accesses 429system.l2c.demand_miss_rate::cpu0.inst 0.015985 # miss rate for demand accesses 430system.l2c.demand_miss_rate::cpu0.data 0.245386 # miss rate for demand accesses 431system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for demand accesses 432system.l2c.demand_miss_rate::cpu1.inst 0.010548 # miss rate for demand accesses 433system.l2c.demand_miss_rate::cpu1.data 0.243858 # miss rate for demand accesses 434system.l2c.demand_miss_rate::total 0.098640 # miss rate for demand accesses 435system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for overall accesses 436system.l2c.overall_miss_rate::cpu0.itb.walker 0.000471 # miss rate for overall accesses 437system.l2c.overall_miss_rate::cpu0.inst 0.015985 # miss rate for overall accesses 438system.l2c.overall_miss_rate::cpu0.data 0.245386 # miss rate for overall accesses 439system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for overall accesses 440system.l2c.overall_miss_rate::cpu1.inst 0.010548 # miss rate for overall accesses 441system.l2c.overall_miss_rate::cpu1.data 0.243858 # miss rate for overall accesses 442system.l2c.overall_miss_rate::total 0.098640 # miss rate for overall accesses 443system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average ReadReq miss latency 444system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency 445system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55337.587747 # average ReadReq miss latency 446system.l2c.ReadReq_avg_miss_latency::cpu0.data 56919.663735 # average ReadReq miss latency 447system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68025 # average ReadReq miss latency 448system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60386.316791 # average ReadReq miss latency 449system.l2c.ReadReq_avg_miss_latency::cpu1.data 62829.202256 # average ReadReq miss latency 450system.l2c.ReadReq_avg_miss_latency::total 58877.399106 # average ReadReq miss latency 451system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1707.182330 # average UpgradeReq miss latency 452system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3085.436383 # average UpgradeReq miss latency 453system.l2c.UpgradeReq_avg_miss_latency::total 2292.717110 # average UpgradeReq miss latency 454system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 917.701863 # average SCUpgradeReq miss latency 455system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6915.069378 # average SCUpgradeReq miss latency 456system.l2c.SCUpgradeReq_avg_miss_latency::total 3278.247646 # average SCUpgradeReq miss latency 457system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49542.646977 # average ReadExReq miss latency 458system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53812.993602 # average ReadExReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::total 51877.577896 # average ReadExReq miss latency 460system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average overall miss latency 461system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency 462system.l2c.demand_avg_miss_latency::cpu0.inst 55337.587747 # average overall miss latency 463system.l2c.demand_avg_miss_latency::cpu0.data 50215.051394 # average overall miss latency 464system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68025 # average overall miss latency 465system.l2c.demand_avg_miss_latency::cpu1.inst 60386.316791 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.data 54497.653279 # average overall miss latency 467system.l2c.demand_avg_miss_latency::total 52947.325469 # average overall miss latency 468system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average overall miss latency 469system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency 470system.l2c.overall_avg_miss_latency::cpu0.inst 55337.587747 # average overall miss latency 471system.l2c.overall_avg_miss_latency::cpu0.data 50215.051394 # average overall miss latency 472system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68025 # average overall miss latency 473system.l2c.overall_avg_miss_latency::cpu1.inst 60386.316791 # average overall miss latency 474system.l2c.overall_avg_miss_latency::cpu1.data 54497.653279 # average overall miss latency 475system.l2c.overall_avg_miss_latency::total 52947.325469 # average overall miss latency | 325system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 326system.l2c.overall_misses::cpu0.inst 6270 # number of overall misses 327system.l2c.overall_misses::cpu0.data 69691 # number of overall misses 328system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses 329system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 330system.l2c.overall_misses::cpu1.inst 6302 # number of overall misses 331system.l2c.overall_misses::cpu1.data 83224 # number of overall misses 332system.l2c.overall_misses::total 165520 # number of overall misses 333system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 728500 # number of ReadReq miss cycles 334system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles 335system.l2c.ReadReq_miss_latency::cpu0.inst 345548000 # number of ReadReq miss cycles 336system.l2c.ReadReq_miss_latency::cpu0.data 371089999 # number of ReadReq miss cycles 337system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1384000 # number of ReadReq miss cycles 338system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles 339system.l2c.ReadReq_miss_latency::cpu1.inst 378000500 # number of ReadReq miss cycles 340system.l2c.ReadReq_miss_latency::cpu1.data 393265500 # number of ReadReq miss cycles 341system.l2c.ReadReq_miss_latency::total 1490340499 # number of ReadReq miss cycles 342system.l2c.UpgradeReq_miss_latency::cpu0.data 8952484 # number of UpgradeReq miss cycles 343system.l2c.UpgradeReq_miss_latency::cpu1.data 11872000 # number of UpgradeReq miss cycles 344system.l2c.UpgradeReq_miss_latency::total 20824484 # number of UpgradeReq miss cycles 345system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles 346system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2820500 # number of SCUpgradeReq miss cycles 347system.l2c.SCUpgradeReq_miss_latency::total 3434500 # number of SCUpgradeReq miss cycles 348system.l2c.ReadExReq_miss_latency::cpu0.data 3142895481 # number of ReadExReq miss cycles 349system.l2c.ReadExReq_miss_latency::cpu1.data 4127198996 # number of ReadExReq miss cycles 350system.l2c.ReadExReq_miss_latency::total 7270094477 # number of ReadExReq miss cycles 351system.l2c.demand_miss_latency::cpu0.dtb.walker 728500 # number of demand (read+write) miss cycles 352system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles 353system.l2c.demand_miss_latency::cpu0.inst 345548000 # number of demand (read+write) miss cycles 354system.l2c.demand_miss_latency::cpu0.data 3513985480 # number of demand (read+write) miss cycles 355system.l2c.demand_miss_latency::cpu1.dtb.walker 1384000 # number of demand (read+write) miss cycles 356system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles 357system.l2c.demand_miss_latency::cpu1.inst 378000500 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu1.data 4520464496 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::total 8760434976 # number of demand (read+write) miss cycles 360system.l2c.overall_miss_latency::cpu0.dtb.walker 728500 # number of overall miss cycles 361system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles 362system.l2c.overall_miss_latency::cpu0.inst 345548000 # number of overall miss cycles 363system.l2c.overall_miss_latency::cpu0.data 3513985480 # number of overall miss cycles 364system.l2c.overall_miss_latency::cpu1.dtb.walker 1384000 # number of overall miss cycles 365system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles 366system.l2c.overall_miss_latency::cpu1.inst 378000500 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu1.data 4520464496 # number of overall miss cycles 368system.l2c.overall_miss_latency::total 8760434976 # number of overall miss cycles 369system.l2c.ReadReq_accesses::cpu0.dtb.walker 21941 # number of ReadReq accesses(hits+misses) 370system.l2c.ReadReq_accesses::cpu0.itb.walker 4447 # number of ReadReq accesses(hits+misses) 371system.l2c.ReadReq_accesses::cpu0.inst 392886 # number of ReadReq accesses(hits+misses) 372system.l2c.ReadReq_accesses::cpu0.data 173056 # number of ReadReq accesses(hits+misses) 373system.l2c.ReadReq_accesses::cpu1.dtb.walker 30291 # number of ReadReq accesses(hits+misses) 374system.l2c.ReadReq_accesses::cpu1.itb.walker 5232 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu1.inst 596718 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.data 204152 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::total 1428723 # number of ReadReq accesses(hits+misses) 378system.l2c.Writeback_accesses::writebacks 581067 # number of Writeback accesses(hits+misses) 379system.l2c.Writeback_accesses::total 581067 # number of Writeback accesses(hits+misses) 380system.l2c.UpgradeReq_accesses::cpu0.data 6367 # number of UpgradeReq accesses(hits+misses) 381system.l2c.UpgradeReq_accesses::cpu1.data 4511 # number of UpgradeReq accesses(hits+misses) 382system.l2c.UpgradeReq_accesses::total 10878 # number of UpgradeReq accesses(hits+misses) 383system.l2c.SCUpgradeReq_accesses::cpu0.data 840 # number of SCUpgradeReq accesses(hits+misses) 384system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses) 385system.l2c.SCUpgradeReq_accesses::total 1397 # number of SCUpgradeReq accesses(hits+misses) 386system.l2c.ReadExReq_accesses::cpu0.data 111683 # number of ReadExReq accesses(hits+misses) 387system.l2c.ReadExReq_accesses::cpu1.data 135531 # number of ReadExReq accesses(hits+misses) 388system.l2c.ReadExReq_accesses::total 247214 # number of ReadExReq accesses(hits+misses) 389system.l2c.demand_accesses::cpu0.dtb.walker 21941 # number of demand (read+write) accesses 390system.l2c.demand_accesses::cpu0.itb.walker 4447 # number of demand (read+write) accesses 391system.l2c.demand_accesses::cpu0.inst 392886 # number of demand (read+write) accesses 392system.l2c.demand_accesses::cpu0.data 284739 # number of demand (read+write) accesses 393system.l2c.demand_accesses::cpu1.dtb.walker 30291 # number of demand (read+write) accesses 394system.l2c.demand_accesses::cpu1.itb.walker 5232 # number of demand (read+write) accesses 395system.l2c.demand_accesses::cpu1.inst 596718 # number of demand (read+write) accesses 396system.l2c.demand_accesses::cpu1.data 339683 # number of demand (read+write) accesses 397system.l2c.demand_accesses::total 1675937 # number of demand (read+write) accesses 398system.l2c.overall_accesses::cpu0.dtb.walker 21941 # number of overall (read+write) accesses 399system.l2c.overall_accesses::cpu0.itb.walker 4447 # number of overall (read+write) accesses 400system.l2c.overall_accesses::cpu0.inst 392886 # number of overall (read+write) accesses 401system.l2c.overall_accesses::cpu0.data 284739 # number of overall (read+write) accesses 402system.l2c.overall_accesses::cpu1.dtb.walker 30291 # number of overall (read+write) accesses 403system.l2c.overall_accesses::cpu1.itb.walker 5232 # number of overall (read+write) accesses 404system.l2c.overall_accesses::cpu1.inst 596718 # number of overall (read+write) accesses 405system.l2c.overall_accesses::cpu1.data 339683 # number of overall (read+write) accesses 406system.l2c.overall_accesses::total 1675937 # number of overall (read+write) accesses 407system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for ReadReq accesses 408system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000899 # miss rate for ReadReq accesses 409system.l2c.ReadReq_miss_rate::cpu0.inst 0.015959 # miss rate for ReadReq accesses 410system.l2c.ReadReq_miss_rate::cpu0.data 0.037063 # miss rate for ReadReq accesses 411system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for ReadReq accesses 412system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses 413system.l2c.ReadReq_miss_rate::cpu1.inst 0.010561 # miss rate for ReadReq accesses 414system.l2c.ReadReq_miss_rate::cpu1.data 0.030864 # miss rate for ReadReq accesses 415system.l2c.ReadReq_miss_rate::total 0.017722 # miss rate for ReadReq accesses 416system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806816 # miss rate for UpgradeReq accesses 417system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836622 # miss rate for UpgradeReq accesses 418system.l2c.UpgradeReq_miss_rate::total 0.819176 # miss rate for UpgradeReq accesses 419system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.763095 # miss rate for SCUpgradeReq accesses 420system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.743268 # miss rate for SCUpgradeReq accesses 421system.l2c.SCUpgradeReq_miss_rate::total 0.755190 # miss rate for SCUpgradeReq accesses 422system.l2c.ReadExReq_miss_rate::cpu0.data 0.566577 # miss rate for ReadExReq accesses 423system.l2c.ReadExReq_miss_rate::cpu1.data 0.567568 # miss rate for ReadExReq accesses 424system.l2c.ReadExReq_miss_rate::total 0.567120 # miss rate for ReadExReq accesses 425system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for demand accesses 426system.l2c.demand_miss_rate::cpu0.itb.walker 0.000899 # miss rate for demand accesses 427system.l2c.demand_miss_rate::cpu0.inst 0.015959 # miss rate for demand accesses 428system.l2c.demand_miss_rate::cpu0.data 0.244754 # miss rate for demand accesses 429system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for demand accesses 430system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses 431system.l2c.demand_miss_rate::cpu1.inst 0.010561 # miss rate for demand accesses 432system.l2c.demand_miss_rate::cpu1.data 0.245005 # miss rate for demand accesses 433system.l2c.demand_miss_rate::total 0.098763 # miss rate for demand accesses 434system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for overall accesses 435system.l2c.overall_miss_rate::cpu0.itb.walker 0.000899 # miss rate for overall accesses 436system.l2c.overall_miss_rate::cpu0.inst 0.015959 # miss rate for overall accesses 437system.l2c.overall_miss_rate::cpu0.data 0.244754 # miss rate for overall accesses 438system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for overall accesses 439system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses 440system.l2c.overall_miss_rate::cpu1.inst 0.010561 # miss rate for overall accesses 441system.l2c.overall_miss_rate::cpu1.data 0.245005 # miss rate for overall accesses 442system.l2c.overall_miss_rate::total 0.098763 # miss rate for overall accesses 443system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average ReadReq miss latency 444system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency 445system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55111.323764 # average ReadReq miss latency 446system.l2c.ReadReq_avg_miss_latency::cpu0.data 57856.251793 # average ReadReq miss latency 447system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average ReadReq miss latency 448system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency 449system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59981.037766 # average ReadReq miss latency 450system.l2c.ReadReq_avg_miss_latency::cpu1.data 62413.188383 # average ReadReq miss latency 451system.l2c.ReadReq_avg_miss_latency::total 58860.209281 # average ReadReq miss latency 452system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1742.745571 # average UpgradeReq miss latency 453system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3145.733969 # average UpgradeReq miss latency 454system.l2c.UpgradeReq_avg_miss_latency::total 2336.941308 # average UpgradeReq miss latency 455system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 957.878315 # average SCUpgradeReq miss latency 456system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6812.801932 # average SCUpgradeReq miss latency 457system.l2c.SCUpgradeReq_avg_miss_latency::total 3255.450237 # average SCUpgradeReq miss latency 458system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49668.844620 # average ReadExReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53653.640602 # average ReadExReq miss latency 460system.l2c.ReadExReq_avg_miss_latency::total 51855.167454 # average ReadExReq miss latency 461system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency 462system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency 463system.l2c.demand_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency 464system.l2c.demand_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency 465system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency 467system.l2c.demand_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency 468system.l2c.demand_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency 469system.l2c.demand_avg_miss_latency::total 52926.745868 # average overall miss latency 470system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency 471system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency 472system.l2c.overall_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency 473system.l2c.overall_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency 474system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency 475system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency 476system.l2c.overall_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency 477system.l2c.overall_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency 478system.l2c.overall_avg_miss_latency::total 52926.745868 # average overall miss latency |
476system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 477system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 478system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 479system.l2c.blocked::no_targets 0 # number of cycles access was blocked 480system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 481system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 482system.l2c.fast_writes 0 # number of fast writes performed 483system.l2c.cache_copies 0 # number of cache copies performed | 479system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 480system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 481system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 482system.l2c.blocked::no_targets 0 # number of cycles access was blocked 483system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 484system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 485system.l2c.fast_writes 0 # number of fast writes performed 486system.l2c.cache_copies 0 # number of cache copies performed |
484system.l2c.writebacks::writebacks 66554 # number of writebacks 485system.l2c.writebacks::total 66554 # number of writebacks | 487system.l2c.writebacks::writebacks 66701 # number of writebacks 488system.l2c.writebacks::total 66701 # number of writebacks |
486system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits | 489system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits |
487system.l2c.ReadReq_mshr_hits::cpu0.data 36 # number of ReadReq MSHR hits 488system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits | 490system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits 491system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits |
489system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits 490system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 491system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits | 492system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits 493system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 494system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits |
492system.l2c.demand_mshr_hits::cpu0.data 36 # number of demand (read+write) MSHR hits 493system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits | 495system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits 496system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits |
494system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits 495system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 496system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits | 497system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits 498system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 499system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits |
497system.l2c.overall_mshr_hits::cpu0.data 36 # number of overall MSHR hits 498system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits | 500system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits 501system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits |
499system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 500system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits 501system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses | 502system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 503system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits 504system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses |
502system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 503system.l2c.ReadReq_mshr_misses::cpu0.inst 6264 # number of ReadReq MSHR misses 504system.l2c.ReadReq_mshr_misses::cpu0.data 6331 # number of ReadReq MSHR misses 505system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 20 # number of ReadReq MSHR misses 506system.l2c.ReadReq_mshr_misses::cpu1.inst 6299 # number of ReadReq MSHR misses 507system.l2c.ReadReq_mshr_misses::cpu1.data 6270 # number of ReadReq MSHR misses 508system.l2c.ReadReq_mshr_misses::total 25197 # number of ReadReq MSHR misses 509system.l2c.UpgradeReq_mshr_misses::cpu0.data 5150 # number of UpgradeReq MSHR misses 510system.l2c.UpgradeReq_mshr_misses::cpu1.data 3804 # number of UpgradeReq MSHR misses 511system.l2c.UpgradeReq_mshr_misses::total 8954 # number of UpgradeReq MSHR misses 512system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 644 # number of SCUpgradeReq MSHR misses 513system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 418 # number of SCUpgradeReq MSHR misses 514system.l2c.SCUpgradeReq_mshr_misses::total 1062 # number of SCUpgradeReq MSHR misses 515system.l2c.ReadExReq_mshr_misses::cpu0.data 63486 # number of ReadExReq MSHR misses 516system.l2c.ReadExReq_mshr_misses::cpu1.data 76591 # number of ReadExReq MSHR misses 517system.l2c.ReadExReq_mshr_misses::total 140077 # number of ReadExReq MSHR misses | 505system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses 506system.l2c.ReadReq_mshr_misses::cpu0.inst 6266 # number of ReadReq MSHR misses 507system.l2c.ReadReq_mshr_misses::cpu0.data 6377 # number of ReadReq MSHR misses 508system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses 509system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 510system.l2c.ReadReq_mshr_misses::cpu1.inst 6295 # number of ReadReq MSHR misses 511system.l2c.ReadReq_mshr_misses::cpu1.data 6277 # number of ReadReq MSHR misses 512system.l2c.ReadReq_mshr_misses::total 25248 # number of ReadReq MSHR misses 513system.l2c.UpgradeReq_mshr_misses::cpu0.data 5137 # number of UpgradeReq MSHR misses 514system.l2c.UpgradeReq_mshr_misses::cpu1.data 3774 # number of UpgradeReq MSHR misses 515system.l2c.UpgradeReq_mshr_misses::total 8911 # number of UpgradeReq MSHR misses 516system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 641 # number of SCUpgradeReq MSHR misses 517system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 414 # number of SCUpgradeReq MSHR misses 518system.l2c.SCUpgradeReq_mshr_misses::total 1055 # number of SCUpgradeReq MSHR misses 519system.l2c.ReadExReq_mshr_misses::cpu0.data 63277 # number of ReadExReq MSHR misses 520system.l2c.ReadExReq_mshr_misses::cpu1.data 76923 # number of ReadExReq MSHR misses 521system.l2c.ReadExReq_mshr_misses::total 140200 # number of ReadExReq MSHR misses |
518system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses | 522system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses |
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526system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses | 531system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses |
527system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 528system.l2c.overall_mshr_misses::cpu0.inst 6264 # number of overall MSHR misses 529system.l2c.overall_mshr_misses::cpu0.data 69817 # number of overall MSHR misses 530system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 # number of overall MSHR misses 531system.l2c.overall_mshr_misses::cpu1.inst 6299 # number of overall MSHR misses 532system.l2c.overall_mshr_misses::cpu1.data 82861 # number of overall MSHR misses 533system.l2c.overall_mshr_misses::total 165274 # number of overall MSHR misses 534system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 591272 # number of ReadReq MSHR miss cycles 535system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93252 # number of ReadReq MSHR miss cycles 536system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 268680120 # number of ReadReq MSHR miss cycles 537system.l2c.ReadReq_mshr_miss_latency::cpu0.data 282241162 # number of ReadReq MSHR miss cycles 538system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1109289 # 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mshr miss rate for overall accesses 618system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses 619system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses 620system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses 621system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses 622system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses 623system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses 624system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses 625system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency 626system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency 627system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency 628system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency 629system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency 630system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency 631system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency 632system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency 633system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency 634system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency 635system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency 636system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency 637system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency 638system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency 639system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency 640system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency 641system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency 642system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency 643system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency 644system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency 645system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency 646system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency 647system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency 648system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency 649system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency 650system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency 651system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency 652system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency 653system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency 654system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency 655system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency 656system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency 657system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency 658system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency 659system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency 660system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency |
646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 648system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 649system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 650system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 651system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 652system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 653system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 658system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 659system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 660system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 661system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 662system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 663system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 664system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 665system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 661system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 662system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 663system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 664system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 665system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 666system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 667system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 668system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 673system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 674system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 676system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 677system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 678system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 679system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 680system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
666system.cpu0.branchPred.lookups 5998436 # Number of BP lookups 667system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted 668system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect 669system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups 670system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits | 681system.cpu0.branchPred.lookups 6001263 # Number of BP lookups 682system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted 683system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect 684system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups 685system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits |
671system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 686system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
672system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage 673system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target. 674system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions. | 687system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage 688system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. 689system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. |
675system.cpu0.dtb.inst_hits 0 # ITB inst hits 676system.cpu0.dtb.inst_misses 0 # ITB inst misses | 690system.cpu0.dtb.inst_hits 0 # ITB inst hits 691system.cpu0.dtb.inst_misses 0 # ITB inst misses |
677system.cpu0.dtb.read_hits 8902974 # DTB read hits 678system.cpu0.dtb.read_misses 28685 # DTB read misses 679system.cpu0.dtb.write_hits 5134917 # DTB write hits 680system.cpu0.dtb.write_misses 5599 # DTB write misses | 692system.cpu0.dtb.read_hits 8907872 # DTB read hits 693system.cpu0.dtb.read_misses 28815 # DTB read misses 694system.cpu0.dtb.write_hits 5138143 # DTB write hits 695system.cpu0.dtb.write_misses 5606 # DTB write misses |
681system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 682system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 683system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 684system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 685system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB | 696system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 697system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 698system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 699system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 700system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB |
686system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions 687system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch | 701system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions 702system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch |
688system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 703system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
689system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions 690system.cpu0.dtb.read_accesses 8931659 # DTB read accesses 691system.cpu0.dtb.write_accesses 5140516 # DTB write accesses | 704system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions 705system.cpu0.dtb.read_accesses 8936687 # DTB read accesses 706system.cpu0.dtb.write_accesses 5143749 # DTB write accesses |
692system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 707system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
693system.cpu0.dtb.hits 14037891 # DTB hits 694system.cpu0.dtb.misses 34284 # DTB misses 695system.cpu0.dtb.accesses 14072175 # DTB accesses 696system.cpu0.itb.inst_hits 4215172 # ITB inst hits 697system.cpu0.itb.inst_misses 5141 # ITB inst misses | 708system.cpu0.dtb.hits 14046015 # DTB hits 709system.cpu0.dtb.misses 34421 # DTB misses 710system.cpu0.dtb.accesses 14080436 # DTB accesses 711system.cpu0.itb.inst_hits 4220167 # ITB inst hits 712system.cpu0.itb.inst_misses 5223 # ITB inst misses |
698system.cpu0.itb.read_hits 0 # DTB read hits 699system.cpu0.itb.read_misses 0 # DTB read misses 700system.cpu0.itb.write_hits 0 # DTB write hits 701system.cpu0.itb.write_misses 0 # DTB write misses 702system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 703system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 704system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 705system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 713system.cpu0.itb.read_hits 0 # DTB read hits 714system.cpu0.itb.read_misses 0 # DTB read misses 715system.cpu0.itb.write_hits 0 # DTB write hits 716system.cpu0.itb.write_misses 0 # DTB write misses 717system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 718system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 719system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 720system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
706system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB | 721system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB |
707system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 708system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 709system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 722system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 723system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 724system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
710system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions | 725system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions |
711system.cpu0.itb.read_accesses 0 # DTB read accesses 712system.cpu0.itb.write_accesses 0 # DTB write accesses | 726system.cpu0.itb.read_accesses 0 # DTB read accesses 727system.cpu0.itb.write_accesses 0 # DTB write accesses |
713system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses 714system.cpu0.itb.hits 4215172 # DTB hits 715system.cpu0.itb.misses 5141 # DTB misses 716system.cpu0.itb.accesses 4220313 # DTB accesses 717system.cpu0.numCycles 67779631 # number of cpu cycles simulated | 728system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses 729system.cpu0.itb.hits 4220167 # DTB hits 730system.cpu0.itb.misses 5223 # DTB misses 731system.cpu0.itb.accesses 4225390 # DTB accesses 732system.cpu0.numCycles 67827032 # number of cpu cycles simulated |
718system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 719system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 733system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 734system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
720system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss 721system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed 722system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered 723system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken 724system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked 725system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing 726system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb 727system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked 728system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 729system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps 730system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions 731system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR 732system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched 733system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed 734system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed 735system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total) 736system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total) 737system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total) | 735system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss 736system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed 737system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered 738system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken 739system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked 740system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing 741system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb 742system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked 743system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 744system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps 745system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions 746system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR 747system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched 748system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed 749system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed 750system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) 751system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) 752system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) |
738system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 753system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
739system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total) 740system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total) 741system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total) 742system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total) 743system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total) 744system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total) 745system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total) 746system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total) 747system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total) | 754system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) 755system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) 756system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) 757system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) 758system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) 759system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) 760system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) 761system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) 762system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) |
748system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 749system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 750system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 763system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 764system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 765system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
751system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total) 752system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle 753system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle 754system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle 755system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked 756system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running 757system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking 758system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing 759system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch 760system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction 761system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode 762system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode 763system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing 764system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle 765system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking 766system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst 767system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running 768system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking 769system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename 770system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full 771system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full 772system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full 773system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers 774system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed 775system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made 776system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups 777system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups 778system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed 779system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing 780system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed 781system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed 782system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer 783system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit. 784system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit. 785system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads. 786system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores. 787system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec) 788system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ 789system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued 790system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued 791system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling 792system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph 793system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed 794system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle 795system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle 796system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle | 766system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) 767system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle 768system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle 769system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle 770system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked 771system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running 772system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking 773system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing 774system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch 775system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction 776system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode 777system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode 778system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing 779system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle 780system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking 781system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst 782system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running 783system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking 784system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename 785system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full 786system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full 787system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full 788system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers 789system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed 790system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made 791system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups 792system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups 793system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed 794system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing 795system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed 796system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed 797system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer 798system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. 799system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. 800system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. 801system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. 802system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) 803system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ 804system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued 805system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued 806system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling 807system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph 808system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed 809system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle 810system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle 811system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle |
797system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 812system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
798system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle 799system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle 800system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle 801system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle 802system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle 803system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle 804system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle 805system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle 806system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle | 813system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle 814system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle 815system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle 816system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle 817system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle 818system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle 819system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle 820system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle 821system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle |
807system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 808system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 809system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 822system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 823system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 824system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
810system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle | 825system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle |
811system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 826system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
812system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available 813system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available 814system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available 815system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available 816system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available 817system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available 818system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available 819system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available 820system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available 821system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available 822system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available 823system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available 824system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available 825system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available 826system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available 827system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available 828system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available 829system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available 830system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available 831system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available 832system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available 833system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available 834system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available 835system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available 836system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available 841system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available 842system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available | 827system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available 828system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available 829system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available 830system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available 831system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available 832system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available 833system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available 834system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available 835system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available 836system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available 837system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available 838system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available 839system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available 840system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available 841system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available 842system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available 843system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available 844system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available 845system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available 846system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available 847system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available 848system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available 849system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available 850system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available 851system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available 852system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available 853system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available 854system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available 855system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available 856system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available 857system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available |
843system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 844system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 858system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 859system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
845system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued 846system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued 847system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued | 860system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued 861system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued 862system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued |
848system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued 849system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued 850system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued 851system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued 852system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued 853system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued 854system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued 855system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 867system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued 868system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued 869system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued 870system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued 871system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued 872system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 873system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued 874system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued | 863system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued 864system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued 865system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued 866system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued 867system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued 868system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued 869system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued 870system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 882system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued 883system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued 884system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued 885system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued 886system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued 887system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 888system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued 889system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued |
875system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued 876system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued | 890system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued 891system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued |
877system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 878system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 892system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 893system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
879system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued 880system.cpu0.iq.rate 0.549060 # Inst issue rate 881system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested 882system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst) 883system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads 884system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes 885system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses 886system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads 887system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes 888system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses 889system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses 890system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses 891system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores | 894system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued 895system.cpu0.iq.rate 0.549010 # Inst issue rate 896system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested 897system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) 898system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads 899system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes 900system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses 901system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads 902system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes 903system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses 904system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses 905system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses 906system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores |
892system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 907system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
893system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed 894system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed 895system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations 896system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed | 908system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed 909system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed 910system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations 911system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed |
897system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 898system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 912system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 913system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
899system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled 900system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked | 914system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled 915system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked |
901system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 916system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
902system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing 903system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking 904system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking 905system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ 906system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch 907system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions 908system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions 909system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions 910system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall 911system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall 912system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations 913system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly 914system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly 915system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute 916system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions 917system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed 918system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute | 917system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing 918system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking 919system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking 920system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ 921system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch 922system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions 923system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions 924system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions 925system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall 926system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall 927system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations 928system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly 929system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly 930system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute 931system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions 932system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed 933system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute |
919system.cpu0.iew.exec_swp 0 # number of swp insts executed | 934system.cpu0.iew.exec_swp 0 # number of swp insts executed |
920system.cpu0.iew.exec_nop 118422 # number of nop insts executed 921system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed 922system.cpu0.iew.exec_branches 4852888 # Number of branches executed 923system.cpu0.iew.exec_stores 5394475 # Number of stores executed 924system.cpu0.iew.exec_rate 0.543552 # Inst execution rate 925system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit 926system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back 927system.cpu0.iew.wb_producers 18273947 # num instructions producing a value 928system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value | 935system.cpu0.iew.exec_nop 118689 # number of nop insts executed 936system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed 937system.cpu0.iew.exec_branches 4854206 # Number of branches executed 938system.cpu0.iew.exec_stores 5397839 # Number of stores executed 939system.cpu0.iew.exec_rate 0.543462 # Inst execution rate 940system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit 941system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back 942system.cpu0.iew.wb_producers 18281082 # num instructions producing a value 943system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value |
929system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 944system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
930system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle 931system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back | 945system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle 946system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back |
932system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 947system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
933system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit 934system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards 935system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted 936system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle 937system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle 938system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle | 948system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit 949system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards 950system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted 951system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle 952system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle 953system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle |
939system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 954system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
940system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle 941system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle 942system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle 943system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle 944system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle 945system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle 946system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle 947system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle 948system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle | 955system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle 956system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle 957system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle 958system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle 959system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle 960system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle 961system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle 962system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle 963system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle |
949system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 950system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 951system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 964system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 965system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 966system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
952system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle 953system.cpu0.commit.committedInsts 23670531 # Number of instructions committed 954system.cpu0.commit.committedOps 31269562 # Number of ops (including micro ops) committed | 967system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle 968system.cpu0.commit.committedInsts 23679748 # Number of instructions committed 969system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed |
955system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 970system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
956system.cpu0.commit.refs 11418468 # Number of memory references committed 957system.cpu0.commit.loads 6271892 # Number of loads committed 958system.cpu0.commit.membars 229609 # Number of memory barriers committed 959system.cpu0.commit.branches 4243643 # Number of branches committed | 971system.cpu0.commit.refs 11426897 # Number of memory references committed 972system.cpu0.commit.loads 6276420 # Number of loads committed 973system.cpu0.commit.membars 229667 # Number of memory barriers committed 974system.cpu0.commit.branches 4245051 # Number of branches committed |
960system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. | 975system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. |
961system.cpu0.commit.int_insts 27627358 # Number of committed integer instructions. 962system.cpu0.commit.function_calls 489165 # Number of function calls committed. 963system.cpu0.commit.bw_lim_events 1149237 # number cycles where commit BW limit reached | 976system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. 977system.cpu0.commit.function_calls 489354 # Number of function calls committed. 978system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached |
964system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 979system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
965system.cpu0.rob.rob_reads 75500320 # The number of ROB reads 966system.cpu0.rob.rob_writes 75691570 # The number of ROB writes 967system.cpu0.timesIdled 360084 # Number of times that the entire CPU went into an idle state and unscheduled itself 968system.cpu0.idleCycles 26658070 # Total number of cycles that the CPU has spent unscheduled due to idling 969system.cpu0.quiesceCycles 2138053443 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 970system.cpu0.committedInsts 23589789 # Number of Instructions Simulated 971system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated 972system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated 973system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction 974system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads 975system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle 976system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads 977system.cpu0.int_regfile_reads 171728285 # number of integer regfile reads 978system.cpu0.int_regfile_writes 34072180 # number of integer regfile writes 979system.cpu0.fp_regfile_reads 3295 # number of floating regfile reads | 980system.cpu0.rob.rob_reads 75566033 # The number of ROB reads 981system.cpu0.rob.rob_writes 75750322 # The number of ROB writes 982system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself 983system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling 984system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 985system.cpu0.committedInsts 23599006 # Number of Instructions Simulated 986system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated 987system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated 988system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction 989system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads 990system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle 991system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads 992system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads 993system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes 994system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads |
980system.cpu0.fp_regfile_writes 900 # number of floating regfile writes | 995system.cpu0.fp_regfile_writes 900 # number of floating regfile writes |
981system.cpu0.misc_regfile_reads 12998314 # number of misc regfile reads 982system.cpu0.misc_regfile_writes 450987 # number of misc regfile writes 983system.cpu0.icache.replacements 392135 # number of replacements 984system.cpu0.icache.tagsinuse 511.076170 # Cycle average of tags in use 985system.cpu0.icache.total_refs 3790159 # Total number of references to valid blocks. 986system.cpu0.icache.sampled_refs 392647 # Sample count of references to valid blocks. 987system.cpu0.icache.avg_refs 9.652841 # Average number of references to valid blocks. | 996system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads 997system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes 998system.cpu0.icache.replacements 392871 # number of replacements 999system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use 1000system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. 1001system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. 1002system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. |
988system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. | 1003system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. |
989system.cpu0.icache.occ_blocks::cpu0.inst 511.076170 # Average occupied blocks per requestor | 1004system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor |
990system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy 991system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy | 1005system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy 1006system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy |
992system.cpu0.icache.ReadReq_hits::cpu0.inst 3790159 # number of ReadReq hits 993system.cpu0.icache.ReadReq_hits::total 3790159 # number of ReadReq hits 994system.cpu0.icache.demand_hits::cpu0.inst 3790159 # number of demand (read+write) hits 995system.cpu0.icache.demand_hits::total 3790159 # number of demand (read+write) hits 996system.cpu0.icache.overall_hits::cpu0.inst 3790159 # number of overall hits 997system.cpu0.icache.overall_hits::total 3790159 # number of overall hits 998system.cpu0.icache.ReadReq_misses::cpu0.inst 423214 # number of ReadReq misses 999system.cpu0.icache.ReadReq_misses::total 423214 # number of ReadReq misses 1000system.cpu0.icache.demand_misses::cpu0.inst 423214 # number of demand (read+write) misses 1001system.cpu0.icache.demand_misses::total 423214 # number of demand (read+write) misses 1002system.cpu0.icache.overall_misses::cpu0.inst 423214 # number of overall misses 1003system.cpu0.icache.overall_misses::total 423214 # number of overall misses 1004system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5793685997 # number of ReadReq miss cycles 1005system.cpu0.icache.ReadReq_miss_latency::total 5793685997 # number of ReadReq miss cycles 1006system.cpu0.icache.demand_miss_latency::cpu0.inst 5793685997 # number of demand (read+write) miss cycles 1007system.cpu0.icache.demand_miss_latency::total 5793685997 # number of demand (read+write) miss cycles 1008system.cpu0.icache.overall_miss_latency::cpu0.inst 5793685997 # number of overall miss cycles 1009system.cpu0.icache.overall_miss_latency::total 5793685997 # number of overall miss cycles 1010system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213373 # number of ReadReq accesses(hits+misses) 1011system.cpu0.icache.ReadReq_accesses::total 4213373 # number of ReadReq accesses(hits+misses) 1012system.cpu0.icache.demand_accesses::cpu0.inst 4213373 # number of demand (read+write) accesses 1013system.cpu0.icache.demand_accesses::total 4213373 # number of demand (read+write) accesses 1014system.cpu0.icache.overall_accesses::cpu0.inst 4213373 # number of overall (read+write) accesses 1015system.cpu0.icache.overall_accesses::total 4213373 # number of overall (read+write) accesses 1016system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100445 # miss rate for ReadReq accesses 1017system.cpu0.icache.ReadReq_miss_rate::total 0.100445 # miss rate for ReadReq accesses 1018system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100445 # miss rate for demand accesses 1019system.cpu0.icache.demand_miss_rate::total 0.100445 # miss rate for demand accesses 1020system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100445 # miss rate for overall accesses 1021system.cpu0.icache.overall_miss_rate::total 0.100445 # miss rate for overall accesses 1022system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429 # average ReadReq miss latency 1023system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429 # average ReadReq miss latency 1024system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency 1025system.cpu0.icache.demand_avg_miss_latency::total 13689.731429 # average overall miss latency 1026system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency 1027system.cpu0.icache.overall_avg_miss_latency::total 13689.731429 # average overall miss latency 1028system.cpu0.icache.blocked_cycles::no_mshrs 2401 # number of cycles access was blocked | 1007system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits 1008system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits 1009system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits 1010system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits 1011system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits 1012system.cpu0.icache.overall_hits::total 3794104 # number of overall hits 1013system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses 1014system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses 1015system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses 1016system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses 1017system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses 1018system.cpu0.icache.overall_misses::total 424196 # number of overall misses 1019system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles 1020system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles 1021system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles 1022system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles 1023system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles 1024system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles 1025system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) 1026system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) 1027system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses 1028system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses 1029system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses 1030system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses 1031system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses 1032system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses 1033system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses 1034system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses 1035system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses 1036system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses 1037system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency 1038system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency 1039system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency 1040system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency 1041system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency 1042system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency 1043system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked |
1029system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1044system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1030system.cpu0.icache.blocked::no_mshrs 146 # number of cycles access was blocked | 1045system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked |
1031system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 1046system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
1032system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.445205 # average number of cycles each access was blocked | 1047system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked |
1033system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1034system.cpu0.icache.fast_writes 0 # number of fast writes performed 1035system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1048system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu0.icache.fast_writes 0 # number of fast writes performed 1050system.cpu0.icache.cache_copies 0 # number of cache copies performed |
1036system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30547 # number of ReadReq MSHR hits 1037system.cpu0.icache.ReadReq_mshr_hits::total 30547 # number of ReadReq MSHR hits 1038system.cpu0.icache.demand_mshr_hits::cpu0.inst 30547 # number of demand (read+write) MSHR hits 1039system.cpu0.icache.demand_mshr_hits::total 30547 # number of demand (read+write) MSHR hits 1040system.cpu0.icache.overall_mshr_hits::cpu0.inst 30547 # number of overall MSHR hits 1041system.cpu0.icache.overall_mshr_hits::total 30547 # number of overall MSHR hits 1042system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392667 # number of ReadReq MSHR misses 1043system.cpu0.icache.ReadReq_mshr_misses::total 392667 # number of ReadReq MSHR misses 1044system.cpu0.icache.demand_mshr_misses::cpu0.inst 392667 # number of demand (read+write) MSHR misses 1045system.cpu0.icache.demand_mshr_misses::total 392667 # number of demand (read+write) MSHR misses 1046system.cpu0.icache.overall_mshr_misses::cpu0.inst 392667 # number of overall MSHR misses 1047system.cpu0.icache.overall_mshr_misses::total 392667 # number of overall MSHR misses 1048system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4739152997 # number of ReadReq MSHR miss cycles 1049system.cpu0.icache.ReadReq_mshr_miss_latency::total 4739152997 # number of ReadReq MSHR miss cycles 1050system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4739152997 # number of demand (read+write) MSHR miss cycles 1051system.cpu0.icache.demand_mshr_miss_latency::total 4739152997 # number of demand (read+write) MSHR miss cycles 1052system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4739152997 # number of overall MSHR miss cycles 1053system.cpu0.icache.overall_mshr_miss_latency::total 4739152997 # number of overall MSHR miss cycles | 1051system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits 1052system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits 1053system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits 1054system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits 1055system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits 1056system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits 1057system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses 1058system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses 1059system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses 1060system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses 1061system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses 1062system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses 1063system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles 1064system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles 1065system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles 1066system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles 1067system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles 1068system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles |
1054system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles 1055system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles 1056system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles 1057system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles | 1069system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles 1070system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles 1071system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles 1072system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles |
1058system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for ReadReq accesses 1059system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093195 # mshr miss rate for ReadReq accesses 1060system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for demand accesses 1061system.cpu0.icache.demand_mshr_miss_rate::total 0.093195 # mshr miss rate for demand accesses 1062system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for overall accesses 1063system.cpu0.icache.overall_mshr_miss_rate::total 0.093195 # mshr miss rate for overall accesses 1064system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average ReadReq mshr miss latency 1065system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002 # average ReadReq mshr miss latency 1066system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency 1067system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency 1068system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency 1069system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency | 1073system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses 1074system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses 1075system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses 1076system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses 1077system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses 1078system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses 1079system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency 1080system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency 1081system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency 1082system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency 1083system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency 1084system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency |
1070system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1071system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1072system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1073system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1074system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1085system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1086system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1087system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1088system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1089system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
1075system.cpu0.dcache.replacements 276137 # number of replacements 1076system.cpu0.dcache.tagsinuse 461.136878 # Cycle average of tags in use 1077system.cpu0.dcache.total_refs 9254727 # Total number of references to valid blocks. 1078system.cpu0.dcache.sampled_refs 276649 # Sample count of references to valid blocks. 1079system.cpu0.dcache.avg_refs 33.452957 # Average number of references to valid blocks. 1080system.cpu0.dcache.warmup_cycle 43495000 # Cycle when the warmup percentage was hit. 1081system.cpu0.dcache.occ_blocks::cpu0.data 461.136878 # Average occupied blocks per requestor 1082system.cpu0.dcache.occ_percent::cpu0.data 0.900658 # Average percentage of cache occupancy 1083system.cpu0.dcache.occ_percent::total 0.900658 # Average percentage of cache occupancy 1084system.cpu0.dcache.ReadReq_hits::cpu0.data 5777010 # number of ReadReq hits 1085system.cpu0.dcache.ReadReq_hits::total 5777010 # number of ReadReq hits 1086system.cpu0.dcache.WriteReq_hits::cpu0.data 3157960 # number of WriteReq hits 1087system.cpu0.dcache.WriteReq_hits::total 3157960 # number of WriteReq hits 1088system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139054 # number of LoadLockedReq hits 1089system.cpu0.dcache.LoadLockedReq_hits::total 139054 # number of LoadLockedReq hits 1090system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137010 # number of StoreCondReq hits 1091system.cpu0.dcache.StoreCondReq_hits::total 137010 # number of StoreCondReq hits 1092system.cpu0.dcache.demand_hits::cpu0.data 8934970 # number of demand (read+write) hits 1093system.cpu0.dcache.demand_hits::total 8934970 # number of demand (read+write) hits 1094system.cpu0.dcache.overall_hits::cpu0.data 8934970 # number of overall hits 1095system.cpu0.dcache.overall_hits::total 8934970 # number of overall hits 1096system.cpu0.dcache.ReadReq_misses::cpu0.data 392909 # number of ReadReq misses 1097system.cpu0.dcache.ReadReq_misses::total 392909 # number of ReadReq misses 1098system.cpu0.dcache.WriteReq_misses::cpu0.data 1581686 # number of WriteReq misses 1099system.cpu0.dcache.WriteReq_misses::total 1581686 # number of WriteReq misses 1100system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8773 # number of LoadLockedReq misses 1101system.cpu0.dcache.LoadLockedReq_misses::total 8773 # number of LoadLockedReq misses 1102system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7509 # number of StoreCondReq misses 1103system.cpu0.dcache.StoreCondReq_misses::total 7509 # number of StoreCondReq misses 1104system.cpu0.dcache.demand_misses::cpu0.data 1974595 # number of demand (read+write) misses 1105system.cpu0.dcache.demand_misses::total 1974595 # number of demand (read+write) misses 1106system.cpu0.dcache.overall_misses::cpu0.data 1974595 # number of overall misses 1107system.cpu0.dcache.overall_misses::total 1974595 # number of overall misses 1108system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5473319500 # number of ReadReq miss cycles 1109system.cpu0.dcache.ReadReq_miss_latency::total 5473319500 # number of ReadReq miss cycles 1110system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60618366371 # number of WriteReq miss cycles 1111system.cpu0.dcache.WriteReq_miss_latency::total 60618366371 # number of WriteReq miss cycles 1112system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87499000 # number of LoadLockedReq miss cycles 1113system.cpu0.dcache.LoadLockedReq_miss_latency::total 87499000 # number of LoadLockedReq miss cycles 1114system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46786000 # number of StoreCondReq miss cycles 1115system.cpu0.dcache.StoreCondReq_miss_latency::total 46786000 # number of StoreCondReq miss cycles 1116system.cpu0.dcache.demand_miss_latency::cpu0.data 66091685871 # number of demand (read+write) miss cycles 1117system.cpu0.dcache.demand_miss_latency::total 66091685871 # number of demand (read+write) miss cycles 1118system.cpu0.dcache.overall_miss_latency::cpu0.data 66091685871 # number of overall miss cycles 1119system.cpu0.dcache.overall_miss_latency::total 66091685871 # number of overall miss cycles 1120system.cpu0.dcache.ReadReq_accesses::cpu0.data 6169919 # number of ReadReq accesses(hits+misses) 1121system.cpu0.dcache.ReadReq_accesses::total 6169919 # number of ReadReq accesses(hits+misses) 1122system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739646 # number of WriteReq accesses(hits+misses) 1123system.cpu0.dcache.WriteReq_accesses::total 4739646 # number of WriteReq accesses(hits+misses) 1124system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147827 # number of LoadLockedReq accesses(hits+misses) 1125system.cpu0.dcache.LoadLockedReq_accesses::total 147827 # number of LoadLockedReq accesses(hits+misses) 1126system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144519 # number of StoreCondReq accesses(hits+misses) 1127system.cpu0.dcache.StoreCondReq_accesses::total 144519 # number of StoreCondReq accesses(hits+misses) 1128system.cpu0.dcache.demand_accesses::cpu0.data 10909565 # number of demand (read+write) accesses 1129system.cpu0.dcache.demand_accesses::total 10909565 # number of demand (read+write) accesses 1130system.cpu0.dcache.overall_accesses::cpu0.data 10909565 # number of overall (read+write) accesses 1131system.cpu0.dcache.overall_accesses::total 10909565 # number of overall (read+write) accesses 1132system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063681 # miss rate for ReadReq accesses 1133system.cpu0.dcache.ReadReq_miss_rate::total 0.063681 # miss rate for ReadReq accesses 1134system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333714 # miss rate for WriteReq accesses 1135system.cpu0.dcache.WriteReq_miss_rate::total 0.333714 # miss rate for WriteReq accesses 1136system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059346 # miss rate for LoadLockedReq accesses 1137system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059346 # miss rate for LoadLockedReq accesses 1138system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051959 # miss rate for StoreCondReq accesses 1139system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051959 # miss rate for StoreCondReq accesses 1140system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180997 # miss rate for demand accesses 1141system.cpu0.dcache.demand_miss_rate::total 0.180997 # miss rate for demand accesses 1142system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180997 # miss rate for overall accesses 1143system.cpu0.dcache.overall_miss_rate::total 0.180997 # miss rate for overall accesses 1144system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207 # average ReadReq miss latency 1145system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207 # average ReadReq miss latency 1146system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325 # average WriteReq miss latency 1147system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325 # average WriteReq miss latency 1148system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9973.669212 # average LoadLockedReq miss latency 1149system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9973.669212 # average LoadLockedReq miss latency 1150system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6230.656545 # average StoreCondReq miss latency 1151system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6230.656545 # average StoreCondReq miss latency 1152system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency 1153system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420 # average overall miss latency 1154system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency 1155system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420 # average overall miss latency 1156system.cpu0.dcache.blocked_cycles::no_mshrs 9022 # number of cycles access was blocked 1157system.cpu0.dcache.blocked_cycles::no_targets 2690 # number of cycles access was blocked 1158system.cpu0.dcache.blocked::no_mshrs 641 # number of cycles access was blocked 1159system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked 1160system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.074883 # average number of cycles each access was blocked 1161system.cpu0.dcache.avg_blocked_cycles::no_targets 33.625000 # average number of cycles each access was blocked | 1090system.cpu0.dcache.replacements 276008 # number of replacements 1091system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use 1092system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks. 1093system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks. 1094system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks. 1095system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. 1096system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor 1097system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy 1098system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy 1099system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits 1100system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits 1101system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits 1102system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits 1103system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits 1104system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits 1105system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits 1106system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits 1107system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits 1108system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits 1109system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits 1110system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits 1111system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses 1112system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses 1113system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses 1114system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses 1115system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses 1116system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses 1117system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses 1118system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses 1119system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses 1120system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses 1121system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses 1122system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses 1123system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles 1124system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles 1125system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles 1126system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles 1127system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles 1128system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles 1129system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles 1130system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles 1131system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles 1132system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles 1133system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles 1134system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles 1135system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses) 1136system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses) 1137system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses) 1138system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses) 1139system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses) 1140system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses) 1141system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses) 1142system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses) 1143system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses 1144system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses 1145system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses 1146system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses 1147system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses 1148system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses 1149system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses 1150system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses 1151system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses 1152system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses 1153system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses 1154system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses 1155system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses 1156system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses 1157system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses 1158system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses 1159system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency 1160system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency 1161system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency 1162system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency 1163system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency 1164system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency 1165system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency 1166system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency 1167system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency 1168system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency 1169system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency 1170system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency 1171system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked 1172system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked 1173system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked 1174system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked 1175system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked 1176system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked |
1162system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1163system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1177system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1178system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
1164system.cpu0.dcache.writebacks::writebacks 256527 # number of writebacks 1165system.cpu0.dcache.writebacks::total 256527 # number of writebacks 1166system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204116 # number of ReadReq MSHR hits 1167system.cpu0.dcache.ReadReq_mshr_hits::total 204116 # number of ReadReq MSHR hits 1168system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451395 # number of WriteReq MSHR hits 1169system.cpu0.dcache.WriteReq_mshr_hits::total 1451395 # number of WriteReq MSHR hits | 1179system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks 1180system.cpu0.dcache.writebacks::total 256612 # number of writebacks 1181system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits 1182system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits 1183system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits 1184system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits |
1170system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits 1171system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits | 1185system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits 1186system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits |
1172system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655511 # number of demand (read+write) MSHR hits 1173system.cpu0.dcache.demand_mshr_hits::total 1655511 # number of demand (read+write) MSHR hits 1174system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655511 # number of overall MSHR hits 1175system.cpu0.dcache.overall_mshr_hits::total 1655511 # number of overall MSHR hits 1176system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188793 # number of ReadReq MSHR misses 1177system.cpu0.dcache.ReadReq_mshr_misses::total 188793 # number of ReadReq MSHR misses 1178system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130291 # number of WriteReq MSHR misses 1179system.cpu0.dcache.WriteReq_mshr_misses::total 130291 # number of WriteReq MSHR misses 1180system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8302 # number of LoadLockedReq MSHR misses 1181system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8302 # number of LoadLockedReq MSHR misses 1182system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7505 # number of StoreCondReq MSHR misses 1183system.cpu0.dcache.StoreCondReq_mshr_misses::total 7505 # number of StoreCondReq MSHR misses 1184system.cpu0.dcache.demand_mshr_misses::cpu0.data 319084 # number of demand (read+write) MSHR misses 1185system.cpu0.dcache.demand_mshr_misses::total 319084 # number of demand (read+write) MSHR misses 1186system.cpu0.dcache.overall_mshr_misses::cpu0.data 319084 # number of overall MSHR misses 1187system.cpu0.dcache.overall_mshr_misses::total 319084 # number of overall MSHR misses 1188system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371443000 # number of ReadReq MSHR miss cycles 1189system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371443000 # number of ReadReq MSHR miss cycles 1190system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4036122491 # number of WriteReq MSHR miss cycles 1191system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4036122491 # number of WriteReq MSHR miss cycles 1192system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65692500 # number of LoadLockedReq MSHR miss cycles 1193system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65692500 # number of LoadLockedReq MSHR miss cycles 1194system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31776000 # number of StoreCondReq MSHR miss cycles 1195system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31776000 # number of StoreCondReq MSHR miss cycles 1196system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6407565491 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.dcache.demand_mshr_miss_latency::total 6407565491 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6407565491 # number of overall MSHR miss cycles 1199system.cpu0.dcache.overall_mshr_miss_latency::total 6407565491 # number of overall MSHR miss cycles 1200system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513513000 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513513000 # number of ReadReq MSHR uncacheable cycles 1202system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180350378 # number of WriteReq MSHR uncacheable cycles 1203system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180350378 # number of WriteReq MSHR uncacheable cycles 1204system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693863378 # number of overall MSHR uncacheable cycles 1205system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693863378 # number of overall MSHR uncacheable cycles 1206system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030599 # mshr miss rate for ReadReq accesses 1207system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030599 # mshr miss rate for ReadReq accesses 1208system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027490 # mshr miss rate for WriteReq accesses 1209system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027490 # mshr miss rate for WriteReq accesses 1210system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056160 # mshr miss rate for LoadLockedReq accesses 1211system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056160 # mshr miss rate for LoadLockedReq accesses 1212system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051931 # mshr miss rate for StoreCondReq accesses 1213system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051931 # mshr miss rate for StoreCondReq accesses 1214system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for demand accesses 1215system.cpu0.dcache.demand_mshr_miss_rate::total 0.029248 # mshr miss rate for demand accesses 1216system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for overall accesses 1217system.cpu0.dcache.overall_mshr_miss_rate::total 0.029248 # mshr miss rate for overall accesses 1218system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828 # average ReadReq mshr miss latency 1219system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828 # average ReadReq mshr miss latency 1220system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575 # average WriteReq mshr miss latency 1221system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575 # average WriteReq mshr miss latency 1222system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.852325 # average LoadLockedReq mshr miss latency 1223system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.852325 # average LoadLockedReq mshr miss latency 1224system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4233.977348 # average StoreCondReq mshr miss latency 1225system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4233.977348 # average StoreCondReq mshr miss latency 1226system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency 1227system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency 1228system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency 1229system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency | 1187system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits 1188system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits 1189system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits 1190system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits 1191system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses 1192system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses 1193system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses 1194system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses 1195system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses 1196system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses 1197system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses 1198system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses 1199system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses 1200system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses 1201system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses 1202system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses 1203system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles 1204system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles 1205system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles 1206system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles 1207system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles 1208system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles 1209system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles 1210system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles 1211system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles 1212system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles 1213system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles 1214system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles 1215system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles 1216system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles 1217system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles 1218system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles 1219system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles 1220system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles 1221system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses 1222system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses 1223system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses 1224system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses 1225system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses 1226system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses 1227system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses 1228system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses 1229system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses 1230system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses 1231system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses 1232system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses 1233system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency 1234system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency 1235system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency 1236system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency 1237system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency 1238system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency 1239system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency 1240system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency 1241system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency 1242system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency 1243system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency 1244system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency |
1230system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1231system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1232system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1233system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1234system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1235system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1236system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1245system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1246system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1247system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1248system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1249system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1250system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1251system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
1237system.cpu1.branchPred.lookups 9086614 # Number of BP lookups 1238system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted 1239system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect 1240system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups 1241system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits | 1252system.cpu1.branchPred.lookups 9071093 # Number of BP lookups 1253system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted 1254system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect 1255system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups 1256system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits |
1242system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1257system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
1243system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage 1244system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target. 1245system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions. | 1258system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage 1259system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. 1260system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. |
1246system.cpu1.dtb.inst_hits 0 # ITB inst hits 1247system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1261system.cpu1.dtb.inst_hits 0 # ITB inst hits 1262system.cpu1.dtb.inst_misses 0 # ITB inst misses |
1248system.cpu1.dtb.read_hits 42908069 # DTB read hits 1249system.cpu1.dtb.read_misses 37093 # DTB read misses 1250system.cpu1.dtb.write_hits 6828111 # DTB write hits 1251system.cpu1.dtb.write_misses 10566 # DTB write misses | 1263system.cpu1.dtb.read_hits 42899284 # DTB read hits 1264system.cpu1.dtb.read_misses 36667 # DTB read misses 1265system.cpu1.dtb.write_hits 6823776 # DTB write hits 1266system.cpu1.dtb.write_misses 10740 # DTB write misses |
1252system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1253system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1254system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1255system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1267system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1268system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1269system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1270system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
1256system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB 1257system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions 1258system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch | 1271system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 1272system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions 1273system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch |
1259system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1274system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
1260system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions 1261system.cpu1.dtb.read_accesses 42945162 # DTB read accesses 1262system.cpu1.dtb.write_accesses 6838677 # DTB write accesses | 1275system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions 1276system.cpu1.dtb.read_accesses 42935951 # DTB read accesses 1277system.cpu1.dtb.write_accesses 6834516 # DTB write accesses |
1263system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1278system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
1264system.cpu1.dtb.hits 49736180 # DTB hits 1265system.cpu1.dtb.misses 47659 # DTB misses 1266system.cpu1.dtb.accesses 49783839 # DTB accesses 1267system.cpu1.itb.inst_hits 8400139 # ITB inst hits 1268system.cpu1.itb.inst_misses 5511 # ITB inst misses | 1279system.cpu1.dtb.hits 49723060 # DTB hits 1280system.cpu1.dtb.misses 47407 # DTB misses 1281system.cpu1.dtb.accesses 49770467 # DTB accesses 1282system.cpu1.itb.inst_hits 8396614 # ITB inst hits 1283system.cpu1.itb.inst_misses 5496 # ITB inst misses |
1269system.cpu1.itb.read_hits 0 # DTB read hits 1270system.cpu1.itb.read_misses 0 # DTB read misses 1271system.cpu1.itb.write_hits 0 # DTB write hits 1272system.cpu1.itb.write_misses 0 # DTB write misses 1273system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1274system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1275system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1276system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1284system.cpu1.itb.read_hits 0 # DTB read hits 1285system.cpu1.itb.read_misses 0 # DTB read misses 1286system.cpu1.itb.write_hits 0 # DTB write hits 1287system.cpu1.itb.write_misses 0 # DTB write misses 1288system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1289system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1290system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1291system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
1277system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB | 1292system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB |
1278system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1279system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1280system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1293system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1294system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1295system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
1281system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions | 1296system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions |
1282system.cpu1.itb.read_accesses 0 # DTB read accesses 1283system.cpu1.itb.write_accesses 0 # DTB write accesses | 1297system.cpu1.itb.read_accesses 0 # DTB read accesses 1298system.cpu1.itb.write_accesses 0 # DTB write accesses |
1284system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses 1285system.cpu1.itb.hits 8400139 # DTB hits 1286system.cpu1.itb.misses 5511 # DTB misses 1287system.cpu1.itb.accesses 8405650 # DTB accesses 1288system.cpu1.numCycles 408778710 # number of cpu cycles simulated | 1299system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses 1300system.cpu1.itb.hits 8396614 # DTB hits 1301system.cpu1.itb.misses 5496 # DTB misses 1302system.cpu1.itb.accesses 8402110 # DTB accesses 1303system.cpu1.numCycles 408759365 # number of cpu cycles simulated |
1289system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1290system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1304system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1305system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
1291system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss 1292system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed 1293system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered 1294system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken 1295system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked 1296system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing 1297system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb 1298system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked 1299system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1300system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps 1301system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions 1302system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR 1303system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched 1304system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed 1305system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed 1306system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total) 1307system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total) 1308system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total) | 1306system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss 1307system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed 1308system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered 1309system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken 1310system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked 1311system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing 1312system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb 1313system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked 1314system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1315system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps 1316system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions 1317system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR 1318system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched 1319system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed 1320system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed 1321system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) 1322system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) 1323system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) |
1309system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1324system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
1310system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total) 1311system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total) 1312system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total) 1313system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total) 1314system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total) 1315system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total) 1316system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total) 1317system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total) 1318system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total) | 1325system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) 1326system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) 1327system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) 1328system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) 1329system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) 1330system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) 1331system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) 1332system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) 1333system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) |
1319system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1320system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1321system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1334system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1335system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1336system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
1322system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total) 1323system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle 1324system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle 1325system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle 1326system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked 1327system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running 1328system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking 1329system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing 1330system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch 1331system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction 1332system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode 1333system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode 1334system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing 1335system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle 1336system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking 1337system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst 1338system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running 1339system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking 1340system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename 1341system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full 1342system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full 1343system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full 1344system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers 1345system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed 1346system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made 1347system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups 1348system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups 1349system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed 1350system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing 1351system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed 1352system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed 1353system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer 1354system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit. 1355system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit. 1356system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads. 1357system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores. 1358system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec) 1359system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ 1360system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued 1361system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued 1362system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling 1363system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph 1364system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed 1365system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle 1366system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle 1367system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle | 1337system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) 1338system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle 1339system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle 1340system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle 1341system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked 1342system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running 1343system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking 1344system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing 1345system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch 1346system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction 1347system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode 1348system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode 1349system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing 1350system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle 1351system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking 1352system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst 1353system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running 1354system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking 1355system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename 1356system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full 1357system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full 1358system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full 1359system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers 1360system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed 1361system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made 1362system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups 1363system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups 1364system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed 1365system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing 1366system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed 1367system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed 1368system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer 1369system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. 1370system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. 1371system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. 1372system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. 1373system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) 1374system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ 1375system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued 1376system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued 1377system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling 1378system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph 1379system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed 1380system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle 1381system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle 1382system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle |
1368system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1383system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
1369system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle 1370system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle 1371system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle 1372system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle 1373system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle 1374system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle 1375system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle 1376system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle 1377system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle | 1384system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle 1385system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle 1386system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle 1387system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle 1388system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle 1389system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle 1390system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle 1391system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle 1392system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle |
1378system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1379system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1380system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1393system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1394system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1395system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
1381system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle | 1396system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle |
1382system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1397system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
1383system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available 1384system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available | 1398system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available 1399system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available |
1385system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available 1386system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1387system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1388system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1389system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available 1390system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1391system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1392system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 1404system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1408system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available 1409system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available 1410system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1411system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available | 1400system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available 1401system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available 1402system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1403system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1404system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available 1405system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1406system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available 1407system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 1419system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available 1420system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available 1421system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available 1422system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available 1423system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available 1424system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available 1425system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available 1426system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available |
1412system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available 1413system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available | 1427system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available 1428system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available |
1414system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1415system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1416system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued | 1429system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1430system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1431system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued |
1417system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued 1418system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued 1419system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued 1420system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued 1421system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued 1422system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued 1423system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued 1424system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued 1425system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued 1426system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued 1427system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued 1428system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued 1429system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued 1430system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued 1431system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued 1432system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued 1433system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued 1434system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued 1435system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued 1436system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued 1437system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued 1438system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued 1439system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued 1440system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued 1441system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued 1442system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued 1443system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued 1444system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued 1445system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued 1446system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued 1447system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued | 1432system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued 1433system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued 1434system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued 1435system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued 1436system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued 1437system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued 1438system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued 1439system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued 1440system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued 1441system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued 1442system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued 1443system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued 1444system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued 1445system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued 1446system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued 1447system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued 1448system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued 1449system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued 1450system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued 1451system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued 1452system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued 1453system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued 1454system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued 1455system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued 1456system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued 1457system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued 1458system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued 1459system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued 1460system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued 1461system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued 1462system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued |
1448system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1449system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1463system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1464system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
1450system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued 1451system.cpu1.iq.rate 0.218115 # Inst issue rate 1452system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested 1453system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst) 1454system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads 1455system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes 1456system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses 1457system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads 1458system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes 1459system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses 1460system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses 1461system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses 1462system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores | 1465system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued 1466system.cpu1.iq.rate 0.218037 # Inst issue rate 1467system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested 1468system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) 1469system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads 1470system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes 1471system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses 1472system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads 1473system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes 1474system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses 1475system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses 1476system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses 1477system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores |
1463system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1478system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
1464system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed 1465system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed 1466system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations 1467system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed | 1479system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed 1480system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed 1481system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations 1482system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed |
1468system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1469system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1483system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1484system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
1470system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled 1471system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked | 1485system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled 1486system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked |
1472system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1487system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
1473system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing 1474system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking 1475system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking 1476system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ 1477system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch 1478system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions 1479system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions 1480system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions 1481system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall 1482system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall 1483system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations 1484system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly 1485system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly 1486system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute 1487system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions 1488system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed 1489system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute | 1488system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing 1489system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking 1490system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking 1491system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ 1492system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch 1493system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions 1494system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions 1495system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions 1496system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall 1497system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall 1498system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations 1499system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly 1500system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly 1501system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute 1502system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions 1503system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed 1504system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute |
1490system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1505system.cpu1.iew.exec_swp 0 # number of swp insts executed |
1491system.cpu1.iew.exec_nop 104517 # number of nop insts executed 1492system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed 1493system.cpu1.iew.exec_branches 7007502 # Number of branches executed 1494system.cpu1.iew.exec_stores 7113991 # Number of stores executed 1495system.cpu1.iew.exec_rate 0.212186 # Inst execution rate 1496system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit 1497system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back 1498system.cpu1.iew.wb_producers 29917161 # num instructions producing a value 1499system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value | 1506system.cpu1.iew.exec_nop 104622 # number of nop insts executed 1507system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed 1508system.cpu1.iew.exec_branches 7000416 # Number of branches executed 1509system.cpu1.iew.exec_stores 7109526 # Number of stores executed 1510system.cpu1.iew.exec_rate 0.212092 # Inst execution rate 1511system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit 1512system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back 1513system.cpu1.iew.wb_producers 29911901 # num instructions producing a value 1514system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value |
1500system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1515system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
1501system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle 1502system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back | 1516system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle 1517system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back |
1503system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1518system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
1504system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit 1505system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards 1506system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted 1507system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle 1508system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle 1509system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle | 1519system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit 1520system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards 1521system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted 1522system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle 1523system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle 1524system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle |
1510system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1525system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
1511system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle 1512system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle 1513system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle 1514system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle 1515system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle 1516system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle 1517system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle 1518system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle 1519system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle | 1526system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle 1527system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle 1528system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle 1529system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle 1530system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle 1531system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle 1532system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle 1533system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle 1534system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle |
1520system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1521system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1522system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1535system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1536system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1537system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
1523system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle 1524system.cpu1.commit.committedInsts 38064892 # Number of instructions committed 1525system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed | 1538system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle 1539system.cpu1.commit.committedInsts 38058920 # Number of instructions committed 1540system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed |
1526system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1541system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
1527system.cpu1.commit.refs 16595277 # Number of memory references committed 1528system.cpu1.commit.loads 9755144 # Number of loads committed 1529system.cpu1.commit.membars 190149 # Number of memory barriers committed 1530system.cpu1.commit.branches 5967637 # Number of branches committed 1531system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. 1532system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions. 1533system.cpu1.commit.function_calls 534638 # Number of function calls committed. 1534system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached | 1542system.cpu1.commit.refs 16590474 # Number of memory references committed 1543system.cpu1.commit.loads 9752596 # Number of loads committed 1544system.cpu1.commit.membars 190088 # Number of memory barriers committed 1545system.cpu1.commit.branches 5966646 # Number of branches committed 1546system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1547system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. 1548system.cpu1.commit.function_calls 534484 # Number of function calls committed. 1549system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached |
1535system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1550system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
1536system.cpu1.rob.rob_reads 173015978 # The number of ROB reads 1537system.cpu1.rob.rob_writes 131360292 # The number of ROB writes 1538system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself 1539system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling 1540system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1541system.cpu1.committedInsts 37995253 # Number of Instructions Simulated 1542system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated 1543system.cpu1.committedInsts_total 37995253 # Number of Instructions Simulated 1544system.cpu1.cpi 10.758678 # CPI: Cycles Per Instruction 1545system.cpu1.cpi_total 10.758678 # CPI: Total CPI of All Threads 1546system.cpu1.ipc 0.092948 # IPC: Instructions Per Cycle 1547system.cpu1.ipc_total 0.092948 # IPC: Total IPC of All Threads 1548system.cpu1.int_regfile_reads 388090475 # number of integer regfile reads 1549system.cpu1.int_regfile_writes 56232580 # number of integer regfile writes 1550system.cpu1.fp_regfile_reads 4956 # number of floating regfile reads 1551system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes 1552system.cpu1.misc_regfile_reads 18472941 # number of misc regfile reads 1553system.cpu1.misc_regfile_writes 405527 # number of misc regfile writes 1554system.cpu1.icache.replacements 597992 # number of replacements 1555system.cpu1.icache.tagsinuse 480.750463 # Cycle average of tags in use 1556system.cpu1.icache.total_refs 7754983 # Total number of references to valid blocks. 1557system.cpu1.icache.sampled_refs 598504 # Sample count of references to valid blocks. 1558system.cpu1.icache.avg_refs 12.957278 # Average number of references to valid blocks. 1559system.cpu1.icache.warmup_cycle 74232640500 # Cycle when the warmup percentage was hit. 1560system.cpu1.icache.occ_blocks::cpu1.inst 480.750463 # Average occupied blocks per requestor 1561system.cpu1.icache.occ_percent::cpu1.inst 0.938966 # Average percentage of cache occupancy 1562system.cpu1.icache.occ_percent::total 0.938966 # Average percentage of cache occupancy 1563system.cpu1.icache.ReadReq_hits::cpu1.inst 7754983 # number of ReadReq hits 1564system.cpu1.icache.ReadReq_hits::total 7754983 # number of ReadReq hits 1565system.cpu1.icache.demand_hits::cpu1.inst 7754983 # number of demand (read+write) hits 1566system.cpu1.icache.demand_hits::total 7754983 # number of demand (read+write) hits 1567system.cpu1.icache.overall_hits::cpu1.inst 7754983 # number of overall hits 1568system.cpu1.icache.overall_hits::total 7754983 # number of overall hits 1569system.cpu1.icache.ReadReq_misses::cpu1.inst 643188 # number of ReadReq misses 1570system.cpu1.icache.ReadReq_misses::total 643188 # number of ReadReq misses 1571system.cpu1.icache.demand_misses::cpu1.inst 643188 # number of demand (read+write) misses 1572system.cpu1.icache.demand_misses::total 643188 # number of demand (read+write) misses 1573system.cpu1.icache.overall_misses::cpu1.inst 643188 # number of overall misses 1574system.cpu1.icache.overall_misses::total 643188 # number of overall misses 1575system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8662129496 # number of ReadReq miss cycles 1576system.cpu1.icache.ReadReq_miss_latency::total 8662129496 # number of ReadReq miss cycles 1577system.cpu1.icache.demand_miss_latency::cpu1.inst 8662129496 # number of demand (read+write) miss cycles 1578system.cpu1.icache.demand_miss_latency::total 8662129496 # number of demand (read+write) miss cycles 1579system.cpu1.icache.overall_miss_latency::cpu1.inst 8662129496 # number of overall miss cycles 1580system.cpu1.icache.overall_miss_latency::total 8662129496 # number of overall miss cycles 1581system.cpu1.icache.ReadReq_accesses::cpu1.inst 8398171 # number of ReadReq accesses(hits+misses) 1582system.cpu1.icache.ReadReq_accesses::total 8398171 # number of ReadReq accesses(hits+misses) 1583system.cpu1.icache.demand_accesses::cpu1.inst 8398171 # number of demand (read+write) accesses 1584system.cpu1.icache.demand_accesses::total 8398171 # number of demand (read+write) accesses 1585system.cpu1.icache.overall_accesses::cpu1.inst 8398171 # number of overall (read+write) accesses 1586system.cpu1.icache.overall_accesses::total 8398171 # number of overall (read+write) accesses 1587system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076587 # miss rate for ReadReq accesses 1588system.cpu1.icache.ReadReq_miss_rate::total 0.076587 # miss rate for ReadReq accesses 1589system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076587 # miss rate for demand accesses 1590system.cpu1.icache.demand_miss_rate::total 0.076587 # miss rate for demand accesses 1591system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076587 # miss rate for overall accesses 1592system.cpu1.icache.overall_miss_rate::total 0.076587 # miss rate for overall accesses 1593system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.492391 # average ReadReq miss latency 1594system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.492391 # average ReadReq miss latency 1595system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency 1596system.cpu1.icache.demand_avg_miss_latency::total 13467.492391 # average overall miss latency 1597system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency 1598system.cpu1.icache.overall_avg_miss_latency::total 13467.492391 # average overall miss latency 1599system.cpu1.icache.blocked_cycles::no_mshrs 2692 # number of cycles access was blocked | 1551system.cpu1.rob.rob_reads 172926580 # The number of ROB reads 1552system.cpu1.rob.rob_writes 131236338 # The number of ROB writes 1553system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself 1554system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling 1555system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1556system.cpu1.committedInsts 37989281 # Number of Instructions Simulated 1557system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated 1558system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated 1559system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction 1560system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads 1561system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle 1562system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads 1563system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads 1564system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes 1565system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads 1566system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes 1567system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads 1568system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes 1569system.cpu1.icache.replacements 596801 # number of replacements 1570system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use 1571system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. 1572system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. 1573system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. 1574system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. 1575system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor 1576system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy 1577system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy 1578system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits 1579system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits 1580system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits 1581system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits 1582system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits 1583system.cpu1.icache.overall_hits::total 7752714 # number of overall hits 1584system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses 1585system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses 1586system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses 1587system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses 1588system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses 1589system.cpu1.icache.overall_misses::total 641884 # number of overall misses 1590system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles 1591system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles 1592system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles 1593system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles 1594system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles 1595system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles 1596system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) 1597system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) 1598system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses 1599system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses 1600system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses 1601system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses 1602system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses 1603system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses 1604system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses 1605system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses 1606system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses 1607system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses 1608system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency 1609system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency 1610system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency 1611system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency 1612system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency 1613system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency 1614system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked |
1600system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1615system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1601system.cpu1.icache.blocked::no_mshrs 184 # number of cycles access was blocked | 1616system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked |
1602system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1617system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
1603system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.630435 # average number of cycles each access was blocked | 1618system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked |
1604system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1605system.cpu1.icache.fast_writes 0 # number of fast writes performed 1606system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1619system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1620system.cpu1.icache.fast_writes 0 # number of fast writes performed 1621system.cpu1.icache.cache_copies 0 # number of cache copies performed |
1607system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44654 # number of ReadReq MSHR hits 1608system.cpu1.icache.ReadReq_mshr_hits::total 44654 # number of ReadReq MSHR hits 1609system.cpu1.icache.demand_mshr_hits::cpu1.inst 44654 # number of demand (read+write) MSHR hits 1610system.cpu1.icache.demand_mshr_hits::total 44654 # number of demand (read+write) MSHR hits 1611system.cpu1.icache.overall_mshr_hits::cpu1.inst 44654 # number of overall MSHR hits 1612system.cpu1.icache.overall_mshr_hits::total 44654 # number of overall MSHR hits 1613system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 598534 # number of ReadReq MSHR misses 1614system.cpu1.icache.ReadReq_mshr_misses::total 598534 # number of ReadReq MSHR misses 1615system.cpu1.icache.demand_mshr_misses::cpu1.inst 598534 # number of demand (read+write) MSHR misses 1616system.cpu1.icache.demand_mshr_misses::total 598534 # number of demand (read+write) MSHR misses 1617system.cpu1.icache.overall_mshr_misses::cpu1.inst 598534 # number of overall MSHR misses 1618system.cpu1.icache.overall_mshr_misses::total 598534 # number of overall MSHR misses 1619system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7093435997 # number of ReadReq MSHR miss cycles 1620system.cpu1.icache.ReadReq_mshr_miss_latency::total 7093435997 # number of ReadReq MSHR miss cycles 1621system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7093435997 # number of demand (read+write) MSHR miss cycles 1622system.cpu1.icache.demand_mshr_miss_latency::total 7093435997 # number of demand (read+write) MSHR miss cycles 1623system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7093435997 # number of overall MSHR miss cycles 1624system.cpu1.icache.overall_mshr_miss_latency::total 7093435997 # number of overall MSHR miss cycles | 1622system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits 1623system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits 1624system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits 1625system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits 1626system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits 1627system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits 1628system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses 1629system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses 1630system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses 1631system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses 1632system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses 1633system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses 1634system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles 1635system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles 1636system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles 1637system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles 1638system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles 1639system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles |
1625system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles 1626system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles 1627system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles 1628system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles | 1640system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles 1641system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles 1642system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles 1643system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles |
1629system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for ReadReq accesses 1630system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071270 # mshr miss rate for ReadReq accesses 1631system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for demand accesses 1632system.cpu1.icache.demand_mshr_miss_rate::total 0.071270 # mshr miss rate for demand accesses 1633system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for overall accesses 1634system.cpu1.icache.overall_mshr_miss_rate::total 0.071270 # mshr miss rate for overall accesses 1635system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average ReadReq mshr miss latency 1636system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.350127 # average ReadReq mshr miss latency 1637system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency 1638system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency 1639system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency 1640system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency | 1644system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for ReadReq accesses 1645system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071158 # mshr miss rate for ReadReq accesses 1646system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for demand accesses 1647system.cpu1.icache.demand_mshr_miss_rate::total 0.071158 # mshr miss rate for demand accesses 1648system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses 1649system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses 1650system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency 1651system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency 1652system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency 1653system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency 1654system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency 1655system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency |
1641system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1642system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1643system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1644system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1645system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1656system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1657system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1658system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1659system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1660system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
1646system.cpu1.dcache.replacements 360685 # number of replacements 1647system.cpu1.dcache.tagsinuse 474.635478 # Cycle average of tags in use 1648system.cpu1.dcache.total_refs 12674649 # Total number of references to valid blocks. 1649system.cpu1.dcache.sampled_refs 361036 # Sample count of references to valid blocks. 1650system.cpu1.dcache.avg_refs 35.106330 # Average number of references to valid blocks. 1651system.cpu1.dcache.warmup_cycle 70356699000 # Cycle when the warmup percentage was hit. 1652system.cpu1.dcache.occ_blocks::cpu1.data 474.635478 # Average occupied blocks per requestor 1653system.cpu1.dcache.occ_percent::cpu1.data 0.927022 # Average percentage of cache occupancy 1654system.cpu1.dcache.occ_percent::total 0.927022 # Average percentage of cache occupancy 1655system.cpu1.dcache.ReadReq_hits::cpu1.data 8306809 # number of ReadReq hits 1656system.cpu1.dcache.ReadReq_hits::total 8306809 # number of ReadReq hits 1657system.cpu1.dcache.WriteReq_hits::cpu1.data 4139176 # number of WriteReq hits 1658system.cpu1.dcache.WriteReq_hits::total 4139176 # number of WriteReq hits 1659system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97757 # number of LoadLockedReq hits 1660system.cpu1.dcache.LoadLockedReq_hits::total 97757 # number of LoadLockedReq hits 1661system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94875 # number of StoreCondReq hits 1662system.cpu1.dcache.StoreCondReq_hits::total 94875 # number of StoreCondReq hits 1663system.cpu1.dcache.demand_hits::cpu1.data 12445985 # number of demand (read+write) hits 1664system.cpu1.dcache.demand_hits::total 12445985 # number of demand (read+write) hits 1665system.cpu1.dcache.overall_hits::cpu1.data 12445985 # number of overall hits 1666system.cpu1.dcache.overall_hits::total 12445985 # number of overall hits 1667system.cpu1.dcache.ReadReq_misses::cpu1.data 399972 # number of ReadReq misses 1668system.cpu1.dcache.ReadReq_misses::total 399972 # number of ReadReq misses 1669system.cpu1.dcache.WriteReq_misses::cpu1.data 1557467 # number of WriteReq misses 1670system.cpu1.dcache.WriteReq_misses::total 1557467 # number of WriteReq misses 1671system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14022 # number of LoadLockedReq misses 1672system.cpu1.dcache.LoadLockedReq_misses::total 14022 # number of LoadLockedReq misses 1673system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10623 # number of StoreCondReq misses 1674system.cpu1.dcache.StoreCondReq_misses::total 10623 # number of StoreCondReq misses 1675system.cpu1.dcache.demand_misses::cpu1.data 1957439 # number of demand (read+write) misses 1676system.cpu1.dcache.demand_misses::total 1957439 # number of demand (read+write) misses 1677system.cpu1.dcache.overall_misses::cpu1.data 1957439 # number of overall misses 1678system.cpu1.dcache.overall_misses::total 1957439 # number of overall misses 1679system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6115655000 # number of ReadReq miss cycles 1680system.cpu1.dcache.ReadReq_miss_latency::total 6115655000 # number of ReadReq miss cycles 1681system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61487432499 # number of WriteReq miss cycles 1682system.cpu1.dcache.WriteReq_miss_latency::total 61487432499 # number of WriteReq miss cycles 1683system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129927000 # number of LoadLockedReq miss cycles 1684system.cpu1.dcache.LoadLockedReq_miss_latency::total 129927000 # number of LoadLockedReq miss cycles 1685system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53882500 # number of StoreCondReq miss cycles 1686system.cpu1.dcache.StoreCondReq_miss_latency::total 53882500 # number of StoreCondReq miss cycles 1687system.cpu1.dcache.demand_miss_latency::cpu1.data 67603087499 # number of demand (read+write) miss cycles 1688system.cpu1.dcache.demand_miss_latency::total 67603087499 # number of demand (read+write) miss cycles 1689system.cpu1.dcache.overall_miss_latency::cpu1.data 67603087499 # number of overall miss cycles 1690system.cpu1.dcache.overall_miss_latency::total 67603087499 # number of overall miss cycles 1691system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706781 # number of ReadReq accesses(hits+misses) 1692system.cpu1.dcache.ReadReq_accesses::total 8706781 # number of ReadReq accesses(hits+misses) 1693system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696643 # number of WriteReq accesses(hits+misses) 1694system.cpu1.dcache.WriteReq_accesses::total 5696643 # number of WriteReq accesses(hits+misses) 1695system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111779 # number of LoadLockedReq accesses(hits+misses) 1696system.cpu1.dcache.LoadLockedReq_accesses::total 111779 # number of LoadLockedReq accesses(hits+misses) 1697system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105498 # number of StoreCondReq accesses(hits+misses) 1698system.cpu1.dcache.StoreCondReq_accesses::total 105498 # number of StoreCondReq accesses(hits+misses) 1699system.cpu1.dcache.demand_accesses::cpu1.data 14403424 # number of demand (read+write) accesses 1700system.cpu1.dcache.demand_accesses::total 14403424 # number of demand (read+write) accesses 1701system.cpu1.dcache.overall_accesses::cpu1.data 14403424 # number of overall (read+write) accesses 1702system.cpu1.dcache.overall_accesses::total 14403424 # number of overall (read+write) accesses 1703system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045938 # miss rate for ReadReq accesses 1704system.cpu1.dcache.ReadReq_miss_rate::total 0.045938 # miss rate for ReadReq accesses 1705system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273401 # miss rate for WriteReq accesses 1706system.cpu1.dcache.WriteReq_miss_rate::total 0.273401 # miss rate for WriteReq accesses 1707system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125444 # miss rate for LoadLockedReq accesses 1708system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125444 # miss rate for LoadLockedReq accesses 1709system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100694 # miss rate for StoreCondReq accesses 1710system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100694 # miss rate for StoreCondReq accesses 1711system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135901 # miss rate for demand accesses 1712system.cpu1.dcache.demand_miss_rate::total 0.135901 # miss rate for demand accesses 1713system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135901 # miss rate for overall accesses 1714system.cpu1.dcache.overall_miss_rate::total 0.135901 # miss rate for overall accesses 1715system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15290.207815 # average ReadReq miss latency 1716system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815 # average ReadReq miss latency 1717system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795 # average WriteReq miss latency 1718system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795 # average WriteReq miss latency 1719system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9265.939238 # average LoadLockedReq miss latency 1720system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9265.939238 # average LoadLockedReq miss latency 1721system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.248894 # average StoreCondReq miss latency 1722system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.248894 # average StoreCondReq miss latency 1723system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency 1724system.cpu1.dcache.demand_avg_miss_latency::total 34536.497689 # average overall miss latency 1725system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency 1726system.cpu1.dcache.overall_avg_miss_latency::total 34536.497689 # average overall miss latency 1727system.cpu1.dcache.blocked_cycles::no_mshrs 30853 # number of cycles access was blocked 1728system.cpu1.dcache.blocked_cycles::no_targets 12637 # number of cycles access was blocked 1729system.cpu1.dcache.blocked::no_mshrs 3329 # number of cycles access was blocked 1730system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked 1731system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.267948 # average number of cycles each access was blocked 1732system.cpu1.dcache.avg_blocked_cycles::no_targets 80.490446 # average number of cycles each access was blocked | 1661system.cpu1.dcache.replacements 360372 # number of replacements 1662system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use 1663system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks. 1664system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks. 1665system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks. 1666system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. 1667system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor 1668system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy 1669system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy 1670system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits 1671system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits 1672system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits 1673system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits 1674system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # number of LoadLockedReq hits 1675system.cpu1.dcache.LoadLockedReq_hits::total 97570 # number of LoadLockedReq hits 1676system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94868 # number of StoreCondReq hits 1677system.cpu1.dcache.StoreCondReq_hits::total 94868 # number of StoreCondReq hits 1678system.cpu1.dcache.demand_hits::cpu1.data 12441592 # number of demand (read+write) hits 1679system.cpu1.dcache.demand_hits::total 12441592 # number of demand (read+write) hits 1680system.cpu1.dcache.overall_hits::cpu1.data 12441592 # number of overall hits 1681system.cpu1.dcache.overall_hits::total 12441592 # number of overall hits 1682system.cpu1.dcache.ReadReq_misses::cpu1.data 400129 # number of ReadReq misses 1683system.cpu1.dcache.ReadReq_misses::total 400129 # number of ReadReq misses 1684system.cpu1.dcache.WriteReq_misses::cpu1.data 1556605 # number of WriteReq misses 1685system.cpu1.dcache.WriteReq_misses::total 1556605 # number of WriteReq misses 1686system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13952 # number of LoadLockedReq misses 1687system.cpu1.dcache.LoadLockedReq_misses::total 13952 # number of LoadLockedReq misses 1688system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10604 # number of StoreCondReq misses 1689system.cpu1.dcache.StoreCondReq_misses::total 10604 # number of StoreCondReq misses 1690system.cpu1.dcache.demand_misses::cpu1.data 1956734 # number of demand (read+write) misses 1691system.cpu1.dcache.demand_misses::total 1956734 # number of demand (read+write) misses 1692system.cpu1.dcache.overall_misses::cpu1.data 1956734 # number of overall misses 1693system.cpu1.dcache.overall_misses::total 1956734 # number of overall misses 1694system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6110776000 # number of ReadReq miss cycles 1695system.cpu1.dcache.ReadReq_miss_latency::total 6110776000 # number of ReadReq miss cycles 1696system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61798994997 # number of WriteReq miss cycles 1697system.cpu1.dcache.WriteReq_miss_latency::total 61798994997 # number of WriteReq miss cycles 1698system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128780500 # number of LoadLockedReq miss cycles 1699system.cpu1.dcache.LoadLockedReq_miss_latency::total 128780500 # number of LoadLockedReq miss cycles 1700system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles 1701system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles 1702system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles 1703system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles 1704system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles 1705system.cpu1.dcache.overall_miss_latency::total 67909770997 # number of overall miss cycles 1706system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703766 # number of ReadReq accesses(hits+misses) 1707system.cpu1.dcache.ReadReq_accesses::total 8703766 # number of ReadReq accesses(hits+misses) 1708system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694560 # number of WriteReq accesses(hits+misses) 1709system.cpu1.dcache.WriteReq_accesses::total 5694560 # number of WriteReq accesses(hits+misses) 1710system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111522 # number of LoadLockedReq accesses(hits+misses) 1711system.cpu1.dcache.LoadLockedReq_accesses::total 111522 # number of LoadLockedReq accesses(hits+misses) 1712system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105472 # number of StoreCondReq accesses(hits+misses) 1713system.cpu1.dcache.StoreCondReq_accesses::total 105472 # number of StoreCondReq accesses(hits+misses) 1714system.cpu1.dcache.demand_accesses::cpu1.data 14398326 # number of demand (read+write) accesses 1715system.cpu1.dcache.demand_accesses::total 14398326 # number of demand (read+write) accesses 1716system.cpu1.dcache.overall_accesses::cpu1.data 14398326 # number of overall (read+write) accesses 1717system.cpu1.dcache.overall_accesses::total 14398326 # number of overall (read+write) accesses 1718system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045972 # miss rate for ReadReq accesses 1719system.cpu1.dcache.ReadReq_miss_rate::total 0.045972 # miss rate for ReadReq accesses 1720system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273349 # miss rate for WriteReq accesses 1721system.cpu1.dcache.WriteReq_miss_rate::total 0.273349 # miss rate for WriteReq accesses 1722system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125105 # miss rate for LoadLockedReq accesses 1723system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125105 # miss rate for LoadLockedReq accesses 1724system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100539 # miss rate for StoreCondReq accesses 1725system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100539 # miss rate for StoreCondReq accesses 1726system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135900 # miss rate for demand accesses 1727system.cpu1.dcache.demand_miss_rate::total 0.135900 # miss rate for demand accesses 1728system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses 1729system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses 1730system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency 1731system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency 1732system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency 1733system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency 1734system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency 1735system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency 1736system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency 1737system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency 1738system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency 1739system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency 1740system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency 1741system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency 1742system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked 1743system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked 1744system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked 1745system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked 1746system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked 1747system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked |
1733system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1734system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1748system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1749system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
1735system.cpu1.dcache.writebacks::writebacks 324651 # number of writebacks 1736system.cpu1.dcache.writebacks::total 324651 # number of writebacks 1737system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171732 # number of ReadReq MSHR hits 1738system.cpu1.dcache.ReadReq_mshr_hits::total 171732 # number of ReadReq MSHR hits 1739system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395801 # number of WriteReq MSHR hits 1740system.cpu1.dcache.WriteReq_mshr_hits::total 1395801 # number of WriteReq MSHR hits 1741system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1444 # number of LoadLockedReq MSHR hits 1742system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1444 # number of LoadLockedReq MSHR hits 1743system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567533 # number of demand (read+write) MSHR hits 1744system.cpu1.dcache.demand_mshr_hits::total 1567533 # number of demand (read+write) MSHR hits 1745system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567533 # number of overall MSHR hits 1746system.cpu1.dcache.overall_mshr_hits::total 1567533 # number of overall MSHR hits 1747system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228240 # number of ReadReq MSHR misses 1748system.cpu1.dcache.ReadReq_mshr_misses::total 228240 # number of ReadReq MSHR misses 1749system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161666 # number of WriteReq MSHR misses 1750system.cpu1.dcache.WriteReq_mshr_misses::total 161666 # number of WriteReq MSHR misses 1751system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12578 # number of LoadLockedReq MSHR misses 1752system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12578 # number of LoadLockedReq MSHR misses 1753system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10618 # number of StoreCondReq MSHR misses 1754system.cpu1.dcache.StoreCondReq_mshr_misses::total 10618 # number of StoreCondReq MSHR misses 1755system.cpu1.dcache.demand_mshr_misses::cpu1.data 389906 # number of demand (read+write) MSHR misses 1756system.cpu1.dcache.demand_mshr_misses::total 389906 # number of demand (read+write) MSHR misses 1757system.cpu1.dcache.overall_mshr_misses::cpu1.data 389906 # number of overall MSHR misses 1758system.cpu1.dcache.overall_mshr_misses::total 389906 # number of overall MSHR misses 1759system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2856522500 # number of ReadReq MSHR miss cycles 1760system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2856522500 # number of ReadReq MSHR miss cycles 1761system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131083207 # number of WriteReq MSHR miss cycles 1762system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131083207 # number of WriteReq MSHR miss cycles 1763system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89046000 # number of LoadLockedReq MSHR miss cycles 1764system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89046000 # number of LoadLockedReq MSHR miss cycles 1765system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32648500 # number of StoreCondReq MSHR miss cycles 1766system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32648500 # number of StoreCondReq MSHR miss cycles 1767system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1768system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1769system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7987605707 # number of demand (read+write) MSHR miss cycles 1770system.cpu1.dcache.demand_mshr_miss_latency::total 7987605707 # number of demand (read+write) MSHR miss cycles 1771system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7987605707 # number of overall MSHR miss cycles 1772system.cpu1.dcache.overall_mshr_miss_latency::total 7987605707 # number of overall MSHR miss cycles 1773system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000 # number of ReadReq MSHR uncacheable cycles 1774system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000 # number of ReadReq MSHR uncacheable cycles 1775system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35686741676 # number of WriteReq MSHR uncacheable cycles 1776system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35686741676 # number of WriteReq MSHR uncacheable cycles 1777system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676 # number of overall MSHR uncacheable cycles 1778system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676 # number of overall MSHR uncacheable cycles 1779system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for ReadReq accesses 1780system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026214 # mshr miss rate for ReadReq accesses 1781system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028379 # mshr miss rate for WriteReq accesses 1782system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028379 # mshr miss rate for WriteReq accesses 1783system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112526 # mshr miss rate for LoadLockedReq accesses 1784system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112526 # mshr miss rate for LoadLockedReq accesses 1785system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for StoreCondReq accesses 1786system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100646 # mshr miss rate for StoreCondReq accesses 1787system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for demand accesses 1788system.cpu1.dcache.demand_mshr_miss_rate::total 0.027070 # mshr miss rate for demand accesses 1789system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for overall accesses 1790system.cpu1.dcache.overall_mshr_miss_rate::total 0.027070 # mshr miss rate for overall accesses 1791system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316 # average ReadReq mshr miss latency 1792system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316 # average ReadReq mshr miss latency 1793system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894 # average WriteReq mshr miss latency 1794system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894 # average WriteReq mshr miss latency 1795system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.503896 # average LoadLockedReq mshr miss latency 1796system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.503896 # average LoadLockedReq mshr miss latency 1797system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.825768 # average StoreCondReq mshr miss latency 1798system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.825768 # average StoreCondReq mshr miss latency 1799system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1800system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1801system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency 1802system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency 1803system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency 1804system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency | 1750system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks 1751system.cpu1.dcache.writebacks::total 324455 # number of writebacks 1752system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits 1753system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits 1754system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits 1755system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits 1756system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits 1757system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits 1758system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits 1759system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits 1760system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits 1761system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits 1762system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses 1763system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses 1764system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses 1765system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses 1766system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses 1767system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses 1768system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses 1769system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses 1770system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses 1771system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses 1772system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses 1773system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses 1774system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles 1775system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles 1776system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles 1777system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles 1778system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles 1779system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles 1780system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles 1781system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles 1782system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles 1783system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles 1784system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles 1785system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles 1786system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles 1787system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles 1788system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles 1789system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles 1790system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles 1791system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles 1792system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses 1793system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses 1794system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses 1795system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses 1796system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses 1797system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses 1798system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses 1799system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses 1800system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses 1801system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses 1802system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses 1803system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses 1804system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency 1805system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency 1806system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency 1807system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency 1808system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency 1809system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency 1810system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency 1811system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency 1812system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency 1813system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency 1814system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency 1815system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency |
1805system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1806system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1807system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1808system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1809system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1810system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1811system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1812system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1818system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1819system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1820system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1821system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1822system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1823system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1824system.iocache.fast_writes 0 # number of fast writes performed 1825system.iocache.cache_copies 0 # number of cache copies performed | 1816system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1817system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1818system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1819system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1820system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1821system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1822system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1823system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1829system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1830system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1831system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1832system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1833system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1834system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1835system.iocache.fast_writes 0 # number of fast writes performed 1836system.iocache.cache_copies 0 # number of cache copies performed |
1826system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles 1827system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles 1828system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles 1829system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles | 1837system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles 1838system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles 1839system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles 1840system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles |
1830system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1831system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1832system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1833system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1834system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1835system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1841system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1842system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1843system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1844system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1845system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1846system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
1836system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed | 1847system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed |
1837system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1848system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
1838system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed | 1849system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed |
1839 1840---------- End Simulation Statistics ---------- | 1850 1851---------- End Simulation Statistics ---------- |