| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.569716 # Number of seconds simulated 4sim_ticks 2569716290500 # Number of ticks simulated 5final_tick 2569716290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.581528 # Number of seconds simulated 4sim_ticks 2581527583500 # Number of ticks simulated 5final_tick 2581527583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 91215 # Simulator instruction rate (inst/s) 8host_op_rate 117813 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3779331614 # Simulator tick rate (ticks/s) 10host_mem_usage 391064 # Number of bytes of host memory used 11host_seconds 679.94 # Real time elapsed on the host 12sim_insts 62020337 # Number of instructions simulated 13sim_ops 80105642 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 383040 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4310004 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 438272 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 5311600 # Number of bytes read from this memory 23system.physmem.bytes_read::total 129982372 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 383040 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 438272 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 821312 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 4277376 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 30system.physmem.bytes_written::total 7306512 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 5985 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 67416 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6848 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 83020 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15105505 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66834 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 824118 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46517845 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 149059 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 1677230 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.itb.walker 50 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 170553 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 2066999 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 50582382 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 149059 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 170553 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 319612 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 1664532 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu0.data 6616 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 1172167 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 2843315 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 1664532 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::realview.clcd 46517845 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.inst 149059 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.data 1683845 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 170553 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 3239165 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::total 53425697 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 89313 # Simulator instruction rate (inst/s) 8host_op_rate 115365 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3717496726 # Simulator tick rate (ticks/s) 10host_mem_usage 390980 # Number of bytes of host memory used 11host_seconds 694.43 # Real time elapsed on the host 12sim_insts 62021206 # Number of instructions simulated 13sim_ops 80112751 # Number of ops (including micro ops) simulated |
| 73system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 74system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory 76system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 79system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 80system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory 82system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) | 14system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) |
| 83system.realview.nvmem.bw_read::cpu1.inst 125 # Total read bandwidth from this memory (bytes/s) | 24system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) |
| 84system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) | 25system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) |
| 86system.realview.nvmem.bw_inst_read::cpu1.inst 125 # Instruction read bandwidth from this memory (bytes/s) | 27system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) |
| 87system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) 88system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) | 28system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) |
| 89system.realview.nvmem.bw_total::cpu1.inst 125 # Total bandwidth to/from this memory (bytes/s) | 30system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) |
| 90system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) | 31system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) |
| 91system.l2c.replacements 72902 # number of replacements 92system.l2c.tagsinuse 52914.655952 # Cycle average of tags in use 93system.l2c.total_refs 2024041 # Total number of references to valid blocks. 94system.l2c.sampled_refs 138037 # Sample count of references to valid blocks. 95system.l2c.avg_refs 14.663032 # Average number of references to valid blocks. | 32system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4372084 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.data 5226480 # Number of bytes read from this memory 40system.physmem.bytes_read::total 129958756 # Number of bytes read from this memory 41system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory 42system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::total 820544 # Number of instructions bytes read from this memory 44system.physmem.bytes_written::writebacks 4244480 # Number of bytes written to this memory 45system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 47system.physmem.bytes_written::total 7273616 # Number of bytes written to this memory 48system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 49system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.data 68386 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 81690 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 15105136 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 66320 # Number of write requests responded to by this memory 58system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 59system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 60system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 46305011 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.inst 153013 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 1693603 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu1.dtb.walker 521 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu1.inst 164839 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.data 2024569 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::total 50341804 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu0.inst 153013 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::cpu1.inst 164839 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::total 317852 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_write::writebacks 1644174 # Write bandwidth from this memory (bytes/s) 74system.physmem.bw_write::cpu0.data 6585 # Write bandwidth from this memory (bytes/s) 75system.physmem.bw_write::cpu1.data 1166804 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::total 2817563 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_total::writebacks 1644174 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.clcd 46305011 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu0.inst 153013 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.data 1700189 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.dtb.walker 521 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.inst 164839 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu1.data 3191372 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::total 53159367 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 72536 # number of replacements 88system.l2c.tagsinuse 53024.626088 # Cycle average of tags in use 89system.l2c.total_refs 2019266 # Total number of references to valid blocks. 90system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. 91system.l2c.avg_refs 14.660834 # Average number of references to valid blocks. |
| 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 97system.l2c.occ_blocks::writebacks 37560.940783 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 3.394478 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.000176 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu0.inst 4213.394018 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 2969.636370 # Average occupied blocks per requestor 102system.l2c.occ_blocks::cpu1.dtb.walker 12.170115 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.970249 # Average occupied blocks per requestor 104system.l2c.occ_blocks::cpu1.inst 4028.311406 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 4125.838357 # Average occupied blocks per requestor 106system.l2c.occ_percent::writebacks 0.573134 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu0.dtb.walker 0.000052 # Average percentage of cache occupancy | 93system.l2c.occ_blocks::writebacks 37701.415204 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 3.259804 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.000179 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 4215.968317 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 2959.624437 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 13.637835 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 4028.150256 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 4102.570055 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.575278 # Average percentage of cache occupancy 102system.l2c.occ_percent::cpu0.dtb.walker 0.000050 # Average percentage of cache occupancy |
| 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 109system.l2c.occ_percent::cpu0.inst 0.064291 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.045313 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000186 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.061467 # Average percentage of cache occupancy 114system.l2c.occ_percent::cpu1.data 0.062955 # Average percentage of cache occupancy 115system.l2c.occ_percent::total 0.807414 # Average percentage of cache occupancy 116system.l2c.ReadReq_hits::cpu0.dtb.walker 50859 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu0.itb.walker 5940 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu0.inst 395141 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu0.data 161674 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.dtb.walker 79156 # number of ReadReq hits 121system.l2c.ReadReq_hits::cpu1.itb.walker 6590 # number of ReadReq hits 122system.l2c.ReadReq_hits::cpu1.inst 619717 # number of ReadReq hits 123system.l2c.ReadReq_hits::cpu1.data 202375 # number of ReadReq hits 124system.l2c.ReadReq_hits::total 1521452 # number of ReadReq hits 125system.l2c.Writeback_hits::writebacks 646021 # number of Writeback hits 126system.l2c.Writeback_hits::total 646021 # number of Writeback hits 127system.l2c.UpgradeReq_hits::cpu0.data 861 # number of UpgradeReq hits 128system.l2c.UpgradeReq_hits::cpu1.data 1085 # number of UpgradeReq hits 129system.l2c.UpgradeReq_hits::total 1946 # number of UpgradeReq hits 130system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits 131system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits 132system.l2c.SCUpgradeReq_hits::total 373 # number of SCUpgradeReq hits 133system.l2c.ReadExReq_hits::cpu0.data 50919 # number of ReadExReq hits 134system.l2c.ReadExReq_hits::cpu1.data 55813 # number of ReadExReq hits 135system.l2c.ReadExReq_hits::total 106732 # number of ReadExReq hits 136system.l2c.demand_hits::cpu0.dtb.walker 50859 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu0.itb.walker 5940 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu0.inst 395141 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu0.data 212593 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.dtb.walker 79156 # number of demand (read+write) hits 141system.l2c.demand_hits::cpu1.itb.walker 6590 # number of demand (read+write) hits 142system.l2c.demand_hits::cpu1.inst 619717 # number of demand (read+write) hits 143system.l2c.demand_hits::cpu1.data 258188 # number of demand (read+write) hits 144system.l2c.demand_hits::total 1628184 # number of demand (read+write) hits 145system.l2c.overall_hits::cpu0.dtb.walker 50859 # number of overall hits 146system.l2c.overall_hits::cpu0.itb.walker 5940 # number of overall hits 147system.l2c.overall_hits::cpu0.inst 395141 # number of overall hits 148system.l2c.overall_hits::cpu0.data 212593 # number of overall hits 149system.l2c.overall_hits::cpu1.dtb.walker 79156 # number of overall hits 150system.l2c.overall_hits::cpu1.itb.walker 6590 # number of overall hits 151system.l2c.overall_hits::cpu1.inst 619717 # number of overall hits 152system.l2c.overall_hits::cpu1.data 258188 # number of overall hits 153system.l2c.overall_hits::total 1628184 # number of overall hits 154system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses | 104system.l2c.occ_percent::cpu0.inst 0.064331 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.045160 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000208 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.061465 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.062600 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.809092 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 53338 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 6106 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 398719 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 164464 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 78886 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 6452 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 615129 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 199702 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1522796 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 645710 # number of Writeback hits 120system.l2c.Writeback_hits::total 645710 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 806 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1849 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 48030 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 59189 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 107219 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 53338 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 6106 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 398719 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 212494 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 78886 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 6452 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 615129 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 258891 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1630015 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 53338 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 6106 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 398719 # number of overall hits 142system.l2c.overall_hits::cpu0.data 212494 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 78886 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 6452 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 615129 # number of overall hits 146system.l2c.overall_hits::cpu1.data 258891 # number of overall hits 147system.l2c.overall_hits::total 1630015 # number of overall hits 148system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses |
| 155system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 149system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
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number of overall (read+write) accesses 263system.l2c.overall_accesses::total 1793887 # number of overall (read+write) accesses 264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for ReadReq accesses 265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000168 # miss rate for ReadReq accesses 266system.l2c.ReadReq_miss_rate::cpu0.inst 0.014596 # miss rate for ReadReq accesses 267system.l2c.ReadReq_miss_rate::cpu0.data 0.036582 # miss rate for ReadReq accesses 268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000303 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu1.inst 0.010868 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu1.data 0.031291 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::total 0.016399 # miss rate for ReadReq accesses 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.860114 # miss rate for UpgradeReq accesses 274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.814593 # miss rate for UpgradeReq accesses 275system.l2c.UpgradeReq_miss_rate::total 0.837928 # miss rate for UpgradeReq accesses 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787602 # miss rate for SCUpgradeReq accesses 277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.778677 # miss rate for SCUpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::total 0.783768 # miss rate for SCUpgradeReq accesses 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.551596 # miss rate for ReadExReq accesses 280system.l2c.ReadExReq_miss_rate::cpu1.data 0.581966 # miss rate for ReadExReq accesses 281system.l2c.ReadExReq_miss_rate::total 0.568007 # miss rate for ReadExReq accesses 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for demand accesses 283system.l2c.demand_miss_rate::cpu0.itb.walker 0.000168 # miss rate for demand accesses 284system.l2c.demand_miss_rate::cpu0.inst 0.014596 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.data 0.244433 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu1.itb.walker 0.000303 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.010868 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.246001 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.092371 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.000168 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.014596 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.244433 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000303 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.010868 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.246001 # 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average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 324system.l2c.demand_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 52452.095007 # average overall miss latency 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 53000 # average overall miss latency 329system.l2c.overall_avg_miss_latency::cpu0.inst 52296.429182 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 333system.l2c.overall_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 52452.095007 # average overall miss latency | 175system.l2c.overall_misses::cpu0.inst 6044 # number of overall misses 176system.l2c.overall_misses::cpu0.data 69753 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 6609 # number of overall misses 179system.l2c.overall_misses::cpu1.data 82900 # number of overall misses 180system.l2c.overall_misses::total 165337 # number of overall misses 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 471000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 322261499 # 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number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1722 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 111481 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 135761 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 247242 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 53347 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 6107 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 404763 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 282247 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 78907 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 6452 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 621738 # 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number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000164 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.014932 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.036904 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.010630 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.030714 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.016352 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844930 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841744 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.843557 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784848 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.804645 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.793264 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.569164 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.564021 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.566340 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.000164 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.014932 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.247135 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.010630 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.242546 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.092092 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.000164 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.014932 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.247135 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.010630 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.242546 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.092092 # miss rate for overall accesses 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53319.242058 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52506.426055 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.128764 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52557.442952 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52892.964052 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3554.900581 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6393.864941 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 4775.626780 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2215.572716 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12119.694397 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 6486.090776 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.206742 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53172.921956 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 53216.099969 # average ReadExReq miss latency 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 53166.626091 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 53166.626091 # average overall miss latency |
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| 355system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits | 339system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits |
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| 390system.l2c.overall_mshr_misses::cpu0.inst 5849 # number of overall MSHR misses 391system.l2c.overall_mshr_misses::cpu0.data 68738 # number of overall MSHR misses 392system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses 393system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses 394system.l2c.overall_mshr_misses::cpu1.inst 6803 # number of overall MSHR misses 395system.l2c.overall_mshr_misses::cpu1.data 84212 # number of overall MSHR misses 396system.l2c.overall_mshr_misses::total 165630 # number of overall MSHR misses 397system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles 398system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 41000 # number of ReadReq MSHR miss cycles 399system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 234434500 # number of ReadReq MSHR miss cycles 400system.l2c.ReadReq_mshr_miss_latency::cpu0.data 244221500 # number of ReadReq MSHR miss cycles 401system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 601000 # number of ReadReq MSHR miss cycles 402system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 80000 # number of ReadReq MSHR miss cycles 403system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 273121500 # number of ReadReq MSHR miss cycles 404system.l2c.ReadReq_mshr_miss_latency::cpu1.data 260689500 # number of ReadReq MSHR miss cycles 405system.l2c.ReadReq_mshr_miss_latency::total 1013589000 # number of ReadReq MSHR miss cycles 406system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 211949500 # number of UpgradeReq MSHR miss cycles 407system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190864500 # number of UpgradeReq MSHR miss cycles 408system.l2c.UpgradeReq_mshr_miss_latency::total 402814000 # number of UpgradeReq MSHR miss cycles 409system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31033000 # number of SCUpgradeReq MSHR miss cycles 410system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23118500 # number of SCUpgradeReq MSHR miss cycles 411system.l2c.SCUpgradeReq_mshr_miss_latency::total 54151500 # number of SCUpgradeReq MSHR miss cycles 412system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2507451999 # number of ReadExReq MSHR miss cycles 413system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3115007000 # number of ReadExReq MSHR miss cycles 414system.l2c.ReadExReq_mshr_miss_latency::total 5622458999 # number of ReadExReq MSHR miss cycles 415system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles 416system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 41000 # number of demand (read+write) MSHR miss cycles 417system.l2c.demand_mshr_miss_latency::cpu0.inst 234434500 # number of demand (read+write) MSHR miss cycles 418system.l2c.demand_mshr_miss_latency::cpu0.data 2751673499 # number of demand (read+write) MSHR miss cycles 419system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 601000 # number of demand (read+write) MSHR miss cycles 420system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 421system.l2c.demand_mshr_miss_latency::cpu1.inst 273121500 # number of demand (read+write) MSHR miss cycles 422system.l2c.demand_mshr_miss_latency::cpu1.data 3375696500 # number of demand (read+write) MSHR miss cycles 423system.l2c.demand_mshr_miss_latency::total 6636047999 # number of demand (read+write) MSHR miss cycles 424system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles 425system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 41000 # number of overall MSHR miss cycles 426system.l2c.overall_mshr_miss_latency::cpu0.inst 234434500 # number of overall MSHR miss cycles 427system.l2c.overall_mshr_miss_latency::cpu0.data 2751673499 # number of overall MSHR miss cycles 428system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 601000 # number of overall MSHR miss cycles 429system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 80000 # number of overall MSHR miss cycles 430system.l2c.overall_mshr_miss_latency::cpu1.inst 273121500 # number of overall MSHR miss cycles 431system.l2c.overall_mshr_miss_latency::cpu1.data 3375696500 # number of overall MSHR miss cycles 432system.l2c.overall_mshr_miss_latency::total 6636047999 # number of overall MSHR miss cycles 433system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5501500 # number of ReadReq MSHR uncacheable cycles 434system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 21616744000 # number of ReadReq MSHR uncacheable cycles 435system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2009500 # number of ReadReq MSHR uncacheable cycles 436system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 110336260000 # number of ReadReq MSHR uncacheable cycles 437system.l2c.ReadReq_mshr_uncacheable_latency::total 131960515000 # number of ReadReq MSHR uncacheable cycles 438system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 713445484 # number of WriteReq MSHR uncacheable cycles 439system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31812115712 # number of WriteReq MSHR uncacheable cycles 440system.l2c.WriteReq_mshr_uncacheable_latency::total 32525561196 # number of WriteReq MSHR uncacheable cycles 441system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5501500 # number of overall MSHR uncacheable cycles 442system.l2c.overall_mshr_uncacheable_latency::cpu0.data 22330189484 # number of overall MSHR uncacheable cycles 443system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2009500 # number of overall MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu1.data 142148375712 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::total 164486076196 # number of overall MSHR uncacheable cycles 446system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for ReadReq accesses 447system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for ReadReq accesses 449system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036356 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for ReadReq accesses 452system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for ReadReq accesses 453system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031171 # mshr miss rate for ReadReq accesses 454system.l2c.ReadReq_mshr_miss_rate::total 0.016352 # mshr miss rate for ReadReq accesses 455system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.860114 # mshr miss rate for UpgradeReq accesses 456system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814593 # mshr miss rate for UpgradeReq accesses 457system.l2c.UpgradeReq_mshr_miss_rate::total 0.837928 # mshr miss rate for UpgradeReq accesses 458system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787602 # mshr miss rate for SCUpgradeReq accesses 459system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.778677 # mshr miss rate for SCUpgradeReq accesses 460system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783768 # mshr miss rate for SCUpgradeReq accesses 461system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551596 # mshr miss rate for ReadExReq accesses 462system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581966 # mshr miss rate for ReadExReq accesses 463system.l2c.ReadExReq_mshr_miss_rate::total 0.568007 # mshr miss rate for ReadExReq accesses 464system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for demand accesses 466system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for demand accesses 467system.l2c.demand_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for demand accesses 469system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for demand accesses 470system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for demand accesses 471system.l2c.demand_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for demand accesses 472system.l2c.demand_mshr_miss_rate::total 0.092330 # mshr miss rate for demand accesses 473system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for overall accesses 474system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for overall accesses 475system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for overall accesses 476system.l2c.overall_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for overall accesses 477system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for overall accesses 478system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for overall accesses 479system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for overall accesses 480system.l2c.overall_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for overall accesses 481system.l2c.overall_mshr_miss_rate::total 0.092330 # mshr miss rate for overall accesses | 372system.l2c.overall_mshr_misses::cpu0.inst 6039 # number of overall MSHR misses 373system.l2c.overall_mshr_misses::cpu0.data 69713 # number of overall MSHR misses 374system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses 375system.l2c.overall_mshr_misses::cpu1.inst 6604 # number of overall MSHR misses 376system.l2c.overall_mshr_misses::cpu1.data 82877 # number of overall MSHR misses 377system.l2c.overall_mshr_misses::total 165264 # number of overall MSHR misses 378system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles 379system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 48000 # number of ReadReq MSHR miss cycles 380system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248302999 # number of ReadReq MSHR miss cycles 381system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253032000 # number of ReadReq MSHR miss cycles 382system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 846000 # number of ReadReq MSHR miss cycles 383system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270719997 # number of ReadReq MSHR miss cycles 384system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254713500 # number of ReadReq MSHR miss cycles 385system.l2c.ReadReq_mshr_miss_latency::total 1028022496 # number of ReadReq MSHR miss cycles 386system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227576000 # number of UpgradeReq MSHR miss cycles 387system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 171718000 # number of UpgradeReq MSHR miss cycles 388system.l2c.UpgradeReq_mshr_miss_latency::total 399294000 # number of UpgradeReq MSHR miss cycles 389system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31112500 # number of SCUpgradeReq MSHR miss cycles 390system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23586500 # number of SCUpgradeReq MSHR miss cycles 391system.l2c.SCUpgradeReq_mshr_miss_latency::total 54699000 # number of SCUpgradeReq MSHR miss cycles 392system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2608560498 # number of ReadExReq MSHR miss cycles 393system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3134816489 # number of ReadExReq MSHR miss cycles 394system.l2c.ReadExReq_mshr_miss_latency::total 5743376987 # number of ReadExReq MSHR miss cycles 395system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles 396system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 48000 # number of demand (read+write) MSHR miss cycles 397system.l2c.demand_mshr_miss_latency::cpu0.inst 248302999 # number of demand (read+write) MSHR miss cycles 398system.l2c.demand_mshr_miss_latency::cpu0.data 2861592498 # number of demand (read+write) MSHR miss cycles 399system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 846000 # number of demand (read+write) MSHR miss cycles 400system.l2c.demand_mshr_miss_latency::cpu1.inst 270719997 # number of demand (read+write) MSHR miss cycles 401system.l2c.demand_mshr_miss_latency::cpu1.data 3389529989 # number of demand (read+write) MSHR miss cycles 402system.l2c.demand_mshr_miss_latency::total 6771399483 # number of demand (read+write) MSHR miss cycles 403system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles 404system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 48000 # number of overall MSHR miss cycles 405system.l2c.overall_mshr_miss_latency::cpu0.inst 248302999 # number of overall MSHR miss cycles 406system.l2c.overall_mshr_miss_latency::cpu0.data 2861592498 # number of overall MSHR miss cycles 407system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 846000 # number of overall MSHR miss cycles 408system.l2c.overall_mshr_miss_latency::cpu1.inst 270719997 # number of overall MSHR miss cycles 409system.l2c.overall_mshr_miss_latency::cpu1.data 3389529989 # number of overall MSHR miss cycles 410system.l2c.overall_mshr_miss_latency::total 6771399483 # number of overall MSHR miss cycles 411system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles 412system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9186859000 # number of ReadReq MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2133500 # number of ReadReq MSHR uncacheable cycles 414system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122397706500 # number of ReadReq MSHR uncacheable cycles 415system.l2c.ReadReq_mshr_uncacheable_latency::total 131592278000 # number of ReadReq MSHR uncacheable cycles 416system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 704572999 # number of WriteReq MSHR uncacheable cycles 417system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30781654107 # number of WriteReq MSHR uncacheable cycles 418system.l2c.WriteReq_mshr_uncacheable_latency::total 31486227106 # number of WriteReq MSHR uncacheable cycles 419system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles 420system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891431999 # number of overall MSHR uncacheable cycles 421system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2133500 # number of overall MSHR uncacheable cycles 422system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607 # number of overall MSHR uncacheable cycles 423system.l2c.overall_mshr_uncacheable_latency::total 163078505106 # number of overall MSHR uncacheable cycles 424system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for ReadReq accesses 425system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for ReadReq accesses 426system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for ReadReq accesses 427system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036676 # mshr miss rate for ReadReq accesses 428system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for ReadReq accesses 429system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for ReadReq accesses 430system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030602 # mshr miss rate for ReadReq accesses 431system.l2c.ReadReq_mshr_miss_rate::total 0.016305 # mshr miss rate for ReadReq accesses 432system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844930 # mshr miss rate for UpgradeReq accesses 433system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841744 # mshr miss rate for UpgradeReq accesses 434system.l2c.UpgradeReq_mshr_miss_rate::total 0.843557 # mshr miss rate for UpgradeReq accesses 435system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784848 # mshr miss rate for SCUpgradeReq accesses 436system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.804645 # mshr miss rate for SCUpgradeReq accesses 437system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.793264 # mshr miss rate for SCUpgradeReq accesses 438system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569155 # mshr miss rate for ReadExReq accesses 439system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564021 # mshr miss rate for ReadExReq accesses 440system.l2c.ReadExReq_mshr_miss_rate::total 0.566336 # mshr miss rate for ReadExReq accesses 441system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for demand accesses 442system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for demand accesses 443system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for demand accesses 444system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses 445system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for demand accesses 446system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for demand accesses 447system.l2c.demand_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for demand accesses 448system.l2c.demand_mshr_miss_rate::total 0.092051 # mshr miss rate for demand accesses 449system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for overall accesses 450system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for overall accesses 451system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for overall accesses 452system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses 453system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for overall accesses 454system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for overall accesses 455system.l2c.overall_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for overall accesses 456system.l2c.overall_mshr_miss_rate::total 0.092051 # mshr miss rate for overall accesses |
| 482system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency | 457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency |
| 483system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average ReadReq mshr miss latency 484system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average ReadReq mshr miss latency 485system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.749221 # average ReadReq mshr miss latency 486system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average ReadReq mshr miss latency 487system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 488system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average ReadReq mshr miss latency 489system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40032.171376 # average ReadReq mshr miss latency 490system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.893963 # average ReadReq mshr miss latency 491system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.795240 # average UpgradeReq mshr miss latency 492system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.703587 # average UpgradeReq mshr miss latency 493system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.173243 # average UpgradeReq mshr miss latency 494system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40042.580645 # average SCUpgradeReq mshr miss latency 495system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.724437 # average SCUpgradeReq mshr miss latency 496system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40052.884615 # average SCUpgradeReq mshr miss latency 497system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40031.482973 # average ReadExReq mshr miss latency 498system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40090.180180 # average ReadExReq mshr miss latency 499system.l2c.ReadExReq_avg_mshr_miss_latency::total 40063.981694 # average ReadExReq mshr miss latency | 458system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency 459system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average ReadReq mshr miss latency 460system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742 # average ReadReq mshr miss latency 461system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average ReadReq mshr miss latency 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716 # average ReadReq mshr miss latency 465system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630 # average UpgradeReq mshr miss latency 466system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678 # average UpgradeReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646 # average UpgradeReq mshr miss latency 468system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542 # average SCUpgradeReq mshr miss latency 469system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511 # average SCUpgradeReq mshr miss latency 470system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801 # average SCUpgradeReq mshr miss latency 471system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586 # average ReadExReq mshr miss latency 472system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062 # average ReadExReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701 # average ReadExReq mshr miss latency |
| 500system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency | 474system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency |
| 501system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency 502system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency 503system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency 504system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency 505system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 506system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency 507system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency 508system.l2c.demand_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency | 475system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency 481system.l2c.demand_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency |
| 509system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency | 482system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency |
| 510system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency 511system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency 512system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency 513system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency 514system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 515system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency 516system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency 517system.l2c.overall_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency | 483system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency 486system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency 487system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency 488system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency 489system.l2c.overall_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency |
| 518system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 519system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 520system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 521system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 522system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 523system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 524system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 525system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 532system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 533system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 534system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 535system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 536system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 537system.cf0.dma_write_txs 0 # Number of DMA write transactions. 538system.cpu0.dtb.inst_hits 0 # ITB inst hits 539system.cpu0.dtb.inst_misses 0 # ITB inst misses | 490system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 491system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 492system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 493system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 494system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 495system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 496system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 497system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 504system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 505system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 506system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 507system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 508system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 509system.cf0.dma_write_txs 0 # Number of DMA write transactions. 510system.cpu0.dtb.inst_hits 0 # ITB inst hits 511system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 540system.cpu0.dtb.read_hits 12222008 # DTB read hits 541system.cpu0.dtb.read_misses 34799 # DTB read misses 542system.cpu0.dtb.write_hits 5155654 # DTB write hits 543system.cpu0.dtb.write_misses 4970 # DTB write misses | 512system.cpu0.dtb.read_hits 9084255 # DTB read hits 513system.cpu0.dtb.read_misses 36769 # DTB read misses 514system.cpu0.dtb.write_hits 5284576 # DTB write hits 515system.cpu0.dtb.write_misses 6773 # DTB write misses |
| 544system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 545system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 546system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 547system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 516system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 517system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 518system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 519system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 548system.cpu0.dtb.flush_entries 2546 # Number of entries that have been flushed from TLB 549system.cpu0.dtb.align_faults 1270 # Number of TLB faults due to alignment restrictions 550system.cpu0.dtb.prefetch_faults 369 # Number of TLB faults due to prefetch | 520system.cpu0.dtb.flush_entries 2261 # Number of entries that have been flushed from TLB 521system.cpu0.dtb.align_faults 1412 # Number of TLB faults due to alignment restrictions 522system.cpu0.dtb.prefetch_faults 383 # Number of TLB faults due to prefetch |
| 551system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 523system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 552system.cpu0.dtb.perms_faults 661 # Number of TLB faults due to permissions restrictions 553system.cpu0.dtb.read_accesses 12256807 # DTB read accesses 554system.cpu0.dtb.write_accesses 5160624 # DTB write accesses | 524system.cpu0.dtb.perms_faults 588 # Number of TLB faults due to permissions restrictions 525system.cpu0.dtb.read_accesses 9121024 # DTB read accesses 526system.cpu0.dtb.write_accesses 5291349 # DTB write accesses |
| 555system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 527system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 556system.cpu0.dtb.hits 17377662 # DTB hits 557system.cpu0.dtb.misses 39769 # DTB misses 558system.cpu0.dtb.accesses 17417431 # DTB accesses 559system.cpu0.itb.inst_hits 4312814 # ITB inst hits 560system.cpu0.itb.inst_misses 5659 # ITB inst misses | 528system.cpu0.dtb.hits 14368831 # DTB hits 529system.cpu0.dtb.misses 43542 # DTB misses 530system.cpu0.dtb.accesses 14412373 # DTB accesses 531system.cpu0.itb.inst_hits 4421795 # ITB inst hits 532system.cpu0.itb.inst_misses 5958 # ITB inst misses |
| 561system.cpu0.itb.read_hits 0 # DTB read hits 562system.cpu0.itb.read_misses 0 # DTB read misses 563system.cpu0.itb.write_hits 0 # DTB write hits 564system.cpu0.itb.write_misses 0 # DTB write misses 565system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 566system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 567system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 568system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 533system.cpu0.itb.read_hits 0 # DTB read hits 534system.cpu0.itb.read_misses 0 # DTB read misses 535system.cpu0.itb.write_hits 0 # DTB write hits 536system.cpu0.itb.write_misses 0 # DTB write misses 537system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 538system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 539system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 540system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 569system.cpu0.itb.flush_entries 1615 # Number of entries that have been flushed from TLB | 541system.cpu0.itb.flush_entries 1415 # Number of entries that have been flushed from TLB |
| 570system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 571system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 572system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 542system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 543system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 544system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 573system.cpu0.itb.perms_faults 1550 # Number of TLB faults due to permissions restrictions | 545system.cpu0.itb.perms_faults 1713 # Number of TLB faults due to permissions restrictions |
| 574system.cpu0.itb.read_accesses 0 # DTB read accesses 575system.cpu0.itb.write_accesses 0 # DTB write accesses | 546system.cpu0.itb.read_accesses 0 # DTB read accesses 547system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 576system.cpu0.itb.inst_accesses 4318473 # ITB inst accesses 577system.cpu0.itb.hits 4312814 # DTB hits 578system.cpu0.itb.misses 5659 # DTB misses 579system.cpu0.itb.accesses 4318473 # DTB accesses 580system.cpu0.numCycles 91755333 # number of cpu cycles simulated | 548system.cpu0.itb.inst_accesses 4427753 # ITB inst accesses 549system.cpu0.itb.hits 4421795 # DTB hits 550system.cpu0.itb.misses 5958 # DTB misses 551system.cpu0.itb.accesses 4427753 # DTB accesses 552system.cpu0.numCycles 66112093 # number of cpu cycles simulated |
| 581system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 582system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 553system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 554system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 583system.cpu0.BPredUnit.lookups 5952266 # Number of BP lookups 584system.cpu0.BPredUnit.condPredicted 4505075 # Number of conditional branches predicted 585system.cpu0.BPredUnit.condIncorrect 304047 # Number of conditional branches incorrect 586system.cpu0.BPredUnit.BTBLookups 3800923 # Number of BTB lookups 587system.cpu0.BPredUnit.BTBHits 2764349 # Number of BTB hits | 555system.cpu0.BPredUnit.lookups 6172143 # Number of BP lookups 556system.cpu0.BPredUnit.condPredicted 4680207 # Number of conditional branches predicted 557system.cpu0.BPredUnit.condIncorrect 316413 # Number of conditional branches incorrect 558system.cpu0.BPredUnit.BTBLookups 3902841 # Number of BTB lookups 559system.cpu0.BPredUnit.BTBHits 2861272 # Number of BTB hits |
| 588system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 560system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 589system.cpu0.BPredUnit.usedRAS 686219 # Number of times the RAS was used to get a target. 590system.cpu0.BPredUnit.RASInCorrect 29965 # Number of incorrect RAS predictions. 591system.cpu0.fetch.icacheStallCycles 12225669 # Number of cycles fetch is stalled on an Icache miss 592system.cpu0.fetch.Insts 31634782 # Number of instructions fetch has processed 593system.cpu0.fetch.Branches 5952266 # Number of branches that fetch encountered 594system.cpu0.fetch.predictedBranches 3450568 # Number of branches that fetch has predicted taken 595system.cpu0.fetch.Cycles 7438203 # Number of cycles fetch has run and was not squashing or blocked 596system.cpu0.fetch.SquashCycles 1498517 # Number of cycles fetch has spent squashing 597system.cpu0.fetch.TlbCycles 86111 # Number of cycles fetch has spent waiting for tlb 598system.cpu0.fetch.BlockedCycles 25429329 # Number of cycles fetch has spent blocked 599system.cpu0.fetch.MiscStallCycles 5796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 600system.cpu0.fetch.PendingTrapStallCycles 56004 # Number of stall cycles due to pending traps 601system.cpu0.fetch.PendingQuiesceStallCycles 89121 # Number of stall cycles due to pending quiesce instructions 602system.cpu0.fetch.IcacheWaitRetryStallCycles 253 # Number of stall cycles due to full MSHR 603system.cpu0.fetch.CacheLines 4310960 # Number of cache lines fetched 604system.cpu0.fetch.IcacheSquashes 168036 # Number of outstanding Icache misses that were squashed 605system.cpu0.fetch.ItlbSquashes 2895 # Number of outstanding ITLB misses that were squashed 606system.cpu0.fetch.rateDist::samples 46396814 # Number of instructions fetched each cycle (Total) 607system.cpu0.fetch.rateDist::mean 0.887686 # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.rateDist::stdev 2.274992 # Number of instructions fetched each cycle (Total) | 561system.cpu0.BPredUnit.usedRAS 700420 # Number of times the RAS was used to get a target. 562system.cpu0.BPredUnit.RASInCorrect 30889 # Number of incorrect RAS predictions. 563system.cpu0.fetch.icacheStallCycles 12972431 # Number of cycles fetch is stalled on an Icache miss 564system.cpu0.fetch.Insts 32579396 # Number of instructions fetch has processed 565system.cpu0.fetch.Branches 6172143 # Number of branches that fetch encountered 566system.cpu0.fetch.predictedBranches 3561692 # Number of branches that fetch has predicted taken 567system.cpu0.fetch.Cycles 7636967 # Number of cycles fetch has run and was not squashing or blocked 568system.cpu0.fetch.SquashCycles 1568394 # Number of cycles fetch has spent squashing 569system.cpu0.fetch.TlbCycles 92289 # Number of cycles fetch has spent waiting for tlb 570system.cpu0.fetch.BlockedCycles 21876805 # Number of cycles fetch has spent blocked 571system.cpu0.fetch.MiscStallCycles 5742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 572system.cpu0.fetch.PendingTrapStallCycles 73340 # Number of stall cycles due to pending traps 573system.cpu0.fetch.PendingQuiesceStallCycles 91549 # Number of stall cycles due to pending quiesce instructions 574system.cpu0.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR 575system.cpu0.fetch.CacheLines 4419869 # Number of cache lines fetched 576system.cpu0.fetch.IcacheSquashes 175391 # Number of outstanding Icache misses that were squashed 577system.cpu0.fetch.ItlbSquashes 2999 # Number of outstanding ITLB misses that were squashed 578system.cpu0.fetch.rateDist::samples 43870869 # Number of instructions fetched each cycle (Total) 579system.cpu0.fetch.rateDist::mean 0.963501 # Number of instructions fetched each cycle (Total) 580system.cpu0.fetch.rateDist::stdev 2.353712 # Number of instructions fetched each cycle (Total) |
| 609system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 581system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 610system.cpu0.fetch.rateDist::0 38966492 83.99% 83.99% # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.rateDist::1 608768 1.31% 85.30% # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::2 793531 1.71% 87.01% # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::3 678621 1.46% 88.47% # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::4 615872 1.33% 89.80% # Number of instructions fetched each cycle (Total) 615system.cpu0.fetch.rateDist::5 550838 1.19% 90.98% # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.rateDist::6 680018 1.47% 92.45% # Number of instructions fetched each cycle (Total) 617system.cpu0.fetch.rateDist::7 365085 0.79% 93.24% # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::8 3137589 6.76% 100.00% # Number of instructions fetched each cycle (Total) | 582system.cpu0.fetch.rateDist::0 36242473 82.61% 82.61% # Number of instructions fetched each cycle (Total) 583system.cpu0.fetch.rateDist::1 623814 1.42% 84.03% # Number of instructions fetched each cycle (Total) 584system.cpu0.fetch.rateDist::2 820212 1.87% 85.90% # Number of instructions fetched each cycle (Total) 585system.cpu0.fetch.rateDist::3 686089 1.56% 87.47% # Number of instructions fetched each cycle (Total) 586system.cpu0.fetch.rateDist::4 622737 1.42% 88.89% # Number of instructions fetched each cycle (Total) 587system.cpu0.fetch.rateDist::5 578948 1.32% 90.21% # Number of instructions fetched each cycle (Total) 588system.cpu0.fetch.rateDist::6 720296 1.64% 91.85% # Number of instructions fetched each cycle (Total) 589system.cpu0.fetch.rateDist::7 370745 0.85% 92.69% # Number of instructions fetched each cycle (Total) 590system.cpu0.fetch.rateDist::8 3205555 7.31% 100.00% # Number of instructions fetched each cycle (Total) |
| 619system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 620system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 621system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 591system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 592system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 593system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 622system.cpu0.fetch.rateDist::total 46396814 # Number of instructions fetched each cycle (Total) 623system.cpu0.fetch.branchRate 0.064871 # Number of branch fetches per cycle 624system.cpu0.fetch.rate 0.344773 # Number of inst fetches per cycle 625system.cpu0.decode.IdleCycles 12690058 # Number of cycles decode is idle 626system.cpu0.decode.BlockedCycles 25456221 # Number of cycles decode is blocked 627system.cpu0.decode.RunCycles 6703467 # Number of cycles decode is running 628system.cpu0.decode.UnblockCycles 545759 # Number of cycles decode is unblocking 629system.cpu0.decode.SquashCycles 1001309 # Number of cycles decode is squashing 630system.cpu0.decode.BranchResolved 958631 # Number of times decode resolved a branch 631system.cpu0.decode.BranchMispred 66338 # Number of times decode detected a branch misprediction 632system.cpu0.decode.DecodedInsts 39766150 # Number of instructions handled by decode 633system.cpu0.decode.SquashedInsts 219028 # Number of squashed instructions handled by decode 634system.cpu0.rename.SquashCycles 1001309 # Number of cycles rename is squashing 635system.cpu0.rename.IdleCycles 13289637 # Number of cycles rename is idle 636system.cpu0.rename.BlockCycles 7972865 # Number of cycles rename is blocking 637system.cpu0.rename.serializeStallCycles 15343248 # count of cycles rename stalled for serializing inst 638system.cpu0.rename.RunCycles 6631332 # Number of cycles rename is running 639system.cpu0.rename.UnblockCycles 2158423 # Number of cycles rename is unblocking 640system.cpu0.rename.RenamedInsts 38589176 # Number of instructions processed by rename 641system.cpu0.rename.ROBFullEvents 848 # Number of times rename has blocked due to ROB full 642system.cpu0.rename.IQFullEvents 416461 # Number of times rename has blocked due to IQ full 643system.cpu0.rename.LSQFullEvents 1242307 # Number of times rename has blocked due to LSQ full 644system.cpu0.rename.FullRegisterEvents 106 # Number of times there has been no free registers 645system.cpu0.rename.RenamedOperands 38596643 # Number of destination operands rename has renamed 646system.cpu0.rename.RenameLookups 175113710 # Number of register rename lookups that rename has made 647system.cpu0.rename.int_rename_lookups 175069465 # Number of integer rename lookups 648system.cpu0.rename.fp_rename_lookups 44245 # Number of floating rename lookups 649system.cpu0.rename.CommittedMaps 30775876 # Number of HB maps that are committed 650system.cpu0.rename.UndoneMaps 7820767 # Number of HB maps that are undone due to squashing 651system.cpu0.rename.serializingInsts 452714 # count of serializing insts renamed 652system.cpu0.rename.tempSerializingInsts 409285 # count of temporary serializing insts renamed 653system.cpu0.rename.skidInsts 5195885 # count of insts added to the skid buffer 654system.cpu0.memDep0.insertedLoads 7781233 # Number of loads inserted to the mem dependence unit. 655system.cpu0.memDep0.insertedStores 5757511 # Number of stores inserted to the mem dependence unit. 656system.cpu0.memDep0.conflictingLoads 1120127 # Number of conflicting loads. 657system.cpu0.memDep0.conflictingStores 1192401 # Number of conflicting stores. 658system.cpu0.iq.iqInstsAdded 36577178 # Number of instructions added to the IQ (excludes non-spec) 659system.cpu0.iq.iqNonSpecInstsAdded 791583 # Number of non-speculative instructions added to the IQ 660system.cpu0.iq.iqInstsIssued 40176979 # Number of instructions issued 661system.cpu0.iq.iqSquashedInstsIssued 83237 # Number of squashed instructions issued 662system.cpu0.iq.iqSquashedInstsExamined 5967561 # Number of squashed instructions iterated over during squash; mainly for profiling 663system.cpu0.iq.iqSquashedOperandsExamined 13599049 # Number of squashed operands that are examined and possibly removed from graph 664system.cpu0.iq.iqSquashedNonSpecRemoved 145097 # Number of squashed non-spec instructions that were removed 665system.cpu0.iq.issued_per_cycle::samples 46396814 # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::mean 0.865943 # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::stdev 1.513269 # Number of insts issued each cycle | 594system.cpu0.fetch.rateDist::total 43870869 # Number of instructions fetched each cycle (Total) 595system.cpu0.fetch.branchRate 0.093359 # Number of branch fetches per cycle 596system.cpu0.fetch.rate 0.492790 # Number of inst fetches per cycle 597system.cpu0.decode.IdleCycles 13461534 # Number of cycles decode is idle 598system.cpu0.decode.BlockedCycles 21912526 # Number of cycles decode is blocked 599system.cpu0.decode.RunCycles 6836712 # Number of cycles decode is running 600system.cpu0.decode.UnblockCycles 603785 # Number of cycles decode is unblocking 601system.cpu0.decode.SquashCycles 1056312 # Number of cycles decode is squashing 602system.cpu0.decode.BranchResolved 995110 # Number of times decode resolved a branch 603system.cpu0.decode.BranchMispred 66550 # Number of times decode detected a branch misprediction 604system.cpu0.decode.DecodedInsts 40827533 # Number of instructions handled by decode 605system.cpu0.decode.SquashedInsts 217718 # Number of squashed instructions handled by decode 606system.cpu0.rename.SquashCycles 1056312 # Number of cycles rename is squashing 607system.cpu0.rename.IdleCycles 14066817 # Number of cycles rename is idle 608system.cpu0.rename.BlockCycles 6153021 # Number of cycles rename is blocking 609system.cpu0.rename.serializeStallCycles 13456769 # count of cycles rename stalled for serializing inst 610system.cpu0.rename.RunCycles 6788701 # Number of cycles rename is running 611system.cpu0.rename.UnblockCycles 2349249 # Number of cycles rename is unblocking 612system.cpu0.rename.RenamedInsts 39593607 # Number of instructions processed by rename 613system.cpu0.rename.ROBFullEvents 1040 # Number of times rename has blocked due to ROB full 614system.cpu0.rename.IQFullEvents 472233 # Number of times rename has blocked due to IQ full 615system.cpu0.rename.LSQFullEvents 1335984 # Number of times rename has blocked due to LSQ full 616system.cpu0.rename.FullRegisterEvents 103 # Number of times there has been no free registers 617system.cpu0.rename.RenamedOperands 39791095 # Number of destination operands rename has renamed 618system.cpu0.rename.RenameLookups 179675714 # Number of register rename lookups that rename has made 619system.cpu0.rename.int_rename_lookups 179640853 # Number of integer rename lookups 620system.cpu0.rename.fp_rename_lookups 34861 # Number of floating rename lookups 621system.cpu0.rename.CommittedMaps 31537071 # Number of HB maps that are committed 622system.cpu0.rename.UndoneMaps 8254023 # Number of HB maps that are undone due to squashing 623system.cpu0.rename.serializingInsts 463697 # count of serializing insts renamed 624system.cpu0.rename.tempSerializingInsts 419128 # count of temporary serializing insts renamed 625system.cpu0.rename.skidInsts 5673165 # count of insts added to the skid buffer 626system.cpu0.memDep0.insertedLoads 7928571 # Number of loads inserted to the mem dependence unit. 627system.cpu0.memDep0.insertedStores 5881726 # Number of stores inserted to the mem dependence unit. 628system.cpu0.memDep0.conflictingLoads 1132931 # Number of conflicting loads. 629system.cpu0.memDep0.conflictingStores 1238845 # Number of conflicting stores. 630system.cpu0.iq.iqInstsAdded 37538443 # Number of instructions added to the IQ (excludes non-spec) 631system.cpu0.iq.iqNonSpecInstsAdded 794373 # Number of non-speculative instructions added to the IQ 632system.cpu0.iq.iqInstsIssued 37739879 # Number of instructions issued 633system.cpu0.iq.iqSquashedInstsIssued 92690 # Number of squashed instructions issued 634system.cpu0.iq.iqSquashedInstsExamined 6264606 # Number of squashed instructions iterated over during squash; mainly for profiling 635system.cpu0.iq.iqSquashedOperandsExamined 14354053 # Number of squashed operands that are examined and possibly removed from graph 636system.cpu0.iq.iqSquashedNonSpecRemoved 137507 # Number of squashed non-spec instructions that were removed 637system.cpu0.iq.issued_per_cycle::samples 43870869 # Number of insts issued each cycle 638system.cpu0.iq.issued_per_cycle::mean 0.860249 # Number of insts issued each cycle 639system.cpu0.iq.issued_per_cycle::stdev 1.478315 # Number of insts issued each cycle |
| 668system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 640system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 669system.cpu0.iq.issued_per_cycle::0 30520128 65.78% 65.78% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::1 5937185 12.80% 78.58% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::2 3046653 6.57% 85.14% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::3 2264959 4.88% 90.03% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::4 2893477 6.24% 96.26% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::5 928258 2.00% 98.26% # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::6 563400 1.21% 99.48% # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::7 186019 0.40% 99.88% # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::8 56735 0.12% 100.00% # Number of insts issued each cycle | 641system.cpu0.iq.issued_per_cycle::0 28164784 64.20% 64.20% # Number of insts issued each cycle 642system.cpu0.iq.issued_per_cycle::1 6326126 14.42% 78.62% # Number of insts issued each cycle 643system.cpu0.iq.issued_per_cycle::2 3234526 7.37% 85.99% # Number of insts issued each cycle 644system.cpu0.iq.issued_per_cycle::3 2361316 5.38% 91.37% # Number of insts issued each cycle 645system.cpu0.iq.issued_per_cycle::4 2098246 4.78% 96.16% # Number of insts issued each cycle 646system.cpu0.iq.issued_per_cycle::5 936106 2.13% 98.29% # Number of insts issued each cycle 647system.cpu0.iq.issued_per_cycle::6 514694 1.17% 99.46% # Number of insts issued each cycle 648system.cpu0.iq.issued_per_cycle::7 181493 0.41% 99.88% # Number of insts issued each cycle 649system.cpu0.iq.issued_per_cycle::8 53578 0.12% 100.00% # Number of insts issued each cycle |
| 678system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 679system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 680system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 650system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 651system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 652system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 681system.cpu0.iq.issued_per_cycle::total 46396814 # Number of insts issued each cycle | 653system.cpu0.iq.issued_per_cycle::total 43870869 # Number of insts issued each cycle |
| 682system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 654system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 683system.cpu0.iq.fu_full::IntAlu 26385 1.46% 1.46% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IntMult 453 0.03% 1.49% # attempts to use FU when none available 685system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.49% # attempts to use FU when none available 686system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.49% # attempts to use FU when none available 687system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.49% # attempts to use FU when none available 688system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.49% # attempts to use FU when none available 689system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.49% # attempts to use FU when none available 690system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.49% # attempts to use FU when none available 691system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.49% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.49% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.49% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.49% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.49% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.49% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.49% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.49% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.49% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.49% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.49% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.49% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.49% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.49% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.49% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.49% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.49% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.49% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.49% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.49% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.49% # attempts to use FU when none available 712system.cpu0.iq.fu_full::MemRead 1567613 86.92% 88.41% # attempts to use FU when none available 713system.cpu0.iq.fu_full::MemWrite 209022 11.59% 100.00% # attempts to use FU when none available | 655system.cpu0.iq.fu_full::IntAlu 27565 2.58% 2.58% # attempts to use FU when none available 656system.cpu0.iq.fu_full::IntMult 466 0.04% 2.62% # attempts to use FU when none available 657system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available 658system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available 659system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available 660system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available 661system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available 662system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available 663system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available 664system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available 665system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available 666system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available 667system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available 668system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available 669system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available 670system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available 671system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available 672system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available 673system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available 674system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available 675system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available 676system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available 677system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available 678system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available 679system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available 680system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available 681system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available 682system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available 683system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available 684system.cpu0.iq.fu_full::MemRead 837939 78.44% 81.06% # attempts to use FU when none available 685system.cpu0.iq.fu_full::MemWrite 202337 18.94% 100.00% # attempts to use FU when none available |
| 714system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 715system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 686system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 687system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 716system.cpu0.iq.FU_type_0::No_OpClass 25309 0.06% 0.06% # Type of FU issued 717system.cpu0.iq.FU_type_0::IntAlu 21935197 54.60% 54.66% # Type of FU issued 718system.cpu0.iq.FU_type_0::IntMult 48039 0.12% 54.78% # Type of FU issued 719system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 54.78% # Type of FU issued 720system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 54.78% # Type of FU issued 721system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 54.78% # Type of FU issued 722system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 54.78% # Type of FU issued 723system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 54.78% # Type of FU issued 724system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 54.78% # Type of FU issued 725system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 54.78% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 54.78% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 54.78% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 54.78% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 54.78% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 54.78% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 54.78% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 54.78% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 54.78% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 54.78% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 54.78% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 54.78% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.78% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.78% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.78% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.78% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.78% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdFloatMisc 725 0.00% 54.78% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 54.78% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 54.78% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.78% # Type of FU issued 746system.cpu0.iq.FU_type_0::MemRead 12687286 31.58% 86.36% # Type of FU issued 747system.cpu0.iq.FU_type_0::MemWrite 5480393 13.64% 100.00% # Type of FU issued | 688system.cpu0.iq.FU_type_0::No_OpClass 20407 0.05% 0.05% # Type of FU issued 689system.cpu0.iq.FU_type_0::IntAlu 22494595 59.60% 59.66% # Type of FU issued 690system.cpu0.iq.FU_type_0::IntMult 50051 0.13% 59.79% # Type of FU issued 691system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.79% # Type of FU issued 692system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.79% # Type of FU issued 693system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.79% # Type of FU issued 694system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.79% # Type of FU issued 695system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.79% # Type of FU issued 696system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued 697system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued 698system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued 699system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued 700system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 59.79% # Type of FU issued 701system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued 702system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued 703system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.79% # Type of FU issued 704system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued 705system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued 706system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 59.79% # Type of FU issued 707system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.79% # Type of FU issued 708system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued 709system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued 710system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued 711system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued 712system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued 713system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued 714system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 59.79% # Type of FU issued 715system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued 716system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.79% # Type of FU issued 717system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued 718system.cpu0.iq.FU_type_0::MemRead 9563453 25.34% 85.13% # Type of FU issued 719system.cpu0.iq.FU_type_0::MemWrite 5610668 14.87% 100.00% # Type of FU issued |
| 748system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 749system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 720system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 721system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 750system.cpu0.iq.FU_type_0::total 40176979 # Type of FU issued 751system.cpu0.iq.rate 0.437871 # Inst issue rate 752system.cpu0.iq.fu_busy_cnt 1803473 # FU busy when requested 753system.cpu0.iq.fu_busy_rate 0.044888 # FU busy rate (busy events/executed inst) 754system.cpu0.iq.int_inst_queue_reads 128665759 # Number of integer instruction queue reads 755system.cpu0.iq.int_inst_queue_writes 43343315 # Number of integer instruction queue writes 756system.cpu0.iq.int_inst_queue_wakeup_accesses 34031138 # Number of integer instruction queue wakeup accesses 757system.cpu0.iq.fp_inst_queue_reads 11205 # Number of floating instruction queue reads 758system.cpu0.iq.fp_inst_queue_writes 6096 # Number of floating instruction queue writes 759system.cpu0.iq.fp_inst_queue_wakeup_accesses 4927 # Number of floating instruction queue wakeup accesses 760system.cpu0.iq.int_alu_accesses 41949154 # Number of integer alu accesses 761system.cpu0.iq.fp_alu_accesses 5989 # Number of floating point alu accesses 762system.cpu0.iew.lsq.thread0.forwLoads 311358 # Number of loads that had data forwarded from stores | 722system.cpu0.iq.FU_type_0::total 37739879 # Type of FU issued 723system.cpu0.iq.rate 0.570847 # Inst issue rate 724system.cpu0.iq.fu_busy_cnt 1068307 # FU busy when requested 725system.cpu0.iq.fu_busy_rate 0.028307 # FU busy rate (busy events/executed inst) 726system.cpu0.iq.int_inst_queue_reads 120546534 # Number of integer instruction queue reads 727system.cpu0.iq.int_inst_queue_writes 44606042 # Number of integer instruction queue writes 728system.cpu0.iq.int_inst_queue_wakeup_accesses 34820056 # Number of integer instruction queue wakeup accesses 729system.cpu0.iq.fp_inst_queue_reads 8333 # Number of floating instruction queue reads 730system.cpu0.iq.fp_inst_queue_writes 4740 # Number of floating instruction queue writes 731system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses 732system.cpu0.iq.int_alu_accesses 38783456 # Number of integer alu accesses 733system.cpu0.iq.fp_alu_accesses 4323 # Number of floating point alu accesses 734system.cpu0.iew.lsq.thread0.forwLoads 326383 # Number of loads that had data forwarded from stores |
| 763system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 735system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 764system.cpu0.iew.lsq.thread0.squashedLoads 1414489 # Number of loads squashed 765system.cpu0.iew.lsq.thread0.ignoredResponses 4027 # Number of memory responses ignored because the instruction is squashed 766system.cpu0.iew.lsq.thread0.memOrderViolation 13694 # Number of memory ordering violations 767system.cpu0.iew.lsq.thread0.squashedStores 607908 # Number of stores squashed | 736system.cpu0.iew.lsq.thread0.squashedLoads 1507630 # Number of loads squashed 737system.cpu0.iew.lsq.thread0.ignoredResponses 4080 # Number of memory responses ignored because the instruction is squashed 738system.cpu0.iew.lsq.thread0.memOrderViolation 13930 # Number of memory ordering violations 739system.cpu0.iew.lsq.thread0.squashedStores 608245 # Number of stores squashed |
| 768system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 769system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 740system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 741system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 770system.cpu0.iew.lsq.thread0.rescheduledLoads 5397304 # Number of loads that were rescheduled 771system.cpu0.iew.lsq.thread0.cacheBlocked 5188 # Number of times an access to memory failed due to the cache being blocked | 742system.cpu0.iew.lsq.thread0.rescheduledLoads 2149509 # Number of loads that were rescheduled 743system.cpu0.iew.lsq.thread0.cacheBlocked 5404 # Number of times an access to memory failed due to the cache being blocked |
| 772system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 744system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 773system.cpu0.iew.iewSquashCycles 1001309 # Number of cycles IEW is squashing 774system.cpu0.iew.iewBlockCycles 6077720 # Number of cycles IEW is blocking 775system.cpu0.iew.iewUnblockCycles 124694 # Number of cycles IEW is unblocking 776system.cpu0.iew.iewDispatchedInsts 37485087 # Number of instructions dispatched to IQ 777system.cpu0.iew.iewDispSquashedInsts 95046 # Number of squashed instructions skipped by dispatch 778system.cpu0.iew.iewDispLoadInsts 7781233 # Number of dispatched load instructions 779system.cpu0.iew.iewDispStoreInsts 5757511 # Number of dispatched store instructions 780system.cpu0.iew.iewDispNonSpecInsts 467034 # Number of dispatched non-speculative instructions 781system.cpu0.iew.iewIQFullEvents 52649 # Number of times the IQ has become full, causing a stall 782system.cpu0.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall 783system.cpu0.iew.memOrderViolationEvents 13694 # Number of memory order violations 784system.cpu0.iew.predictedTakenIncorrect 153875 # Number of branches that were predicted taken incorrectly 785system.cpu0.iew.predictedNotTakenIncorrect 138964 # Number of branches that were predicted not taken incorrectly 786system.cpu0.iew.branchMispredicts 292839 # Number of branch mispredicts detected at execute 787system.cpu0.iew.iewExecutedInsts 39778235 # Number of executed instructions 788system.cpu0.iew.iewExecLoadInsts 12530314 # Number of load instructions executed 789system.cpu0.iew.iewExecSquashedInsts 398744 # Number of squashed instructions skipped in execute | 745system.cpu0.iew.iewSquashCycles 1056312 # Number of cycles IEW is squashing 746system.cpu0.iew.iewBlockCycles 4064319 # Number of cycles IEW is blocking 747system.cpu0.iew.iewUnblockCycles 129740 # Number of cycles IEW is unblocking 748system.cpu0.iew.iewDispatchedInsts 38471177 # Number of instructions dispatched to IQ 749system.cpu0.iew.iewDispSquashedInsts 88757 # Number of squashed instructions skipped by dispatch 750system.cpu0.iew.iewDispLoadInsts 7928571 # Number of dispatched load instructions 751system.cpu0.iew.iewDispStoreInsts 5881726 # Number of dispatched store instructions 752system.cpu0.iew.iewDispNonSpecInsts 461616 # Number of dispatched non-speculative instructions 753system.cpu0.iew.iewIQFullEvents 49674 # Number of times the IQ has become full, causing a stall 754system.cpu0.iew.iewLSQFullEvents 17745 # Number of times the LSQ has become full, causing a stall 755system.cpu0.iew.memOrderViolationEvents 13930 # Number of memory order violations 756system.cpu0.iew.predictedTakenIncorrect 159357 # Number of branches that were predicted taken incorrectly 757system.cpu0.iew.predictedNotTakenIncorrect 144737 # Number of branches that were predicted not taken incorrectly 758system.cpu0.iew.branchMispredicts 304094 # Number of branch mispredicts detected at execute 759system.cpu0.iew.iewExecutedInsts 37337331 # Number of executed instructions 760system.cpu0.iew.iewExecLoadInsts 9402148 # Number of load instructions executed 761system.cpu0.iew.iewExecSquashedInsts 402548 # Number of squashed instructions skipped in execute |
| 790system.cpu0.iew.exec_swp 0 # number of swp insts executed | 762system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 791system.cpu0.iew.exec_nop 116326 # number of nop insts executed 792system.cpu0.iew.exec_refs 17957262 # number of memory reference insts executed 793system.cpu0.iew.exec_branches 4780864 # Number of branches executed 794system.cpu0.iew.exec_stores 5426948 # Number of stores executed 795system.cpu0.iew.exec_rate 0.433525 # Inst execution rate 796system.cpu0.iew.wb_sent 39572300 # cumulative count of insts sent to commit 797system.cpu0.iew.wb_count 34036065 # cumulative count of insts written-back 798system.cpu0.iew.wb_producers 18213937 # num instructions producing a value 799system.cpu0.iew.wb_consumers 35297892 # num instructions consuming a value | 763system.cpu0.iew.exec_nop 138361 # number of nop insts executed 764system.cpu0.iew.exec_refs 14958639 # number of memory reference insts executed 765system.cpu0.iew.exec_branches 4921687 # Number of branches executed 766system.cpu0.iew.exec_stores 5556491 # Number of stores executed 767system.cpu0.iew.exec_rate 0.564758 # Inst execution rate 768system.cpu0.iew.wb_sent 37117116 # cumulative count of insts sent to commit 769system.cpu0.iew.wb_count 34823949 # cumulative count of insts written-back 770system.cpu0.iew.wb_producers 18360594 # num instructions producing a value 771system.cpu0.iew.wb_consumers 34980725 # num instructions consuming a value |
| 800system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 772system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 801system.cpu0.iew.wb_rate 0.370944 # insts written-back per cycle 802system.cpu0.iew.wb_fanout 0.516006 # average fanout of values written-back | 773system.cpu0.iew.wb_rate 0.526741 # insts written-back per cycle 774system.cpu0.iew.wb_fanout 0.524877 # average fanout of values written-back |
| 803system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 775system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 804system.cpu0.commit.commitCommittedInsts 23601687 # The number of committed instructions 805system.cpu0.commit.commitCommittedOps 31186721 # The number of committed instructions 806system.cpu0.commit.commitSquashedInsts 6143896 # The number of squashed insts skipped by commit 807system.cpu0.commit.commitNonSpecStalls 646486 # The number of times commit has been forced to stall to communicate backwards 808system.cpu0.commit.branchMispredicts 256571 # The number of times a branch was mispredicted 809system.cpu0.commit.committed_per_cycle::samples 45430638 # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::mean 0.686469 # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::stdev 1.654503 # Number of insts commited each cycle | 776system.cpu0.commit.commitCommittedInsts 24134633 # The number of committed instructions 777system.cpu0.commit.commitCommittedOps 31866160 # The number of committed instructions 778system.cpu0.commit.commitSquashedInsts 6466683 # The number of squashed insts skipped by commit 779system.cpu0.commit.commitNonSpecStalls 656866 # The number of times commit has been forced to stall to communicate backwards 780system.cpu0.commit.branchMispredicts 267750 # The number of times a branch was mispredicted 781system.cpu0.commit.committed_per_cycle::samples 42850944 # Number of insts commited each cycle 782system.cpu0.commit.committed_per_cycle::mean 0.743651 # Number of insts commited each cycle 783system.cpu0.commit.committed_per_cycle::stdev 1.697776 # Number of insts commited each cycle |
| 812system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 784system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 813system.cpu0.commit.committed_per_cycle::0 33717084 74.22% 74.22% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::1 5850006 12.88% 87.09% # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::2 1884843 4.15% 91.24% # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::3 960822 2.11% 93.36% # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::4 731888 1.61% 94.97% # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::5 454898 1.00% 95.97% # Number of insts commited each cycle 819system.cpu0.commit.committed_per_cycle::6 476885 1.05% 97.02% # Number of insts commited each cycle 820system.cpu0.commit.committed_per_cycle::7 212485 0.47% 97.49% # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::8 1141727 2.51% 100.00% # Number of insts commited each cycle | 785system.cpu0.commit.committed_per_cycle::0 30739496 71.74% 71.74% # Number of insts commited each cycle 786system.cpu0.commit.committed_per_cycle::1 6075340 14.18% 85.91% # Number of insts commited each cycle 787system.cpu0.commit.committed_per_cycle::2 1944692 4.54% 90.45% # Number of insts commited each cycle 788system.cpu0.commit.committed_per_cycle::3 1041937 2.43% 92.88% # Number of insts commited each cycle 789system.cpu0.commit.committed_per_cycle::4 773699 1.81% 94.69% # Number of insts commited each cycle 790system.cpu0.commit.committed_per_cycle::5 503770 1.18% 95.86% # Number of insts commited each cycle 791system.cpu0.commit.committed_per_cycle::6 405337 0.95% 96.81% # Number of insts commited each cycle 792system.cpu0.commit.committed_per_cycle::7 203427 0.47% 97.29% # Number of insts commited each cycle 793system.cpu0.commit.committed_per_cycle::8 1163246 2.71% 100.00% # Number of insts commited each cycle |
| 822system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 823system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 794system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 795system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 796system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 825system.cpu0.commit.committed_per_cycle::total 45430638 # Number of insts commited each cycle 826system.cpu0.commit.committedInsts 23601687 # Number of instructions committed 827system.cpu0.commit.committedOps 31186721 # Number of ops (including micro ops) committed | 797system.cpu0.commit.committed_per_cycle::total 42850944 # Number of insts commited each cycle 798system.cpu0.commit.committedInsts 24134633 # Number of instructions committed 799system.cpu0.commit.committedOps 31866160 # Number of ops (including micro ops) committed |
| 828system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 800system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 829system.cpu0.commit.refs 11516347 # Number of memory references committed 830system.cpu0.commit.loads 6366744 # Number of loads committed 831system.cpu0.commit.membars 228774 # Number of memory barriers committed 832system.cpu0.commit.branches 4268909 # Number of branches committed 833system.cpu0.commit.fp_insts 4838 # Number of committed floating point instructions. 834system.cpu0.commit.int_insts 27636133 # Number of committed integer instructions. 835system.cpu0.commit.function_calls 492618 # Number of function calls committed. 836system.cpu0.commit.bw_lim_events 1141727 # number cycles where commit BW limit reached | 801system.cpu0.commit.refs 11694422 # Number of memory references committed 802system.cpu0.commit.loads 6420941 # Number of loads committed 803system.cpu0.commit.membars 234529 # Number of memory barriers committed 804system.cpu0.commit.branches 4382702 # Number of branches committed 805system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 806system.cpu0.commit.int_insts 28193395 # Number of committed integer instructions. 807system.cpu0.commit.function_calls 499856 # Number of function calls committed. 808system.cpu0.commit.bw_lim_events 1163246 # number cycles where commit BW limit reached |
| 837system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 809system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 838system.cpu0.rob.rob_reads 80832744 # The number of ROB reads 839system.cpu0.rob.rob_writes 75665562 # The number of ROB writes 840system.cpu0.timesIdled 511317 # Number of times that the entire CPU went into an idle state and unscheduled itself 841system.cpu0.idleCycles 45358519 # Total number of cycles that the CPU has spent unscheduled due to idling 842system.cpu0.quiesceCycles 5047039822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 843system.cpu0.committedInsts 23536584 # Number of Instructions Simulated 844system.cpu0.committedOps 31121618 # Number of Ops (including micro ops) Simulated 845system.cpu0.committedInsts_total 23536584 # Number of Instructions Simulated 846system.cpu0.cpi 3.898413 # CPI: Cycles Per Instruction 847system.cpu0.cpi_total 3.898413 # CPI: Total CPI of All Threads 848system.cpu0.ipc 0.256515 # IPC: Instructions Per Cycle 849system.cpu0.ipc_total 0.256515 # IPC: Total IPC of All Threads 850system.cpu0.int_regfile_reads 183926116 # number of integer regfile reads 851system.cpu0.int_regfile_writes 33429350 # number of integer regfile writes 852system.cpu0.fp_regfile_reads 4511 # number of floating regfile reads 853system.cpu0.fp_regfile_writes 934 # number of floating regfile writes 854system.cpu0.misc_regfile_reads 45525801 # number of misc regfile reads 855system.cpu0.misc_regfile_writes 515221 # number of misc regfile writes 856system.cpu0.icache.replacements 402234 # number of replacements 857system.cpu0.icache.tagsinuse 511.630403 # Cycle average of tags in use 858system.cpu0.icache.total_refs 3875529 # Total number of references to valid blocks. 859system.cpu0.icache.sampled_refs 402746 # Sample count of references to valid blocks. 860system.cpu0.icache.avg_refs 9.622762 # Average number of references to valid blocks. 861system.cpu0.icache.warmup_cycle 6260006000 # Cycle when the warmup percentage was hit. 862system.cpu0.icache.occ_blocks::cpu0.inst 511.630403 # Average occupied blocks per requestor 863system.cpu0.icache.occ_percent::cpu0.inst 0.999278 # Average percentage of cache occupancy 864system.cpu0.icache.occ_percent::total 0.999278 # Average percentage of cache occupancy 865system.cpu0.icache.ReadReq_hits::cpu0.inst 3875529 # number of ReadReq hits 866system.cpu0.icache.ReadReq_hits::total 3875529 # number of ReadReq hits 867system.cpu0.icache.demand_hits::cpu0.inst 3875529 # number of demand (read+write) hits 868system.cpu0.icache.demand_hits::total 3875529 # number of demand (read+write) hits 869system.cpu0.icache.overall_hits::cpu0.inst 3875529 # number of overall hits 870system.cpu0.icache.overall_hits::total 3875529 # number of overall hits 871system.cpu0.icache.ReadReq_misses::cpu0.inst 435289 # number of ReadReq misses 872system.cpu0.icache.ReadReq_misses::total 435289 # number of ReadReq misses 873system.cpu0.icache.demand_misses::cpu0.inst 435289 # number of demand (read+write) misses 874system.cpu0.icache.demand_misses::total 435289 # number of demand (read+write) misses 875system.cpu0.icache.overall_misses::cpu0.inst 435289 # number of overall misses 876system.cpu0.icache.overall_misses::total 435289 # number of overall misses 877system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6419795491 # number of ReadReq miss cycles 878system.cpu0.icache.ReadReq_miss_latency::total 6419795491 # number of ReadReq miss cycles 879system.cpu0.icache.demand_miss_latency::cpu0.inst 6419795491 # number of demand (read+write) miss cycles 880system.cpu0.icache.demand_miss_latency::total 6419795491 # number of demand (read+write) miss cycles 881system.cpu0.icache.overall_miss_latency::cpu0.inst 6419795491 # number of overall miss cycles 882system.cpu0.icache.overall_miss_latency::total 6419795491 # number of overall miss cycles 883system.cpu0.icache.ReadReq_accesses::cpu0.inst 4310818 # number of ReadReq accesses(hits+misses) 884system.cpu0.icache.ReadReq_accesses::total 4310818 # number of ReadReq accesses(hits+misses) 885system.cpu0.icache.demand_accesses::cpu0.inst 4310818 # number of demand (read+write) accesses 886system.cpu0.icache.demand_accesses::total 4310818 # number of demand (read+write) accesses 887system.cpu0.icache.overall_accesses::cpu0.inst 4310818 # number of overall (read+write) accesses 888system.cpu0.icache.overall_accesses::total 4310818 # number of overall (read+write) accesses 889system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100976 # miss rate for ReadReq accesses 890system.cpu0.icache.ReadReq_miss_rate::total 0.100976 # miss rate for ReadReq accesses 891system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100976 # miss rate for demand accesses 892system.cpu0.icache.demand_miss_rate::total 0.100976 # miss rate for demand accesses 893system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100976 # miss rate for overall accesses 894system.cpu0.icache.overall_miss_rate::total 0.100976 # miss rate for overall accesses 895system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223 # average ReadReq miss latency 896system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223 # average ReadReq miss latency 897system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency 898system.cpu0.icache.demand_avg_miss_latency::total 14748.352223 # average overall miss latency 899system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency 900system.cpu0.icache.overall_avg_miss_latency::total 14748.352223 # average overall miss latency 901system.cpu0.icache.blocked_cycles::no_mshrs 1456992 # number of cycles access was blocked | 810system.cpu0.rob.rob_reads 79207972 # The number of ROB reads 811system.cpu0.rob.rob_writes 77724528 # The number of ROB writes 812system.cpu0.timesIdled 427936 # Number of times that the entire CPU went into an idle state and unscheduled itself 813system.cpu0.idleCycles 22241224 # Total number of cycles that the CPU has spent unscheduled due to idling 814system.cpu0.quiesceCycles 5096899290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 815system.cpu0.committedInsts 24053891 # Number of Instructions Simulated 816system.cpu0.committedOps 31785418 # Number of Ops (including micro ops) Simulated 817system.cpu0.committedInsts_total 24053891 # Number of Instructions Simulated 818system.cpu0.cpi 2.748499 # CPI: Cycles Per Instruction 819system.cpu0.cpi_total 2.748499 # CPI: Total CPI of All Threads 820system.cpu0.ipc 0.363835 # IPC: Instructions Per Cycle 821system.cpu0.ipc_total 0.363835 # IPC: Total IPC of All Threads 822system.cpu0.int_regfile_reads 174526329 # number of integer regfile reads 823system.cpu0.int_regfile_writes 34331240 # number of integer regfile writes 824system.cpu0.fp_regfile_reads 3280 # number of floating regfile reads 825system.cpu0.fp_regfile_writes 898 # number of floating regfile writes 826system.cpu0.misc_regfile_reads 46875879 # number of misc regfile reads 827system.cpu0.misc_regfile_writes 527497 # number of misc regfile writes 828system.cpu0.icache.replacements 406974 # number of replacements 829system.cpu0.icache.tagsinuse 511.614338 # Cycle average of tags in use 830system.cpu0.icache.total_refs 3978434 # Total number of references to valid blocks. 831system.cpu0.icache.sampled_refs 407486 # Sample count of references to valid blocks. 832system.cpu0.icache.avg_refs 9.763364 # Average number of references to valid blocks. 833system.cpu0.icache.warmup_cycle 6469268000 # Cycle when the warmup percentage was hit. 834system.cpu0.icache.occ_blocks::cpu0.inst 511.614338 # Average occupied blocks per requestor 835system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy 836system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy 837system.cpu0.icache.ReadReq_hits::cpu0.inst 3978434 # number of ReadReq hits 838system.cpu0.icache.ReadReq_hits::total 3978434 # number of ReadReq hits 839system.cpu0.icache.demand_hits::cpu0.inst 3978434 # number of demand (read+write) hits 840system.cpu0.icache.demand_hits::total 3978434 # number of demand (read+write) hits 841system.cpu0.icache.overall_hits::cpu0.inst 3978434 # number of overall hits 842system.cpu0.icache.overall_hits::total 3978434 # number of overall hits 843system.cpu0.icache.ReadReq_misses::cpu0.inst 441298 # number of ReadReq misses 844system.cpu0.icache.ReadReq_misses::total 441298 # number of ReadReq misses 845system.cpu0.icache.demand_misses::cpu0.inst 441298 # number of demand (read+write) misses 846system.cpu0.icache.demand_misses::total 441298 # number of demand (read+write) misses 847system.cpu0.icache.overall_misses::cpu0.inst 441298 # number of overall misses 848system.cpu0.icache.overall_misses::total 441298 # number of overall misses 849system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7186656997 # number of ReadReq miss cycles 850system.cpu0.icache.ReadReq_miss_latency::total 7186656997 # number of ReadReq miss cycles 851system.cpu0.icache.demand_miss_latency::cpu0.inst 7186656997 # number of demand (read+write) miss cycles 852system.cpu0.icache.demand_miss_latency::total 7186656997 # number of demand (read+write) miss cycles 853system.cpu0.icache.overall_miss_latency::cpu0.inst 7186656997 # number of overall miss cycles 854system.cpu0.icache.overall_miss_latency::total 7186656997 # number of overall miss cycles 855system.cpu0.icache.ReadReq_accesses::cpu0.inst 4419732 # number of ReadReq accesses(hits+misses) 856system.cpu0.icache.ReadReq_accesses::total 4419732 # number of ReadReq accesses(hits+misses) 857system.cpu0.icache.demand_accesses::cpu0.inst 4419732 # number of demand (read+write) accesses 858system.cpu0.icache.demand_accesses::total 4419732 # number of demand (read+write) accesses 859system.cpu0.icache.overall_accesses::cpu0.inst 4419732 # number of overall (read+write) accesses 860system.cpu0.icache.overall_accesses::total 4419732 # number of overall (read+write) accesses 861system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099847 # miss rate for ReadReq accesses 862system.cpu0.icache.ReadReq_miss_rate::total 0.099847 # miss rate for ReadReq accesses 863system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099847 # miss rate for demand accesses 864system.cpu0.icache.demand_miss_rate::total 0.099847 # miss rate for demand accesses 865system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099847 # miss rate for overall accesses 866system.cpu0.icache.overall_miss_rate::total 0.099847 # miss rate for overall accesses 867system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811 # average ReadReq miss latency 868system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811 # average ReadReq miss latency 869system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency 870system.cpu0.icache.demand_avg_miss_latency::total 16285.269811 # average overall miss latency 871system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency 872system.cpu0.icache.overall_avg_miss_latency::total 16285.269811 # average overall miss latency 873system.cpu0.icache.blocked_cycles::no_mshrs 1454497 # number of cycles access was blocked |
| 902system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 874system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 903system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked | 875system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked |
| 904system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 876system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 905system.cpu0.icache.avg_blocked_cycles::no_mshrs 8938.601227 # average number of cycles each access was blocked | 877system.cpu0.icache.avg_blocked_cycles::no_mshrs 8505.830409 # average number of cycles each access was blocked |
| 906system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu0.icache.fast_writes 0 # number of fast writes performed 908system.cpu0.icache.cache_copies 0 # number of cache copies performed | 878system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 879system.cpu0.icache.fast_writes 0 # number of fast writes performed 880system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 909system.cpu0.icache.writebacks::writebacks 31582 # number of writebacks 910system.cpu0.icache.writebacks::total 31582 # number of writebacks 911system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32527 # number of ReadReq MSHR hits 912system.cpu0.icache.ReadReq_mshr_hits::total 32527 # number of ReadReq MSHR hits 913system.cpu0.icache.demand_mshr_hits::cpu0.inst 32527 # number of demand (read+write) MSHR hits 914system.cpu0.icache.demand_mshr_hits::total 32527 # number of demand (read+write) MSHR hits 915system.cpu0.icache.overall_mshr_hits::cpu0.inst 32527 # number of overall MSHR hits 916system.cpu0.icache.overall_mshr_hits::total 32527 # number of overall MSHR hits 917system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 402762 # number of ReadReq MSHR misses 918system.cpu0.icache.ReadReq_mshr_misses::total 402762 # number of ReadReq MSHR misses 919system.cpu0.icache.demand_mshr_misses::cpu0.inst 402762 # number of demand (read+write) MSHR misses 920system.cpu0.icache.demand_mshr_misses::total 402762 # number of demand (read+write) MSHR misses 921system.cpu0.icache.overall_mshr_misses::cpu0.inst 402762 # number of overall MSHR misses 922system.cpu0.icache.overall_mshr_misses::total 402762 # number of overall MSHR misses 923system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4809385492 # number of ReadReq MSHR miss cycles 924system.cpu0.icache.ReadReq_mshr_miss_latency::total 4809385492 # number of ReadReq MSHR miss cycles 925system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4809385492 # number of demand (read+write) MSHR miss cycles 926system.cpu0.icache.demand_mshr_miss_latency::total 4809385492 # number of demand (read+write) MSHR miss cycles 927system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4809385492 # number of overall MSHR miss cycles 928system.cpu0.icache.overall_mshr_miss_latency::total 4809385492 # number of overall MSHR miss cycles 929system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7376000 # number of ReadReq MSHR uncacheable cycles 930system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7376000 # number of ReadReq MSHR uncacheable cycles 931system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7376000 # number of overall MSHR uncacheable cycles 932system.cpu0.icache.overall_mshr_uncacheable_latency::total 7376000 # number of overall MSHR uncacheable cycles 933system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for ReadReq accesses 934system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093431 # mshr miss rate for ReadReq accesses 935system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for demand accesses 936system.cpu0.icache.demand_mshr_miss_rate::total 0.093431 # mshr miss rate for demand accesses 937system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for overall accesses 938system.cpu0.icache.overall_mshr_miss_rate::total 0.093431 # mshr miss rate for overall accesses 939system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average ReadReq mshr miss latency 940system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049 # average ReadReq mshr miss latency 941system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency 942system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency 943system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency 944system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency | 881system.cpu0.icache.writebacks::writebacks 29234 # number of writebacks 882system.cpu0.icache.writebacks::total 29234 # number of writebacks 883system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33802 # number of ReadReq MSHR hits 884system.cpu0.icache.ReadReq_mshr_hits::total 33802 # number of ReadReq MSHR hits 885system.cpu0.icache.demand_mshr_hits::cpu0.inst 33802 # number of demand (read+write) MSHR hits 886system.cpu0.icache.demand_mshr_hits::total 33802 # number of demand (read+write) MSHR hits 887system.cpu0.icache.overall_mshr_hits::cpu0.inst 33802 # number of overall MSHR hits 888system.cpu0.icache.overall_mshr_hits::total 33802 # number of overall MSHR hits 889system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407496 # number of ReadReq MSHR misses 890system.cpu0.icache.ReadReq_mshr_misses::total 407496 # number of ReadReq MSHR misses 891system.cpu0.icache.demand_mshr_misses::cpu0.inst 407496 # number of demand (read+write) MSHR misses 892system.cpu0.icache.demand_mshr_misses::total 407496 # number of demand (read+write) MSHR misses 893system.cpu0.icache.overall_mshr_misses::cpu0.inst 407496 # number of overall MSHR misses 894system.cpu0.icache.overall_mshr_misses::total 407496 # number of overall MSHR misses 895system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5527499503 # number of ReadReq MSHR miss cycles 896system.cpu0.icache.ReadReq_mshr_miss_latency::total 5527499503 # number of ReadReq MSHR miss cycles 897system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5527499503 # number of demand (read+write) MSHR miss cycles 898system.cpu0.icache.demand_mshr_miss_latency::total 5527499503 # number of demand (read+write) MSHR miss cycles 899system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5527499503 # number of overall MSHR miss cycles 900system.cpu0.icache.overall_mshr_miss_latency::total 5527499503 # number of overall MSHR miss cycles 901system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles 902system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles 903system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles 904system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles 905system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for ReadReq accesses 906system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092199 # mshr miss rate for ReadReq accesses 907system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for demand accesses 908system.cpu0.icache.demand_mshr_miss_rate::total 0.092199 # mshr miss rate for demand accesses 909system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for overall accesses 910system.cpu0.icache.overall_mshr_miss_rate::total 0.092199 # mshr miss rate for overall accesses 911system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average ReadReq mshr miss latency 912system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107 # average ReadReq mshr miss latency 913system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency 914system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency 915system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency 916system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency |
| 945system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 946system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 947system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 948system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 949system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 917system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 918system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 919system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 920system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 921system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 950system.cpu0.dcache.replacements 272390 # number of replacements 951system.cpu0.dcache.tagsinuse 477.646995 # Cycle average of tags in use 952system.cpu0.dcache.total_refs 9259935 # Total number of references to valid blocks. 953system.cpu0.dcache.sampled_refs 272772 # Sample count of references to valid blocks. 954system.cpu0.dcache.avg_refs 33.947528 # Average number of references to valid blocks. 955system.cpu0.dcache.warmup_cycle 49645000 # Cycle when the warmup percentage was hit. 956system.cpu0.dcache.occ_blocks::cpu0.data 477.646995 # Average occupied blocks per requestor 957system.cpu0.dcache.occ_percent::cpu0.data 0.932904 # Average percentage of cache occupancy 958system.cpu0.dcache.occ_percent::total 0.932904 # Average percentage of cache occupancy 959system.cpu0.dcache.ReadReq_hits::cpu0.data 5751664 # number of ReadReq hits 960system.cpu0.dcache.ReadReq_hits::total 5751664 # number of ReadReq hits 961system.cpu0.dcache.WriteReq_hits::cpu0.data 3128629 # number of WriteReq hits 962system.cpu0.dcache.WriteReq_hits::total 3128629 # number of WriteReq hits 963system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172667 # number of LoadLockedReq hits 964system.cpu0.dcache.LoadLockedReq_hits::total 172667 # number of LoadLockedReq hits 965system.cpu0.dcache.StoreCondReq_hits::cpu0.data 169954 # number of StoreCondReq hits 966system.cpu0.dcache.StoreCondReq_hits::total 169954 # number of StoreCondReq hits 967system.cpu0.dcache.demand_hits::cpu0.data 8880293 # number of demand (read+write) hits 968system.cpu0.dcache.demand_hits::total 8880293 # number of demand (read+write) hits 969system.cpu0.dcache.overall_hits::cpu0.data 8880293 # number of overall hits 970system.cpu0.dcache.overall_hits::total 8880293 # number of overall hits 971system.cpu0.dcache.ReadReq_misses::cpu0.data 380393 # number of ReadReq misses 972system.cpu0.dcache.ReadReq_misses::total 380393 # number of ReadReq misses 973system.cpu0.dcache.WriteReq_misses::cpu0.data 1568163 # number of WriteReq misses 974system.cpu0.dcache.WriteReq_misses::total 1568163 # number of WriteReq misses 975system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9112 # number of LoadLockedReq misses 976system.cpu0.dcache.LoadLockedReq_misses::total 9112 # number of LoadLockedReq misses 977system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7881 # number of StoreCondReq misses 978system.cpu0.dcache.StoreCondReq_misses::total 7881 # number of StoreCondReq misses 979system.cpu0.dcache.demand_misses::cpu0.data 1948556 # number of demand (read+write) misses 980system.cpu0.dcache.demand_misses::total 1948556 # number of demand (read+write) misses 981system.cpu0.dcache.overall_misses::cpu0.data 1948556 # number of overall misses 982system.cpu0.dcache.overall_misses::total 1948556 # number of overall misses 983system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5112833000 # number of ReadReq miss cycles 984system.cpu0.dcache.ReadReq_miss_latency::total 5112833000 # number of ReadReq miss cycles 985system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57745298395 # number of WriteReq miss cycles 986system.cpu0.dcache.WriteReq_miss_latency::total 57745298395 # number of WriteReq miss cycles 987system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100839000 # number of LoadLockedReq miss cycles 988system.cpu0.dcache.LoadLockedReq_miss_latency::total 100839000 # number of LoadLockedReq miss cycles 989system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 84292000 # number of StoreCondReq miss cycles 990system.cpu0.dcache.StoreCondReq_miss_latency::total 84292000 # number of StoreCondReq miss cycles 991system.cpu0.dcache.demand_miss_latency::cpu0.data 62858131395 # number of demand (read+write) miss cycles 992system.cpu0.dcache.demand_miss_latency::total 62858131395 # number of demand (read+write) miss cycles 993system.cpu0.dcache.overall_miss_latency::cpu0.data 62858131395 # number of overall miss cycles 994system.cpu0.dcache.overall_miss_latency::total 62858131395 # number of overall miss cycles 995system.cpu0.dcache.ReadReq_accesses::cpu0.data 6132057 # number of ReadReq accesses(hits+misses) 996system.cpu0.dcache.ReadReq_accesses::total 6132057 # number of ReadReq accesses(hits+misses) 997system.cpu0.dcache.WriteReq_accesses::cpu0.data 4696792 # number of WriteReq accesses(hits+misses) 998system.cpu0.dcache.WriteReq_accesses::total 4696792 # number of WriteReq accesses(hits+misses) 999system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181779 # number of LoadLockedReq accesses(hits+misses) 1000system.cpu0.dcache.LoadLockedReq_accesses::total 181779 # number of LoadLockedReq accesses(hits+misses) 1001system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 177835 # number of StoreCondReq accesses(hits+misses) 1002system.cpu0.dcache.StoreCondReq_accesses::total 177835 # number of StoreCondReq accesses(hits+misses) 1003system.cpu0.dcache.demand_accesses::cpu0.data 10828849 # number of demand (read+write) accesses 1004system.cpu0.dcache.demand_accesses::total 10828849 # number of demand (read+write) accesses 1005system.cpu0.dcache.overall_accesses::cpu0.data 10828849 # number of overall (read+write) accesses 1006system.cpu0.dcache.overall_accesses::total 10828849 # number of overall (read+write) accesses 1007system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062034 # miss rate for ReadReq accesses 1008system.cpu0.dcache.ReadReq_miss_rate::total 0.062034 # miss rate for ReadReq accesses 1009system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333880 # miss rate for WriteReq accesses 1010system.cpu0.dcache.WriteReq_miss_rate::total 0.333880 # miss rate for WriteReq accesses 1011system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050127 # miss rate for LoadLockedReq accesses 1012system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.050127 # miss rate for LoadLockedReq accesses 1013system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044316 # miss rate for StoreCondReq accesses 1014system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044316 # miss rate for StoreCondReq accesses 1015system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179941 # miss rate for demand accesses 1016system.cpu0.dcache.demand_miss_rate::total 0.179941 # miss rate for demand accesses 1017system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179941 # miss rate for overall accesses 1018system.cpu0.dcache.overall_miss_rate::total 0.179941 # miss rate for overall accesses 1019system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940 # average ReadReq miss latency 1020system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940 # average ReadReq miss latency 1021system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714 # average WriteReq miss latency 1022system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714 # average WriteReq miss latency 1023system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452 # average LoadLockedReq miss latency 1024system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452 # average LoadLockedReq miss latency 1025system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005 # average StoreCondReq miss latency 1026system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005 # average StoreCondReq miss latency 1027system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency 1028system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252 # average overall miss latency 1029system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency 1030system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252 # average overall miss latency 1031system.cpu0.dcache.blocked_cycles::no_mshrs 3762493 # number of cycles access was blocked 1032system.cpu0.dcache.blocked_cycles::no_targets 1470000 # number of cycles access was blocked 1033system.cpu0.dcache.blocked::no_mshrs 438 # number of cycles access was blocked 1034system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked 1035system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8590.166667 # average number of cycles each access was blocked 1036system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937 # average number of cycles each access was blocked | 922system.cpu0.dcache.replacements 275761 # number of replacements 923system.cpu0.dcache.tagsinuse 476.305820 # Cycle average of tags in use 924system.cpu0.dcache.total_refs 9551525 # Total number of references to valid blocks. 925system.cpu0.dcache.sampled_refs 276273 # Sample count of references to valid blocks. 926system.cpu0.dcache.avg_refs 34.572778 # Average number of references to valid blocks. 927system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. 928system.cpu0.dcache.occ_blocks::cpu0.data 476.305820 # Average occupied blocks per requestor 929system.cpu0.dcache.occ_percent::cpu0.data 0.930285 # Average percentage of cache occupancy 930system.cpu0.dcache.occ_percent::total 0.930285 # Average percentage of cache occupancy 931system.cpu0.dcache.ReadReq_hits::cpu0.data 5934693 # number of ReadReq hits 932system.cpu0.dcache.ReadReq_hits::total 5934693 # number of ReadReq hits 933system.cpu0.dcache.WriteReq_hits::cpu0.data 3224707 # number of WriteReq hits 934system.cpu0.dcache.WriteReq_hits::total 3224707 # number of WriteReq hits 935system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174478 # number of LoadLockedReq hits 936system.cpu0.dcache.LoadLockedReq_hits::total 174478 # number of LoadLockedReq hits 937system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171499 # number of StoreCondReq hits 938system.cpu0.dcache.StoreCondReq_hits::total 171499 # number of StoreCondReq hits 939system.cpu0.dcache.demand_hits::cpu0.data 9159400 # number of demand (read+write) hits 940system.cpu0.dcache.demand_hits::total 9159400 # number of demand (read+write) hits 941system.cpu0.dcache.overall_hits::cpu0.data 9159400 # number of overall hits 942system.cpu0.dcache.overall_hits::total 9159400 # number of overall hits 943system.cpu0.dcache.ReadReq_misses::cpu0.data 401255 # number of ReadReq misses 944system.cpu0.dcache.ReadReq_misses::total 401255 # number of ReadReq misses 945system.cpu0.dcache.WriteReq_misses::cpu0.data 1594245 # number of WriteReq misses 946system.cpu0.dcache.WriteReq_misses::total 1594245 # number of WriteReq misses 947system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9007 # number of LoadLockedReq misses 948system.cpu0.dcache.LoadLockedReq_misses::total 9007 # number of LoadLockedReq misses 949system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7794 # number of StoreCondReq misses 950system.cpu0.dcache.StoreCondReq_misses::total 7794 # number of StoreCondReq misses 951system.cpu0.dcache.demand_misses::cpu0.data 1995500 # number of demand (read+write) misses 952system.cpu0.dcache.demand_misses::total 1995500 # number of demand (read+write) misses 953system.cpu0.dcache.overall_misses::cpu0.data 1995500 # number of overall misses 954system.cpu0.dcache.overall_misses::total 1995500 # number of overall misses 955system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7289566500 # number of ReadReq miss cycles 956system.cpu0.dcache.ReadReq_miss_latency::total 7289566500 # number of ReadReq miss cycles 957system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71816395371 # number of WriteReq miss cycles 958system.cpu0.dcache.WriteReq_miss_latency::total 71816395371 # number of WriteReq miss cycles 959system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114642500 # number of LoadLockedReq miss cycles 960system.cpu0.dcache.LoadLockedReq_miss_latency::total 114642500 # number of LoadLockedReq miss cycles 961system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93715000 # number of StoreCondReq miss cycles 962system.cpu0.dcache.StoreCondReq_miss_latency::total 93715000 # number of StoreCondReq miss cycles 963system.cpu0.dcache.demand_miss_latency::cpu0.data 79105961871 # number of demand (read+write) miss cycles 964system.cpu0.dcache.demand_miss_latency::total 79105961871 # number of demand (read+write) miss cycles 965system.cpu0.dcache.overall_miss_latency::cpu0.data 79105961871 # number of overall miss cycles 966system.cpu0.dcache.overall_miss_latency::total 79105961871 # number of overall miss cycles 967system.cpu0.dcache.ReadReq_accesses::cpu0.data 6335948 # number of ReadReq accesses(hits+misses) 968system.cpu0.dcache.ReadReq_accesses::total 6335948 # number of ReadReq accesses(hits+misses) 969system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818952 # number of WriteReq accesses(hits+misses) 970system.cpu0.dcache.WriteReq_accesses::total 4818952 # number of WriteReq accesses(hits+misses) 971system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183485 # number of LoadLockedReq accesses(hits+misses) 972system.cpu0.dcache.LoadLockedReq_accesses::total 183485 # number of LoadLockedReq accesses(hits+misses) 973system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179293 # number of StoreCondReq accesses(hits+misses) 974system.cpu0.dcache.StoreCondReq_accesses::total 179293 # number of StoreCondReq accesses(hits+misses) 975system.cpu0.dcache.demand_accesses::cpu0.data 11154900 # number of demand (read+write) accesses 976system.cpu0.dcache.demand_accesses::total 11154900 # number of demand (read+write) accesses 977system.cpu0.dcache.overall_accesses::cpu0.data 11154900 # number of overall (read+write) accesses 978system.cpu0.dcache.overall_accesses::total 11154900 # number of overall (read+write) accesses 979system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063330 # miss rate for ReadReq accesses 980system.cpu0.dcache.ReadReq_miss_rate::total 0.063330 # miss rate for ReadReq accesses 981system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330828 # miss rate for WriteReq accesses 982system.cpu0.dcache.WriteReq_miss_rate::total 0.330828 # miss rate for WriteReq accesses 983system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049088 # miss rate for LoadLockedReq accesses 984system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049088 # miss rate for LoadLockedReq accesses 985system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043471 # miss rate for StoreCondReq accesses 986system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043471 # miss rate for StoreCondReq accesses 987system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178890 # miss rate for demand accesses 988system.cpu0.dcache.demand_miss_rate::total 0.178890 # miss rate for demand accesses 989system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178890 # miss rate for overall accesses 990system.cpu0.dcache.overall_miss_rate::total 0.178890 # miss rate for overall accesses 991system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546 # average ReadReq miss latency 992system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546 # average ReadReq miss latency 993system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530 # average WriteReq miss latency 994system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530 # average WriteReq miss latency 995system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879 # average LoadLockedReq miss latency 996system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879 # average LoadLockedReq miss latency 997system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815 # average StoreCondReq miss latency 998system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815 # average StoreCondReq miss latency 999system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency 1000system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831 # average overall miss latency 1001system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency 1002system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831 # average overall miss latency 1003system.cpu0.dcache.blocked_cycles::no_mshrs 7140493 # number of cycles access was blocked 1004system.cpu0.dcache.blocked_cycles::no_targets 1629000 # number of cycles access was blocked 1005system.cpu0.dcache.blocked::no_mshrs 1441 # number of cycles access was blocked 1006system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked 1007system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4955.234559 # average number of cycles each access was blocked 1008system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787 # average number of cycles each access was blocked |
| 1037system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1038system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1009system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1010system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1039system.cpu0.dcache.writebacks::writebacks 253456 # number of writebacks 1040system.cpu0.dcache.writebacks::total 253456 # number of writebacks 1041system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195063 # number of ReadReq MSHR hits 1042system.cpu0.dcache.ReadReq_mshr_hits::total 195063 # number of ReadReq MSHR hits 1043system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436472 # number of WriteReq MSHR hits 1044system.cpu0.dcache.WriteReq_mshr_hits::total 1436472 # number of WriteReq MSHR hits 1045system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 621 # number of LoadLockedReq MSHR hits 1046system.cpu0.dcache.LoadLockedReq_mshr_hits::total 621 # number of LoadLockedReq MSHR hits 1047system.cpu0.dcache.demand_mshr_hits::cpu0.data 1631535 # number of demand (read+write) MSHR hits 1048system.cpu0.dcache.demand_mshr_hits::total 1631535 # number of demand (read+write) MSHR hits 1049system.cpu0.dcache.overall_mshr_hits::cpu0.data 1631535 # number of overall MSHR hits 1050system.cpu0.dcache.overall_mshr_hits::total 1631535 # number of overall MSHR hits 1051system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185330 # number of ReadReq MSHR misses 1052system.cpu0.dcache.ReadReq_mshr_misses::total 185330 # number of ReadReq MSHR misses 1053system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131691 # number of WriteReq MSHR misses 1054system.cpu0.dcache.WriteReq_mshr_misses::total 131691 # number of WriteReq MSHR misses 1055system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8491 # number of LoadLockedReq MSHR misses 1056system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8491 # number of LoadLockedReq MSHR misses 1057system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7877 # number of StoreCondReq MSHR misses 1058system.cpu0.dcache.StoreCondReq_mshr_misses::total 7877 # number of StoreCondReq MSHR misses 1059system.cpu0.dcache.demand_mshr_misses::cpu0.data 317021 # number of demand (read+write) MSHR misses 1060system.cpu0.dcache.demand_mshr_misses::total 317021 # number of demand (read+write) MSHR misses 1061system.cpu0.dcache.overall_mshr_misses::cpu0.data 317021 # number of overall MSHR misses 1062system.cpu0.dcache.overall_mshr_misses::total 317021 # number of overall MSHR misses 1063system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2232196000 # number of ReadReq MSHR miss cycles 1064system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2232196000 # number of ReadReq MSHR miss cycles 1065system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4281157492 # number of WriteReq MSHR miss cycles 1066system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4281157492 # number of WriteReq MSHR miss cycles 1067system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67651500 # number of LoadLockedReq MSHR miss cycles 1068system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67651500 # number of LoadLockedReq MSHR miss cycles 1069system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60619000 # number of StoreCondReq MSHR miss cycles 1070system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60619000 # number of StoreCondReq MSHR miss cycles 1071system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6513353492 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.dcache.demand_mshr_miss_latency::total 6513353492 # number of demand (read+write) MSHR miss cycles 1073system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6513353492 # number of overall MSHR miss cycles 1074system.cpu0.dcache.overall_mshr_miss_latency::total 6513353492 # number of overall MSHR miss cycles 1075system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 24166586500 # number of ReadReq MSHR uncacheable cycles 1076system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 24166586500 # number of ReadReq MSHR uncacheable cycles 1077system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 850308391 # number of WriteReq MSHR uncacheable cycles 1078system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 850308391 # number of WriteReq MSHR uncacheable cycles 1079system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 25016894891 # number of overall MSHR uncacheable cycles 1080system.cpu0.dcache.overall_mshr_uncacheable_latency::total 25016894891 # number of overall MSHR uncacheable cycles 1081system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030223 # mshr miss rate for ReadReq accesses 1082system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030223 # mshr miss rate for ReadReq accesses 1083system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028038 # mshr miss rate for WriteReq accesses 1084system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028038 # mshr miss rate for WriteReq accesses 1085system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046711 # mshr miss rate for LoadLockedReq accesses 1086system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046711 # mshr miss rate for LoadLockedReq accesses 1087system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses 1088system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses 1089system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for demand accesses 1090system.cpu0.dcache.demand_mshr_miss_rate::total 0.029276 # mshr miss rate for demand accesses 1091system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for overall accesses 1092system.cpu0.dcache.overall_mshr_miss_rate::total 0.029276 # mshr miss rate for overall accesses 1093system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648 # average ReadReq mshr miss latency 1094system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648 # average ReadReq mshr miss latency 1095system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179 # average WriteReq mshr miss latency 1096system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179 # average WriteReq mshr miss latency 1097system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7967.436109 # average LoadLockedReq mshr miss latency 1098system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7967.436109 # average LoadLockedReq mshr miss latency 1099system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7695.696331 # average StoreCondReq mshr miss latency 1100system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7695.696331 # average StoreCondReq mshr miss latency 1101system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency 1102system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency 1103system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency 1104system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency | 1011system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks 1012system.cpu0.dcache.writebacks::total 255942 # number of writebacks 1013system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211815 # number of ReadReq MSHR hits 1014system.cpu0.dcache.ReadReq_mshr_hits::total 211815 # number of ReadReq MSHR hits 1015system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463184 # number of WriteReq MSHR hits 1016system.cpu0.dcache.WriteReq_mshr_hits::total 1463184 # number of WriteReq MSHR hits 1017system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 509 # number of LoadLockedReq MSHR hits 1018system.cpu0.dcache.LoadLockedReq_mshr_hits::total 509 # number of LoadLockedReq MSHR hits 1019system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674999 # number of demand (read+write) MSHR hits 1020system.cpu0.dcache.demand_mshr_hits::total 1674999 # number of demand (read+write) MSHR hits 1021system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674999 # number of overall MSHR hits 1022system.cpu0.dcache.overall_mshr_hits::total 1674999 # number of overall MSHR hits 1023system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189440 # number of ReadReq MSHR misses 1024system.cpu0.dcache.ReadReq_mshr_misses::total 189440 # number of ReadReq MSHR misses 1025system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131061 # number of WriteReq MSHR misses 1026system.cpu0.dcache.WriteReq_mshr_misses::total 131061 # number of WriteReq MSHR misses 1027system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8498 # number of LoadLockedReq MSHR misses 1028system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8498 # number of LoadLockedReq MSHR misses 1029system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7791 # number of StoreCondReq MSHR misses 1030system.cpu0.dcache.StoreCondReq_mshr_misses::total 7791 # number of StoreCondReq MSHR misses 1031system.cpu0.dcache.demand_mshr_misses::cpu0.data 320501 # number of demand (read+write) MSHR misses 1032system.cpu0.dcache.demand_mshr_misses::total 320501 # number of demand (read+write) MSHR misses 1033system.cpu0.dcache.overall_mshr_misses::cpu0.data 320501 # number of overall MSHR misses 1034system.cpu0.dcache.overall_mshr_misses::total 320501 # number of overall MSHR misses 1035system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2806583905 # number of ReadReq MSHR miss cycles 1036system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2806583905 # number of ReadReq MSHR miss cycles 1037system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685193022 # number of WriteReq MSHR miss cycles 1038system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685193022 # number of WriteReq MSHR miss cycles 1039system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 80265007 # number of LoadLockedReq MSHR miss cycles 1040system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 80265007 # number of LoadLockedReq MSHR miss cycles 1041system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 69214057 # number of StoreCondReq MSHR miss cycles 1042system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 69214057 # number of StoreCondReq MSHR miss cycles 1043system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7491776927 # number of demand (read+write) MSHR miss cycles 1044system.cpu0.dcache.demand_mshr_miss_latency::total 7491776927 # number of demand (read+write) MSHR miss cycles 1045system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7491776927 # number of overall MSHR miss cycles 1046system.cpu0.dcache.overall_mshr_miss_latency::total 7491776927 # number of overall MSHR miss cycles 1047system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315161000 # number of ReadReq MSHR uncacheable cycles 1048system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315161000 # number of ReadReq MSHR uncacheable cycles 1049system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849550399 # number of WriteReq MSHR uncacheable cycles 1050system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849550399 # number of WriteReq MSHR uncacheable cycles 1051system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164711399 # number of overall MSHR uncacheable cycles 1052system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164711399 # number of overall MSHR uncacheable cycles 1053system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029899 # mshr miss rate for ReadReq accesses 1054system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029899 # mshr miss rate for ReadReq accesses 1055system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027197 # mshr miss rate for WriteReq accesses 1056system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027197 # mshr miss rate for WriteReq accesses 1057system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046314 # mshr miss rate for LoadLockedReq accesses 1058system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046314 # mshr miss rate for LoadLockedReq accesses 1059system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043454 # mshr miss rate for StoreCondReq accesses 1060system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043454 # mshr miss rate for StoreCondReq accesses 1061system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for demand accesses 1062system.cpu0.dcache.demand_mshr_miss_rate::total 0.028732 # mshr miss rate for demand accesses 1063system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for overall accesses 1064system.cpu0.dcache.overall_mshr_miss_rate::total 0.028732 # mshr miss rate for overall accesses 1065system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971 # average ReadReq mshr miss latency 1066system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971 # average ReadReq mshr miss latency 1067system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127 # average WriteReq mshr miss latency 1068system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127 # average WriteReq mshr miss latency 1069system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9445.164392 # average LoadLockedReq mshr miss latency 1070system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9445.164392 # average LoadLockedReq mshr miss latency 1071system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8883.847645 # average StoreCondReq mshr miss latency 1072system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8883.847645 # average StoreCondReq mshr miss latency 1073system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency 1074system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency 1075system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency 1076system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency |
| 1105system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1106system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1107system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1108system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1109system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1110system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1111system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1112system.cpu1.dtb.inst_hits 0 # ITB inst hits 1113system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1077system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1078system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1079system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1080system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1081system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1082system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1083system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1084system.cpu1.dtb.inst_hits 0 # ITB inst hits 1085system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1114system.cpu1.dtb.read_hits 40314372 # DTB read hits 1115system.cpu1.dtb.read_misses 47835 # DTB read misses 1116system.cpu1.dtb.write_hits 7207214 # DTB write hits 1117system.cpu1.dtb.write_misses 14308 # DTB write misses | 1086system.cpu1.dtb.read_hits 43446349 # DTB read hits 1087system.cpu1.dtb.read_misses 46684 # DTB read misses 1088system.cpu1.dtb.write_hits 7088138 # DTB write hits 1089system.cpu1.dtb.write_misses 12274 # DTB write misses |
| 1118system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1119system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1120system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1121system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1090system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1091system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1092system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1093system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1122system.cpu1.dtb.flush_entries 2204 # Number of entries that have been flushed from TLB 1123system.cpu1.dtb.align_faults 3789 # Number of TLB faults due to alignment restrictions 1124system.cpu1.dtb.prefetch_faults 426 # Number of TLB faults due to prefetch | 1094system.cpu1.dtb.flush_entries 2545 # Number of entries that have been flushed from TLB 1095system.cpu1.dtb.align_faults 3731 # Number of TLB faults due to alignment restrictions 1096system.cpu1.dtb.prefetch_faults 361 # Number of TLB faults due to prefetch |
| 1125system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1097system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1126system.cpu1.dtb.perms_faults 618 # Number of TLB faults due to permissions restrictions 1127system.cpu1.dtb.read_accesses 40362207 # DTB read accesses 1128system.cpu1.dtb.write_accesses 7221522 # DTB write accesses | 1098system.cpu1.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions 1099system.cpu1.dtb.read_accesses 43493033 # DTB read accesses 1100system.cpu1.dtb.write_accesses 7100412 # DTB write accesses |
| 1129system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1101system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1130system.cpu1.dtb.hits 47521586 # DTB hits 1131system.cpu1.dtb.misses 62143 # DTB misses 1132system.cpu1.dtb.accesses 47583729 # DTB accesses 1133system.cpu1.itb.inst_hits 9199147 # ITB inst hits 1134system.cpu1.itb.inst_misses 6537 # ITB inst misses | 1102system.cpu1.dtb.hits 50534487 # DTB hits 1103system.cpu1.dtb.misses 58958 # DTB misses 1104system.cpu1.dtb.accesses 50593445 # DTB accesses 1105system.cpu1.itb.inst_hits 9221438 # ITB inst hits 1106system.cpu1.itb.inst_misses 6034 # ITB inst misses |
| 1135system.cpu1.itb.read_hits 0 # DTB read hits 1136system.cpu1.itb.read_misses 0 # DTB read misses 1137system.cpu1.itb.write_hits 0 # DTB write hits 1138system.cpu1.itb.write_misses 0 # DTB write misses 1139system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1140system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1141system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1142system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1107system.cpu1.itb.read_hits 0 # DTB read hits 1108system.cpu1.itb.read_misses 0 # DTB read misses 1109system.cpu1.itb.write_hits 0 # DTB write hits 1110system.cpu1.itb.write_misses 0 # DTB write misses 1111system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1112system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1113system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1114system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1143system.cpu1.itb.flush_entries 1398 # Number of entries that have been flushed from TLB | 1115system.cpu1.itb.flush_entries 1610 # Number of entries that have been flushed from TLB |
| 1144system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1145system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1146system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1116system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1117system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1118system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1147system.cpu1.itb.perms_faults 1778 # Number of TLB faults due to permissions restrictions | 1119system.cpu1.itb.perms_faults 1730 # Number of TLB faults due to permissions restrictions |
| 1148system.cpu1.itb.read_accesses 0 # DTB read accesses 1149system.cpu1.itb.write_accesses 0 # DTB write accesses | 1120system.cpu1.itb.read_accesses 0 # DTB read accesses 1121system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1150system.cpu1.itb.inst_accesses 9205684 # ITB inst accesses 1151system.cpu1.itb.hits 9199147 # DTB hits 1152system.cpu1.itb.misses 6537 # DTB misses 1153system.cpu1.itb.accesses 9205684 # DTB accesses 1154system.cpu1.numCycles 321589455 # number of cpu cycles simulated | 1122system.cpu1.itb.inst_accesses 9227472 # ITB inst accesses 1123system.cpu1.itb.hits 9221438 # DTB hits 1124system.cpu1.itb.misses 6034 # DTB misses 1125system.cpu1.itb.accesses 9227472 # DTB accesses 1126system.cpu1.numCycles 353824423 # number of cpu cycles simulated |
| 1155system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1156system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1127system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1128system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1157system.cpu1.BPredUnit.lookups 9609219 # Number of BP lookups 1158system.cpu1.BPredUnit.condPredicted 7804241 # Number of conditional branches predicted 1159system.cpu1.BPredUnit.condIncorrect 456907 # Number of conditional branches incorrect 1160system.cpu1.BPredUnit.BTBLookups 6466725 # Number of BTB lookups 1161system.cpu1.BPredUnit.BTBHits 5325877 # Number of BTB hits | 1129system.cpu1.BPredUnit.lookups 9470897 # Number of BP lookups 1130system.cpu1.BPredUnit.condPredicted 7703385 # Number of conditional branches predicted 1131system.cpu1.BPredUnit.condIncorrect 447489 # Number of conditional branches incorrect 1132system.cpu1.BPredUnit.BTBLookups 6420671 # Number of BTB lookups 1133system.cpu1.BPredUnit.BTBHits 5281203 # Number of BTB hits |
| 1162system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1134system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1163system.cpu1.BPredUnit.usedRAS 844527 # Number of times the RAS was used to get a target. 1164system.cpu1.BPredUnit.RASInCorrect 50619 # Number of incorrect RAS predictions. 1165system.cpu1.fetch.icacheStallCycles 21504333 # Number of cycles fetch is stalled on an Icache miss 1166system.cpu1.fetch.Insts 71435147 # Number of instructions fetch has processed 1167system.cpu1.fetch.Branches 9609219 # Number of branches that fetch encountered 1168system.cpu1.fetch.predictedBranches 6170404 # Number of branches that fetch has predicted taken 1169system.cpu1.fetch.Cycles 15136389 # Number of cycles fetch has run and was not squashing or blocked 1170system.cpu1.fetch.SquashCycles 4734420 # Number of cycles fetch has spent squashing 1171system.cpu1.fetch.TlbCycles 89053 # Number of cycles fetch has spent waiting for tlb 1172system.cpu1.fetch.BlockedCycles 66067639 # Number of cycles fetch has spent blocked 1173system.cpu1.fetch.MiscStallCycles 5715 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1174system.cpu1.fetch.PendingTrapStallCycles 64771 # Number of stall cycles due to pending traps 1175system.cpu1.fetch.PendingQuiesceStallCycles 143196 # Number of stall cycles due to pending quiesce instructions 1176system.cpu1.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR 1177system.cpu1.fetch.CacheLines 9197098 # Number of cache lines fetched 1178system.cpu1.fetch.IcacheSquashes 766779 # Number of outstanding Icache misses that were squashed 1179system.cpu1.fetch.ItlbSquashes 3914 # Number of outstanding ITLB misses that were squashed 1180system.cpu1.fetch.rateDist::samples 106241109 # Number of instructions fetched each cycle (Total) 1181system.cpu1.fetch.rateDist::mean 0.815152 # Number of instructions fetched each cycle (Total) 1182system.cpu1.fetch.rateDist::stdev 2.196213 # Number of instructions fetched each cycle (Total) | 1135system.cpu1.BPredUnit.usedRAS 834152 # Number of times the RAS was used to get a target. 1136system.cpu1.BPredUnit.RASInCorrect 50449 # Number of incorrect RAS predictions. 1137system.cpu1.fetch.icacheStallCycles 22167103 # Number of cycles fetch is stalled on an Icache miss 1138system.cpu1.fetch.Insts 70445168 # Number of instructions fetch has processed 1139system.cpu1.fetch.Branches 9470897 # Number of branches that fetch encountered 1140system.cpu1.fetch.predictedBranches 6115355 # Number of branches that fetch has predicted taken 1141system.cpu1.fetch.Cycles 14956565 # Number of cycles fetch has run and was not squashing or blocked 1142system.cpu1.fetch.SquashCycles 4597208 # Number of cycles fetch has spent squashing 1143system.cpu1.fetch.TlbCycles 88094 # Number of cycles fetch has spent waiting for tlb 1144system.cpu1.fetch.BlockedCycles 73687570 # Number of cycles fetch has spent blocked 1145system.cpu1.fetch.MiscStallCycles 6011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1146system.cpu1.fetch.PendingTrapStallCycles 61739 # Number of stall cycles due to pending traps 1147system.cpu1.fetch.PendingQuiesceStallCycles 141755 # Number of stall cycles due to pending quiesce instructions 1148system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR 1149system.cpu1.fetch.CacheLines 9219303 # Number of cache lines fetched 1150system.cpu1.fetch.IcacheSquashes 857673 # Number of outstanding Icache misses that were squashed 1151system.cpu1.fetch.ItlbSquashes 3541 # Number of outstanding ITLB misses that were squashed 1152system.cpu1.fetch.rateDist::samples 114241434 # Number of instructions fetched each cycle (Total) 1153system.cpu1.fetch.rateDist::mean 0.747913 # Number of instructions fetched each cycle (Total) 1154system.cpu1.fetch.rateDist::stdev 2.114106 # Number of instructions fetched each cycle (Total) |
| 1183system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1155system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1184system.cpu1.fetch.rateDist::0 91113370 85.76% 85.76% # Number of instructions fetched each cycle (Total) 1185system.cpu1.fetch.rateDist::1 835957 0.79% 86.55% # Number of instructions fetched each cycle (Total) 1186system.cpu1.fetch.rateDist::2 1038807 0.98% 87.53% # Number of instructions fetched each cycle (Total) 1187system.cpu1.fetch.rateDist::3 2054123 1.93% 89.46% # Number of instructions fetched each cycle (Total) 1188system.cpu1.fetch.rateDist::4 1283354 1.21% 90.67% # Number of instructions fetched each cycle (Total) 1189system.cpu1.fetch.rateDist::5 639035 0.60% 91.27% # Number of instructions fetched each cycle (Total) 1190system.cpu1.fetch.rateDist::6 2277082 2.14% 93.41% # Number of instructions fetched each cycle (Total) 1191system.cpu1.fetch.rateDist::7 459375 0.43% 93.84% # Number of instructions fetched each cycle (Total) 1192system.cpu1.fetch.rateDist::8 6540006 6.16% 100.00% # Number of instructions fetched each cycle (Total) | 1156system.cpu1.fetch.rateDist::0 99293168 86.92% 86.92% # Number of instructions fetched each cycle (Total) 1157system.cpu1.fetch.rateDist::1 828706 0.73% 87.64% # Number of instructions fetched each cycle (Total) 1158system.cpu1.fetch.rateDist::2 1015866 0.89% 88.53% # Number of instructions fetched each cycle (Total) 1159system.cpu1.fetch.rateDist::3 2054648 1.80% 90.33% # Number of instructions fetched each cycle (Total) 1160system.cpu1.fetch.rateDist::4 1280264 1.12% 91.45% # Number of instructions fetched each cycle (Total) 1161system.cpu1.fetch.rateDist::5 613123 0.54% 91.99% # Number of instructions fetched each cycle (Total) 1162system.cpu1.fetch.rateDist::6 2273093 1.99% 93.98% # Number of instructions fetched each cycle (Total) 1163system.cpu1.fetch.rateDist::7 467514 0.41% 94.38% # Number of instructions fetched each cycle (Total) 1164system.cpu1.fetch.rateDist::8 6415052 5.62% 100.00% # Number of instructions fetched each cycle (Total) |
| 1193system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1194system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1195system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1165system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1166system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1167system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1196system.cpu1.fetch.rateDist::total 106241109 # Number of instructions fetched each cycle (Total) 1197system.cpu1.fetch.branchRate 0.029880 # Number of branch fetches per cycle 1198system.cpu1.fetch.rate 0.222131 # Number of inst fetches per cycle 1199system.cpu1.decode.IdleCycles 23013271 # Number of cycles decode is idle 1200system.cpu1.decode.BlockedCycles 65947642 # Number of cycles decode is blocked 1201system.cpu1.decode.RunCycles 13617278 # Number of cycles decode is running 1202system.cpu1.decode.UnblockCycles 534194 # Number of cycles decode is unblocking 1203system.cpu1.decode.SquashCycles 3128724 # Number of cycles decode is squashing 1204system.cpu1.decode.BranchResolved 1272359 # Number of times decode resolved a branch 1205system.cpu1.decode.BranchMispred 103085 # Number of times decode detected a branch misprediction 1206system.cpu1.decode.DecodedInsts 80569967 # Number of instructions handled by decode 1207system.cpu1.decode.SquashedInsts 342001 # Number of squashed instructions handled by decode 1208system.cpu1.rename.SquashCycles 3128724 # Number of cycles rename is squashing 1209system.cpu1.rename.IdleCycles 24438096 # Number of cycles rename is idle 1210system.cpu1.rename.BlockCycles 29197230 # Number of cycles rename is blocking 1211system.cpu1.rename.serializeStallCycles 32706540 # count of cycles rename stalled for serializing inst 1212system.cpu1.rename.RunCycles 12706787 # Number of cycles rename is running 1213system.cpu1.rename.UnblockCycles 4063732 # Number of cycles rename is unblocking 1214system.cpu1.rename.RenamedInsts 74758294 # Number of instructions processed by rename 1215system.cpu1.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full 1216system.cpu1.rename.IQFullEvents 627503 # Number of times rename has blocked due to IQ full 1217system.cpu1.rename.LSQFullEvents 2908939 # Number of times rename has blocked due to LSQ full 1218system.cpu1.rename.FullRegisterEvents 45012 # Number of times there has been no free registers 1219system.cpu1.rename.RenamedOperands 79187879 # Number of destination operands rename has renamed 1220system.cpu1.rename.RenameLookups 346602336 # Number of register rename lookups that rename has made 1221system.cpu1.rename.int_rename_lookups 346555262 # Number of integer rename lookups 1222system.cpu1.rename.fp_rename_lookups 47074 # Number of floating rename lookups 1223system.cpu1.rename.CommittedMaps 50022423 # Number of HB maps that are committed 1224system.cpu1.rename.UndoneMaps 29165455 # Number of HB maps that are undone due to squashing 1225system.cpu1.rename.serializingInsts 496148 # count of serializing insts renamed 1226system.cpu1.rename.tempSerializingInsts 429704 # count of temporary serializing insts renamed 1227system.cpu1.rename.skidInsts 7532124 # count of insts added to the skid buffer 1228system.cpu1.memDep0.insertedLoads 14054260 # Number of loads inserted to the mem dependence unit. 1229system.cpu1.memDep0.insertedStores 8745175 # Number of stores inserted to the mem dependence unit. 1230system.cpu1.memDep0.conflictingLoads 1095062 # Number of conflicting loads. 1231system.cpu1.memDep0.conflictingStores 1520090 # Number of conflicting stores. 1232system.cpu1.iq.iqInstsAdded 67170682 # Number of instructions added to the IQ (excludes non-spec) 1233system.cpu1.iq.iqNonSpecInstsAdded 857343 # Number of non-speculative instructions added to the IQ 1234system.cpu1.iq.iqInstsIssued 88258087 # Number of instructions issued 1235system.cpu1.iq.iqSquashedInstsIssued 108704 # Number of squashed instructions issued 1236system.cpu1.iq.iqSquashedInstsExamined 18559774 # Number of squashed instructions iterated over during squash; mainly for profiling 1237system.cpu1.iq.iqSquashedOperandsExamined 53338169 # Number of squashed operands that are examined and possibly removed from graph 1238system.cpu1.iq.iqSquashedNonSpecRemoved 154632 # Number of squashed non-spec instructions that were removed 1239system.cpu1.iq.issued_per_cycle::samples 106241109 # Number of insts issued each cycle 1240system.cpu1.iq.issued_per_cycle::mean 0.830734 # Number of insts issued each cycle 1241system.cpu1.iq.issued_per_cycle::stdev 1.556038 # Number of insts issued each cycle | 1168system.cpu1.fetch.rateDist::total 114241434 # Number of instructions fetched each cycle (Total) 1169system.cpu1.fetch.branchRate 0.026767 # Number of branch fetches per cycle 1170system.cpu1.fetch.rate 0.199096 # Number of inst fetches per cycle 1171system.cpu1.decode.IdleCycles 23740446 # Number of cycles decode is idle 1172system.cpu1.decode.BlockedCycles 73499308 # Number of cycles decode is blocked 1173system.cpu1.decode.RunCycles 13432186 # Number of cycles decode is running 1174system.cpu1.decode.UnblockCycles 537783 # Number of cycles decode is unblocking 1175system.cpu1.decode.SquashCycles 3031711 # Number of cycles decode is squashing 1176system.cpu1.decode.BranchResolved 1242419 # Number of times decode resolved a branch 1177system.cpu1.decode.BranchMispred 102480 # Number of times decode detected a branch misprediction 1178system.cpu1.decode.DecodedInsts 79700896 # Number of instructions handled by decode 1179system.cpu1.decode.SquashedInsts 342426 # Number of squashed instructions handled by decode 1180system.cpu1.rename.SquashCycles 3031711 # Number of cycles rename is squashing 1181system.cpu1.rename.IdleCycles 25267828 # Number of cycles rename is idle 1182system.cpu1.rename.BlockCycles 33699109 # Number of cycles rename is blocking 1183system.cpu1.rename.serializeStallCycles 35312301 # count of cycles rename stalled for serializing inst 1184system.cpu1.rename.RunCycles 12394168 # Number of cycles rename is running 1185system.cpu1.rename.UnblockCycles 4536317 # Number of cycles rename is unblocking 1186system.cpu1.rename.RenamedInsts 73261010 # Number of instructions processed by rename 1187system.cpu1.rename.ROBFullEvents 3244 # Number of times rename has blocked due to ROB full 1188system.cpu1.rename.IQFullEvents 714923 # Number of times rename has blocked due to IQ full 1189system.cpu1.rename.LSQFullEvents 3281779 # Number of times rename has blocked due to LSQ full 1190system.cpu1.rename.FullRegisterEvents 33706 # Number of times there has been no free registers 1191system.cpu1.rename.RenamedOperands 77426546 # Number of destination operands rename has renamed 1192system.cpu1.rename.RenameLookups 339504965 # Number of register rename lookups that rename has made 1193system.cpu1.rename.int_rename_lookups 339445449 # Number of integer rename lookups 1194system.cpu1.rename.fp_rename_lookups 59516 # Number of floating rename lookups 1195system.cpu1.rename.CommittedMaps 49265102 # Number of HB maps that are committed 1196system.cpu1.rename.UndoneMaps 28161444 # Number of HB maps that are undone due to squashing 1197system.cpu1.rename.serializingInsts 486276 # count of serializing insts renamed 1198system.cpu1.rename.tempSerializingInsts 420659 # count of temporary serializing insts renamed 1199system.cpu1.rename.skidInsts 8155263 # count of insts added to the skid buffer 1200system.cpu1.memDep0.insertedLoads 14019935 # Number of loads inserted to the mem dependence unit. 1201system.cpu1.memDep0.insertedStores 8605996 # Number of stores inserted to the mem dependence unit. 1202system.cpu1.memDep0.conflictingLoads 1069297 # Number of conflicting loads. 1203system.cpu1.memDep0.conflictingStores 1521896 # Number of conflicting stores. 1204system.cpu1.iq.iqInstsAdded 66318588 # Number of instructions added to the IQ (excludes non-spec) 1205system.cpu1.iq.iqNonSpecInstsAdded 855610 # Number of non-speculative instructions added to the IQ 1206system.cpu1.iq.iqInstsIssued 90596015 # Number of instructions issued 1207system.cpu1.iq.iqSquashedInstsIssued 108958 # Number of squashed instructions issued 1208system.cpu1.iq.iqSquashedInstsExamined 18341957 # Number of squashed instructions iterated over during squash; mainly for profiling 1209system.cpu1.iq.iqSquashedOperandsExamined 53651445 # Number of squashed operands that are examined and possibly removed from graph 1210system.cpu1.iq.iqSquashedNonSpecRemoved 163223 # Number of squashed non-spec instructions that were removed 1211system.cpu1.iq.issued_per_cycle::samples 114241434 # Number of insts issued each cycle 1212system.cpu1.iq.issued_per_cycle::mean 0.793022 # Number of insts issued each cycle 1213system.cpu1.iq.issued_per_cycle::stdev 1.525613 # Number of insts issued each cycle |
| 1242system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1214system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1243system.cpu1.iq.issued_per_cycle::0 76008182 71.54% 71.54% # Number of insts issued each cycle 1244system.cpu1.iq.issued_per_cycle::1 8446540 7.95% 79.49% # Number of insts issued each cycle 1245system.cpu1.iq.issued_per_cycle::2 4482838 4.22% 83.71% # Number of insts issued each cycle 1246system.cpu1.iq.issued_per_cycle::3 3826420 3.60% 87.31% # Number of insts issued each cycle 1247system.cpu1.iq.issued_per_cycle::4 9985833 9.40% 96.71% # Number of insts issued each cycle 1248system.cpu1.iq.issued_per_cycle::5 1963466 1.85% 98.56% # Number of insts issued each cycle 1249system.cpu1.iq.issued_per_cycle::6 1174590 1.11% 99.67% # Number of insts issued each cycle 1250system.cpu1.iq.issued_per_cycle::7 267511 0.25% 99.92% # Number of insts issued each cycle 1251system.cpu1.iq.issued_per_cycle::8 85729 0.08% 100.00% # Number of insts issued each cycle | 1215system.cpu1.iq.issued_per_cycle::0 83094748 72.74% 72.74% # Number of insts issued each cycle 1216system.cpu1.iq.issued_per_cycle::1 8828314 7.73% 80.46% # Number of insts issued each cycle 1217system.cpu1.iq.issued_per_cycle::2 4518450 3.96% 84.42% # Number of insts issued each cycle 1218system.cpu1.iq.issued_per_cycle::3 3737052 3.27% 87.69% # Number of insts issued each cycle 1219system.cpu1.iq.issued_per_cycle::4 10664138 9.33% 97.02% # Number of insts issued each cycle 1220system.cpu1.iq.issued_per_cycle::5 1972512 1.73% 98.75% # Number of insts issued each cycle 1221system.cpu1.iq.issued_per_cycle::6 1063413 0.93% 99.68% # Number of insts issued each cycle 1222system.cpu1.iq.issued_per_cycle::7 282401 0.25% 99.93% # Number of insts issued each cycle 1223system.cpu1.iq.issued_per_cycle::8 80406 0.07% 100.00% # Number of insts issued each cycle |
| 1252system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1253system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1254system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1224system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1225system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1226system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1255system.cpu1.iq.issued_per_cycle::total 106241109 # Number of insts issued each cycle | 1227system.cpu1.iq.issued_per_cycle::total 114241434 # Number of insts issued each cycle |
| 1256system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1228system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1257system.cpu1.iq.fu_full::IntAlu 34820 0.48% 0.48% # attempts to use FU when none available 1258system.cpu1.iq.fu_full::IntMult 995 0.01% 0.50% # attempts to use FU when none available 1259system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available 1260system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available 1261system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available 1262system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available 1263system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available 1264system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available 1265system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available 1266system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available 1267system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available 1268system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available 1269system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available 1270system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available 1271system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available 1272system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available 1273system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available 1274system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available 1275system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available 1276system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available 1277system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available 1278system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available 1279system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available 1280system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available 1281system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available 1282system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available 1283system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available 1284system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available 1285system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available 1286system.cpu1.iq.fu_full::MemRead 6868408 95.11% 95.61% # attempts to use FU when none available 1287system.cpu1.iq.fu_full::MemWrite 317335 4.39% 100.00% # attempts to use FU when none available | 1229system.cpu1.iq.fu_full::IntAlu 29108 0.37% 0.37% # attempts to use FU when none available 1230system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available 1231system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available 1232system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1233system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1234system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1235system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available 1236system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1237system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1238system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available 1239system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available 1240system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available 1241system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available 1242system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available 1243system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available 1244system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available 1245system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1246system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available 1247system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available 1248system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available 1249system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1250system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available 1251system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1252system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1253system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1254system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available 1255system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available 1256system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1257system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1258system.cpu1.iq.fu_full::MemRead 7574349 95.84% 96.22% # attempts to use FU when none available 1259system.cpu1.iq.fu_full::MemWrite 298565 3.78% 100.00% # attempts to use FU when none available |
| 1288system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1289system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1260system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1261system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1290system.cpu1.iq.FU_type_0::No_OpClass 81809 0.09% 0.09% # Type of FU issued 1291system.cpu1.iq.FU_type_0::IntAlu 39074007 44.27% 44.37% # Type of FU issued 1292system.cpu1.iq.FU_type_0::IntMult 63191 0.07% 44.44% # Type of FU issued 1293system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.44% # Type of FU issued 1294system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.44% # Type of FU issued 1295system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.44% # Type of FU issued 1296system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.44% # Type of FU issued 1297system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.44% # Type of FU issued 1298system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.44% # Type of FU issued 1299system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.44% # Type of FU issued 1300system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.44% # Type of FU issued 1301system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.44% # Type of FU issued 1302system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.44% # Type of FU issued 1303system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.44% # Type of FU issued 1304system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.44% # Type of FU issued 1305system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 44.44% # Type of FU issued 1306system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.44% # Type of FU issued 1307system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.44% # Type of FU issued 1308system.cpu1.iq.FU_type_0::SimdShift 5 0.00% 44.44% # Type of FU issued 1309system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 44.44% # Type of FU issued 1310system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.44% # Type of FU issued 1311system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.44% # Type of FU issued 1312system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.44% # Type of FU issued 1313system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.44% # Type of FU issued 1314system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.44% # Type of FU issued 1315system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.44% # Type of FU issued 1316system.cpu1.iq.FU_type_0::SimdFloatMisc 1634 0.00% 44.44% # Type of FU issued 1317system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.44% # Type of FU issued 1318system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 44.44% # Type of FU issued 1319system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.44% # Type of FU issued 1320system.cpu1.iq.FU_type_0::MemRead 41444924 46.96% 91.40% # Type of FU issued 1321system.cpu1.iq.FU_type_0::MemWrite 7592491 8.60% 100.00% # Type of FU issued | 1262system.cpu1.iq.FU_type_0::No_OpClass 86745 0.10% 0.10% # Type of FU issued 1263system.cpu1.iq.FU_type_0::IntAlu 38337785 42.32% 42.41% # Type of FU issued 1264system.cpu1.iq.FU_type_0::IntMult 61539 0.07% 42.48% # Type of FU issued 1265system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued 1266system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued 1267system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued 1268system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued 1269system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued 1270system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued 1271system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued 1272system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued 1273system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued 1274system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued 1275system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued 1276system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued 1277system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued 1278system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued 1279system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued 1280system.cpu1.iq.FU_type_0::SimdShift 4 0.00% 42.48% # Type of FU issued 1281system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.48% # Type of FU issued 1282system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued 1283system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued 1284system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued 1285system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued 1286system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued 1287system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued 1288system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.48% # Type of FU issued 1289system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued 1290system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.48% # Type of FU issued 1291system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued 1292system.cpu1.iq.FU_type_0::MemRead 44639306 49.27% 91.76% # Type of FU issued 1293system.cpu1.iq.FU_type_0::MemWrite 7468915 8.24% 100.00% # Type of FU issued |
| 1322system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1323system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1294system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1295system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1324system.cpu1.iq.FU_type_0::total 88258087 # Type of FU issued 1325system.cpu1.iq.rate 0.274443 # Inst issue rate 1326system.cpu1.iq.fu_busy_cnt 7221558 # FU busy when requested 1327system.cpu1.iq.fu_busy_rate 0.081823 # FU busy rate (busy events/executed inst) 1328system.cpu1.iq.int_inst_queue_reads 290137702 # Number of integer instruction queue reads 1329system.cpu1.iq.int_inst_queue_writes 86602000 # Number of integer instruction queue writes 1330system.cpu1.iq.int_inst_queue_wakeup_accesses 55480726 # Number of integer instruction queue wakeup accesses 1331system.cpu1.iq.fp_inst_queue_reads 11865 # Number of floating instruction queue reads 1332system.cpu1.iq.fp_inst_queue_writes 6384 # Number of floating instruction queue writes 1333system.cpu1.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses 1334system.cpu1.iq.int_alu_accesses 95391603 # Number of integer alu accesses 1335system.cpu1.iq.fp_alu_accesses 6233 # Number of floating point alu accesses 1336system.cpu1.iew.lsq.thread0.forwLoads 377691 # Number of loads that had data forwarded from stores | 1296system.cpu1.iq.FU_type_0::total 90596015 # Type of FU issued 1297system.cpu1.iq.rate 0.256048 # Inst issue rate 1298system.cpu1.iq.fu_busy_cnt 7903015 # FU busy when requested 1299system.cpu1.iq.fu_busy_rate 0.087234 # FU busy rate (busy events/executed inst) 1300system.cpu1.iq.int_inst_queue_reads 303489486 # Number of integer instruction queue reads 1301system.cpu1.iq.int_inst_queue_writes 85529327 # Number of integer instruction queue writes 1302system.cpu1.iq.int_inst_queue_wakeup_accesses 54443530 # Number of integer instruction queue wakeup accesses 1303system.cpu1.iq.fp_inst_queue_reads 14763 # Number of floating instruction queue reads 1304system.cpu1.iq.fp_inst_queue_writes 8091 # Number of floating instruction queue writes 1305system.cpu1.iq.fp_inst_queue_wakeup_accesses 6830 # Number of floating instruction queue wakeup accesses 1306system.cpu1.iq.int_alu_accesses 98404572 # Number of integer alu accesses 1307system.cpu1.iq.fp_alu_accesses 7713 # Number of floating point alu accesses 1308system.cpu1.iew.lsq.thread0.forwLoads 368848 # Number of loads that had data forwarded from stores |
| 1337system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1309system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1338system.cpu1.iew.lsq.thread0.squashedLoads 4014151 # Number of loads squashed 1339system.cpu1.iew.lsq.thread0.ignoredResponses 6631 # Number of memory responses ignored because the instruction is squashed 1340system.cpu1.iew.lsq.thread0.memOrderViolation 21303 # Number of memory ordering violations 1341system.cpu1.iew.lsq.thread0.squashedStores 1605227 # Number of stores squashed | 1310system.cpu1.iew.lsq.thread0.squashedLoads 4030694 # Number of loads squashed 1311system.cpu1.iew.lsq.thread0.ignoredResponses 6909 # Number of memory responses ignored because the instruction is squashed 1312system.cpu1.iew.lsq.thread0.memOrderViolation 21919 # Number of memory ordering violations 1313system.cpu1.iew.lsq.thread0.squashedStores 1587988 # Number of stores squashed |
| 1342system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1343system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1314system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1315system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1344system.cpu1.iew.lsq.thread0.rescheduledLoads 28717238 # Number of loads that were rescheduled 1345system.cpu1.iew.lsq.thread0.cacheBlocked 1149940 # Number of times an access to memory failed due to the cache being blocked | 1316system.cpu1.iew.lsq.thread0.rescheduledLoads 31965710 # Number of loads that were rescheduled 1317system.cpu1.iew.lsq.thread0.cacheBlocked 1045299 # Number of times an access to memory failed due to the cache being blocked |
| 1346system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1318system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1347system.cpu1.iew.iewSquashCycles 3128724 # Number of cycles IEW is squashing 1348system.cpu1.iew.iewBlockCycles 22478642 # Number of cycles IEW is blocking 1349system.cpu1.iew.iewUnblockCycles 328290 # Number of cycles IEW is unblocking 1350system.cpu1.iew.iewDispatchedInsts 68173106 # Number of instructions dispatched to IQ 1351system.cpu1.iew.iewDispSquashedInsts 141945 # Number of squashed instructions skipped by dispatch 1352system.cpu1.iew.iewDispLoadInsts 14054260 # Number of dispatched load instructions 1353system.cpu1.iew.iewDispStoreInsts 8745175 # Number of dispatched store instructions 1354system.cpu1.iew.iewDispNonSpecInsts 539434 # Number of dispatched non-speculative instructions 1355system.cpu1.iew.iewIQFullEvents 62530 # Number of times the IQ has become full, causing a stall 1356system.cpu1.iew.iewLSQFullEvents 3755 # Number of times the LSQ has become full, causing a stall 1357system.cpu1.iew.memOrderViolationEvents 21303 # Number of memory order violations 1358system.cpu1.iew.predictedTakenIncorrect 237741 # Number of branches that were predicted taken incorrectly 1359system.cpu1.iew.predictedNotTakenIncorrect 202628 # Number of branches that were predicted not taken incorrectly 1360system.cpu1.iew.branchMispredicts 440369 # Number of branch mispredicts detected at execute 1361system.cpu1.iew.iewExecutedInsts 85609132 # Number of executed instructions 1362system.cpu1.iew.iewExecLoadInsts 40707747 # Number of load instructions executed 1363system.cpu1.iew.iewExecSquashedInsts 2648955 # Number of squashed instructions skipped in execute | 1319system.cpu1.iew.iewSquashCycles 3031711 # Number of cycles IEW is squashing 1320system.cpu1.iew.iewBlockCycles 25598263 # Number of cycles IEW is blocking 1321system.cpu1.iew.iewUnblockCycles 405605 # Number of cycles IEW is unblocking 1322system.cpu1.iew.iewDispatchedInsts 67299344 # Number of instructions dispatched to IQ 1323system.cpu1.iew.iewDispSquashedInsts 135063 # Number of squashed instructions skipped by dispatch 1324system.cpu1.iew.iewDispLoadInsts 14019935 # Number of dispatched load instructions 1325system.cpu1.iew.iewDispStoreInsts 8605996 # Number of dispatched store instructions 1326system.cpu1.iew.iewDispNonSpecInsts 545729 # Number of dispatched non-speculative instructions 1327system.cpu1.iew.iewIQFullEvents 81019 # Number of times the IQ has become full, causing a stall 1328system.cpu1.iew.iewLSQFullEvents 7196 # Number of times the LSQ has become full, causing a stall 1329system.cpu1.iew.memOrderViolationEvents 21919 # Number of memory order violations 1330system.cpu1.iew.predictedTakenIncorrect 232087 # Number of branches that were predicted taken incorrectly 1331system.cpu1.iew.predictedNotTakenIncorrect 197105 # Number of branches that were predicted not taken incorrectly 1332system.cpu1.iew.branchMispredicts 429192 # Number of branch mispredicts detected at execute 1333system.cpu1.iew.iewExecutedInsts 87765278 # Number of executed instructions 1334system.cpu1.iew.iewExecLoadInsts 43831578 # Number of load instructions executed 1335system.cpu1.iew.iewExecSquashedInsts 2830737 # Number of squashed instructions skipped in execute |
| 1364system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1336system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1365system.cpu1.iew.exec_nop 145081 # number of nop insts executed 1366system.cpu1.iew.exec_refs 48220727 # number of memory reference insts executed 1367system.cpu1.iew.exec_branches 7143156 # Number of branches executed 1368system.cpu1.iew.exec_stores 7512980 # Number of stores executed 1369system.cpu1.iew.exec_rate 0.266206 # Inst execution rate 1370system.cpu1.iew.wb_sent 84396881 # cumulative count of insts sent to commit 1371system.cpu1.iew.wb_count 55486086 # cumulative count of insts written-back 1372system.cpu1.iew.wb_producers 30755357 # num instructions producing a value 1373system.cpu1.iew.wb_consumers 55849815 # num instructions consuming a value | 1337system.cpu1.iew.exec_nop 125146 # number of nop insts executed 1338system.cpu1.iew.exec_refs 51224987 # number of memory reference insts executed 1339system.cpu1.iew.exec_branches 7024509 # Number of branches executed 1340system.cpu1.iew.exec_stores 7393409 # Number of stores executed 1341system.cpu1.iew.exec_rate 0.248048 # Inst execution rate 1342system.cpu1.iew.wb_sent 86598496 # cumulative count of insts sent to commit 1343system.cpu1.iew.wb_count 54450360 # cumulative count of insts written-back 1344system.cpu1.iew.wb_producers 30044182 # num instructions producing a value 1345system.cpu1.iew.wb_consumers 53342809 # num instructions consuming a value |
| 1374system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1346system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1375system.cpu1.iew.wb_rate 0.172537 # insts written-back per cycle 1376system.cpu1.iew.wb_fanout 0.550680 # average fanout of values written-back | 1347system.cpu1.iew.wb_rate 0.153891 # insts written-back per cycle 1348system.cpu1.iew.wb_fanout 0.563228 # average fanout of values written-back |
| 1377system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1349system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1378system.cpu1.commit.commitCommittedInsts 38569031 # The number of committed instructions 1379system.cpu1.commit.commitCommittedOps 49069302 # The number of committed instructions 1380system.cpu1.commit.commitSquashedInsts 19027054 # The number of squashed insts skipped by commit 1381system.cpu1.commit.commitNonSpecStalls 702711 # The number of times commit has been forced to stall to communicate backwards 1382system.cpu1.commit.branchMispredicts 384240 # The number of times a branch was mispredicted 1383system.cpu1.commit.committed_per_cycle::samples 103162057 # Number of insts commited each cycle 1384system.cpu1.commit.committed_per_cycle::mean 0.475653 # Number of insts commited each cycle 1385system.cpu1.commit.committed_per_cycle::stdev 1.464816 # Number of insts commited each cycle | 1350system.cpu1.commit.commitCommittedInsts 38036954 # The number of committed instructions 1351system.cpu1.commit.commitCommittedOps 48396972 # The number of committed instructions 1352system.cpu1.commit.commitSquashedInsts 18817114 # The number of squashed insts skipped by commit 1353system.cpu1.commit.commitNonSpecStalls 692387 # The number of times commit has been forced to stall to communicate backwards 1354system.cpu1.commit.branchMispredicts 376510 # The number of times a branch was mispredicted 1355system.cpu1.commit.committed_per_cycle::samples 111258144 # Number of insts commited each cycle 1356system.cpu1.commit.committed_per_cycle::mean 0.434997 # Number of insts commited each cycle 1357system.cpu1.commit.committed_per_cycle::stdev 1.402953 # Number of insts commited each cycle |
| 1386system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1358system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1387system.cpu1.commit.committed_per_cycle::0 86125230 83.49% 83.49% # Number of insts commited each cycle 1388system.cpu1.commit.committed_per_cycle::1 8314170 8.06% 91.54% # Number of insts commited each cycle 1389system.cpu1.commit.committed_per_cycle::2 2284328 2.21% 93.76% # Number of insts commited each cycle 1390system.cpu1.commit.committed_per_cycle::3 1318858 1.28% 95.04% # Number of insts commited each cycle 1391system.cpu1.commit.committed_per_cycle::4 1066734 1.03% 96.07% # Number of insts commited each cycle 1392system.cpu1.commit.committed_per_cycle::5 616185 0.60% 96.67% # Number of insts commited each cycle 1393system.cpu1.commit.committed_per_cycle::6 1058049 1.03% 97.69% # Number of insts commited each cycle 1394system.cpu1.commit.committed_per_cycle::7 494277 0.48% 98.17% # Number of insts commited each cycle 1395system.cpu1.commit.committed_per_cycle::8 1884226 1.83% 100.00% # Number of insts commited each cycle | 1359system.cpu1.commit.committed_per_cycle::0 94210177 84.68% 84.68% # Number of insts commited each cycle 1360system.cpu1.commit.committed_per_cycle::1 8524716 7.66% 92.34% # Number of insts commited each cycle 1361system.cpu1.commit.committed_per_cycle::2 2208233 1.98% 94.32% # Number of insts commited each cycle 1362system.cpu1.commit.committed_per_cycle::3 1307974 1.18% 95.50% # Number of insts commited each cycle 1363system.cpu1.commit.committed_per_cycle::4 1064973 0.96% 96.46% # Number of insts commited each cycle 1364system.cpu1.commit.committed_per_cycle::5 589982 0.53% 96.99% # Number of insts commited each cycle 1365system.cpu1.commit.committed_per_cycle::6 1003368 0.90% 97.89% # Number of insts commited each cycle 1366system.cpu1.commit.committed_per_cycle::7 487910 0.44% 98.33% # Number of insts commited each cycle 1367system.cpu1.commit.committed_per_cycle::8 1860811 1.67% 100.00% # Number of insts commited each cycle |
| 1396system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1397system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1398system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1368system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1369system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1370system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1399system.cpu1.commit.committed_per_cycle::total 103162057 # Number of insts commited each cycle 1400system.cpu1.commit.committedInsts 38569031 # Number of instructions committed 1401system.cpu1.commit.committedOps 49069302 # Number of ops (including micro ops) committed | 1371system.cpu1.commit.committed_per_cycle::total 111258144 # Number of insts commited each cycle 1372system.cpu1.commit.committedInsts 38036954 # Number of instructions committed 1373system.cpu1.commit.committedOps 48396972 # Number of ops (including micro ops) committed |
| 1402system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1374system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1403system.cpu1.commit.refs 17180057 # Number of memory references committed 1404system.cpu1.commit.loads 10040109 # Number of loads committed 1405system.cpu1.commit.membars 207982 # Number of memory barriers committed 1406system.cpu1.commit.branches 6108113 # Number of branches committed 1407system.cpu1.commit.fp_insts 5310 # Number of committed floating point instructions. 1408system.cpu1.commit.int_insts 43785233 # Number of committed integer instructions. 1409system.cpu1.commit.function_calls 563417 # Number of function calls committed. 1410system.cpu1.commit.bw_lim_events 1884226 # number cycles where commit BW limit reached | 1375system.cpu1.commit.refs 17007249 # Number of memory references committed 1376system.cpu1.commit.loads 9989241 # Number of loads committed 1377system.cpu1.commit.membars 202226 # Number of memory barriers committed 1378system.cpu1.commit.branches 5993368 # Number of branches committed 1379system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1380system.cpu1.commit.int_insts 43235909 # Number of committed integer instructions. 1381system.cpu1.commit.function_calls 556157 # Number of function calls committed. 1382system.cpu1.commit.bw_lim_events 1860811 # number cycles where commit BW limit reached |
| 1411system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1383system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1412system.cpu1.rob.rob_reads 168322862 # The number of ROB reads 1413system.cpu1.rob.rob_writes 139443210 # The number of ROB writes 1414system.cpu1.timesIdled 1396987 # Number of times that the entire CPU went into an idle state and unscheduled itself 1415system.cpu1.idleCycles 215348346 # Total number of cycles that the CPU has spent unscheduled due to idling 1416system.cpu1.quiesceCycles 4817788385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1417system.cpu1.committedInsts 38483753 # Number of Instructions Simulated 1418system.cpu1.committedOps 48984024 # Number of Ops (including micro ops) Simulated 1419system.cpu1.committedInsts_total 38483753 # Number of Instructions Simulated 1420system.cpu1.cpi 8.356499 # CPI: Cycles Per Instruction 1421system.cpu1.cpi_total 8.356499 # CPI: Total CPI of All Threads 1422system.cpu1.ipc 0.119667 # IPC: Instructions Per Cycle 1423system.cpu1.ipc_total 0.119667 # IPC: Total IPC of All Threads 1424system.cpu1.int_regfile_reads 385614321 # number of integer regfile reads 1425system.cpu1.int_regfile_writes 58138574 # number of integer regfile writes 1426system.cpu1.fp_regfile_reads 3969 # number of floating regfile reads 1427system.cpu1.fp_regfile_writes 1880 # number of floating regfile writes 1428system.cpu1.misc_regfile_reads 91635789 # number of misc regfile reads 1429system.cpu1.misc_regfile_writes 441645 # number of misc regfile writes 1430system.cpu1.icache.replacements 628575 # number of replacements 1431system.cpu1.icache.tagsinuse 498.649539 # Cycle average of tags in use 1432system.cpu1.icache.total_refs 8518604 # Total number of references to valid blocks. 1433system.cpu1.icache.sampled_refs 629087 # Sample count of references to valid blocks. 1434system.cpu1.icache.avg_refs 13.541218 # Average number of references to valid blocks. 1435system.cpu1.icache.warmup_cycle 73946666000 # Cycle when the warmup percentage was hit. 1436system.cpu1.icache.occ_blocks::cpu1.inst 498.649539 # Average occupied blocks per requestor 1437system.cpu1.icache.occ_percent::cpu1.inst 0.973925 # Average percentage of cache occupancy 1438system.cpu1.icache.occ_percent::total 0.973925 # Average percentage of cache occupancy 1439system.cpu1.icache.ReadReq_hits::cpu1.inst 8518604 # number of ReadReq hits 1440system.cpu1.icache.ReadReq_hits::total 8518604 # number of ReadReq hits 1441system.cpu1.icache.demand_hits::cpu1.inst 8518604 # number of demand (read+write) hits 1442system.cpu1.icache.demand_hits::total 8518604 # number of demand (read+write) hits 1443system.cpu1.icache.overall_hits::cpu1.inst 8518604 # number of overall hits 1444system.cpu1.icache.overall_hits::total 8518604 # number of overall hits 1445system.cpu1.icache.ReadReq_misses::cpu1.inst 678443 # number of ReadReq misses 1446system.cpu1.icache.ReadReq_misses::total 678443 # number of ReadReq misses 1447system.cpu1.icache.demand_misses::cpu1.inst 678443 # number of demand (read+write) misses 1448system.cpu1.icache.demand_misses::total 678443 # number of demand (read+write) misses 1449system.cpu1.icache.overall_misses::cpu1.inst 678443 # number of overall misses 1450system.cpu1.icache.overall_misses::total 678443 # number of overall misses 1451system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9864551499 # number of ReadReq miss cycles 1452system.cpu1.icache.ReadReq_miss_latency::total 9864551499 # number of ReadReq miss cycles 1453system.cpu1.icache.demand_miss_latency::cpu1.inst 9864551499 # number of demand (read+write) miss cycles 1454system.cpu1.icache.demand_miss_latency::total 9864551499 # number of demand (read+write) miss cycles 1455system.cpu1.icache.overall_miss_latency::cpu1.inst 9864551499 # number of overall miss cycles 1456system.cpu1.icache.overall_miss_latency::total 9864551499 # number of overall miss cycles 1457system.cpu1.icache.ReadReq_accesses::cpu1.inst 9197047 # number of ReadReq accesses(hits+misses) 1458system.cpu1.icache.ReadReq_accesses::total 9197047 # number of ReadReq accesses(hits+misses) 1459system.cpu1.icache.demand_accesses::cpu1.inst 9197047 # number of demand (read+write) accesses 1460system.cpu1.icache.demand_accesses::total 9197047 # number of demand (read+write) accesses 1461system.cpu1.icache.overall_accesses::cpu1.inst 9197047 # number of overall (read+write) accesses 1462system.cpu1.icache.overall_accesses::total 9197047 # number of overall (read+write) accesses 1463system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073767 # miss rate for ReadReq accesses 1464system.cpu1.icache.ReadReq_miss_rate::total 0.073767 # miss rate for ReadReq accesses 1465system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073767 # miss rate for demand accesses 1466system.cpu1.icache.demand_miss_rate::total 0.073767 # miss rate for demand accesses 1467system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073767 # miss rate for overall accesses 1468system.cpu1.icache.overall_miss_rate::total 0.073767 # miss rate for overall accesses 1469system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14539.985672 # average ReadReq miss latency 1470system.cpu1.icache.ReadReq_avg_miss_latency::total 14539.985672 # average ReadReq miss latency 1471system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency 1472system.cpu1.icache.demand_avg_miss_latency::total 14539.985672 # average overall miss latency 1473system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency 1474system.cpu1.icache.overall_avg_miss_latency::total 14539.985672 # average overall miss latency 1475system.cpu1.icache.blocked_cycles::no_mshrs 932999 # number of cycles access was blocked | 1384system.cpu1.rob.rob_reads 175585773 # The number of ROB reads 1385system.cpu1.rob.rob_writes 137553768 # The number of ROB writes 1386system.cpu1.timesIdled 1520299 # Number of times that the entire CPU went into an idle state and unscheduled itself 1387system.cpu1.idleCycles 239582989 # Total number of cycles that the CPU has spent unscheduled due to idling 1388system.cpu1.quiesceCycles 4808538839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1389system.cpu1.committedInsts 37967315 # Number of Instructions Simulated 1390system.cpu1.committedOps 48327333 # Number of Ops (including micro ops) Simulated 1391system.cpu1.committedInsts_total 37967315 # Number of Instructions Simulated 1392system.cpu1.cpi 9.319185 # CPI: Cycles Per Instruction 1393system.cpu1.cpi_total 9.319185 # CPI: Total CPI of All Threads 1394system.cpu1.ipc 0.107306 # IPC: Instructions Per Cycle 1395system.cpu1.ipc_total 0.107306 # IPC: Total IPC of All Threads 1396system.cpu1.int_regfile_reads 393921761 # number of integer regfile reads 1397system.cpu1.int_regfile_writes 56840694 # number of integer regfile writes 1398system.cpu1.fp_regfile_reads 4925 # number of floating regfile reads 1399system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes 1400system.cpu1.misc_regfile_reads 90313719 # number of misc regfile reads 1401system.cpu1.misc_regfile_writes 429414 # number of misc regfile writes 1402system.cpu1.icache.replacements 622931 # number of replacements 1403system.cpu1.icache.tagsinuse 498.760560 # Cycle average of tags in use 1404system.cpu1.icache.total_refs 8545880 # Total number of references to valid blocks. 1405system.cpu1.icache.sampled_refs 623443 # Sample count of references to valid blocks. 1406system.cpu1.icache.avg_refs 13.707556 # Average number of references to valid blocks. 1407system.cpu1.icache.warmup_cycle 74633827000 # Cycle when the warmup percentage was hit. 1408system.cpu1.icache.occ_blocks::cpu1.inst 498.760560 # Average occupied blocks per requestor 1409system.cpu1.icache.occ_percent::cpu1.inst 0.974142 # Average percentage of cache occupancy 1410system.cpu1.icache.occ_percent::total 0.974142 # Average percentage of cache occupancy 1411system.cpu1.icache.ReadReq_hits::cpu1.inst 8545880 # number of ReadReq hits 1412system.cpu1.icache.ReadReq_hits::total 8545880 # number of ReadReq hits 1413system.cpu1.icache.demand_hits::cpu1.inst 8545880 # number of demand (read+write) hits 1414system.cpu1.icache.demand_hits::total 8545880 # number of demand (read+write) hits 1415system.cpu1.icache.overall_hits::cpu1.inst 8545880 # number of overall hits 1416system.cpu1.icache.overall_hits::total 8545880 # number of overall hits 1417system.cpu1.icache.ReadReq_misses::cpu1.inst 673372 # number of ReadReq misses 1418system.cpu1.icache.ReadReq_misses::total 673372 # number of ReadReq misses 1419system.cpu1.icache.demand_misses::cpu1.inst 673372 # number of demand (read+write) misses 1420system.cpu1.icache.demand_misses::total 673372 # number of demand (read+write) misses 1421system.cpu1.icache.overall_misses::cpu1.inst 673372 # number of overall misses 1422system.cpu1.icache.overall_misses::total 673372 # number of overall misses 1423system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10716931993 # number of ReadReq miss cycles 1424system.cpu1.icache.ReadReq_miss_latency::total 10716931993 # number of ReadReq miss cycles 1425system.cpu1.icache.demand_miss_latency::cpu1.inst 10716931993 # number of demand (read+write) miss cycles 1426system.cpu1.icache.demand_miss_latency::total 10716931993 # number of demand (read+write) miss cycles 1427system.cpu1.icache.overall_miss_latency::cpu1.inst 10716931993 # number of overall miss cycles 1428system.cpu1.icache.overall_miss_latency::total 10716931993 # number of overall miss cycles 1429system.cpu1.icache.ReadReq_accesses::cpu1.inst 9219252 # number of ReadReq accesses(hits+misses) 1430system.cpu1.icache.ReadReq_accesses::total 9219252 # number of ReadReq accesses(hits+misses) 1431system.cpu1.icache.demand_accesses::cpu1.inst 9219252 # number of demand (read+write) accesses 1432system.cpu1.icache.demand_accesses::total 9219252 # number of demand (read+write) accesses 1433system.cpu1.icache.overall_accesses::cpu1.inst 9219252 # number of overall (read+write) accesses 1434system.cpu1.icache.overall_accesses::total 9219252 # number of overall (read+write) accesses 1435system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073040 # miss rate for ReadReq accesses 1436system.cpu1.icache.ReadReq_miss_rate::total 0.073040 # miss rate for ReadReq accesses 1437system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073040 # miss rate for demand accesses 1438system.cpu1.icache.demand_miss_rate::total 0.073040 # miss rate for demand accesses 1439system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073040 # miss rate for overall accesses 1440system.cpu1.icache.overall_miss_rate::total 0.073040 # miss rate for overall accesses 1441system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684 # average ReadReq miss latency 1442system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684 # average ReadReq miss latency 1443system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency 1444system.cpu1.icache.demand_avg_miss_latency::total 15915.321684 # average overall miss latency 1445system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency 1446system.cpu1.icache.overall_avg_miss_latency::total 15915.321684 # average overall miss latency 1447system.cpu1.icache.blocked_cycles::no_mshrs 1332494 # number of cycles access was blocked |
| 1476system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1448system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1477system.cpu1.icache.blocked::no_mshrs 153 # number of cycles access was blocked | 1449system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked |
| 1478system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1450system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1479system.cpu1.icache.avg_blocked_cycles::no_mshrs 6098.032680 # average number of cycles each access was blocked | 1451system.cpu1.icache.avg_blocked_cycles::no_mshrs 6499.970732 # average number of cycles each access was blocked |
| 1480system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1481system.cpu1.icache.fast_writes 0 # number of fast writes performed 1482system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1452system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1453system.cpu1.icache.fast_writes 0 # number of fast writes performed 1454system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1483system.cpu1.icache.writebacks::writebacks 30976 # number of writebacks 1484system.cpu1.icache.writebacks::total 30976 # number of writebacks 1485system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49327 # number of ReadReq MSHR hits 1486system.cpu1.icache.ReadReq_mshr_hits::total 49327 # number of ReadReq MSHR hits 1487system.cpu1.icache.demand_mshr_hits::cpu1.inst 49327 # number of demand (read+write) MSHR hits 1488system.cpu1.icache.demand_mshr_hits::total 49327 # number of demand (read+write) MSHR hits 1489system.cpu1.icache.overall_mshr_hits::cpu1.inst 49327 # number of overall MSHR hits 1490system.cpu1.icache.overall_mshr_hits::total 49327 # number of overall MSHR hits 1491system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 629116 # number of ReadReq MSHR misses 1492system.cpu1.icache.ReadReq_mshr_misses::total 629116 # number of ReadReq MSHR misses 1493system.cpu1.icache.demand_mshr_misses::cpu1.inst 629116 # number of demand (read+write) MSHR misses 1494system.cpu1.icache.demand_mshr_misses::total 629116 # number of demand (read+write) MSHR misses 1495system.cpu1.icache.overall_mshr_misses::cpu1.inst 629116 # number of overall MSHR misses 1496system.cpu1.icache.overall_mshr_misses::total 629116 # number of overall MSHR misses 1497system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7390302499 # number of ReadReq MSHR miss cycles 1498system.cpu1.icache.ReadReq_mshr_miss_latency::total 7390302499 # number of ReadReq MSHR miss cycles 1499system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7390302499 # number of demand (read+write) MSHR miss cycles 1500system.cpu1.icache.demand_mshr_miss_latency::total 7390302499 # number of demand (read+write) MSHR miss cycles 1501system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7390302499 # number of overall MSHR miss cycles 1502system.cpu1.icache.overall_mshr_miss_latency::total 7390302499 # number of overall MSHR miss cycles 1503system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2676000 # number of ReadReq MSHR uncacheable cycles 1504system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2676000 # number of ReadReq MSHR uncacheable cycles 1505system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2676000 # number of overall MSHR uncacheable cycles 1506system.cpu1.icache.overall_mshr_uncacheable_latency::total 2676000 # number of overall MSHR uncacheable cycles 1507system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for ReadReq accesses 1508system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068404 # mshr miss rate for ReadReq accesses 1509system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for demand accesses 1510system.cpu1.icache.demand_mshr_miss_rate::total 0.068404 # mshr miss rate for demand accesses 1511system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for overall accesses 1512system.cpu1.icache.overall_mshr_miss_rate::total 0.068404 # mshr miss rate for overall accesses 1513system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average ReadReq mshr miss latency 1514system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11747.122151 # average ReadReq mshr miss latency 1515system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency 1516system.cpu1.icache.demand_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency 1517system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency 1518system.cpu1.icache.overall_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency | 1455system.cpu1.icache.writebacks::writebacks 33068 # number of writebacks 1456system.cpu1.icache.writebacks::total 33068 # number of writebacks 1457system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49906 # number of ReadReq MSHR hits 1458system.cpu1.icache.ReadReq_mshr_hits::total 49906 # number of ReadReq MSHR hits 1459system.cpu1.icache.demand_mshr_hits::cpu1.inst 49906 # number of demand (read+write) MSHR hits 1460system.cpu1.icache.demand_mshr_hits::total 49906 # number of demand (read+write) MSHR hits 1461system.cpu1.icache.overall_mshr_hits::cpu1.inst 49906 # number of overall MSHR hits 1462system.cpu1.icache.overall_mshr_hits::total 49906 # number of overall MSHR hits 1463system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623466 # number of ReadReq MSHR misses 1464system.cpu1.icache.ReadReq_mshr_misses::total 623466 # number of ReadReq MSHR misses 1465system.cpu1.icache.demand_mshr_misses::cpu1.inst 623466 # number of demand (read+write) MSHR misses 1466system.cpu1.icache.demand_mshr_misses::total 623466 # number of demand (read+write) MSHR misses 1467system.cpu1.icache.overall_mshr_misses::cpu1.inst 623466 # number of overall MSHR misses 1468system.cpu1.icache.overall_mshr_misses::total 623466 # number of overall MSHR misses 1469system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8227032008 # number of ReadReq MSHR miss cycles 1470system.cpu1.icache.ReadReq_mshr_miss_latency::total 8227032008 # number of ReadReq MSHR miss cycles 1471system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8227032008 # number of demand (read+write) MSHR miss cycles 1472system.cpu1.icache.demand_mshr_miss_latency::total 8227032008 # number of demand (read+write) MSHR miss cycles 1473system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8227032008 # number of overall MSHR miss cycles 1474system.cpu1.icache.overall_mshr_miss_latency::total 8227032008 # number of overall MSHR miss cycles 1475system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles 1476system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles 1477system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles 1478system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles 1479system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for ReadReq accesses 1480system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067627 # mshr miss rate for ReadReq accesses 1481system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for demand accesses 1482system.cpu1.icache.demand_mshr_miss_rate::total 0.067627 # mshr miss rate for demand accesses 1483system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for overall accesses 1484system.cpu1.icache.overall_mshr_miss_rate::total 0.067627 # mshr miss rate for overall accesses 1485system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average ReadReq mshr miss latency 1486system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588 # average ReadReq mshr miss latency 1487system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency 1488system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency 1489system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency 1490system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency |
| 1519system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1520system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1521system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1522system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1523system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1491system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1492system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1493system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1494system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1495system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1524system.cpu1.dcache.replacements 365990 # number of replacements 1525system.cpu1.dcache.tagsinuse 486.374853 # Cycle average of tags in use 1526system.cpu1.dcache.total_refs 13437990 # Total number of references to valid blocks. 1527system.cpu1.dcache.sampled_refs 366502 # Sample count of references to valid blocks. 1528system.cpu1.dcache.avg_refs 36.665530 # Average number of references to valid blocks. 1529system.cpu1.dcache.warmup_cycle 70078369000 # Cycle when the warmup percentage was hit. 1530system.cpu1.dcache.occ_blocks::cpu1.data 486.374853 # Average occupied blocks per requestor 1531system.cpu1.dcache.occ_percent::cpu1.data 0.949951 # Average percentage of cache occupancy 1532system.cpu1.dcache.occ_percent::total 0.949951 # Average percentage of cache occupancy 1533system.cpu1.dcache.ReadReq_hits::cpu1.data 8795505 # number of ReadReq hits 1534system.cpu1.dcache.ReadReq_hits::total 8795505 # number of ReadReq hits 1535system.cpu1.dcache.WriteReq_hits::cpu1.data 4385128 # number of WriteReq hits 1536system.cpu1.dcache.WriteReq_hits::total 4385128 # number of WriteReq hits 1537system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106581 # number of LoadLockedReq hits 1538system.cpu1.dcache.LoadLockedReq_hits::total 106581 # number of LoadLockedReq hits 1539system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102282 # number of StoreCondReq hits 1540system.cpu1.dcache.StoreCondReq_hits::total 102282 # number of StoreCondReq hits 1541system.cpu1.dcache.demand_hits::cpu1.data 13180633 # number of demand (read+write) hits 1542system.cpu1.dcache.demand_hits::total 13180633 # number of demand (read+write) hits 1543system.cpu1.dcache.overall_hits::cpu1.data 13180633 # number of overall hits 1544system.cpu1.dcache.overall_hits::total 13180633 # number of overall hits 1545system.cpu1.dcache.ReadReq_misses::cpu1.data 408153 # number of ReadReq misses 1546system.cpu1.dcache.ReadReq_misses::total 408153 # number of ReadReq misses 1547system.cpu1.dcache.WriteReq_misses::cpu1.data 1582783 # number of WriteReq misses 1548system.cpu1.dcache.WriteReq_misses::total 1582783 # number of WriteReq misses 1549system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13916 # number of LoadLockedReq misses 1550system.cpu1.dcache.LoadLockedReq_misses::total 13916 # number of LoadLockedReq misses 1551system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10800 # number of StoreCondReq misses 1552system.cpu1.dcache.StoreCondReq_misses::total 10800 # number of StoreCondReq misses 1553system.cpu1.dcache.demand_misses::cpu1.data 1990936 # number of demand (read+write) misses 1554system.cpu1.dcache.demand_misses::total 1990936 # number of demand (read+write) misses 1555system.cpu1.dcache.overall_misses::cpu1.data 1990936 # number of overall misses 1556system.cpu1.dcache.overall_misses::total 1990936 # number of overall misses 1557system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5766799000 # number of ReadReq miss cycles 1558system.cpu1.dcache.ReadReq_miss_latency::total 5766799000 # number of ReadReq miss cycles 1559system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 55285236443 # number of WriteReq miss cycles 1560system.cpu1.dcache.WriteReq_miss_latency::total 55285236443 # number of WriteReq miss cycles 1561system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 141367500 # number of LoadLockedReq miss cycles 1562system.cpu1.dcache.LoadLockedReq_miss_latency::total 141367500 # number of LoadLockedReq miss cycles 1563system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 89573500 # number of StoreCondReq miss cycles 1564system.cpu1.dcache.StoreCondReq_miss_latency::total 89573500 # number of StoreCondReq miss cycles 1565system.cpu1.dcache.demand_miss_latency::cpu1.data 61052035443 # number of demand (read+write) miss cycles 1566system.cpu1.dcache.demand_miss_latency::total 61052035443 # number of demand (read+write) miss cycles 1567system.cpu1.dcache.overall_miss_latency::cpu1.data 61052035443 # number of overall miss cycles 1568system.cpu1.dcache.overall_miss_latency::total 61052035443 # number of overall miss cycles 1569system.cpu1.dcache.ReadReq_accesses::cpu1.data 9203658 # number of ReadReq accesses(hits+misses) 1570system.cpu1.dcache.ReadReq_accesses::total 9203658 # number of ReadReq accesses(hits+misses) 1571system.cpu1.dcache.WriteReq_accesses::cpu1.data 5967911 # number of WriteReq accesses(hits+misses) 1572system.cpu1.dcache.WriteReq_accesses::total 5967911 # number of WriteReq accesses(hits+misses) 1573system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120497 # number of LoadLockedReq accesses(hits+misses) 1574system.cpu1.dcache.LoadLockedReq_accesses::total 120497 # number of LoadLockedReq accesses(hits+misses) 1575system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 113082 # number of StoreCondReq accesses(hits+misses) 1576system.cpu1.dcache.StoreCondReq_accesses::total 113082 # number of StoreCondReq accesses(hits+misses) 1577system.cpu1.dcache.demand_accesses::cpu1.data 15171569 # number of demand (read+write) accesses 1578system.cpu1.dcache.demand_accesses::total 15171569 # number of demand (read+write) accesses 1579system.cpu1.dcache.overall_accesses::cpu1.data 15171569 # number of overall (read+write) accesses 1580system.cpu1.dcache.overall_accesses::total 15171569 # number of overall (read+write) accesses 1581system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044347 # miss rate for ReadReq accesses 1582system.cpu1.dcache.ReadReq_miss_rate::total 0.044347 # miss rate for ReadReq accesses 1583system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.265216 # miss rate for WriteReq accesses 1584system.cpu1.dcache.WriteReq_miss_rate::total 0.265216 # miss rate for WriteReq accesses 1585system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115488 # miss rate for LoadLockedReq accesses 1586system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115488 # miss rate for LoadLockedReq accesses 1587system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095506 # miss rate for StoreCondReq accesses 1588system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095506 # miss rate for StoreCondReq accesses 1589system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131228 # miss rate for demand accesses 1590system.cpu1.dcache.demand_miss_rate::total 0.131228 # miss rate for demand accesses 1591system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131228 # miss rate for overall accesses 1592system.cpu1.dcache.overall_miss_rate::total 0.131228 # miss rate for overall accesses 1593system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895 # average ReadReq miss latency 1594system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895 # average ReadReq miss latency 1595system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069 # average WriteReq miss latency 1596system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069 # average WriteReq miss latency 1597system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354 # average LoadLockedReq miss latency 1598system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354 # average LoadLockedReq miss latency 1599system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8293.842593 # average StoreCondReq miss latency 1600system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8293.842593 # average StoreCondReq miss latency 1601system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency 1602system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463 # average overall miss latency 1603system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency 1604system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463 # average overall miss latency 1605system.cpu1.dcache.blocked_cycles::no_mshrs 12254574 # number of cycles access was blocked 1606system.cpu1.dcache.blocked_cycles::no_targets 5966500 # number of cycles access was blocked 1607system.cpu1.dcache.blocked::no_mshrs 3013 # number of cycles access was blocked 1608system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked 1609system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4067.233322 # average number of cycles each access was blocked 1610system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910 # average number of cycles each access was blocked | 1496system.cpu1.dcache.replacements 362729 # number of replacements 1497system.cpu1.dcache.tagsinuse 487.126779 # Cycle average of tags in use 1498system.cpu1.dcache.total_refs 13112337 # Total number of references to valid blocks. 1499system.cpu1.dcache.sampled_refs 363073 # Sample count of references to valid blocks. 1500system.cpu1.dcache.avg_refs 36.114878 # Average number of references to valid blocks. 1501system.cpu1.dcache.warmup_cycle 70483759000 # Cycle when the warmup percentage was hit. 1502system.cpu1.dcache.occ_blocks::cpu1.data 487.126779 # Average occupied blocks per requestor 1503system.cpu1.dcache.occ_percent::cpu1.data 0.951419 # Average percentage of cache occupancy 1504system.cpu1.dcache.occ_percent::total 0.951419 # Average percentage of cache occupancy 1505system.cpu1.dcache.ReadReq_hits::cpu1.data 8613908 # number of ReadReq hits 1506system.cpu1.dcache.ReadReq_hits::total 8613908 # number of ReadReq hits 1507system.cpu1.dcache.WriteReq_hits::cpu1.data 4252702 # number of WriteReq hits 1508system.cpu1.dcache.WriteReq_hits::total 4252702 # number of WriteReq hits 1509system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105106 # number of LoadLockedReq hits 1510system.cpu1.dcache.LoadLockedReq_hits::total 105106 # number of LoadLockedReq hits 1511system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100709 # number of StoreCondReq hits 1512system.cpu1.dcache.StoreCondReq_hits::total 100709 # number of StoreCondReq hits 1513system.cpu1.dcache.demand_hits::cpu1.data 12866610 # number of demand (read+write) hits 1514system.cpu1.dcache.demand_hits::total 12866610 # number of demand (read+write) hits 1515system.cpu1.dcache.overall_hits::cpu1.data 12866610 # number of overall hits 1516system.cpu1.dcache.overall_hits::total 12866610 # number of overall hits 1517system.cpu1.dcache.ReadReq_misses::cpu1.data 410185 # number of ReadReq misses 1518system.cpu1.dcache.ReadReq_misses::total 410185 # number of ReadReq misses 1519system.cpu1.dcache.WriteReq_misses::cpu1.data 1595357 # number of WriteReq misses 1520system.cpu1.dcache.WriteReq_misses::total 1595357 # number of WriteReq misses 1521system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses 1522system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses 1523system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10900 # number of StoreCondReq misses 1524system.cpu1.dcache.StoreCondReq_misses::total 10900 # number of StoreCondReq misses 1525system.cpu1.dcache.demand_misses::cpu1.data 2005542 # number of demand (read+write) misses 1526system.cpu1.dcache.demand_misses::total 2005542 # number of demand (read+write) misses 1527system.cpu1.dcache.overall_misses::cpu1.data 2005542 # number of overall misses 1528system.cpu1.dcache.overall_misses::total 2005542 # number of overall misses 1529system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8114216000 # number of ReadReq miss cycles 1530system.cpu1.dcache.ReadReq_miss_latency::total 8114216000 # number of ReadReq miss cycles 1531system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66620735237 # number of WriteReq miss cycles 1532system.cpu1.dcache.WriteReq_miss_latency::total 66620735237 # number of WriteReq miss cycles 1533system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166584000 # number of LoadLockedReq miss cycles 1534system.cpu1.dcache.LoadLockedReq_miss_latency::total 166584000 # number of LoadLockedReq miss cycles 1535system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94819000 # number of StoreCondReq miss cycles 1536system.cpu1.dcache.StoreCondReq_miss_latency::total 94819000 # number of StoreCondReq miss cycles 1537system.cpu1.dcache.demand_miss_latency::cpu1.data 74734951237 # number of demand (read+write) miss cycles 1538system.cpu1.dcache.demand_miss_latency::total 74734951237 # number of demand (read+write) miss cycles 1539system.cpu1.dcache.overall_miss_latency::cpu1.data 74734951237 # number of overall miss cycles 1540system.cpu1.dcache.overall_miss_latency::total 74734951237 # number of overall miss cycles 1541system.cpu1.dcache.ReadReq_accesses::cpu1.data 9024093 # number of ReadReq accesses(hits+misses) 1542system.cpu1.dcache.ReadReq_accesses::total 9024093 # number of ReadReq accesses(hits+misses) 1543system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848059 # number of WriteReq accesses(hits+misses) 1544system.cpu1.dcache.WriteReq_accesses::total 5848059 # number of WriteReq accesses(hits+misses) 1545system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119384 # number of LoadLockedReq accesses(hits+misses) 1546system.cpu1.dcache.LoadLockedReq_accesses::total 119384 # number of LoadLockedReq accesses(hits+misses) 1547system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111609 # number of StoreCondReq accesses(hits+misses) 1548system.cpu1.dcache.StoreCondReq_accesses::total 111609 # number of StoreCondReq accesses(hits+misses) 1549system.cpu1.dcache.demand_accesses::cpu1.data 14872152 # number of demand (read+write) accesses 1550system.cpu1.dcache.demand_accesses::total 14872152 # number of demand (read+write) accesses 1551system.cpu1.dcache.overall_accesses::cpu1.data 14872152 # number of overall (read+write) accesses 1552system.cpu1.dcache.overall_accesses::total 14872152 # number of overall (read+write) accesses 1553system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045454 # miss rate for ReadReq accesses 1554system.cpu1.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses 1555system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272801 # miss rate for WriteReq accesses 1556system.cpu1.dcache.WriteReq_miss_rate::total 0.272801 # miss rate for WriteReq accesses 1557system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119597 # miss rate for LoadLockedReq accesses 1558system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119597 # miss rate for LoadLockedReq accesses 1559system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097662 # miss rate for StoreCondReq accesses 1560system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097662 # miss rate for StoreCondReq accesses 1561system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134852 # miss rate for demand accesses 1562system.cpu1.dcache.demand_miss_rate::total 0.134852 # miss rate for demand accesses 1563system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134852 # miss rate for overall accesses 1564system.cpu1.dcache.overall_miss_rate::total 0.134852 # miss rate for overall accesses 1565system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777 # average ReadReq miss latency 1566system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777 # average ReadReq miss latency 1567system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326 # average WriteReq miss latency 1568system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326 # average WriteReq miss latency 1569system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277 # average LoadLockedReq miss latency 1570system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277 # average LoadLockedReq miss latency 1571system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8698.990826 # average StoreCondReq miss latency 1572system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8698.990826 # average StoreCondReq miss latency 1573system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency 1574system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475 # average overall miss latency 1575system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency 1576system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475 # average overall miss latency 1577system.cpu1.dcache.blocked_cycles::no_mshrs 29196505 # number of cycles access was blocked 1578system.cpu1.dcache.blocked_cycles::no_targets 5606000 # number of cycles access was blocked 1579system.cpu1.dcache.blocked::no_mshrs 6645 # number of cycles access was blocked 1580system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked 1581system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4393.755455 # average number of cycles each access was blocked 1582system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805 # average number of cycles each access was blocked |
| 1611system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1612system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1583system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1584system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1613system.cpu1.dcache.writebacks::writebacks 330007 # number of writebacks 1614system.cpu1.dcache.writebacks::total 330007 # number of writebacks 1615system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172901 # number of ReadReq MSHR hits 1616system.cpu1.dcache.ReadReq_mshr_hits::total 172901 # number of ReadReq MSHR hits 1617system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1420692 # number of WriteReq MSHR hits 1618system.cpu1.dcache.WriteReq_mshr_hits::total 1420692 # number of WriteReq MSHR hits 1619system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1265 # number of LoadLockedReq MSHR hits 1620system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1265 # number of LoadLockedReq MSHR hits 1621system.cpu1.dcache.demand_mshr_hits::cpu1.data 1593593 # number of demand (read+write) MSHR hits 1622system.cpu1.dcache.demand_mshr_hits::total 1593593 # number of demand (read+write) MSHR hits 1623system.cpu1.dcache.overall_mshr_hits::cpu1.data 1593593 # number of overall MSHR hits 1624system.cpu1.dcache.overall_mshr_hits::total 1593593 # number of overall MSHR hits 1625system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 235252 # number of ReadReq MSHR misses 1626system.cpu1.dcache.ReadReq_mshr_misses::total 235252 # number of ReadReq MSHR misses 1627system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162091 # number of WriteReq MSHR misses 1628system.cpu1.dcache.WriteReq_mshr_misses::total 162091 # number of WriteReq MSHR misses 1629system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12651 # number of LoadLockedReq MSHR misses 1630system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12651 # number of LoadLockedReq MSHR misses 1631system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10796 # number of StoreCondReq MSHR misses 1632system.cpu1.dcache.StoreCondReq_mshr_misses::total 10796 # number of StoreCondReq MSHR misses 1633system.cpu1.dcache.demand_mshr_misses::cpu1.data 397343 # number of demand (read+write) MSHR misses 1634system.cpu1.dcache.demand_mshr_misses::total 397343 # number of demand (read+write) MSHR misses 1635system.cpu1.dcache.overall_mshr_misses::cpu1.data 397343 # number of overall MSHR misses 1636system.cpu1.dcache.overall_mshr_misses::total 397343 # number of overall MSHR misses 1637system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2772800000 # number of ReadReq MSHR miss cycles 1638system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2772800000 # number of ReadReq MSHR miss cycles 1639system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5167139074 # number of WriteReq MSHR miss cycles 1640system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5167139074 # number of WriteReq MSHR miss cycles 1641system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88580000 # number of LoadLockedReq MSHR miss cycles 1642system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88580000 # number of LoadLockedReq MSHR miss cycles 1643system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57154000 # number of StoreCondReq MSHR miss cycles 1644system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57154000 # number of StoreCondReq MSHR miss cycles 1645system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7939939074 # number of demand (read+write) MSHR miss cycles 1646system.cpu1.dcache.demand_mshr_miss_latency::total 7939939074 # number of demand (read+write) MSHR miss cycles 1647system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7939939074 # number of overall MSHR miss cycles 1648system.cpu1.dcache.overall_mshr_miss_latency::total 7939939074 # number of overall MSHR miss cycles 1649system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500 # number of ReadReq MSHR uncacheable cycles 1650system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500 # number of ReadReq MSHR uncacheable cycles 1651system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41654166350 # number of WriteReq MSHR uncacheable cycles 1652system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41654166350 # number of WriteReq MSHR uncacheable cycles 1653system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850 # number of overall MSHR uncacheable cycles 1654system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850 # number of overall MSHR uncacheable cycles 1655system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025561 # mshr miss rate for ReadReq accesses 1656system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025561 # mshr miss rate for ReadReq accesses 1657system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027160 # mshr miss rate for WriteReq accesses 1658system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027160 # mshr miss rate for WriteReq accesses 1659system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104990 # mshr miss rate for LoadLockedReq accesses 1660system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104990 # mshr miss rate for LoadLockedReq accesses 1661system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095471 # mshr miss rate for StoreCondReq accesses 1662system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095471 # mshr miss rate for StoreCondReq accesses 1663system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for demand accesses 1664system.cpu1.dcache.demand_mshr_miss_rate::total 0.026190 # mshr miss rate for demand accesses 1665system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for overall accesses 1666system.cpu1.dcache.overall_mshr_miss_rate::total 0.026190 # mshr miss rate for overall accesses 1667system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785 # average ReadReq mshr miss latency 1668system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785 # average ReadReq mshr miss latency 1669system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425 # average WriteReq mshr miss latency 1670system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425 # average WriteReq mshr miss latency 1671system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7001.818038 # average LoadLockedReq mshr miss latency 1672system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7001.818038 # average LoadLockedReq mshr miss latency 1673system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5293.997777 # average StoreCondReq mshr miss latency 1674system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5293.997777 # average StoreCondReq mshr miss latency 1675system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency 1676system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency 1677system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency 1678system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency | 1585system.cpu1.dcache.writebacks::writebacks 327467 # number of writebacks 1586system.cpu1.dcache.writebacks::total 327467 # number of writebacks 1587system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179191 # number of ReadReq MSHR hits 1588system.cpu1.dcache.ReadReq_mshr_hits::total 179191 # number of ReadReq MSHR hits 1589system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432552 # number of WriteReq MSHR hits 1590system.cpu1.dcache.WriteReq_mshr_hits::total 1432552 # number of WriteReq MSHR hits 1591system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1457 # number of LoadLockedReq MSHR hits 1592system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits 1593system.cpu1.dcache.demand_mshr_hits::cpu1.data 1611743 # number of demand (read+write) MSHR hits 1594system.cpu1.dcache.demand_mshr_hits::total 1611743 # number of demand (read+write) MSHR hits 1595system.cpu1.dcache.overall_mshr_hits::cpu1.data 1611743 # number of overall MSHR hits 1596system.cpu1.dcache.overall_mshr_hits::total 1611743 # number of overall MSHR hits 1597system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 230994 # number of ReadReq MSHR misses 1598system.cpu1.dcache.ReadReq_mshr_misses::total 230994 # number of ReadReq MSHR misses 1599system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162805 # number of WriteReq MSHR misses 1600system.cpu1.dcache.WriteReq_mshr_misses::total 162805 # number of WriteReq MSHR misses 1601system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12821 # number of LoadLockedReq MSHR misses 1602system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12821 # number of LoadLockedReq MSHR misses 1603system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10892 # number of StoreCondReq MSHR misses 1604system.cpu1.dcache.StoreCondReq_mshr_misses::total 10892 # number of StoreCondReq MSHR misses 1605system.cpu1.dcache.demand_mshr_misses::cpu1.data 393799 # number of demand (read+write) MSHR misses 1606system.cpu1.dcache.demand_mshr_misses::total 393799 # number of demand (read+write) MSHR misses 1607system.cpu1.dcache.overall_mshr_misses::cpu1.data 393799 # number of overall MSHR misses 1608system.cpu1.dcache.overall_mshr_misses::total 393799 # number of overall MSHR misses 1609system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3545762451 # number of ReadReq MSHR miss cycles 1610system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3545762451 # number of ReadReq MSHR miss cycles 1611system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5565749199 # number of WriteReq MSHR miss cycles 1612system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5565749199 # number of WriteReq MSHR miss cycles 1613system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104395505 # number of LoadLockedReq MSHR miss cycles 1614system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104395505 # number of LoadLockedReq MSHR miss cycles 1615system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60832506 # number of StoreCondReq MSHR miss cycles 1616system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60832506 # number of StoreCondReq MSHR miss cycles 1617system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1618system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1619system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9111511650 # number of demand (read+write) MSHR miss cycles 1620system.cpu1.dcache.demand_mshr_miss_latency::total 9111511650 # number of demand (read+write) MSHR miss cycles 1621system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9111511650 # number of overall MSHR miss cycles 1622system.cpu1.dcache.overall_mshr_miss_latency::total 9111511650 # number of overall MSHR miss cycles 1623system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500 # number of ReadReq MSHR uncacheable cycles 1624system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500 # number of ReadReq MSHR uncacheable cycles 1625system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40571899654 # number of WriteReq MSHR uncacheable cycles 1626system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40571899654 # number of WriteReq MSHR uncacheable cycles 1627system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154 # number of overall MSHR uncacheable cycles 1628system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154 # number of overall MSHR uncacheable cycles 1629system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for ReadReq accesses 1630system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025597 # mshr miss rate for ReadReq accesses 1631system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027839 # mshr miss rate for WriteReq accesses 1632system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027839 # mshr miss rate for WriteReq accesses 1633system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107393 # mshr miss rate for LoadLockedReq accesses 1634system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107393 # mshr miss rate for LoadLockedReq accesses 1635system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097591 # mshr miss rate for StoreCondReq accesses 1636system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097591 # mshr miss rate for StoreCondReq accesses 1637system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for demand accesses 1638system.cpu1.dcache.demand_mshr_miss_rate::total 0.026479 # mshr miss rate for demand accesses 1639system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for overall accesses 1640system.cpu1.dcache.overall_mshr_miss_rate::total 0.026479 # mshr miss rate for overall accesses 1641system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702 # average ReadReq mshr miss latency 1642system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702 # average ReadReq mshr miss latency 1643system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686 # average WriteReq mshr miss latency 1644system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686 # average WriteReq mshr miss latency 1645system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8142.539973 # average LoadLockedReq mshr miss latency 1646system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8142.539973 # average LoadLockedReq mshr miss latency 1647system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5585.062982 # average StoreCondReq mshr miss latency 1648system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5585.062982 # average StoreCondReq mshr miss latency 1649system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1650system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1651system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency 1652system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency 1653system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency 1654system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency |
| 1679system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1680system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1681system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1682system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1683system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1684system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1685system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1686system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1692system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1693system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1694system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1695system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1696system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1697system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1698system.iocache.fast_writes 0 # number of fast writes performed 1699system.iocache.cache_copies 0 # number of cache copies performed | 1655system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1656system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1657system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1658system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1659system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1660system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1661system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1662system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1668system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1669system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1670system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1671system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1672system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1673system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1674system.iocache.fast_writes 0 # number of fast writes performed 1675system.iocache.cache_copies 0 # number of cache copies performed |
| 1700system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of ReadReq MSHR uncacheable cycles 1701system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055 # number of ReadReq MSHR uncacheable cycles 1702system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of overall MSHR uncacheable cycles 1703system.iocache.overall_mshr_uncacheable_latency::total 1308136748055 # number of overall MSHR uncacheable cycles | 1676system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of ReadReq MSHR uncacheable cycles 1677system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135 # number of ReadReq MSHR uncacheable cycles 1678system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of overall MSHR uncacheable cycles 1679system.iocache.overall_mshr_uncacheable_latency::total 1305278151135 # number of overall MSHR uncacheable cycles |
| 1704system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1705system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1706system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1707system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1708system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1709system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1680system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1681system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1682system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1683system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1684system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1685system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1710system.cpu0.kern.inst.quiesce 42935 # number of quiesce instructions executed | 1686system.cpu0.kern.inst.quiesce 43785 # number of quiesce instructions executed |
| 1711system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1687system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1712system.cpu1.kern.inst.quiesce 54742 # number of quiesce instructions executed | 1688system.cpu1.kern.inst.quiesce 53912 # number of quiesce instructions executed |
| 1713 1714---------- End Simulation Statistics ---------- | 1689 1690---------- End Simulation Statistics ---------- |