| stats.txt (9005:f681719e2e99) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.570834 # Number of seconds simulated 4sim_ticks 2570833934500 # Number of ticks simulated 5final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.570834 # Number of seconds simulated 4sim_ticks 2570833934500 # Number of ticks simulated 5final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 63716 # Simulator instruction rate (inst/s) 8host_op_rate 82290 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2641493756 # Simulator tick rate (ticks/s) 10host_mem_usage 388068 # Number of bytes of host memory used 11host_seconds 973.25 # Real time elapsed on the host | 7host_inst_rate 53678 # Simulator instruction rate (inst/s) 8host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2225327298 # Simulator tick rate (ticks/s) 10host_mem_usage 390932 # Number of bytes of host memory used 11host_seconds 1155.26 # Real time elapsed on the host |
| 12sim_insts 62012062 # Number of instructions simulated 13sim_ops 80088895 # Number of ops (including micro ops) simulated | 12sim_insts 62012062 # Number of instructions simulated 13sim_ops 80088895 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 131429540 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1199424 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10175696 # Number of bytes written to this memory 17system.physmem.num_reads 15128117 # Number of read requests responded to by this memory 18system.physmem.num_writes 868949 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 51123310 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 466551 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 3958130 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 55081440 # Total bandwidth to/from this memory (bytes/s) 24system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory 23system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 30system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) 73system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 74system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory 76system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 79system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 80system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory 82system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 86system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) 87system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) 88system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 89system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) 90system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) |
| 33system.l2c.replacements 130926 # number of replacements 34system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use 35system.l2c.total_refs 1855308 # Total number of references to valid blocks. 36system.l2c.sampled_refs 161029 # Sample count of references to valid blocks. 37system.l2c.avg_refs 11.521577 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 15187.159331 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu0.dtb.walker 17.600608 # Average occupied blocks per requestor --- 165 unchanged lines hidden (view full) --- 206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for ReadReq accesses 207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000869 # miss rate for ReadReq accesses 208system.l2c.ReadReq_miss_rate::cpu0.inst 0.024345 # miss rate for ReadReq accesses 209system.l2c.ReadReq_miss_rate::cpu0.data 0.061877 # miss rate for ReadReq accesses 210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for ReadReq accesses 211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses 212system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses 213system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses | 91system.l2c.replacements 130926 # number of replacements 92system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use 93system.l2c.total_refs 1855308 # Total number of references to valid blocks. 94system.l2c.sampled_refs 161029 # Sample count of references to valid blocks. 95system.l2c.avg_refs 11.521577 # Average number of references to valid blocks. 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 97system.l2c.occ_blocks::writebacks 15187.159331 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 17.600608 # Average occupied blocks per requestor --- 165 unchanged lines hidden (view full) --- 264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for ReadReq accesses 265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000869 # miss rate for ReadReq accesses 266system.l2c.ReadReq_miss_rate::cpu0.inst 0.024345 # miss rate for ReadReq accesses 267system.l2c.ReadReq_miss_rate::cpu0.data 0.061877 # miss rate for ReadReq accesses 268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses |
| 272system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses |
|
| 214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses 215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses | 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses 274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses |
| 275system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses |
|
| 216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses 217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses | 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses 277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses |
| 278system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses |
|
| 218system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses 219system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses | 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses 280system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses |
| 281system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses |
|
| 220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses 221system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses 222system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses 223system.l2c.demand_miss_rate::cpu0.data 0.306759 # miss rate for demand accesses 224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for demand accesses 225system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses 226system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses 227system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses | 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses 283system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses 284system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.data 0.306759 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses |
| 290system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses |
|
| 228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses 229system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses 230system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses 231system.l2c.overall_miss_rate::cpu0.data 0.306759 # miss rate for overall accesses 232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for overall accesses 233system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses 234system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses 235system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses | 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.306759 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses |
| 299system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses |
|
| 236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency 237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency 238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency 239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.838160 # average ReadReq miss latency 240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average ReadReq miss latency 241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency 242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency 243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency | 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.838160 # average ReadReq miss latency 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average ReadReq miss latency 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency |
| 308system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency |
|
| 244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency 245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency | 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency |
| 311system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency |
|
| 246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency 247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency | 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency |
| 314system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency |
|
| 248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency 249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency | 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency |
| 317system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency |
|
| 250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency 251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency 252system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency 253system.l2c.demand_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency 254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency 255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 256system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency 257system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency | 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency 320system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 324system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency |
| 326system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency |
|
| 258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency 259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency 260system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency 261system.l2c.overall_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency 262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency 263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 264system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency 265system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency | 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency 329system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 333system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency |
| 335system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency |
|
| 266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 269system.l2c.blocked::no_targets 0 # number of cycles access was blocked 270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 272system.l2c.fast_writes 0 # number of fast writes performed 273system.l2c.cache_copies 0 # number of cache copies performed --- 102 unchanged lines hidden (view full) --- 376system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for ReadReq accesses 377system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for ReadReq accesses 378system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for ReadReq accesses 379system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061547 # mshr miss rate for ReadReq accesses 380system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses 381system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses 382system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses 383system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses | 336system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 337system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 338system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 339system.l2c.blocked::no_targets 0 # number of cycles access was blocked 340system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 341system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 342system.l2c.fast_writes 0 # number of fast writes performed 343system.l2c.cache_copies 0 # number of cache copies performed --- 102 unchanged lines hidden (view full) --- 446system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for ReadReq accesses 447system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for ReadReq accesses 449system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061547 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses 452system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses 453system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses |
| 454system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses |
|
| 384system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses 385system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses | 455system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses 456system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses |
| 457system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses |
|
| 386system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses 387system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses | 458system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses 459system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses |
| 460system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses |
|
| 388system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses 389system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses | 461system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses 462system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses |
| 463system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses |
|
| 390system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses 391system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses 392system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses 393system.l2c.demand_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for demand accesses 394system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for demand accesses 395system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses 396system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses 397system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses | 464system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses 466system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses 467system.l2c.demand_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for demand accesses 469system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses 470system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses 471system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses |
| 472system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses |
|
| 398system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses 399system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses 400system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses 401system.l2c.overall_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for overall accesses 402system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for overall accesses 403system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses 404system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses 405system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses | 473system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses 474system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses 475system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses 476system.l2c.overall_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for overall accesses 477system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for overall accesses 478system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses 479system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses 480system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses |
| 481system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses |
|
| 406system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency 407system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency 408system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency 409system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40057.319023 # average ReadReq mshr miss latency 410system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average ReadReq mshr miss latency 411system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 412system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency 413system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency | 482system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency 483system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency 484system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency 485system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40057.319023 # average ReadReq mshr miss latency 486system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average ReadReq mshr miss latency 487system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 488system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency 489system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency |
| 490system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency |
|
| 414system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency 415system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency | 491system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency 492system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency |
| 493system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency |
|
| 416system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency 417system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency | 494system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency 495system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency |
| 496system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency |
|
| 418system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency 419system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency | 497system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency 498system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency |
| 499system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency |
|
| 420system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency 421system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency 422system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency 423system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency 424system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency 425system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 426system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency 427system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency | 500system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency 501system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency 502system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency 503system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency 504system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency 505system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 506system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency 507system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency |
| 508system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency |
|
| 428system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency 429system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency 430system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency 431system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency 432system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency 433system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 434system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency 435system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency | 509system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency 510system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency 511system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency 512system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency 513system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency 514system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 515system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency 516system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency |
| 517system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency |
|
| 436system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 437system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 438system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 439system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency | 518system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 519system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 520system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 521system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency |
| 522system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 440system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 441system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency | 523system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 524system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |
| 525system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 442system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 443system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 444system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 445system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency | 526system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 527system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 528system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 529system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency |
| 530system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 446system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 447system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 448system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 449system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 450system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 451system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 452system.cf0.dma_write_txs 0 # Number of DMA write transactions. 453system.cpu0.dtb.inst_hits 0 # ITB inst hits --- 343 unchanged lines hidden (view full) --- 797system.cpu0.icache.overall_miss_latency::total 5700257984 # number of overall miss cycles 798system.cpu0.icache.ReadReq_accesses::cpu0.inst 3831829 # number of ReadReq accesses(hits+misses) 799system.cpu0.icache.ReadReq_accesses::total 3831829 # number of ReadReq accesses(hits+misses) 800system.cpu0.icache.demand_accesses::cpu0.inst 3831829 # number of demand (read+write) accesses 801system.cpu0.icache.demand_accesses::total 3831829 # number of demand (read+write) accesses 802system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses 803system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses 804system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses | 531system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 533system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 534system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 535system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 536system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 537system.cf0.dma_write_txs 0 # Number of DMA write transactions. 538system.cpu0.dtb.inst_hits 0 # ITB inst hits --- 343 unchanged lines hidden (view full) --- 882system.cpu0.icache.overall_miss_latency::total 5700257984 # number of overall miss cycles 883system.cpu0.icache.ReadReq_accesses::cpu0.inst 3831829 # number of ReadReq accesses(hits+misses) 884system.cpu0.icache.ReadReq_accesses::total 3831829 # number of ReadReq accesses(hits+misses) 885system.cpu0.icache.demand_accesses::cpu0.inst 3831829 # number of demand (read+write) accesses 886system.cpu0.icache.demand_accesses::total 3831829 # number of demand (read+write) accesses 887system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses 888system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses 889system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses |
| 890system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses |
|
| 805system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses | 891system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses |
| 892system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses |
|
| 806system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses | 893system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses |
| 894system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses |
|
| 807system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency | 895system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency |
| 896system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency |
|
| 808system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency | 897system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency |
| 898system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency |
|
| 809system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency | 899system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency |
| 900system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency |
|
| 810system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked 811system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 812system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked 813system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 814system.cpu0.icache.avg_blocked_cycles::no_mshrs 8546.023041 # average number of cycles each access was blocked 815system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 816system.cpu0.icache.fast_writes 0 # number of fast writes performed 817system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 835system.cpu0.icache.demand_mshr_miss_latency::total 4268453987 # number of demand (read+write) MSHR miss cycles 836system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4268453987 # number of overall MSHR miss cycles 837system.cpu0.icache.overall_mshr_miss_latency::total 4268453987 # number of overall MSHR miss cycles 838system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles 839system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles 840system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles 841system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles 842system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses | 901system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked 902system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked 904system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu0.icache.avg_blocked_cycles::no_mshrs 8546.023041 # average number of cycles each access was blocked 906system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu0.icache.fast_writes 0 # number of fast writes performed 908system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 926system.cpu0.icache.demand_mshr_miss_latency::total 4268453987 # number of demand (read+write) MSHR miss cycles 927system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4268453987 # number of overall MSHR miss cycles 928system.cpu0.icache.overall_mshr_miss_latency::total 4268453987 # number of overall MSHR miss cycles 929system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles 930system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles 931system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles 932system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles 933system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses |
| 934system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses |
|
| 843system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses | 935system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses |
| 936system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses |
|
| 844system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses | 937system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses |
| 938system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses |
|
| 845system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency | 939system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency |
| 940system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency |
|
| 846system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency | 941system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency |
| 942system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency |
|
| 847system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency | 943system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency |
| 944system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency |
|
| 848system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency | 945system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency |
| 946system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 849system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency | 947system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency |
| 948system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 850system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 851system.cpu0.dcache.replacements 232498 # number of replacements 852system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use 853system.cpu0.dcache.total_refs 7750511 # Total number of references to valid blocks. 854system.cpu0.dcache.sampled_refs 232862 # Sample count of references to valid blocks. 855system.cpu0.dcache.avg_refs 33.283709 # Average number of references to valid blocks. 856system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit. 857system.cpu0.dcache.occ_blocks::cpu0.data 430.308093 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 901system.cpu0.dcache.LoadLockedReq_accesses::total 163597 # number of LoadLockedReq accesses(hits+misses) 902system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160348 # number of StoreCondReq accesses(hits+misses) 903system.cpu0.dcache.StoreCondReq_accesses::total 160348 # number of StoreCondReq accesses(hits+misses) 904system.cpu0.dcache.demand_accesses::cpu0.data 9184667 # number of demand (read+write) accesses 905system.cpu0.dcache.demand_accesses::total 9184667 # number of demand (read+write) accesses 906system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses 907system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses 908system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses | 949system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 950system.cpu0.dcache.replacements 232498 # number of replacements 951system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use 952system.cpu0.dcache.total_refs 7750511 # Total number of references to valid blocks. 953system.cpu0.dcache.sampled_refs 232862 # Sample count of references to valid blocks. 954system.cpu0.dcache.avg_refs 33.283709 # Average number of references to valid blocks. 955system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit. 956system.cpu0.dcache.occ_blocks::cpu0.data 430.308093 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 1000system.cpu0.dcache.LoadLockedReq_accesses::total 163597 # number of LoadLockedReq accesses(hits+misses) 1001system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160348 # number of StoreCondReq accesses(hits+misses) 1002system.cpu0.dcache.StoreCondReq_accesses::total 160348 # number of StoreCondReq accesses(hits+misses) 1003system.cpu0.dcache.demand_accesses::cpu0.data 9184667 # number of demand (read+write) accesses 1004system.cpu0.dcache.demand_accesses::total 9184667 # number of demand (read+write) accesses 1005system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses 1006system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses 1007system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses |
| 1008system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses |
|
| 909system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses | 1009system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses |
| 1010system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses |
|
| 910system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses | 1011system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses |
| 1012system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses |
|
| 911system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses | 1013system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses |
| 1014system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses |
|
| 912system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses | 1015system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses |
| 1016system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses |
|
| 913system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses | 1017system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses |
| 1018system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses |
|
| 914system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency | 1019system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency |
| 1020system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency |
|
| 915system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency | 1021system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency |
| 1022system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency |
|
| 916system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency | 1023system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency |
| 1024system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency |
|
| 917system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency | 1025system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency |
| 1026system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency |
|
| 918system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency | 1027system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency |
| 1028system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency |
|
| 919system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency | 1029system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency |
| 1030system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency |
|
| 920system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked 921system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked 922system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked 923system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked 924system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10316.831395 # average number of cycles each access was blocked 925system.cpu0.dcache.avg_blocked_cycles::no_targets 20542.553191 # average number of cycles each access was blocked 926system.cpu0.dcache.fast_writes 0 # number of fast writes performed 927system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 35 unchanged lines hidden (view full) --- 963system.cpu0.dcache.overall_mshr_miss_latency::total 6305406989 # number of overall MSHR miss cycles 964system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9221981000 # number of ReadReq MSHR uncacheable cycles 965system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9221981000 # number of ReadReq MSHR uncacheable cycles 966system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843217391 # number of WriteReq MSHR uncacheable cycles 967system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 # number of WriteReq MSHR uncacheable cycles 968system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles 969system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles 970system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses | 1031system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked 1032system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked 1033system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked 1034system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked 1035system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10316.831395 # average number of cycles each access was blocked 1036system.cpu0.dcache.avg_blocked_cycles::no_targets 20542.553191 # average number of cycles each access was blocked 1037system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1038system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 35 unchanged lines hidden (view full) --- 1074system.cpu0.dcache.overall_mshr_miss_latency::total 6305406989 # number of overall MSHR miss cycles 1075system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9221981000 # number of ReadReq MSHR uncacheable cycles 1076system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9221981000 # number of ReadReq MSHR uncacheable cycles 1077system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843217391 # number of WriteReq MSHR uncacheable cycles 1078system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 # number of WriteReq MSHR uncacheable cycles 1079system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles 1080system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles 1081system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses |
| 1082system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses |
|
| 971system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses | 1083system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses |
| 1084system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses |
|
| 972system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses | 1085system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses |
| 1086system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses |
|
| 973system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses | 1087system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses |
| 1088system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses |
|
| 974system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses | 1089system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses |
| 1090system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses |
|
| 975system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses | 1091system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses |
| 1092system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses |
|
| 976system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency | 1093system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency |
| 1094system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency |
|
| 977system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency | 1095system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency |
| 1096system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency |
|
| 978system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency | 1097system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency |
| 1098system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency |
|
| 979system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency | 1099system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency |
| 1100system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency |
|
| 980system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency | 1101system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency |
| 1102system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency |
|
| 981system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency | 1103system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency |
| 1104system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency |
|
| 982system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency | 1105system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency |
| 1106system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 983system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency | 1107system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency |
| 1108system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 984system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency | 1109system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency |
| 1110system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 985system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 986system.cpu1.dtb.inst_hits 0 # ITB inst hits 987system.cpu1.dtb.inst_misses 0 # ITB inst misses 988system.cpu1.dtb.read_hits 45335988 # DTB read hits 989system.cpu1.dtb.read_misses 67766 # DTB read misses 990system.cpu1.dtb.write_hits 7974825 # DTB write hits 991system.cpu1.dtb.write_misses 20571 # DTB write misses 992system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed --- 337 unchanged lines hidden (view full) --- 1330system.cpu1.icache.overall_miss_latency::total 11390030990 # number of overall miss cycles 1331system.cpu1.icache.ReadReq_accesses::cpu1.inst 10441732 # number of ReadReq accesses(hits+misses) 1332system.cpu1.icache.ReadReq_accesses::total 10441732 # number of ReadReq accesses(hits+misses) 1333system.cpu1.icache.demand_accesses::cpu1.inst 10441732 # number of demand (read+write) accesses 1334system.cpu1.icache.demand_accesses::total 10441732 # number of demand (read+write) accesses 1335system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses 1336system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses 1337system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses | 1111system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1112system.cpu1.dtb.inst_hits 0 # ITB inst hits 1113system.cpu1.dtb.inst_misses 0 # ITB inst misses 1114system.cpu1.dtb.read_hits 45335988 # DTB read hits 1115system.cpu1.dtb.read_misses 67766 # DTB read misses 1116system.cpu1.dtb.write_hits 7974825 # DTB write hits 1117system.cpu1.dtb.write_misses 20571 # DTB write misses 1118system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed --- 337 unchanged lines hidden (view full) --- 1456system.cpu1.icache.overall_miss_latency::total 11390030990 # number of overall miss cycles 1457system.cpu1.icache.ReadReq_accesses::cpu1.inst 10441732 # number of ReadReq accesses(hits+misses) 1458system.cpu1.icache.ReadReq_accesses::total 10441732 # number of ReadReq accesses(hits+misses) 1459system.cpu1.icache.demand_accesses::cpu1.inst 10441732 # number of demand (read+write) accesses 1460system.cpu1.icache.demand_accesses::total 10441732 # number of demand (read+write) accesses 1461system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses 1462system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses 1463system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses |
| 1464system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses |
|
| 1338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses | 1465system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses |
| 1466system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses |
|
| 1339system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses | 1467system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses |
| 1468system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses |
|
| 1340system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency | 1469system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency |
| 1470system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency |
|
| 1341system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency | 1471system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency |
| 1472system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency |
|
| 1342system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency | 1473system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency |
| 1474system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency |
|
| 1343system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked 1344system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1345system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked 1346system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1347system.cpu1.icache.avg_blocked_cycles::no_mshrs 6609.210084 # average number of cycles each access was blocked 1348system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1349system.cpu1.icache.fast_writes 0 # number of fast writes performed 1350system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 1368system.cpu1.icache.demand_mshr_miss_latency::total 8506439492 # number of demand (read+write) MSHR miss cycles 1369system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8506439492 # number of overall MSHR miss cycles 1370system.cpu1.icache.overall_mshr_miss_latency::total 8506439492 # number of overall MSHR miss cycles 1371system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles 1372system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles 1373system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles 1374system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles 1375system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses | 1475system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked 1476system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1477system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked 1478system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1479system.cpu1.icache.avg_blocked_cycles::no_mshrs 6609.210084 # average number of cycles each access was blocked 1480system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1481system.cpu1.icache.fast_writes 0 # number of fast writes performed 1482system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 1500system.cpu1.icache.demand_mshr_miss_latency::total 8506439492 # number of demand (read+write) MSHR miss cycles 1501system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8506439492 # number of overall MSHR miss cycles 1502system.cpu1.icache.overall_mshr_miss_latency::total 8506439492 # number of overall MSHR miss cycles 1503system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles 1504system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles 1505system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles 1506system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles 1507system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses |
| 1508system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses |
|
| 1376system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses | 1509system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses |
| 1510system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses |
|
| 1377system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses | 1511system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses |
| 1512system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses |
|
| 1378system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency | 1513system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency |
| 1514system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency |
|
| 1379system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency | 1515system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency |
| 1516system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency |
|
| 1380system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency | 1517system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency |
| 1518system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency |
|
| 1381system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency | 1519system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency |
| 1520system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 1382system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency | 1521system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency |
| 1522system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 1383system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1384system.cpu1.dcache.replacements 417022 # number of replacements 1385system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use 1386system.cpu1.dcache.total_refs 15242379 # Total number of references to valid blocks. 1387system.cpu1.dcache.sampled_refs 417534 # Sample count of references to valid blocks. 1388system.cpu1.dcache.avg_refs 36.505719 # Average number of references to valid blocks. 1389system.cpu1.dcache.warmup_cycle 72565634000 # Cycle when the warmup percentage was hit. 1390system.cpu1.dcache.occ_blocks::cpu1.data 464.475329 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 1434system.cpu1.dcache.LoadLockedReq_accesses::total 141213 # number of LoadLockedReq accesses(hits+misses) 1435system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130601 # number of StoreCondReq accesses(hits+misses) 1436system.cpu1.dcache.StoreCondReq_accesses::total 130601 # number of StoreCondReq accesses(hits+misses) 1437system.cpu1.dcache.demand_accesses::cpu1.data 17145866 # number of demand (read+write) accesses 1438system.cpu1.dcache.demand_accesses::total 17145866 # number of demand (read+write) accesses 1439system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses 1440system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses 1441system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses | 1523system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1524system.cpu1.dcache.replacements 417022 # number of replacements 1525system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use 1526system.cpu1.dcache.total_refs 15242379 # Total number of references to valid blocks. 1527system.cpu1.dcache.sampled_refs 417534 # Sample count of references to valid blocks. 1528system.cpu1.dcache.avg_refs 36.505719 # Average number of references to valid blocks. 1529system.cpu1.dcache.warmup_cycle 72565634000 # Cycle when the warmup percentage was hit. 1530system.cpu1.dcache.occ_blocks::cpu1.data 464.475329 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 1574system.cpu1.dcache.LoadLockedReq_accesses::total 141213 # number of LoadLockedReq accesses(hits+misses) 1575system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130601 # number of StoreCondReq accesses(hits+misses) 1576system.cpu1.dcache.StoreCondReq_accesses::total 130601 # number of StoreCondReq accesses(hits+misses) 1577system.cpu1.dcache.demand_accesses::cpu1.data 17145866 # number of demand (read+write) accesses 1578system.cpu1.dcache.demand_accesses::total 17145866 # number of demand (read+write) accesses 1579system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses 1580system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses 1581system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses |
| 1582system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses |
|
| 1442system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses | 1583system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses |
| 1584system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses |
|
| 1443system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses | 1585system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses |
| 1586system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses |
|
| 1444system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses | 1587system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses |
| 1588system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses |
|
| 1445system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses | 1589system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses |
| 1590system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses |
|
| 1446system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses | 1591system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses |
| 1592system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses |
|
| 1447system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency | 1593system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency |
| 1594system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency |
|
| 1448system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency | 1595system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency |
| 1596system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency |
|
| 1449system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency | 1597system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency |
| 1598system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency |
|
| 1450system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency | 1599system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency |
| 1600system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency |
|
| 1451system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency | 1601system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency |
| 1602system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency |
|
| 1452system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency | 1603system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency |
| 1604system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency |
|
| 1453system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked 1454system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked 1455system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked 1456system.cpu1.dcache.blocked::no_targets 149 # number of cycles access was blocked 1457system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4702.128642 # average number of cycles each access was blocked 1458system.cpu1.dcache.avg_blocked_cycles::no_targets 35590.604027 # average number of cycles each access was blocked 1459system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1460system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 37 unchanged lines hidden (view full) --- 1498system.cpu1.dcache.overall_mshr_miss_latency::total 8961010067 # number of overall MSHR miss cycles 1499system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000 # number of ReadReq MSHR uncacheable cycles 1500system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000 # number of ReadReq MSHR uncacheable cycles 1501system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41662340533 # number of WriteReq MSHR uncacheable cycles 1502system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 # number of WriteReq MSHR uncacheable cycles 1503system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles 1504system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles 1505system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses | 1605system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked 1606system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked 1607system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked 1608system.cpu1.dcache.blocked::no_targets 149 # number of cycles access was blocked 1609system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4702.128642 # average number of cycles each access was blocked 1610system.cpu1.dcache.avg_blocked_cycles::no_targets 35590.604027 # average number of cycles each access was blocked 1611system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1612system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 37 unchanged lines hidden (view full) --- 1650system.cpu1.dcache.overall_mshr_miss_latency::total 8961010067 # number of overall MSHR miss cycles 1651system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000 # number of ReadReq MSHR uncacheable cycles 1652system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000 # number of ReadReq MSHR uncacheable cycles 1653system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41662340533 # number of WriteReq MSHR uncacheable cycles 1654system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 # number of WriteReq MSHR uncacheable cycles 1655system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles 1656system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles 1657system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses |
| 1658system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses |
|
| 1506system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses | 1659system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses |
| 1660system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses |
|
| 1507system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses | 1661system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses |
| 1662system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses |
|
| 1508system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses | 1663system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses |
| 1664system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses |
|
| 1509system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses | 1665system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses |
| 1666system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses |
|
| 1510system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses | 1667system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses |
| 1668system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses |
|
| 1511system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency | 1669system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency |
| 1670system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency |
|
| 1512system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency | 1671system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency |
| 1672system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency |
|
| 1513system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency | 1673system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency |
| 1674system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency |
|
| 1514system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency | 1675system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency |
| 1676system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency |
|
| 1515system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency | 1677system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency |
| 1678system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
|
| 1516system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency | 1679system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency |
| 1680system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency |
|
| 1517system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency | 1681system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency |
| 1682system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency |
|
| 1518system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency | 1683system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency |
| 1684system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 1519system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency | 1685system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |
| 1686system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 1520system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency | 1687system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency |
| 1688system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 1521system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1522system.iocache.replacements 0 # number of replacements 1523system.iocache.tagsinuse 0 # Cycle average of tags in use 1524system.iocache.total_refs 0 # Total number of references to valid blocks. 1525system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1526system.iocache.avg_refs nan # Average number of references to valid blocks. 1527system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1528system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 1533system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1534system.iocache.fast_writes 0 # number of fast writes performed 1535system.iocache.cache_copies 0 # number of cache copies performed 1536system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of ReadReq MSHR uncacheable cycles 1537system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 # number of ReadReq MSHR uncacheable cycles 1538system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles 1539system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles 1540system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency | 1689system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1690system.iocache.replacements 0 # number of replacements 1691system.iocache.tagsinuse 0 # Cycle average of tags in use 1692system.iocache.total_refs 0 # Total number of references to valid blocks. 1693system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1694system.iocache.avg_refs nan # Average number of references to valid blocks. 1695system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1696system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 1701system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1702system.iocache.fast_writes 0 # number of fast writes performed 1703system.iocache.cache_copies 0 # number of cache copies performed 1704system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of ReadReq MSHR uncacheable cycles 1705system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 # number of ReadReq MSHR uncacheable cycles 1706system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles 1707system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles 1708system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency |
| 1709system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 1541system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency | 1710system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |
| 1711system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 1542system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1543system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1544system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed 1545system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1546system.cpu1.kern.inst.quiesce 61621 # number of quiesce instructions executed 1547 1548---------- End Simulation Statistics ---------- | 1712system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1713system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1714system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed 1715system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1716system.cpu1.kern.inst.quiesce 61621 # number of quiesce instructions executed 1717 1718---------- End Simulation Statistics ---------- |