| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.570828 # Number of seconds simulated 4sim_ticks 2570828403500 # Number of ticks simulated 5final_tick 2570828403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.570828 # Number of seconds simulated 4sim_ticks 2570828403500 # Number of ticks simulated 5final_tick 2570828403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 96885 # Simulator instruction rate (inst/s) 8host_op_rate 125154 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4026902595 # Simulator tick rate (ticks/s) 10host_mem_usage 385208 # Number of bytes of host memory used 11host_seconds 638.41 # Real time elapsed on the host | 7host_inst_rate 36466 # Simulator instruction rate (inst/s) 8host_op_rate 47106 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1515652841 # Simulator tick rate (ticks/s) 10host_mem_usage 392156 # Number of bytes of host memory used 11host_seconds 1696.19 # Real time elapsed on the host |
| 12sim_insts 61852501 # Number of instructions simulated 13sim_ops 79899751 # Number of ops (including micro ops) simulated | 12sim_insts 61852501 # Number of instructions simulated 13sim_ops 79899751 # Number of ops (including micro ops) simulated |
| 14system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory 15system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory 16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory 18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) 22system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) | |
| 23system.physmem.bytes_read 131418468 # Number of bytes read from this memory 24system.physmem.bytes_inst_read 1192320 # Number of instructions bytes read from this memory 25system.physmem.bytes_written 10172560 # Number of bytes written to this memory 26system.physmem.num_reads 15127944 # Number of read requests responded to by this memory 27system.physmem.num_writes 868900 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 51119113 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 463788 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 3956919 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 55076032 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read 131418468 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1192320 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10172560 # Number of bytes written to this memory 17system.physmem.num_reads 15127944 # Number of read requests responded to by this memory 18system.physmem.num_writes 868900 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 51119113 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 463788 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 3956919 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 55076032 # Total bandwidth to/from this memory (bytes/s) |
| 24system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) |
|
| 33system.l2c.replacements 130877 # number of replacements 34system.l2c.tagsinuse 27573.095607 # Cycle average of tags in use 35system.l2c.total_refs 1846037 # Total number of references to valid blocks. 36system.l2c.sampled_refs 160860 # Sample count of references to valid blocks. 37system.l2c.avg_refs 11.476047 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 15182.704930 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu0.dtb.walker 18.055930 # Average occupied blocks per requestor --- 221 unchanged lines hidden (view full) --- 262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency 263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 264system.l2c.overall_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency 265system.l2c.overall_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency 266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 269system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 33system.l2c.replacements 130877 # number of replacements 34system.l2c.tagsinuse 27573.095607 # Cycle average of tags in use 35system.l2c.total_refs 1846037 # Total number of references to valid blocks. 36system.l2c.sampled_refs 160860 # Sample count of references to valid blocks. 37system.l2c.avg_refs 11.476047 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 15182.704930 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu0.dtb.walker 18.055930 # Average occupied blocks per requestor --- 221 unchanged lines hidden (view full) --- 262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency 263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 264system.l2c.overall_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency 265system.l2c.overall_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency 266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 269system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 270system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 271system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 272system.l2c.fast_writes 0 # number of fast writes performed 273system.l2c.cache_copies 0 # number of cache copies performed 274system.l2c.writebacks::writebacks 111616 # number of writebacks 275system.l2c.writebacks::total 111616 # number of writebacks 276system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits 277system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits 278system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits 279system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits --- 527 unchanged lines hidden (view full) --- 807system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15192.075771 # average ReadReq miss latency 808system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency 809system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency 810system.cpu0.icache.blocked_cycles::no_mshrs 1691991 # number of cycles access was blocked 811system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 812system.cpu0.icache.blocked::no_mshrs 206 # number of cycles access was blocked 813system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 814system.cpu0.icache.avg_blocked_cycles::no_mshrs 8213.548544 # average number of cycles each access was blocked | 272system.l2c.fast_writes 0 # number of fast writes performed 273system.l2c.cache_copies 0 # number of cache copies performed 274system.l2c.writebacks::writebacks 111616 # number of writebacks 275system.l2c.writebacks::total 111616 # number of writebacks 276system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits 277system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits 278system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits 279system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits --- 527 unchanged lines hidden (view full) --- 807system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15192.075771 # average ReadReq miss latency 808system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency 809system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency 810system.cpu0.icache.blocked_cycles::no_mshrs 1691991 # number of cycles access was blocked 811system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 812system.cpu0.icache.blocked::no_mshrs 206 # number of cycles access was blocked 813system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 814system.cpu0.icache.avg_blocked_cycles::no_mshrs 8213.548544 # average number of cycles each access was blocked |
| 815system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 815system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 816system.cpu0.icache.fast_writes 0 # number of fast writes performed 817system.cpu0.icache.cache_copies 0 # number of cache copies performed 818system.cpu0.icache.writebacks::writebacks 19233 # number of writebacks 819system.cpu0.icache.writebacks::total 19233 # number of writebacks 820system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29370 # number of ReadReq MSHR hits 821system.cpu0.icache.ReadReq_mshr_hits::total 29370 # number of ReadReq MSHR hits 822system.cpu0.icache.demand_mshr_hits::cpu0.inst 29370 # number of demand (read+write) MSHR hits 823system.cpu0.icache.demand_mshr_hits::total 29370 # number of demand (read+write) MSHR hits --- 516 unchanged lines hidden (view full) --- 1340system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.627953 # average ReadReq miss latency 1341system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency 1342system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency 1343system.cpu1.icache.blocked_cycles::no_mshrs 1533994 # number of cycles access was blocked 1344system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1345system.cpu1.icache.blocked::no_mshrs 234 # number of cycles access was blocked 1346system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1347system.cpu1.icache.avg_blocked_cycles::no_mshrs 6555.529915 # average number of cycles each access was blocked | 816system.cpu0.icache.fast_writes 0 # number of fast writes performed 817system.cpu0.icache.cache_copies 0 # number of cache copies performed 818system.cpu0.icache.writebacks::writebacks 19233 # number of writebacks 819system.cpu0.icache.writebacks::total 19233 # number of writebacks 820system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29370 # number of ReadReq MSHR hits 821system.cpu0.icache.ReadReq_mshr_hits::total 29370 # number of ReadReq MSHR hits 822system.cpu0.icache.demand_mshr_hits::cpu0.inst 29370 # number of demand (read+write) MSHR hits 823system.cpu0.icache.demand_mshr_hits::total 29370 # number of demand (read+write) MSHR hits --- 516 unchanged lines hidden (view full) --- 1340system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.627953 # average ReadReq miss latency 1341system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency 1342system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency 1343system.cpu1.icache.blocked_cycles::no_mshrs 1533994 # number of cycles access was blocked 1344system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1345system.cpu1.icache.blocked::no_mshrs 234 # number of cycles access was blocked 1346system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1347system.cpu1.icache.avg_blocked_cycles::no_mshrs 6555.529915 # average number of cycles each access was blocked |
| 1348system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1348system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1349system.cpu1.icache.fast_writes 0 # number of fast writes performed 1350system.cpu1.icache.cache_copies 0 # number of cache copies performed 1351system.cpu1.icache.writebacks::writebacks 32964 # number of writebacks 1352system.cpu1.icache.writebacks::total 32964 # number of writebacks 1353system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 60264 # number of ReadReq MSHR hits 1354system.cpu1.icache.ReadReq_mshr_hits::total 60264 # number of ReadReq MSHR hits 1355system.cpu1.icache.demand_mshr_hits::cpu1.inst 60264 # number of demand (read+write) MSHR hits 1356system.cpu1.icache.demand_mshr_hits::total 60264 # number of demand (read+write) MSHR hits --- 161 unchanged lines hidden (view full) --- 1518system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1519system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1520system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1521system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1522system.iocache.replacements 0 # number of replacements 1523system.iocache.tagsinuse 0 # Cycle average of tags in use 1524system.iocache.total_refs 0 # Total number of references to valid blocks. 1525system.iocache.sampled_refs 0 # Sample count of references to valid blocks. | 1349system.cpu1.icache.fast_writes 0 # number of fast writes performed 1350system.cpu1.icache.cache_copies 0 # number of cache copies performed 1351system.cpu1.icache.writebacks::writebacks 32964 # number of writebacks 1352system.cpu1.icache.writebacks::total 32964 # number of writebacks 1353system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 60264 # number of ReadReq MSHR hits 1354system.cpu1.icache.ReadReq_mshr_hits::total 60264 # number of ReadReq MSHR hits 1355system.cpu1.icache.demand_mshr_hits::cpu1.inst 60264 # number of demand (read+write) MSHR hits 1356system.cpu1.icache.demand_mshr_hits::total 60264 # number of demand (read+write) MSHR hits --- 161 unchanged lines hidden (view full) --- 1518system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1519system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1520system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1521system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1522system.iocache.replacements 0 # number of replacements 1523system.iocache.tagsinuse 0 # Cycle average of tags in use 1524system.iocache.total_refs 0 # Total number of references to valid blocks. 1525system.iocache.sampled_refs 0 # Sample count of references to valid blocks. |
| 1526system.iocache.avg_refs no_value # Average number of references to valid blocks. | 1526system.iocache.avg_refs nan # Average number of references to valid blocks. |
| 1527system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1528system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1529system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1530system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1531system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1527system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1528system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1529system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1530system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1531system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1532system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1533system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1532system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1533system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1534system.iocache.fast_writes 0 # number of fast writes performed 1535system.iocache.cache_copies 0 # number of cache copies performed 1536system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of ReadReq MSHR uncacheable cycles 1537system.iocache.ReadReq_mshr_uncacheable_latency::total 1308112364906 # number of ReadReq MSHR uncacheable cycles 1538system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of overall MSHR uncacheable cycles 1539system.iocache.overall_mshr_uncacheable_latency::total 1308112364906 # number of overall MSHR uncacheable cycles 1540system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1541system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1542system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1543system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1544system.cpu0.kern.inst.quiesce 36030 # number of quiesce instructions executed 1545system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1546system.cpu1.kern.inst.quiesce 61524 # number of quiesce instructions executed 1547 1548---------- End Simulation Statistics ---------- | 1534system.iocache.fast_writes 0 # number of fast writes performed 1535system.iocache.cache_copies 0 # number of cache copies performed 1536system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of ReadReq MSHR uncacheable cycles 1537system.iocache.ReadReq_mshr_uncacheable_latency::total 1308112364906 # number of ReadReq MSHR uncacheable cycles 1538system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of overall MSHR uncacheable cycles 1539system.iocache.overall_mshr_uncacheable_latency::total 1308112364906 # number of overall MSHR uncacheable cycles 1540system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1541system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1542system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1543system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1544system.cpu0.kern.inst.quiesce 36030 # number of quiesce instructions executed 1545system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1546system.cpu1.kern.inst.quiesce 61524 # number of quiesce instructions executed 1547 1548---------- End Simulation Statistics ---------- |