| stats.txt (11775:0eadb0b6e9de) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.826654 # Number of seconds simulated 4sim_ticks 2826653666000 # Number of ticks simulated 5final_tick 2826653666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.826673 # Number of seconds simulated 4sim_ticks 2826672558500 # Number of ticks simulated 5final_tick 2826672558500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 170078 # Simulator instruction rate (inst/s) 8host_op_rate 206349 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4004321035 # Simulator tick rate (ticks/s) 10host_mem_usage 626896 # Number of bytes of host memory used 11host_seconds 705.90 # Real time elapsed on the host 12sim_insts 120058397 # Number of instructions simulated 13sim_ops 145661611 # Number of ops (including micro ops) simulated | 7host_inst_rate 170041 # Simulator instruction rate (inst/s) 8host_op_rate 206302 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4002646805 # Simulator tick rate (ticks/s) 10host_mem_usage 627056 # Number of bytes of host memory used 11host_seconds 706.20 # Real time elapsed on the host 12sim_insts 120082757 # Number of instructions simulated 13sim_ops 145690782 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1325840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1300840 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8393920 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1308688 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1308456 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8387648 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory | 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::cpu1.inst 176672 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 432960 # Number of bytes read from this memory | 24system.physmem.bytes_read::cpu1.inst 193312 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 594324 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 432320 # Number of bytes read from this memory |
| 27system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 27system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 28system.physmem.bytes_read::total 12220460 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 1325840 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 176672 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 1502512 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 8774720 # Number of bytes written to this memory | 28system.physmem.bytes_read::total 12228268 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 1308688 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 193312 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 1502000 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 8790464 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 33system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 35system.physmem.bytes_written::total 8792284 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 22967 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 20846 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 131155 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory | 35system.physmem.bytes_written::total 8808028 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 22699 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 20965 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 131057 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory |
| 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory | 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::cpu1.inst 2828 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 6765 # Number of read requests responded to by this memory | 43system.physmem.num_reads::cpu1.inst 3088 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 9307 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 6755 # Number of read requests responded to by this memory |
| 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 47system.physmem.num_reads::total 193804 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 137105 # Number of write requests responded to by this memory | 47system.physmem.num_reads::total 193926 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 137351 # Number of write requests responded to by this memory |
| 49system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 49system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 51system.physmem.num_writes::total 141496 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 469049 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 460205 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 2969561 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.num_writes::total 141742 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 462978 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 462896 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 2967322 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::cpu1.inst 62502 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 207631 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 153171 # Total read bandwidth from this memory (bytes/s) | 59system.physmem.bw_read::cpu1.inst 68389 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 210256 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 152943 # Total read bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) | 62system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_read::total 4323296 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 469049 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 62502 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 531552 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 3104278 # Write bandwidth from this memory (bytes/s) | 63system.physmem.bw_read::total 4326029 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 462978 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 68389 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 531367 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 3109827 # Write bandwidth from this memory (bytes/s) |
| 68system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 68system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 70system.physmem.bw_write::total 3110492 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 3104278 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 469049 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 466405 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 2969561 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) | 70system.physmem.bw_write::total 3116041 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 3109827 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 462978 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 469096 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 2967322 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s) |
| 78system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) | 78system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) |
| 79system.physmem.bw_total::cpu1.inst 62502 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 207645 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 153171 # Total bandwidth to/from this memory (bytes/s) | 79system.physmem.bw_total::cpu1.inst 68389 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 210270 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 152943 # Total bandwidth to/from this memory (bytes/s) |
| 82system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) | 82system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) |
| 83system.physmem.bw_total::total 7433788 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 193805 # Number of read requests accepted 85system.physmem.writeReqs 141496 # Number of write requests accepted 86system.physmem.readBursts 193805 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 141496 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 12392576 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue 90system.physmem.bytesWritten 8805056 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 12220524 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 8792284 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue | 83system.physmem.bw_total::total 7442070 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 193927 # Number of read requests accepted 85system.physmem.writeReqs 141742 # Number of write requests accepted 86system.physmem.readBursts 193927 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 141742 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 12400768 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue 90system.physmem.bytesWritten 8820224 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 12228332 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 8808028 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue |
| 94system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 94system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 96system.physmem.perBankRdBursts::0 11925 # Per bank write bursts 97system.physmem.perBankRdBursts::1 11855 # Per bank write bursts 98system.physmem.perBankRdBursts::2 12297 # Per bank write bursts 99system.physmem.perBankRdBursts::3 12187 # Per bank write bursts 100system.physmem.perBankRdBursts::4 14909 # Per bank write bursts 101system.physmem.perBankRdBursts::5 12660 # Per bank write bursts 102system.physmem.perBankRdBursts::6 12587 # Per bank write bursts 103system.physmem.perBankRdBursts::7 12794 # Per bank write bursts 104system.physmem.perBankRdBursts::8 12033 # Per bank write bursts 105system.physmem.perBankRdBursts::9 12070 # Per bank write bursts 106system.physmem.perBankRdBursts::10 11247 # Per bank write bursts 107system.physmem.perBankRdBursts::11 10141 # Per bank write bursts 108system.physmem.perBankRdBursts::12 11323 # Per bank write bursts 109system.physmem.perBankRdBursts::13 11835 # Per bank write bursts 110system.physmem.perBankRdBursts::14 11954 # Per bank write bursts 111system.physmem.perBankRdBursts::15 11817 # Per bank write bursts 112system.physmem.perBankWrBursts::0 8684 # Per bank write bursts 113system.physmem.perBankWrBursts::1 8734 # Per bank write bursts 114system.physmem.perBankWrBursts::2 9001 # Per bank write bursts 115system.physmem.perBankWrBursts::3 8790 # Per bank write bursts 116system.physmem.perBankWrBursts::4 8747 # Per bank write bursts 117system.physmem.perBankWrBursts::5 9254 # Per bank write bursts 118system.physmem.perBankWrBursts::6 9144 # Per bank write bursts 119system.physmem.perBankWrBursts::7 9206 # Per bank write bursts 120system.physmem.perBankWrBursts::8 8582 # Per bank write bursts 121system.physmem.perBankWrBursts::9 8592 # Per bank write bursts 122system.physmem.perBankWrBursts::10 8144 # Per bank write bursts 123system.physmem.perBankWrBursts::11 7450 # Per bank write bursts 124system.physmem.perBankWrBursts::12 8375 # Per bank write bursts 125system.physmem.perBankWrBursts::13 8211 # Per bank write bursts 126system.physmem.perBankWrBursts::14 8456 # Per bank write bursts 127system.physmem.perBankWrBursts::15 8209 # Per bank write bursts | 96system.physmem.perBankRdBursts::0 11912 # Per bank write bursts 97system.physmem.perBankRdBursts::1 11892 # Per bank write bursts 98system.physmem.perBankRdBursts::2 12330 # Per bank write bursts 99system.physmem.perBankRdBursts::3 12174 # Per bank write bursts 100system.physmem.perBankRdBursts::4 14942 # Per bank write bursts 101system.physmem.perBankRdBursts::5 12676 # Per bank write bursts 102system.physmem.perBankRdBursts::6 12556 # Per bank write bursts 103system.physmem.perBankRdBursts::7 12785 # Per bank write bursts 104system.physmem.perBankRdBursts::8 12022 # Per bank write bursts 105system.physmem.perBankRdBursts::9 12081 # Per bank write bursts 106system.physmem.perBankRdBursts::10 11226 # Per bank write bursts 107system.physmem.perBankRdBursts::11 10162 # Per bank write bursts 108system.physmem.perBankRdBursts::12 11365 # Per bank write bursts 109system.physmem.perBankRdBursts::13 11848 # Per bank write bursts 110system.physmem.perBankRdBursts::14 11951 # Per bank write bursts 111system.physmem.perBankRdBursts::15 11840 # Per bank write bursts 112system.physmem.perBankWrBursts::0 8683 # Per bank write bursts 113system.physmem.perBankWrBursts::1 8758 # Per bank write bursts 114system.physmem.perBankWrBursts::2 9038 # Per bank write bursts 115system.physmem.perBankWrBursts::3 8776 # Per bank write bursts 116system.physmem.perBankWrBursts::4 8736 # Per bank write bursts 117system.physmem.perBankWrBursts::5 9287 # Per bank write bursts 118system.physmem.perBankWrBursts::6 9143 # Per bank write bursts 119system.physmem.perBankWrBursts::7 9209 # Per bank write bursts 120system.physmem.perBankWrBursts::8 8594 # Per bank write bursts 121system.physmem.perBankWrBursts::9 8600 # Per bank write bursts 122system.physmem.perBankWrBursts::10 8159 # Per bank write bursts 123system.physmem.perBankWrBursts::11 7478 # Per bank write bursts 124system.physmem.perBankWrBursts::12 8406 # Per bank write bursts 125system.physmem.perBankWrBursts::13 8230 # Per bank write bursts 126system.physmem.perBankWrBursts::14 8500 # Per bank write bursts 127system.physmem.perBankWrBursts::15 8219 # Per bank write bursts |
| 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 129system.physmem.numWrRetry 72 # Number of times write queue was full causing retry 130system.physmem.totGap 2826653384500 # Total gap between requests | 129system.physmem.numWrRetry 60 # Number of times write queue was full causing retry 130system.physmem.totGap 2826672288500 # Total gap between requests |
| 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 551 # Read request sizes (log2) 134system.physmem.readPktSize::3 28 # Read request sizes (log2) 135system.physmem.readPktSize::4 3091 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) | 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 551 # Read request sizes (log2) 134system.physmem.readPktSize::3 28 # Read request sizes (log2) 135system.physmem.readPktSize::4 3091 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 137system.physmem.readPktSize::6 190135 # Read request sizes (log2) | 137system.physmem.readPktSize::6 190257 # Read request sizes (log2) |
| 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 4391 # Write request sizes (log2) 141system.physmem.writePktSize::3 0 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) | 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 4391 # Write request sizes (log2) 141system.physmem.writePktSize::3 0 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 144system.physmem.writePktSize::6 137105 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 58100 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 70874 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 15772 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 12783 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 8291 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 7517 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 6372 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 5340 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 4622 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 1482 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 762 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 318 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 269 # What read queue length does an incoming req see | 144system.physmem.writePktSize::6 137351 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 58372 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 70356 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 15687 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 12836 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 8377 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 7582 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 6463 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 5422 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 4671 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 1517 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1143 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 311 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see |
| 159system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see | 159system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see |
| 161system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see | 161system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see |
| 165system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 165system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 192system.physmem.wrQLenPdf::15 2435 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 3327 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 3886 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 4434 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 5302 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 5614 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 6568 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 8221 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 8154 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 10030 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 8800 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 8694 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 9370 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 10301 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 8578 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 8277 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 1036 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 736 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 601 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 443 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 320 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 313 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 278 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 265 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 299 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 235 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 191 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 191 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 195 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 221 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 243 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 215 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 165 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 192 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 219 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 262 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 164 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 84669 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 250.358833 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 141.923887 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 307.724934 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 42961 50.74% 50.74% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 17699 20.90% 71.64% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 6074 7.17% 78.82% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 3410 4.03% 82.84% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 2753 3.25% 86.10% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 1498 1.77% 87.87% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 998 1.18% 89.04% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 977 1.15% 90.20% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 8299 9.80% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 84669 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 6797 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 28.488009 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 564.388330 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-2047 6795 99.97% 99.97% # Reads before turning the bus around for writes | 192system.physmem.wrQLenPdf::15 2460 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 3319 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 3946 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 4422 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 5293 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 5687 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 6555 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 7267 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 8245 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 8247 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 9579 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 10099 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 8863 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 8597 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 9328 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 10498 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 8586 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 8360 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 775 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 597 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 398 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 318 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 317 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 293 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 192 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 226 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 221 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 192 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 194 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 206 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 213 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 174 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 229 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 202 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 208 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 84506 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 251.118169 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 142.721377 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 307.168687 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 42580 50.39% 50.39% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 17667 20.91% 71.29% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 6229 7.37% 78.66% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 3460 4.09% 82.76% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 2829 3.35% 86.11% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 1565 1.85% 87.96% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 960 1.14% 89.09% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 994 1.18% 90.27% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 8222 9.73% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 84506 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 6824 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 28.393318 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 563.270042 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-2047 6822 99.97% 99.97% # Reads before turning the bus around for writes |
| 259system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes | 259system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::total 6797 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 6797 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.241136 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.514528 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 14.610339 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-23 6111 89.91% 89.91% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-31 128 1.88% 91.79% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::32-39 273 4.02% 95.81% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::40-47 31 0.46% 96.26% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::48-55 13 0.19% 96.45% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-63 14 0.21% 96.66% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-71 146 2.15% 98.81% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::72-79 13 0.19% 99.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::80-87 11 0.16% 99.16% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::96-103 7 0.10% 99.26% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::104-111 8 0.12% 99.38% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::112-119 5 0.07% 99.46% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::120-127 4 0.06% 99.51% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::128-135 8 0.12% 99.63% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::136-143 6 0.09% 99.72% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::144-151 2 0.03% 99.75% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::152-159 1 0.01% 99.76% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::160-167 3 0.04% 99.81% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::168-175 2 0.03% 99.84% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::176-183 5 0.07% 99.91% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::192-199 4 0.06% 99.97% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::200-207 1 0.01% 99.99% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::320-327 1 0.01% 100.00% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::total 6797 # Writes before turning the bus around for reads 290system.physmem.totQLat 9919718835 # Total ticks spent queuing 291system.physmem.totMemAccLat 13550356335 # Total ticks spent from burst creation until serviced by the DRAM 292system.physmem.totBusLat 968170000 # Total ticks spent in databus transfers 293system.physmem.avgQLat 51228.96 # Average queueing delay per DRAM burst | 261system.physmem.rdPerTurnAround::total 6824 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 6824 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.195780 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.530637 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 13.731147 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 5748 84.23% 84.23% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 362 5.30% 89.54% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 98 1.44% 90.97% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 53 0.78% 91.75% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 250 3.66% 95.41% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 24 0.35% 95.76% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 17 0.25% 96.01% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 13 0.19% 96.20% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 6 0.09% 96.29% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 8 0.12% 96.41% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 10 0.15% 96.56% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 144 2.11% 98.67% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 13 0.19% 98.86% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 7 0.10% 98.96% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 6 0.09% 99.05% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 7 0.10% 99.15% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 1 0.01% 99.21% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 4 0.06% 99.27% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::104-107 1 0.01% 99.28% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::108-111 7 0.10% 99.38% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 5 0.07% 99.46% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::116-119 2 0.03% 99.49% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::120-123 2 0.03% 99.52% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::124-127 5 0.07% 99.59% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::128-131 9 0.13% 99.72% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::132-135 1 0.01% 99.74% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::140-143 5 0.07% 99.81% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::156-159 2 0.03% 99.84% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::160-163 3 0.04% 99.88% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::164-167 1 0.01% 99.90% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::176-179 3 0.04% 99.97% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::184-187 1 0.01% 99.99% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::total 6824 # Writes before turning the bus around for reads 303system.physmem.totQLat 10004432906 # Total ticks spent queuing 304system.physmem.totMemAccLat 13637470406 # Total ticks spent from burst creation until serviced by the DRAM 305system.physmem.totBusLat 968810000 # Total ticks spent in databus transfers 306system.physmem.avgQLat 51632.32 # Average queueing delay per DRAM burst |
| 294system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst | 307system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst |
| 295system.physmem.avgMemAccLat 69978.86 # Average memory access latency per DRAM burst 296system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s | 308system.physmem.avgMemAccLat 70382.22 # Average memory access latency per DRAM burst 309system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s |
| 297system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s | 310system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s |
| 298system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s 299system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s | 311system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s 312system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s |
| 300system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 301system.physmem.busUtil 0.06 # Data bus utilization in percentage 302system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 303system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 313system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 314system.physmem.busUtil 0.06 # Data bus utilization in percentage 315system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 316system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 304system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing 305system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing 306system.physmem.readRowHits 161407 # Number of row buffer hits during reads 307system.physmem.writeRowHits 85137 # Number of row buffer hits during writes 308system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads 309system.physmem.writeRowHitRate 61.87 # Row buffer hit rate for writes 310system.physmem.avgGap 8430196.70 # Average gap between requests 311system.physmem.pageHitRate 74.43 # Row buffer hit rate, read and write combined 312system.physmem_0.actEnergy 316180620 # Energy for activate commands per rank (pJ) 313system.physmem_0.preEnergy 168053985 # Energy for precharge commands per rank (pJ) 314system.physmem_0.readEnergy 722667960 # Energy for read commands per rank (pJ) 315system.physmem_0.writeEnergy 373543200 # Energy for write commands per rank (pJ) 316system.physmem_0.refreshEnergy 4556326320.000001 # Energy for refresh commands per rank (pJ) 317system.physmem_0.actBackEnergy 4729873110 # Energy for active background per rank (pJ) 318system.physmem_0.preBackEnergy 240133440 # Energy for precharge background per rank (pJ) 319system.physmem_0.actPowerDownEnergy 9128983770 # Energy for active power-down per rank (pJ) 320system.physmem_0.prePowerDownEnergy 6579538080 # Energy for precharge power-down per rank (pJ) 321system.physmem_0.selfRefreshEnergy 667569876735 # Energy for self refresh per rank (pJ) 322system.physmem_0.totalEnergy 694387365510 # Total energy per rank (pJ) 323system.physmem_0.averagePower 245.657037 # Core power per rank (mW) 324system.physmem_0.totalIdleTime 2815586462334 # Total Idle time Per DRAM Rank 325system.physmem_0.memoryStateTime::IDLE 417040689 # Time in different power states 326system.physmem_0.memoryStateTime::REF 1935564000 # Time in different power states 327system.physmem_0.memoryStateTime::SREF 2778497008500 # Time in different power states 328system.physmem_0.memoryStateTime::PRE_PDN 17134268560 # Time in different power states 329system.physmem_0.memoryStateTime::ACT 8650044977 # Time in different power states 330system.physmem_0.memoryStateTime::ACT_PDN 20019739274 # Time in different power states 331system.physmem_1.actEnergy 288356040 # Energy for activate commands per rank (pJ) 332system.physmem_1.preEnergy 153264870 # Energy for precharge commands per rank (pJ) 333system.physmem_1.readEnergy 659878800 # Energy for read commands per rank (pJ) 334system.physmem_1.writeEnergy 344619180 # Energy for write commands per rank (pJ) 335system.physmem_1.refreshEnergy 4568619120.000001 # Energy for refresh commands per rank (pJ) 336system.physmem_1.actBackEnergy 4738351860 # Energy for active background per rank (pJ) 337system.physmem_1.preBackEnergy 236664480 # Energy for precharge background per rank (pJ) 338system.physmem_1.actPowerDownEnergy 8828064240 # Energy for active power-down per rank (pJ) 339system.physmem_1.prePowerDownEnergy 6766632480 # Energy for precharge power-down per rank (pJ) 340system.physmem_1.selfRefreshEnergy 667633644195 # Energy for self refresh per rank (pJ) 341system.physmem_1.totalEnergy 694220207745 # Total energy per rank (pJ) 342system.physmem_1.averagePower 245.597901 # Core power per rank (mW) 343system.physmem_1.totalIdleTime 2815641624954 # Total Idle time Per DRAM Rank 344system.physmem_1.memoryStateTime::IDLE 407791169 # Time in different power states 345system.physmem_1.memoryStateTime::REF 1940956000 # Time in different power states 346system.physmem_1.memoryStateTime::SREF 2778660280000 # Time in different power states 347system.physmem_1.memoryStateTime::PRE_PDN 17621547350 # Time in different power states 348system.physmem_1.memoryStateTime::ACT 8663293877 # Time in different power states 349system.physmem_1.memoryStateTime::ACT_PDN 19359797604 # Time in different power states 350system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 317system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 318system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing 319system.physmem.readRowHits 161584 # Number of row buffer hits during reads 320system.physmem.writeRowHits 85488 # Number of row buffer hits during writes 321system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads 322system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes 323system.physmem.avgGap 8421010.84 # Average gap between requests 324system.physmem.pageHitRate 74.51 # Row buffer hit rate, read and write combined 325system.physmem_0.actEnergy 316830360 # Energy for activate commands per rank (pJ) 326system.physmem_0.preEnergy 168399330 # Energy for precharge commands per rank (pJ) 327system.physmem_0.readEnergy 723046380 # Energy for read commands per rank (pJ) 328system.physmem_0.writeEnergy 373908600 # Energy for write commands per rank (pJ) 329system.physmem_0.refreshEnergy 4521291840.000001 # Energy for refresh commands per rank (pJ) 330system.physmem_0.actBackEnergy 4723358580 # Energy for active background per rank (pJ) 331system.physmem_0.preBackEnergy 248942400 # Energy for precharge background per rank (pJ) 332system.physmem_0.actPowerDownEnergy 9096613470 # Energy for active power-down per rank (pJ) 333system.physmem_0.prePowerDownEnergy 6505168320 # Energy for precharge power-down per rank (pJ) 334system.physmem_0.selfRefreshEnergy 667621594905 # Energy for self refresh per rank (pJ) 335system.physmem_0.totalEnergy 694301661855 # Total energy per rank (pJ) 336system.physmem_0.averagePower 245.625060 # Core power per rank (mW) 337system.physmem_0.totalIdleTime 2815660418258 # Total Idle time Per DRAM Rank 338system.physmem_0.memoryStateTime::IDLE 439528927 # Time in different power states 339system.physmem_0.memoryStateTime::REF 1920369500 # Time in different power states 340system.physmem_0.memoryStateTime::SREF 2778771385500 # Time in different power states 341system.physmem_0.memoryStateTime::PRE_PDN 16940567035 # Time in different power states 342system.physmem_0.memoryStateTime::ACT 8652241815 # Time in different power states 343system.physmem_0.memoryStateTime::ACT_PDN 19948465723 # Time in different power states 344system.physmem_1.actEnergy 286542480 # Energy for activate commands per rank (pJ) 345system.physmem_1.preEnergy 152300940 # Energy for precharge commands per rank (pJ) 346system.physmem_1.readEnergy 660414300 # Energy for read commands per rank (pJ) 347system.physmem_1.writeEnergy 345490920 # Energy for write commands per rank (pJ) 348system.physmem_1.refreshEnergy 4558170240.000001 # Energy for refresh commands per rank (pJ) 349system.physmem_1.actBackEnergy 4719582900 # Energy for active background per rank (pJ) 350system.physmem_1.preBackEnergy 238189440 # Energy for precharge background per rank (pJ) 351system.physmem_1.actPowerDownEnergy 8751236790 # Energy for active power-down per rank (pJ) 352system.physmem_1.prePowerDownEnergy 6789483360 # Energy for precharge power-down per rank (pJ) 353system.physmem_1.selfRefreshEnergy 667674392880 # Energy for self refresh per rank (pJ) 354system.physmem_1.totalEnergy 694177600920 # Total energy per rank (pJ) 355system.physmem_1.averagePower 245.581186 # Core power per rank (mW) 356system.physmem_1.totalIdleTime 2815698296531 # Total Idle time Per DRAM Rank 357system.physmem_1.memoryStateTime::IDLE 410333187 # Time in different power states 358system.physmem_1.memoryStateTime::REF 1936500000 # Time in different power states 359system.physmem_1.memoryStateTime::SREF 2778826050750 # Time in different power states 360system.physmem_1.memoryStateTime::PRE_PDN 17681028809 # Time in different power states 361system.physmem_1.memoryStateTime::ACT 8627428782 # Time in different power states 362system.physmem_1.memoryStateTime::ACT_PDN 19191216972 # Time in different power states 363system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 351system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 357system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 360system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 367system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 368system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) | 364system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 365system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 366system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 367system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 368system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 369system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 370system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 371system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 372system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 373system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 381system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) |
| 369system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 370system.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 371system.bridge.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 382system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 383system.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 384system.bridge.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 372system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 373system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 374system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 375system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 376system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 377system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 385system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 386system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 387system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 388system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 389system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 390system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 378system.cpu0.branchPred.lookups 53099847 # Number of BP lookups 379system.cpu0.branchPred.condPredicted 24413538 # Number of conditional branches predicted 380system.cpu0.branchPred.condIncorrect 933900 # Number of conditional branches incorrect 381system.cpu0.branchPred.BTBLookups 32114969 # Number of BTB lookups 382system.cpu0.branchPred.BTBHits 13973138 # Number of BTB hits | 391system.cpu0.branchPred.lookups 23882865 # Number of BP lookups 392system.cpu0.branchPred.condPredicted 15636955 # Number of conditional branches predicted 393system.cpu0.branchPred.condIncorrect 931558 # Number of conditional branches incorrect 394system.cpu0.branchPred.BTBLookups 14470894 # Number of BTB lookups 395system.cpu0.branchPred.BTBHits 9520533 # Number of BTB hits |
| 383system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 396system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 384system.cpu0.branchPred.BTBHitPct 43.509735 # BTB Hit Percentage 385system.cpu0.branchPred.usedRAS 15469071 # Number of times the RAS was used to get a target. 386system.cpu0.branchPred.RASInCorrect 33231 # Number of incorrect RAS predictions. 387system.cpu0.branchPred.indirectLookups 10119740 # Number of indirect predictor lookups. 388system.cpu0.branchPred.indirectHits 9963994 # Number of indirect target hits. 389system.cpu0.branchPred.indirectMisses 155746 # Number of indirect misses. 390system.cpu0.branchPredindirectMispredicted 49057 # Number of mispredicted indirect branches. | 397system.cpu0.branchPred.BTBHitPct 65.790911 # BTB Hit Percentage 398system.cpu0.branchPred.usedRAS 3844072 # Number of times the RAS was used to get a target. 399system.cpu0.branchPred.RASInCorrect 34146 # Number of incorrect RAS predictions. 400system.cpu0.branchPred.indirectLookups 1359371 # Number of indirect predictor lookups. 401system.cpu0.branchPred.indirectHits 1203202 # Number of indirect target hits. 402system.cpu0.branchPred.indirectMisses 156169 # Number of indirect misses. 403system.cpu0.branchPredindirectMispredicted 49075 # Number of mispredicted indirect branches. |
| 391system.cpu_clk_domain.clock 500 # Clock period in ticks | 404system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 392system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 405system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 414system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 416system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 417system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 418system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 419system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 420system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 421system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 406system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 427system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 428system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 429system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 430system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 431system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 432system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 433system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 434system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 422system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 423system.cpu0.dtb.walker.walks 65583 # Table walker walks requested 424system.cpu0.dtb.walker.walksShort 65583 # Table walker walks initiated with short descriptors 425system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25222 # Level at which table walker walks with short descriptors terminate 426system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18949 # Level at which table walker walks with short descriptors terminate 427system.cpu0.dtb.walker.walksSquashedBefore 21412 # Table walks squashed before starting 428system.cpu0.dtb.walker.walkWaitTime::samples 44171 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::mean 487.310679 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::stdev 3087.040611 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::0-8191 42986 97.32% 97.32% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::8192-16383 897 2.03% 99.35% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.63% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::24576-32767 93 0.21% 99.84% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::32768-40959 33 0.07% 99.92% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::57344-65535 15 0.03% 100.00% # Table walker wait (enqueue to first request) latency | 435system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 436system.cpu0.dtb.walker.walks 66298 # Table walker walks requested 437system.cpu0.dtb.walker.walksShort 66298 # Table walker walks initiated with short descriptors 438system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25087 # Level at which table walker walks with short descriptors terminate 439system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19168 # Level at which table walker walks with short descriptors terminate 440system.cpu0.dtb.walker.walksSquashedBefore 22043 # Table walks squashed before starting 441system.cpu0.dtb.walker.walkWaitTime::samples 44255 # Table walker wait (enqueue to first request) latency 442system.cpu0.dtb.walker.walkWaitTime::mean 493.831206 # Table walker wait (enqueue to first request) latency 443system.cpu0.dtb.walker.walkWaitTime::stdev 3088.958464 # Table walker wait (enqueue to first request) latency 444system.cpu0.dtb.walker.walkWaitTime::0-8191 43053 97.28% 97.28% # Table walker wait (enqueue to first request) latency 445system.cpu0.dtb.walker.walkWaitTime::8192-16383 899 2.03% 99.32% # Table walker wait (enqueue to first request) latency 446system.cpu0.dtb.walker.walkWaitTime::16384-24575 141 0.32% 99.63% # Table walker wait (enqueue to first request) latency 447system.cpu0.dtb.walker.walkWaitTime::24576-32767 95 0.21% 99.85% # Table walker wait (enqueue to first request) latency 448system.cpu0.dtb.walker.walkWaitTime::32768-40959 32 0.07% 99.92% # Table walker wait (enqueue to first request) latency 449system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency 450system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency 451system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency |
| 438system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 452system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 453system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 440system.cpu0.dtb.walker.walkWaitTime::total 44171 # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkCompletionTime::samples 16005 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::mean 11349.047173 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::gmean 9735.111358 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::stdev 7638.174811 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::0-16383 14581 91.10% 91.10% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1176 7.35% 98.45% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::32768-49151 210 1.31% 99.76% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.86% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.88% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::114688-131071 7 0.04% 99.92% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::131072-147455 12 0.07% 99.99% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::total 16005 # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walksPending::samples 82168586356 # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::mean 0.591771 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::stdev 0.502145 # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::0-1 82111702356 99.93% 99.93% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::2-3 39388000 0.05% 99.98% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::4-5 7963500 0.01% 99.99% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::6-7 4902500 0.01% 99.99% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::8-9 2427000 0.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::10-11 777000 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::12-13 938000 0.00% 100.00% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::14-15 463500 0.00% 100.00% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::16-17 24500 0.00% 100.00% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::total 82168586356 # Table walker pending requests distribution 468system.cpu0.dtb.walker.walkPageSizes::4K 5127 78.72% 78.72% # Table walker page sizes translated 469system.cpu0.dtb.walker.walkPageSizes::1M 1386 21.28% 100.00% # Table walker page sizes translated 470system.cpu0.dtb.walker.walkPageSizes::total 6513 # Table walker page sizes translated 471system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65583 # Table walker requests started/completed, data/inst | 454system.cpu0.dtb.walker.walkWaitTime::total 44255 # Table walker wait (enqueue to first request) latency 455system.cpu0.dtb.walker.walkCompletionTime::samples 16149 # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::mean 11407.424608 # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::gmean 9685.730755 # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::stdev 9901.207568 # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walkCompletionTime::0-16383 14668 90.83% 90.83% # Table walker service (enqueue to completion) latency 460system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1230 7.62% 98.45% # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walkCompletionTime::32768-49151 211 1.31% 99.75% # Table walker service (enqueue to completion) latency 462system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.85% # Table walker service (enqueue to completion) latency 463system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.87% # Table walker service (enqueue to completion) latency 464system.cpu0.dtb.walker.walkCompletionTime::114688-131071 4 0.02% 99.89% # Table walker service (enqueue to completion) latency 465system.cpu0.dtb.walker.walkCompletionTime::229376-245759 17 0.11% 100.00% # Table walker service (enqueue to completion) latency 466system.cpu0.dtb.walker.walkCompletionTime::total 16149 # Table walker service (enqueue to completion) latency 467system.cpu0.dtb.walker.walksPending::samples 86482404152 # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::mean 0.594104 # Table walker pending requests distribution 469system.cpu0.dtb.walker.walksPending::stdev 0.503301 # Table walker pending requests distribution 470system.cpu0.dtb.walker.walksPending::0-1 86424292152 99.93% 99.93% # Table walker pending requests distribution 471system.cpu0.dtb.walker.walksPending::2-3 40499500 0.05% 99.98% # Table walker pending requests distribution 472system.cpu0.dtb.walker.walksPending::4-5 7958000 0.01% 99.99% # Table walker pending requests distribution 473system.cpu0.dtb.walker.walksPending::6-7 4655000 0.01% 99.99% # Table walker pending requests distribution 474system.cpu0.dtb.walker.walksPending::8-9 1502500 0.00% 100.00% # Table walker pending requests distribution 475system.cpu0.dtb.walker.walksPending::10-11 969000 0.00% 100.00% # Table walker pending requests distribution 476system.cpu0.dtb.walker.walksPending::12-13 1099000 0.00% 100.00% # Table walker pending requests distribution 477system.cpu0.dtb.walker.walksPending::14-15 1428000 0.00% 100.00% # Table walker pending requests distribution 478system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution 479system.cpu0.dtb.walker.walksPending::total 86482404152 # Table walker pending requests distribution 480system.cpu0.dtb.walker.walkPageSizes::4K 5106 78.70% 78.70% # Table walker page sizes translated 481system.cpu0.dtb.walker.walkPageSizes::1M 1382 21.30% 100.00% # Table walker page sizes translated 482system.cpu0.dtb.walker.walkPageSizes::total 6488 # Table walker page sizes translated 483system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66298 # Table walker requests started/completed, data/inst |
| 472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 484system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 473system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65583 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6513 # Table walker requests started/completed, data/inst | 485system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66298 # Table walker requests started/completed, data/inst 486system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6488 # Table walker requests started/completed, data/inst |
| 475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 487system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 476system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6513 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin::total 72096 # Table walker requests started/completed, data/inst | 488system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6488 # Table walker requests started/completed, data/inst 489system.cpu0.dtb.walker.walkRequestOrigin::total 72786 # Table walker requests started/completed, data/inst |
| 478system.cpu0.dtb.inst_hits 0 # ITB inst hits 479system.cpu0.dtb.inst_misses 0 # ITB inst misses | 490system.cpu0.dtb.inst_hits 0 # ITB inst hits 491system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 480system.cpu0.dtb.read_hits 23662283 # DTB read hits 481system.cpu0.dtb.read_misses 55655 # DTB read misses 482system.cpu0.dtb.write_hits 17589226 # DTB write hits 483system.cpu0.dtb.write_misses 9928 # DTB write misses | 492system.cpu0.dtb.read_hits 17693188 # DTB read hits 493system.cpu0.dtb.read_misses 55688 # DTB read misses 494system.cpu0.dtb.write_hits 14580631 # DTB write hits 495system.cpu0.dtb.write_misses 10610 # DTB write misses |
| 484system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 485system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 496system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 497system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 498system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 499system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 488system.cpu0.dtb.flush_entries 3427 # Number of entries that have been flushed from TLB 489system.cpu0.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions 490system.cpu0.dtb.prefetch_faults 2234 # Number of TLB faults due to prefetch | 500system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB 501system.cpu0.dtb.align_faults 159 # Number of TLB faults due to alignment restrictions 502system.cpu0.dtb.prefetch_faults 2213 # Number of TLB faults due to prefetch |
| 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 503system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 492system.cpu0.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 23717938 # DTB read accesses 494system.cpu0.dtb.write_accesses 17599154 # DTB write accesses | 504system.cpu0.dtb.perms_faults 845 # Number of TLB faults due to permissions restrictions 505system.cpu0.dtb.read_accesses 17748876 # DTB read accesses 506system.cpu0.dtb.write_accesses 14591241 # DTB write accesses |
| 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 507system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 496system.cpu0.dtb.hits 41251509 # DTB hits 497system.cpu0.dtb.misses 65583 # DTB misses 498system.cpu0.dtb.accesses 41317092 # DTB accesses 499system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 508system.cpu0.dtb.hits 32273819 # DTB hits 509system.cpu0.dtb.misses 66298 # DTB misses 510system.cpu0.dtb.accesses 32340117 # DTB accesses 511system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 500system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 521system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 524system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 525system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 526system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 527system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 528system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 512system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 513system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 514system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 515system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 516system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 517system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 518system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 519system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 533system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 536system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 537system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 538system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 539system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 540system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 529system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 530system.cpu0.itb.walker.walks 10907 # Table walker walks requested 531system.cpu0.itb.walker.walksShort 10907 # Table walker walks initiated with short descriptors 532system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3899 # Level at which table walker walks with short descriptors terminate 533system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5942 # Level at which table walker walks with short descriptors terminate 534system.cpu0.itb.walker.walksSquashedBefore 1066 # Table walks squashed before starting 535system.cpu0.itb.walker.walkWaitTime::samples 9841 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::mean 431.460217 # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::stdev 2241.549622 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::0-4095 9464 96.17% 96.17% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::4096-8191 172 1.75% 97.92% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::12288-16383 49 0.50% 99.66% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::16384-20479 6 0.06% 99.73% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.19% 99.92% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 549system.cpu0.itb.walker.walkWaitTime::total 9841 # Table walker wait (enqueue to first request) latency 550system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::mean 12380.384088 # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::gmean 11386.423562 # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::stdev 5549.123195 # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::0-8191 601 16.49% 16.49% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::8192-16383 2727 74.81% 91.30% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::16384-24575 175 4.80% 96.10% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::24576-32767 87 2.39% 98.49% # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.84% # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.92% # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.95% # Table walker service (enqueue to completion) latency 561system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.03% 99.97% # Table walker service (enqueue to completion) latency | 541system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 542system.cpu0.itb.walker.walks 11677 # Table walker walks requested 543system.cpu0.itb.walker.walksShort 11677 # Table walker walks initiated with short descriptors 544system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3850 # Level at which table walker walks with short descriptors terminate 545system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6772 # Level at which table walker walks with short descriptors terminate 546system.cpu0.itb.walker.walksSquashedBefore 1055 # Table walks squashed before starting 547system.cpu0.itb.walker.walkWaitTime::samples 10622 # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkWaitTime::mean 1021.559028 # Table walker wait (enqueue to first request) latency 549system.cpu0.itb.walker.walkWaitTime::stdev 3971.298769 # Table walker wait (enqueue to first request) latency 550system.cpu0.itb.walker.walkWaitTime::0-4095 9829 92.53% 92.53% # Table walker wait (enqueue to first request) latency 551system.cpu0.itb.walker.walkWaitTime::4096-8191 232 2.18% 94.72% # Table walker wait (enqueue to first request) latency 552system.cpu0.itb.walker.walkWaitTime::8192-12287 234 2.20% 96.92% # Table walker wait (enqueue to first request) latency 553system.cpu0.itb.walker.walkWaitTime::12288-16383 118 1.11% 98.03% # Table walker wait (enqueue to first request) latency 554system.cpu0.itb.walker.walkWaitTime::16384-20479 84 0.79% 98.82% # Table walker wait (enqueue to first request) latency 555system.cpu0.itb.walker.walkWaitTime::20480-24575 68 0.64% 99.46% # Table walker wait (enqueue to first request) latency 556system.cpu0.itb.walker.walkWaitTime::24576-28671 21 0.20% 99.66% # Table walker wait (enqueue to first request) latency 557system.cpu0.itb.walker.walkWaitTime::28672-32767 17 0.16% 99.82% # Table walker wait (enqueue to first request) latency 558system.cpu0.itb.walker.walkWaitTime::32768-36863 11 0.10% 99.92% # Table walker wait (enqueue to first request) latency 559system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency 560system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency 561system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 562system.cpu0.itb.walker.walkWaitTime::49152-53247 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency 563system.cpu0.itb.walker.walkWaitTime::total 10622 # Table walker wait (enqueue to first request) latency 564system.cpu0.itb.walker.walkCompletionTime::samples 3671 # Table walker service (enqueue to completion) latency 565system.cpu0.itb.walker.walkCompletionTime::mean 12324.162354 # Table walker service (enqueue to completion) latency 566system.cpu0.itb.walker.walkCompletionTime::gmean 11375.149198 # Table walker service (enqueue to completion) latency 567system.cpu0.itb.walker.walkCompletionTime::stdev 5369.602272 # Table walker service (enqueue to completion) latency 568system.cpu0.itb.walker.walkCompletionTime::0-8191 593 16.15% 16.15% # Table walker service (enqueue to completion) latency 569system.cpu0.itb.walker.walkCompletionTime::8192-16383 2793 76.08% 92.24% # Table walker service (enqueue to completion) latency 570system.cpu0.itb.walker.walkCompletionTime::16384-24575 150 4.09% 96.32% # Table walker service (enqueue to completion) latency 571system.cpu0.itb.walker.walkCompletionTime::24576-32767 91 2.48% 98.80% # Table walker service (enqueue to completion) latency 572system.cpu0.itb.walker.walkCompletionTime::32768-40959 38 1.04% 99.84% # Table walker service (enqueue to completion) latency 573system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.86% # Table walker service (enqueue to completion) latency 574system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.95% # Table walker service (enqueue to completion) latency 575system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency |
| 562system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency | 576system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency |
| 563system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency 564system.cpu0.itb.walker.walksPending::samples 22038229712 # Table walker pending requests distribution 565system.cpu0.itb.walker.walksPending::mean 0.837207 # Table walker pending requests distribution 566system.cpu0.itb.walker.walksPending::stdev 0.369334 # Table walker pending requests distribution 567system.cpu0.itb.walker.walksPending::0 3588883500 16.28% 16.28% # Table walker pending requests distribution 568system.cpu0.itb.walker.walksPending::1 18448211212 83.71% 99.99% # Table walker pending requests distribution 569system.cpu0.itb.walker.walksPending::2 1065000 0.00% 100.00% # Table walker pending requests distribution 570system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution 571system.cpu0.itb.walker.walksPending::total 22038229712 # Table walker pending requests distribution 572system.cpu0.itb.walker.walkPageSizes::4K 2246 87.09% 87.09% # Table walker page sizes translated 573system.cpu0.itb.walker.walkPageSizes::1M 333 12.91% 100.00% # Table walker page sizes translated 574system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated | 577system.cpu0.itb.walker.walkCompletionTime::total 3671 # Table walker service (enqueue to completion) latency 578system.cpu0.itb.walker.walksPending::samples 22057105212 # Table walker pending requests distribution 579system.cpu0.itb.walker.walksPending::mean 0.847252 # Table walker pending requests distribution 580system.cpu0.itb.walker.walksPending::stdev 0.360404 # Table walker pending requests distribution 581system.cpu0.itb.walker.walksPending::0 3373925500 15.30% 15.30% # Table walker pending requests distribution 582system.cpu0.itb.walker.walksPending::1 18678889712 84.68% 99.98% # Table walker pending requests distribution 583system.cpu0.itb.walker.walksPending::2 3873000 0.02% 100.00% # Table walker pending requests distribution 584system.cpu0.itb.walker.walksPending::3 379500 0.00% 100.00% # Table walker pending requests distribution 585system.cpu0.itb.walker.walksPending::4 37500 0.00% 100.00% # Table walker pending requests distribution 586system.cpu0.itb.walker.walksPending::total 22057105212 # Table walker pending requests distribution 587system.cpu0.itb.walker.walkPageSizes::4K 2281 87.19% 87.19% # Table walker page sizes translated 588system.cpu0.itb.walker.walkPageSizes::1M 335 12.81% 100.00% # Table walker page sizes translated 589system.cpu0.itb.walker.walkPageSizes::total 2616 # Table walker page sizes translated |
| 575system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 590system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 576system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10907 # Table walker requests started/completed, data/inst 577system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10907 # Table walker requests started/completed, data/inst | 591system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11677 # Table walker requests started/completed, data/inst 592system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11677 # Table walker requests started/completed, data/inst |
| 578system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 593system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 579system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst 580system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst 581system.cpu0.itb.walker.walkRequestOrigin::total 13486 # Table walker requests started/completed, data/inst 582system.cpu0.itb.inst_hits 72758108 # ITB inst hits 583system.cpu0.itb.inst_misses 10907 # ITB inst misses | 594system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2616 # Table walker requests started/completed, data/inst 595system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2616 # Table walker requests started/completed, data/inst 596system.cpu0.itb.walker.walkRequestOrigin::total 14293 # Table walker requests started/completed, data/inst 597system.cpu0.itb.inst_hits 37442886 # ITB inst hits 598system.cpu0.itb.inst_misses 11677 # ITB inst misses |
| 584system.cpu0.itb.read_hits 0 # DTB read hits 585system.cpu0.itb.read_misses 0 # DTB read misses 586system.cpu0.itb.write_hits 0 # DTB write hits 587system.cpu0.itb.write_misses 0 # DTB write misses 588system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 589system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 590system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 591system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 599system.cpu0.itb.read_hits 0 # DTB read hits 600system.cpu0.itb.read_misses 0 # DTB read misses 601system.cpu0.itb.write_hits 0 # DTB write hits 602system.cpu0.itb.write_misses 0 # DTB write misses 603system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 604system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 605system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 606system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 592system.cpu0.itb.flush_entries 2282 # Number of entries that have been flushed from TLB | 607system.cpu0.itb.flush_entries 2325 # Number of entries that have been flushed from TLB |
| 593system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 594system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 595system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 608system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 609system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 610system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 596system.cpu0.itb.perms_faults 1937 # Number of TLB faults due to permissions restrictions | 611system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions |
| 597system.cpu0.itb.read_accesses 0 # DTB read accesses 598system.cpu0.itb.write_accesses 0 # DTB write accesses | 612system.cpu0.itb.read_accesses 0 # DTB read accesses 613system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 599system.cpu0.itb.inst_accesses 72769015 # ITB inst accesses 600system.cpu0.itb.hits 72758108 # DTB hits 601system.cpu0.itb.misses 10907 # DTB misses 602system.cpu0.itb.accesses 72769015 # DTB accesses | 614system.cpu0.itb.inst_accesses 37454563 # ITB inst accesses 615system.cpu0.itb.hits 37442886 # DTB hits 616system.cpu0.itb.misses 11677 # DTB misses 617system.cpu0.itb.accesses 37454563 # DTB accesses |
| 603system.cpu0.numPwrStateTransitions 3670 # Number of power state transitions 604system.cpu0.pwrStateClkGateDist::samples 1835 # Distribution of time spent in the clock gated state | 618system.cpu0.numPwrStateTransitions 3670 # Number of power state transitions 619system.cpu0.pwrStateClkGateDist::samples 1835 # Distribution of time spent in the clock gated state |
| 605system.cpu0.pwrStateClkGateDist::mean 1484523232.318801 # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::stdev 23903491534.812244 # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::underflows 1057 57.60% 57.60% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.13% 99.73% # Distribution of time spent in the clock gated state | 620system.cpu0.pwrStateClkGateDist::mean 1504014886.326976 # Distribution of time spent in the clock gated state 621system.cpu0.pwrStateClkGateDist::stdev 24031487578.448807 # Distribution of time spent in the clock gated state 622system.cpu0.pwrStateClkGateDist::underflows 1058 57.66% 57.66% # Distribution of time spent in the clock gated state 623system.cpu0.pwrStateClkGateDist::1000-5e+10 770 41.96% 99.62% # Distribution of time spent in the clock gated state 624system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state |
| 609system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateClkGateDist::max_value 499970835992 # Distribution of time spent in the clock gated state 613system.cpu0.pwrStateClkGateDist::total 1835 # Distribution of time spent in the clock gated state | 625system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 626system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 627system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 628system.cpu0.pwrStateClkGateDist::max_value 499970835992 # Distribution of time spent in the clock gated state 629system.cpu0.pwrStateClkGateDist::total 1835 # Distribution of time spent in the clock gated state |
| 614system.cpu0.pwrStateResidencyTicks::ON 102553534695 # Cumulative time (in ticks) in various power states 615system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724100131305 # Cumulative time (in ticks) in various power states 616system.cpu0.numCycles 205108250 # number of cpu cycles simulated | 630system.cpu0.pwrStateResidencyTicks::ON 66805242090 # Cumulative time (in ticks) in various power states 631system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759867316410 # Cumulative time (in ticks) in various power states 632system.cpu0.numCycles 133611951 # number of cpu cycles simulated |
| 617system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 618system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 633system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 634system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 619system.cpu0.fetch.icacheStallCycles 20843459 # Number of cycles fetch is stalled on an Icache miss 620system.cpu0.fetch.Insts 195936196 # Number of instructions fetch has processed 621system.cpu0.fetch.Branches 53099847 # Number of branches that fetch encountered 622system.cpu0.fetch.predictedBranches 39406203 # Number of branches that fetch has predicted taken 623system.cpu0.fetch.Cycles 175823444 # Number of cycles fetch has run and was not squashing or blocked 624system.cpu0.fetch.SquashCycles 5691288 # Number of cycles fetch has spent squashing 625system.cpu0.fetch.TlbCycles 148299 # Number of cycles fetch has spent waiting for tlb 626system.cpu0.fetch.MiscStallCycles 58157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 627system.cpu0.fetch.PendingTrapStallCycles 416860 # Number of stall cycles due to pending traps 628system.cpu0.fetch.PendingQuiesceStallCycles 413792 # Number of stall cycles due to pending quiesce instructions 629system.cpu0.fetch.IcacheWaitRetryStallCycles 98564 # Number of stall cycles due to full MSHR 630system.cpu0.fetch.CacheLines 72757810 # Number of cache lines fetched 631system.cpu0.fetch.IcacheSquashes 257476 # Number of outstanding Icache misses that were squashed 632system.cpu0.fetch.ItlbSquashes 5315 # Number of outstanding ITLB misses that were squashed 633system.cpu0.fetch.rateDist::samples 200648219 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::mean 1.193498 # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::stdev 1.306871 # Number of instructions fetched each cycle (Total) | 635system.cpu0.fetch.icacheStallCycles 19303849 # Number of cycles fetch is stalled on an Icache miss 636system.cpu0.fetch.Insts 111829084 # Number of instructions fetch has processed 637system.cpu0.fetch.Branches 23882865 # Number of branches that fetch encountered 638system.cpu0.fetch.predictedBranches 14567807 # Number of branches that fetch has predicted taken 639system.cpu0.fetch.Cycles 107369786 # Number of cycles fetch has run and was not squashing or blocked 640system.cpu0.fetch.SquashCycles 2747392 # Number of cycles fetch has spent squashing 641system.cpu0.fetch.TlbCycles 153767 # Number of cycles fetch has spent waiting for tlb 642system.cpu0.fetch.MiscStallCycles 58387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 643system.cpu0.fetch.PendingTrapStallCycles 435607 # Number of stall cycles due to pending traps 644system.cpu0.fetch.PendingQuiesceStallCycles 423633 # Number of stall cycles due to pending quiesce instructions 645system.cpu0.fetch.IcacheWaitRetryStallCycles 97811 # Number of stall cycles due to full MSHR 646system.cpu0.fetch.CacheLines 37442098 # Number of cache lines fetched 647system.cpu0.fetch.IcacheSquashes 257331 # Number of outstanding Icache misses that were squashed 648system.cpu0.fetch.ItlbSquashes 6030 # Number of outstanding ITLB misses that were squashed 649system.cpu0.fetch.rateDist::samples 129216536 # Number of instructions fetched each cycle (Total) 650system.cpu0.fetch.rateDist::mean 1.043099 # Number of instructions fetched each cycle (Total) 651system.cpu0.fetch.rateDist::stdev 1.255701 # Number of instructions fetched each cycle (Total) |
| 636system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 652system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 637system.cpu0.fetch.rateDist::0 95712766 47.70% 47.70% # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::1 30373277 15.14% 62.84% # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::2 14586568 7.27% 70.11% # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.rateDist::3 59975608 29.89% 100.00% # Number of instructions fetched each cycle (Total) | 653system.cpu0.fetch.rateDist::0 67189169 52.00% 52.00% # Number of instructions fetched each cycle (Total) 654system.cpu0.fetch.rateDist::1 21288743 16.48% 68.47% # Number of instructions fetched each cycle (Total) 655system.cpu0.fetch.rateDist::2 8719000 6.75% 75.22% # Number of instructions fetched each cycle (Total) 656system.cpu0.fetch.rateDist::3 32019624 24.78% 100.00% # Number of instructions fetched each cycle (Total) |
| 641system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 642system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 643system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 657system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 658system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 659system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 644system.cpu0.fetch.rateDist::total 200648219 # Number of instructions fetched each cycle (Total) 645system.cpu0.fetch.branchRate 0.258887 # Number of branch fetches per cycle 646system.cpu0.fetch.rate 0.955282 # Number of inst fetches per cycle 647system.cpu0.decode.IdleCycles 25818393 # Number of cycles decode is idle 648system.cpu0.decode.BlockedCycles 108480918 # Number of cycles decode is blocked 649system.cpu0.decode.RunCycles 58863420 # Number of cycles decode is running 650system.cpu0.decode.UnblockCycles 4969304 # Number of cycles decode is unblocking 651system.cpu0.decode.SquashCycles 2516184 # Number of cycles decode is squashing 652system.cpu0.decode.BranchResolved 3061987 # Number of times decode resolved a branch 653system.cpu0.decode.BranchMispred 333558 # Number of times decode detected a branch misprediction 654system.cpu0.decode.DecodedInsts 154376244 # Number of instructions handled by decode 655system.cpu0.decode.SquashedInsts 3806825 # Number of squashed instructions handled by decode 656system.cpu0.rename.SquashCycles 2516184 # Number of cycles rename is squashing 657system.cpu0.rename.IdleCycles 34429607 # Number of cycles rename is idle 658system.cpu0.rename.BlockCycles 12873889 # Number of cycles rename is blocking 659system.cpu0.rename.serializeStallCycles 83899455 # count of cycles rename stalled for serializing inst 660system.cpu0.rename.RunCycles 55085453 # Number of cycles rename is running 661system.cpu0.rename.UnblockCycles 11843631 # Number of cycles rename is unblocking 662system.cpu0.rename.RenamedInsts 137696782 # Number of instructions processed by rename 663system.cpu0.rename.SquashedInsts 1037438 # Number of squashed instructions processed by rename 664system.cpu0.rename.ROBFullEvents 1493634 # Number of times rename has blocked due to ROB full 665system.cpu0.rename.IQFullEvents 164344 # Number of times rename has blocked due to IQ full 666system.cpu0.rename.LQFullEvents 57817 # Number of times rename has blocked due to LQ full 667system.cpu0.rename.SQFullEvents 7635337 # Number of times rename has blocked due to SQ full 668system.cpu0.rename.RenamedOperands 141807029 # Number of destination operands rename has renamed 669system.cpu0.rename.RenameLookups 635200062 # Number of register rename lookups that rename has made 670system.cpu0.rename.int_rename_lookups 152788581 # Number of integer rename lookups 671system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups 672system.cpu0.rename.CommittedMaps 130609661 # Number of HB maps that are committed 673system.cpu0.rename.UndoneMaps 11197357 # Number of HB maps that are undone due to squashing 674system.cpu0.rename.serializingInsts 2697375 # count of serializing insts renamed 675system.cpu0.rename.tempSerializingInsts 2554361 # count of temporary serializing insts renamed 676system.cpu0.rename.skidInsts 22576827 # count of insts added to the skid buffer 677system.cpu0.memDep0.insertedLoads 24592847 # Number of loads inserted to the mem dependence unit. 678system.cpu0.memDep0.insertedStores 19077592 # Number of stores inserted to the mem dependence unit. 679system.cpu0.memDep0.conflictingLoads 1691886 # Number of conflicting loads. 680system.cpu0.memDep0.conflictingStores 2320615 # Number of conflicting stores. 681system.cpu0.iq.iqInstsAdded 134759616 # Number of instructions added to the IQ (excludes non-spec) 682system.cpu0.iq.iqNonSpecInstsAdded 1714081 # Number of non-speculative instructions added to the IQ 683system.cpu0.iq.iqInstsIssued 132897861 # Number of instructions issued 684system.cpu0.iq.iqSquashedInstsIssued 450666 # Number of squashed instructions issued 685system.cpu0.iq.iqSquashedInstsExamined 10595447 # Number of squashed instructions iterated over during squash; mainly for profiling 686system.cpu0.iq.iqSquashedOperandsExamined 21697472 # Number of squashed operands that are examined and possibly removed from graph 687system.cpu0.iq.iqSquashedNonSpecRemoved 119702 # Number of squashed non-spec instructions that were removed 688system.cpu0.iq.issued_per_cycle::samples 200648219 # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::mean 0.662343 # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::stdev 0.961216 # Number of insts issued each cycle | 660system.cpu0.fetch.rateDist::total 129216536 # Number of instructions fetched each cycle (Total) 661system.cpu0.fetch.branchRate 0.178748 # Number of branch fetches per cycle 662system.cpu0.fetch.rate 0.836969 # Number of inst fetches per cycle 663system.cpu0.decode.IdleCycles 19892285 # Number of cycles decode is idle 664system.cpu0.decode.BlockedCycles 62318410 # Number of cycles decode is blocked 665system.cpu0.decode.RunCycles 41002144 # Number of cycles decode is running 666system.cpu0.decode.UnblockCycles 4961574 # Number of cycles decode is unblocking 667system.cpu0.decode.SquashCycles 1042123 # Number of cycles decode is squashing 668system.cpu0.decode.BranchResolved 8668351 # Number of times decode resolved a branch 669system.cpu0.decode.BranchMispred 335752 # Number of times decode detected a branch misprediction 670system.cpu0.decode.DecodedInsts 109935605 # Number of instructions handled by decode 671system.cpu0.decode.SquashedInsts 3778741 # Number of squashed instructions handled by decode 672system.cpu0.rename.SquashCycles 1042123 # Number of cycles rename is squashing 673system.cpu0.rename.IdleCycles 25542587 # Number of cycles rename is idle 674system.cpu0.rename.BlockCycles 12841185 # Number of cycles rename is blocking 675system.cpu0.rename.serializeStallCycles 37729185 # count of cycles rename stalled for serializing inst 676system.cpu0.rename.RunCycles 40176897 # Number of cycles rename is running 677system.cpu0.rename.UnblockCycles 11884559 # Number of cycles rename is unblocking 678system.cpu0.rename.RenamedInsts 104971930 # Number of instructions processed by rename 679system.cpu0.rename.SquashedInsts 1005936 # Number of squashed instructions processed by rename 680system.cpu0.rename.ROBFullEvents 1490559 # Number of times rename has blocked due to ROB full 681system.cpu0.rename.IQFullEvents 163297 # Number of times rename has blocked due to IQ full 682system.cpu0.rename.LQFullEvents 57296 # Number of times rename has blocked due to LQ full 683system.cpu0.rename.SQFullEvents 7681326 # Number of times rename has blocked due to SQ full 684system.cpu0.rename.RenamedOperands 109147487 # Number of destination operands rename has renamed 685system.cpu0.rename.RenameLookups 479167735 # Number of register rename lookups that rename has made 686system.cpu0.rename.int_rename_lookups 120008007 # Number of integer rename lookups 687system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups 688system.cpu0.rename.CommittedMaps 98091135 # Number of HB maps that are committed 689system.cpu0.rename.UndoneMaps 11056341 # Number of HB maps that are undone due to squashing 690system.cpu0.rename.serializingInsts 1226764 # count of serializing insts renamed 691system.cpu0.rename.tempSerializingInsts 1083940 # count of temporary serializing insts renamed 692system.cpu0.rename.skidInsts 12369905 # count of insts added to the skid buffer 693system.cpu0.memDep0.insertedLoads 18622381 # Number of loads inserted to the mem dependence unit. 694system.cpu0.memDep0.insertedStores 16045587 # Number of stores inserted to the mem dependence unit. 695system.cpu0.memDep0.conflictingLoads 1690063 # Number of conflicting loads. 696system.cpu0.memDep0.conflictingStores 2196173 # Number of conflicting stores. 697system.cpu0.iq.iqInstsAdded 102089116 # Number of instructions added to the IQ (excludes non-spec) 698system.cpu0.iq.iqNonSpecInstsAdded 1690972 # Number of non-speculative instructions added to the IQ 699system.cpu0.iq.iqInstsIssued 100270845 # Number of instructions issued 700system.cpu0.iq.iqSquashedInstsIssued 450536 # Number of squashed instructions issued 701system.cpu0.iq.iqSquashedInstsExamined 9007472 # Number of squashed instructions iterated over during squash; mainly for profiling 702system.cpu0.iq.iqSquashedOperandsExamined 21276029 # Number of squashed operands that are examined and possibly removed from graph 703system.cpu0.iq.iqSquashedNonSpecRemoved 120459 # Number of squashed non-spec instructions that were removed 704system.cpu0.iq.issued_per_cycle::samples 129216536 # Number of insts issued each cycle 705system.cpu0.iq.issued_per_cycle::mean 0.775991 # Number of insts issued each cycle 706system.cpu0.iq.issued_per_cycle::stdev 1.026149 # Number of insts issued each cycle |
| 691system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 707system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 692system.cpu0.iq.issued_per_cycle::0 123885975 61.74% 61.74% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::1 33618455 16.75% 78.50% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::2 31280513 15.59% 94.09% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::3 10734778 5.35% 99.44% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::4 1128444 0.56% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle | 708system.cpu0.iq.issued_per_cycle::0 73187499 56.64% 56.64% # Number of insts issued each cycle 709system.cpu0.iq.issued_per_cycle::1 23243158 17.99% 74.63% # Number of insts issued each cycle 710system.cpu0.iq.issued_per_cycle::2 22432715 17.36% 91.99% # Number of insts issued each cycle 711system.cpu0.iq.issued_per_cycle::3 9250445 7.16% 99.15% # Number of insts issued each cycle 712system.cpu0.iq.issued_per_cycle::4 1102673 0.85% 100.00% # Number of insts issued each cycle 713system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle |
| 698system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 701system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 702system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 703system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 714system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 715system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 716system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 717system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 718system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 719system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 704system.cpu0.iq.issued_per_cycle::total 200648219 # Number of insts issued each cycle | 720system.cpu0.iq.issued_per_cycle::total 129216536 # Number of insts issued each cycle |
| 705system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 721system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 706system.cpu0.iq.fu_full::IntAlu 10806493 43.96% 43.96% # attempts to use FU when none available 707system.cpu0.iq.fu_full::IntMult 67 0.00% 43.96% # attempts to use FU when none available 708system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.96% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.96% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.96% # attempts to use FU when none available 711system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.96% # attempts to use FU when none available 712system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.96% # attempts to use FU when none available 713system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available 714system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.96% # attempts to use FU when none available 715system.cpu0.iq.fu_full::FloatMisc 0 0.00% 43.96% # attempts to use FU when none available 716system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.96% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.96% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.96% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.96% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.96% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.96% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.96% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.96% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.96% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.96% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.96% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.96% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.96% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.96% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.96% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.96% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.96% # attempts to use FU when none available 733system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.96% # attempts to use FU when none available 734system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.96% # attempts to use FU when none available 735system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available 736system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.96% # attempts to use FU when none available 737system.cpu0.iq.fu_full::MemRead 5620315 22.86% 66.82% # attempts to use FU when none available 738system.cpu0.iq.fu_full::MemWrite 8146085 33.14% 99.96% # attempts to use FU when none available 739system.cpu0.iq.fu_full::FloatMemRead 2848 0.01% 99.97% # attempts to use FU when none available 740system.cpu0.iq.fu_full::FloatMemWrite 7137 0.03% 100.00% # attempts to use FU when none available | 722system.cpu0.iq.fu_full::IntAlu 9305182 40.57% 40.57% # attempts to use FU when none available 723system.cpu0.iq.fu_full::IntMult 67 0.00% 40.57% # attempts to use FU when none available 724system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.57% # attempts to use FU when none available 725system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.57% # attempts to use FU when none available 726system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.57% # attempts to use FU when none available 727system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.57% # attempts to use FU when none available 728system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.57% # attempts to use FU when none available 729system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available 730system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.57% # attempts to use FU when none available 731system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.57% # attempts to use FU when none available 732system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.57% # attempts to use FU when none available 733system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.57% # attempts to use FU when none available 734system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.57% # attempts to use FU when none available 735system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.57% # attempts to use FU when none available 736system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.57% # attempts to use FU when none available 737system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.57% # attempts to use FU when none available 738system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.57% # attempts to use FU when none available 739system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.57% # attempts to use FU when none available 740system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.57% # attempts to use FU when none available 741system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.57% # attempts to use FU when none available 742system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.57% # attempts to use FU when none available 743system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.57% # attempts to use FU when none available 744system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.57% # attempts to use FU when none available 745system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.57% # attempts to use FU when none available 746system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.57% # attempts to use FU when none available 747system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.57% # attempts to use FU when none available 748system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.57% # attempts to use FU when none available 749system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.57% # attempts to use FU when none available 750system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.57% # attempts to use FU when none available 751system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available 752system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.57% # attempts to use FU when none available 753system.cpu0.iq.fu_full::MemRead 5565388 24.27% 64.84% # attempts to use FU when none available 754system.cpu0.iq.fu_full::MemWrite 8055351 35.12% 99.96% # attempts to use FU when none available 755system.cpu0.iq.fu_full::FloatMemRead 2851 0.01% 99.97% # attempts to use FU when none available 756system.cpu0.iq.fu_full::FloatMemWrite 6938 0.03% 100.00% # attempts to use FU when none available |
| 741system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 742system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 743system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued | 757system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 758system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 759system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued |
| 744system.cpu0.iq.FU_type_0::IntAlu 89788621 67.56% 67.56% # Type of FU issued 745system.cpu0.iq.FU_type_0::IntMult 110178 0.08% 67.65% # Type of FU issued 746system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued 747system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued 748system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued 749system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued 750system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued 751system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 67.65% # Type of FU issued 752system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued 753system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 67.65% # Type of FU issued 754system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.65% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued 767system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued 768system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued 769system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued 770system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.65% # Type of FU issued 771system.cpu0.iq.FU_type_0::SimdFloatMisc 8088 0.01% 67.65% # Type of FU issued 772system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued 773system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.65% # Type of FU issued 774system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued 775system.cpu0.iq.FU_type_0::MemRead 24348007 18.32% 85.97% # Type of FU issued 776system.cpu0.iq.FU_type_0::MemWrite 18629393 14.02% 99.99% # Type of FU issued 777system.cpu0.iq.FU_type_0::FloatMemRead 3106 0.00% 99.99% # Type of FU issued 778system.cpu0.iq.FU_type_0::FloatMemWrite 8193 0.01% 100.00% # Type of FU issued | 760system.cpu0.iq.FU_type_0::IntAlu 66163298 65.98% 65.99% # Type of FU issued 761system.cpu0.iq.FU_type_0::IntMult 92264 0.09% 66.08% # Type of FU issued 762system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued 763system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.08% # Type of FU issued 764system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.08% # Type of FU issued 765system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.08% # Type of FU issued 766system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.08% # Type of FU issued 767system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.08% # Type of FU issued 768system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.08% # Type of FU issued 769system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 66.08% # Type of FU issued 770system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued 771system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued 772system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued 773system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued 774system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued 775system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued 776system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued 777system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued 778system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued 779system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued 780system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued 781system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued 782system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued 783system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued 784system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued 785system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued 786system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.08% # Type of FU issued 787system.cpu0.iq.FU_type_0::SimdFloatMisc 8058 0.01% 66.09% # Type of FU issued 788system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued 789system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued 791system.cpu0.iq.FU_type_0::MemRead 18375460 18.33% 84.41% # Type of FU issued 792system.cpu0.iq.FU_type_0::MemWrite 15618206 15.58% 99.99% # Type of FU issued 793system.cpu0.iq.FU_type_0::FloatMemRead 3108 0.00% 99.99% # Type of FU issued 794system.cpu0.iq.FU_type_0::FloatMemWrite 8177 0.01% 100.00% # Type of FU issued |
| 779system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 780system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 795system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 796system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 781system.cpu0.iq.FU_type_0::total 132897861 # Type of FU issued 782system.cpu0.iq.rate 0.647940 # Inst issue rate 783system.cpu0.iq.fu_busy_cnt 24582945 # FU busy when requested 784system.cpu0.iq.fu_busy_rate 0.184976 # FU busy rate (busy events/executed inst) 785system.cpu0.iq.int_inst_queue_reads 491444928 # Number of integer instruction queue reads 786system.cpu0.iq.int_inst_queue_writes 147076893 # Number of integer instruction queue writes 787system.cpu0.iq.int_inst_queue_wakeup_accesses 129373990 # Number of integer instruction queue wakeup accesses 788system.cpu0.iq.fp_inst_queue_reads 32623 # Number of floating instruction queue reads 789system.cpu0.iq.fp_inst_queue_writes 11320 # Number of floating instruction queue writes 790system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses 791system.cpu0.iq.int_alu_accesses 157457242 # Number of integer alu accesses 792system.cpu0.iq.fp_alu_accesses 21291 # Number of floating point alu accesses 793system.cpu0.iew.lsq.thread0.forwLoads 367347 # Number of loads that had data forwarded from stores | 797system.cpu0.iq.FU_type_0::total 100270845 # Type of FU issued 798system.cpu0.iq.rate 0.750463 # Inst issue rate 799system.cpu0.iq.fu_busy_cnt 22935777 # FU busy when requested 800system.cpu0.iq.fu_busy_rate 0.228738 # FU busy rate (busy events/executed inst) 801system.cpu0.iq.int_inst_queue_reads 353112143 # Number of integer instruction queue reads 802system.cpu0.iq.int_inst_queue_writes 112794988 # Number of integer instruction queue writes 803system.cpu0.iq.int_inst_queue_wakeup_accesses 98251090 # Number of integer instruction queue wakeup accesses 804system.cpu0.iq.fp_inst_queue_reads 32395 # Number of floating instruction queue reads 805system.cpu0.iq.fp_inst_queue_writes 11310 # Number of floating instruction queue writes 806system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses 807system.cpu0.iq.int_alu_accesses 123183269 # Number of integer alu accesses 808system.cpu0.iq.fp_alu_accesses 21080 # Number of floating point alu accesses 809system.cpu0.iew.lsq.thread0.forwLoads 364715 # Number of loads that had data forwarded from stores |
| 794system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 810system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 795system.cpu0.iew.lsq.thread0.squashedLoads 1915298 # Number of loads squashed 796system.cpu0.iew.lsq.thread0.ignoredResponses 2464 # Number of memory responses ignored because the instruction is squashed 797system.cpu0.iew.lsq.thread0.memOrderViolation 19139 # Number of memory ordering violations 798system.cpu0.iew.lsq.thread0.squashedStores 903377 # Number of stores squashed | 811system.cpu0.iew.lsq.thread0.squashedLoads 1893331 # Number of loads squashed 812system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed 813system.cpu0.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations 814system.cpu0.iew.lsq.thread0.squashedStores 881018 # Number of stores squashed |
| 799system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 800system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 815system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 816system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 801system.cpu0.iew.lsq.thread0.rescheduledLoads 121005 # Number of loads that were rescheduled 802system.cpu0.iew.lsq.thread0.cacheBlocked 360360 # Number of times an access to memory failed due to the cache being blocked | 817system.cpu0.iew.lsq.thread0.rescheduledLoads 109546 # Number of loads that were rescheduled 818system.cpu0.iew.lsq.thread0.cacheBlocked 360879 # Number of times an access to memory failed due to the cache being blocked |
| 803system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 819system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 804system.cpu0.iew.iewSquashCycles 2516184 # Number of cycles IEW is squashing 805system.cpu0.iew.iewBlockCycles 1671558 # Number of cycles IEW is blocking 806system.cpu0.iew.iewUnblockCycles 251575 # Number of cycles IEW is unblocking 807system.cpu0.iew.iewDispatchedInsts 136626375 # Number of instructions dispatched to IQ | 820system.cpu0.iew.iewSquashCycles 1042123 # Number of cycles IEW is squashing 821system.cpu0.iew.iewBlockCycles 1649895 # Number of cycles IEW is blocking 822system.cpu0.iew.iewUnblockCycles 244572 # Number of cycles IEW is unblocking 823system.cpu0.iew.iewDispatchedInsts 103932598 # Number of instructions dispatched to IQ |
| 808system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 824system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 809system.cpu0.iew.iewDispLoadInsts 24592847 # Number of dispatched load instructions 810system.cpu0.iew.iewDispStoreInsts 19077592 # Number of dispatched store instructions 811system.cpu0.iew.iewDispNonSpecInsts 875905 # Number of dispatched non-speculative instructions 812system.cpu0.iew.iewIQFullEvents 27780 # Number of times the IQ has become full, causing a stall 813system.cpu0.iew.iewLSQFullEvents 199746 # Number of times the LSQ has become full, causing a stall 814system.cpu0.iew.memOrderViolationEvents 19139 # Number of memory order violations 815system.cpu0.iew.predictedTakenIncorrect 262593 # Number of branches that were predicted taken incorrectly 816system.cpu0.iew.predictedNotTakenIncorrect 398520 # Number of branches that were predicted not taken incorrectly 817system.cpu0.iew.branchMispredicts 661113 # Number of branch mispredicts detected at execute 818system.cpu0.iew.iewExecutedInsts 131868425 # Number of executed instructions 819system.cpu0.iew.iewExecLoadInsts 23910267 # Number of load instructions executed 820system.cpu0.iew.iewExecSquashedInsts 963966 # Number of squashed instructions skipped in execute | 825system.cpu0.iew.iewDispLoadInsts 18622381 # Number of dispatched load instructions 826system.cpu0.iew.iewDispStoreInsts 16045587 # Number of dispatched store instructions 827system.cpu0.iew.iewDispNonSpecInsts 874828 # Number of dispatched non-speculative instructions 828system.cpu0.iew.iewIQFullEvents 27967 # Number of times the IQ has become full, causing a stall 829system.cpu0.iew.iewLSQFullEvents 192686 # Number of times the LSQ has become full, causing a stall 830system.cpu0.iew.memOrderViolationEvents 18814 # Number of memory order violations 831system.cpu0.iew.predictedTakenIncorrect 252890 # Number of branches that were predicted taken incorrectly 832system.cpu0.iew.predictedNotTakenIncorrect 404204 # Number of branches that were predicted not taken incorrectly 833system.cpu0.iew.branchMispredicts 657094 # Number of branch mispredicts detected at execute 834system.cpu0.iew.iewExecutedInsts 99256545 # Number of executed instructions 835system.cpu0.iew.iewExecLoadInsts 17939836 # Number of load instructions executed 836system.cpu0.iew.iewExecSquashedInsts 948116 # Number of squashed instructions skipped in execute |
| 821system.cpu0.iew.exec_swp 0 # number of swp insts executed | 837system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 822system.cpu0.iew.exec_nop 152678 # number of nop insts executed 823system.cpu0.iew.exec_refs 42387378 # number of memory reference insts executed 824system.cpu0.iew.exec_branches 25593933 # Number of branches executed 825system.cpu0.iew.exec_stores 18477111 # Number of stores executed 826system.cpu0.iew.exec_rate 0.642921 # Inst execution rate 827system.cpu0.iew.wb_sent 131315181 # cumulative count of insts sent to commit 828system.cpu0.iew.wb_count 129383707 # cumulative count of insts written-back 829system.cpu0.iew.wb_producers 66018205 # num instructions producing a value 830system.cpu0.iew.wb_consumers 106739719 # num instructions consuming a value 831system.cpu0.iew.wb_rate 0.630807 # insts written-back per cycle 832system.cpu0.iew.wb_fanout 0.618497 # average fanout of values written-back 833system.cpu0.commit.commitSquashedInsts 9567606 # The number of squashed insts skipped by commit 834system.cpu0.commit.commitNonSpecStalls 1594379 # The number of times commit has been forced to stall to communicate backwards 835system.cpu0.commit.branchMispredicts 604440 # The number of times a branch was mispredicted 836system.cpu0.commit.committed_per_cycle::samples 197485844 # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::mean 0.638022 # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::stdev 1.337140 # Number of insts commited each cycle | 838system.cpu0.iew.exec_nop 152510 # number of nop insts executed 839system.cpu0.iew.exec_refs 33405569 # number of memory reference insts executed 840system.cpu0.iew.exec_branches 16813883 # Number of branches executed 841system.cpu0.iew.exec_stores 15465733 # Number of stores executed 842system.cpu0.iew.exec_rate 0.742872 # Inst execution rate 843system.cpu0.iew.wb_sent 98711091 # cumulative count of insts sent to commit 844system.cpu0.iew.wb_count 98260806 # cumulative count of insts written-back 845system.cpu0.iew.wb_producers 51187228 # num instructions producing a value 846system.cpu0.iew.wb_consumers 84552650 # num instructions consuming a value 847system.cpu0.iew.wb_rate 0.735419 # insts written-back per cycle 848system.cpu0.iew.wb_fanout 0.605389 # average fanout of values written-back 849system.cpu0.commit.commitSquashedInsts 8010093 # The number of squashed insts skipped by commit 850system.cpu0.commit.commitNonSpecStalls 1570513 # The number of times commit has been forced to stall to communicate backwards 851system.cpu0.commit.branchMispredicts 599985 # The number of times a branch was mispredicted 852system.cpu0.commit.committed_per_cycle::samples 127532122 # Number of insts commited each cycle 853system.cpu0.commit.committed_per_cycle::mean 0.744084 # Number of insts commited each cycle 854system.cpu0.commit.committed_per_cycle::stdev 1.464109 # Number of insts commited each cycle |
| 839system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 855system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 840system.cpu0.commit.committed_per_cycle::0 137054336 69.40% 69.40% # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::1 33455560 16.94% 86.34% # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::2 12646051 6.40% 92.74% # Number of insts commited each cycle 843system.cpu0.commit.committed_per_cycle::3 3243439 1.64% 94.39% # Number of insts commited each cycle 844system.cpu0.commit.committed_per_cycle::4 4914257 2.49% 96.87% # Number of insts commited each cycle 845system.cpu0.commit.committed_per_cycle::5 2777569 1.41% 98.28% # Number of insts commited each cycle 846system.cpu0.commit.committed_per_cycle::6 1312207 0.66% 98.95% # Number of insts commited each cycle 847system.cpu0.commit.committed_per_cycle::7 555201 0.28% 99.23% # Number of insts commited each cycle 848system.cpu0.commit.committed_per_cycle::8 1527224 0.77% 100.00% # Number of insts commited each cycle | 856system.cpu0.commit.committed_per_cycle::0 83238506 65.27% 65.27% # Number of insts commited each cycle 857system.cpu0.commit.committed_per_cycle::1 24683933 19.36% 84.62% # Number of insts commited each cycle 858system.cpu0.commit.committed_per_cycle::2 8242078 6.46% 91.09% # Number of insts commited each cycle 859system.cpu0.commit.committed_per_cycle::3 3223359 2.53% 93.61% # Number of insts commited each cycle 860system.cpu0.commit.committed_per_cycle::4 3451127 2.71% 96.32% # Number of insts commited each cycle 861system.cpu0.commit.committed_per_cycle::5 1466865 1.15% 97.47% # Number of insts commited each cycle 862system.cpu0.commit.committed_per_cycle::6 1171264 0.92% 98.39% # Number of insts commited each cycle 863system.cpu0.commit.committed_per_cycle::7 549844 0.43% 98.82% # Number of insts commited each cycle 864system.cpu0.commit.committed_per_cycle::8 1505146 1.18% 100.00% # Number of insts commited each cycle |
| 849system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 850system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 851system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 865system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 866system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 867system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 852system.cpu0.commit.committed_per_cycle::total 197485844 # Number of insts commited each cycle 853system.cpu0.commit.committedInsts 104056922 # Number of instructions committed 854system.cpu0.commit.committedOps 126000293 # Number of ops (including micro ops) committed | 868system.cpu0.commit.committed_per_cycle::total 127532122 # Number of insts commited each cycle 869system.cpu0.commit.committedInsts 78880347 # Number of instructions committed 870system.cpu0.commit.committedOps 94894659 # Number of ops (including micro ops) committed |
| 855system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 871system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 856system.cpu0.commit.refs 40851763 # Number of memory references committed 857system.cpu0.commit.loads 22677548 # Number of loads committed 858system.cpu0.commit.membars 647714 # Number of memory barriers committed 859system.cpu0.commit.branches 24989662 # Number of branches committed | 872system.cpu0.commit.refs 31893618 # Number of memory references committed 873system.cpu0.commit.loads 16729049 # Number of loads committed 874system.cpu0.commit.membars 646523 # Number of memory barriers committed 875system.cpu0.commit.branches 16211772 # Number of branches committed |
| 860system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. | 876system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. |
| 861system.cpu0.commit.int_insts 109983283 # Number of committed integer instructions. 862system.cpu0.commit.function_calls 4835482 # Number of function calls committed. | 877system.cpu0.commit.int_insts 81832780 # Number of committed integer instructions. 878system.cpu0.commit.function_calls 1927003 # Number of function calls committed. |
| 863system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 879system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 864system.cpu0.commit.op_class_0::IntAlu 85032586 67.49% 67.49% # Class of committed instruction 865system.cpu0.commit.op_class_0::IntMult 107857 0.09% 67.57% # Class of committed instruction 866system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction 867system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction 868system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction 869system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction 870system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction 871system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction 872system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction 873system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction 874system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction 883system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction 884system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction 885system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction 886system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction 887system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction 888system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction 889system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction 890system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction 891system.cpu0.commit.op_class_0::SimdFloatMisc 8087 0.01% 67.58% # Class of committed instruction 892system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction 893system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction 894system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction 895system.cpu0.commit.op_class_0::MemRead 22675292 18.00% 85.57% # Class of committed instruction 896system.cpu0.commit.op_class_0::MemWrite 18166767 14.42% 99.99% # Class of committed instruction | 880system.cpu0.commit.op_class_0::IntAlu 62903043 66.29% 66.29% # Class of committed instruction 881system.cpu0.commit.op_class_0::IntMult 89941 0.09% 66.38% # Class of committed instruction 882system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 883system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 884system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 885system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 886system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 887system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 66.38% # Class of committed instruction 888system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 889system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 66.38% # Class of committed instruction 890system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 891system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction 892system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction 893system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction 894system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction 895system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction 896system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction 897system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction 898system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction 899system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 900system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 901system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 902system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 903system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 904system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 905system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 906system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction 907system.cpu0.commit.op_class_0::SimdFloatMisc 8057 0.01% 66.39% # Class of committed instruction 908system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction 909system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction 910system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction 911system.cpu0.commit.op_class_0::MemRead 16726793 17.63% 84.02% # Class of committed instruction 912system.cpu0.commit.op_class_0::MemWrite 15157121 15.97% 99.99% # Class of committed instruction |
| 897system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction 898system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction 899system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 900system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 913system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction 914system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction 915system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 916system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 901system.cpu0.commit.op_class_0::total 126000293 # Class of committed instruction 902system.cpu0.commit.bw_lim_events 1527224 # number cycles where commit BW limit reached 903system.cpu0.rob.rob_reads 308240127 # The number of ROB reads 904system.cpu0.rob.rob_writes 274288918 # The number of ROB writes 905system.cpu0.timesIdled 136024 # Number of times that the entire CPU went into an idle state and unscheduled itself 906system.cpu0.idleCycles 4460031 # Total number of cycles that the CPU has spent unscheduled due to idling 907system.cpu0.quiesceCycles 5448199500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 908system.cpu0.committedInsts 103934870 # Number of Instructions Simulated 909system.cpu0.committedOps 125878241 # Number of Ops (including micro ops) Simulated 910system.cpu0.cpi 1.973431 # CPI: Cycles Per Instruction 911system.cpu0.cpi_total 1.973431 # CPI: Total CPI of All Threads 912system.cpu0.ipc 0.506732 # IPC: Instructions Per Cycle 913system.cpu0.ipc_total 0.506732 # IPC: Total IPC of All Threads 914system.cpu0.int_regfile_reads 142861191 # number of integer regfile reads 915system.cpu0.int_regfile_writes 81742978 # number of integer regfile writes 916system.cpu0.fp_regfile_reads 8188 # number of floating regfile reads 917system.cpu0.fp_regfile_writes 2265 # number of floating regfile writes 918system.cpu0.cc_regfile_reads 465378109 # number of cc regfile reads 919system.cpu0.cc_regfile_writes 49818068 # number of cc regfile writes 920system.cpu0.misc_regfile_reads 399016543 # number of misc regfile reads 921system.cpu0.misc_regfile_writes 1225433 # number of misc regfile writes 922system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 923system.cpu0.dcache.tags.replacements 712812 # number of replacements 924system.cpu0.dcache.tags.tagsinuse 499.246418 # Cycle average of tags in use 925system.cpu0.dcache.tags.total_refs 37680999 # Total number of references to valid blocks. 926system.cpu0.dcache.tags.sampled_refs 713324 # Sample count of references to valid blocks. 927system.cpu0.dcache.tags.avg_refs 52.824522 # Average number of references to valid blocks. | 917system.cpu0.commit.op_class_0::total 94894659 # Class of committed instruction 918system.cpu0.commit.bw_lim_events 1505146 # number cycles where commit BW limit reached 919system.cpu0.rob.rob_reads 224742704 # The number of ROB reads 920system.cpu0.rob.rob_writes 207484818 # The number of ROB writes 921system.cpu0.timesIdled 136289 # Number of times that the entire CPU went into an idle state and unscheduled itself 922system.cpu0.idleCycles 4395415 # Total number of cycles that the CPU has spent unscheduled due to idling 923system.cpu0.quiesceCycles 5519733867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 924system.cpu0.committedInsts 78758295 # Number of Instructions Simulated 925system.cpu0.committedOps 94772607 # Number of Ops (including micro ops) Simulated 926system.cpu0.cpi 1.696481 # CPI: Cycles Per Instruction 927system.cpu0.cpi_total 1.696481 # CPI: Total CPI of All Threads 928system.cpu0.ipc 0.589455 # IPC: Instructions Per Cycle 929system.cpu0.ipc_total 0.589455 # IPC: Total IPC of All Threads 930system.cpu0.int_regfile_reads 110218064 # number of integer regfile reads 931system.cpu0.int_regfile_writes 59484746 # number of integer regfile writes 932system.cpu0.fp_regfile_reads 8170 # number of floating regfile reads 933system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 934system.cpu0.cc_regfile_reads 349694687 # number of cc regfile reads 935system.cpu0.cc_regfile_writes 40999571 # number of cc regfile writes 936system.cpu0.misc_regfile_reads 254801117 # number of misc regfile reads 937system.cpu0.misc_regfile_writes 1223326 # number of misc regfile writes 938system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 939system.cpu0.dcache.tags.replacements 712506 # number of replacements 940system.cpu0.dcache.tags.tagsinuse 498.213160 # Cycle average of tags in use 941system.cpu0.dcache.tags.total_refs 28740042 # Total number of references to valid blocks. 942system.cpu0.dcache.tags.sampled_refs 713018 # Sample count of references to valid blocks. 943system.cpu0.dcache.tags.avg_refs 40.307597 # Average number of references to valid blocks. |
| 928system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. | 944system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. |
| 929system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.246418 # Average occupied blocks per requestor 930system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975091 # Average percentage of cache occupancy 931system.cpu0.dcache.tags.occ_percent::total 0.975091 # Average percentage of cache occupancy | 945system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.213160 # Average occupied blocks per requestor 946system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973073 # Average percentage of cache occupancy 947system.cpu0.dcache.tags.occ_percent::total 0.973073 # Average percentage of cache occupancy |
| 932system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 948system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 933system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id 934system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id 935system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id | 949system.cpu0.dcache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id 950system.cpu0.dcache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id 951system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id |
| 936system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 952system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 937system.cpu0.dcache.tags.tag_accesses 81225267 # Number of tag accesses 938system.cpu0.dcache.tags.data_accesses 81225267 # Number of data accesses 939system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 940system.cpu0.dcache.ReadReq_hits::cpu0.data 21467047 # number of ReadReq hits 941system.cpu0.dcache.ReadReq_hits::total 21467047 # number of ReadReq hits 942system.cpu0.dcache.WriteReq_hits::cpu0.data 14989931 # number of WriteReq hits 943system.cpu0.dcache.WriteReq_hits::total 14989931 # number of WriteReq hits 944system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307917 # number of SoftPFReq hits 945system.cpu0.dcache.SoftPFReq_hits::total 307917 # number of SoftPFReq hits 946system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363108 # number of LoadLockedReq hits 947system.cpu0.dcache.LoadLockedReq_hits::total 363108 # number of LoadLockedReq hits 948system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361279 # number of StoreCondReq hits 949system.cpu0.dcache.StoreCondReq_hits::total 361279 # number of StoreCondReq hits 950system.cpu0.dcache.demand_hits::cpu0.data 36456978 # number of demand (read+write) hits 951system.cpu0.dcache.demand_hits::total 36456978 # number of demand (read+write) hits 952system.cpu0.dcache.overall_hits::cpu0.data 36764895 # number of overall hits 953system.cpu0.dcache.overall_hits::total 36764895 # number of overall hits 954system.cpu0.dcache.ReadReq_misses::cpu0.data 649306 # number of ReadReq misses 955system.cpu0.dcache.ReadReq_misses::total 649306 # number of ReadReq misses 956system.cpu0.dcache.WriteReq_misses::cpu0.data 1896144 # number of WriteReq misses 957system.cpu0.dcache.WriteReq_misses::total 1896144 # number of WriteReq misses 958system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148546 # number of SoftPFReq misses 959system.cpu0.dcache.SoftPFReq_misses::total 148546 # number of SoftPFReq misses 960system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25295 # number of LoadLockedReq misses 961system.cpu0.dcache.LoadLockedReq_misses::total 25295 # number of LoadLockedReq misses 962system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20257 # number of StoreCondReq misses 963system.cpu0.dcache.StoreCondReq_misses::total 20257 # number of StoreCondReq misses 964system.cpu0.dcache.demand_misses::cpu0.data 2545450 # number of demand (read+write) misses 965system.cpu0.dcache.demand_misses::total 2545450 # number of demand (read+write) misses 966system.cpu0.dcache.overall_misses::cpu0.data 2693996 # number of overall misses 967system.cpu0.dcache.overall_misses::total 2693996 # number of overall misses 968system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9384044500 # number of ReadReq miss cycles 969system.cpu0.dcache.ReadReq_miss_latency::total 9384044500 # number of ReadReq miss cycles 970system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32956196365 # number of WriteReq miss cycles 971system.cpu0.dcache.WriteReq_miss_latency::total 32956196365 # number of WriteReq miss cycles 972system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 411578000 # number of LoadLockedReq miss cycles 973system.cpu0.dcache.LoadLockedReq_miss_latency::total 411578000 # number of LoadLockedReq miss cycles 974system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 478843500 # number of StoreCondReq miss cycles 975system.cpu0.dcache.StoreCondReq_miss_latency::total 478843500 # number of StoreCondReq miss cycles 976system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 432000 # number of StoreCondFailReq miss cycles 977system.cpu0.dcache.StoreCondFailReq_miss_latency::total 432000 # number of StoreCondFailReq miss cycles 978system.cpu0.dcache.demand_miss_latency::cpu0.data 42340240865 # number of demand (read+write) miss cycles 979system.cpu0.dcache.demand_miss_latency::total 42340240865 # number of demand (read+write) miss cycles 980system.cpu0.dcache.overall_miss_latency::cpu0.data 42340240865 # number of overall miss cycles 981system.cpu0.dcache.overall_miss_latency::total 42340240865 # number of overall miss cycles 982system.cpu0.dcache.ReadReq_accesses::cpu0.data 22116353 # number of ReadReq accesses(hits+misses) 983system.cpu0.dcache.ReadReq_accesses::total 22116353 # number of ReadReq accesses(hits+misses) 984system.cpu0.dcache.WriteReq_accesses::cpu0.data 16886075 # number of WriteReq accesses(hits+misses) 985system.cpu0.dcache.WriteReq_accesses::total 16886075 # number of WriteReq accesses(hits+misses) 986system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456463 # number of SoftPFReq accesses(hits+misses) 987system.cpu0.dcache.SoftPFReq_accesses::total 456463 # number of SoftPFReq accesses(hits+misses) 988system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388403 # number of LoadLockedReq accesses(hits+misses) 989system.cpu0.dcache.LoadLockedReq_accesses::total 388403 # number of LoadLockedReq accesses(hits+misses) 990system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381536 # number of StoreCondReq accesses(hits+misses) 991system.cpu0.dcache.StoreCondReq_accesses::total 381536 # number of StoreCondReq accesses(hits+misses) 992system.cpu0.dcache.demand_accesses::cpu0.data 39002428 # number of demand (read+write) accesses 993system.cpu0.dcache.demand_accesses::total 39002428 # number of demand (read+write) accesses 994system.cpu0.dcache.overall_accesses::cpu0.data 39458891 # number of overall (read+write) accesses 995system.cpu0.dcache.overall_accesses::total 39458891 # number of overall (read+write) accesses 996system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029359 # miss rate for ReadReq accesses 997system.cpu0.dcache.ReadReq_miss_rate::total 0.029359 # miss rate for ReadReq accesses 998system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112290 # miss rate for WriteReq accesses 999system.cpu0.dcache.WriteReq_miss_rate::total 0.112290 # miss rate for WriteReq accesses 1000system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325428 # miss rate for SoftPFReq accesses 1001system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325428 # miss rate for SoftPFReq accesses 1002system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065126 # miss rate for LoadLockedReq accesses 1003system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065126 # miss rate for LoadLockedReq accesses 1004system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053093 # miss rate for StoreCondReq accesses 1005system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053093 # miss rate for StoreCondReq accesses 1006system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065264 # miss rate for demand accesses 1007system.cpu0.dcache.demand_miss_rate::total 0.065264 # miss rate for demand accesses 1008system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068273 # miss rate for overall accesses 1009system.cpu0.dcache.overall_miss_rate::total 0.068273 # miss rate for overall accesses 1010system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14452.422279 # average ReadReq miss latency 1011system.cpu0.dcache.ReadReq_avg_miss_latency::total 14452.422279 # average ReadReq miss latency 1012system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17380.640060 # average WriteReq miss latency 1013system.cpu0.dcache.WriteReq_avg_miss_latency::total 17380.640060 # average WriteReq miss latency 1014system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16271.120775 # average LoadLockedReq miss latency 1015system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.120775 # average LoadLockedReq miss latency 1016system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23638.421286 # average StoreCondReq miss latency 1017system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23638.421286 # average StoreCondReq miss latency | 953system.cpu0.dcache.tags.tag_accesses 63341698 # Number of tag accesses 954system.cpu0.dcache.tags.data_accesses 63341698 # Number of data accesses 955system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 956system.cpu0.dcache.ReadReq_hits::cpu0.data 15523802 # number of ReadReq hits 957system.cpu0.dcache.ReadReq_hits::total 15523802 # number of ReadReq hits 958system.cpu0.dcache.WriteReq_hits::cpu0.data 11993925 # number of WriteReq hits 959system.cpu0.dcache.WriteReq_hits::total 11993925 # number of WriteReq hits 960system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307586 # number of SoftPFReq hits 961system.cpu0.dcache.SoftPFReq_hits::total 307586 # number of SoftPFReq hits 962system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362517 # number of LoadLockedReq hits 963system.cpu0.dcache.LoadLockedReq_hits::total 362517 # number of LoadLockedReq hits 964system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360768 # number of StoreCondReq hits 965system.cpu0.dcache.StoreCondReq_hits::total 360768 # number of StoreCondReq hits 966system.cpu0.dcache.demand_hits::cpu0.data 27517727 # number of demand (read+write) hits 967system.cpu0.dcache.demand_hits::total 27517727 # number of demand (read+write) hits 968system.cpu0.dcache.overall_hits::cpu0.data 27825313 # number of overall hits 969system.cpu0.dcache.overall_hits::total 27825313 # number of overall hits 970system.cpu0.dcache.ReadReq_misses::cpu0.data 649486 # number of ReadReq misses 971system.cpu0.dcache.ReadReq_misses::total 649486 # number of ReadReq misses 972system.cpu0.dcache.WriteReq_misses::cpu0.data 1895154 # number of WriteReq misses 973system.cpu0.dcache.WriteReq_misses::total 1895154 # number of WriteReq misses 974system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148364 # number of SoftPFReq misses 975system.cpu0.dcache.SoftPFReq_misses::total 148364 # number of SoftPFReq misses 976system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25286 # number of LoadLockedReq misses 977system.cpu0.dcache.LoadLockedReq_misses::total 25286 # number of LoadLockedReq misses 978system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses 979system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses 980system.cpu0.dcache.demand_misses::cpu0.data 2544640 # number of demand (read+write) misses 981system.cpu0.dcache.demand_misses::total 2544640 # number of demand (read+write) misses 982system.cpu0.dcache.overall_misses::cpu0.data 2693004 # number of overall misses 983system.cpu0.dcache.overall_misses::total 2693004 # number of overall misses 984system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9367064500 # number of ReadReq miss cycles 985system.cpu0.dcache.ReadReq_miss_latency::total 9367064500 # number of ReadReq miss cycles 986system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33076385872 # number of WriteReq miss cycles 987system.cpu0.dcache.WriteReq_miss_latency::total 33076385872 # number of WriteReq miss cycles 988system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412133000 # number of LoadLockedReq miss cycles 989system.cpu0.dcache.LoadLockedReq_miss_latency::total 412133000 # number of LoadLockedReq miss cycles 990system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479472000 # number of StoreCondReq miss cycles 991system.cpu0.dcache.StoreCondReq_miss_latency::total 479472000 # number of StoreCondReq miss cycles 992system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles 993system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # number of StoreCondFailReq miss cycles 994system.cpu0.dcache.demand_miss_latency::cpu0.data 42443450372 # number of demand (read+write) miss cycles 995system.cpu0.dcache.demand_miss_latency::total 42443450372 # number of demand (read+write) miss cycles 996system.cpu0.dcache.overall_miss_latency::cpu0.data 42443450372 # number of overall miss cycles 997system.cpu0.dcache.overall_miss_latency::total 42443450372 # number of overall miss cycles 998system.cpu0.dcache.ReadReq_accesses::cpu0.data 16173288 # number of ReadReq accesses(hits+misses) 999system.cpu0.dcache.ReadReq_accesses::total 16173288 # number of ReadReq accesses(hits+misses) 1000system.cpu0.dcache.WriteReq_accesses::cpu0.data 13889079 # number of WriteReq accesses(hits+misses) 1001system.cpu0.dcache.WriteReq_accesses::total 13889079 # number of WriteReq accesses(hits+misses) 1002system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455950 # number of SoftPFReq accesses(hits+misses) 1003system.cpu0.dcache.SoftPFReq_accesses::total 455950 # number of SoftPFReq accesses(hits+misses) 1004system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387803 # number of LoadLockedReq accesses(hits+misses) 1005system.cpu0.dcache.LoadLockedReq_accesses::total 387803 # number of LoadLockedReq accesses(hits+misses) 1006system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381015 # number of StoreCondReq accesses(hits+misses) 1007system.cpu0.dcache.StoreCondReq_accesses::total 381015 # number of StoreCondReq accesses(hits+misses) 1008system.cpu0.dcache.demand_accesses::cpu0.data 30062367 # number of demand (read+write) accesses 1009system.cpu0.dcache.demand_accesses::total 30062367 # number of demand (read+write) accesses 1010system.cpu0.dcache.overall_accesses::cpu0.data 30518317 # number of overall (read+write) accesses 1011system.cpu0.dcache.overall_accesses::total 30518317 # number of overall (read+write) accesses 1012system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040158 # miss rate for ReadReq accesses 1013system.cpu0.dcache.ReadReq_miss_rate::total 0.040158 # miss rate for ReadReq accesses 1014system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136449 # miss rate for WriteReq accesses 1015system.cpu0.dcache.WriteReq_miss_rate::total 0.136449 # miss rate for WriteReq accesses 1016system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325395 # miss rate for SoftPFReq accesses 1017system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325395 # miss rate for SoftPFReq accesses 1018system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065203 # miss rate for LoadLockedReq accesses 1019system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065203 # miss rate for LoadLockedReq accesses 1020system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053140 # miss rate for StoreCondReq accesses 1021system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053140 # miss rate for StoreCondReq accesses 1022system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084645 # miss rate for demand accesses 1023system.cpu0.dcache.demand_miss_rate::total 0.084645 # miss rate for demand accesses 1024system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088242 # miss rate for overall accesses 1025system.cpu0.dcache.overall_miss_rate::total 0.088242 # miss rate for overall accesses 1026system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14422.273151 # average ReadReq miss latency 1027system.cpu0.dcache.ReadReq_avg_miss_latency::total 14422.273151 # average ReadReq miss latency 1028system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17453.138833 # average WriteReq miss latency 1029system.cpu0.dcache.WriteReq_avg_miss_latency::total 17453.138833 # average WriteReq miss latency 1030system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16298.861030 # average LoadLockedReq miss latency 1031system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16298.861030 # average LoadLockedReq miss latency 1032system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23681.137946 # average StoreCondReq miss latency 1033system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23681.137946 # average StoreCondReq miss latency |
| 1018system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1019system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1034system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1035system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1020system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16633.695757 # average overall miss latency 1021system.cpu0.dcache.demand_avg_miss_latency::total 16633.695757 # average overall miss latency 1022system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15716.519574 # average overall miss latency 1023system.cpu0.dcache.overall_avg_miss_latency::total 15716.519574 # average overall miss latency 1024system.cpu0.dcache.blocked_cycles::no_mshrs 757 # number of cycles access was blocked 1025system.cpu0.dcache.blocked_cycles::no_targets 4969613 # number of cycles access was blocked 1026system.cpu0.dcache.blocked::no_mshrs 42 # number of cycles access was blocked 1027system.cpu0.dcache.blocked::no_targets 201973 # number of cycles access was blocked 1028system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.023810 # average number of cycles each access was blocked 1029system.cpu0.dcache.avg_blocked_cycles::no_targets 24.605333 # average number of cycles each access was blocked 1030system.cpu0.dcache.writebacks::writebacks 712815 # number of writebacks 1031system.cpu0.dcache.writebacks::total 712815 # number of writebacks 1032system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260774 # number of ReadReq MSHR hits 1033system.cpu0.dcache.ReadReq_mshr_hits::total 260774 # number of ReadReq MSHR hits 1034system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570443 # number of WriteReq MSHR hits 1035system.cpu0.dcache.WriteReq_mshr_hits::total 1570443 # number of WriteReq MSHR hits 1036system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18576 # number of LoadLockedReq MSHR hits 1037system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18576 # number of LoadLockedReq MSHR hits 1038system.cpu0.dcache.demand_mshr_hits::cpu0.data 1831217 # number of demand (read+write) MSHR hits 1039system.cpu0.dcache.demand_mshr_hits::total 1831217 # number of demand (read+write) MSHR hits 1040system.cpu0.dcache.overall_mshr_hits::cpu0.data 1831217 # number of overall MSHR hits 1041system.cpu0.dcache.overall_mshr_hits::total 1831217 # number of overall MSHR hits 1042system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388532 # number of ReadReq MSHR misses 1043system.cpu0.dcache.ReadReq_mshr_misses::total 388532 # number of ReadReq MSHR misses 1044system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325701 # number of WriteReq MSHR misses 1045system.cpu0.dcache.WriteReq_mshr_misses::total 325701 # number of WriteReq MSHR misses 1046system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102377 # number of SoftPFReq MSHR misses 1047system.cpu0.dcache.SoftPFReq_mshr_misses::total 102377 # number of SoftPFReq MSHR misses 1048system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6719 # number of LoadLockedReq MSHR misses 1049system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6719 # number of LoadLockedReq MSHR misses 1050system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20257 # number of StoreCondReq MSHR misses 1051system.cpu0.dcache.StoreCondReq_mshr_misses::total 20257 # number of StoreCondReq MSHR misses 1052system.cpu0.dcache.demand_mshr_misses::cpu0.data 714233 # number of demand (read+write) MSHR misses 1053system.cpu0.dcache.demand_mshr_misses::total 714233 # number of demand (read+write) MSHR misses 1054system.cpu0.dcache.overall_mshr_misses::cpu0.data 816610 # number of overall MSHR misses 1055system.cpu0.dcache.overall_mshr_misses::total 816610 # number of overall MSHR misses 1056system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable 1057system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32008 # number of ReadReq MSHR uncacheable 1058system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable 1059system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable 1060system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses 1061system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60690 # number of overall MSHR uncacheable misses 1062system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5031436500 # number of ReadReq MSHR miss cycles 1063system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5031436500 # number of ReadReq MSHR miss cycles 1064system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6631878895 # number of WriteReq MSHR miss cycles 1065system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6631878895 # number of WriteReq MSHR miss cycles 1066system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1714108500 # number of SoftPFReq MSHR miss cycles 1067system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1714108500 # number of SoftPFReq MSHR miss cycles 1068system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107735000 # number of LoadLockedReq MSHR miss cycles 1069system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107735000 # number of LoadLockedReq MSHR miss cycles 1070system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458598500 # number of StoreCondReq MSHR miss cycles 1071system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458598500 # number of StoreCondReq MSHR miss cycles 1072system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 420000 # number of StoreCondFailReq MSHR miss cycles 1073system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 420000 # number of StoreCondFailReq MSHR miss cycles 1074system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11663315395 # number of demand (read+write) MSHR miss cycles 1075system.cpu0.dcache.demand_mshr_miss_latency::total 11663315395 # number of demand (read+write) MSHR miss cycles 1076system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13377423895 # number of overall MSHR miss cycles 1077system.cpu0.dcache.overall_mshr_miss_latency::total 13377423895 # number of overall MSHR miss cycles 1078system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6681974000 # number of ReadReq MSHR uncacheable cycles 1079system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6681974000 # number of ReadReq MSHR uncacheable cycles 1080system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6681974000 # number of overall MSHR uncacheable cycles 1081system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6681974000 # number of overall MSHR uncacheable cycles 1082system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017568 # mshr miss rate for ReadReq accesses 1083system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017568 # mshr miss rate for ReadReq accesses 1084system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019288 # mshr miss rate for WriteReq accesses 1085system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019288 # mshr miss rate for WriteReq accesses 1086system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224283 # mshr miss rate for SoftPFReq accesses 1087system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224283 # mshr miss rate for SoftPFReq accesses 1088system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017299 # mshr miss rate for LoadLockedReq accesses 1089system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017299 # mshr miss rate for LoadLockedReq accesses 1090system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053093 # mshr miss rate for StoreCondReq accesses 1091system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053093 # mshr miss rate for StoreCondReq accesses 1092system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018313 # mshr miss rate for demand accesses 1093system.cpu0.dcache.demand_mshr_miss_rate::total 0.018313 # mshr miss rate for demand accesses 1094system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020695 # mshr miss rate for overall accesses 1095system.cpu0.dcache.overall_mshr_miss_rate::total 0.020695 # mshr miss rate for overall accesses 1096system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12949.863846 # average ReadReq mshr miss latency 1097system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12949.863846 # average ReadReq mshr miss latency 1098system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20361.862245 # average WriteReq mshr miss latency 1099system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20361.862245 # average WriteReq mshr miss latency 1100system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16743.101478 # average SoftPFReq mshr miss latency 1101system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16743.101478 # average SoftPFReq mshr miss latency 1102system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16034.380116 # average LoadLockedReq mshr miss latency 1103system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16034.380116 # average LoadLockedReq mshr miss latency 1104system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22639.013674 # average StoreCondReq mshr miss latency 1105system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22639.013674 # average StoreCondReq mshr miss latency | 1036system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16679.550102 # average overall miss latency 1037system.cpu0.dcache.demand_avg_miss_latency::total 16679.550102 # average overall miss latency 1038system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15760.633988 # average overall miss latency 1039system.cpu0.dcache.overall_avg_miss_latency::total 15760.633988 # average overall miss latency 1040system.cpu0.dcache.blocked_cycles::no_mshrs 689 # number of cycles access was blocked 1041system.cpu0.dcache.blocked_cycles::no_targets 4988118 # number of cycles access was blocked 1042system.cpu0.dcache.blocked::no_mshrs 32 # number of cycles access was blocked 1043system.cpu0.dcache.blocked::no_targets 201830 # number of cycles access was blocked 1044system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.531250 # average number of cycles each access was blocked 1045system.cpu0.dcache.avg_blocked_cycles::no_targets 24.714453 # average number of cycles each access was blocked 1046system.cpu0.dcache.writebacks::writebacks 712509 # number of writebacks 1047system.cpu0.dcache.writebacks::total 712509 # number of writebacks 1048system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 261058 # number of ReadReq MSHR hits 1049system.cpu0.dcache.ReadReq_mshr_hits::total 261058 # number of ReadReq MSHR hits 1050system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569543 # number of WriteReq MSHR hits 1051system.cpu0.dcache.WriteReq_mshr_hits::total 1569543 # number of WriteReq MSHR hits 1052system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18570 # number of LoadLockedReq MSHR hits 1053system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18570 # number of LoadLockedReq MSHR hits 1054system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830601 # number of demand (read+write) MSHR hits 1055system.cpu0.dcache.demand_mshr_hits::total 1830601 # number of demand (read+write) MSHR hits 1056system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830601 # number of overall MSHR hits 1057system.cpu0.dcache.overall_mshr_hits::total 1830601 # number of overall MSHR hits 1058system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388428 # number of ReadReq MSHR misses 1059system.cpu0.dcache.ReadReq_mshr_misses::total 388428 # number of ReadReq MSHR misses 1060system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325611 # number of WriteReq MSHR misses 1061system.cpu0.dcache.WriteReq_mshr_misses::total 325611 # number of WriteReq MSHR misses 1062system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102372 # number of SoftPFReq MSHR misses 1063system.cpu0.dcache.SoftPFReq_mshr_misses::total 102372 # number of SoftPFReq MSHR misses 1064system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6716 # number of LoadLockedReq MSHR misses 1065system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6716 # number of LoadLockedReq MSHR misses 1066system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20247 # number of StoreCondReq MSHR misses 1067system.cpu0.dcache.StoreCondReq_mshr_misses::total 20247 # number of StoreCondReq MSHR misses 1068system.cpu0.dcache.demand_mshr_misses::cpu0.data 714039 # number of demand (read+write) MSHR misses 1069system.cpu0.dcache.demand_mshr_misses::total 714039 # number of demand (read+write) MSHR misses 1070system.cpu0.dcache.overall_mshr_misses::cpu0.data 816411 # number of overall MSHR misses 1071system.cpu0.dcache.overall_mshr_misses::total 816411 # number of overall MSHR misses 1072system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable 1073system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable 1074system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable 1075system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19269 # number of WriteReq MSHR uncacheable 1076system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 1077system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses 1078system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5013254500 # number of ReadReq MSHR miss cycles 1079system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5013254500 # number of ReadReq MSHR miss cycles 1080system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6647950897 # number of WriteReq MSHR miss cycles 1081system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6647950897 # number of WriteReq MSHR miss cycles 1082system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1709667500 # number of SoftPFReq MSHR miss cycles 1083system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1709667500 # number of SoftPFReq MSHR miss cycles 1084system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108314000 # number of LoadLockedReq MSHR miss cycles 1085system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108314000 # number of LoadLockedReq MSHR miss cycles 1086system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459237000 # number of StoreCondReq MSHR miss cycles 1087system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459237000 # number of StoreCondReq MSHR miss cycles 1088system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 442500 # number of StoreCondFailReq MSHR miss cycles 1089system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 442500 # number of StoreCondFailReq MSHR miss cycles 1090system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11661205397 # number of demand (read+write) MSHR miss cycles 1091system.cpu0.dcache.demand_mshr_miss_latency::total 11661205397 # number of demand (read+write) MSHR miss cycles 1092system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13370872897 # number of overall MSHR miss cycles 1093system.cpu0.dcache.overall_mshr_miss_latency::total 13370872897 # number of overall MSHR miss cycles 1094system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4595503500 # number of ReadReq MSHR uncacheable cycles 1095system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4595503500 # number of ReadReq MSHR uncacheable cycles 1096system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4595503500 # number of overall MSHR uncacheable cycles 1097system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4595503500 # number of overall MSHR uncacheable cycles 1098system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024017 # mshr miss rate for ReadReq accesses 1099system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024017 # mshr miss rate for ReadReq accesses 1100system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023444 # mshr miss rate for WriteReq accesses 1101system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023444 # mshr miss rate for WriteReq accesses 1102system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224525 # mshr miss rate for SoftPFReq accesses 1103system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224525 # mshr miss rate for SoftPFReq accesses 1104system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017318 # mshr miss rate for LoadLockedReq accesses 1105system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017318 # mshr miss rate for LoadLockedReq accesses 1106system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053140 # mshr miss rate for StoreCondReq accesses 1107system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053140 # mshr miss rate for StoreCondReq accesses 1108system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023752 # mshr miss rate for demand accesses 1109system.cpu0.dcache.demand_mshr_miss_rate::total 0.023752 # mshr miss rate for demand accesses 1110system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026752 # mshr miss rate for overall accesses 1111system.cpu0.dcache.overall_mshr_miss_rate::total 0.026752 # mshr miss rate for overall accesses 1112system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12906.521929 # average ReadReq mshr miss latency 1113system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12906.521929 # average ReadReq mshr miss latency 1114system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20416.849852 # average WriteReq mshr miss latency 1115system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20416.849852 # average WriteReq mshr miss latency 1116system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16700.538233 # average SoftPFReq mshr miss latency 1117system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16700.538233 # average SoftPFReq mshr miss latency 1118system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16127.754616 # average LoadLockedReq mshr miss latency 1119system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16127.754616 # average LoadLockedReq mshr miss latency 1120system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22681.730627 # average StoreCondReq mshr miss latency 1121system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22681.730627 # average StoreCondReq mshr miss latency |
| 1106system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1107system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1122system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1123system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1108system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16329.846696 # average overall mshr miss latency 1109system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16329.846696 # average overall mshr miss latency 1110system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16381.655741 # average overall mshr miss latency 1111system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16381.655741 # average overall mshr miss latency 1112system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208759.497626 # average ReadReq mshr uncacheable latency 1113system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208759.497626 # average ReadReq mshr uncacheable latency 1114system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110100.082386 # average overall mshr uncacheable latency 1115system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110100.082386 # average overall mshr uncacheable latency 1116system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1117system.cpu0.icache.tags.replacements 1249331 # number of replacements 1118system.cpu0.icache.tags.tagsinuse 511.757700 # Cycle average of tags in use 1119system.cpu0.icache.tags.total_refs 71450204 # Total number of references to valid blocks. 1120system.cpu0.icache.tags.sampled_refs 1249842 # Sample count of references to valid blocks. 1121system.cpu0.icache.tags.avg_refs 57.167389 # Average number of references to valid blocks. 1122system.cpu0.icache.tags.warmup_cycle 6584638000 # Cycle when the warmup percentage was hit. 1123system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757700 # Average occupied blocks per requestor | 1124system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16331.328397 # average overall mshr miss latency 1125system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16331.328397 # average overall mshr miss latency 1126system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16377.624624 # average overall mshr miss latency 1127system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16377.624624 # average overall mshr miss latency 1128system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223332.045488 # average ReadReq mshr uncacheable latency 1129system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223332.045488 # average ReadReq mshr uncacheable latency 1130system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115331.614215 # average overall mshr uncacheable latency 1131system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115331.614215 # average overall mshr uncacheable latency 1132system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1133system.cpu0.icache.tags.replacements 1246758 # number of replacements 1134system.cpu0.icache.tags.tagsinuse 511.757641 # Cycle average of tags in use 1135system.cpu0.icache.tags.total_refs 36137139 # Total number of references to valid blocks. 1136system.cpu0.icache.tags.sampled_refs 1247269 # Sample count of references to valid blocks. 1137system.cpu0.icache.tags.avg_refs 28.973011 # Average number of references to valid blocks. 1138system.cpu0.icache.tags.warmup_cycle 6586723000 # Cycle when the warmup percentage was hit. 1139system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757641 # Average occupied blocks per requestor |
| 1124system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy 1125system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy 1126system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id | 1140system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy 1141system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy 1142system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| 1127system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 1128system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 1129system.cpu0.icache.tags.age_task_id_blocks_1024::2 125 # Occupied blocks per task id | 1143system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 1144system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 1145system.cpu0.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id |
| 1130system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 1146system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 1131system.cpu0.icache.tags.tag_accesses 146758301 # Number of tag accesses 1132system.cpu0.icache.tags.data_accesses 146758301 # Number of data accesses 1133system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1134system.cpu0.icache.ReadReq_hits::cpu0.inst 71450207 # number of ReadReq hits 1135system.cpu0.icache.ReadReq_hits::total 71450207 # number of ReadReq hits 1136system.cpu0.icache.demand_hits::cpu0.inst 71450207 # number of demand (read+write) hits 1137system.cpu0.icache.demand_hits::total 71450207 # number of demand (read+write) hits 1138system.cpu0.icache.overall_hits::cpu0.inst 71450207 # number of overall hits 1139system.cpu0.icache.overall_hits::total 71450207 # number of overall hits 1140system.cpu0.icache.ReadReq_misses::cpu0.inst 1303999 # number of ReadReq misses 1141system.cpu0.icache.ReadReq_misses::total 1303999 # number of ReadReq misses 1142system.cpu0.icache.demand_misses::cpu0.inst 1303999 # number of demand (read+write) misses 1143system.cpu0.icache.demand_misses::total 1303999 # number of demand (read+write) misses 1144system.cpu0.icache.overall_misses::cpu0.inst 1303999 # number of overall misses 1145system.cpu0.icache.overall_misses::total 1303999 # number of overall misses 1146system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14174791933 # number of ReadReq miss cycles 1147system.cpu0.icache.ReadReq_miss_latency::total 14174791933 # number of ReadReq miss cycles 1148system.cpu0.icache.demand_miss_latency::cpu0.inst 14174791933 # number of demand (read+write) miss cycles 1149system.cpu0.icache.demand_miss_latency::total 14174791933 # number of demand (read+write) miss cycles 1150system.cpu0.icache.overall_miss_latency::cpu0.inst 14174791933 # number of overall miss cycles 1151system.cpu0.icache.overall_miss_latency::total 14174791933 # number of overall miss cycles 1152system.cpu0.icache.ReadReq_accesses::cpu0.inst 72754206 # number of ReadReq accesses(hits+misses) 1153system.cpu0.icache.ReadReq_accesses::total 72754206 # number of ReadReq accesses(hits+misses) 1154system.cpu0.icache.demand_accesses::cpu0.inst 72754206 # number of demand (read+write) accesses 1155system.cpu0.icache.demand_accesses::total 72754206 # number of demand (read+write) accesses 1156system.cpu0.icache.overall_accesses::cpu0.inst 72754206 # number of overall (read+write) accesses 1157system.cpu0.icache.overall_accesses::total 72754206 # number of overall (read+write) accesses 1158system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017923 # miss rate for ReadReq accesses 1159system.cpu0.icache.ReadReq_miss_rate::total 0.017923 # miss rate for ReadReq accesses 1160system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017923 # miss rate for demand accesses 1161system.cpu0.icache.demand_miss_rate::total 0.017923 # miss rate for demand accesses 1162system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017923 # miss rate for overall accesses 1163system.cpu0.icache.overall_miss_rate::total 0.017923 # miss rate for overall accesses 1164system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10870.247549 # average ReadReq miss latency 1165system.cpu0.icache.ReadReq_avg_miss_latency::total 10870.247549 # average ReadReq miss latency 1166system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency 1167system.cpu0.icache.demand_avg_miss_latency::total 10870.247549 # average overall miss latency 1168system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency 1169system.cpu0.icache.overall_avg_miss_latency::total 10870.247549 # average overall miss latency 1170system.cpu0.icache.blocked_cycles::no_mshrs 1760744 # number of cycles access was blocked 1171system.cpu0.icache.blocked_cycles::no_targets 1640 # number of cycles access was blocked 1172system.cpu0.icache.blocked::no_mshrs 114723 # number of cycles access was blocked | 1147system.cpu0.icache.tags.tag_accesses 76124237 # Number of tag accesses 1148system.cpu0.icache.tags.data_accesses 76124237 # Number of data accesses 1149system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1150system.cpu0.icache.ReadReq_hits::cpu0.inst 36137142 # number of ReadReq hits 1151system.cpu0.icache.ReadReq_hits::total 36137142 # number of ReadReq hits 1152system.cpu0.icache.demand_hits::cpu0.inst 36137142 # number of demand (read+write) hits 1153system.cpu0.icache.demand_hits::total 36137142 # number of demand (read+write) hits 1154system.cpu0.icache.overall_hits::cpu0.inst 36137142 # number of overall hits 1155system.cpu0.icache.overall_hits::total 36137142 # number of overall hits 1156system.cpu0.icache.ReadReq_misses::cpu0.inst 1301318 # number of ReadReq misses 1157system.cpu0.icache.ReadReq_misses::total 1301318 # number of ReadReq misses 1158system.cpu0.icache.demand_misses::cpu0.inst 1301318 # number of demand (read+write) misses 1159system.cpu0.icache.demand_misses::total 1301318 # number of demand (read+write) misses 1160system.cpu0.icache.overall_misses::cpu0.inst 1301318 # number of overall misses 1161system.cpu0.icache.overall_misses::total 1301318 # number of overall misses 1162system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14070925518 # number of ReadReq miss cycles 1163system.cpu0.icache.ReadReq_miss_latency::total 14070925518 # number of ReadReq miss cycles 1164system.cpu0.icache.demand_miss_latency::cpu0.inst 14070925518 # number of demand (read+write) miss cycles 1165system.cpu0.icache.demand_miss_latency::total 14070925518 # number of demand (read+write) miss cycles 1166system.cpu0.icache.overall_miss_latency::cpu0.inst 14070925518 # number of overall miss cycles 1167system.cpu0.icache.overall_miss_latency::total 14070925518 # number of overall miss cycles 1168system.cpu0.icache.ReadReq_accesses::cpu0.inst 37438460 # number of ReadReq accesses(hits+misses) 1169system.cpu0.icache.ReadReq_accesses::total 37438460 # number of ReadReq accesses(hits+misses) 1170system.cpu0.icache.demand_accesses::cpu0.inst 37438460 # number of demand (read+write) accesses 1171system.cpu0.icache.demand_accesses::total 37438460 # number of demand (read+write) accesses 1172system.cpu0.icache.overall_accesses::cpu0.inst 37438460 # number of overall (read+write) accesses 1173system.cpu0.icache.overall_accesses::total 37438460 # number of overall (read+write) accesses 1174system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034759 # miss rate for ReadReq accesses 1175system.cpu0.icache.ReadReq_miss_rate::total 0.034759 # miss rate for ReadReq accesses 1176system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034759 # miss rate for demand accesses 1177system.cpu0.icache.demand_miss_rate::total 0.034759 # miss rate for demand accesses 1178system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034759 # miss rate for overall accesses 1179system.cpu0.icache.overall_miss_rate::total 0.034759 # miss rate for overall accesses 1180system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10812.826318 # average ReadReq miss latency 1181system.cpu0.icache.ReadReq_avg_miss_latency::total 10812.826318 # average ReadReq miss latency 1182system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency 1183system.cpu0.icache.demand_avg_miss_latency::total 10812.826318 # average overall miss latency 1184system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency 1185system.cpu0.icache.overall_avg_miss_latency::total 10812.826318 # average overall miss latency 1186system.cpu0.icache.blocked_cycles::no_mshrs 1742114 # number of cycles access was blocked 1187system.cpu0.icache.blocked_cycles::no_targets 1649 # number of cycles access was blocked 1188system.cpu0.icache.blocked::no_mshrs 114160 # number of cycles access was blocked |
| 1173system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked | 1189system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked |
| 1174system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.347786 # average number of cycles each access was blocked 1175system.cpu0.icache.avg_blocked_cycles::no_targets 126.153846 # average number of cycles each access was blocked 1176system.cpu0.icache.writebacks::writebacks 1249331 # number of writebacks 1177system.cpu0.icache.writebacks::total 1249331 # number of writebacks 1178system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54109 # number of ReadReq MSHR hits 1179system.cpu0.icache.ReadReq_mshr_hits::total 54109 # number of ReadReq MSHR hits 1180system.cpu0.icache.demand_mshr_hits::cpu0.inst 54109 # number of demand (read+write) MSHR hits 1181system.cpu0.icache.demand_mshr_hits::total 54109 # number of demand (read+write) MSHR hits 1182system.cpu0.icache.overall_mshr_hits::cpu0.inst 54109 # number of overall MSHR hits 1183system.cpu0.icache.overall_mshr_hits::total 54109 # number of overall MSHR hits 1184system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1249890 # number of ReadReq MSHR misses 1185system.cpu0.icache.ReadReq_mshr_misses::total 1249890 # number of ReadReq MSHR misses 1186system.cpu0.icache.demand_mshr_misses::cpu0.inst 1249890 # number of demand (read+write) MSHR misses 1187system.cpu0.icache.demand_mshr_misses::total 1249890 # number of demand (read+write) MSHR misses 1188system.cpu0.icache.overall_mshr_misses::cpu0.inst 1249890 # number of overall MSHR misses 1189system.cpu0.icache.overall_mshr_misses::total 1249890 # number of overall MSHR misses | 1190system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.260284 # average number of cycles each access was blocked 1191system.cpu0.icache.avg_blocked_cycles::no_targets 126.846154 # average number of cycles each access was blocked 1192system.cpu0.icache.writebacks::writebacks 1246758 # number of writebacks 1193system.cpu0.icache.writebacks::total 1246758 # number of writebacks 1194system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54000 # number of ReadReq MSHR hits 1195system.cpu0.icache.ReadReq_mshr_hits::total 54000 # number of ReadReq MSHR hits 1196system.cpu0.icache.demand_mshr_hits::cpu0.inst 54000 # number of demand (read+write) MSHR hits 1197system.cpu0.icache.demand_mshr_hits::total 54000 # number of demand (read+write) MSHR hits 1198system.cpu0.icache.overall_mshr_hits::cpu0.inst 54000 # number of overall MSHR hits 1199system.cpu0.icache.overall_mshr_hits::total 54000 # number of overall MSHR hits 1200system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1247318 # number of ReadReq MSHR misses 1201system.cpu0.icache.ReadReq_mshr_misses::total 1247318 # number of ReadReq MSHR misses 1202system.cpu0.icache.demand_mshr_misses::cpu0.inst 1247318 # number of demand (read+write) MSHR misses 1203system.cpu0.icache.demand_mshr_misses::total 1247318 # number of demand (read+write) MSHR misses 1204system.cpu0.icache.overall_mshr_misses::cpu0.inst 1247318 # number of overall MSHR misses 1205system.cpu0.icache.overall_mshr_misses::total 1247318 # number of overall MSHR misses |
| 1190system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable 1191system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable 1192system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses 1193system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses | 1206system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable 1207system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable 1208system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses 1209system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses |
| 1194system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12814231927 # number of ReadReq MSHR miss cycles 1195system.cpu0.icache.ReadReq_mshr_miss_latency::total 12814231927 # number of ReadReq MSHR miss cycles 1196system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12814231927 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.icache.demand_mshr_miss_latency::total 12814231927 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12814231927 # number of overall MSHR miss cycles 1199system.cpu0.icache.overall_mshr_miss_latency::total 12814231927 # number of overall MSHR miss cycles | 1210system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12734729518 # number of ReadReq MSHR miss cycles 1211system.cpu0.icache.ReadReq_mshr_miss_latency::total 12734729518 # number of ReadReq MSHR miss cycles 1212system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12734729518 # number of demand (read+write) MSHR miss cycles 1213system.cpu0.icache.demand_mshr_miss_latency::total 12734729518 # number of demand (read+write) MSHR miss cycles 1214system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12734729518 # number of overall MSHR miss cycles 1215system.cpu0.icache.overall_mshr_miss_latency::total 12734729518 # number of overall MSHR miss cycles |
| 1200system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles 1202system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles 1203system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles | 1216system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles 1217system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles 1218system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles 1219system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles |
| 1204system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for ReadReq accesses 1205system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017180 # mshr miss rate for ReadReq accesses 1206system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for demand accesses 1207system.cpu0.icache.demand_mshr_miss_rate::total 0.017180 # mshr miss rate for demand accesses 1208system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for overall accesses 1209system.cpu0.icache.overall_mshr_miss_rate::total 0.017180 # mshr miss rate for overall accesses 1210system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average ReadReq mshr miss latency 1211system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10252.287743 # average ReadReq mshr miss latency 1212system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency 1213system.cpu0.icache.demand_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency 1214system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency 1215system.cpu0.icache.overall_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency | 1220system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for ReadReq accesses 1221system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses 1222system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for demand accesses 1223system.cpu0.icache.demand_mshr_miss_rate::total 0.033316 # mshr miss rate for demand accesses 1224system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for overall accesses 1225system.cpu0.icache.overall_mshr_miss_rate::total 0.033316 # mshr miss rate for overall accesses 1226system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average ReadReq mshr miss latency 1227system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10209.689524 # average ReadReq mshr miss latency 1228system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency 1229system.cpu0.icache.demand_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency 1230system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency 1231system.cpu0.icache.overall_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency |
| 1216system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency 1217system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency 1218system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency 1219system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency | 1232system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency 1233system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency 1234system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency 1235system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency |
| 1220system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1221system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846767 # number of hwpf issued 1222system.cpu0.l2cache.prefetcher.pfIdentified 1849379 # number of prefetch candidates identified 1223system.cpu0.l2cache.prefetcher.pfBufferHit 2365 # number of redundant prefetches already in prefetch queue | 1236system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1237system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845705 # number of hwpf issued 1238system.cpu0.l2cache.prefetcher.pfIdentified 1848223 # number of prefetch candidates identified 1239system.cpu0.l2cache.prefetcher.pfBufferHit 2284 # number of redundant prefetches already in prefetch queue |
| 1224system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1225system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1240system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1241system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1226system.cpu0.l2cache.prefetcher.pfSpanPage 236461 # number of prefetches not generated due to page crossing 1227system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1228system.cpu0.l2cache.tags.replacements 270933 # number of replacements 1229system.cpu0.l2cache.tags.tagsinuse 15649.129225 # Cycle average of tags in use 1230system.cpu0.l2cache.tags.total_refs 1883932 # Total number of references to valid blocks. 1231system.cpu0.l2cache.tags.sampled_refs 286558 # Sample count of references to valid blocks. 1232system.cpu0.l2cache.tags.avg_refs 6.574348 # Average number of references to valid blocks. | 1242system.cpu0.l2cache.prefetcher.pfSpanPage 235089 # number of prefetches not generated due to page crossing 1243system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1244system.cpu0.l2cache.tags.replacements 270085 # number of replacements 1245system.cpu0.l2cache.tags.tagsinuse 15641.965642 # Cycle average of tags in use 1246system.cpu0.l2cache.tags.total_refs 1885208 # Total number of references to valid blocks. 1247system.cpu0.l2cache.tags.sampled_refs 285711 # Sample count of references to valid blocks. 1248system.cpu0.l2cache.tags.avg_refs 6.598304 # Average number of references to valid blocks. |
| 1233system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1249system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1234system.cpu0.l2cache.tags.occ_blocks::writebacks 14546.798617 # Average occupied blocks per requestor 1235system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.022626 # Average occupied blocks per requestor 1236system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137647 # Average occupied blocks per requestor 1237system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1090.170335 # Average occupied blocks per requestor 1238system.cpu0.l2cache.tags.occ_percent::writebacks 0.887866 # Average percentage of cache occupancy 1239system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000734 # Average percentage of cache occupancy 1240system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 1241system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066539 # Average percentage of cache occupancy 1242system.cpu0.l2cache.tags.occ_percent::total 0.955147 # Average percentage of cache occupancy 1243system.cpu0.l2cache.tags.occ_task_id_blocks::1022 298 # Occupied blocks per task id 1244system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id 1245system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15316 # Occupied blocks per task id 1246system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 1247system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id 1248system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 145 # Occupied blocks per task id 1249system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 80 # Occupied blocks per task id 1250system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1251system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1252system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1433 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7528 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4690 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018188 # Percentage of cache occupancy per task id 1260system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 1261system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934814 # Percentage of cache occupancy per task id 1262system.cpu0.l2cache.tags.tag_accesses 67601036 # Number of tag accesses 1263system.cpu0.l2cache.tags.data_accesses 67601036 # Number of data accesses 1264system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1265system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54858 # number of ReadReq hits 1266system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13069 # number of ReadReq hits 1267system.cpu0.l2cache.ReadReq_hits::total 67927 # number of ReadReq hits 1268system.cpu0.l2cache.WritebackDirty_hits::writebacks 483646 # number of WritebackDirty hits 1269system.cpu0.l2cache.WritebackDirty_hits::total 483646 # number of WritebackDirty hits 1270system.cpu0.l2cache.WritebackClean_hits::writebacks 1447155 # number of WritebackClean hits 1271system.cpu0.l2cache.WritebackClean_hits::total 1447155 # number of WritebackClean hits 1272system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 1273system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 1274system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221212 # number of ReadExReq hits 1275system.cpu0.l2cache.ReadExReq_hits::total 221212 # number of ReadExReq hits 1276system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1179291 # number of ReadCleanReq hits 1277system.cpu0.l2cache.ReadCleanReq_hits::total 1179291 # number of ReadCleanReq hits 1278system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 390010 # number of ReadSharedReq hits 1279system.cpu0.l2cache.ReadSharedReq_hits::total 390010 # number of ReadSharedReq hits 1280system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54858 # number of demand (read+write) hits 1281system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13069 # number of demand (read+write) hits 1282system.cpu0.l2cache.demand_hits::cpu0.inst 1179291 # number of demand (read+write) hits 1283system.cpu0.l2cache.demand_hits::cpu0.data 611222 # number of demand (read+write) hits 1284system.cpu0.l2cache.demand_hits::total 1858440 # number of demand (read+write) hits 1285system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54858 # number of overall hits 1286system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13069 # number of overall hits 1287system.cpu0.l2cache.overall_hits::cpu0.inst 1179291 # number of overall hits 1288system.cpu0.l2cache.overall_hits::cpu0.data 611222 # number of overall hits 1289system.cpu0.l2cache.overall_hits::total 1858440 # number of overall hits 1290system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 514 # number of ReadReq misses 1291system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 209 # number of ReadReq misses 1292system.cpu0.l2cache.ReadReq_misses::total 723 # number of ReadReq misses 1293system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55801 # number of UpgradeReq misses 1294system.cpu0.l2cache.UpgradeReq_misses::total 55801 # number of UpgradeReq misses 1295system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20257 # number of SCUpgradeReq misses 1296system.cpu0.l2cache.SCUpgradeReq_misses::total 20257 # number of SCUpgradeReq misses 1297system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48873 # number of ReadExReq misses 1298system.cpu0.l2cache.ReadExReq_misses::total 48873 # number of ReadExReq misses 1299system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70560 # number of ReadCleanReq misses 1300system.cpu0.l2cache.ReadCleanReq_misses::total 70560 # number of ReadCleanReq misses 1301system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107498 # number of ReadSharedReq misses 1302system.cpu0.l2cache.ReadSharedReq_misses::total 107498 # number of ReadSharedReq misses 1303system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 514 # number of demand (read+write) misses 1304system.cpu0.l2cache.demand_misses::cpu0.itb.walker 209 # number of demand (read+write) misses 1305system.cpu0.l2cache.demand_misses::cpu0.inst 70560 # number of demand (read+write) misses 1306system.cpu0.l2cache.demand_misses::cpu0.data 156371 # number of demand (read+write) misses 1307system.cpu0.l2cache.demand_misses::total 227654 # number of demand (read+write) misses 1308system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 514 # number of overall misses 1309system.cpu0.l2cache.overall_misses::cpu0.itb.walker 209 # number of overall misses 1310system.cpu0.l2cache.overall_misses::cpu0.inst 70560 # number of overall misses 1311system.cpu0.l2cache.overall_misses::cpu0.data 156371 # number of overall misses 1312system.cpu0.l2cache.overall_misses::total 227654 # number of overall misses 1313system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15837500 # number of ReadReq miss cycles 1314system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5057000 # number of ReadReq miss cycles 1315system.cpu0.l2cache.ReadReq_miss_latency::total 20894500 # number of ReadReq miss cycles 1316system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 37580500 # number of UpgradeReq miss cycles 1317system.cpu0.l2cache.UpgradeReq_miss_latency::total 37580500 # number of UpgradeReq miss cycles 1318system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9656000 # number of SCUpgradeReq miss cycles 1319system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9656000 # number of SCUpgradeReq miss cycles 1320system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 401500 # number of SCUpgradeFailReq miss cycles 1321system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 401500 # number of SCUpgradeFailReq miss cycles 1322system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3379601499 # number of ReadExReq miss cycles 1323system.cpu0.l2cache.ReadExReq_miss_latency::total 3379601499 # number of ReadExReq miss cycles 1324system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3771387500 # number of ReadCleanReq miss cycles 1325system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3771387500 # number of ReadCleanReq miss cycles 1326system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3519117997 # number of ReadSharedReq miss cycles 1327system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3519117997 # number of ReadSharedReq miss cycles 1328system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15837500 # number of demand (read+write) miss cycles 1329system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5057000 # number of demand (read+write) miss cycles 1330system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3771387500 # number of demand (read+write) miss cycles 1331system.cpu0.l2cache.demand_miss_latency::cpu0.data 6898719496 # number of demand (read+write) miss cycles 1332system.cpu0.l2cache.demand_miss_latency::total 10691001496 # number of demand (read+write) miss cycles 1333system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15837500 # number of overall miss cycles 1334system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5057000 # number of overall miss cycles 1335system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3771387500 # number of overall miss cycles 1336system.cpu0.l2cache.overall_miss_latency::cpu0.data 6898719496 # number of overall miss cycles 1337system.cpu0.l2cache.overall_miss_latency::total 10691001496 # number of overall miss cycles 1338system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55372 # number of ReadReq accesses(hits+misses) 1339system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13278 # number of ReadReq accesses(hits+misses) 1340system.cpu0.l2cache.ReadReq_accesses::total 68650 # number of ReadReq accesses(hits+misses) 1341system.cpu0.l2cache.WritebackDirty_accesses::writebacks 483646 # number of WritebackDirty accesses(hits+misses) 1342system.cpu0.l2cache.WritebackDirty_accesses::total 483646 # number of WritebackDirty accesses(hits+misses) 1343system.cpu0.l2cache.WritebackClean_accesses::writebacks 1447155 # number of WritebackClean accesses(hits+misses) 1344system.cpu0.l2cache.WritebackClean_accesses::total 1447155 # number of WritebackClean accesses(hits+misses) 1345system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55802 # number of UpgradeReq accesses(hits+misses) 1346system.cpu0.l2cache.UpgradeReq_accesses::total 55802 # number of UpgradeReq accesses(hits+misses) 1347system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20257 # number of SCUpgradeReq accesses(hits+misses) 1348system.cpu0.l2cache.SCUpgradeReq_accesses::total 20257 # number of SCUpgradeReq accesses(hits+misses) 1349system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270085 # number of ReadExReq accesses(hits+misses) 1350system.cpu0.l2cache.ReadExReq_accesses::total 270085 # number of ReadExReq accesses(hits+misses) 1351system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1249851 # number of ReadCleanReq accesses(hits+misses) 1352system.cpu0.l2cache.ReadCleanReq_accesses::total 1249851 # number of ReadCleanReq accesses(hits+misses) 1353system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497508 # number of ReadSharedReq accesses(hits+misses) 1354system.cpu0.l2cache.ReadSharedReq_accesses::total 497508 # number of ReadSharedReq accesses(hits+misses) 1355system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55372 # number of demand (read+write) accesses 1356system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13278 # number of demand (read+write) accesses 1357system.cpu0.l2cache.demand_accesses::cpu0.inst 1249851 # number of demand (read+write) accesses 1358system.cpu0.l2cache.demand_accesses::cpu0.data 767593 # number of demand (read+write) accesses 1359system.cpu0.l2cache.demand_accesses::total 2086094 # number of demand (read+write) accesses 1360system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55372 # number of overall (read+write) accesses 1361system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13278 # number of overall (read+write) accesses 1362system.cpu0.l2cache.overall_accesses::cpu0.inst 1249851 # number of overall (read+write) accesses 1363system.cpu0.l2cache.overall_accesses::cpu0.data 767593 # number of overall (read+write) accesses 1364system.cpu0.l2cache.overall_accesses::total 2086094 # number of overall (read+write) accesses 1365system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for ReadReq accesses 1366system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015740 # miss rate for ReadReq accesses 1367system.cpu0.l2cache.ReadReq_miss_rate::total 0.010532 # miss rate for ReadReq accesses 1368system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses 1369system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses | 1250system.cpu0.l2cache.tags.occ_blocks::writebacks 14498.888394 # Average occupied blocks per requestor 1251system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.509265 # Average occupied blocks per requestor 1252system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.944405 # Average occupied blocks per requestor 1253system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1130.623578 # Average occupied blocks per requestor 1254system.cpu0.l2cache.tags.occ_percent::writebacks 0.884942 # Average percentage of cache occupancy 1255system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000702 # Average percentage of cache occupancy 1256system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000058 # Average percentage of cache occupancy 1257system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.069008 # Average percentage of cache occupancy 1258system.cpu0.l2cache.tags.occ_percent::total 0.954710 # Average percentage of cache occupancy 1259system.cpu0.l2cache.tags.occ_task_id_blocks::1022 275 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15342 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 1267system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1456 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id 1272system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4683 # Occupied blocks per task id 1273system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1303 # Occupied blocks per task id 1274system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016785 # Percentage of cache occupancy per task id 1275system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 1276system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936401 # Percentage of cache occupancy per task id 1277system.cpu0.l2cache.tags.tag_accesses 67537653 # Number of tag accesses 1278system.cpu0.l2cache.tags.data_accesses 67537653 # Number of data accesses 1279system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1280system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55283 # number of ReadReq hits 1281system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14603 # number of ReadReq hits 1282system.cpu0.l2cache.ReadReq_hits::total 69886 # number of ReadReq hits 1283system.cpu0.l2cache.WritebackDirty_hits::writebacks 482862 # number of WritebackDirty hits 1284system.cpu0.l2cache.WritebackDirty_hits::total 482862 # number of WritebackDirty hits 1285system.cpu0.l2cache.WritebackClean_hits::writebacks 1445066 # number of WritebackClean hits 1286system.cpu0.l2cache.WritebackClean_hits::total 1445066 # number of WritebackClean hits 1287system.cpu0.l2cache.ReadExReq_hits::cpu0.data 220992 # number of ReadExReq hits 1288system.cpu0.l2cache.ReadExReq_hits::total 220992 # number of ReadExReq hits 1289system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1177410 # number of ReadCleanReq hits 1290system.cpu0.l2cache.ReadCleanReq_hits::total 1177410 # number of ReadCleanReq hits 1291system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389847 # number of ReadSharedReq hits 1292system.cpu0.l2cache.ReadSharedReq_hits::total 389847 # number of ReadSharedReq hits 1293system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55283 # number of demand (read+write) hits 1294system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14603 # number of demand (read+write) hits 1295system.cpu0.l2cache.demand_hits::cpu0.inst 1177410 # number of demand (read+write) hits 1296system.cpu0.l2cache.demand_hits::cpu0.data 610839 # number of demand (read+write) hits 1297system.cpu0.l2cache.demand_hits::total 1858135 # number of demand (read+write) hits 1298system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55283 # number of overall hits 1299system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14603 # number of overall hits 1300system.cpu0.l2cache.overall_hits::cpu0.inst 1177410 # number of overall hits 1301system.cpu0.l2cache.overall_hits::cpu0.data 610839 # number of overall hits 1302system.cpu0.l2cache.overall_hits::total 1858135 # number of overall hits 1303system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 528 # number of ReadReq misses 1304system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 200 # number of ReadReq misses 1305system.cpu0.l2cache.ReadReq_misses::total 728 # number of ReadReq misses 1306system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55774 # number of UpgradeReq misses 1307system.cpu0.l2cache.UpgradeReq_misses::total 55774 # number of UpgradeReq misses 1308system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20246 # number of SCUpgradeReq misses 1309system.cpu0.l2cache.SCUpgradeReq_misses::total 20246 # number of SCUpgradeReq misses 1310system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1311system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1312system.cpu0.l2cache.ReadExReq_misses::cpu0.data 49029 # number of ReadExReq misses 1313system.cpu0.l2cache.ReadExReq_misses::total 49029 # number of ReadExReq misses 1314system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 69866 # number of ReadCleanReq misses 1315system.cpu0.l2cache.ReadCleanReq_misses::total 69866 # number of ReadCleanReq misses 1316system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107548 # number of ReadSharedReq misses 1317system.cpu0.l2cache.ReadSharedReq_misses::total 107548 # number of ReadSharedReq misses 1318system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 528 # number of demand (read+write) misses 1319system.cpu0.l2cache.demand_misses::cpu0.itb.walker 200 # number of demand (read+write) misses 1320system.cpu0.l2cache.demand_misses::cpu0.inst 69866 # number of demand (read+write) misses 1321system.cpu0.l2cache.demand_misses::cpu0.data 156577 # number of demand (read+write) misses 1322system.cpu0.l2cache.demand_misses::total 227171 # number of demand (read+write) misses 1323system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 528 # number of overall misses 1324system.cpu0.l2cache.overall_misses::cpu0.itb.walker 200 # number of overall misses 1325system.cpu0.l2cache.overall_misses::cpu0.inst 69866 # number of overall misses 1326system.cpu0.l2cache.overall_misses::cpu0.data 156577 # number of overall misses 1327system.cpu0.l2cache.overall_misses::total 227171 # number of overall misses 1328system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 17967500 # number of ReadReq miss cycles 1329system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4680500 # number of ReadReq miss cycles 1330system.cpu0.l2cache.ReadReq_miss_latency::total 22648000 # number of ReadReq miss cycles 1331system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 38083500 # number of UpgradeReq miss cycles 1332system.cpu0.l2cache.UpgradeReq_miss_latency::total 38083500 # number of UpgradeReq miss cycles 1333system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9705500 # number of SCUpgradeReq miss cycles 1334system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9705500 # number of SCUpgradeReq miss cycles 1335system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 424500 # number of SCUpgradeFailReq miss cycles 1336system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 424500 # number of SCUpgradeFailReq miss cycles 1337system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3399006998 # number of ReadExReq miss cycles 1338system.cpu0.l2cache.ReadExReq_miss_latency::total 3399006998 # number of ReadExReq miss cycles 1339system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3707068000 # number of ReadCleanReq miss cycles 1340system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3707068000 # number of ReadCleanReq miss cycles 1341system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3498037999 # number of ReadSharedReq miss cycles 1342system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3498037999 # number of ReadSharedReq miss cycles 1343system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 17967500 # number of demand (read+write) miss cycles 1344system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4680500 # number of demand (read+write) miss cycles 1345system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3707068000 # number of demand (read+write) miss cycles 1346system.cpu0.l2cache.demand_miss_latency::cpu0.data 6897044997 # number of demand (read+write) miss cycles 1347system.cpu0.l2cache.demand_miss_latency::total 10626760997 # number of demand (read+write) miss cycles 1348system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 17967500 # number of overall miss cycles 1349system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4680500 # number of overall miss cycles 1350system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3707068000 # number of overall miss cycles 1351system.cpu0.l2cache.overall_miss_latency::cpu0.data 6897044997 # number of overall miss cycles 1352system.cpu0.l2cache.overall_miss_latency::total 10626760997 # number of overall miss cycles 1353system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55811 # number of ReadReq accesses(hits+misses) 1354system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14803 # number of ReadReq accesses(hits+misses) 1355system.cpu0.l2cache.ReadReq_accesses::total 70614 # number of ReadReq accesses(hits+misses) 1356system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482862 # number of WritebackDirty accesses(hits+misses) 1357system.cpu0.l2cache.WritebackDirty_accesses::total 482862 # number of WritebackDirty accesses(hits+misses) 1358system.cpu0.l2cache.WritebackClean_accesses::writebacks 1445066 # number of WritebackClean accesses(hits+misses) 1359system.cpu0.l2cache.WritebackClean_accesses::total 1445066 # number of WritebackClean accesses(hits+misses) 1360system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55774 # number of UpgradeReq accesses(hits+misses) 1361system.cpu0.l2cache.UpgradeReq_accesses::total 55774 # number of UpgradeReq accesses(hits+misses) 1362system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20246 # number of SCUpgradeReq accesses(hits+misses) 1363system.cpu0.l2cache.SCUpgradeReq_accesses::total 20246 # number of SCUpgradeReq accesses(hits+misses) 1364system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1365system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270021 # number of ReadExReq accesses(hits+misses) 1367system.cpu0.l2cache.ReadExReq_accesses::total 270021 # number of ReadExReq accesses(hits+misses) 1368system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1247276 # number of ReadCleanReq accesses(hits+misses) 1369system.cpu0.l2cache.ReadCleanReq_accesses::total 1247276 # number of ReadCleanReq accesses(hits+misses) 1370system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497395 # number of ReadSharedReq accesses(hits+misses) 1371system.cpu0.l2cache.ReadSharedReq_accesses::total 497395 # number of ReadSharedReq accesses(hits+misses) 1372system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55811 # number of demand (read+write) accesses 1373system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14803 # number of demand (read+write) accesses 1374system.cpu0.l2cache.demand_accesses::cpu0.inst 1247276 # number of demand (read+write) accesses 1375system.cpu0.l2cache.demand_accesses::cpu0.data 767416 # number of demand (read+write) accesses 1376system.cpu0.l2cache.demand_accesses::total 2085306 # number of demand (read+write) accesses 1377system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55811 # number of overall (read+write) accesses 1378system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14803 # number of overall (read+write) accesses 1379system.cpu0.l2cache.overall_accesses::cpu0.inst 1247276 # number of overall (read+write) accesses 1380system.cpu0.l2cache.overall_accesses::cpu0.data 767416 # number of overall (read+write) accesses 1381system.cpu0.l2cache.overall_accesses::total 2085306 # number of overall (read+write) accesses 1382system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for ReadReq accesses 1383system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013511 # miss rate for ReadReq accesses 1384system.cpu0.l2cache.ReadReq_miss_rate::total 0.010310 # miss rate for ReadReq accesses 1385system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1386system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1370system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1371system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1387system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1388system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1372system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180954 # miss rate for ReadExReq accesses 1373system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180954 # miss rate for ReadExReq accesses 1374system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056455 # miss rate for ReadCleanReq accesses 1375system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056455 # miss rate for ReadCleanReq accesses 1376system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216073 # miss rate for ReadSharedReq accesses 1377system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216073 # miss rate for ReadSharedReq accesses 1378system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for demand accesses 1379system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015740 # miss rate for demand accesses 1380system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056455 # miss rate for demand accesses 1381system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203716 # miss rate for demand accesses 1382system.cpu0.l2cache.demand_miss_rate::total 0.109129 # miss rate for demand accesses 1383system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for overall accesses 1384system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015740 # miss rate for overall accesses 1385system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056455 # miss rate for overall accesses 1386system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203716 # miss rate for overall accesses 1387system.cpu0.l2cache.overall_miss_rate::total 0.109129 # miss rate for overall accesses 1388system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average ReadReq miss latency 1389system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24196.172249 # average ReadReq miss latency 1390system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28899.723375 # average ReadReq miss latency 1391system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 673.473594 # average UpgradeReq miss latency 1392system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 673.473594 # average UpgradeReq miss latency 1393system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 476.674730 # average SCUpgradeReq miss latency 1394system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 476.674730 # average SCUpgradeReq miss latency 1395system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1396system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1397system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69150.686453 # average ReadExReq miss latency 1398system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69150.686453 # average ReadExReq miss latency 1399system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53449.369331 # average ReadCleanReq miss latency 1400system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53449.369331 # average ReadCleanReq miss latency 1401system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32736.590420 # average ReadSharedReq miss latency 1402system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32736.590420 # average ReadSharedReq miss latency 1403system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency 1404system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency 1405system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency 1406system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency 1407system.cpu0.l2cache.demand_avg_miss_latency::total 46961.623762 # average overall miss latency 1408system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency 1409system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency 1410system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency 1411system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency 1412system.cpu0.l2cache.overall_avg_miss_latency::total 46961.623762 # average overall miss latency 1413system.cpu0.l2cache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked | 1389system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1390system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1391system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.181575 # miss rate for ReadExReq accesses 1392system.cpu0.l2cache.ReadExReq_miss_rate::total 0.181575 # miss rate for ReadExReq accesses 1393system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056015 # miss rate for ReadCleanReq accesses 1394system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056015 # miss rate for ReadCleanReq accesses 1395system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216223 # miss rate for ReadSharedReq accesses 1396system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216223 # miss rate for ReadSharedReq accesses 1397system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for demand accesses 1398system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013511 # miss rate for demand accesses 1399system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056015 # miss rate for demand accesses 1400system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.204031 # miss rate for demand accesses 1401system.cpu0.l2cache.demand_miss_rate::total 0.108939 # miss rate for demand accesses 1402system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for overall accesses 1403system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013511 # miss rate for overall accesses 1404system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056015 # miss rate for overall accesses 1405system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.204031 # miss rate for overall accesses 1406system.cpu0.l2cache.overall_miss_rate::total 0.108939 # miss rate for overall accesses 1407system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average ReadReq miss latency 1408system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23402.500000 # average ReadReq miss latency 1409system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.890110 # average ReadReq miss latency 1410system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 682.818159 # average UpgradeReq miss latency 1411system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 682.818159 # average UpgradeReq miss latency 1412system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 479.378643 # average SCUpgradeReq miss latency 1413system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 479.378643 # average SCUpgradeReq miss latency 1414system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 424500 # average SCUpgradeFailReq miss latency 1415system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 424500 # average SCUpgradeFailReq miss latency 1416system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69326.459810 # average ReadExReq miss latency 1417system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69326.459810 # average ReadExReq miss latency 1418system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53059.685684 # average ReadCleanReq miss latency 1419system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53059.685684 # average ReadCleanReq miss latency 1420system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32525.365409 # average ReadSharedReq miss latency 1421system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32525.365409 # average ReadSharedReq miss latency 1422system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average overall miss latency 1423system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23402.500000 # average overall miss latency 1424system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53059.685684 # average overall miss latency 1425system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44048.902438 # average overall miss latency 1426system.cpu0.l2cache.demand_avg_miss_latency::total 46778.686527 # average overall miss latency 1427system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average overall miss latency 1428system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23402.500000 # average overall miss latency 1429system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53059.685684 # average overall miss latency 1430system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44048.902438 # average overall miss latency 1431system.cpu0.l2cache.overall_avg_miss_latency::total 46778.686527 # average overall miss latency 1432system.cpu0.l2cache.blocked_cycles::no_mshrs 192 # number of cycles access was blocked |
| 1414system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1433system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1415system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked | 1434system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked |
| 1416system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1435system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1417system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 28.714286 # average number of cycles each access was blocked | 1436system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked |
| 1418system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1437system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1419system.cpu0.l2cache.unused_prefetches 10601 # number of HardPF blocks evicted w/o reference 1420system.cpu0.l2cache.writebacks::writebacks 229825 # number of writebacks 1421system.cpu0.l2cache.writebacks::total 229825 # number of writebacks 1422system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1423system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits | 1438system.cpu0.l2cache.unused_prefetches 10583 # number of HardPF blocks evicted w/o reference 1439system.cpu0.l2cache.writebacks::writebacks 229428 # number of writebacks 1440system.cpu0.l2cache.writebacks::total 229428 # number of writebacks 1441system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits 1442system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits |
| 1424system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits | 1443system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits |
| 1425system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5836 # number of ReadExReq MSHR hits 1426system.cpu0.l2cache.ReadExReq_mshr_hits::total 5836 # number of ReadExReq MSHR hits 1427system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 40 # number of ReadCleanReq MSHR hits 1428system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 40 # number of ReadCleanReq MSHR hits 1429system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 788 # number of ReadSharedReq MSHR hits 1430system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 788 # number of ReadSharedReq MSHR hits 1431system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1432system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 1433system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 40 # number of demand (read+write) MSHR hits 1434system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6624 # number of demand (read+write) MSHR hits 1435system.cpu0.l2cache.demand_mshr_hits::total 6668 # number of demand (read+write) MSHR hits 1436system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1437system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 1438system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 40 # number of overall MSHR hits 1439system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6624 # number of overall MSHR hits 1440system.cpu0.l2cache.overall_mshr_hits::total 6668 # number of overall MSHR hits 1441system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 513 # number of ReadReq MSHR misses 1442system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 206 # number of ReadReq MSHR misses 1443system.cpu0.l2cache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses 1444system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of HardPFReq MSHR misses 1445system.cpu0.l2cache.HardPFReq_mshr_misses::total 262614 # number of HardPFReq MSHR misses 1446system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55801 # number of UpgradeReq MSHR misses 1447system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55801 # number of UpgradeReq MSHR misses 1448system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20257 # number of SCUpgradeReq MSHR misses 1449system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20257 # number of SCUpgradeReq MSHR misses 1450system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43037 # number of ReadExReq MSHR misses 1451system.cpu0.l2cache.ReadExReq_mshr_misses::total 43037 # number of ReadExReq MSHR misses 1452system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70520 # number of ReadCleanReq MSHR misses 1453system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70520 # number of ReadCleanReq MSHR misses 1454system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106710 # number of ReadSharedReq MSHR misses 1455system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106710 # number of ReadSharedReq MSHR misses 1456system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 513 # number of demand (read+write) MSHR misses 1457system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 206 # number of demand (read+write) MSHR misses 1458system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70520 # number of demand (read+write) MSHR misses 1459system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149747 # number of demand (read+write) MSHR misses 1460system.cpu0.l2cache.demand_mshr_misses::total 220986 # number of demand (read+write) MSHR misses 1461system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 513 # number of overall MSHR misses 1462system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 206 # number of overall MSHR misses 1463system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70520 # number of overall MSHR misses 1464system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149747 # number of overall MSHR misses 1465system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of overall MSHR misses 1466system.cpu0.l2cache.overall_mshr_misses::total 483600 # number of overall MSHR misses | 1444system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5884 # number of ReadExReq MSHR hits 1445system.cpu0.l2cache.ReadExReq_mshr_hits::total 5884 # number of ReadExReq MSHR hits 1446system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 42 # number of ReadCleanReq MSHR hits 1447system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 42 # number of ReadCleanReq MSHR hits 1448system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 782 # number of ReadSharedReq MSHR hits 1449system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 782 # number of ReadSharedReq MSHR hits 1450system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits 1451system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits 1452system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits 1453system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6666 # number of demand (read+write) MSHR hits 1454system.cpu0.l2cache.demand_mshr_hits::total 6712 # number of demand (read+write) MSHR hits 1455system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits 1456system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits 1457system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 42 # number of overall MSHR hits 1458system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6666 # number of overall MSHR hits 1459system.cpu0.l2cache.overall_mshr_hits::total 6712 # number of overall MSHR hits 1460system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 526 # number of ReadReq MSHR misses 1461system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 198 # number of ReadReq MSHR misses 1462system.cpu0.l2cache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses 1463system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262267 # number of HardPFReq MSHR misses 1464system.cpu0.l2cache.HardPFReq_mshr_misses::total 262267 # number of HardPFReq MSHR misses 1465system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55774 # number of UpgradeReq MSHR misses 1466system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55774 # number of UpgradeReq MSHR misses 1467system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20246 # number of SCUpgradeReq MSHR misses 1468system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20246 # number of SCUpgradeReq MSHR misses 1469system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1470system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1471system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43145 # number of ReadExReq MSHR misses 1472system.cpu0.l2cache.ReadExReq_mshr_misses::total 43145 # number of ReadExReq MSHR misses 1473system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 69824 # number of ReadCleanReq MSHR misses 1474system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 69824 # number of ReadCleanReq MSHR misses 1475system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106766 # number of ReadSharedReq MSHR misses 1476system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106766 # number of ReadSharedReq MSHR misses 1477system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 526 # number of demand (read+write) MSHR misses 1478system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 198 # number of demand (read+write) MSHR misses 1479system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69824 # number of demand (read+write) MSHR misses 1480system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149911 # number of demand (read+write) MSHR misses 1481system.cpu0.l2cache.demand_mshr_misses::total 220459 # number of demand (read+write) MSHR misses 1482system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 526 # number of overall MSHR misses 1483system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 198 # number of overall MSHR misses 1484system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69824 # number of overall MSHR misses 1485system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149911 # number of overall MSHR misses 1486system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262267 # number of overall MSHR misses 1487system.cpu0.l2cache.overall_mshr_misses::total 482726 # number of overall MSHR misses |
| 1467system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable | 1488system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable |
| 1468system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable 1469system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35016 # number of ReadReq MSHR uncacheable 1470system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable 1471system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable | 1489system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable 1490system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23585 # number of ReadReq MSHR uncacheable 1491system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable 1492system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19269 # number of WriteReq MSHR uncacheable |
| 1472system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses | 1493system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses |
| 1473system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses 1474system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63698 # number of overall MSHR uncacheable misses 1475system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of ReadReq MSHR miss cycles 1476system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3770500 # number of ReadReq MSHR miss cycles 1477system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 16512000 # number of ReadReq MSHR miss cycles 1478system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of HardPFReq MSHR miss cycles 1479system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17165691219 # number of HardPFReq MSHR miss cycles 1480system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 965407999 # number of UpgradeReq MSHR miss cycles 1481system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 965407999 # number of UpgradeReq MSHR miss cycles 1482system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 305528000 # number of SCUpgradeReq MSHR miss cycles 1483system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 305528000 # number of SCUpgradeReq MSHR miss cycles 1484system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 329500 # number of SCUpgradeFailReq MSHR miss cycles 1485system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 329500 # number of SCUpgradeFailReq MSHR miss cycles 1486system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2246676499 # number of ReadExReq MSHR miss cycles 1487system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2246676499 # number of ReadExReq MSHR miss cycles 1488system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3346200500 # number of ReadCleanReq MSHR miss cycles 1489system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3346200500 # number of ReadCleanReq MSHR miss cycles 1490system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2833954497 # number of ReadSharedReq MSHR miss cycles 1491system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2833954497 # number of ReadSharedReq MSHR miss cycles 1492system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of demand (read+write) MSHR miss cycles 1493system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3770500 # number of demand (read+write) MSHR miss cycles 1494system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3346200500 # number of demand (read+write) MSHR miss cycles 1495system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5080630996 # number of demand (read+write) MSHR miss cycles 1496system.cpu0.l2cache.demand_mshr_miss_latency::total 8443343496 # number of demand (read+write) MSHR miss cycles 1497system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of overall MSHR miss cycles 1498system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3770500 # number of overall MSHR miss cycles 1499system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3346200500 # number of overall MSHR miss cycles 1500system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5080630996 # number of overall MSHR miss cycles 1501system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of overall MSHR miss cycles 1502system.cpu0.l2cache.overall_mshr_miss_latency::total 25609034715 # number of overall MSHR miss cycles | 1494system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 1495system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42854 # number of overall MSHR uncacheable misses 1496system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of ReadReq MSHR miss cycles 1497system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3455500 # number of ReadReq MSHR miss cycles 1498system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 18241000 # number of ReadReq MSHR miss cycles 1499system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17281059402 # number of HardPFReq MSHR miss cycles 1500system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17281059402 # number of HardPFReq MSHR miss cycles 1501system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 963844000 # number of UpgradeReq MSHR miss cycles 1502system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 963844000 # number of UpgradeReq MSHR miss cycles 1503system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 306251499 # number of SCUpgradeReq MSHR miss cycles 1504system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 306251499 # number of SCUpgradeReq MSHR miss cycles 1505system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 352500 # number of SCUpgradeFailReq MSHR miss cycles 1506system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 352500 # number of SCUpgradeFailReq MSHR miss cycles 1507system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2242873000 # number of ReadExReq MSHR miss cycles 1508system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2242873000 # number of ReadExReq MSHR miss cycles 1509system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3286309500 # number of ReadCleanReq MSHR miss cycles 1510system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3286309500 # number of ReadCleanReq MSHR miss cycles 1511system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2812269499 # number of ReadSharedReq MSHR miss cycles 1512system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2812269499 # number of ReadSharedReq MSHR miss cycles 1513system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of demand (read+write) MSHR miss cycles 1514system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3455500 # number of demand (read+write) MSHR miss cycles 1515system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3286309500 # number of demand (read+write) MSHR miss cycles 1516system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5055142499 # number of demand (read+write) MSHR miss cycles 1517system.cpu0.l2cache.demand_mshr_miss_latency::total 8359692999 # number of demand (read+write) MSHR miss cycles 1518system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of overall MSHR miss cycles 1519system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3455500 # number of overall MSHR miss cycles 1520system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3286309500 # number of overall MSHR miss cycles 1521system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5055142499 # number of overall MSHR miss cycles 1522system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17281059402 # number of overall MSHR miss cycles 1523system.cpu0.l2cache.overall_mshr_miss_latency::total 25640752401 # number of overall MSHR miss cycles |
| 1503system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles | 1524system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles |
| 1504system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6425579500 # number of ReadReq MSHR uncacheable cycles 1505system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6690665500 # number of ReadReq MSHR uncacheable cycles | 1525system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4430574500 # number of ReadReq MSHR uncacheable cycles 1526system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4695660500 # number of ReadReq MSHR uncacheable cycles |
| 1506system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles | 1527system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles |
| 1507system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6425579500 # number of overall MSHR uncacheable cycles 1508system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6690665500 # number of overall MSHR uncacheable cycles 1509system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for ReadReq accesses 1510system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for ReadReq accesses 1511system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010473 # mshr miss rate for ReadReq accesses | 1528system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4430574500 # number of overall MSHR uncacheable cycles 1529system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4695660500 # number of overall MSHR uncacheable cycles 1530system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for ReadReq accesses 1531system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for ReadReq accesses 1532system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010253 # mshr miss rate for ReadReq accesses |
| 1512system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1513system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1533system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1534system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1514system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses 1515system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses | 1535system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1536system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1516system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1517system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1537system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1538system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1518system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159346 # mshr miss rate for ReadExReq accesses 1519system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159346 # mshr miss rate for ReadExReq accesses 1520system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for ReadCleanReq accesses 1521system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056423 # mshr miss rate for ReadCleanReq accesses 1522system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214489 # mshr miss rate for ReadSharedReq accesses 1523system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214489 # mshr miss rate for ReadSharedReq accesses 1524system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for demand accesses 1525system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for demand accesses 1526system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for demand accesses 1527system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for demand accesses 1528system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105933 # mshr miss rate for demand accesses 1529system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for overall accesses 1530system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for overall accesses 1531system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for overall accesses 1532system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for overall accesses | 1539system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1540system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1541system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159784 # mshr miss rate for ReadExReq accesses 1542system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159784 # mshr miss rate for ReadExReq accesses 1543system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for ReadCleanReq accesses 1544system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.055981 # mshr miss rate for ReadCleanReq accesses 1545system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214650 # mshr miss rate for ReadSharedReq accesses 1546system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214650 # mshr miss rate for ReadSharedReq accesses 1547system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for demand accesses 1548system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for demand accesses 1549system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for demand accesses 1550system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for demand accesses 1551system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105720 # mshr miss rate for demand accesses 1552system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for overall accesses 1553system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for overall accesses 1554system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for overall accesses 1555system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for overall accesses |
| 1533system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1556system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1534system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231821 # mshr miss rate for overall accesses 1535system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average ReadReq mshr miss latency 1536system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average ReadReq mshr miss latency 1537system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22965.229485 # average ReadReq mshr miss latency 1538system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average HardPFReq mshr miss latency 1539system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65364.722441 # average HardPFReq mshr miss latency 1540system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17300.908568 # average UpgradeReq mshr miss latency 1541system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300.908568 # average UpgradeReq mshr miss latency 1542system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15082.588735 # average SCUpgradeReq mshr miss latency 1543system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.588735 # average SCUpgradeReq mshr miss latency 1544system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1545system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1546system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52203.371494 # average ReadExReq mshr miss latency 1547system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52203.371494 # average ReadExReq mshr miss latency 1548system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average ReadCleanReq mshr miss latency 1549system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47450.375780 # average ReadCleanReq mshr miss latency 1550system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26557.534411 # average ReadSharedReq mshr miss latency 1551system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26557.534411 # average ReadSharedReq mshr miss latency 1552system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency 1553system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency 1554system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency 1555system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency 1556system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38207.594581 # average overall mshr miss latency 1557system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency 1558system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency 1559system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency 1560system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency 1561system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average overall mshr miss latency 1562system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52954.993207 # average overall mshr miss latency | 1557system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231489 # mshr miss rate for overall accesses 1558system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average ReadReq mshr miss latency 1559system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average ReadReq mshr miss latency 1560system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25194.751381 # average ReadReq mshr miss latency 1561system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average HardPFReq mshr miss latency 1562system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65891.093435 # average HardPFReq mshr miss latency 1563system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17281.242156 # average UpgradeReq mshr miss latency 1564system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17281.242156 # average UpgradeReq mshr miss latency 1565system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15126.518769 # average SCUpgradeReq mshr miss latency 1566system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15126.518769 # average SCUpgradeReq mshr miss latency 1567system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 352500 # average SCUpgradeFailReq mshr miss latency 1568system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 352500 # average SCUpgradeFailReq mshr miss latency 1569system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51984.540503 # average ReadExReq mshr miss latency 1570system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51984.540503 # average ReadExReq mshr miss latency 1571system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average ReadCleanReq mshr miss latency 1572system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47065.614975 # average ReadCleanReq mshr miss latency 1573system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26340.496965 # average ReadSharedReq mshr miss latency 1574system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26340.496965 # average ReadSharedReq mshr miss latency 1575system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency 1576system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency 1577system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency 1578system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency 1579system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37919.490694 # average overall mshr miss latency 1580system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency 1581system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency 1582system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency 1583system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency 1584system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average overall mshr miss latency 1585system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53116.576279 # average overall mshr miss latency |
| 1563system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency | 1586system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency |
| 1564system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200749.172082 # average ReadReq mshr uncacheable latency 1565system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191074.523075 # average ReadReq mshr uncacheable latency | 1587system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215316.834330 # average ReadReq mshr uncacheable latency 1588system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 199095.208819 # average ReadReq mshr uncacheable latency |
| 1566system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency | 1589system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency |
| 1567system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105875.424287 # average overall mshr uncacheable latency 1568system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105037.293165 # average overall mshr uncacheable latency 1569system.cpu0.toL2Bus.snoop_filter.tot_requests 4075722 # Total number of requests made to the snoop filter. 1570system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058160 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1571system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32446 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1572system.cpu0.toL2Bus.snoop_filter.tot_snoops 214641 # Total number of snoops made to the snoop filter. 1573system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212781 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1574system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1860 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1575system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1576system.cpu0.toL2Bus.trans_dist::ReadReq 113949 # Transaction distribution 1577system.cpu0.toL2Bus.trans_dist::ReadResp 1910077 # Transaction distribution 1578system.cpu0.toL2Bus.trans_dist::WriteReq 28682 # Transaction distribution 1579system.cpu0.toL2Bus.trans_dist::WriteResp 28682 # Transaction distribution 1580system.cpu0.toL2Bus.trans_dist::WritebackDirty 713807 # Transaction distribution 1581system.cpu0.toL2Bus.trans_dist::WritebackClean 1478497 # Transaction distribution 1582system.cpu0.toL2Bus.trans_dist::CleanEvict 89121 # Transaction distribution 1583system.cpu0.toL2Bus.trans_dist::HardPFReq 330731 # Transaction distribution 1584system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution 1585system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution 1586system.cpu0.toL2Bus.trans_dist::UpgradeResp 113662 # Transaction distribution 1587system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution | 1590system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111192.453446 # average overall mshr uncacheable latency 1591system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109573.447053 # average overall mshr uncacheable latency 1592system.cpu0.toL2Bus.snoop_filter.tot_requests 4070347 # Total number of requests made to the snoop filter. 1593system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2055545 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1594system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32650 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1595system.cpu0.toL2Bus.snoop_filter.tot_snoops 214495 # Total number of snoops made to the snoop filter. 1596system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1597system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1598system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1599system.cpu0.toL2Bus.trans_dist::ReadReq 104418 # Transaction distribution 1600system.cpu0.toL2Bus.trans_dist::ReadResp 1897981 # Transaction distribution 1601system.cpu0.toL2Bus.trans_dist::WriteReq 19269 # Transaction distribution 1602system.cpu0.toL2Bus.trans_dist::WriteResp 19269 # Transaction distribution 1603system.cpu0.toL2Bus.trans_dist::WritebackDirty 712665 # Transaction distribution 1604system.cpu0.toL2Bus.trans_dist::WritebackClean 1476401 # Transaction distribution 1605system.cpu0.toL2Bus.trans_dist::CleanEvict 88407 # Transaction distribution 1606system.cpu0.toL2Bus.trans_dist::HardPFReq 330099 # Transaction distribution 1607system.cpu0.toL2Bus.trans_dist::UpgradeReq 87722 # Transaction distribution 1608system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42827 # Transaction distribution 1609system.cpu0.toL2Bus.trans_dist::UpgradeResp 113743 # Transaction distribution 1610system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution |
| 1588system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution | 1611system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution |
| 1589system.cpu0.toL2Bus.trans_dist::ReadExReq 288564 # Transaction distribution 1590system.cpu0.toL2Bus.trans_dist::ReadExResp 284982 # Transaction distribution 1591system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1249890 # Transaction distribution 1592system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587175 # Transaction distribution 1593system.cpu0.toL2Bus.trans_dist::InvalidateReq 3237 # Transaction distribution | 1612system.cpu0.toL2Bus.trans_dist::ReadExReq 288516 # Transaction distribution 1613system.cpu0.toL2Bus.trans_dist::ReadExResp 284937 # Transaction distribution 1614system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1247318 # Transaction distribution 1615system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587795 # Transaction distribution 1616system.cpu0.toL2Bus.trans_dist::InvalidateReq 3260 # Transaction distribution |
| 1594system.cpu0.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution | 1617system.cpu0.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution |
| 1595system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3755087 # Packet count per connected master and slave (bytes) 1596system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2622795 # Packet count per connected master and slave (bytes) 1597system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29061 # Packet count per connected master and slave (bytes) 1598system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 118492 # Packet count per connected master and slave (bytes) 1599system.cpu0.toL2Bus.pkt_count::total 6525435 # Packet count per connected master and slave (bytes) 1600system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159995712 # Cumulative packet size per connected master and slave (bytes) 1601system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99013924 # Cumulative packet size per connected master and slave (bytes) 1602system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53112 # Cumulative packet size per connected master and slave (bytes) 1603system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 221488 # Cumulative packet size per connected master and slave (bytes) 1604system.cpu0.toL2Bus.pkt_size::total 259284236 # Cumulative packet size per connected master and slave (bytes) 1605system.cpu0.toL2Bus.snoops 927446 # Total snoops (count) 1606system.cpu0.toL2Bus.snoopTraffic 18848064 # Total snoop traffic (bytes) 1607system.cpu0.toL2Bus.snoop_fanout::samples 3052004 # Request fanout histogram 1608system.cpu0.toL2Bus.snoop_fanout::mean 0.088140 # Request fanout histogram 1609system.cpu0.toL2Bus.snoop_fanout::stdev 0.285640 # Request fanout histogram | 1618system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3747367 # Packet count per connected master and slave (bytes) 1619system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2580614 # Packet count per connected master and slave (bytes) 1620system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32197 # Packet count per connected master and slave (bytes) 1621system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119234 # Packet count per connected master and slave (bytes) 1622system.cpu0.toL2Bus.pkt_count::total 6479412 # Packet count per connected master and slave (bytes) 1623system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159666240 # Cumulative packet size per connected master and slave (bytes) 1624system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98907572 # Cumulative packet size per connected master and slave (bytes) 1625system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59212 # Cumulative packet size per connected master and slave (bytes) 1626system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223244 # Cumulative packet size per connected master and slave (bytes) 1627system.cpu0.toL2Bus.pkt_size::total 258856268 # Cumulative packet size per connected master and slave (bytes) 1628system.cpu0.toL2Bus.snoops 926807 # Total snoops (count) 1629system.cpu0.toL2Bus.snoopTraffic 18833272 # Total snoop traffic (bytes) 1630system.cpu0.toL2Bus.snoop_fanout::samples 3029449 # Request fanout histogram 1631system.cpu0.toL2Bus.snoop_fanout::mean 0.088921 # Request fanout histogram 1632system.cpu0.toL2Bus.snoop_fanout::stdev 0.286812 # Request fanout histogram |
| 1610system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1633system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1611system.cpu0.toL2Bus.snoop_fanout::0 2784861 91.25% 91.25% # Request fanout histogram 1612system.cpu0.toL2Bus.snoop_fanout::1 265283 8.69% 99.94% # Request fanout histogram 1613system.cpu0.toL2Bus.snoop_fanout::2 1860 0.06% 100.00% # Request fanout histogram | 1634system.cpu0.toL2Bus.snoop_fanout::0 2761954 91.17% 91.17% # Request fanout histogram 1635system.cpu0.toL2Bus.snoop_fanout::1 265607 8.77% 99.94% # Request fanout histogram 1636system.cpu0.toL2Bus.snoop_fanout::2 1888 0.06% 100.00% # Request fanout histogram |
| 1614system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1615system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1616system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1637system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1638system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1639system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1617system.cpu0.toL2Bus.snoop_fanout::total 3052004 # Request fanout histogram 1618system.cpu0.toL2Bus.reqLayer0.occupancy 4075635489 # Layer occupancy (ticks) | 1640system.cpu0.toL2Bus.snoop_fanout::total 3029449 # Request fanout histogram 1641system.cpu0.toL2Bus.reqLayer0.occupancy 4055747992 # Layer occupancy (ticks) |
| 1619system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1642system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1620system.cpu0.toL2Bus.snoopLayer0.occupancy 114371967 # Layer occupancy (ticks) | 1643system.cpu0.toL2Bus.snoopLayer0.occupancy 114619003 # Layer occupancy (ticks) |
| 1621system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1644system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1622system.cpu0.toL2Bus.respLayer0.occupancy 1878285609 # Layer occupancy (ticks) | 1645system.cpu0.toL2Bus.respLayer0.occupancy 1874463037 # Layer occupancy (ticks) |
| 1623system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1646system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1624system.cpu0.toL2Bus.respLayer1.occupancy 1237556949 # Layer occupancy (ticks) | 1647system.cpu0.toL2Bus.respLayer1.occupancy 1221112489 # Layer occupancy (ticks) |
| 1625system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1648system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1626system.cpu0.toL2Bus.respLayer2.occupancy 15793479 # Layer occupancy (ticks) | 1649system.cpu0.toL2Bus.respLayer2.occupancy 17401984 # Layer occupancy (ticks) |
| 1627system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1650system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1628system.cpu0.toL2Bus.respLayer3.occupancy 63149938 # Layer occupancy (ticks) | 1651system.cpu0.toL2Bus.respLayer3.occupancy 63454935 # Layer occupancy (ticks) |
| 1629system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1652system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1630system.cpu1.branchPred.lookups 4617850 # Number of BP lookups 1631system.cpu1.branchPred.condPredicted 2715513 # Number of conditional branches predicted 1632system.cpu1.branchPred.condIncorrect 269466 # Number of conditional branches incorrect 1633system.cpu1.branchPred.BTBLookups 2413279 # Number of BTB lookups 1634system.cpu1.branchPred.BTBHits 1525969 # Number of BTB hits | 1653system.cpu1.branchPred.lookups 33856624 # Number of BP lookups 1654system.cpu1.branchPred.condPredicted 11500186 # Number of conditional branches predicted 1655system.cpu1.branchPred.condIncorrect 284574 # Number of conditional branches incorrect 1656system.cpu1.branchPred.BTBLookups 18698220 # Number of BTB lookups 1657system.cpu1.branchPred.BTBHits 5965214 # Number of BTB hits |
| 1635system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1658system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1636system.cpu1.branchPred.BTBHitPct 63.232183 # BTB Hit Percentage 1637system.cpu1.branchPred.usedRAS 876806 # Number of times the RAS was used to get a target. 1638system.cpu1.branchPred.RASInCorrect 7196 # Number of incorrect RAS predictions. 1639system.cpu1.branchPred.indirectLookups 247807 # Number of indirect predictor lookups. 1640system.cpu1.branchPred.indirectHits 212871 # Number of indirect target hits. 1641system.cpu1.branchPred.indirectMisses 34936 # Number of indirect misses. 1642system.cpu1.branchPredindirectMispredicted 10588 # Number of mispredicted indirect branches. 1643system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 1659system.cpu1.branchPred.BTBHitPct 31.902577 # BTB Hit Percentage 1660system.cpu1.branchPred.usedRAS 12503434 # Number of times the RAS was used to get a target. 1661system.cpu1.branchPred.RASInCorrect 7767 # Number of incorrect RAS predictions. 1662system.cpu1.branchPred.indirectLookups 9010077 # Number of indirect predictor lookups. 1663system.cpu1.branchPred.indirectHits 8973983 # Number of indirect target hits. 1664system.cpu1.branchPred.indirectMisses 36094 # Number of indirect misses. 1665system.cpu1.branchPredindirectMispredicted 10763 # Number of mispredicted indirect branches. 1666system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 1644system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1645system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1646system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1647system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1648system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1649system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1650system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1651system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1665system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1666system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1667system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1668system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1669system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1670system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1671system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1672system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1667system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1668system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1669system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1670system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1671system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1672system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1673system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1674system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1688system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1689system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1690system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1691system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1692system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1693system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1694system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1695system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1673system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1674system.cpu1.dtb.walker.walks 21585 # Table walker walks requested 1675system.cpu1.dtb.walker.walksShort 21585 # Table walker walks initiated with short descriptors 1676system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8697 # Level at which table walker walks with short descriptors terminate 1677system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5905 # Level at which table walker walks with short descriptors terminate 1678system.cpu1.dtb.walker.walksSquashedBefore 6983 # Table walks squashed before starting 1679system.cpu1.dtb.walker.walkWaitTime::samples 14602 # Table walker wait (enqueue to first request) latency 1680system.cpu1.dtb.walker.walkWaitTime::mean 620.599918 # Table walker wait (enqueue to first request) latency 1681system.cpu1.dtb.walker.walkWaitTime::stdev 3321.361869 # Table walker wait (enqueue to first request) latency 1682system.cpu1.dtb.walker.walkWaitTime::0-4095 13932 95.41% 95.41% # Table walker wait (enqueue to first request) latency 1683system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.74% # Table walker wait (enqueue to first request) latency 1684system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.56% 98.30% # Table walker wait (enqueue to first request) latency 1685system.cpu1.dtb.walker.walkWaitTime::12288-16383 109 0.75% 99.05% # Table walker wait (enqueue to first request) latency 1686system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.21% # Table walker wait (enqueue to first request) latency 1687system.cpu1.dtb.walker.walkWaitTime::20480-24575 26 0.18% 99.39% # Table walker wait (enqueue to first request) latency 1688system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.45% # Table walker wait (enqueue to first request) latency 1689system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.89% # Table walker wait (enqueue to first request) latency 1690system.cpu1.dtb.walker.walkWaitTime::32768-36863 7 0.05% 99.94% # Table walker wait (enqueue to first request) latency 1691system.cpu1.dtb.walker.walkWaitTime::36864-40959 6 0.04% 99.98% # Table walker wait (enqueue to first request) latency 1692system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1693system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1694system.cpu1.dtb.walker.walkWaitTime::total 14602 # Table walker wait (enqueue to first request) latency 1695system.cpu1.dtb.walker.walkCompletionTime::samples 5436 # Table walker service (enqueue to completion) latency 1696system.cpu1.dtb.walker.walkCompletionTime::mean 11628.403238 # Table walker service (enqueue to completion) latency 1697system.cpu1.dtb.walker.walkCompletionTime::gmean 9929.194928 # Table walker service (enqueue to completion) latency 1698system.cpu1.dtb.walker.walkCompletionTime::stdev 8303.343609 # Table walker service (enqueue to completion) latency 1699system.cpu1.dtb.walker.walkCompletionTime::0-8191 1858 34.18% 34.18% # Table walker service (enqueue to completion) latency 1700system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2915 53.62% 87.80% # Table walker service (enqueue to completion) latency 1701system.cpu1.dtb.walker.walkCompletionTime::16384-24575 446 8.20% 96.01% # Table walker service (enqueue to completion) latency 1702system.cpu1.dtb.walker.walkCompletionTime::24576-32767 133 2.45% 98.45% # Table walker service (enqueue to completion) latency 1703system.cpu1.dtb.walker.walkCompletionTime::32768-40959 34 0.63% 99.08% # Table walker service (enqueue to completion) latency 1704system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.46% 99.54% # Table walker service (enqueue to completion) latency 1705system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.11% 99.65% # Table walker service (enqueue to completion) latency 1706system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.67% # Table walker service (enqueue to completion) latency 1707system.cpu1.dtb.walker.walkCompletionTime::98304-106495 11 0.20% 99.87% # Table walker service (enqueue to completion) latency 1708system.cpu1.dtb.walker.walkCompletionTime::106496-114687 7 0.13% 100.00% # Table walker service (enqueue to completion) latency 1709system.cpu1.dtb.walker.walkCompletionTime::total 5436 # Table walker service (enqueue to completion) latency 1710system.cpu1.dtb.walker.walksPending::samples 81885681356 # Table walker pending requests distribution 1711system.cpu1.dtb.walker.walksPending::mean 0.177146 # Table walker pending requests distribution 1712system.cpu1.dtb.walker.walksPending::stdev 0.385706 # Table walker pending requests distribution 1713system.cpu1.dtb.walker.walksPending::0 67426452132 82.34% 82.34% # Table walker pending requests distribution 1714system.cpu1.dtb.walker.walksPending::1 14437765724 17.63% 99.97% # Table walker pending requests distribution 1715system.cpu1.dtb.walker.walksPending::2 12512000 0.02% 99.99% # Table walker pending requests distribution 1716system.cpu1.dtb.walker.walksPending::3 4018500 0.00% 99.99% # Table walker pending requests distribution 1717system.cpu1.dtb.walker.walksPending::4 1336000 0.00% 100.00% # Table walker pending requests distribution 1718system.cpu1.dtb.walker.walksPending::5 984500 0.00% 100.00% # Table walker pending requests distribution 1719system.cpu1.dtb.walker.walksPending::6 1256500 0.00% 100.00% # Table walker pending requests distribution 1720system.cpu1.dtb.walker.walksPending::7 435000 0.00% 100.00% # Table walker pending requests distribution 1721system.cpu1.dtb.walker.walksPending::8 231000 0.00% 100.00% # Table walker pending requests distribution 1722system.cpu1.dtb.walker.walksPending::9 183500 0.00% 100.00% # Table walker pending requests distribution 1723system.cpu1.dtb.walker.walksPending::10 98500 0.00% 100.00% # Table walker pending requests distribution 1724system.cpu1.dtb.walker.walksPending::11 31000 0.00% 100.00% # Table walker pending requests distribution 1725system.cpu1.dtb.walker.walksPending::12 125000 0.00% 100.00% # Table walker pending requests distribution 1726system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution 1727system.cpu1.dtb.walker.walksPending::14 29500 0.00% 100.00% # Table walker pending requests distribution 1728system.cpu1.dtb.walker.walksPending::15 188500 0.00% 100.00% # Table walker pending requests distribution 1729system.cpu1.dtb.walker.walksPending::total 81885681356 # Table walker pending requests distribution 1730system.cpu1.dtb.walker.walkPageSizes::4K 1913 75.20% 75.20% # Table walker page sizes translated 1731system.cpu1.dtb.walker.walkPageSizes::1M 631 24.80% 100.00% # Table walker page sizes translated 1732system.cpu1.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated 1733system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21585 # Table walker requests started/completed, data/inst | 1696system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1697system.cpu1.dtb.walker.walks 21842 # Table walker walks requested 1698system.cpu1.dtb.walker.walksShort 21842 # Table walker walks initiated with short descriptors 1699system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8830 # Level at which table walker walks with short descriptors terminate 1700system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5887 # Level at which table walker walks with short descriptors terminate 1701system.cpu1.dtb.walker.walksSquashedBefore 7125 # Table walks squashed before starting 1702system.cpu1.dtb.walker.walkWaitTime::samples 14717 # Table walker wait (enqueue to first request) latency 1703system.cpu1.dtb.walker.walkWaitTime::mean 626.588299 # Table walker wait (enqueue to first request) latency 1704system.cpu1.dtb.walker.walkWaitTime::stdev 3443.893339 # Table walker wait (enqueue to first request) latency 1705system.cpu1.dtb.walker.walkWaitTime::0-4095 14047 95.45% 95.45% # Table walker wait (enqueue to first request) latency 1706system.cpu1.dtb.walker.walkWaitTime::4096-8191 191 1.30% 96.75% # Table walker wait (enqueue to first request) latency 1707system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.55% 98.29% # Table walker wait (enqueue to first request) latency 1708system.cpu1.dtb.walker.walkWaitTime::12288-16383 115 0.78% 99.08% # Table walker wait (enqueue to first request) latency 1709system.cpu1.dtb.walker.walkWaitTime::16384-20479 21 0.14% 99.22% # Table walker wait (enqueue to first request) latency 1710system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.16% 99.37% # Table walker wait (enqueue to first request) latency 1711system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.05% 99.42% # Table walker wait (enqueue to first request) latency 1712system.cpu1.dtb.walker.walkWaitTime::28672-32767 61 0.41% 99.84% # Table walker wait (enqueue to first request) latency 1713system.cpu1.dtb.walker.walkWaitTime::32768-36863 9 0.06% 99.90% # Table walker wait (enqueue to first request) latency 1714system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.92% # Table walker wait (enqueue to first request) latency 1715system.cpu1.dtb.walker.walkWaitTime::40960-45055 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency 1716system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1717system.cpu1.dtb.walker.walkWaitTime::57344-61439 4 0.03% 100.00% # Table walker wait (enqueue to first request) latency 1718system.cpu1.dtb.walker.walkWaitTime::total 14717 # Table walker wait (enqueue to first request) latency 1719system.cpu1.dtb.walker.walkCompletionTime::samples 5501 # Table walker service (enqueue to completion) latency 1720system.cpu1.dtb.walker.walkCompletionTime::mean 11163.061262 # Table walker service (enqueue to completion) latency 1721system.cpu1.dtb.walker.walkCompletionTime::gmean 9675.830911 # Table walker service (enqueue to completion) latency 1722system.cpu1.dtb.walker.walkCompletionTime::stdev 6263.258432 # Table walker service (enqueue to completion) latency 1723system.cpu1.dtb.walker.walkCompletionTime::0-8191 1953 35.50% 35.50% # Table walker service (enqueue to completion) latency 1724system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2904 52.79% 88.29% # Table walker service (enqueue to completion) latency 1725system.cpu1.dtb.walker.walkCompletionTime::16384-24575 452 8.22% 96.51% # Table walker service (enqueue to completion) latency 1726system.cpu1.dtb.walker.walkCompletionTime::24576-32767 149 2.71% 99.22% # Table walker service (enqueue to completion) latency 1727system.cpu1.dtb.walker.walkCompletionTime::32768-40959 15 0.27% 99.49% # Table walker service (enqueue to completion) latency 1728system.cpu1.dtb.walker.walkCompletionTime::40960-49151 22 0.40% 99.89% # Table walker service (enqueue to completion) latency 1729system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.96% # Table walker service (enqueue to completion) latency 1730system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 1731system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1732system.cpu1.dtb.walker.walkCompletionTime::total 5501 # Table walker service (enqueue to completion) latency 1733system.cpu1.dtb.walker.walksPending::samples 77610116560 # Table walker pending requests distribution 1734system.cpu1.dtb.walker.walksPending::mean 0.192083 # Table walker pending requests distribution 1735system.cpu1.dtb.walker.walksPending::stdev 0.397646 # Table walker pending requests distribution 1736system.cpu1.dtb.walker.walksPending::0 62747643816 80.85% 80.85% # Table walker pending requests distribution 1737system.cpu1.dtb.walker.walksPending::1 14840857744 19.12% 99.97% # Table walker pending requests distribution 1738system.cpu1.dtb.walker.walksPending::2 12907000 0.02% 99.99% # Table walker pending requests distribution 1739system.cpu1.dtb.walker.walksPending::3 3989500 0.01% 99.99% # Table walker pending requests distribution 1740system.cpu1.dtb.walker.walksPending::4 1311000 0.00% 100.00% # Table walker pending requests distribution 1741system.cpu1.dtb.walker.walksPending::5 947500 0.00% 100.00% # Table walker pending requests distribution 1742system.cpu1.dtb.walker.walksPending::6 1279000 0.00% 100.00% # Table walker pending requests distribution 1743system.cpu1.dtb.walker.walksPending::7 355000 0.00% 100.00% # Table walker pending requests distribution 1744system.cpu1.dtb.walker.walksPending::8 209000 0.00% 100.00% # Table walker pending requests distribution 1745system.cpu1.dtb.walker.walksPending::9 144500 0.00% 100.00% # Table walker pending requests distribution 1746system.cpu1.dtb.walker.walksPending::10 123000 0.00% 100.00% # Table walker pending requests distribution 1747system.cpu1.dtb.walker.walksPending::11 26500 0.00% 100.00% # Table walker pending requests distribution 1748system.cpu1.dtb.walker.walksPending::12 158000 0.00% 100.00% # Table walker pending requests distribution 1749system.cpu1.dtb.walker.walksPending::13 24500 0.00% 100.00% # Table walker pending requests distribution 1750system.cpu1.dtb.walker.walksPending::14 7000 0.00% 100.00% # Table walker pending requests distribution 1751system.cpu1.dtb.walker.walksPending::15 133500 0.00% 100.00% # Table walker pending requests distribution 1752system.cpu1.dtb.walker.walksPending::total 77610116560 # Table walker pending requests distribution 1753system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.26% 75.26% # Table walker page sizes translated 1754system.cpu1.dtb.walker.walkPageSizes::1M 628 24.74% 100.00% # Table walker page sizes translated 1755system.cpu1.dtb.walker.walkPageSizes::total 2538 # Table walker page sizes translated 1756system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21842 # Table walker requests started/completed, data/inst |
| 1734system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1757system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1735system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21585 # Table walker requests started/completed, data/inst 1736system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst | 1758system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21842 # Table walker requests started/completed, data/inst 1759system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2538 # Table walker requests started/completed, data/inst |
| 1737system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1760system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1738system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst 1739system.cpu1.dtb.walker.walkRequestOrigin::total 24129 # Table walker requests started/completed, data/inst | 1761system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2538 # Table walker requests started/completed, data/inst 1762system.cpu1.dtb.walker.walkRequestOrigin::total 24380 # Table walker requests started/completed, data/inst |
| 1740system.cpu1.dtb.inst_hits 0 # ITB inst hits 1741system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1763system.cpu1.dtb.inst_hits 0 # ITB inst hits 1764system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1742system.cpu1.dtb.read_hits 4154069 # DTB read hits 1743system.cpu1.dtb.read_misses 18709 # DTB read misses 1744system.cpu1.dtb.write_hits 3480708 # DTB write hits 1745system.cpu1.dtb.write_misses 2876 # DTB write misses | 1765system.cpu1.dtb.read_hits 10130559 # DTB read hits 1766system.cpu1.dtb.read_misses 18924 # DTB read misses 1767system.cpu1.dtb.write_hits 6492882 # DTB write hits 1768system.cpu1.dtb.write_misses 2918 # DTB write misses |
| 1746system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1747system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1748system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1749system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1769system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1770system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1771system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1772system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1750system.cpu1.dtb.flush_entries 1944 # Number of entries that have been flushed from TLB 1751system.cpu1.dtb.align_faults 52 # Number of TLB faults due to alignment restrictions 1752system.cpu1.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch | 1773system.cpu1.dtb.flush_entries 1948 # Number of entries that have been flushed from TLB 1774system.cpu1.dtb.align_faults 62 # Number of TLB faults due to alignment restrictions 1775system.cpu1.dtb.prefetch_faults 418 # Number of TLB faults due to prefetch |
| 1753system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1776system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1754system.cpu1.dtb.perms_faults 381 # Number of TLB faults due to permissions restrictions 1755system.cpu1.dtb.read_accesses 4172778 # DTB read accesses 1756system.cpu1.dtb.write_accesses 3483584 # DTB write accesses | 1777system.cpu1.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions 1778system.cpu1.dtb.read_accesses 10149483 # DTB read accesses 1779system.cpu1.dtb.write_accesses 6495800 # DTB write accesses |
| 1757system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1780system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1758system.cpu1.dtb.hits 7634777 # DTB hits 1759system.cpu1.dtb.misses 21585 # DTB misses 1760system.cpu1.dtb.accesses 7656362 # DTB accesses 1761system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 1781system.cpu1.dtb.hits 16623441 # DTB hits 1782system.cpu1.dtb.misses 21842 # DTB misses 1783system.cpu1.dtb.accesses 16645283 # DTB accesses 1784system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 1762system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1763system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1764system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1765system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1766system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1767system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1768system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1769system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1783system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1784system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1785system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1786system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1787system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1788system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1789system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1790system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1785system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1786system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1787system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1788system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1789system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1790system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1791system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1792system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1806system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1807system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1808system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1809system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1810system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1811system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1812system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1813system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1791system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 1792system.cpu1.itb.walker.walks 5903 # Table walker walks requested 1793system.cpu1.itb.walker.walksShort 5903 # Table walker walks initiated with short descriptors 1794system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2681 # Level at which table walker walks with short descriptors terminate 1795system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2633 # Level at which table walker walks with short descriptors terminate 1796system.cpu1.itb.walker.walksSquashedBefore 589 # Table walks squashed before starting 1797system.cpu1.itb.walker.walkWaitTime::samples 5314 # Table walker wait (enqueue to first request) latency 1798system.cpu1.itb.walker.walkWaitTime::mean 359.427926 # Table walker wait (enqueue to first request) latency 1799system.cpu1.itb.walker.walkWaitTime::stdev 2179.481540 # Table walker wait (enqueue to first request) latency 1800system.cpu1.itb.walker.walkWaitTime::0-2047 5115 96.26% 96.26% # Table walker wait (enqueue to first request) latency 1801system.cpu1.itb.walker.walkWaitTime::2048-4095 44 0.83% 97.08% # Table walker wait (enqueue to first request) latency 1802system.cpu1.itb.walker.walkWaitTime::4096-6143 38 0.72% 97.80% # Table walker wait (enqueue to first request) latency 1803system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.40% 98.19% # Table walker wait (enqueue to first request) latency 1804system.cpu1.itb.walker.walkWaitTime::8192-10239 22 0.41% 98.61% # Table walker wait (enqueue to first request) latency 1805system.cpu1.itb.walker.walkWaitTime::10240-12287 26 0.49% 99.10% # Table walker wait (enqueue to first request) latency 1806system.cpu1.itb.walker.walkWaitTime::12288-14335 16 0.30% 99.40% # Table walker wait (enqueue to first request) latency 1807system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.09% 99.49% # Table walker wait (enqueue to first request) latency 1808system.cpu1.itb.walker.walkWaitTime::16384-18431 7 0.13% 99.62% # Table walker wait (enqueue to first request) latency 1809system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.06% 99.68% # Table walker wait (enqueue to first request) latency 1810system.cpu1.itb.walker.walkWaitTime::20480-22527 3 0.06% 99.74% # Table walker wait (enqueue to first request) latency 1811system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.08% 99.81% # Table walker wait (enqueue to first request) latency 1812system.cpu1.itb.walker.walkWaitTime::24576-26623 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency 1813system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.08% 99.98% # Table walker wait (enqueue to first request) latency 1814system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1815system.cpu1.itb.walker.walkWaitTime::total 5314 # Table walker wait (enqueue to first request) latency 1816system.cpu1.itb.walker.walkCompletionTime::samples 1751 # Table walker service (enqueue to completion) latency 1817system.cpu1.itb.walker.walkCompletionTime::mean 12219.588806 # Table walker service (enqueue to completion) latency 1818system.cpu1.itb.walker.walkCompletionTime::gmean 11149.776616 # Table walker service (enqueue to completion) latency 1819system.cpu1.itb.walker.walkCompletionTime::stdev 5813.276337 # Table walker service (enqueue to completion) latency 1820system.cpu1.itb.walker.walkCompletionTime::0-8191 298 17.02% 17.02% # Table walker service (enqueue to completion) latency 1821system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 71.96% 88.98% # Table walker service (enqueue to completion) latency 1822system.cpu1.itb.walker.walkCompletionTime::16384-24575 107 6.11% 95.09% # Table walker service (enqueue to completion) latency 1823system.cpu1.itb.walker.walkCompletionTime::24576-32767 68 3.88% 98.97% # Table walker service (enqueue to completion) latency 1824system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.46% 99.43% # Table walker service (enqueue to completion) latency 1825system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.29% 99.71% # Table walker service (enqueue to completion) latency 1826system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.89% # Table walker service (enqueue to completion) latency 1827system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.06% 99.94% # Table walker service (enqueue to completion) latency | 1814system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 1815system.cpu1.itb.walker.walks 6562 # Table walker walks requested 1816system.cpu1.itb.walker.walksShort 6562 # Table walker walks initiated with short descriptors 1817system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2897 # Level at which table walker walks with short descriptors terminate 1818system.cpu1.itb.walker.walksShortTerminationLevel::Level2 3033 # Level at which table walker walks with short descriptors terminate 1819system.cpu1.itb.walker.walksSquashedBefore 632 # Table walks squashed before starting 1820system.cpu1.itb.walker.walkWaitTime::samples 5930 # Table walker wait (enqueue to first request) latency 1821system.cpu1.itb.walker.walkWaitTime::mean 575.716695 # Table walker wait (enqueue to first request) latency 1822system.cpu1.itb.walker.walkWaitTime::stdev 2785.933852 # Table walker wait (enqueue to first request) latency 1823system.cpu1.itb.walker.walkWaitTime::0-4095 5654 95.35% 95.35% # Table walker wait (enqueue to first request) latency 1824system.cpu1.itb.walker.walkWaitTime::4096-8191 104 1.75% 97.10% # Table walker wait (enqueue to first request) latency 1825system.cpu1.itb.walker.walkWaitTime::8192-12287 84 1.42% 98.52% # Table walker wait (enqueue to first request) latency 1826system.cpu1.itb.walker.walkWaitTime::12288-16383 46 0.78% 99.29% # Table walker wait (enqueue to first request) latency 1827system.cpu1.itb.walker.walkWaitTime::16384-20479 13 0.22% 99.51% # Table walker wait (enqueue to first request) latency 1828system.cpu1.itb.walker.walkWaitTime::20480-24575 9 0.15% 99.66% # Table walker wait (enqueue to first request) latency 1829system.cpu1.itb.walker.walkWaitTime::24576-28671 14 0.24% 99.90% # Table walker wait (enqueue to first request) latency 1830system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency 1831system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency 1832system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1833system.cpu1.itb.walker.walkWaitTime::total 5930 # Table walker wait (enqueue to first request) latency 1834system.cpu1.itb.walker.walkCompletionTime::samples 1787 # Table walker service (enqueue to completion) latency 1835system.cpu1.itb.walker.walkCompletionTime::mean 12039.171796 # Table walker service (enqueue to completion) latency 1836system.cpu1.itb.walker.walkCompletionTime::gmean 10885.386949 # Table walker service (enqueue to completion) latency 1837system.cpu1.itb.walker.walkCompletionTime::stdev 5807.969289 # Table walker service (enqueue to completion) latency 1838system.cpu1.itb.walker.walkCompletionTime::0-8191 326 18.24% 18.24% # Table walker service (enqueue to completion) latency 1839system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 70.51% 88.75% # Table walker service (enqueue to completion) latency 1840system.cpu1.itb.walker.walkCompletionTime::16384-24575 112 6.27% 95.02% # Table walker service (enqueue to completion) latency 1841system.cpu1.itb.walker.walkCompletionTime::24576-32767 73 4.09% 99.10% # Table walker service (enqueue to completion) latency 1842system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.28% 99.38% # Table walker service (enqueue to completion) latency 1843system.cpu1.itb.walker.walkCompletionTime::40960-49151 6 0.34% 99.72% # Table walker service (enqueue to completion) latency 1844system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.94% # Table walker service (enqueue to completion) latency |
| 1828system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency | 1845system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency |
| 1829system.cpu1.itb.walker.walkCompletionTime::total 1751 # Table walker service (enqueue to completion) latency 1830system.cpu1.itb.walker.walksPending::samples 17441612916 # Table walker pending requests distribution 1831system.cpu1.itb.walker.walksPending::mean 0.860137 # Table walker pending requests distribution 1832system.cpu1.itb.walker.walksPending::stdev 0.346964 # Table walker pending requests distribution 1833system.cpu1.itb.walker.walksPending::0 2440154764 13.99% 13.99% # Table walker pending requests distribution 1834system.cpu1.itb.walker.walksPending::1 15000736652 86.01% 100.00% # Table walker pending requests distribution 1835system.cpu1.itb.walker.walksPending::2 721500 0.00% 100.00% # Table walker pending requests distribution 1836system.cpu1.itb.walker.walksPending::total 17441612916 # Table walker pending requests distribution 1837system.cpu1.itb.walker.walkPageSizes::4K 992 85.37% 85.37% # Table walker page sizes translated 1838system.cpu1.itb.walker.walkPageSizes::1M 170 14.63% 100.00% # Table walker page sizes translated 1839system.cpu1.itb.walker.walkPageSizes::total 1162 # Table walker page sizes translated | 1846system.cpu1.itb.walker.walkCompletionTime::total 1787 # Table walker service (enqueue to completion) latency 1847system.cpu1.itb.walker.walksPending::samples 17460932916 # Table walker pending requests distribution 1848system.cpu1.itb.walker.walksPending::mean 0.922072 # Table walker pending requests distribution 1849system.cpu1.itb.walker.walksPending::stdev 0.268326 # Table walker pending requests distribution 1850system.cpu1.itb.walker.walksPending::0 1361890264 7.80% 7.80% # Table walker pending requests distribution 1851system.cpu1.itb.walker.walksPending::1 16097906652 92.19% 99.99% # Table walker pending requests distribution 1852system.cpu1.itb.walker.walksPending::2 1078000 0.01% 100.00% # Table walker pending requests distribution 1853system.cpu1.itb.walker.walksPending::3 58000 0.00% 100.00% # Table walker pending requests distribution 1854system.cpu1.itb.walker.walksPending::total 17460932916 # Table walker pending requests distribution 1855system.cpu1.itb.walker.walkPageSizes::4K 986 85.37% 85.37% # Table walker page sizes translated 1856system.cpu1.itb.walker.walkPageSizes::1M 169 14.63% 100.00% # Table walker page sizes translated 1857system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated |
| 1840system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1858system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1841system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5903 # Table walker requests started/completed, data/inst 1842system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5903 # Table walker requests started/completed, data/inst | 1859system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6562 # Table walker requests started/completed, data/inst 1860system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6562 # Table walker requests started/completed, data/inst |
| 1843system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1861system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1844system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1162 # Table walker requests started/completed, data/inst 1845system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1162 # Table walker requests started/completed, data/inst 1846system.cpu1.itb.walker.walkRequestOrigin::total 7065 # Table walker requests started/completed, data/inst 1847system.cpu1.itb.inst_hits 8146400 # ITB inst hits 1848system.cpu1.itb.inst_misses 5903 # ITB inst misses | 1862system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst 1863system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst 1864system.cpu1.itb.walker.walkRequestOrigin::total 7717 # Table walker requests started/completed, data/inst 1865system.cpu1.itb.inst_hits 43481037 # ITB inst hits 1866system.cpu1.itb.inst_misses 6562 # ITB inst misses |
| 1849system.cpu1.itb.read_hits 0 # DTB read hits 1850system.cpu1.itb.read_misses 0 # DTB read misses 1851system.cpu1.itb.write_hits 0 # DTB write hits 1852system.cpu1.itb.write_misses 0 # DTB write misses 1853system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1854system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1855system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1856system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1867system.cpu1.itb.read_hits 0 # DTB read hits 1868system.cpu1.itb.read_misses 0 # DTB read misses 1869system.cpu1.itb.write_hits 0 # DTB write hits 1870system.cpu1.itb.write_misses 0 # DTB write misses 1871system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1872system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1873system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1874system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1857system.cpu1.itb.flush_entries 1127 # Number of entries that have been flushed from TLB | 1875system.cpu1.itb.flush_entries 1123 # Number of entries that have been flushed from TLB |
| 1858system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1859system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1860system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1876system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1877system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1878system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1861system.cpu1.itb.perms_faults 570 # Number of TLB faults due to permissions restrictions | 1879system.cpu1.itb.perms_faults 565 # Number of TLB faults due to permissions restrictions |
| 1862system.cpu1.itb.read_accesses 0 # DTB read accesses 1863system.cpu1.itb.write_accesses 0 # DTB write accesses | 1880system.cpu1.itb.read_accesses 0 # DTB read accesses 1881system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1864system.cpu1.itb.inst_accesses 8152303 # ITB inst accesses 1865system.cpu1.itb.hits 8146400 # DTB hits 1866system.cpu1.itb.misses 5903 # DTB misses 1867system.cpu1.itb.accesses 8152303 # DTB accesses 1868system.cpu1.numPwrStateTransitions 5563 # Number of power state transitions 1869system.cpu1.pwrStateClkGateDist::samples 2782 # Distribution of time spent in the clock gated state 1870system.cpu1.pwrStateClkGateDist::mean 1009807188.625809 # Distribution of time spent in the clock gated state 1871system.cpu1.pwrStateClkGateDist::stdev 25701428342.991928 # Distribution of time spent in the clock gated state 1872system.cpu1.pwrStateClkGateDist::underflows 1977 71.06% 71.06% # Distribution of time spent in the clock gated state 1873system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.72% 99.78% # Distribution of time spent in the clock gated state 1874system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.89% # Distribution of time spent in the clock gated state | 1882system.cpu1.itb.inst_accesses 43487599 # ITB inst accesses 1883system.cpu1.itb.hits 43481037 # DTB hits 1884system.cpu1.itb.misses 6562 # DTB misses 1885system.cpu1.itb.accesses 43487599 # DTB accesses 1886system.cpu1.numPwrStateTransitions 5583 # Number of power state transitions 1887system.cpu1.pwrStateClkGateDist::samples 2792 # Distribution of time spent in the clock gated state 1888system.cpu1.pwrStateClkGateDist::mean 993380119.566619 # Distribution of time spent in the clock gated state 1889system.cpu1.pwrStateClkGateDist::stdev 25601801103.735863 # Distribution of time spent in the clock gated state 1890system.cpu1.pwrStateClkGateDist::underflows 1979 70.88% 70.88% # Distribution of time spent in the clock gated state 1891system.cpu1.pwrStateClkGateDist::1000-5e+10 809 28.98% 99.86% # Distribution of time spent in the clock gated state 1892system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state |
| 1875system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1876system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1877system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state | 1893system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1894system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1895system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state |
| 1878system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1879system.cpu1.pwrStateClkGateDist::max_value 959983958132 # Distribution of time spent in the clock gated state 1880system.cpu1.pwrStateClkGateDist::total 2782 # Distribution of time spent in the clock gated state 1881system.cpu1.pwrStateResidencyTicks::ON 17370067243 # Cumulative time (in ticks) in various power states 1882system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809283598757 # Cumulative time (in ticks) in various power states 1883system.cpu1.numCycles 34740953 # number of cpu cycles simulated | 1896system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 1897system.cpu1.pwrStateClkGateDist::max_value 959983178648 # Distribution of time spent in the clock gated state 1898system.cpu1.pwrStateClkGateDist::total 2792 # Distribution of time spent in the clock gated state 1899system.cpu1.pwrStateResidencyTicks::ON 53155264670 # Cumulative time (in ticks) in various power states 1900system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773517293830 # Cumulative time (in ticks) in various power states 1901system.cpu1.numCycles 106311330 # number of cpu cycles simulated |
| 1884system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1885system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1902system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1903system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1886system.cpu1.fetch.icacheStallCycles 8935699 # Number of cycles fetch is stalled on an Icache miss 1887system.cpu1.fetch.Insts 24503906 # Number of instructions fetch has processed 1888system.cpu1.fetch.Branches 4617850 # Number of branches that fetch encountered 1889system.cpu1.fetch.predictedBranches 2615646 # Number of branches that fetch has predicted taken 1890system.cpu1.fetch.Cycles 23842655 # Number of cycles fetch has run and was not squashing or blocked 1891system.cpu1.fetch.SquashCycles 779742 # Number of cycles fetch has spent squashing 1892system.cpu1.fetch.TlbCycles 80208 # Number of cycles fetch has spent waiting for tlb 1893system.cpu1.fetch.MiscStallCycles 31335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1894system.cpu1.fetch.PendingTrapStallCycles 166914 # Number of stall cycles due to pending traps 1895system.cpu1.fetch.PendingQuiesceStallCycles 295220 # Number of stall cycles due to pending quiesce instructions 1896system.cpu1.fetch.IcacheWaitRetryStallCycles 22708 # Number of stall cycles due to full MSHR 1897system.cpu1.fetch.CacheLines 8145254 # Number of cache lines fetched 1898system.cpu1.fetch.IcacheSquashes 111581 # Number of outstanding Icache misses that were squashed 1899system.cpu1.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed 1900system.cpu1.fetch.rateDist::samples 33764610 # Number of instructions fetched each cycle (Total) 1901system.cpu1.fetch.rateDist::mean 0.884848 # Number of instructions fetched each cycle (Total) 1902system.cpu1.fetch.rateDist::stdev 1.220160 # Number of instructions fetched each cycle (Total) | 1904system.cpu1.fetch.icacheStallCycles 10498191 # Number of cycles fetch is stalled on an Icache miss 1905system.cpu1.fetch.Insts 108665043 # Number of instructions fetch has processed 1906system.cpu1.fetch.Branches 33856624 # Number of branches that fetch encountered 1907system.cpu1.fetch.predictedBranches 27442631 # Number of branches that fetch has predicted taken 1908system.cpu1.fetch.Cycles 92291638 # Number of cycles fetch has run and was not squashing or blocked 1909system.cpu1.fetch.SquashCycles 3748932 # Number of cycles fetch has spent squashing 1910system.cpu1.fetch.TlbCycles 86712 # Number of cycles fetch has spent waiting for tlb 1911system.cpu1.fetch.MiscStallCycles 30975 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1912system.cpu1.fetch.PendingTrapStallCycles 185919 # Number of stall cycles due to pending traps 1913system.cpu1.fetch.PendingQuiesceStallCycles 298023 # Number of stall cycles due to pending quiesce instructions 1914system.cpu1.fetch.IcacheWaitRetryStallCycles 23349 # Number of stall cycles due to full MSHR 1915system.cpu1.fetch.CacheLines 43479865 # Number of cache lines fetched 1916system.cpu1.fetch.IcacheSquashes 112855 # Number of outstanding Icache misses that were squashed 1917system.cpu1.fetch.ItlbSquashes 2560 # Number of outstanding ITLB misses that were squashed 1918system.cpu1.fetch.rateDist::samples 105289273 # Number of instructions fetched each cycle (Total) 1919system.cpu1.fetch.rateDist::mean 1.278878 # Number of instructions fetched each cycle (Total) 1920system.cpu1.fetch.rateDist::stdev 1.339497 # Number of instructions fetched each cycle (Total) |
| 1903system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1921system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1904system.cpu1.fetch.rateDist::0 20042304 59.36% 59.36% # Number of instructions fetched each cycle (Total) 1905system.cpu1.fetch.rateDist::1 4827845 14.30% 73.66% # Number of instructions fetched each cycle (Total) 1906system.cpu1.fetch.rateDist::2 1634677 4.84% 78.50% # Number of instructions fetched each cycle (Total) 1907system.cpu1.fetch.rateDist::3 7259784 21.50% 100.00% # Number of instructions fetched each cycle (Total) | 1922system.cpu1.fetch.rateDist::0 48625526 46.18% 46.18% # Number of instructions fetched each cycle (Total) 1923system.cpu1.fetch.rateDist::1 13920511 13.22% 59.40% # Number of instructions fetched each cycle (Total) 1924system.cpu1.fetch.rateDist::2 7498101 7.12% 66.53% # Number of instructions fetched each cycle (Total) 1925system.cpu1.fetch.rateDist::3 35245135 33.47% 100.00% # Number of instructions fetched each cycle (Total) |
| 1908system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1909system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1910system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1926system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1927system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1928system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1911system.cpu1.fetch.rateDist::total 33764610 # Number of instructions fetched each cycle (Total) 1912system.cpu1.fetch.branchRate 0.132922 # Number of branch fetches per cycle 1913system.cpu1.fetch.rate 0.705332 # Number of inst fetches per cycle 1914system.cpu1.decode.IdleCycles 7349000 # Number of cycles decode is idle 1915system.cpu1.decode.BlockedCycles 16390631 # Number of cycles decode is blocked 1916system.cpu1.decode.RunCycles 8692861 # Number of cycles decode is running 1917system.cpu1.decode.UnblockCycles 1069281 # Number of cycles decode is unblocking 1918system.cpu1.decode.SquashCycles 262837 # Number of cycles decode is squashing 1919system.cpu1.decode.BranchResolved 706015 # Number of times decode resolved a branch 1920system.cpu1.decode.BranchMispred 129761 # Number of times decode detected a branch misprediction 1921system.cpu1.decode.DecodedInsts 23185557 # Number of instructions handled by decode 1922system.cpu1.decode.SquashedInsts 1033744 # Number of squashed instructions handled by decode 1923system.cpu1.rename.SquashCycles 262837 # Number of cycles rename is squashing 1924system.cpu1.rename.IdleCycles 8748161 # Number of cycles rename is idle 1925system.cpu1.rename.BlockCycles 2379135 # Number of cycles rename is blocking 1926system.cpu1.rename.serializeStallCycles 11360118 # count of cycles rename stalled for serializing inst 1927system.cpu1.rename.RunCycles 8342372 # Number of cycles rename is running 1928system.cpu1.rename.UnblockCycles 2671987 # Number of cycles rename is unblocking 1929system.cpu1.rename.RenamedInsts 22035257 # Number of instructions processed by rename 1930system.cpu1.rename.SquashedInsts 184232 # Number of squashed instructions processed by rename 1931system.cpu1.rename.ROBFullEvents 261771 # Number of times rename has blocked due to ROB full 1932system.cpu1.rename.IQFullEvents 36717 # Number of times rename has blocked due to IQ full 1933system.cpu1.rename.LQFullEvents 15492 # Number of times rename has blocked due to LQ full 1934system.cpu1.rename.SQFullEvents 1677749 # Number of times rename has blocked due to SQ full 1935system.cpu1.rename.RenamedOperands 21981180 # Number of destination operands rename has renamed 1936system.cpu1.rename.RenameLookups 102687971 # Number of register rename lookups that rename has made 1937system.cpu1.rename.int_rename_lookups 25443797 # Number of integer rename lookups | 1929system.cpu1.fetch.rateDist::total 105289273 # Number of instructions fetched each cycle (Total) 1930system.cpu1.fetch.branchRate 0.318467 # Number of branch fetches per cycle 1931system.cpu1.fetch.rate 1.022140 # Number of inst fetches per cycle 1932system.cpu1.decode.IdleCycles 13318727 # Number of cycles decode is idle 1933system.cpu1.decode.BlockedCycles 62566078 # Number of cycles decode is blocked 1934system.cpu1.decode.RunCycles 26583147 # Number of cycles decode is running 1935system.cpu1.decode.UnblockCycles 1076022 # Number of cycles decode is unblocking 1936system.cpu1.decode.SquashCycles 1745299 # Number of cycles decode is squashing 1937system.cpu1.decode.BranchResolved 4334852 # Number of times decode resolved a branch 1938system.cpu1.decode.BranchMispred 132018 # Number of times decode detected a branch misprediction 1939system.cpu1.decode.DecodedInsts 67655162 # Number of instructions handled by decode 1940system.cpu1.decode.SquashedInsts 1099039 # Number of squashed instructions handled by decode 1941system.cpu1.rename.SquashCycles 1745299 # Number of cycles rename is squashing 1942system.cpu1.rename.IdleCycles 17698509 # Number of cycles rename is idle 1943system.cpu1.rename.BlockCycles 2385948 # Number of cycles rename is blocking 1944system.cpu1.rename.serializeStallCycles 57515508 # count of cycles rename stalled for serializing inst 1945system.cpu1.rename.RunCycles 23258780 # Number of cycles rename is running 1946system.cpu1.rename.UnblockCycles 2685229 # Number of cycles rename is unblocking 1947system.cpu1.rename.RenamedInsts 54782270 # Number of instructions processed by rename 1948system.cpu1.rename.SquashedInsts 214949 # Number of squashed instructions processed by rename 1949system.cpu1.rename.ROBFullEvents 261715 # Number of times rename has blocked due to ROB full 1950system.cpu1.rename.IQFullEvents 37045 # Number of times rename has blocked due to IQ full 1951system.cpu1.rename.LQFullEvents 16294 # Number of times rename has blocked due to LQ full 1952system.cpu1.rename.SQFullEvents 1684754 # Number of times rename has blocked due to SQ full 1953system.cpu1.rename.RenamedOperands 54670319 # Number of destination operands rename has renamed 1954system.cpu1.rename.RenameLookups 258827504 # Number of register rename lookups that rename has made 1955system.cpu1.rename.int_rename_lookups 58243055 # Number of integer rename lookups |
| 1938system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups | 1956system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups |
| 1939system.cpu1.rename.CommittedMaps 19631101 # Number of HB maps that are committed 1940system.cpu1.rename.UndoneMaps 2350079 # Number of HB maps that are undone due to squashing 1941system.cpu1.rename.serializingInsts 398085 # count of serializing insts renamed 1942system.cpu1.rename.tempSerializingInsts 327427 # count of temporary serializing insts renamed 1943system.cpu1.rename.skidInsts 2832658 # count of insts added to the skid buffer 1944system.cpu1.memDep0.insertedLoads 4406260 # Number of loads inserted to the mem dependence unit. 1945system.cpu1.memDep0.insertedStores 3798525 # Number of stores inserted to the mem dependence unit. 1946system.cpu1.memDep0.conflictingLoads 616794 # Number of conflicting loads. 1947system.cpu1.memDep0.conflictingStores 601017 # Number of conflicting stores. 1948system.cpu1.iq.iqInstsAdded 21230855 # Number of instructions added to the IQ (excludes non-spec) 1949system.cpu1.iq.iqNonSpecInstsAdded 553061 # Number of non-speculative instructions added to the IQ 1950system.cpu1.iq.iqInstsIssued 21048993 # Number of instructions issued 1951system.cpu1.iq.iqSquashedInstsIssued 91520 # Number of squashed instructions issued 1952system.cpu1.iq.iqSquashedInstsExamined 2000545 # Number of squashed instructions iterated over during squash; mainly for profiling 1953system.cpu1.iq.iqSquashedOperandsExamined 4635811 # Number of squashed operands that are examined and possibly removed from graph 1954system.cpu1.iq.iqSquashedNonSpecRemoved 42283 # Number of squashed non-spec instructions that were removed 1955system.cpu1.iq.issued_per_cycle::samples 33764610 # Number of insts issued each cycle 1956system.cpu1.iq.issued_per_cycle::mean 0.623404 # Number of insts issued each cycle 1957system.cpu1.iq.issued_per_cycle::stdev 0.949604 # Number of insts issued each cycle | 1957system.cpu1.rename.CommittedMaps 52176795 # Number of HB maps that are committed 1958system.cpu1.rename.UndoneMaps 2493524 # Number of HB maps that are undone due to squashing 1959system.cpu1.rename.serializingInsts 1869295 # count of serializing insts renamed 1960system.cpu1.rename.tempSerializingInsts 1798183 # count of temporary serializing insts renamed 1961system.cpu1.rename.skidInsts 13052424 # count of insts added to the skid buffer 1962system.cpu1.memDep0.insertedLoads 10386014 # Number of loads inserted to the mem dependence unit. 1963system.cpu1.memDep0.insertedStores 6834101 # Number of stores inserted to the mem dependence unit. 1964system.cpu1.memDep0.conflictingLoads 620797 # Number of conflicting loads. 1965system.cpu1.memDep0.conflictingStores 744232 # Number of conflicting stores. 1966system.cpu1.iq.iqInstsAdded 53921335 # Number of instructions added to the IQ (excludes non-spec) 1967system.cpu1.iq.iqNonSpecInstsAdded 577687 # Number of non-speculative instructions added to the IQ 1968system.cpu1.iq.iqInstsIssued 53701083 # Number of instructions issued 1969system.cpu1.iq.iqSquashedInstsIssued 93984 # Number of squashed instructions issued 1970system.cpu1.iq.iqSquashedInstsExamined 3580846 # Number of squashed instructions iterated over during squash; mainly for profiling 1971system.cpu1.iq.iqSquashedOperandsExamined 5052182 # Number of squashed operands that are examined and possibly removed from graph 1972system.cpu1.iq.iqSquashedNonSpecRemoved 42977 # Number of squashed non-spec instructions that were removed 1973system.cpu1.iq.issued_per_cycle::samples 105289273 # Number of insts issued each cycle 1974system.cpu1.iq.issued_per_cycle::mean 0.510034 # Number of insts issued each cycle 1975system.cpu1.iq.issued_per_cycle::stdev 0.848273 # Number of insts issued each cycle |
| 1958system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1976system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1959system.cpu1.iq.issued_per_cycle::0 21364495 63.27% 63.27% # Number of insts issued each cycle 1960system.cpu1.iq.issued_per_cycle::1 6105280 18.08% 81.36% # Number of insts issued each cycle 1961system.cpu1.iq.issued_per_cycle::2 4197946 12.43% 93.79% # Number of insts issued each cycle 1962system.cpu1.iq.issued_per_cycle::3 1839743 5.45% 99.24% # Number of insts issued each cycle 1963system.cpu1.iq.issued_per_cycle::4 257138 0.76% 100.00% # Number of insts issued each cycle 1964system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle | 1977system.cpu1.iq.issued_per_cycle::0 72135914 68.51% 68.51% # Number of insts issued each cycle 1978system.cpu1.iq.issued_per_cycle::1 16498960 15.67% 84.18% # Number of insts issued each cycle 1979system.cpu1.iq.issued_per_cycle::2 13045494 12.39% 96.57% # Number of insts issued each cycle 1980system.cpu1.iq.issued_per_cycle::3 3324500 3.16% 99.73% # Number of insts issued each cycle 1981system.cpu1.iq.issued_per_cycle::4 284390 0.27% 100.00% # Number of insts issued each cycle 1982system.cpu1.iq.issued_per_cycle::5 15 0.00% 100.00% # Number of insts issued each cycle |
| 1965system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1966system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1967system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1968system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1969system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1970system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1983system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1984system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1985system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1986system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1987system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1988system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1971system.cpu1.iq.issued_per_cycle::total 33764610 # Number of insts issued each cycle | 1989system.cpu1.iq.issued_per_cycle::total 105289273 # Number of insts issued each cycle |
| 1972system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1990system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1973system.cpu1.iq.fu_full::IntAlu 1397917 29.28% 29.28% # attempts to use FU when none available 1974system.cpu1.iq.fu_full::IntMult 677 0.01% 29.30% # attempts to use FU when none available 1975system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.30% # attempts to use FU when none available 1976system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.30% # attempts to use FU when none available 1977system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.30% # attempts to use FU when none available 1978system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.30% # attempts to use FU when none available 1979system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.30% # attempts to use FU when none available 1980system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available 1981system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.30% # attempts to use FU when none available 1982system.cpu1.iq.fu_full::FloatMisc 0 0.00% 29.30% # attempts to use FU when none available 1983system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.30% # attempts to use FU when none available 1984system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.30% # attempts to use FU when none available 1985system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.30% # attempts to use FU when none available 1986system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.30% # attempts to use FU when none available 1987system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.30% # attempts to use FU when none available 1988system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.30% # attempts to use FU when none available 1989system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.30% # attempts to use FU when none available 1990system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.30% # attempts to use FU when none available 1991system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.30% # attempts to use FU when none available 1992system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.30% # attempts to use FU when none available 1993system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.30% # attempts to use FU when none available 1994system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.30% # attempts to use FU when none available 1995system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.30% # attempts to use FU when none available 1996system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.30% # attempts to use FU when none available 1997system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.30% # attempts to use FU when none available 1998system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.30% # attempts to use FU when none available 1999system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.30% # attempts to use FU when none available 2000system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.30% # attempts to use FU when none available 2001system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.30% # attempts to use FU when none available 2002system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available 2003system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.30% # attempts to use FU when none available 2004system.cpu1.iq.fu_full::MemRead 1598296 33.48% 62.78% # attempts to use FU when none available 2005system.cpu1.iq.fu_full::MemWrite 1774858 37.18% 99.96% # attempts to use FU when none available 2006system.cpu1.iq.fu_full::FloatMemRead 659 0.01% 99.97% # attempts to use FU when none available 2007system.cpu1.iq.fu_full::FloatMemWrite 1349 0.03% 100.00% # attempts to use FU when none available | 1991system.cpu1.iq.fu_full::IntAlu 2891632 45.26% 45.26% # attempts to use FU when none available 1992system.cpu1.iq.fu_full::IntMult 674 0.01% 45.27% # attempts to use FU when none available 1993system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.27% # attempts to use FU when none available 1994system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.27% # attempts to use FU when none available 1995system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.27% # attempts to use FU when none available 1996system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.27% # attempts to use FU when none available 1997system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.27% # attempts to use FU when none available 1998system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available 1999system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.27% # attempts to use FU when none available 2000system.cpu1.iq.fu_full::FloatMisc 0 0.00% 45.27% # attempts to use FU when none available 2001system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.27% # attempts to use FU when none available 2002system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.27% # attempts to use FU when none available 2003system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.27% # attempts to use FU when none available 2004system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.27% # attempts to use FU when none available 2005system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.27% # attempts to use FU when none available 2006system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.27% # attempts to use FU when none available 2007system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.27% # attempts to use FU when none available 2008system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.27% # attempts to use FU when none available 2009system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.27% # attempts to use FU when none available 2010system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.27% # attempts to use FU when none available 2011system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.27% # attempts to use FU when none available 2012system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.27% # attempts to use FU when none available 2013system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.27% # attempts to use FU when none available 2014system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.27% # attempts to use FU when none available 2015system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.27% # attempts to use FU when none available 2016system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.27% # attempts to use FU when none available 2017system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.27% # attempts to use FU when none available 2018system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.27% # attempts to use FU when none available 2019system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.27% # attempts to use FU when none available 2020system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available 2021system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.27% # attempts to use FU when none available 2022system.cpu1.iq.fu_full::MemRead 1660257 25.99% 71.25% # attempts to use FU when none available 2023system.cpu1.iq.fu_full::MemWrite 1834987 28.72% 99.97% # attempts to use FU when none available 2024system.cpu1.iq.fu_full::FloatMemRead 656 0.01% 99.98% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::FloatMemWrite 1067 0.02% 100.00% # attempts to use FU when none available |
| 2008system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2009system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2010system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued | 2026system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2027system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2028system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued |
| 2011system.cpu1.iq.FU_type_0::IntAlu 12978869 61.66% 61.66% # Type of FU issued 2012system.cpu1.iq.FU_type_0::IntMult 28429 0.14% 61.80% # Type of FU issued 2013system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued 2014system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.80% # Type of FU issued 2015system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued 2016system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued 2017system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued 2018system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 61.80% # Type of FU issued 2019system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued 2020system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 61.80% # Type of FU issued 2021system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued 2022system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued 2023system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued 2024system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued 2025system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued 2026system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued 2027system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued 2028system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued 2029system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued 2030system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued 2031system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued 2032system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued 2033system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued 2034system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued 2035system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued 2036system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.80% # Type of FU issued 2037system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.80% # Type of FU issued 2038system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.81% # Type of FU issued 2039system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued 2040system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued 2041system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued 2042system.cpu1.iq.FU_type_0::MemRead 4359753 20.71% 82.52% # Type of FU issued 2043system.cpu1.iq.FU_type_0::MemWrite 3676453 17.47% 99.99% # Type of FU issued 2044system.cpu1.iq.FU_type_0::FloatMemRead 718 0.00% 99.99% # Type of FU issued 2045system.cpu1.iq.FU_type_0::FloatMemWrite 1404 0.01% 100.00% # Type of FU issued | 2029system.cpu1.iq.FU_type_0::IntAlu 36615420 68.18% 68.18% # Type of FU issued 2030system.cpu1.iq.FU_type_0::IntMult 46378 0.09% 68.27% # Type of FU issued 2031system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued 2032system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.27% # Type of FU issued 2033system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued 2034system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued 2035system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued 2036system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.27% # Type of FU issued 2037system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued 2038system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 68.27% # Type of FU issued 2039system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued 2040system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued 2041system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued 2042system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued 2043system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued 2044system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued 2045system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued 2046system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued 2047system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued 2048system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued 2049system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued 2050system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued 2051system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued 2052system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued 2053system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued 2054system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued 2055system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued 2056system.cpu1.iq.FU_type_0::SimdFloatMisc 3321 0.01% 68.28% # Type of FU issued 2057system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued 2058system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued 2059system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued 2060system.cpu1.iq.FU_type_0::MemRead 10339913 19.25% 87.53% # Type of FU issued 2061system.cpu1.iq.FU_type_0::MemWrite 6693876 12.47% 100.00% # Type of FU issued 2062system.cpu1.iq.FU_type_0::FloatMemRead 720 0.00% 100.00% # Type of FU issued 2063system.cpu1.iq.FU_type_0::FloatMemWrite 1389 0.00% 100.00% # Type of FU issued |
| 2046system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2047system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2064system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2065system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2048system.cpu1.iq.FU_type_0::total 21048993 # Type of FU issued 2049system.cpu1.iq.rate 0.605884 # Inst issue rate 2050system.cpu1.iq.fu_busy_cnt 4773756 # FU busy when requested 2051system.cpu1.iq.fu_busy_rate 0.226793 # FU busy rate (busy events/executed inst) 2052system.cpu1.iq.int_inst_queue_reads 80721609 # Number of integer instruction queue reads 2053system.cpu1.iq.int_inst_queue_writes 23791762 # Number of integer instruction queue writes 2054system.cpu1.iq.int_inst_queue_wakeup_accesses 20591914 # Number of integer instruction queue wakeup accesses 2055system.cpu1.iq.fp_inst_queue_reads 6263 # Number of floating instruction queue reads 2056system.cpu1.iq.fp_inst_queue_writes 2082 # Number of floating instruction queue writes | 2066system.cpu1.iq.FU_type_0::total 53701083 # Type of FU issued 2067system.cpu1.iq.rate 0.505130 # Inst issue rate 2068system.cpu1.iq.fu_busy_cnt 6389273 # FU busy when requested 2069system.cpu1.iq.fu_busy_rate 0.118978 # FU busy rate (busy events/executed inst) 2070system.cpu1.iq.int_inst_queue_reads 219168744 # Number of integer instruction queue reads 2071system.cpu1.iq.int_inst_queue_writes 58087331 # Number of integer instruction queue writes 2072system.cpu1.iq.int_inst_queue_wakeup_accesses 51738316 # Number of integer instruction queue wakeup accesses 2073system.cpu1.iq.fp_inst_queue_reads 5952 # Number of floating instruction queue reads 2074system.cpu1.iq.fp_inst_queue_writes 2080 # Number of floating instruction queue writes |
| 2057system.cpu1.iq.fp_inst_queue_wakeup_accesses 1787 # Number of floating instruction queue wakeup accesses | 2075system.cpu1.iq.fp_inst_queue_wakeup_accesses 1787 # Number of floating instruction queue wakeup accesses |
| 2058system.cpu1.iq.int_alu_accesses 25818553 # Number of integer alu accesses 2059system.cpu1.iq.fp_alu_accesses 4130 # Number of floating point alu accesses 2060system.cpu1.iew.lsq.thread0.forwLoads 87577 # Number of loads that had data forwarded from stores | 2076system.cpu1.iq.int_alu_accesses 60086458 # Number of integer alu accesses 2077system.cpu1.iq.fp_alu_accesses 3832 # Number of floating point alu accesses 2078system.cpu1.iew.lsq.thread0.forwLoads 90387 # Number of loads that had data forwarded from stores |
| 2061system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2079system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2062system.cpu1.iew.lsq.thread0.squashedLoads 404936 # Number of loads squashed 2063system.cpu1.iew.lsq.thread0.ignoredResponses 702 # Number of memory responses ignored because the instruction is squashed 2064system.cpu1.iew.lsq.thread0.memOrderViolation 9416 # Number of memory ordering violations 2065system.cpu1.iew.lsq.thread0.squashedStores 250549 # Number of stores squashed | 2080system.cpu1.iew.lsq.thread0.squashedLoads 431562 # Number of loads squashed 2081system.cpu1.iew.lsq.thread0.ignoredResponses 735 # Number of memory responses ignored because the instruction is squashed 2082system.cpu1.iew.lsq.thread0.memOrderViolation 9576 # Number of memory ordering violations 2083system.cpu1.iew.lsq.thread0.squashedStores 270603 # Number of stores squashed |
| 2066system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2067system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2084system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2085system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2068system.cpu1.iew.lsq.thread0.rescheduledLoads 40531 # Number of loads that were rescheduled 2069system.cpu1.iew.lsq.thread0.cacheBlocked 75671 # Number of times an access to memory failed due to the cache being blocked | 2086system.cpu1.iew.lsq.thread0.rescheduledLoads 51945 # Number of loads that were rescheduled 2087system.cpu1.iew.lsq.thread0.cacheBlocked 76138 # Number of times an access to memory failed due to the cache being blocked |
| 2070system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2088system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2071system.cpu1.iew.iewSquashCycles 262837 # Number of cycles IEW is squashing 2072system.cpu1.iew.iewBlockCycles 524383 # Number of cycles IEW is blocking 2073system.cpu1.iew.iewUnblockCycles 105080 # Number of cycles IEW is unblocking 2074system.cpu1.iew.iewDispatchedInsts 21825012 # Number of instructions dispatched to IQ | 2089system.cpu1.iew.iewSquashCycles 1745299 # Number of cycles IEW is squashing 2090system.cpu1.iew.iewBlockCycles 526771 # Number of cycles IEW is blocking 2091system.cpu1.iew.iewUnblockCycles 105542 # Number of cycles IEW is unblocking 2092system.cpu1.iew.iewDispatchedInsts 54540026 # Number of instructions dispatched to IQ |
| 2075system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 2093system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 2076system.cpu1.iew.iewDispLoadInsts 4406260 # Number of dispatched load instructions 2077system.cpu1.iew.iewDispStoreInsts 3798525 # Number of dispatched store instructions 2078system.cpu1.iew.iewDispNonSpecInsts 290384 # Number of dispatched non-speculative instructions 2079system.cpu1.iew.iewIQFullEvents 7837 # Number of times the IQ has become full, causing a stall 2080system.cpu1.iew.iewLSQFullEvents 90528 # Number of times the LSQ has become full, causing a stall 2081system.cpu1.iew.memOrderViolationEvents 9416 # Number of memory order violations 2082system.cpu1.iew.predictedTakenIncorrect 33554 # Number of branches that were predicted taken incorrectly 2083system.cpu1.iew.predictedNotTakenIncorrect 119405 # Number of branches that were predicted not taken incorrectly 2084system.cpu1.iew.branchMispredicts 152959 # Number of branch mispredicts detected at execute 2085system.cpu1.iew.iewExecutedInsts 20820702 # Number of executed instructions 2086system.cpu1.iew.iewExecLoadInsts 4265911 # Number of load instructions executed 2087system.cpu1.iew.iewExecSquashedInsts 206727 # Number of squashed instructions skipped in execute | 2094system.cpu1.iew.iewDispLoadInsts 10386014 # Number of dispatched load instructions 2095system.cpu1.iew.iewDispStoreInsts 6834101 # Number of dispatched store instructions 2096system.cpu1.iew.iewDispNonSpecInsts 292206 # Number of dispatched non-speculative instructions 2097system.cpu1.iew.iewIQFullEvents 7827 # Number of times the IQ has become full, causing a stall 2098system.cpu1.iew.iewLSQFullEvents 90888 # Number of times the LSQ has become full, causing a stall 2099system.cpu1.iew.memOrderViolationEvents 9576 # Number of memory order violations 2100system.cpu1.iew.predictedTakenIncorrect 43509 # Number of branches that were predicted taken incorrectly 2101system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly 2102system.cpu1.iew.branchMispredicts 166283 # Number of branch mispredicts detected at execute 2103system.cpu1.iew.iewExecutedInsts 53458422 # Number of executed instructions 2104system.cpu1.iew.iewExecLoadInsts 10243364 # Number of load instructions executed 2105system.cpu1.iew.iewExecSquashedInsts 220834 # Number of squashed instructions skipped in execute |
| 2088system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2106system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2089system.cpu1.iew.exec_nop 41096 # number of nop insts executed 2090system.cpu1.iew.exec_refs 7893380 # number of memory reference insts executed 2091system.cpu1.iew.exec_branches 3012609 # Number of branches executed 2092system.cpu1.iew.exec_stores 3627469 # Number of stores executed 2093system.cpu1.iew.exec_rate 0.599313 # Inst execution rate 2094system.cpu1.iew.wb_sent 20691409 # cumulative count of insts sent to commit 2095system.cpu1.iew.wb_count 20593701 # cumulative count of insts written-back 2096system.cpu1.iew.wb_producers 10296891 # num instructions producing a value 2097system.cpu1.iew.wb_consumers 16154886 # num instructions consuming a value 2098system.cpu1.iew.wb_rate 0.592779 # insts written-back per cycle 2099system.cpu1.iew.wb_fanout 0.637386 # average fanout of values written-back 2100system.cpu1.commit.commitSquashedInsts 1790740 # The number of squashed insts skipped by commit 2101system.cpu1.commit.commitNonSpecStalls 510778 # The number of times commit has been forced to stall to communicate backwards 2102system.cpu1.commit.branchMispredicts 142432 # The number of times a branch was mispredicted 2103system.cpu1.commit.committed_per_cycle::samples 33360276 # Number of insts commited each cycle 2104system.cpu1.commit.committed_per_cycle::mean 0.594007 # Number of insts commited each cycle 2105system.cpu1.commit.committed_per_cycle::stdev 1.352197 # Number of insts commited each cycle | 2107system.cpu1.iew.exec_nop 41004 # number of nop insts executed 2108system.cpu1.iew.exec_refs 16887479 # number of memory reference insts executed 2109system.cpu1.iew.exec_branches 11797622 # Number of branches executed 2110system.cpu1.iew.exec_stores 6644115 # Number of stores executed 2111system.cpu1.iew.exec_rate 0.502848 # Inst execution rate 2112system.cpu1.iew.wb_sent 53318700 # cumulative count of insts sent to commit 2113system.cpu1.iew.wb_count 51740103 # cumulative count of insts written-back 2114system.cpu1.iew.wb_producers 25143993 # num instructions producing a value 2115system.cpu1.iew.wb_consumers 38375917 # num instructions consuming a value 2116system.cpu1.iew.wb_rate 0.486685 # insts written-back per cycle 2117system.cpu1.iew.wb_fanout 0.655202 # average fanout of values written-back 2118system.cpu1.commit.commitSquashedInsts 3338971 # The number of squashed insts skipped by commit 2119system.cpu1.commit.commitNonSpecStalls 534710 # The number of times commit has been forced to stall to communicate backwards 2120system.cpu1.commit.branchMispredicts 155407 # The number of times a branch was mispredicted 2121system.cpu1.commit.committed_per_cycle::samples 103400366 # Number of insts commited each cycle 2122system.cpu1.commit.committed_per_cycle::mean 0.492755 # Number of insts commited each cycle 2123system.cpu1.commit.committed_per_cycle::stdev 1.151487 # Number of insts commited each cycle |
| 2106system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2124system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2107system.cpu1.commit.committed_per_cycle::0 23884731 71.60% 71.60% # Number of insts commited each cycle 2108system.cpu1.commit.committed_per_cycle::1 5569703 16.70% 88.29% # Number of insts commited each cycle 2109system.cpu1.commit.committed_per_cycle::2 1678289 5.03% 93.32% # Number of insts commited each cycle 2110system.cpu1.commit.committed_per_cycle::3 665043 1.99% 95.32% # Number of insts commited each cycle 2111system.cpu1.commit.committed_per_cycle::4 510124 1.53% 96.85% # Number of insts commited each cycle 2112system.cpu1.commit.committed_per_cycle::5 336609 1.01% 97.85% # Number of insts commited each cycle 2113system.cpu1.commit.committed_per_cycle::6 218533 0.66% 98.51% # Number of insts commited each cycle 2114system.cpu1.commit.committed_per_cycle::7 117875 0.35% 98.86% # Number of insts commited each cycle 2115system.cpu1.commit.committed_per_cycle::8 379369 1.14% 100.00% # Number of insts commited each cycle | 2125system.cpu1.commit.committed_per_cycle::0 77772385 75.21% 75.21% # Number of insts commited each cycle 2126system.cpu1.commit.committed_per_cycle::1 14344116 13.87% 89.09% # Number of insts commited each cycle 2127system.cpu1.commit.committed_per_cycle::2 6076791 5.88% 94.96% # Number of insts commited each cycle 2128system.cpu1.commit.committed_per_cycle::3 698306 0.68% 95.64% # Number of insts commited each cycle 2129system.cpu1.commit.committed_per_cycle::4 1980317 1.92% 97.55% # Number of insts commited each cycle 2130system.cpu1.commit.committed_per_cycle::5 1651720 1.60% 99.15% # Number of insts commited each cycle 2131system.cpu1.commit.committed_per_cycle::6 355943 0.34% 99.50% # Number of insts commited each cycle 2132system.cpu1.commit.committed_per_cycle::7 123415 0.12% 99.62% # Number of insts commited each cycle 2133system.cpu1.commit.committed_per_cycle::8 397373 0.38% 100.00% # Number of insts commited each cycle |
| 2116system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2117system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2118system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2134system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2135system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2136system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2119system.cpu1.commit.committed_per_cycle::total 33360276 # Number of insts commited each cycle 2120system.cpu1.commit.committedInsts 16156383 # Number of instructions committed 2121system.cpu1.commit.committedOps 19816226 # Number of ops (including micro ops) committed | 2137system.cpu1.commit.committed_per_cycle::total 103400366 # Number of insts commited each cycle 2138system.cpu1.commit.committedInsts 41357318 # Number of instructions committed 2139system.cpu1.commit.committedOps 50951031 # Number of ops (including micro ops) committed |
| 2122system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2140system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2123system.cpu1.commit.refs 7549300 # Number of memory references committed 2124system.cpu1.commit.loads 4001324 # Number of loads committed 2125system.cpu1.commit.membars 208499 # Number of memory barriers committed 2126system.cpu1.commit.branches 2862007 # Number of branches committed | 2141system.cpu1.commit.refs 16517950 # Number of memory references committed 2142system.cpu1.commit.loads 9954452 # Number of loads committed 2143system.cpu1.commit.membars 209769 # Number of memory barriers committed 2144system.cpu1.commit.branches 11645067 # Number of branches committed |
| 2127system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. | 2145system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. |
| 2128system.cpu1.commit.int_insts 17632180 # Number of committed integer instructions. 2129system.cpu1.commit.function_calls 461985 # Number of function calls committed. | 2146system.cpu1.commit.int_insts 45808028 # Number of committed integer instructions. 2147system.cpu1.commit.function_calls 3371132 # Number of function calls committed. |
| 2130system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 2148system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 2131system.cpu1.commit.op_class_0::IntAlu 12236255 61.75% 61.75% # Class of committed instruction 2132system.cpu1.commit.op_class_0::IntMult 27370 0.14% 61.89% # Class of committed instruction 2133system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.89% # Class of committed instruction 2134system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.89% # Class of committed instruction 2135system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.89% # Class of committed instruction 2136system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.89% # Class of committed instruction 2137system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.89% # Class of committed instruction 2138system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 61.89% # Class of committed instruction 2139system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.89% # Class of committed instruction 2140system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 61.89% # Class of committed instruction 2141system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.89% # Class of committed instruction 2142system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.89% # Class of committed instruction 2143system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.89% # Class of committed instruction 2144system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.89% # Class of committed instruction 2145system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.89% # Class of committed instruction 2146system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.89% # Class of committed instruction 2147system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.89% # Class of committed instruction 2148system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.89% # Class of committed instruction 2149system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.89% # Class of committed instruction 2150system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.89% # Class of committed instruction 2151system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.89% # Class of committed instruction 2152system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.89% # Class of committed instruction 2153system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.89% # Class of committed instruction 2154system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.89% # Class of committed instruction 2155system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.89% # Class of committed instruction 2156system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.89% # Class of committed instruction 2157system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.89% # Class of committed instruction 2158system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 61.90% # Class of committed instruction 2159system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.90% # Class of committed instruction 2160system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.90% # Class of committed instruction 2161system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.90% # Class of committed instruction 2162system.cpu1.commit.op_class_0::MemRead 4000808 20.19% 82.09% # Class of committed instruction 2163system.cpu1.commit.op_class_0::MemWrite 3546708 17.90% 99.99% # Class of committed instruction 2164system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 99.99% # Class of committed instruction 2165system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.01% 100.00% # Class of committed instruction | 2149system.cpu1.commit.op_class_0::IntAlu 34384478 67.49% 67.49% # Class of committed instruction 2150system.cpu1.commit.op_class_0::IntMult 45282 0.09% 67.57% # Class of committed instruction 2151system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction 2152system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction 2153system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction 2154system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction 2155system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction 2156system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction 2157system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction 2158system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction 2159system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction 2160system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction 2161system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction 2162system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction 2163system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction 2164system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction 2165system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction 2166system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction 2167system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction 2168system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction 2169system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction 2170system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction 2171system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction 2172system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction 2173system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction 2174system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction 2175system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction 2176system.cpu1.commit.op_class_0::SimdFloatMisc 3321 0.01% 67.58% # Class of committed instruction 2177system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction 2178system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction 2179system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction 2180system.cpu1.commit.op_class_0::MemRead 9953936 19.54% 87.12% # Class of committed instruction 2181system.cpu1.commit.op_class_0::MemWrite 6562230 12.88% 100.00% # Class of committed instruction 2182system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction 2183system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction |
| 2166system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2167system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2184system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2185system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2168system.cpu1.commit.op_class_0::total 19816226 # Class of committed instruction 2169system.cpu1.commit.bw_lim_events 379369 # number cycles where commit BW limit reached 2170system.cpu1.rob.rob_reads 53607539 # The number of ROB reads 2171system.cpu1.rob.rob_writes 43609460 # The number of ROB writes 2172system.cpu1.timesIdled 58654 # Number of times that the entire CPU went into an idle state and unscheduled itself 2173system.cpu1.idleCycles 976343 # Total number of cycles that the CPU has spent unscheduled due to idling 2174system.cpu1.quiesceCycles 5617999605 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2175system.cpu1.committedInsts 16123527 # Number of Instructions Simulated 2176system.cpu1.committedOps 19783370 # Number of Ops (including micro ops) Simulated 2177system.cpu1.cpi 2.154675 # CPI: Cycles Per Instruction 2178system.cpu1.cpi_total 2.154675 # CPI: Total CPI of All Threads 2179system.cpu1.ipc 0.464107 # IPC: Instructions Per Cycle 2180system.cpu1.ipc_total 0.464107 # IPC: Total IPC of All Threads 2181system.cpu1.int_regfile_reads 23404305 # number of integer regfile reads 2182system.cpu1.int_regfile_writes 13364979 # number of integer regfile writes 2183system.cpu1.fp_regfile_reads 1400 # number of floating regfile reads | 2186system.cpu1.commit.op_class_0::total 50951031 # Class of committed instruction 2187system.cpu1.commit.bw_lim_events 397373 # number cycles where commit BW limit reached 2188system.cpu1.rob.rob_reads 137214928 # The number of ROB reads 2189system.cpu1.rob.rob_writes 110460111 # The number of ROB writes 2190system.cpu1.timesIdled 59286 # Number of times that the entire CPU went into an idle state and unscheduled itself 2191system.cpu1.idleCycles 1022057 # Total number of cycles that the CPU has spent unscheduled due to idling 2192system.cpu1.quiesceCycles 5546467999 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2193system.cpu1.committedInsts 41324462 # Number of Instructions Simulated 2194system.cpu1.committedOps 50918175 # Number of Ops (including micro ops) Simulated 2195system.cpu1.cpi 2.572600 # CPI: Cycles Per Instruction 2196system.cpu1.cpi_total 2.572600 # CPI: Total CPI of All Threads 2197system.cpu1.ipc 0.388712 # IPC: Instructions Per Cycle 2198system.cpu1.ipc_total 0.388712 # IPC: Total IPC of All Threads 2199system.cpu1.int_regfile_reads 56077052 # number of integer regfile reads 2200system.cpu1.int_regfile_writes 35632532 # number of integer regfile writes 2201system.cpu1.fp_regfile_reads 1385 # number of floating regfile reads |
| 2184system.cpu1.fp_regfile_writes 516 # number of floating regfile writes | 2202system.cpu1.fp_regfile_writes 516 # number of floating regfile writes |
| 2185system.cpu1.cc_regfile_reads 74742517 # number of cc regfile reads 2186system.cpu1.cc_regfile_writes 6682824 # number of cc regfile writes 2187system.cpu1.misc_regfile_reads 68400417 # number of misc regfile reads 2188system.cpu1.misc_regfile_writes 381677 # number of misc regfile writes 2189system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2190system.cpu1.dcache.tags.replacements 186538 # number of replacements 2191system.cpu1.dcache.tags.tagsinuse 471.297864 # Cycle average of tags in use 2192system.cpu1.dcache.tags.total_refs 6754124 # Total number of references to valid blocks. 2193system.cpu1.dcache.tags.sampled_refs 186882 # Sample count of references to valid blocks. 2194system.cpu1.dcache.tags.avg_refs 36.141116 # Average number of references to valid blocks. 2195system.cpu1.dcache.tags.warmup_cycle 89307598000 # Cycle when the warmup percentage was hit. 2196system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.297864 # Average occupied blocks per requestor 2197system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920504 # Average percentage of cache occupancy 2198system.cpu1.dcache.tags.occ_percent::total 0.920504 # Average percentage of cache occupancy 2199system.cpu1.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id 2200system.cpu1.dcache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id 2201system.cpu1.dcache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 2202system.cpu1.dcache.tags.occ_task_id_percent::1024 0.671875 # Percentage of cache occupancy per task id 2203system.cpu1.dcache.tags.tag_accesses 14996504 # Number of tag accesses 2204system.cpu1.dcache.tags.data_accesses 14996504 # Number of data accesses 2205system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2206system.cpu1.dcache.ReadReq_hits::cpu1.data 3592307 # number of ReadReq hits 2207system.cpu1.dcache.ReadReq_hits::total 3592307 # number of ReadReq hits 2208system.cpu1.dcache.WriteReq_hits::cpu1.data 2912324 # number of WriteReq hits 2209system.cpu1.dcache.WriteReq_hits::total 2912324 # number of WriteReq hits 2210system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49253 # number of SoftPFReq hits 2211system.cpu1.dcache.SoftPFReq_hits::total 49253 # number of SoftPFReq hits 2212system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78431 # number of LoadLockedReq hits 2213system.cpu1.dcache.LoadLockedReq_hits::total 78431 # number of LoadLockedReq hits 2214system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70573 # number of StoreCondReq hits 2215system.cpu1.dcache.StoreCondReq_hits::total 70573 # number of StoreCondReq hits 2216system.cpu1.dcache.demand_hits::cpu1.data 6504631 # number of demand (read+write) hits 2217system.cpu1.dcache.demand_hits::total 6504631 # number of demand (read+write) hits 2218system.cpu1.dcache.overall_hits::cpu1.data 6553884 # number of overall hits 2219system.cpu1.dcache.overall_hits::total 6553884 # number of overall hits 2220system.cpu1.dcache.ReadReq_misses::cpu1.data 213962 # number of ReadReq misses 2221system.cpu1.dcache.ReadReq_misses::total 213962 # number of ReadReq misses 2222system.cpu1.dcache.WriteReq_misses::cpu1.data 393973 # number of WriteReq misses 2223system.cpu1.dcache.WriteReq_misses::total 393973 # number of WriteReq misses 2224system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30075 # number of SoftPFReq misses 2225system.cpu1.dcache.SoftPFReq_misses::total 30075 # number of SoftPFReq misses 2226system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18449 # number of LoadLockedReq misses 2227system.cpu1.dcache.LoadLockedReq_misses::total 18449 # number of LoadLockedReq misses 2228system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23608 # number of StoreCondReq misses 2229system.cpu1.dcache.StoreCondReq_misses::total 23608 # number of StoreCondReq misses 2230system.cpu1.dcache.demand_misses::cpu1.data 607935 # number of demand (read+write) misses 2231system.cpu1.dcache.demand_misses::total 607935 # number of demand (read+write) misses 2232system.cpu1.dcache.overall_misses::cpu1.data 638010 # number of overall misses 2233system.cpu1.dcache.overall_misses::total 638010 # number of overall misses 2234system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3561244000 # number of ReadReq miss cycles 2235system.cpu1.dcache.ReadReq_miss_latency::total 3561244000 # number of ReadReq miss cycles 2236system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10027675956 # number of WriteReq miss cycles 2237system.cpu1.dcache.WriteReq_miss_latency::total 10027675956 # number of WriteReq miss cycles 2238system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 364257500 # number of LoadLockedReq miss cycles 2239system.cpu1.dcache.LoadLockedReq_miss_latency::total 364257500 # number of LoadLockedReq miss cycles 2240system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554259000 # number of StoreCondReq miss cycles 2241system.cpu1.dcache.StoreCondReq_miss_latency::total 554259000 # number of StoreCondReq miss cycles 2242system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 434000 # number of StoreCondFailReq miss cycles 2243system.cpu1.dcache.StoreCondFailReq_miss_latency::total 434000 # number of StoreCondFailReq miss cycles 2244system.cpu1.dcache.demand_miss_latency::cpu1.data 13588919956 # number of demand (read+write) miss cycles 2245system.cpu1.dcache.demand_miss_latency::total 13588919956 # number of demand (read+write) miss cycles 2246system.cpu1.dcache.overall_miss_latency::cpu1.data 13588919956 # number of overall miss cycles 2247system.cpu1.dcache.overall_miss_latency::total 13588919956 # number of overall miss cycles 2248system.cpu1.dcache.ReadReq_accesses::cpu1.data 3806269 # number of ReadReq accesses(hits+misses) 2249system.cpu1.dcache.ReadReq_accesses::total 3806269 # number of ReadReq accesses(hits+misses) 2250system.cpu1.dcache.WriteReq_accesses::cpu1.data 3306297 # number of WriteReq accesses(hits+misses) 2251system.cpu1.dcache.WriteReq_accesses::total 3306297 # number of WriteReq accesses(hits+misses) 2252system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79328 # number of SoftPFReq accesses(hits+misses) 2253system.cpu1.dcache.SoftPFReq_accesses::total 79328 # number of SoftPFReq accesses(hits+misses) 2254system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96880 # number of LoadLockedReq accesses(hits+misses) 2255system.cpu1.dcache.LoadLockedReq_accesses::total 96880 # number of LoadLockedReq accesses(hits+misses) 2256system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94181 # number of StoreCondReq accesses(hits+misses) 2257system.cpu1.dcache.StoreCondReq_accesses::total 94181 # number of StoreCondReq accesses(hits+misses) 2258system.cpu1.dcache.demand_accesses::cpu1.data 7112566 # number of demand (read+write) accesses 2259system.cpu1.dcache.demand_accesses::total 7112566 # number of demand (read+write) accesses 2260system.cpu1.dcache.overall_accesses::cpu1.data 7191894 # number of overall (read+write) accesses 2261system.cpu1.dcache.overall_accesses::total 7191894 # number of overall (read+write) accesses 2262system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056213 # miss rate for ReadReq accesses 2263system.cpu1.dcache.ReadReq_miss_rate::total 0.056213 # miss rate for ReadReq accesses 2264system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.119158 # miss rate for WriteReq accesses 2265system.cpu1.dcache.WriteReq_miss_rate::total 0.119158 # miss rate for WriteReq accesses 2266system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379122 # miss rate for SoftPFReq accesses 2267system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379122 # miss rate for SoftPFReq accesses 2268system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190431 # miss rate for LoadLockedReq accesses 2269system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190431 # miss rate for LoadLockedReq accesses 2270system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250666 # miss rate for StoreCondReq accesses 2271system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250666 # miss rate for StoreCondReq accesses 2272system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085473 # miss rate for demand accesses 2273system.cpu1.dcache.demand_miss_rate::total 0.085473 # miss rate for demand accesses 2274system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088712 # miss rate for overall accesses 2275system.cpu1.dcache.overall_miss_rate::total 0.088712 # miss rate for overall accesses 2276system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16644.282630 # average ReadReq miss latency 2277system.cpu1.dcache.ReadReq_avg_miss_latency::total 16644.282630 # average ReadReq miss latency 2278system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25452.698423 # average WriteReq miss latency 2279system.cpu1.dcache.WriteReq_avg_miss_latency::total 25452.698423 # average WriteReq miss latency 2280system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19744.024066 # average LoadLockedReq miss latency 2281system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19744.024066 # average LoadLockedReq miss latency 2282system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23477.592342 # average StoreCondReq miss latency 2283system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23477.592342 # average StoreCondReq miss latency | 2203system.cpu1.cc_regfile_reads 190521590 # number of cc regfile reads 2204system.cpu1.cc_regfile_writes 15513949 # number of cc regfile writes 2205system.cpu1.misc_regfile_reads 212156067 # number of misc regfile reads 2206system.cpu1.misc_regfile_writes 383841 # number of misc regfile writes 2207system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2208system.cpu1.dcache.tags.replacements 187625 # number of replacements 2209system.cpu1.dcache.tags.tagsinuse 471.246001 # Cycle average of tags in use 2210system.cpu1.dcache.tags.total_refs 15706444 # Total number of references to valid blocks. 2211system.cpu1.dcache.tags.sampled_refs 187980 # Sample count of references to valid blocks. 2212system.cpu1.dcache.tags.avg_refs 83.553804 # Average number of references to valid blocks. 2213system.cpu1.dcache.tags.warmup_cycle 89314291000 # Cycle when the warmup percentage was hit. 2214system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.246001 # Average occupied blocks per requestor 2215system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920402 # Average percentage of cache occupancy 2216system.cpu1.dcache.tags.occ_percent::total 0.920402 # Average percentage of cache occupancy 2217system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 2218system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 2219system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 2220system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id 2221system.cpu1.dcache.tags.tag_accesses 32901851 # Number of tag accesses 2222system.cpu1.dcache.tags.data_accesses 32901851 # Number of data accesses 2223system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2224system.cpu1.dcache.ReadReq_hits::cpu1.data 9540637 # number of ReadReq hits 2225system.cpu1.dcache.ReadReq_hits::total 9540637 # number of ReadReq hits 2226system.cpu1.dcache.WriteReq_hits::cpu1.data 5911714 # number of WriteReq hits 2227system.cpu1.dcache.WriteReq_hits::total 5911714 # number of WriteReq hits 2228system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49749 # number of SoftPFReq hits 2229system.cpu1.dcache.SoftPFReq_hits::total 49749 # number of SoftPFReq hits 2230system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits 2231system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits 2232system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71099 # number of StoreCondReq hits 2233system.cpu1.dcache.StoreCondReq_hits::total 71099 # number of StoreCondReq hits 2234system.cpu1.dcache.demand_hits::cpu1.data 15452351 # number of demand (read+write) hits 2235system.cpu1.dcache.demand_hits::total 15452351 # number of demand (read+write) hits 2236system.cpu1.dcache.overall_hits::cpu1.data 15502100 # number of overall hits 2237system.cpu1.dcache.overall_hits::total 15502100 # number of overall hits 2238system.cpu1.dcache.ReadReq_misses::cpu1.data 214896 # number of ReadReq misses 2239system.cpu1.dcache.ReadReq_misses::total 214896 # number of ReadReq misses 2240system.cpu1.dcache.WriteReq_misses::cpu1.data 395681 # number of WriteReq misses 2241system.cpu1.dcache.WriteReq_misses::total 395681 # number of WriteReq misses 2242system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30189 # number of SoftPFReq misses 2243system.cpu1.dcache.SoftPFReq_misses::total 30189 # number of SoftPFReq misses 2244system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18483 # number of LoadLockedReq misses 2245system.cpu1.dcache.LoadLockedReq_misses::total 18483 # number of LoadLockedReq misses 2246system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23644 # number of StoreCondReq misses 2247system.cpu1.dcache.StoreCondReq_misses::total 23644 # number of StoreCondReq misses 2248system.cpu1.dcache.demand_misses::cpu1.data 610577 # number of demand (read+write) misses 2249system.cpu1.dcache.demand_misses::total 610577 # number of demand (read+write) misses 2250system.cpu1.dcache.overall_misses::cpu1.data 640766 # number of overall misses 2251system.cpu1.dcache.overall_misses::total 640766 # number of overall misses 2252system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3583570500 # number of ReadReq miss cycles 2253system.cpu1.dcache.ReadReq_miss_latency::total 3583570500 # number of ReadReq miss cycles 2254system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10071608465 # number of WriteReq miss cycles 2255system.cpu1.dcache.WriteReq_miss_latency::total 10071608465 # number of WriteReq miss cycles 2256system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363005500 # number of LoadLockedReq miss cycles 2257system.cpu1.dcache.LoadLockedReq_miss_latency::total 363005500 # number of LoadLockedReq miss cycles 2258system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554928000 # number of StoreCondReq miss cycles 2259system.cpu1.dcache.StoreCondReq_miss_latency::total 554928000 # number of StoreCondReq miss cycles 2260system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 408500 # number of StoreCondFailReq miss cycles 2261system.cpu1.dcache.StoreCondFailReq_miss_latency::total 408500 # number of StoreCondFailReq miss cycles 2262system.cpu1.dcache.demand_miss_latency::cpu1.data 13655178965 # number of demand (read+write) miss cycles 2263system.cpu1.dcache.demand_miss_latency::total 13655178965 # number of demand (read+write) miss cycles 2264system.cpu1.dcache.overall_miss_latency::cpu1.data 13655178965 # number of overall miss cycles 2265system.cpu1.dcache.overall_miss_latency::total 13655178965 # number of overall miss cycles 2266system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755533 # number of ReadReq accesses(hits+misses) 2267system.cpu1.dcache.ReadReq_accesses::total 9755533 # number of ReadReq accesses(hits+misses) 2268system.cpu1.dcache.WriteReq_accesses::cpu1.data 6307395 # number of WriteReq accesses(hits+misses) 2269system.cpu1.dcache.WriteReq_accesses::total 6307395 # number of WriteReq accesses(hits+misses) 2270system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79938 # number of SoftPFReq accesses(hits+misses) 2271system.cpu1.dcache.SoftPFReq_accesses::total 79938 # number of SoftPFReq accesses(hits+misses) 2272system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97456 # number of LoadLockedReq accesses(hits+misses) 2273system.cpu1.dcache.LoadLockedReq_accesses::total 97456 # number of LoadLockedReq accesses(hits+misses) 2274system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94743 # number of StoreCondReq accesses(hits+misses) 2275system.cpu1.dcache.StoreCondReq_accesses::total 94743 # number of StoreCondReq accesses(hits+misses) 2276system.cpu1.dcache.demand_accesses::cpu1.data 16062928 # number of demand (read+write) accesses 2277system.cpu1.dcache.demand_accesses::total 16062928 # number of demand (read+write) accesses 2278system.cpu1.dcache.overall_accesses::cpu1.data 16142866 # number of overall (read+write) accesses 2279system.cpu1.dcache.overall_accesses::total 16142866 # number of overall (read+write) accesses 2280system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022028 # miss rate for ReadReq accesses 2281system.cpu1.dcache.ReadReq_miss_rate::total 0.022028 # miss rate for ReadReq accesses 2282system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062733 # miss rate for WriteReq accesses 2283system.cpu1.dcache.WriteReq_miss_rate::total 0.062733 # miss rate for WriteReq accesses 2284system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377655 # miss rate for SoftPFReq accesses 2285system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377655 # miss rate for SoftPFReq accesses 2286system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189655 # miss rate for LoadLockedReq accesses 2287system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189655 # miss rate for LoadLockedReq accesses 2288system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249559 # miss rate for StoreCondReq accesses 2289system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249559 # miss rate for StoreCondReq accesses 2290system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038012 # miss rate for demand accesses 2291system.cpu1.dcache.demand_miss_rate::total 0.038012 # miss rate for demand accesses 2292system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039693 # miss rate for overall accesses 2293system.cpu1.dcache.overall_miss_rate::total 0.039693 # miss rate for overall accesses 2294system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16675.836218 # average ReadReq miss latency 2295system.cpu1.dcache.ReadReq_avg_miss_latency::total 16675.836218 # average ReadReq miss latency 2296system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25453.859207 # average WriteReq miss latency 2297system.cpu1.dcache.WriteReq_avg_miss_latency::total 25453.859207 # average WriteReq miss latency 2298system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19639.966456 # average LoadLockedReq miss latency 2299system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19639.966456 # average LoadLockedReq miss latency 2300system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23470.140416 # average StoreCondReq miss latency 2301system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23470.140416 # average StoreCondReq miss latency |
| 2284system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2285system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2302system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2303system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2286system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22352.586964 # average overall miss latency 2287system.cpu1.dcache.demand_avg_miss_latency::total 22352.586964 # average overall miss latency 2288system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21298.913741 # average overall miss latency 2289system.cpu1.dcache.overall_avg_miss_latency::total 21298.913741 # average overall miss latency 2290system.cpu1.dcache.blocked_cycles::no_mshrs 300 # number of cycles access was blocked 2291system.cpu1.dcache.blocked_cycles::no_targets 1464130 # number of cycles access was blocked 2292system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked 2293system.cpu1.dcache.blocked::no_targets 39463 # number of cycles access was blocked 2294system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.677419 # average number of cycles each access was blocked 2295system.cpu1.dcache.avg_blocked_cycles::no_targets 37.101335 # average number of cycles each access was blocked 2296system.cpu1.dcache.writebacks::writebacks 186538 # number of writebacks 2297system.cpu1.dcache.writebacks::total 186538 # number of writebacks 2298system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78472 # number of ReadReq MSHR hits 2299system.cpu1.dcache.ReadReq_mshr_hits::total 78472 # number of ReadReq MSHR hits 2300system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 304164 # number of WriteReq MSHR hits 2301system.cpu1.dcache.WriteReq_mshr_hits::total 304164 # number of WriteReq MSHR hits 2302system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13133 # number of LoadLockedReq MSHR hits 2303system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13133 # number of LoadLockedReq MSHR hits 2304system.cpu1.dcache.demand_mshr_hits::cpu1.data 382636 # number of demand (read+write) MSHR hits 2305system.cpu1.dcache.demand_mshr_hits::total 382636 # number of demand (read+write) MSHR hits 2306system.cpu1.dcache.overall_mshr_hits::cpu1.data 382636 # number of overall MSHR hits 2307system.cpu1.dcache.overall_mshr_hits::total 382636 # number of overall MSHR hits 2308system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 135490 # number of ReadReq MSHR misses 2309system.cpu1.dcache.ReadReq_mshr_misses::total 135490 # number of ReadReq MSHR misses 2310system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89809 # number of WriteReq MSHR misses 2311system.cpu1.dcache.WriteReq_mshr_misses::total 89809 # number of WriteReq MSHR misses 2312system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28779 # number of SoftPFReq MSHR misses 2313system.cpu1.dcache.SoftPFReq_mshr_misses::total 28779 # number of SoftPFReq MSHR misses 2314system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5316 # number of LoadLockedReq MSHR misses 2315system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5316 # number of LoadLockedReq MSHR misses 2316system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23608 # number of StoreCondReq MSHR misses 2317system.cpu1.dcache.StoreCondReq_mshr_misses::total 23608 # number of StoreCondReq MSHR misses 2318system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses 2319system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses 2320system.cpu1.dcache.overall_mshr_misses::cpu1.data 254078 # number of overall MSHR misses 2321system.cpu1.dcache.overall_mshr_misses::total 254078 # number of overall MSHR misses 2322system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable 2323system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2880 # number of ReadReq MSHR uncacheable 2324system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable 2325system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable 2326system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses 2327system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5110 # number of overall MSHR uncacheable misses 2328system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973019500 # number of ReadReq MSHR miss cycles 2329system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1973019500 # number of ReadReq MSHR miss cycles 2330system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2438757966 # number of WriteReq MSHR miss cycles 2331system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2438757966 # number of WriteReq MSHR miss cycles 2332system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 489881500 # number of SoftPFReq MSHR miss cycles 2333system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 489881500 # number of SoftPFReq MSHR miss cycles 2334system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95317000 # number of LoadLockedReq MSHR miss cycles 2335system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95317000 # number of LoadLockedReq MSHR miss cycles 2336system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 530661000 # number of StoreCondReq MSHR miss cycles 2337system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 530661000 # number of StoreCondReq MSHR miss cycles 2338system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 424000 # number of StoreCondFailReq MSHR miss cycles 2339system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 424000 # number of StoreCondFailReq MSHR miss cycles 2340system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4411777466 # number of demand (read+write) MSHR miss cycles 2341system.cpu1.dcache.demand_mshr_miss_latency::total 4411777466 # number of demand (read+write) MSHR miss cycles 2342system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4901658966 # number of overall MSHR miss cycles 2343system.cpu1.dcache.overall_mshr_miss_latency::total 4901658966 # number of overall MSHR miss cycles 2344system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 386538000 # number of ReadReq MSHR uncacheable cycles 2345system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 386538000 # number of ReadReq MSHR uncacheable cycles 2346system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 386538000 # number of overall MSHR uncacheable cycles 2347system.cpu1.dcache.overall_mshr_uncacheable_latency::total 386538000 # number of overall MSHR uncacheable cycles 2348system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035597 # mshr miss rate for ReadReq accesses 2349system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035597 # mshr miss rate for ReadReq accesses 2350system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027163 # mshr miss rate for WriteReq accesses 2351system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027163 # mshr miss rate for WriteReq accesses 2352system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362785 # mshr miss rate for SoftPFReq accesses 2353system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362785 # mshr miss rate for SoftPFReq accesses 2354system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054872 # mshr miss rate for LoadLockedReq accesses 2355system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054872 # mshr miss rate for LoadLockedReq accesses 2356system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250666 # mshr miss rate for StoreCondReq accesses 2357system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250666 # mshr miss rate for StoreCondReq accesses 2358system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031676 # mshr miss rate for demand accesses 2359system.cpu1.dcache.demand_mshr_miss_rate::total 0.031676 # mshr miss rate for demand accesses 2360system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035328 # mshr miss rate for overall accesses 2361system.cpu1.dcache.overall_mshr_miss_rate::total 0.035328 # mshr miss rate for overall accesses 2362system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.104214 # average ReadReq mshr miss latency 2363system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14562.104214 # average ReadReq mshr miss latency 2364system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27154.939549 # average WriteReq mshr miss latency 2365system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27154.939549 # average WriteReq mshr miss latency 2366system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17022.186316 # average SoftPFReq mshr miss latency 2367system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17022.186316 # average SoftPFReq mshr miss latency 2368system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17930.210685 # average LoadLockedReq mshr miss latency 2369system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17930.210685 # average LoadLockedReq mshr miss latency 2370system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22478.015927 # average StoreCondReq mshr miss latency 2371system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22478.015927 # average StoreCondReq mshr miss latency | 2304system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22364.384779 # average overall miss latency 2305system.cpu1.dcache.demand_avg_miss_latency::total 22364.384779 # average overall miss latency 2306system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21310.710876 # average overall miss latency 2307system.cpu1.dcache.overall_avg_miss_latency::total 21310.710876 # average overall miss latency 2308system.cpu1.dcache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked 2309system.cpu1.dcache.blocked_cycles::no_targets 1471779 # number of cycles access was blocked 2310system.cpu1.dcache.blocked::no_mshrs 29 # number of cycles access was blocked 2311system.cpu1.dcache.blocked::no_targets 39630 # number of cycles access was blocked 2312system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.137931 # average number of cycles each access was blocked 2313system.cpu1.dcache.avg_blocked_cycles::no_targets 37.138002 # average number of cycles each access was blocked 2314system.cpu1.dcache.writebacks::writebacks 187625 # number of writebacks 2315system.cpu1.dcache.writebacks::total 187625 # number of writebacks 2316system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78547 # number of ReadReq MSHR hits 2317system.cpu1.dcache.ReadReq_mshr_hits::total 78547 # number of ReadReq MSHR hits 2318system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 305511 # number of WriteReq MSHR hits 2319system.cpu1.dcache.WriteReq_mshr_hits::total 305511 # number of WriteReq MSHR hits 2320system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13157 # number of LoadLockedReq MSHR hits 2321system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13157 # number of LoadLockedReq MSHR hits 2322system.cpu1.dcache.demand_mshr_hits::cpu1.data 384058 # number of demand (read+write) MSHR hits 2323system.cpu1.dcache.demand_mshr_hits::total 384058 # number of demand (read+write) MSHR hits 2324system.cpu1.dcache.overall_mshr_hits::cpu1.data 384058 # number of overall MSHR hits 2325system.cpu1.dcache.overall_mshr_hits::total 384058 # number of overall MSHR hits 2326system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136349 # number of ReadReq MSHR misses 2327system.cpu1.dcache.ReadReq_mshr_misses::total 136349 # number of ReadReq MSHR misses 2328system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90170 # number of WriteReq MSHR misses 2329system.cpu1.dcache.WriteReq_mshr_misses::total 90170 # number of WriteReq MSHR misses 2330system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28879 # number of SoftPFReq MSHR misses 2331system.cpu1.dcache.SoftPFReq_mshr_misses::total 28879 # number of SoftPFReq MSHR misses 2332system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5326 # number of LoadLockedReq MSHR misses 2333system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5326 # number of LoadLockedReq MSHR misses 2334system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23644 # number of StoreCondReq MSHR misses 2335system.cpu1.dcache.StoreCondReq_mshr_misses::total 23644 # number of StoreCondReq MSHR misses 2336system.cpu1.dcache.demand_mshr_misses::cpu1.data 226519 # number of demand (read+write) MSHR misses 2337system.cpu1.dcache.demand_mshr_misses::total 226519 # number of demand (read+write) MSHR misses 2338system.cpu1.dcache.overall_mshr_misses::cpu1.data 255398 # number of overall MSHR misses 2339system.cpu1.dcache.overall_mshr_misses::total 255398 # number of overall MSHR misses 2340system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14314 # number of ReadReq MSHR uncacheable 2341system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14314 # number of ReadReq MSHR uncacheable 2342system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable 2343system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11648 # number of WriteReq MSHR uncacheable 2344system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25962 # number of overall MSHR uncacheable misses 2345system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25962 # number of overall MSHR uncacheable misses 2346system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988454500 # number of ReadReq MSHR miss cycles 2347system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988454500 # number of ReadReq MSHR miss cycles 2348system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2445262471 # number of WriteReq MSHR miss cycles 2349system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2445262471 # number of WriteReq MSHR miss cycles 2350system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 492196500 # number of SoftPFReq MSHR miss cycles 2351system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 492196500 # number of SoftPFReq MSHR miss cycles 2352system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93636000 # number of LoadLockedReq MSHR miss cycles 2353system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93636000 # number of LoadLockedReq MSHR miss cycles 2354system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531294000 # number of StoreCondReq MSHR miss cycles 2355system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531294000 # number of StoreCondReq MSHR miss cycles 2356system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 398500 # number of StoreCondFailReq MSHR miss cycles 2357system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 398500 # number of StoreCondFailReq MSHR miss cycles 2358system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4433716971 # number of demand (read+write) MSHR miss cycles 2359system.cpu1.dcache.demand_mshr_miss_latency::total 4433716971 # number of demand (read+write) MSHR miss cycles 2360system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4925913471 # number of overall MSHR miss cycles 2361system.cpu1.dcache.overall_mshr_miss_latency::total 4925913471 # number of overall MSHR miss cycles 2362system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2472670000 # number of ReadReq MSHR uncacheable cycles 2363system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2472670000 # number of ReadReq MSHR uncacheable cycles 2364system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2472670000 # number of overall MSHR uncacheable cycles 2365system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2472670000 # number of overall MSHR uncacheable cycles 2366system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013977 # mshr miss rate for ReadReq accesses 2367system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013977 # mshr miss rate for ReadReq accesses 2368system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014296 # mshr miss rate for WriteReq accesses 2369system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014296 # mshr miss rate for WriteReq accesses 2370system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361267 # mshr miss rate for SoftPFReq accesses 2371system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361267 # mshr miss rate for SoftPFReq accesses 2372system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054650 # mshr miss rate for LoadLockedReq accesses 2373system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054650 # mshr miss rate for LoadLockedReq accesses 2374system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249559 # mshr miss rate for StoreCondReq accesses 2375system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249559 # mshr miss rate for StoreCondReq accesses 2376system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014102 # mshr miss rate for demand accesses 2377system.cpu1.dcache.demand_mshr_miss_rate::total 0.014102 # mshr miss rate for demand accesses 2378system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015821 # mshr miss rate for overall accesses 2379system.cpu1.dcache.overall_mshr_miss_rate::total 0.015821 # mshr miss rate for overall accesses 2380system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14583.564969 # average ReadReq mshr miss latency 2381system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14583.564969 # average ReadReq mshr miss latency 2382system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27118.359443 # average WriteReq mshr miss latency 2383system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27118.359443 # average WriteReq mshr miss latency 2384system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17043.405243 # average SoftPFReq mshr miss latency 2385system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17043.405243 # average SoftPFReq mshr miss latency 2386system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17580.923770 # average LoadLockedReq mshr miss latency 2387system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17580.923770 # average LoadLockedReq mshr miss latency 2388system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22470.563356 # average StoreCondReq mshr miss latency 2389system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22470.563356 # average StoreCondReq mshr miss latency |
| 2372system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2373system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2390system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2391system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2374system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19581.877709 # average overall mshr miss latency 2375system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19581.877709 # average overall mshr miss latency 2376system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19291.945647 # average overall mshr miss latency 2377system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19291.945647 # average overall mshr miss latency 2378system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134214.583333 # average ReadReq mshr uncacheable latency 2379system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134214.583333 # average ReadReq mshr uncacheable latency 2380system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 75643.444227 # average overall mshr uncacheable latency 2381system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 75643.444227 # average overall mshr uncacheable latency 2382system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2383system.cpu1.icache.tags.replacements 594968 # number of replacements 2384system.cpu1.icache.tags.tagsinuse 499.436901 # Cycle average of tags in use 2385system.cpu1.icache.tags.total_refs 7527273 # Total number of references to valid blocks. 2386system.cpu1.icache.tags.sampled_refs 595480 # Sample count of references to valid blocks. 2387system.cpu1.icache.tags.avg_refs 12.640681 # Average number of references to valid blocks. 2388system.cpu1.icache.tags.warmup_cycle 79132209500 # Cycle when the warmup percentage was hit. 2389system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.436901 # Average occupied blocks per requestor 2390system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975463 # Average percentage of cache occupancy 2391system.cpu1.icache.tags.occ_percent::total 0.975463 # Average percentage of cache occupancy | 2392system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19573.267457 # average overall mshr miss latency 2393system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19573.267457 # average overall mshr miss latency 2394system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19287.204563 # average overall mshr miss latency 2395system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19287.204563 # average overall mshr miss latency 2396system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172744.865167 # average ReadReq mshr uncacheable latency 2397system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172744.865167 # average ReadReq mshr uncacheable latency 2398system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95241.891996 # average overall mshr uncacheable latency 2399system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95241.891996 # average overall mshr uncacheable latency 2400system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2401system.cpu1.icache.tags.replacements 599092 # number of replacements 2402system.cpu1.icache.tags.tagsinuse 499.435973 # Cycle average of tags in use 2403system.cpu1.icache.tags.total_refs 42856272 # Total number of references to valid blocks. 2404system.cpu1.icache.tags.sampled_refs 599604 # Sample count of references to valid blocks. 2405system.cpu1.icache.tags.avg_refs 71.474293 # Average number of references to valid blocks. 2406system.cpu1.icache.tags.warmup_cycle 79139515500 # Cycle when the warmup percentage was hit. 2407system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.435973 # Average occupied blocks per requestor 2408system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975461 # Average percentage of cache occupancy 2409system.cpu1.icache.tags.occ_percent::total 0.975461 # Average percentage of cache occupancy |
| 2392system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 2410system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 2393system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id 2394system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id | 2411system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2412system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id |
| 2395system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2413system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2396system.cpu1.icache.tags.tag_accesses 16885432 # Number of tag accesses 2397system.cpu1.icache.tags.data_accesses 16885432 # Number of data accesses 2398system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2399system.cpu1.icache.ReadReq_hits::cpu1.inst 7527273 # number of ReadReq hits 2400system.cpu1.icache.ReadReq_hits::total 7527273 # number of ReadReq hits 2401system.cpu1.icache.demand_hits::cpu1.inst 7527273 # number of demand (read+write) hits 2402system.cpu1.icache.demand_hits::total 7527273 # number of demand (read+write) hits 2403system.cpu1.icache.overall_hits::cpu1.inst 7527273 # number of overall hits 2404system.cpu1.icache.overall_hits::total 7527273 # number of overall hits 2405system.cpu1.icache.ReadReq_misses::cpu1.inst 617701 # number of ReadReq misses 2406system.cpu1.icache.ReadReq_misses::total 617701 # number of ReadReq misses 2407system.cpu1.icache.demand_misses::cpu1.inst 617701 # number of demand (read+write) misses 2408system.cpu1.icache.demand_misses::total 617701 # number of demand (read+write) misses 2409system.cpu1.icache.overall_misses::cpu1.inst 617701 # number of overall misses 2410system.cpu1.icache.overall_misses::total 617701 # number of overall misses 2411system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5784933521 # number of ReadReq miss cycles 2412system.cpu1.icache.ReadReq_miss_latency::total 5784933521 # number of ReadReq miss cycles 2413system.cpu1.icache.demand_miss_latency::cpu1.inst 5784933521 # number of demand (read+write) miss cycles 2414system.cpu1.icache.demand_miss_latency::total 5784933521 # number of demand (read+write) miss cycles 2415system.cpu1.icache.overall_miss_latency::cpu1.inst 5784933521 # number of overall miss cycles 2416system.cpu1.icache.overall_miss_latency::total 5784933521 # number of overall miss cycles 2417system.cpu1.icache.ReadReq_accesses::cpu1.inst 8144974 # number of ReadReq accesses(hits+misses) 2418system.cpu1.icache.ReadReq_accesses::total 8144974 # number of ReadReq accesses(hits+misses) 2419system.cpu1.icache.demand_accesses::cpu1.inst 8144974 # number of demand (read+write) accesses 2420system.cpu1.icache.demand_accesses::total 8144974 # number of demand (read+write) accesses 2421system.cpu1.icache.overall_accesses::cpu1.inst 8144974 # number of overall (read+write) accesses 2422system.cpu1.icache.overall_accesses::total 8144974 # number of overall (read+write) accesses 2423system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.075838 # miss rate for ReadReq accesses 2424system.cpu1.icache.ReadReq_miss_rate::total 0.075838 # miss rate for ReadReq accesses 2425system.cpu1.icache.demand_miss_rate::cpu1.inst 0.075838 # miss rate for demand accesses 2426system.cpu1.icache.demand_miss_rate::total 0.075838 # miss rate for demand accesses 2427system.cpu1.icache.overall_miss_rate::cpu1.inst 0.075838 # miss rate for overall accesses 2428system.cpu1.icache.overall_miss_rate::total 0.075838 # miss rate for overall accesses 2429system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9365.264944 # average ReadReq miss latency 2430system.cpu1.icache.ReadReq_avg_miss_latency::total 9365.264944 # average ReadReq miss latency 2431system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency 2432system.cpu1.icache.demand_avg_miss_latency::total 9365.264944 # average overall miss latency 2433system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency 2434system.cpu1.icache.overall_avg_miss_latency::total 9365.264944 # average overall miss latency 2435system.cpu1.icache.blocked_cycles::no_mshrs 523604 # number of cycles access was blocked 2436system.cpu1.icache.blocked_cycles::no_targets 40 # number of cycles access was blocked 2437system.cpu1.icache.blocked::no_mshrs 42411 # number of cycles access was blocked | 2414system.cpu1.icache.tags.tag_accesses 87558770 # Number of tag accesses 2415system.cpu1.icache.tags.data_accesses 87558770 # Number of data accesses 2416system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2417system.cpu1.icache.ReadReq_hits::cpu1.inst 42856272 # number of ReadReq hits 2418system.cpu1.icache.ReadReq_hits::total 42856272 # number of ReadReq hits 2419system.cpu1.icache.demand_hits::cpu1.inst 42856272 # number of demand (read+write) hits 2420system.cpu1.icache.demand_hits::total 42856272 # number of demand (read+write) hits 2421system.cpu1.icache.overall_hits::cpu1.inst 42856272 # number of overall hits 2422system.cpu1.icache.overall_hits::total 42856272 # number of overall hits 2423system.cpu1.icache.ReadReq_misses::cpu1.inst 623309 # number of ReadReq misses 2424system.cpu1.icache.ReadReq_misses::total 623309 # number of ReadReq misses 2425system.cpu1.icache.demand_misses::cpu1.inst 623309 # number of demand (read+write) misses 2426system.cpu1.icache.demand_misses::total 623309 # number of demand (read+write) misses 2427system.cpu1.icache.overall_misses::cpu1.inst 623309 # number of overall misses 2428system.cpu1.icache.overall_misses::total 623309 # number of overall misses 2429system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5905173986 # number of ReadReq miss cycles 2430system.cpu1.icache.ReadReq_miss_latency::total 5905173986 # number of ReadReq miss cycles 2431system.cpu1.icache.demand_miss_latency::cpu1.inst 5905173986 # number of demand (read+write) miss cycles 2432system.cpu1.icache.demand_miss_latency::total 5905173986 # number of demand (read+write) miss cycles 2433system.cpu1.icache.overall_miss_latency::cpu1.inst 5905173986 # number of overall miss cycles 2434system.cpu1.icache.overall_miss_latency::total 5905173986 # number of overall miss cycles 2435system.cpu1.icache.ReadReq_accesses::cpu1.inst 43479581 # number of ReadReq accesses(hits+misses) 2436system.cpu1.icache.ReadReq_accesses::total 43479581 # number of ReadReq accesses(hits+misses) 2437system.cpu1.icache.demand_accesses::cpu1.inst 43479581 # number of demand (read+write) accesses 2438system.cpu1.icache.demand_accesses::total 43479581 # number of demand (read+write) accesses 2439system.cpu1.icache.overall_accesses::cpu1.inst 43479581 # number of overall (read+write) accesses 2440system.cpu1.icache.overall_accesses::total 43479581 # number of overall (read+write) accesses 2441system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014336 # miss rate for ReadReq accesses 2442system.cpu1.icache.ReadReq_miss_rate::total 0.014336 # miss rate for ReadReq accesses 2443system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014336 # miss rate for demand accesses 2444system.cpu1.icache.demand_miss_rate::total 0.014336 # miss rate for demand accesses 2445system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014336 # miss rate for overall accesses 2446system.cpu1.icache.overall_miss_rate::total 0.014336 # miss rate for overall accesses 2447system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9473.910991 # average ReadReq miss latency 2448system.cpu1.icache.ReadReq_avg_miss_latency::total 9473.910991 # average ReadReq miss latency 2449system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency 2450system.cpu1.icache.demand_avg_miss_latency::total 9473.910991 # average overall miss latency 2451system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency 2452system.cpu1.icache.overall_avg_miss_latency::total 9473.910991 # average overall miss latency 2453system.cpu1.icache.blocked_cycles::no_mshrs 533657 # number of cycles access was blocked 2454system.cpu1.icache.blocked_cycles::no_targets 290 # number of cycles access was blocked 2455system.cpu1.icache.blocked::no_mshrs 42078 # number of cycles access was blocked |
| 2438system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked | 2456system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked |
| 2439system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.345948 # average number of cycles each access was blocked 2440system.cpu1.icache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked 2441system.cpu1.icache.writebacks::writebacks 594968 # number of writebacks 2442system.cpu1.icache.writebacks::total 594968 # number of writebacks 2443system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22217 # number of ReadReq MSHR hits 2444system.cpu1.icache.ReadReq_mshr_hits::total 22217 # number of ReadReq MSHR hits 2445system.cpu1.icache.demand_mshr_hits::cpu1.inst 22217 # number of demand (read+write) MSHR hits 2446system.cpu1.icache.demand_mshr_hits::total 22217 # number of demand (read+write) MSHR hits 2447system.cpu1.icache.overall_mshr_hits::cpu1.inst 22217 # number of overall MSHR hits 2448system.cpu1.icache.overall_mshr_hits::total 22217 # number of overall MSHR hits 2449system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595484 # number of ReadReq MSHR misses 2450system.cpu1.icache.ReadReq_mshr_misses::total 595484 # number of ReadReq MSHR misses 2451system.cpu1.icache.demand_mshr_misses::cpu1.inst 595484 # number of demand (read+write) MSHR misses 2452system.cpu1.icache.demand_mshr_misses::total 595484 # number of demand (read+write) MSHR misses 2453system.cpu1.icache.overall_mshr_misses::cpu1.inst 595484 # number of overall MSHR misses 2454system.cpu1.icache.overall_mshr_misses::total 595484 # number of overall MSHR misses | 2457system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.682566 # average number of cycles each access was blocked 2458system.cpu1.icache.avg_blocked_cycles::no_targets 290 # average number of cycles each access was blocked 2459system.cpu1.icache.writebacks::writebacks 599092 # number of writebacks 2460system.cpu1.icache.writebacks::total 599092 # number of writebacks 2461system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23701 # number of ReadReq MSHR hits 2462system.cpu1.icache.ReadReq_mshr_hits::total 23701 # number of ReadReq MSHR hits 2463system.cpu1.icache.demand_mshr_hits::cpu1.inst 23701 # number of demand (read+write) MSHR hits 2464system.cpu1.icache.demand_mshr_hits::total 23701 # number of demand (read+write) MSHR hits 2465system.cpu1.icache.overall_mshr_hits::cpu1.inst 23701 # number of overall MSHR hits 2466system.cpu1.icache.overall_mshr_hits::total 23701 # number of overall MSHR hits 2467system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 599608 # number of ReadReq MSHR misses 2468system.cpu1.icache.ReadReq_mshr_misses::total 599608 # number of ReadReq MSHR misses 2469system.cpu1.icache.demand_mshr_misses::cpu1.inst 599608 # number of demand (read+write) MSHR misses 2470system.cpu1.icache.demand_mshr_misses::total 599608 # number of demand (read+write) MSHR misses 2471system.cpu1.icache.overall_mshr_misses::cpu1.inst 599608 # number of overall MSHR misses 2472system.cpu1.icache.overall_mshr_misses::total 599608 # number of overall MSHR misses |
| 2455system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable 2456system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable 2457system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses 2458system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses | 2473system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable 2474system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable 2475system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses 2476system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses |
| 2459system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5318077800 # number of ReadReq MSHR miss cycles 2460system.cpu1.icache.ReadReq_mshr_miss_latency::total 5318077800 # number of ReadReq MSHR miss cycles 2461system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5318077800 # number of demand (read+write) MSHR miss cycles 2462system.cpu1.icache.demand_mshr_miss_latency::total 5318077800 # number of demand (read+write) MSHR miss cycles 2463system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5318077800 # number of overall MSHR miss cycles 2464system.cpu1.icache.overall_mshr_miss_latency::total 5318077800 # number of overall MSHR miss cycles 2465system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9663500 # number of ReadReq MSHR uncacheable cycles 2466system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9663500 # number of ReadReq MSHR uncacheable cycles 2467system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9663500 # number of overall MSHR uncacheable cycles 2468system.cpu1.icache.overall_mshr_uncacheable_latency::total 9663500 # number of overall MSHR uncacheable cycles 2469system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for ReadReq accesses 2470system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.073111 # mshr miss rate for ReadReq accesses 2471system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for demand accesses 2472system.cpu1.icache.demand_mshr_miss_rate::total 0.073111 # mshr miss rate for demand accesses 2473system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for overall accesses 2474system.cpu1.icache.overall_mshr_miss_rate::total 0.073111 # mshr miss rate for overall accesses 2475system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average ReadReq mshr miss latency 2476system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8930.681261 # average ReadReq mshr miss latency 2477system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency 2478system.cpu1.icache.demand_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency 2479system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency 2480system.cpu1.icache.overall_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency 2481system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average ReadReq mshr uncacheable latency 2482system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95678.217822 # average ReadReq mshr uncacheable latency 2483system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average overall mshr uncacheable latency 2484system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95678.217822 # average overall mshr uncacheable latency 2485system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2486system.cpu1.l2cache.prefetcher.num_hwpf_issued 194116 # number of hwpf issued 2487system.cpu1.l2cache.prefetcher.pfIdentified 194726 # number of prefetch candidates identified 2488system.cpu1.l2cache.prefetcher.pfBufferHit 546 # number of redundant prefetches already in prefetch queue | 2477system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5403181271 # number of ReadReq MSHR miss cycles 2478system.cpu1.icache.ReadReq_mshr_miss_latency::total 5403181271 # number of ReadReq MSHR miss cycles 2479system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5403181271 # number of demand (read+write) MSHR miss cycles 2480system.cpu1.icache.demand_mshr_miss_latency::total 5403181271 # number of demand (read+write) MSHR miss cycles 2481system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5403181271 # number of overall MSHR miss cycles 2482system.cpu1.icache.overall_mshr_miss_latency::total 5403181271 # number of overall MSHR miss cycles 2483system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9499999 # number of ReadReq MSHR uncacheable cycles 2484system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9499999 # number of ReadReq MSHR uncacheable cycles 2485system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9499999 # number of overall MSHR uncacheable cycles 2486system.cpu1.icache.overall_mshr_uncacheable_latency::total 9499999 # number of overall MSHR uncacheable cycles 2487system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for ReadReq accesses 2488system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013791 # mshr miss rate for ReadReq accesses 2489system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for demand accesses 2490system.cpu1.icache.demand_mshr_miss_rate::total 0.013791 # mshr miss rate for demand accesses 2491system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for overall accesses 2492system.cpu1.icache.overall_mshr_miss_rate::total 0.013791 # mshr miss rate for overall accesses 2493system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average ReadReq mshr miss latency 2494system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9011.189429 # average ReadReq mshr miss latency 2495system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency 2496system.cpu1.icache.demand_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency 2497system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency 2498system.cpu1.icache.overall_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency 2499system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average ReadReq mshr uncacheable latency 2500system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94059.396040 # average ReadReq mshr uncacheable latency 2501system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average overall mshr uncacheable latency 2502system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94059.396040 # average overall mshr uncacheable latency 2503system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2504system.cpu1.l2cache.prefetcher.num_hwpf_issued 194821 # number of hwpf issued 2505system.cpu1.l2cache.prefetcher.pfIdentified 195463 # number of prefetch candidates identified 2506system.cpu1.l2cache.prefetcher.pfBufferHit 575 # number of redundant prefetches already in prefetch queue |
| 2489system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2490system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 2507system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2508system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 2491system.cpu1.l2cache.prefetcher.pfSpanPage 59858 # number of prefetches not generated due to page crossing 2492system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2493system.cpu1.l2cache.tags.replacements 43575 # number of replacements 2494system.cpu1.l2cache.tags.tagsinuse 14594.735842 # Cycle average of tags in use 2495system.cpu1.l2cache.tags.total_refs 700816 # Total number of references to valid blocks. 2496system.cpu1.l2cache.tags.sampled_refs 57699 # Sample count of references to valid blocks. 2497system.cpu1.l2cache.tags.avg_refs 12.146068 # Average number of references to valid blocks. | 2509system.cpu1.l2cache.prefetcher.pfSpanPage 59841 # number of prefetches not generated due to page crossing 2510system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2511system.cpu1.l2cache.tags.replacements 44456 # number of replacements 2512system.cpu1.l2cache.tags.tagsinuse 14684.761874 # Cycle average of tags in use 2513system.cpu1.l2cache.tags.total_refs 706823 # Total number of references to valid blocks. 2514system.cpu1.l2cache.tags.sampled_refs 58616 # Sample count of references to valid blocks. 2515system.cpu1.l2cache.tags.avg_refs 12.058534 # Average number of references to valid blocks. |
| 2498system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2516system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2499system.cpu1.l2cache.tags.occ_blocks::writebacks 14193.075757 # Average occupied blocks per requestor 2500system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.827460 # Average occupied blocks per requestor 2501system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.968470 # Average occupied blocks per requestor 2502system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 387.864155 # Average occupied blocks per requestor 2503system.cpu1.l2cache.tags.occ_percent::writebacks 0.866277 # Average percentage of cache occupancy 2504system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy 2505system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy 2506system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023673 # Average percentage of cache occupancy 2507system.cpu1.l2cache.tags.occ_percent::total 0.890792 # Average percentage of cache occupancy 2508system.cpu1.l2cache.tags.occ_task_id_blocks::1022 356 # Occupied blocks per task id 2509system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id 2510system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13738 # Occupied blocks per task id 2511system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id 2512system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 202 # Occupied blocks per task id 2513system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 139 # Occupied blocks per task id 2514system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 2515system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 2516system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 2517system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1740 # Occupied blocks per task id 2518system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8639 # Occupied blocks per task id 2519system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3359 # Occupied blocks per task id 2520system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021729 # Percentage of cache occupancy per task id 2521system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id 2522system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.838501 # Percentage of cache occupancy per task id 2523system.cpu1.l2cache.tags.tag_accesses 27539438 # Number of tag accesses 2524system.cpu1.l2cache.tags.data_accesses 27539438 # Number of data accesses 2525system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2526system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17059 # number of ReadReq hits 2527system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6202 # number of ReadReq hits 2528system.cpu1.l2cache.ReadReq_hits::total 23261 # number of ReadReq hits 2529system.cpu1.l2cache.WritebackDirty_hits::writebacks 113931 # number of WritebackDirty hits 2530system.cpu1.l2cache.WritebackDirty_hits::total 113931 # number of WritebackDirty hits 2531system.cpu1.l2cache.WritebackClean_hits::writebacks 655101 # number of WritebackClean hits 2532system.cpu1.l2cache.WritebackClean_hits::total 655101 # number of WritebackClean hits 2533system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27113 # number of ReadExReq hits 2534system.cpu1.l2cache.ReadExReq_hits::total 27113 # number of ReadExReq hits 2535system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 571525 # number of ReadCleanReq hits 2536system.cpu1.l2cache.ReadCleanReq_hits::total 571525 # number of ReadCleanReq hits 2537system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98074 # number of ReadSharedReq hits 2538system.cpu1.l2cache.ReadSharedReq_hits::total 98074 # number of ReadSharedReq hits 2539system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17059 # number of demand (read+write) hits 2540system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6202 # number of demand (read+write) hits 2541system.cpu1.l2cache.demand_hits::cpu1.inst 571525 # number of demand (read+write) hits 2542system.cpu1.l2cache.demand_hits::cpu1.data 125187 # number of demand (read+write) hits 2543system.cpu1.l2cache.demand_hits::total 719973 # number of demand (read+write) hits 2544system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17059 # number of overall hits 2545system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6202 # number of overall hits 2546system.cpu1.l2cache.overall_hits::cpu1.inst 571525 # number of overall hits 2547system.cpu1.l2cache.overall_hits::cpu1.data 125187 # number of overall hits 2548system.cpu1.l2cache.overall_hits::total 719973 # number of overall hits 2549system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 502 # number of ReadReq misses 2550system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 304 # number of ReadReq misses 2551system.cpu1.l2cache.ReadReq_misses::total 806 # number of ReadReq misses 2552system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29460 # number of UpgradeReq misses 2553system.cpu1.l2cache.UpgradeReq_misses::total 29460 # number of UpgradeReq misses 2554system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23607 # number of SCUpgradeReq misses 2555system.cpu1.l2cache.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses | 2517system.cpu1.l2cache.tags.occ_blocks::writebacks 14300.099102 # Average occupied blocks per requestor 2518system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.020323 # Average occupied blocks per requestor 2519system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.955758 # Average occupied blocks per requestor 2520system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 371.686691 # Average occupied blocks per requestor 2521system.cpu1.l2cache.tags.occ_percent::writebacks 0.872809 # Average percentage of cache occupancy 2522system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000612 # Average percentage of cache occupancy 2523system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000180 # Average percentage of cache occupancy 2524system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.022686 # Average percentage of cache occupancy 2525system.cpu1.l2cache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy 2526system.cpu1.l2cache.tags.occ_task_id_blocks::1022 332 # Occupied blocks per task id 2527system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id 2528system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13796 # Occupied blocks per task id 2529system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id 2530system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 205 # Occupied blocks per task id 2531system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 117 # Occupied blocks per task id 2532system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 2533system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 2534system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 2535system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1791 # Occupied blocks per task id 2536system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8656 # Occupied blocks per task id 2537system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3349 # Occupied blocks per task id 2538system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020264 # Percentage of cache occupancy per task id 2539system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id 2540system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842041 # Percentage of cache occupancy per task id 2541system.cpu1.l2cache.tags.tag_accesses 27731086 # Number of tag accesses 2542system.cpu1.l2cache.tags.data_accesses 27731086 # Number of data accesses 2543system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2544system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17081 # number of ReadReq hits 2545system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7133 # number of ReadReq hits 2546system.cpu1.l2cache.ReadReq_hits::total 24214 # number of ReadReq hits 2547system.cpu1.l2cache.WritebackDirty_hits::writebacks 114521 # number of WritebackDirty hits 2548system.cpu1.l2cache.WritebackDirty_hits::total 114521 # number of WritebackDirty hits 2549system.cpu1.l2cache.WritebackClean_hits::writebacks 659711 # number of WritebackClean hits 2550system.cpu1.l2cache.WritebackClean_hits::total 659711 # number of WritebackClean hits 2551system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27226 # number of ReadExReq hits 2552system.cpu1.l2cache.ReadExReq_hits::total 27226 # number of ReadExReq hits 2553system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 575115 # number of ReadCleanReq hits 2554system.cpu1.l2cache.ReadCleanReq_hits::total 575115 # number of ReadCleanReq hits 2555system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98702 # number of ReadSharedReq hits 2556system.cpu1.l2cache.ReadSharedReq_hits::total 98702 # number of ReadSharedReq hits 2557system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17081 # number of demand (read+write) hits 2558system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7133 # number of demand (read+write) hits 2559system.cpu1.l2cache.demand_hits::cpu1.inst 575115 # number of demand (read+write) hits 2560system.cpu1.l2cache.demand_hits::cpu1.data 125928 # number of demand (read+write) hits 2561system.cpu1.l2cache.demand_hits::total 725257 # number of demand (read+write) hits 2562system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17081 # number of overall hits 2563system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7133 # number of overall hits 2564system.cpu1.l2cache.overall_hits::cpu1.inst 575115 # number of overall hits 2565system.cpu1.l2cache.overall_hits::cpu1.data 125928 # number of overall hits 2566system.cpu1.l2cache.overall_hits::total 725257 # number of overall hits 2567system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 517 # number of ReadReq misses 2568system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 296 # number of ReadReq misses 2569system.cpu1.l2cache.ReadReq_misses::total 813 # number of ReadReq misses 2570system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 2571system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 2572system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29667 # number of UpgradeReq misses 2573system.cpu1.l2cache.UpgradeReq_misses::total 29667 # number of UpgradeReq misses 2574system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23643 # number of SCUpgradeReq misses 2575system.cpu1.l2cache.SCUpgradeReq_misses::total 23643 # number of SCUpgradeReq misses |
| 2556system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 2557system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses | 2576system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 2577system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses |
| 2558system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33905 # number of ReadExReq misses 2559system.cpu1.l2cache.ReadExReq_misses::total 33905 # number of ReadExReq misses 2560system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 23957 # number of ReadCleanReq misses 2561system.cpu1.l2cache.ReadCleanReq_misses::total 23957 # number of ReadCleanReq misses 2562system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71492 # number of ReadSharedReq misses 2563system.cpu1.l2cache.ReadSharedReq_misses::total 71492 # number of ReadSharedReq misses 2564system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 502 # number of demand (read+write) misses 2565system.cpu1.l2cache.demand_misses::cpu1.itb.walker 304 # number of demand (read+write) misses 2566system.cpu1.l2cache.demand_misses::cpu1.inst 23957 # number of demand (read+write) misses 2567system.cpu1.l2cache.demand_misses::cpu1.data 105397 # number of demand (read+write) misses 2568system.cpu1.l2cache.demand_misses::total 130160 # number of demand (read+write) misses 2569system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 502 # number of overall misses 2570system.cpu1.l2cache.overall_misses::cpu1.itb.walker 304 # number of overall misses 2571system.cpu1.l2cache.overall_misses::cpu1.inst 23957 # number of overall misses 2572system.cpu1.l2cache.overall_misses::cpu1.data 105397 # number of overall misses 2573system.cpu1.l2cache.overall_misses::total 130160 # number of overall misses 2574system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10772500 # number of ReadReq miss cycles 2575system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6194000 # number of ReadReq miss cycles 2576system.cpu1.l2cache.ReadReq_miss_latency::total 16966500 # number of ReadReq miss cycles 2577system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12496500 # number of UpgradeReq miss cycles 2578system.cpu1.l2cache.UpgradeReq_miss_latency::total 12496500 # number of UpgradeReq miss cycles 2579system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18899500 # number of SCUpgradeReq miss cycles 2580system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18899500 # number of SCUpgradeReq miss cycles 2581system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 407499 # number of SCUpgradeFailReq miss cycles 2582system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 407499 # number of SCUpgradeFailReq miss cycles 2583system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1469375000 # number of ReadExReq miss cycles 2584system.cpu1.l2cache.ReadExReq_miss_latency::total 1469375000 # number of ReadExReq miss cycles 2585system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 945511500 # number of ReadCleanReq miss cycles 2586system.cpu1.l2cache.ReadCleanReq_miss_latency::total 945511500 # number of ReadCleanReq miss cycles 2587system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1646741997 # number of ReadSharedReq miss cycles 2588system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1646741997 # number of ReadSharedReq miss cycles 2589system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10772500 # number of demand (read+write) miss cycles 2590system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6194000 # number of demand (read+write) miss cycles 2591system.cpu1.l2cache.demand_miss_latency::cpu1.inst 945511500 # number of demand (read+write) miss cycles 2592system.cpu1.l2cache.demand_miss_latency::cpu1.data 3116116997 # number of demand (read+write) miss cycles 2593system.cpu1.l2cache.demand_miss_latency::total 4078594997 # number of demand (read+write) miss cycles 2594system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10772500 # number of overall miss cycles 2595system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6194000 # number of overall miss cycles 2596system.cpu1.l2cache.overall_miss_latency::cpu1.inst 945511500 # number of overall miss cycles 2597system.cpu1.l2cache.overall_miss_latency::cpu1.data 3116116997 # number of overall miss cycles 2598system.cpu1.l2cache.overall_miss_latency::total 4078594997 # number of overall miss cycles 2599system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17561 # number of ReadReq accesses(hits+misses) 2600system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6506 # number of ReadReq accesses(hits+misses) 2601system.cpu1.l2cache.ReadReq_accesses::total 24067 # number of ReadReq accesses(hits+misses) 2602system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113931 # number of WritebackDirty accesses(hits+misses) 2603system.cpu1.l2cache.WritebackDirty_accesses::total 113931 # number of WritebackDirty accesses(hits+misses) 2604system.cpu1.l2cache.WritebackClean_accesses::writebacks 655101 # number of WritebackClean accesses(hits+misses) 2605system.cpu1.l2cache.WritebackClean_accesses::total 655101 # number of WritebackClean accesses(hits+misses) 2606system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29460 # number of UpgradeReq accesses(hits+misses) 2607system.cpu1.l2cache.UpgradeReq_accesses::total 29460 # number of UpgradeReq accesses(hits+misses) 2608system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23607 # number of SCUpgradeReq accesses(hits+misses) 2609system.cpu1.l2cache.SCUpgradeReq_accesses::total 23607 # number of SCUpgradeReq accesses(hits+misses) | 2578system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33950 # number of ReadExReq misses 2579system.cpu1.l2cache.ReadExReq_misses::total 33950 # number of ReadExReq misses 2580system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 24491 # number of ReadCleanReq misses 2581system.cpu1.l2cache.ReadCleanReq_misses::total 24491 # number of ReadCleanReq misses 2582system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71832 # number of ReadSharedReq misses 2583system.cpu1.l2cache.ReadSharedReq_misses::total 71832 # number of ReadSharedReq misses 2584system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 517 # number of demand (read+write) misses 2585system.cpu1.l2cache.demand_misses::cpu1.itb.walker 296 # number of demand (read+write) misses 2586system.cpu1.l2cache.demand_misses::cpu1.inst 24491 # number of demand (read+write) misses 2587system.cpu1.l2cache.demand_misses::cpu1.data 105782 # number of demand (read+write) misses 2588system.cpu1.l2cache.demand_misses::total 131086 # number of demand (read+write) misses 2589system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 517 # number of overall misses 2590system.cpu1.l2cache.overall_misses::cpu1.itb.walker 296 # number of overall misses 2591system.cpu1.l2cache.overall_misses::cpu1.inst 24491 # number of overall misses 2592system.cpu1.l2cache.overall_misses::cpu1.data 105782 # number of overall misses 2593system.cpu1.l2cache.overall_misses::total 131086 # number of overall misses 2594system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11135000 # number of ReadReq miss cycles 2595system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6028000 # number of ReadReq miss cycles 2596system.cpu1.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles 2597system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12712500 # number of UpgradeReq miss cycles 2598system.cpu1.l2cache.UpgradeReq_miss_latency::total 12712500 # number of UpgradeReq miss cycles 2599system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18521500 # number of SCUpgradeReq miss cycles 2600system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18521500 # number of SCUpgradeReq miss cycles 2601system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 382999 # number of SCUpgradeFailReq miss cycles 2602system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 382999 # number of SCUpgradeFailReq miss cycles 2603system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1470067999 # number of ReadExReq miss cycles 2604system.cpu1.l2cache.ReadExReq_miss_latency::total 1470067999 # number of ReadExReq miss cycles 2605system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1003037500 # number of ReadCleanReq miss cycles 2606system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1003037500 # number of ReadCleanReq miss cycles 2607system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1657187499 # number of ReadSharedReq miss cycles 2608system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1657187499 # number of ReadSharedReq miss cycles 2609system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11135000 # number of demand (read+write) miss cycles 2610system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6028000 # number of demand (read+write) miss cycles 2611system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1003037500 # number of demand (read+write) miss cycles 2612system.cpu1.l2cache.demand_miss_latency::cpu1.data 3127255498 # number of demand (read+write) miss cycles 2613system.cpu1.l2cache.demand_miss_latency::total 4147455998 # number of demand (read+write) miss cycles 2614system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11135000 # number of overall miss cycles 2615system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6028000 # number of overall miss cycles 2616system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1003037500 # number of overall miss cycles 2617system.cpu1.l2cache.overall_miss_latency::cpu1.data 3127255498 # number of overall miss cycles 2618system.cpu1.l2cache.overall_miss_latency::total 4147455998 # number of overall miss cycles 2619system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17598 # number of ReadReq accesses(hits+misses) 2620system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7429 # number of ReadReq accesses(hits+misses) 2621system.cpu1.l2cache.ReadReq_accesses::total 25027 # number of ReadReq accesses(hits+misses) 2622system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114522 # number of WritebackDirty accesses(hits+misses) 2623system.cpu1.l2cache.WritebackDirty_accesses::total 114522 # number of WritebackDirty accesses(hits+misses) 2624system.cpu1.l2cache.WritebackClean_accesses::writebacks 659711 # number of WritebackClean accesses(hits+misses) 2625system.cpu1.l2cache.WritebackClean_accesses::total 659711 # number of WritebackClean accesses(hits+misses) 2626system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29667 # number of UpgradeReq accesses(hits+misses) 2627system.cpu1.l2cache.UpgradeReq_accesses::total 29667 # number of UpgradeReq accesses(hits+misses) 2628system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23643 # number of SCUpgradeReq accesses(hits+misses) 2629system.cpu1.l2cache.SCUpgradeReq_accesses::total 23643 # number of SCUpgradeReq accesses(hits+misses) |
| 2610system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2611system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) | 2630system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2631system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) |
| 2612system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61018 # number of ReadExReq accesses(hits+misses) 2613system.cpu1.l2cache.ReadExReq_accesses::total 61018 # number of ReadExReq accesses(hits+misses) 2614system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 595482 # number of ReadCleanReq accesses(hits+misses) 2615system.cpu1.l2cache.ReadCleanReq_accesses::total 595482 # number of ReadCleanReq accesses(hits+misses) 2616system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 169566 # number of ReadSharedReq accesses(hits+misses) 2617system.cpu1.l2cache.ReadSharedReq_accesses::total 169566 # number of ReadSharedReq accesses(hits+misses) 2618system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17561 # number of demand (read+write) accesses 2619system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6506 # number of demand (read+write) accesses 2620system.cpu1.l2cache.demand_accesses::cpu1.inst 595482 # number of demand (read+write) accesses 2621system.cpu1.l2cache.demand_accesses::cpu1.data 230584 # number of demand (read+write) accesses 2622system.cpu1.l2cache.demand_accesses::total 850133 # number of demand (read+write) accesses 2623system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17561 # number of overall (read+write) accesses 2624system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6506 # number of overall (read+write) accesses 2625system.cpu1.l2cache.overall_accesses::cpu1.inst 595482 # number of overall (read+write) accesses 2626system.cpu1.l2cache.overall_accesses::cpu1.data 230584 # number of overall (read+write) accesses 2627system.cpu1.l2cache.overall_accesses::total 850133 # number of overall (read+write) accesses 2628system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for ReadReq accesses 2629system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046726 # miss rate for ReadReq accesses 2630system.cpu1.l2cache.ReadReq_miss_rate::total 0.033490 # miss rate for ReadReq accesses | 2632system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61176 # number of ReadExReq accesses(hits+misses) 2633system.cpu1.l2cache.ReadExReq_accesses::total 61176 # number of ReadExReq accesses(hits+misses) 2634system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 599606 # number of ReadCleanReq accesses(hits+misses) 2635system.cpu1.l2cache.ReadCleanReq_accesses::total 599606 # number of ReadCleanReq accesses(hits+misses) 2636system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 170534 # number of ReadSharedReq accesses(hits+misses) 2637system.cpu1.l2cache.ReadSharedReq_accesses::total 170534 # number of ReadSharedReq accesses(hits+misses) 2638system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17598 # number of demand (read+write) accesses 2639system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7429 # number of demand (read+write) accesses 2640system.cpu1.l2cache.demand_accesses::cpu1.inst 599606 # number of demand (read+write) accesses 2641system.cpu1.l2cache.demand_accesses::cpu1.data 231710 # number of demand (read+write) accesses 2642system.cpu1.l2cache.demand_accesses::total 856343 # number of demand (read+write) accesses 2643system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17598 # number of overall (read+write) accesses 2644system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7429 # number of overall (read+write) accesses 2645system.cpu1.l2cache.overall_accesses::cpu1.inst 599606 # number of overall (read+write) accesses 2646system.cpu1.l2cache.overall_accesses::cpu1.data 231710 # number of overall (read+write) accesses 2647system.cpu1.l2cache.overall_accesses::total 856343 # number of overall (read+write) accesses 2648system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for ReadReq accesses 2649system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.039844 # miss rate for ReadReq accesses 2650system.cpu1.l2cache.ReadReq_miss_rate::total 0.032485 # miss rate for ReadReq accesses 2651system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000009 # miss rate for WritebackDirty accesses 2652system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000009 # miss rate for WritebackDirty accesses |
| 2631system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2632system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2633system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2634system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2635system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2636system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2653system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2654system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2655system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2656system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2657system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2658system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2637system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555656 # miss rate for ReadExReq accesses 2638system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555656 # miss rate for ReadExReq accesses 2639system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040231 # miss rate for ReadCleanReq accesses 2640system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040231 # miss rate for ReadCleanReq accesses 2641system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421618 # miss rate for ReadSharedReq accesses 2642system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421618 # miss rate for ReadSharedReq accesses 2643system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for demand accesses 2644system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046726 # miss rate for demand accesses 2645system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040231 # miss rate for demand accesses 2646system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.457087 # miss rate for demand accesses 2647system.cpu1.l2cache.demand_miss_rate::total 0.153105 # miss rate for demand accesses 2648system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for overall accesses 2649system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046726 # miss rate for overall accesses 2650system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040231 # miss rate for overall accesses 2651system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.457087 # miss rate for overall accesses 2652system.cpu1.l2cache.overall_miss_rate::total 0.153105 # miss rate for overall accesses 2653system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average ReadReq miss latency 2654system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20375 # average ReadReq miss latency 2655system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21050.248139 # average ReadReq miss latency 2656system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 424.185336 # average UpgradeReq miss latency 2657system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 424.185336 # average UpgradeReq miss latency 2658system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 800.588808 # average SCUpgradeReq miss latency 2659system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 800.588808 # average SCUpgradeReq miss latency 2660system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 407499 # average SCUpgradeFailReq miss latency 2661system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407499 # average SCUpgradeFailReq miss latency 2662system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43338.003244 # average ReadExReq miss latency 2663system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43338.003244 # average ReadExReq miss latency 2664system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39467.024252 # average ReadCleanReq miss latency 2665system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39467.024252 # average ReadCleanReq miss latency 2666system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23033.933825 # average ReadSharedReq miss latency 2667system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23033.933825 # average ReadSharedReq miss latency 2668system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency 2669system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency 2670system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency 2671system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency 2672system.cpu1.l2cache.demand_avg_miss_latency::total 31335.241219 # average overall miss latency 2673system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency 2674system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency 2675system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency 2676system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency 2677system.cpu1.l2cache.overall_avg_miss_latency::total 31335.241219 # average overall miss latency 2678system.cpu1.l2cache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked | 2659system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554956 # miss rate for ReadExReq accesses 2660system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554956 # miss rate for ReadExReq accesses 2661system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040845 # miss rate for ReadCleanReq accesses 2662system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040845 # miss rate for ReadCleanReq accesses 2663system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421218 # miss rate for ReadSharedReq accesses 2664system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421218 # miss rate for ReadSharedReq accesses 2665system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for demand accesses 2666system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.039844 # miss rate for demand accesses 2667system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040845 # miss rate for demand accesses 2668system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456528 # miss rate for demand accesses 2669system.cpu1.l2cache.demand_miss_rate::total 0.153077 # miss rate for demand accesses 2670system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for overall accesses 2671system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.039844 # miss rate for overall accesses 2672system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040845 # miss rate for overall accesses 2673system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456528 # miss rate for overall accesses 2674system.cpu1.l2cache.overall_miss_rate::total 0.153077 # miss rate for overall accesses 2675system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average ReadReq miss latency 2676system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20364.864865 # average ReadReq miss latency 2677system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21110.701107 # average ReadReq miss latency 2678system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 428.506421 # average UpgradeReq miss latency 2679system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 428.506421 # average UpgradeReq miss latency 2680system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 783.381974 # average SCUpgradeReq miss latency 2681system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 783.381974 # average SCUpgradeReq miss latency 2682system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 382999 # average SCUpgradeFailReq miss latency 2683system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382999 # average SCUpgradeFailReq miss latency 2684system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43300.971988 # average ReadExReq miss latency 2685system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43300.971988 # average ReadExReq miss latency 2686system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40955.350945 # average ReadCleanReq miss latency 2687system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40955.350945 # average ReadCleanReq miss latency 2688system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23070.323797 # average ReadSharedReq miss latency 2689system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23070.323797 # average ReadSharedReq miss latency 2690system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average overall miss latency 2691system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20364.864865 # average overall miss latency 2692system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40955.350945 # average overall miss latency 2693system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29563.210168 # average overall miss latency 2694system.cpu1.l2cache.demand_avg_miss_latency::total 31639.198679 # average overall miss latency 2695system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average overall miss latency 2696system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20364.864865 # average overall miss latency 2697system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40955.350945 # average overall miss latency 2698system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29563.210168 # average overall miss latency 2699system.cpu1.l2cache.overall_avg_miss_latency::total 31639.198679 # average overall miss latency 2700system.cpu1.l2cache.blocked_cycles::no_mshrs 182 # number of cycles access was blocked |
| 2679system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2701system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2680system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked | 2702system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked |
| 2681system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2703system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2682system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked | 2704system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.333333 # average number of cycles each access was blocked |
| 2683system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2705system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2684system.cpu1.l2cache.unused_prefetches 799 # number of HardPF blocks evicted w/o reference 2685system.cpu1.l2cache.writebacks::writebacks 31397 # number of writebacks 2686system.cpu1.l2cache.writebacks::total 31397 # number of writebacks | 2706system.cpu1.l2cache.unused_prefetches 827 # number of HardPF blocks evicted w/o reference 2707system.cpu1.l2cache.writebacks::writebacks 31720 # number of writebacks 2708system.cpu1.l2cache.writebacks::total 31720 # number of writebacks |
| 2687system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits | 2709system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits |
| 2688system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 2689system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 2690system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 430 # number of ReadExReq MSHR hits 2691system.cpu1.l2cache.ReadExReq_mshr_hits::total 430 # number of ReadExReq MSHR hits | 2710system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2711system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 2712system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 426 # number of ReadExReq MSHR hits 2713system.cpu1.l2cache.ReadExReq_mshr_hits::total 426 # number of ReadExReq MSHR hits |
| 2692system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits 2693system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits | 2714system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits 2715system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits |
| 2694system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 65 # number of ReadSharedReq MSHR hits 2695system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits | 2716system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits 2717system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits |
| 2696system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits | 2718system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits |
| 2697system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits | 2719system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits |
| 2698system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits | 2720system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits |
| 2699system.cpu1.l2cache.demand_mshr_hits::cpu1.data 495 # number of demand (read+write) MSHR hits 2700system.cpu1.l2cache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits | 2721system.cpu1.l2cache.demand_mshr_hits::cpu1.data 500 # number of demand (read+write) MSHR hits 2722system.cpu1.l2cache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits |
| 2701system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits | 2723system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits |
| 2702system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits | 2724system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits |
| 2703system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits | 2725system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits |
| 2704system.cpu1.l2cache.overall_mshr_hits::cpu1.data 495 # number of overall MSHR hits 2705system.cpu1.l2cache.overall_mshr_hits::total 505 # number of overall MSHR hits 2706system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 501 # number of ReadReq MSHR misses 2707system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 302 # number of ReadReq MSHR misses 2708system.cpu1.l2cache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses 2709system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of HardPFReq MSHR misses 2710system.cpu1.l2cache.HardPFReq_mshr_misses::total 25004 # number of HardPFReq MSHR misses 2711system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29460 # number of UpgradeReq MSHR misses 2712system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29460 # number of UpgradeReq MSHR misses 2713system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23607 # number of SCUpgradeReq MSHR misses 2714system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23607 # number of SCUpgradeReq MSHR misses | 2726system.cpu1.l2cache.overall_mshr_hits::cpu1.data 500 # number of overall MSHR hits 2727system.cpu1.l2cache.overall_mshr_hits::total 509 # number of overall MSHR hits 2728system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 516 # number of ReadReq MSHR misses 2729system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 295 # number of ReadReq MSHR misses 2730system.cpu1.l2cache.ReadReq_mshr_misses::total 811 # number of ReadReq MSHR misses 2731system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 2732system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 2733system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25186 # number of HardPFReq MSHR misses 2734system.cpu1.l2cache.HardPFReq_mshr_misses::total 25186 # number of HardPFReq MSHR misses 2735system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29667 # number of UpgradeReq MSHR misses 2736system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29667 # number of UpgradeReq MSHR misses 2737system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23643 # number of SCUpgradeReq MSHR misses 2738system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23643 # number of SCUpgradeReq MSHR misses |
| 2715system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2716system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses | 2739system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2740system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses |
| 2717system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33475 # number of ReadExReq MSHR misses 2718system.cpu1.l2cache.ReadExReq_mshr_misses::total 33475 # number of ReadExReq MSHR misses 2719system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 23950 # number of ReadCleanReq MSHR misses 2720system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 23950 # number of ReadCleanReq MSHR misses 2721system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71427 # number of ReadSharedReq MSHR misses 2722system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71427 # number of ReadSharedReq MSHR misses 2723system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 501 # number of demand (read+write) MSHR misses 2724system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 302 # number of demand (read+write) MSHR misses 2725system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 23950 # number of demand (read+write) MSHR misses 2726system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104902 # number of demand (read+write) MSHR misses 2727system.cpu1.l2cache.demand_mshr_misses::total 129655 # number of demand (read+write) MSHR misses 2728system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 501 # number of overall MSHR misses 2729system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 302 # number of overall MSHR misses 2730system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 23950 # number of overall MSHR misses 2731system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104902 # number of overall MSHR misses 2732system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of overall MSHR misses 2733system.cpu1.l2cache.overall_mshr_misses::total 154659 # number of overall MSHR misses | 2741system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33524 # number of ReadExReq MSHR misses 2742system.cpu1.l2cache.ReadExReq_mshr_misses::total 33524 # number of ReadExReq MSHR misses 2743system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 24484 # number of ReadCleanReq MSHR misses 2744system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 24484 # number of ReadCleanReq MSHR misses 2745system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71758 # number of ReadSharedReq MSHR misses 2746system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71758 # number of ReadSharedReq MSHR misses 2747system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 516 # number of demand (read+write) MSHR misses 2748system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 295 # number of demand (read+write) MSHR misses 2749system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 24484 # number of demand (read+write) MSHR misses 2750system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105282 # number of demand (read+write) MSHR misses 2751system.cpu1.l2cache.demand_mshr_misses::total 130577 # number of demand (read+write) MSHR misses 2752system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 516 # number of overall MSHR misses 2753system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 295 # number of overall MSHR misses 2754system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 24484 # number of overall MSHR misses 2755system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105282 # number of overall MSHR misses 2756system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25186 # number of overall MSHR misses 2757system.cpu1.l2cache.overall_mshr_misses::total 155763 # number of overall MSHR misses |
| 2734system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable | 2758system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable |
| 2735system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable 2736system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2981 # number of ReadReq MSHR uncacheable 2737system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable 2738system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable | 2759system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14314 # number of ReadReq MSHR uncacheable 2760system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14415 # number of ReadReq MSHR uncacheable 2761system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable 2762system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11648 # number of WriteReq MSHR uncacheable |
| 2739system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses | 2763system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses |
| 2740system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses 2741system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5211 # number of overall MSHR uncacheable misses 2742system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of ReadReq MSHR miss cycles 2743system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4342500 # number of ReadReq MSHR miss cycles 2744system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12091000 # number of ReadReq MSHR miss cycles 2745system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of HardPFReq MSHR miss cycles 2746system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1098165233 # number of HardPFReq MSHR miss cycles 2747system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453245500 # number of UpgradeReq MSHR miss cycles 2748system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453245500 # number of UpgradeReq MSHR miss cycles 2749system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353298500 # number of SCUpgradeReq MSHR miss cycles 2750system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353298500 # number of SCUpgradeReq MSHR miss cycles 2751system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 347499 # number of SCUpgradeFailReq MSHR miss cycles 2752system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 347499 # number of SCUpgradeFailReq MSHR miss cycles 2753system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1209651000 # number of ReadExReq MSHR miss cycles 2754system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1209651000 # number of ReadExReq MSHR miss cycles 2755system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 801689000 # number of ReadCleanReq MSHR miss cycles 2756system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 801689000 # number of ReadCleanReq MSHR miss cycles 2757system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1215836497 # number of ReadSharedReq MSHR miss cycles 2758system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1215836497 # number of ReadSharedReq MSHR miss cycles 2759system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of demand (read+write) MSHR miss cycles 2760system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4342500 # number of demand (read+write) MSHR miss cycles 2761system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 801689000 # number of demand (read+write) MSHR miss cycles 2762system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2425487497 # number of demand (read+write) MSHR miss cycles 2763system.cpu1.l2cache.demand_mshr_miss_latency::total 3239267497 # number of demand (read+write) MSHR miss cycles 2764system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of overall MSHR miss cycles 2765system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4342500 # number of overall MSHR miss cycles 2766system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 801689000 # number of overall MSHR miss cycles 2767system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2425487497 # number of overall MSHR miss cycles 2768system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of overall MSHR miss cycles 2769system.cpu1.l2cache.overall_mshr_miss_latency::total 4337432730 # number of overall MSHR miss cycles 2770system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8906000 # number of ReadReq MSHR uncacheable cycles 2771system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 363460500 # number of ReadReq MSHR uncacheable cycles 2772system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 372366500 # number of ReadReq MSHR uncacheable cycles 2773system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8906000 # number of overall MSHR uncacheable cycles 2774system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 363460500 # number of overall MSHR uncacheable cycles 2775system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 372366500 # number of overall MSHR uncacheable cycles 2776system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for ReadReq accesses 2777system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for ReadReq accesses 2778system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses | 2764system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25962 # number of overall MSHR uncacheable misses 2765system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26063 # number of overall MSHR uncacheable misses 2766system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of ReadReq MSHR miss cycles 2767system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4240500 # number of ReadReq MSHR miss cycles 2768system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12261000 # number of ReadReq MSHR miss cycles 2769system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1092841786 # number of HardPFReq MSHR miss cycles 2770system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1092841786 # number of HardPFReq MSHR miss cycles 2771system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 456571000 # number of UpgradeReq MSHR miss cycles 2772system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 456571000 # number of UpgradeReq MSHR miss cycles 2773system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353660000 # number of SCUpgradeReq MSHR miss cycles 2774system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353660000 # number of SCUpgradeReq MSHR miss cycles 2775system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 322999 # number of SCUpgradeFailReq MSHR miss cycles 2776system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 322999 # number of SCUpgradeFailReq MSHR miss cycles 2777system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1211819000 # number of ReadExReq MSHR miss cycles 2778system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1211819000 # number of ReadExReq MSHR miss cycles 2779system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 855998500 # number of ReadCleanReq MSHR miss cycles 2780system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 855998500 # number of ReadCleanReq MSHR miss cycles 2781system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1224293499 # number of ReadSharedReq MSHR miss cycles 2782system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1224293499 # number of ReadSharedReq MSHR miss cycles 2783system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of demand (read+write) MSHR miss cycles 2784system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4240500 # number of demand (read+write) MSHR miss cycles 2785system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 855998500 # number of demand (read+write) MSHR miss cycles 2786system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2436112499 # number of demand (read+write) MSHR miss cycles 2787system.cpu1.l2cache.demand_mshr_miss_latency::total 3304371999 # number of demand (read+write) MSHR miss cycles 2788system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of overall MSHR miss cycles 2789system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4240500 # number of overall MSHR miss cycles 2790system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 855998500 # number of overall MSHR miss cycles 2791system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2436112499 # number of overall MSHR miss cycles 2792system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1092841786 # number of overall MSHR miss cycles 2793system.cpu1.l2cache.overall_mshr_miss_latency::total 4397213785 # number of overall MSHR miss cycles 2794system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8742000 # number of ReadReq MSHR uncacheable cycles 2795system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2358114500 # number of ReadReq MSHR uncacheable cycles 2796system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2366856500 # number of ReadReq MSHR uncacheable cycles 2797system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8742000 # number of overall MSHR uncacheable cycles 2798system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2358114500 # number of overall MSHR uncacheable cycles 2799system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2366856500 # number of overall MSHR uncacheable cycles 2800system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for ReadReq accesses 2801system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for ReadReq accesses 2802system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032405 # mshr miss rate for ReadReq accesses 2803system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for WritebackDirty accesses 2804system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000009 # mshr miss rate for WritebackDirty accesses |
| 2779system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2780system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2781system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2782system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2783system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2784system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2785system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2786system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2805system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2806system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2807system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2808system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2809system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2810system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2811system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2812system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2787system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548609 # mshr miss rate for ReadExReq accesses 2788system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548609 # mshr miss rate for ReadExReq accesses 2789system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for ReadCleanReq accesses 2790system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040220 # mshr miss rate for ReadCleanReq accesses 2791system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.421234 # mshr miss rate for ReadSharedReq accesses 2792system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.421234 # mshr miss rate for ReadSharedReq accesses 2793system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for demand accesses 2794system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for demand accesses 2795system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for demand accesses 2796system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for demand accesses 2797system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152511 # mshr miss rate for demand accesses 2798system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for overall accesses 2799system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for overall accesses 2800system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for overall accesses 2801system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for overall accesses | 2813system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547993 # mshr miss rate for ReadExReq accesses 2814system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547993 # mshr miss rate for ReadExReq accesses 2815system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for ReadCleanReq accesses 2816system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040833 # mshr miss rate for ReadCleanReq accesses 2817system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420784 # mshr miss rate for ReadSharedReq accesses 2818system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420784 # mshr miss rate for ReadSharedReq accesses 2819system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for demand accesses 2820system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for demand accesses 2821system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for demand accesses 2822system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for demand accesses 2823system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152482 # mshr miss rate for demand accesses 2824system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for overall accesses 2825system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for overall accesses 2826system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for overall accesses 2827system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for overall accesses |
| 2802system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2828system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2803system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181923 # mshr miss rate for overall accesses 2804system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average ReadReq mshr miss latency 2805system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average ReadReq mshr miss latency 2806system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15057.285181 # average ReadReq mshr miss latency 2807system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average HardPFReq mshr miss latency 2808system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43919.582187 # average HardPFReq mshr miss latency 2809system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15385.115411 # average UpgradeReq mshr miss latency 2810system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15385.115411 # average UpgradeReq mshr miss latency 2811system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.836404 # average SCUpgradeReq mshr miss latency 2812system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.836404 # average SCUpgradeReq mshr miss latency 2813system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347499 # average SCUpgradeFailReq mshr miss latency 2814system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347499 # average SCUpgradeFailReq mshr miss latency 2815system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36135.952203 # average ReadExReq mshr miss latency 2816system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36135.952203 # average ReadExReq mshr miss latency 2817system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average ReadCleanReq mshr miss latency 2818system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33473.444676 # average ReadCleanReq mshr miss latency 2819system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17022.085444 # average ReadSharedReq mshr miss latency 2820system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17022.085444 # average ReadSharedReq mshr miss latency 2821system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency 2822system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency 2823system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency 2824system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency 2825system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24983.745301 # average overall mshr miss latency 2826system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency 2827system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency 2828system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency 2829system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency 2830system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average overall mshr miss latency 2831system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28045.136268 # average overall mshr miss latency 2832system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average ReadReq mshr uncacheable latency 2833system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126201.562500 # average ReadReq mshr uncacheable latency 2834system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124913.284133 # average ReadReq mshr uncacheable latency 2835system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average overall mshr uncacheable latency 2836system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 71127.299413 # average overall mshr uncacheable latency 2837system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 71457.781616 # average overall mshr uncacheable latency 2838system.cpu1.toL2Bus.snoop_filter.tot_requests 1670520 # Total number of requests made to the snoop filter. 2839system.cpu1.toL2Bus.snoop_filter.hit_single_requests 844468 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2840system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2841system.cpu1.toL2Bus.snoop_filter.tot_snoops 115035 # Total number of snoops made to the snoop filter. 2842system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106284 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2843system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8751 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2844system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 2845system.cpu1.toL2Bus.trans_dist::ReadReq 31435 # Transaction distribution 2846system.cpu1.toL2Bus.trans_dist::ReadResp 834833 # Transaction distribution 2847system.cpu1.toL2Bus.trans_dist::WriteReq 2230 # Transaction distribution 2848system.cpu1.toL2Bus.trans_dist::WriteResp 2230 # Transaction distribution 2849system.cpu1.toL2Bus.trans_dist::WritebackDirty 146689 # Transaction distribution 2850system.cpu1.toL2Bus.trans_dist::WritebackClean 667575 # Transaction distribution 2851system.cpu1.toL2Bus.trans_dist::CleanEvict 29225 # Transaction distribution 2852system.cpu1.toL2Bus.trans_dist::HardPFReq 30255 # Transaction distribution 2853system.cpu1.toL2Bus.trans_dist::UpgradeReq 73183 # Transaction distribution 2854system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41990 # Transaction distribution 2855system.cpu1.toL2Bus.trans_dist::UpgradeResp 85875 # Transaction distribution | 2829system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181893 # mshr miss rate for overall accesses 2830system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average ReadReq mshr miss latency 2831system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average ReadReq mshr miss latency 2832system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15118.372380 # average ReadReq mshr miss latency 2833system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average HardPFReq mshr miss latency 2834system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43390.843564 # average HardPFReq mshr miss latency 2835system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.860788 # average UpgradeReq mshr miss latency 2836system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.860788 # average UpgradeReq mshr miss latency 2837system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14958.338620 # average SCUpgradeReq mshr miss latency 2838system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14958.338620 # average SCUpgradeReq mshr miss latency 2839system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 322999 # average SCUpgradeFailReq mshr miss latency 2840system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 322999 # average SCUpgradeFailReq mshr miss latency 2841system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36147.804558 # average ReadExReq mshr miss latency 2842system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.804558 # average ReadExReq mshr miss latency 2843system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average ReadCleanReq mshr miss latency 2844system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34961.546316 # average ReadCleanReq mshr miss latency 2845system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17061.421709 # average ReadSharedReq mshr miss latency 2846system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17061.421709 # average ReadSharedReq mshr miss latency 2847system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency 2848system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency 2849system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency 2850system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency 2851system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25305.926764 # average overall mshr miss latency 2852system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency 2853system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency 2854system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency 2855system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency 2856system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average overall mshr miss latency 2857system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28230.155974 # average overall mshr miss latency 2858system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average ReadReq mshr uncacheable latency 2859system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164741.826184 # average ReadReq mshr uncacheable latency 2860system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164193.999306 # average ReadReq mshr uncacheable latency 2861system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average overall mshr uncacheable latency 2862system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90829.462291 # average overall mshr uncacheable latency 2863system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90812.895676 # average overall mshr uncacheable latency 2864system.cpu1.toL2Bus.snoop_filter.tot_requests 1681326 # Total number of requests made to the snoop filter. 2865system.cpu1.toL2Bus.snoop_filter.hit_single_requests 850022 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2866system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12491 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2867system.cpu1.toL2Bus.snoop_filter.tot_snoops 115149 # Total number of snoops made to the snoop filter. 2868system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2869system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8768 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2870system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 2871system.cpu1.toL2Bus.trans_dist::ReadReq 43982 # Transaction distribution 2872system.cpu1.toL2Bus.trans_dist::ReadResp 852476 # Transaction distribution 2873system.cpu1.toL2Bus.trans_dist::WriteReq 11648 # Transaction distribution 2874system.cpu1.toL2Bus.trans_dist::WriteResp 11648 # Transaction distribution 2875system.cpu1.toL2Bus.trans_dist::WritebackDirty 147635 # Transaction distribution 2876system.cpu1.toL2Bus.trans_dist::WritebackClean 672194 # Transaction distribution 2877system.cpu1.toL2Bus.trans_dist::CleanEvict 29901 # Transaction distribution 2878system.cpu1.toL2Bus.trans_dist::HardPFReq 30357 # Transaction distribution 2879system.cpu1.toL2Bus.trans_dist::UpgradeReq 73327 # Transaction distribution 2880system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution 2881system.cpu1.toL2Bus.trans_dist::UpgradeResp 86118 # Transaction distribution |
| 2856system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2857system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution | 2882system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2883system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution |
| 2858system.cpu1.toL2Bus.trans_dist::ReadExReq 68405 # Transaction distribution 2859system.cpu1.toL2Bus.trans_dist::ReadExResp 65523 # Transaction distribution 2860system.cpu1.toL2Bus.trans_dist::ReadCleanReq 595484 # Transaction distribution 2861system.cpu1.toL2Bus.trans_dist::ReadSharedReq 273707 # Transaction distribution 2862system.cpu1.toL2Bus.trans_dist::InvalidateReq 370 # Transaction distribution 2863system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1786136 # Packet count per connected master and slave (bytes) 2864system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839744 # Packet count per connected master and slave (bytes) 2865system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14453 # Packet count per connected master and slave (bytes) 2866system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38068 # Packet count per connected master and slave (bytes) 2867system.cpu1.toL2Bus.pkt_count::total 2678401 # Packet count per connected master and slave (bytes) 2868system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76190416 # Cumulative packet size per connected master and slave (bytes) 2869system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29457424 # Cumulative packet size per connected master and slave (bytes) 2870system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26024 # Cumulative packet size per connected master and slave (bytes) 2871system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70244 # Cumulative packet size per connected master and slave (bytes) 2872system.cpu1.toL2Bus.pkt_size::total 105744108 # Cumulative packet size per connected master and slave (bytes) 2873system.cpu1.toL2Bus.snoops 346325 # Total snoops (count) 2874system.cpu1.toL2Bus.snoopTraffic 4857548 # Total snoop traffic (bytes) 2875system.cpu1.toL2Bus.snoop_fanout::samples 1179057 # Request fanout histogram 2876system.cpu1.toL2Bus.snoop_fanout::mean 0.123952 # Request fanout histogram 2877system.cpu1.toL2Bus.snoop_fanout::stdev 0.351329 # Request fanout histogram | 2884system.cpu1.toL2Bus.trans_dist::ReadExReq 68535 # Transaction distribution 2885system.cpu1.toL2Bus.trans_dist::ReadExResp 65700 # Transaction distribution 2886system.cpu1.toL2Bus.trans_dist::ReadCleanReq 599608 # Transaction distribution 2887system.cpu1.toL2Bus.trans_dist::ReadSharedReq 274791 # Transaction distribution 2888system.cpu1.toL2Bus.trans_dist::InvalidateReq 374 # Transaction distribution 2889system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1798508 # Packet count per connected master and slave (bytes) 2890system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885295 # Packet count per connected master and slave (bytes) 2891system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16392 # Packet count per connected master and slave (bytes) 2892system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38202 # Packet count per connected master and slave (bytes) 2893system.cpu1.toL2Bus.pkt_count::total 2738397 # Packet count per connected master and slave (bytes) 2894system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76718288 # Cumulative packet size per connected master and slave (bytes) 2895system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29683872 # Cumulative packet size per connected master and slave (bytes) 2896system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29716 # Cumulative packet size per connected master and slave (bytes) 2897system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70392 # Cumulative packet size per connected master and slave (bytes) 2898system.cpu1.toL2Bus.pkt_size::total 106502268 # Cumulative packet size per connected master and slave (bytes) 2899system.cpu1.toL2Bus.snoops 347702 # Total snoops (count) 2900system.cpu1.toL2Bus.snoopTraffic 4882288 # Total snoop traffic (bytes) 2901system.cpu1.toL2Bus.snoop_fanout::samples 1207717 # Request fanout histogram 2902system.cpu1.toL2Bus.snoop_fanout::mean 0.121214 # Request fanout histogram 2903system.cpu1.toL2Bus.snoop_fanout::stdev 0.347910 # Request fanout histogram |
| 2878system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2904system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2879system.cpu1.toL2Bus.snoop_fanout::0 1041662 88.35% 88.35% # Request fanout histogram 2880system.cpu1.toL2Bus.snoop_fanout::1 128644 10.91% 99.26% # Request fanout histogram 2881system.cpu1.toL2Bus.snoop_fanout::2 8751 0.74% 100.00% # Request fanout histogram | 2905system.cpu1.toL2Bus.snoop_fanout::0 1070093 88.60% 88.60% # Request fanout histogram 2906system.cpu1.toL2Bus.snoop_fanout::1 128856 10.67% 99.27% # Request fanout histogram 2907system.cpu1.toL2Bus.snoop_fanout::2 8768 0.73% 100.00% # Request fanout histogram |
| 2882system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2883system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2884system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2908system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2909system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2910system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2885system.cpu1.toL2Bus.snoop_fanout::total 1179057 # Request fanout histogram 2886system.cpu1.toL2Bus.reqLayer0.occupancy 1629779992 # Layer occupancy (ticks) | 2911system.cpu1.toL2Bus.snoop_fanout::total 1207717 # Request fanout histogram 2912system.cpu1.toL2Bus.reqLayer0.occupancy 1656031495 # Layer occupancy (ticks) |
| 2887system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 2913system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 2888system.cpu1.toL2Bus.snoopLayer0.occupancy 80742792 # Layer occupancy (ticks) | 2914system.cpu1.toL2Bus.snoopLayer0.occupancy 80775328 # Layer occupancy (ticks) |
| 2889system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2915system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2890system.cpu1.toL2Bus.respLayer0.occupancy 893427297 # Layer occupancy (ticks) | 2916system.cpu1.toL2Bus.respLayer0.occupancy 899618286 # Layer occupancy (ticks) |
| 2891system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2917system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2892system.cpu1.toL2Bus.respLayer1.occupancy 378082159 # Layer occupancy (ticks) | 2918system.cpu1.toL2Bus.respLayer1.occupancy 396030671 # Layer occupancy (ticks) |
| 2893system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2919system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2894system.cpu1.toL2Bus.respLayer2.occupancy 7957978 # Layer occupancy (ticks) | 2920system.cpu1.toL2Bus.respLayer2.occupancy 8974477 # Layer occupancy (ticks) |
| 2895system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2921system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2896system.cpu1.toL2Bus.respLayer3.occupancy 20520473 # Layer occupancy (ticks) | 2922system.cpu1.toL2Bus.respLayer3.occupancy 20614978 # Layer occupancy (ticks) |
| 2897system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2923system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2898system.iobus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 2924system.iobus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 2899system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2900system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2901system.iobus.trans_dist::WriteReq 59420 # Transaction distribution 2902system.iobus.trans_dist::WriteResp 59420 # Transaction distribution 2903system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56598 # Packet count per connected master and slave (bytes) 2904system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2905system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2906system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 2941system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2942system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2943system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2944system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2945system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes) 2946system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2947system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2948system.iobus.pkt_size::total 2484040 # Cumulative packet size per connected master and slave (bytes) | 2925system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2926system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2927system.iobus.trans_dist::WriteReq 59420 # Transaction distribution 2928system.iobus.trans_dist::WriteResp 59420 # Transaction distribution 2929system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56598 # Packet count per connected master and slave (bytes) 2930system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2931system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2932system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 2967system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2968system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2969system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2970system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2971system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes) 2972system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2973system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2974system.iobus.pkt_size::total 2484040 # Cumulative packet size per connected master and slave (bytes) |
| 2949system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks) | 2975system.iobus.reqLayer0.occupancy 40387001 # Layer occupancy (ticks) |
| 2950system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2976system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2951system.iobus.reqLayer1.occupancy 114000 # Layer occupancy (ticks) | 2977system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) |
| 2952system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2953system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks) 2954system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2978system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2979system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks) 2980system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2955system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) | 2981system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) |
| 2956system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2957system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) 2958system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 2982system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2983system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) 2984system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 2959system.iobus.reqLayer7.occupancy 90000 # Layer occupancy (ticks) | 2985system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) |
| 2960system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 2986system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 2961system.iobus.reqLayer8.occupancy 573500 # Layer occupancy (ticks) | 2987system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks) |
| 2962system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2963system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2964system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2965system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2966system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2967system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 2968system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2969system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) 2970system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2971system.iobus.reqLayer16.occupancy 53000 # Layer occupancy (ticks) 2972system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) | 2988system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2989system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2990system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2991system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2992system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2993system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 2994system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2995system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) 2996system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2997system.iobus.reqLayer16.occupancy 53000 # Layer occupancy (ticks) 2998system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) |
| 2973system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) | 2999system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) |
| 2974system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 3000system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 2975system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) | 3001system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) |
| 2976system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2977system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2978system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2979system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2980system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) | 3002system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 3003system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 3004system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 3005system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 3006system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) |
| 2981system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) | 3007system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) |
| 2982system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 3008system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 2983system.iobus.reqLayer23.occupancy 6114001 # Layer occupancy (ticks) | 3009system.iobus.reqLayer23.occupancy 6115000 # Layer occupancy (ticks) |
| 2984system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 3010system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 2985system.iobus.reqLayer24.occupancy 33826000 # Layer occupancy (ticks) | 3011system.iobus.reqLayer24.occupancy 33791000 # Layer occupancy (ticks) |
| 2986system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 3012system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 2987system.iobus.reqLayer25.occupancy 187862511 # Layer occupancy (ticks) | 3013system.iobus.reqLayer25.occupancy 187784301 # Layer occupancy (ticks) |
| 2988system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2989system.iobus.respLayer0.occupancy 84716000 # Layer occupancy (ticks) 2990system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2991system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2992system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 3014system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3015system.iobus.respLayer0.occupancy 84716000 # Layer occupancy (ticks) 3016system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3017system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 3018system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2993system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 3019system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 2994system.iocache.tags.replacements 36458 # number of replacements | 3020system.iocache.tags.replacements 36458 # number of replacements |
| 2995system.iocache.tags.tagsinuse 14.554422 # Cycle average of tags in use | 3021system.iocache.tags.tagsinuse 14.554359 # Cycle average of tags in use |
| 2996system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2997system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2998system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 3022system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3023system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 3024system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2999system.iocache.tags.warmup_cycle 255374847000 # Cycle when the warmup percentage was hit. 3000system.iocache.tags.occ_blocks::realview.ide 14.554422 # Average occupied blocks per requestor 3001system.iocache.tags.occ_percent::realview.ide 0.909651 # Average percentage of cache occupancy 3002system.iocache.tags.occ_percent::total 0.909651 # Average percentage of cache occupancy | 3025system.iocache.tags.warmup_cycle 255387586000 # Cycle when the warmup percentage was hit. 3026system.iocache.tags.occ_blocks::realview.ide 14.554359 # Average occupied blocks per requestor 3027system.iocache.tags.occ_percent::realview.ide 0.909647 # Average percentage of cache occupancy 3028system.iocache.tags.occ_percent::total 0.909647 # Average percentage of cache occupancy |
| 3003system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3004system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3005system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3006system.iocache.tags.tag_accesses 328284 # Number of tag accesses 3007system.iocache.tags.data_accesses 328284 # Number of data accesses | 3029system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3030system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3031system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3032system.iocache.tags.tag_accesses 328284 # Number of tag accesses 3033system.iocache.tags.data_accesses 328284 # Number of data accesses |
| 3008system.iocache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 3034system.iocache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 3009system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 3010system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 3011system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 3012system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 3013system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 3014system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 3015system.iocache.overall_misses::realview.ide 36476 # number of overall misses 3016system.iocache.overall_misses::total 36476 # number of overall misses | 3035system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 3036system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 3037system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 3038system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 3039system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 3040system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 3041system.iocache.overall_misses::realview.ide 36476 # number of overall misses 3042system.iocache.overall_misses::total 36476 # number of overall misses |
| 3017system.iocache.ReadReq_miss_latency::realview.ide 39163375 # number of ReadReq miss cycles 3018system.iocache.ReadReq_miss_latency::total 39163375 # number of ReadReq miss cycles 3019system.iocache.WriteLineReq_miss_latency::realview.ide 4357678136 # number of WriteLineReq miss cycles 3020system.iocache.WriteLineReq_miss_latency::total 4357678136 # number of WriteLineReq miss cycles 3021system.iocache.demand_miss_latency::realview.ide 4396841511 # number of demand (read+write) miss cycles 3022system.iocache.demand_miss_latency::total 4396841511 # number of demand (read+write) miss cycles 3023system.iocache.overall_miss_latency::realview.ide 4396841511 # number of overall miss cycles 3024system.iocache.overall_miss_latency::total 4396841511 # number of overall miss cycles | 3043system.iocache.ReadReq_miss_latency::realview.ide 40605876 # number of ReadReq miss cycles 3044system.iocache.ReadReq_miss_latency::total 40605876 # number of ReadReq miss cycles 3045system.iocache.WriteLineReq_miss_latency::realview.ide 4346476425 # number of WriteLineReq miss cycles 3046system.iocache.WriteLineReq_miss_latency::total 4346476425 # number of WriteLineReq miss cycles 3047system.iocache.demand_miss_latency::realview.ide 4387082301 # number of demand (read+write) miss cycles 3048system.iocache.demand_miss_latency::total 4387082301 # number of demand (read+write) miss cycles 3049system.iocache.overall_miss_latency::realview.ide 4387082301 # number of overall miss cycles 3050system.iocache.overall_miss_latency::total 4387082301 # number of overall miss cycles |
| 3025system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 3026system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 3027system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 3028system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 3029system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 3030system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 3031system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 3032system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 3033system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3034system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3035system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3036system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3037system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3038system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3039system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3040system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 3051system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 3052system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 3053system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 3054system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 3055system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 3056system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 3057system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 3058system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 3059system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3060system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3061system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3062system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3063system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3064system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3065system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3066system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 3041system.iocache.ReadReq_avg_miss_latency::realview.ide 155410.218254 # average ReadReq miss latency 3042system.iocache.ReadReq_avg_miss_latency::total 155410.218254 # average ReadReq miss latency 3043system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120298.093419 # average WriteLineReq miss latency 3044system.iocache.WriteLineReq_avg_miss_latency::total 120298.093419 # average WriteLineReq miss latency 3045system.iocache.demand_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency 3046system.iocache.demand_avg_miss_latency::total 120540.670879 # average overall miss latency 3047system.iocache.overall_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency 3048system.iocache.overall_avg_miss_latency::total 120540.670879 # average overall miss latency 3049system.iocache.blocked_cycles::no_mshrs 87 # number of cycles access was blocked | 3067system.iocache.ReadReq_avg_miss_latency::realview.ide 161134.428571 # average ReadReq miss latency 3068system.iocache.ReadReq_avg_miss_latency::total 161134.428571 # average ReadReq miss latency 3069system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119988.858906 # average WriteLineReq miss latency 3070system.iocache.WriteLineReq_avg_miss_latency::total 119988.858906 # average WriteLineReq miss latency 3071system.iocache.demand_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency 3072system.iocache.demand_avg_miss_latency::total 120273.119339 # average overall miss latency 3073system.iocache.overall_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency 3074system.iocache.overall_avg_miss_latency::total 120273.119339 # average overall miss latency 3075system.iocache.blocked_cycles::no_mshrs 191 # number of cycles access was blocked |
| 3050system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3076system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3051system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked | 3077system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked |
| 3052system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 3078system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 3053system.iocache.avg_blocked_cycles::no_mshrs 21.750000 # average number of cycles each access was blocked | 3079system.iocache.avg_blocked_cycles::no_mshrs 63.666667 # average number of cycles each access was blocked |
| 3054system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3055system.iocache.writebacks::writebacks 36206 # number of writebacks 3056system.iocache.writebacks::total 36206 # number of writebacks 3057system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3058system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3059system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3060system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3061system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 3062system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 3063system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 3064system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses | 3080system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3081system.iocache.writebacks::writebacks 36206 # number of writebacks 3082system.iocache.writebacks::total 36206 # number of writebacks 3083system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3084system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3085system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3086system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3087system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 3088system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 3089system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 3090system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses |
| 3065system.iocache.ReadReq_mshr_miss_latency::realview.ide 26563375 # number of ReadReq MSHR miss cycles 3066system.iocache.ReadReq_mshr_miss_latency::total 26563375 # number of ReadReq MSHR miss cycles 3067system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2544616232 # number of WriteLineReq MSHR miss cycles 3068system.iocache.WriteLineReq_mshr_miss_latency::total 2544616232 # number of WriteLineReq MSHR miss cycles 3069system.iocache.demand_mshr_miss_latency::realview.ide 2571179607 # number of demand (read+write) MSHR miss cycles 3070system.iocache.demand_mshr_miss_latency::total 2571179607 # number of demand (read+write) MSHR miss cycles 3071system.iocache.overall_mshr_miss_latency::realview.ide 2571179607 # number of overall MSHR miss cycles 3072system.iocache.overall_mshr_miss_latency::total 2571179607 # number of overall MSHR miss cycles | 3091system.iocache.ReadReq_mshr_miss_latency::realview.ide 28005876 # number of ReadReq MSHR miss cycles 3092system.iocache.ReadReq_mshr_miss_latency::total 28005876 # number of ReadReq MSHR miss cycles 3093system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2533401277 # number of WriteLineReq MSHR miss cycles 3094system.iocache.WriteLineReq_mshr_miss_latency::total 2533401277 # number of WriteLineReq MSHR miss cycles 3095system.iocache.demand_mshr_miss_latency::realview.ide 2561407153 # number of demand (read+write) MSHR miss cycles 3096system.iocache.demand_mshr_miss_latency::total 2561407153 # number of demand (read+write) MSHR miss cycles 3097system.iocache.overall_mshr_miss_latency::realview.ide 2561407153 # number of overall MSHR miss cycles 3098system.iocache.overall_mshr_miss_latency::total 2561407153 # number of overall MSHR miss cycles |
| 3073system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3074system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3075system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3076system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3077system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3078system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3079system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3080system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 3099system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3100system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3101system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3102system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3103system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3104system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3105system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3106system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 3081system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105410.218254 # average ReadReq mshr miss latency 3082system.iocache.ReadReq_avg_mshr_miss_latency::total 105410.218254 # average ReadReq mshr miss latency 3083system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70246.693684 # average WriteLineReq mshr miss latency 3084system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70246.693684 # average WriteLineReq mshr miss latency 3085system.iocache.demand_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency 3086system.iocache.demand_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency 3087system.iocache.overall_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency 3088system.iocache.overall_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency 3089system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3090system.l2c.tags.replacements 137305 # number of replacements 3091system.l2c.tags.tagsinuse 65135.020938 # Cycle average of tags in use 3092system.l2c.tags.total_refs 548309 # Total number of references to valid blocks. 3093system.l2c.tags.sampled_refs 202660 # Sample count of references to valid blocks. 3094system.l2c.tags.avg_refs 2.705561 # Average number of references to valid blocks. 3095system.l2c.tags.warmup_cycle 87489923000 # Cycle when the warmup percentage was hit. 3096system.l2c.tags.occ_blocks::writebacks 6043.335191 # Average occupied blocks per requestor 3097system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.875782 # Average occupied blocks per requestor 3098system.l2c.tags.occ_blocks::cpu0.itb.walker 1.068168 # Average occupied blocks per requestor 3099system.l2c.tags.occ_blocks::cpu0.inst 8238.246856 # Average occupied blocks per requestor 3100system.l2c.tags.occ_blocks::cpu0.data 6901.068519 # Average occupied blocks per requestor 3101system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37215.588563 # Average occupied blocks per requestor 3102system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.685294 # Average occupied blocks per requestor 3103system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909748 # Average occupied blocks per requestor 3104system.l2c.tags.occ_blocks::cpu1.inst 1676.975803 # Average occupied blocks per requestor 3105system.l2c.tags.occ_blocks::cpu1.data 3036.574639 # Average occupied blocks per requestor 3106system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2001.692374 # Average occupied blocks per requestor 3107system.l2c.tags.occ_percent::writebacks 0.092214 # Average percentage of cache occupancy 3108system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000258 # Average percentage of cache occupancy | 3107system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111134.428571 # average ReadReq mshr miss latency 3108system.iocache.ReadReq_avg_mshr_miss_latency::total 111134.428571 # average ReadReq mshr miss latency 3109system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69937.093557 # average WriteLineReq mshr miss latency 3110system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69937.093557 # average WriteLineReq mshr miss latency 3111system.iocache.demand_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency 3112system.iocache.demand_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency 3113system.iocache.overall_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency 3114system.iocache.overall_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency 3115system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3116system.l2c.tags.replacements 137443 # number of replacements 3117system.l2c.tags.tagsinuse 65137.298659 # Cycle average of tags in use 3118system.l2c.tags.total_refs 547823 # Total number of references to valid blocks. 3119system.l2c.tags.sampled_refs 202801 # Sample count of references to valid blocks. 3120system.l2c.tags.avg_refs 2.701284 # Average number of references to valid blocks. 3121system.l2c.tags.warmup_cycle 87493786000 # Cycle when the warmup percentage was hit. 3122system.l2c.tags.occ_blocks::writebacks 6068.008119 # Average occupied blocks per requestor 3123system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.951872 # Average occupied blocks per requestor 3124system.l2c.tags.occ_blocks::cpu0.itb.walker 1.052619 # Average occupied blocks per requestor 3125system.l2c.tags.occ_blocks::cpu0.inst 7988.261154 # Average occupied blocks per requestor 3126system.l2c.tags.occ_blocks::cpu0.data 6937.855049 # Average occupied blocks per requestor 3127system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37116.430492 # Average occupied blocks per requestor 3128system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.708460 # Average occupied blocks per requestor 3129system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909745 # Average occupied blocks per requestor 3130system.l2c.tags.occ_blocks::cpu1.inst 1897.444635 # Average occupied blocks per requestor 3131system.l2c.tags.occ_blocks::cpu1.data 3115.453147 # Average occupied blocks per requestor 3132system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1993.223368 # Average occupied blocks per requestor 3133system.l2c.tags.occ_percent::writebacks 0.092590 # Average percentage of cache occupancy 3134system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000228 # Average percentage of cache occupancy |
| 3109system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy | 3135system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy |
| 3110system.l2c.tags.occ_percent::cpu0.inst 0.125706 # Average percentage of cache occupancy 3111system.l2c.tags.occ_percent::cpu0.data 0.105302 # Average percentage of cache occupancy 3112system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567865 # Average percentage of cache occupancy 3113system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy | 3136system.l2c.tags.occ_percent::cpu0.inst 0.121891 # Average percentage of cache occupancy 3137system.l2c.tags.occ_percent::cpu0.data 0.105863 # Average percentage of cache occupancy 3138system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.566352 # Average percentage of cache occupancy 3139system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000057 # Average percentage of cache occupancy |
| 3114system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy | 3140system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy |
| 3115system.l2c.tags.occ_percent::cpu1.inst 0.025589 # Average percentage of cache occupancy 3116system.l2c.tags.occ_percent::cpu1.data 0.046334 # Average percentage of cache occupancy 3117system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030543 # Average percentage of cache occupancy 3118system.l2c.tags.occ_percent::total 0.993882 # Average percentage of cache occupancy 3119system.l2c.tags.occ_task_id_blocks::1022 33214 # Occupied blocks per task id 3120system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id 3121system.l2c.tags.occ_task_id_blocks::1024 32119 # Occupied blocks per task id | 3141system.l2c.tags.occ_percent::cpu1.inst 0.028953 # Average percentage of cache occupancy 3142system.l2c.tags.occ_percent::cpu1.data 0.047538 # Average percentage of cache occupancy 3143system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030414 # Average percentage of cache occupancy 3144system.l2c.tags.occ_percent::total 0.993916 # Average percentage of cache occupancy 3145system.l2c.tags.occ_task_id_blocks::1022 33259 # Occupied blocks per task id 3146system.l2c.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id 3147system.l2c.tags.occ_task_id_blocks::1024 32074 # Occupied blocks per task id |
| 3122system.l2c.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id | 3148system.l2c.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id |
| 3123system.l2c.tags.age_task_id_blocks_1022::3 6015 # Occupied blocks per task id 3124system.l2c.tags.age_task_id_blocks_1022::4 27014 # Occupied blocks per task id | 3149system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id 3150system.l2c.tags.age_task_id_blocks_1022::4 27100 # Occupied blocks per task id |
| 3125system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id | 3151system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id |
| 3126system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id | 3152system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id 3153system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id |
| 3127system.l2c.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id | 3154system.l2c.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id |
| 3128system.l2c.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id 3129system.l2c.tags.age_task_id_blocks_1024::3 4859 # Occupied blocks per task id 3130system.l2c.tags.age_task_id_blocks_1024::4 27124 # Occupied blocks per task id 3131system.l2c.tags.occ_task_id_percent::1022 0.506805 # Percentage of cache occupancy per task id 3132system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id 3133system.l2c.tags.occ_task_id_percent::1024 0.490097 # Percentage of cache occupancy per task id 3134system.l2c.tags.tag_accesses 6291007 # Number of tag accesses 3135system.l2c.tags.data_accesses 6291007 # Number of data accesses 3136system.l2c.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3137system.l2c.WritebackDirty_hits::writebacks 261222 # number of WritebackDirty hits 3138system.l2c.WritebackDirty_hits::total 261222 # number of WritebackDirty hits 3139system.l2c.UpgradeReq_hits::cpu0.data 41572 # number of UpgradeReq hits 3140system.l2c.UpgradeReq_hits::cpu1.data 4769 # number of UpgradeReq hits 3141system.l2c.UpgradeReq_hits::total 46341 # number of UpgradeReq hits 3142system.l2c.SCUpgradeReq_hits::cpu0.data 2758 # number of SCUpgradeReq hits 3143system.l2c.SCUpgradeReq_hits::cpu1.data 2241 # number of SCUpgradeReq hits 3144system.l2c.SCUpgradeReq_hits::total 4999 # number of SCUpgradeReq hits 3145system.l2c.ReadExReq_hits::cpu0.data 3976 # number of ReadExReq hits 3146system.l2c.ReadExReq_hits::cpu1.data 1584 # number of ReadExReq hits 3147system.l2c.ReadExReq_hits::total 5560 # number of ReadExReq hits 3148system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 265 # number of ReadSharedReq hits 3149system.l2c.ReadSharedReq_hits::cpu0.itb.walker 106 # number of ReadSharedReq hits 3150system.l2c.ReadSharedReq_hits::cpu0.inst 50549 # number of ReadSharedReq hits 3151system.l2c.ReadSharedReq_hits::cpu0.data 57222 # number of ReadSharedReq hits 3152system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46457 # number of ReadSharedReq hits 3153system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 49 # number of ReadSharedReq hits 3154system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits 3155system.l2c.ReadSharedReq_hits::cpu1.inst 21200 # number of ReadSharedReq hits 3156system.l2c.ReadSharedReq_hits::cpu1.data 11593 # number of ReadSharedReq hits 3157system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4929 # number of ReadSharedReq hits 3158system.l2c.ReadSharedReq_hits::total 192388 # number of ReadSharedReq hits 3159system.l2c.demand_hits::cpu0.dtb.walker 265 # number of demand (read+write) hits 3160system.l2c.demand_hits::cpu0.itb.walker 106 # number of demand (read+write) hits 3161system.l2c.demand_hits::cpu0.inst 50549 # number of demand (read+write) hits 3162system.l2c.demand_hits::cpu0.data 61198 # number of demand (read+write) hits 3163system.l2c.demand_hits::cpu0.l2cache.prefetcher 46457 # number of demand (read+write) hits 3164system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits 3165system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits 3166system.l2c.demand_hits::cpu1.inst 21200 # number of demand (read+write) hits 3167system.l2c.demand_hits::cpu1.data 13177 # number of demand (read+write) hits 3168system.l2c.demand_hits::cpu1.l2cache.prefetcher 4929 # number of demand (read+write) hits 3169system.l2c.demand_hits::total 197948 # number of demand (read+write) hits 3170system.l2c.overall_hits::cpu0.dtb.walker 265 # number of overall hits 3171system.l2c.overall_hits::cpu0.itb.walker 106 # number of overall hits 3172system.l2c.overall_hits::cpu0.inst 50549 # number of overall hits 3173system.l2c.overall_hits::cpu0.data 61198 # number of overall hits 3174system.l2c.overall_hits::cpu0.l2cache.prefetcher 46457 # number of overall hits 3175system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits 3176system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits 3177system.l2c.overall_hits::cpu1.inst 21200 # number of overall hits 3178system.l2c.overall_hits::cpu1.data 13177 # number of overall hits 3179system.l2c.overall_hits::cpu1.l2cache.prefetcher 4929 # number of overall hits 3180system.l2c.overall_hits::total 197948 # number of overall hits 3181system.l2c.UpgradeReq_misses::cpu0.data 525 # number of UpgradeReq misses 3182system.l2c.UpgradeReq_misses::cpu1.data 273 # number of UpgradeReq misses 3183system.l2c.UpgradeReq_misses::total 798 # number of UpgradeReq misses 3184system.l2c.SCUpgradeReq_misses::cpu0.data 53 # number of SCUpgradeReq misses 3185system.l2c.SCUpgradeReq_misses::cpu1.data 86 # number of SCUpgradeReq misses 3186system.l2c.SCUpgradeReq_misses::total 139 # number of SCUpgradeReq misses 3187system.l2c.ReadExReq_misses::cpu0.data 11064 # number of ReadExReq misses 3188system.l2c.ReadExReq_misses::cpu1.data 8230 # number of ReadExReq misses 3189system.l2c.ReadExReq_misses::total 19294 # number of ReadExReq misses 3190system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses 3191system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses 3192system.l2c.ReadSharedReq_misses::cpu0.inst 19971 # number of ReadSharedReq misses 3193system.l2c.ReadSharedReq_misses::cpu0.data 9413 # number of ReadSharedReq misses 3194system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq misses 3195system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses | 3155system.l2c.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id 3156system.l2c.tags.age_task_id_blocks_1024::3 4863 # Occupied blocks per task id 3157system.l2c.tags.age_task_id_blocks_1024::4 27079 # Occupied blocks per task id 3158system.l2c.tags.occ_task_id_percent::1022 0.507492 # Percentage of cache occupancy per task id 3159system.l2c.tags.occ_task_id_percent::1023 0.000381 # Percentage of cache occupancy per task id 3160system.l2c.tags.occ_task_id_percent::1024 0.489410 # Percentage of cache occupancy per task id 3161system.l2c.tags.tag_accesses 6288814 # Number of tag accesses 3162system.l2c.tags.data_accesses 6288814 # Number of data accesses 3163system.l2c.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3164system.l2c.WritebackDirty_hits::writebacks 261149 # number of WritebackDirty hits 3165system.l2c.WritebackDirty_hits::total 261149 # number of WritebackDirty hits 3166system.l2c.UpgradeReq_hits::cpu0.data 41513 # number of UpgradeReq hits 3167system.l2c.UpgradeReq_hits::cpu1.data 4842 # number of UpgradeReq hits 3168system.l2c.UpgradeReq_hits::total 46355 # number of UpgradeReq hits 3169system.l2c.SCUpgradeReq_hits::cpu0.data 2681 # number of SCUpgradeReq hits 3170system.l2c.SCUpgradeReq_hits::cpu1.data 2272 # number of SCUpgradeReq hits 3171system.l2c.SCUpgradeReq_hits::total 4953 # number of SCUpgradeReq hits 3172system.l2c.ReadExReq_hits::cpu0.data 4003 # number of ReadExReq hits 3173system.l2c.ReadExReq_hits::cpu1.data 1563 # number of ReadExReq hits 3174system.l2c.ReadExReq_hits::total 5566 # number of ReadExReq hits 3175system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 282 # number of ReadSharedReq hits 3176system.l2c.ReadSharedReq_hits::cpu0.itb.walker 80 # number of ReadSharedReq hits 3177system.l2c.ReadSharedReq_hits::cpu0.inst 50115 # number of ReadSharedReq hits 3178system.l2c.ReadSharedReq_hits::cpu0.data 57309 # number of ReadSharedReq hits 3179system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46378 # number of ReadSharedReq hits 3180system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 44 # number of ReadSharedReq hits 3181system.l2c.ReadSharedReq_hits::cpu1.itb.walker 17 # number of ReadSharedReq hits 3182system.l2c.ReadSharedReq_hits::cpu1.inst 21480 # number of ReadSharedReq hits 3183system.l2c.ReadSharedReq_hits::cpu1.data 11675 # number of ReadSharedReq hits 3184system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4930 # number of ReadSharedReq hits 3185system.l2c.ReadSharedReq_hits::total 192310 # number of ReadSharedReq hits 3186system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits 3187system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits 3188system.l2c.demand_hits::cpu0.inst 50115 # number of demand (read+write) hits 3189system.l2c.demand_hits::cpu0.data 61312 # number of demand (read+write) hits 3190system.l2c.demand_hits::cpu0.l2cache.prefetcher 46378 # number of demand (read+write) hits 3191system.l2c.demand_hits::cpu1.dtb.walker 44 # number of demand (read+write) hits 3192system.l2c.demand_hits::cpu1.itb.walker 17 # number of demand (read+write) hits 3193system.l2c.demand_hits::cpu1.inst 21480 # number of demand (read+write) hits 3194system.l2c.demand_hits::cpu1.data 13238 # number of demand (read+write) hits 3195system.l2c.demand_hits::cpu1.l2cache.prefetcher 4930 # number of demand (read+write) hits 3196system.l2c.demand_hits::total 197876 # number of demand (read+write) hits 3197system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits 3198system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits 3199system.l2c.overall_hits::cpu0.inst 50115 # number of overall hits 3200system.l2c.overall_hits::cpu0.data 61312 # number of overall hits 3201system.l2c.overall_hits::cpu0.l2cache.prefetcher 46378 # number of overall hits 3202system.l2c.overall_hits::cpu1.dtb.walker 44 # number of overall hits 3203system.l2c.overall_hits::cpu1.itb.walker 17 # number of overall hits 3204system.l2c.overall_hits::cpu1.inst 21480 # number of overall hits 3205system.l2c.overall_hits::cpu1.data 13238 # number of overall hits 3206system.l2c.overall_hits::cpu1.l2cache.prefetcher 4930 # number of overall hits 3207system.l2c.overall_hits::total 197876 # number of overall hits 3208system.l2c.UpgradeReq_misses::cpu0.data 453 # number of UpgradeReq misses 3209system.l2c.UpgradeReq_misses::cpu1.data 282 # number of UpgradeReq misses 3210system.l2c.UpgradeReq_misses::total 735 # number of UpgradeReq misses 3211system.l2c.SCUpgradeReq_misses::cpu0.data 99 # number of SCUpgradeReq misses 3212system.l2c.SCUpgradeReq_misses::cpu1.data 81 # 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| 3207system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses | 3234system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses |
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| 3218system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses | 3245system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses |
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number of demand (read+write) miss cycles 3251system.l2c.demand_miss_latency::cpu1.data 895828000 # number of demand (read+write) miss cycles 3252system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of demand (read+write) miss cycles 3253system.l2c.demand_miss_latency::total 23354340820 # number of demand (read+write) miss cycles 3254system.l2c.overall_miss_latency::cpu0.dtb.walker 4012500 # number of overall miss cycles 3255system.l2c.overall_miss_latency::cpu0.itb.walker 353000 # number of overall miss cycles 3256system.l2c.overall_miss_latency::cpu0.inst 2097163000 # number of overall miss cycles 3257system.l2c.overall_miss_latency::cpu0.data 2753889500 # number of overall miss cycles 3258system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of overall miss cycles 3259system.l2c.overall_miss_latency::cpu1.dtb.walker 538500 # number of overall miss cycles 3260system.l2c.overall_miss_latency::cpu1.itb.walker 90000 # number of overall miss cycles 3261system.l2c.overall_miss_latency::cpu1.inst 295133500 # number of overall miss cycles 3262system.l2c.overall_miss_latency::cpu1.data 895828000 # number of overall miss cycles 3263system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of overall miss cycles 3264system.l2c.overall_miss_latency::total 23354340820 # number of overall miss cycles 3265system.l2c.WritebackDirty_accesses::writebacks 261222 # number of WritebackDirty accesses(hits+misses) 3266system.l2c.WritebackDirty_accesses::total 261222 # number of WritebackDirty accesses(hits+misses) 3267system.l2c.UpgradeReq_accesses::cpu0.data 42097 # number of UpgradeReq accesses(hits+misses) 3268system.l2c.UpgradeReq_accesses::cpu1.data 5042 # number of UpgradeReq accesses(hits+misses) 3269system.l2c.UpgradeReq_accesses::total 47139 # number of UpgradeReq accesses(hits+misses) 3270system.l2c.SCUpgradeReq_accesses::cpu0.data 2811 # number of SCUpgradeReq accesses(hits+misses) 3271system.l2c.SCUpgradeReq_accesses::cpu1.data 2327 # number of SCUpgradeReq accesses(hits+misses) 3272system.l2c.SCUpgradeReq_accesses::total 5138 # number of SCUpgradeReq accesses(hits+misses) 3273system.l2c.ReadExReq_accesses::cpu0.data 15040 # number of ReadExReq accesses(hits+misses) 3274system.l2c.ReadExReq_accesses::cpu1.data 9814 # number of ReadExReq accesses(hits+misses) 3275system.l2c.ReadExReq_accesses::total 24854 # number of ReadExReq accesses(hits+misses) 3276system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 291 # number of ReadSharedReq accesses(hits+misses) 3277system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 110 # number of ReadSharedReq accesses(hits+misses) 3278system.l2c.ReadSharedReq_accesses::cpu0.inst 70520 # number of ReadSharedReq accesses(hits+misses) 3279system.l2c.ReadSharedReq_accesses::cpu0.data 66635 # number of ReadSharedReq accesses(hits+misses) 3280system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177769 # number of ReadSharedReq accesses(hits+misses) 3281system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 55 # number of ReadSharedReq accesses(hits+misses) 3282system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 19 # number of ReadSharedReq accesses(hits+misses) 3283system.l2c.ReadSharedReq_accesses::cpu1.inst 23946 # number of ReadSharedReq accesses(hits+misses) 3284system.l2c.ReadSharedReq_accesses::cpu1.data 12538 # number of ReadSharedReq accesses(hits+misses) 3285system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11694 # number of ReadSharedReq accesses(hits+misses) 3286system.l2c.ReadSharedReq_accesses::total 363577 # number of ReadSharedReq accesses(hits+misses) 3287system.l2c.demand_accesses::cpu0.dtb.walker 291 # number of demand (read+write) accesses 3288system.l2c.demand_accesses::cpu0.itb.walker 110 # number of demand (read+write) accesses 3289system.l2c.demand_accesses::cpu0.inst 70520 # number of demand (read+write) accesses 3290system.l2c.demand_accesses::cpu0.data 81675 # number of demand (read+write) accesses 3291system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177769 # number of demand (read+write) accesses 3292system.l2c.demand_accesses::cpu1.dtb.walker 55 # number of demand (read+write) accesses 3293system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses 3294system.l2c.demand_accesses::cpu1.inst 23946 # number of demand (read+write) accesses 3295system.l2c.demand_accesses::cpu1.data 22352 # number of demand (read+write) accesses 3296system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11694 # number of demand (read+write) accesses 3297system.l2c.demand_accesses::total 388431 # number of demand (read+write) accesses 3298system.l2c.overall_accesses::cpu0.dtb.walker 291 # number of overall (read+write) accesses 3299system.l2c.overall_accesses::cpu0.itb.walker 110 # number of overall (read+write) accesses 3300system.l2c.overall_accesses::cpu0.inst 70520 # number of overall (read+write) accesses 3301system.l2c.overall_accesses::cpu0.data 81675 # number of overall (read+write) accesses 3302system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177769 # number of overall (read+write) accesses 3303system.l2c.overall_accesses::cpu1.dtb.walker 55 # number of overall (read+write) accesses 3304system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses 3305system.l2c.overall_accesses::cpu1.inst 23946 # number of overall (read+write) accesses 3306system.l2c.overall_accesses::cpu1.data 22352 # number of overall (read+write) accesses 3307system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11694 # number of overall (read+write) accesses 3308system.l2c.overall_accesses::total 388431 # number of overall (read+write) accesses 3309system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012471 # miss rate for UpgradeReq accesses 3310system.l2c.UpgradeReq_miss_rate::cpu1.data 0.054145 # miss rate for UpgradeReq accesses 3311system.l2c.UpgradeReq_miss_rate::total 0.016929 # miss rate for UpgradeReq accesses 3312system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018855 # miss rate for SCUpgradeReq accesses 3313system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.036957 # miss rate for SCUpgradeReq accesses 3314system.l2c.SCUpgradeReq_miss_rate::total 0.027053 # miss rate for SCUpgradeReq accesses 3315system.l2c.ReadExReq_miss_rate::cpu0.data 0.735638 # miss rate for ReadExReq accesses 3316system.l2c.ReadExReq_miss_rate::cpu1.data 0.838598 # miss rate for ReadExReq accesses 3317system.l2c.ReadExReq_miss_rate::total 0.776294 # miss rate for ReadExReq accesses 3318system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for ReadSharedReq accesses 3319system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036364 # miss rate for ReadSharedReq accesses 3320system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.283196 # miss rate for ReadSharedReq accesses 3321system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.141262 # miss rate for ReadSharedReq accesses 3322system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for ReadSharedReq accesses 3323system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for ReadSharedReq accesses 3324system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.052632 # miss rate for ReadSharedReq accesses 3325system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.114675 # miss rate for ReadSharedReq accesses 3326system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.075371 # miss rate for ReadSharedReq accesses 3327system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for ReadSharedReq accesses 3328system.l2c.ReadSharedReq_miss_rate::total 0.470847 # miss rate for ReadSharedReq accesses 3329system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for demand accesses 3330system.l2c.demand_miss_rate::cpu0.itb.walker 0.036364 # miss rate for demand accesses 3331system.l2c.demand_miss_rate::cpu0.inst 0.283196 # miss rate for demand accesses 3332system.l2c.demand_miss_rate::cpu0.data 0.250713 # miss rate for demand accesses 3333system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for demand accesses 3334system.l2c.demand_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for demand accesses 3335system.l2c.demand_miss_rate::cpu1.itb.walker 0.052632 # miss rate for demand accesses 3336system.l2c.demand_miss_rate::cpu1.inst 0.114675 # miss rate for demand accesses 3337system.l2c.demand_miss_rate::cpu1.data 0.410478 # miss rate for demand accesses 3338system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for demand accesses 3339system.l2c.demand_miss_rate::total 0.490391 # miss rate for demand accesses 3340system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for overall accesses 3341system.l2c.overall_miss_rate::cpu0.itb.walker 0.036364 # miss rate for overall accesses 3342system.l2c.overall_miss_rate::cpu0.inst 0.283196 # miss rate for overall accesses 3343system.l2c.overall_miss_rate::cpu0.data 0.250713 # miss rate for overall accesses 3344system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for overall accesses 3345system.l2c.overall_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for overall accesses 3346system.l2c.overall_miss_rate::cpu1.itb.walker 0.052632 # miss rate for overall accesses 3347system.l2c.overall_miss_rate::cpu1.inst 0.114675 # miss rate for overall accesses 3348system.l2c.overall_miss_rate::cpu1.data 0.410478 # miss rate for overall accesses 3349system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for overall accesses 3350system.l2c.overall_miss_rate::total 0.490391 # miss rate for overall accesses 3351system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19224.761905 # average UpgradeReq miss latency 3352system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1901.098901 # average UpgradeReq miss latency 3353system.l2c.UpgradeReq_avg_miss_latency::total 13298.245614 # average UpgradeReq miss latency 3354system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13386.792453 # average SCUpgradeReq miss latency 3355system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4244.186047 # average SCUpgradeReq miss latency 3356system.l2c.SCUpgradeReq_avg_miss_latency::total 7730.215827 # average SCUpgradeReq miss latency 3357system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148870.074114 # average ReadExReq miss latency 3358system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94763.304982 # average ReadExReq miss latency 3359system.l2c.ReadExReq_avg_miss_latency::total 125790.427076 # average ReadExReq miss latency 3360system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average ReadSharedReq miss latency 3361system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88250 # average ReadSharedReq miss latency 3362system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 105010.415102 # average ReadSharedReq miss latency 3363system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 117581.111229 # average ReadSharedReq miss latency 3364system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average ReadSharedReq miss latency 3365system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89750 # average ReadSharedReq miss latency 3366system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 90000 # average ReadSharedReq miss latency 3367system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 107477.603787 # average ReadSharedReq miss latency 3368system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 122673.015873 # average ReadSharedReq miss latency 3369system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average ReadSharedReq miss latency 3370system.l2c.ReadSharedReq_avg_miss_latency::total 122246.992038 # average ReadSharedReq miss latency 3371system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency 3372system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency 3373system.l2c.demand_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency 3374system.l2c.demand_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency 3375system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency 3376system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency 3377system.l2c.demand_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency 3378system.l2c.demand_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency 3379system.l2c.demand_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency 3380system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency 3381system.l2c.demand_avg_miss_latency::total 122605.906144 # average overall miss latency 3382system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency 3383system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency 3384system.l2c.overall_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency 3385system.l2c.overall_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency 3386system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency 3387system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency 3388system.l2c.overall_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency 3389system.l2c.overall_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency 3390system.l2c.overall_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency 3391system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency 3392system.l2c.overall_avg_miss_latency::total 122605.906144 # average overall miss latency 3393system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 3246system.l2c.overall_misses::cpu1.inst 3001 # number of overall misses 3247system.l2c.overall_misses::cpu1.data 9290 # number of overall misses 3248system.l2c.overall_misses::cpu1.l2cache.prefetcher 6755 # number of overall misses 3249system.l2c.overall_misses::total 190599 # number of overall misses 3250system.l2c.UpgradeReq_miss_latency::cpu0.data 8930500 # number of UpgradeReq miss cycles 3251system.l2c.UpgradeReq_miss_latency::cpu1.data 709000 # number of UpgradeReq miss cycles 3252system.l2c.UpgradeReq_miss_latency::total 9639500 # number of UpgradeReq miss cycles 3253system.l2c.SCUpgradeReq_miss_latency::cpu0.data 540000 # number of SCUpgradeReq miss cycles 3254system.l2c.SCUpgradeReq_miss_latency::cpu1.data 293500 # number of SCUpgradeReq miss cycles 3255system.l2c.SCUpgradeReq_miss_latency::total 833500 # number of SCUpgradeReq miss cycles 3256system.l2c.ReadExReq_miss_latency::cpu0.data 1649495000 # number of ReadExReq miss cycles 3257system.l2c.ReadExReq_miss_latency::cpu1.data 781758500 # number of ReadExReq miss cycles 3258system.l2c.ReadExReq_miss_latency::total 2431253500 # number of ReadExReq miss cycles 3259system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 5602000 # number of ReadSharedReq miss cycles 3260system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 249000 # number of ReadSharedReq miss cycles 3261system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2048083000 # number of ReadSharedReq miss cycles 3262system.l2c.ReadSharedReq_miss_latency::cpu0.data 1082250500 # number of ReadSharedReq miss cycles 3263system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of ReadSharedReq miss cycles 3264system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 622500 # number of ReadSharedReq miss cycles 3265system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 89500 # number of ReadSharedReq miss cycles 3266system.l2c.ReadSharedReq_miss_latency::cpu1.inst 340295000 # number of ReadSharedReq miss cycles 3267system.l2c.ReadSharedReq_miss_latency::cpu1.data 119337000 # number of ReadSharedReq miss cycles 3268system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of ReadSharedReq miss cycles 3269system.l2c.ReadSharedReq_miss_latency::total 21015387223 # number of ReadSharedReq miss cycles 3270system.l2c.demand_miss_latency::cpu0.dtb.walker 5602000 # number of demand (read+write) miss cycles 3271system.l2c.demand_miss_latency::cpu0.itb.walker 249000 # number of demand (read+write) miss cycles 3272system.l2c.demand_miss_latency::cpu0.inst 2048083000 # number of demand (read+write) miss cycles 3273system.l2c.demand_miss_latency::cpu0.data 2731745500 # number of demand (read+write) miss cycles 3274system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of demand (read+write) miss cycles 3275system.l2c.demand_miss_latency::cpu1.dtb.walker 622500 # number of demand (read+write) miss cycles 3276system.l2c.demand_miss_latency::cpu1.itb.walker 89500 # number of demand (read+write) miss cycles 3277system.l2c.demand_miss_latency::cpu1.inst 340295000 # number of demand (read+write) miss cycles 3278system.l2c.demand_miss_latency::cpu1.data 901095500 # number of demand (read+write) miss cycles 3279system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of demand (read+write) miss cycles 3280system.l2c.demand_miss_latency::total 23446640723 # number of demand (read+write) miss cycles 3281system.l2c.overall_miss_latency::cpu0.dtb.walker 5602000 # number of overall miss cycles 3282system.l2c.overall_miss_latency::cpu0.itb.walker 249000 # number of overall miss cycles 3283system.l2c.overall_miss_latency::cpu0.inst 2048083000 # number of overall miss cycles 3284system.l2c.overall_miss_latency::cpu0.data 2731745500 # number of overall miss cycles 3285system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of overall miss cycles 3286system.l2c.overall_miss_latency::cpu1.dtb.walker 622500 # number of overall miss cycles 3287system.l2c.overall_miss_latency::cpu1.itb.walker 89500 # number of overall miss cycles 3288system.l2c.overall_miss_latency::cpu1.inst 340295000 # number of overall miss cycles 3289system.l2c.overall_miss_latency::cpu1.data 901095500 # number of overall miss cycles 3290system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of overall miss cycles 3291system.l2c.overall_miss_latency::total 23446640723 # number of overall miss cycles 3292system.l2c.WritebackDirty_accesses::writebacks 261149 # number of WritebackDirty accesses(hits+misses) 3293system.l2c.WritebackDirty_accesses::total 261149 # number of WritebackDirty accesses(hits+misses) 3294system.l2c.UpgradeReq_accesses::cpu0.data 41966 # number of UpgradeReq accesses(hits+misses) 3295system.l2c.UpgradeReq_accesses::cpu1.data 5124 # number of UpgradeReq accesses(hits+misses) 3296system.l2c.UpgradeReq_accesses::total 47090 # number of UpgradeReq accesses(hits+misses) 3297system.l2c.SCUpgradeReq_accesses::cpu0.data 2780 # number of SCUpgradeReq accesses(hits+misses) 3298system.l2c.SCUpgradeReq_accesses::cpu1.data 2353 # number of SCUpgradeReq accesses(hits+misses) 3299system.l2c.SCUpgradeReq_accesses::total 5133 # number of SCUpgradeReq accesses(hits+misses) 3300system.l2c.ReadExReq_accesses::cpu0.data 15242 # number of ReadExReq accesses(hits+misses) 3301system.l2c.ReadExReq_accesses::cpu1.data 9829 # number of ReadExReq accesses(hits+misses) 3302system.l2c.ReadExReq_accesses::total 25071 # number of ReadExReq accesses(hits+misses) 3303system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 311 # number of ReadSharedReq accesses(hits+misses) 3304system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses) 3305system.l2c.ReadSharedReq_accesses::cpu0.inst 69824 # number of ReadSharedReq accesses(hits+misses) 3306system.l2c.ReadSharedReq_accesses::cpu0.data 66660 # number of ReadSharedReq accesses(hits+misses) 3307system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177592 # number of ReadSharedReq accesses(hits+misses) 3308system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 51 # number of ReadSharedReq accesses(hits+misses) 3309system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses) 3310system.l2c.ReadSharedReq_accesses::cpu1.inst 24481 # number of ReadSharedReq accesses(hits+misses) 3311system.l2c.ReadSharedReq_accesses::cpu1.data 12699 # number of ReadSharedReq accesses(hits+misses) 3312system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11685 # number of ReadSharedReq accesses(hits+misses) 3313system.l2c.ReadSharedReq_accesses::total 363404 # number of ReadSharedReq accesses(hits+misses) 3314system.l2c.demand_accesses::cpu0.dtb.walker 311 # number of demand (read+write) accesses 3315system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses 3316system.l2c.demand_accesses::cpu0.inst 69824 # number of demand (read+write) accesses 3317system.l2c.demand_accesses::cpu0.data 81902 # number of demand (read+write) accesses 3318system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177592 # number of demand (read+write) accesses 3319system.l2c.demand_accesses::cpu1.dtb.walker 51 # number of demand (read+write) accesses 3320system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses 3321system.l2c.demand_accesses::cpu1.inst 24481 # number of demand (read+write) accesses 3322system.l2c.demand_accesses::cpu1.data 22528 # number of demand (read+write) accesses 3323system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11685 # number of demand (read+write) accesses 3324system.l2c.demand_accesses::total 388475 # number of demand (read+write) accesses 3325system.l2c.overall_accesses::cpu0.dtb.walker 311 # number of overall (read+write) accesses 3326system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses 3327system.l2c.overall_accesses::cpu0.inst 69824 # number of overall (read+write) accesses 3328system.l2c.overall_accesses::cpu0.data 81902 # number of overall (read+write) accesses 3329system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177592 # number of overall (read+write) accesses 3330system.l2c.overall_accesses::cpu1.dtb.walker 51 # number of overall (read+write) accesses 3331system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses 3332system.l2c.overall_accesses::cpu1.inst 24481 # number of overall (read+write) accesses 3333system.l2c.overall_accesses::cpu1.data 22528 # number of overall (read+write) accesses 3334system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11685 # number of overall (read+write) accesses 3335system.l2c.overall_accesses::total 388475 # number of overall (read+write) accesses 3336system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010794 # miss rate for UpgradeReq accesses 3337system.l2c.UpgradeReq_miss_rate::cpu1.data 0.055035 # miss rate for UpgradeReq accesses 3338system.l2c.UpgradeReq_miss_rate::total 0.015608 # miss rate for UpgradeReq accesses 3339system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.035612 # miss rate for SCUpgradeReq accesses 3340system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034424 # miss rate for SCUpgradeReq accesses 3341system.l2c.SCUpgradeReq_miss_rate::total 0.035067 # miss rate for SCUpgradeReq accesses 3342system.l2c.ReadExReq_miss_rate::cpu0.data 0.737370 # miss rate for ReadExReq accesses 3343system.l2c.ReadExReq_miss_rate::cpu1.data 0.840981 # miss rate for ReadExReq accesses 3344system.l2c.ReadExReq_miss_rate::total 0.777991 # miss rate for ReadExReq accesses 3345system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for ReadSharedReq accesses 3346system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036145 # miss rate for ReadSharedReq accesses 3347system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.282267 # miss rate for ReadSharedReq accesses 3348system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.140279 # miss rate for ReadSharedReq accesses 3349system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for ReadSharedReq accesses 3350system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for ReadSharedReq accesses 3351system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.055556 # miss rate for ReadSharedReq accesses 3352system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.122585 # miss rate for ReadSharedReq accesses 3353system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.080636 # miss rate for ReadSharedReq accesses 3354system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for ReadSharedReq accesses 3355system.l2c.ReadSharedReq_miss_rate::total 0.470809 # miss rate for ReadSharedReq accesses 3356system.l2c.demand_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for demand accesses 3357system.l2c.demand_miss_rate::cpu0.itb.walker 0.036145 # miss rate for demand accesses 3358system.l2c.demand_miss_rate::cpu0.inst 0.282267 # miss rate for demand accesses 3359system.l2c.demand_miss_rate::cpu0.data 0.251398 # miss rate for demand accesses 3360system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for demand accesses 3361system.l2c.demand_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for demand accesses 3362system.l2c.demand_miss_rate::cpu1.itb.walker 0.055556 # miss rate for demand accesses 3363system.l2c.demand_miss_rate::cpu1.inst 0.122585 # miss rate for demand accesses 3364system.l2c.demand_miss_rate::cpu1.data 0.412376 # miss rate for demand accesses 3365system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for demand accesses 3366system.l2c.demand_miss_rate::total 0.490634 # miss rate for demand accesses 3367system.l2c.overall_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for overall accesses 3368system.l2c.overall_miss_rate::cpu0.itb.walker 0.036145 # miss rate for overall accesses 3369system.l2c.overall_miss_rate::cpu0.inst 0.282267 # miss rate for overall accesses 3370system.l2c.overall_miss_rate::cpu0.data 0.251398 # miss rate for overall accesses 3371system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for overall accesses 3372system.l2c.overall_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for overall accesses 3373system.l2c.overall_miss_rate::cpu1.itb.walker 0.055556 # miss rate for overall accesses 3374system.l2c.overall_miss_rate::cpu1.inst 0.122585 # miss rate for overall accesses 3375system.l2c.overall_miss_rate::cpu1.data 0.412376 # miss rate for overall accesses 3376system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for overall accesses 3377system.l2c.overall_miss_rate::total 0.490634 # miss rate for overall accesses 3378system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19714.128035 # average UpgradeReq miss latency 3379system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2514.184397 # average UpgradeReq miss latency 3380system.l2c.UpgradeReq_avg_miss_latency::total 13114.965986 # average UpgradeReq miss latency 3381system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5454.545455 # average SCUpgradeReq miss latency 3382system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3623.456790 # average SCUpgradeReq miss latency 3383system.l2c.SCUpgradeReq_avg_miss_latency::total 4630.555556 # average SCUpgradeReq miss latency 3384system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146765.281609 # average ReadExReq miss latency 3385system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94575.187515 # average ReadExReq miss latency 3386system.l2c.ReadExReq_avg_miss_latency::total 124647.705716 # average ReadExReq miss latency 3387system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average ReadSharedReq miss latency 3388system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency 3389system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 103916.129687 # average ReadSharedReq miss latency 3390system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115736.338360 # average ReadSharedReq miss latency 3391system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average ReadSharedReq miss latency 3392system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average ReadSharedReq miss latency 3393system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89500 # average ReadSharedReq miss latency 3394system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113393.868710 # average ReadSharedReq miss latency 3395system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116540.039062 # average ReadSharedReq miss latency 3396system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average ReadSharedReq miss latency 3397system.l2c.ReadSharedReq_avg_miss_latency::total 122829.481005 # average ReadSharedReq miss latency 3398system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average overall miss latency 3399system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 3400system.l2c.demand_avg_miss_latency::cpu0.inst 103916.129687 # average overall miss latency 3401system.l2c.demand_avg_miss_latency::cpu0.data 132673.409422 # average overall miss latency 3402system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average overall miss latency 3403system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average overall miss latency 3404system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency 3405system.l2c.demand_avg_miss_latency::cpu1.inst 113393.868710 # average overall miss latency 3406system.l2c.demand_avg_miss_latency::cpu1.data 96996.286329 # average overall miss latency 3407system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average overall miss latency 3408system.l2c.demand_avg_miss_latency::total 123015.549520 # average overall miss latency 3409system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average overall miss latency 3410system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 3411system.l2c.overall_avg_miss_latency::cpu0.inst 103916.129687 # average overall miss latency 3412system.l2c.overall_avg_miss_latency::cpu0.data 132673.409422 # average overall miss latency 3413system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average overall miss latency 3414system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average overall miss latency 3415system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency 3416system.l2c.overall_avg_miss_latency::cpu1.inst 113393.868710 # average overall miss latency 3417system.l2c.overall_avg_miss_latency::cpu1.data 96996.286329 # average overall miss latency 3418system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average overall miss latency 3419system.l2c.overall_avg_miss_latency::total 123015.549520 # average overall miss latency 3420system.l2c.blocked_cycles::no_mshrs 153 # number of cycles access was blocked |
| 3394system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3421system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3395system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked | 3422system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked |
| 3396system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 3423system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 3397system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 3424system.l2c.avg_blocked_cycles::no_mshrs 76.500000 # average number of cycles each access was blocked |
| 3398system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 3425system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 3399system.l2c.writebacks::writebacks 100899 # number of writebacks 3400system.l2c.writebacks::total 100899 # number of writebacks 3401system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits 3402system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits | 3426system.l2c.writebacks::writebacks 101145 # number of writebacks 3427system.l2c.writebacks::total 101145 # number of writebacks 3428system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits 3429system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 3 # number of ReadSharedReq MSHR hits |
| 3403system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits | 3430system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits |
| 3404system.l2c.ReadSharedReq_mshr_hits::total 11 # number of ReadSharedReq MSHR hits 3405system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 3406system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits | 3431system.l2c.ReadSharedReq_mshr_hits::total 12 # number of ReadSharedReq MSHR hits 3432system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 3433system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits |
| 3407system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits | 3434system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits |
| 3408system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 3409system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 3410system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits | 3435system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits 3436system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 3437system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits |
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| 3412system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 3413system.l2c.CleanEvict_mshr_misses::writebacks 4091 # number of CleanEvict MSHR misses 3414system.l2c.CleanEvict_mshr_misses::total 4091 # number of CleanEvict MSHR misses 3415system.l2c.UpgradeReq_mshr_misses::cpu0.data 525 # number of UpgradeReq MSHR misses 3416system.l2c.UpgradeReq_mshr_misses::cpu1.data 273 # number of UpgradeReq MSHR misses 3417system.l2c.UpgradeReq_mshr_misses::total 798 # number of UpgradeReq MSHR misses 3418system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 53 # number of SCUpgradeReq MSHR misses 3419system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 86 # number of SCUpgradeReq MSHR misses 3420system.l2c.SCUpgradeReq_mshr_misses::total 139 # number of SCUpgradeReq MSHR misses 3421system.l2c.ReadExReq_mshr_misses::cpu0.data 11064 # number of ReadExReq MSHR misses 3422system.l2c.ReadExReq_mshr_misses::cpu1.data 8230 # number of ReadExReq MSHR misses 3423system.l2c.ReadExReq_mshr_misses::total 19294 # number of ReadExReq MSHR misses 3424system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 26 # number of ReadSharedReq MSHR misses 3425system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 4 # number of ReadSharedReq MSHR misses 3426system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19969 # number of ReadSharedReq MSHR misses 3427system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9413 # number of ReadSharedReq MSHR misses 3428system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq MSHR misses 3429system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses | 3439system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits 3440system.l2c.CleanEvict_mshr_misses::writebacks 4176 # number of CleanEvict MSHR misses 3441system.l2c.CleanEvict_mshr_misses::total 4176 # number of CleanEvict MSHR misses 3442system.l2c.UpgradeReq_mshr_misses::cpu0.data 453 # number of UpgradeReq MSHR misses 3443system.l2c.UpgradeReq_mshr_misses::cpu1.data 282 # number of UpgradeReq MSHR misses 3444system.l2c.UpgradeReq_mshr_misses::total 735 # number of UpgradeReq MSHR misses 3445system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 99 # number of SCUpgradeReq MSHR misses 3446system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 81 # number of SCUpgradeReq MSHR misses 3447system.l2c.SCUpgradeReq_mshr_misses::total 180 # number of SCUpgradeReq MSHR misses 3448system.l2c.ReadExReq_mshr_misses::cpu0.data 11239 # number of ReadExReq MSHR misses 3449system.l2c.ReadExReq_mshr_misses::cpu1.data 8266 # number of ReadExReq MSHR misses 3450system.l2c.ReadExReq_mshr_misses::total 19505 # number of ReadExReq MSHR misses 3451system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadSharedReq MSHR misses 3452system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses 3453system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19701 # number of ReadSharedReq MSHR misses 3454system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9351 # number of ReadSharedReq MSHR misses 3455system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131214 # number of ReadSharedReq MSHR misses 3456system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses |
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| 3453system.l2c.overall_mshr_misses::cpu1.inst 2738 # number of overall MSHR misses 3454system.l2c.overall_mshr_misses::cpu1.data 9174 # number of overall MSHR misses 3455system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of overall MSHR misses 3456system.l2c.overall_mshr_misses::total 190472 # number of overall MSHR misses | 3480system.l2c.overall_mshr_misses::cpu1.inst 2998 # number of overall MSHR misses 3481system.l2c.overall_mshr_misses::cpu1.data 9289 # number of overall MSHR misses 3482system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6755 # number of overall MSHR misses 3483system.l2c.overall_mshr_misses::total 190587 # number of overall MSHR misses |
| 3457system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable | 3484system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable |
| 3458system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable | 3485system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable |
| 3459system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable | 3486system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable |
| 3460system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2877 # number of ReadReq MSHR uncacheable 3461system.l2c.ReadReq_mshr_uncacheable::total 37994 # number of ReadReq MSHR uncacheable 3462system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable 3463system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable 3464system.l2c.WriteReq_mshr_uncacheable::total 30912 # number of WriteReq MSHR uncacheable | 3487system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14311 # number of ReadReq MSHR uncacheable 3488system.l2c.ReadReq_mshr_uncacheable::total 37997 # number of ReadReq MSHR uncacheable 3489system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable 3490system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable 3491system.l2c.WriteReq_mshr_uncacheable::total 30917 # number of WriteReq MSHR uncacheable |
| 3465system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses | 3492system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses |
| 3466system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses | 3493system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses |
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| 3468system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5107 # number of overall MSHR uncacheable misses 3469system.l2c.overall_mshr_uncacheable_misses::total 68906 # number of overall MSHR uncacheable misses 3470system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11977000 # number of UpgradeReq MSHR miss cycles 3471system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6297000 # number of UpgradeReq MSHR miss cycles 3472system.l2c.UpgradeReq_mshr_miss_latency::total 18274000 # number of UpgradeReq MSHR miss cycles 3473system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1386000 # number of SCUpgradeReq MSHR miss cycles 3474system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1952500 # number of SCUpgradeReq MSHR miss cycles 3475system.l2c.SCUpgradeReq_mshr_miss_latency::total 3338500 # number of SCUpgradeReq MSHR miss cycles 3476system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1536458500 # number of ReadExReq MSHR miss cycles 3477system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 697602000 # 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number of demand (read+write) MSHR miss cycles 3496system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 3497system.l2c.demand_mshr_miss_latency::cpu1.inst 267162500 # number of demand (read+write) MSHR miss cycles 3498system.l2c.demand_mshr_miss_latency::cpu1.data 803724500 # number of demand (read+write) MSHR miss cycles 3499system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of demand (read+write) MSHR miss cycles 3500system.l2c.demand_mshr_miss_latency::total 21448589330 # number of demand (read+write) MSHR miss cycles 3501system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of overall MSHR miss cycles 3502system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 313000 # number of overall MSHR miss cycles 3503system.l2c.overall_mshr_miss_latency::cpu0.inst 1897400002 # number of overall MSHR miss cycles 3504system.l2c.overall_mshr_miss_latency::cpu0.data 2549119001 # number of overall MSHR miss cycles 3505system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # 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number of demand (read+write) MSHR miss cycles 3518system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 219000 # number of demand (read+write) MSHR miss cycles 3519system.l2c.demand_mshr_miss_latency::cpu0.inst 1850579001 # number of demand (read+write) MSHR miss cycles 3520system.l2c.demand_mshr_miss_latency::cpu0.data 2525845001 # number of demand (read+write) MSHR miss cycles 3521system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of demand (read+write) MSHR miss cycles 3522system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 552500 # number of demand (read+write) MSHR miss cycles 3523system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 79500 # number of demand (read+write) MSHR miss cycles 3524system.l2c.demand_mshr_miss_latency::cpu1.inst 310216001 # number of demand (read+write) MSHR miss cycles 3525system.l2c.demand_mshr_miss_latency::cpu1.data 808087000 # number of demand (read+write) MSHR miss cycles 3526system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of demand (read+write) MSHR miss cycles 3527system.l2c.demand_mshr_miss_latency::total 21540052738 # number of demand (read+write) MSHR miss cycles 3528system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5312000 # number of overall MSHR miss cycles 3529system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 219000 # number of overall MSHR miss cycles 3530system.l2c.overall_mshr_miss_latency::cpu0.inst 1850579001 # number of overall MSHR miss cycles 3531system.l2c.overall_mshr_miss_latency::cpu0.data 2525845001 # number of overall MSHR miss cycles 3532system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of overall MSHR miss cycles 3533system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 552500 # number of overall MSHR miss cycles 3534system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 79500 # number of overall MSHR miss cycles 3535system.l2c.overall_mshr_miss_latency::cpu1.inst 310216001 # number of overall MSHR miss cycles 3536system.l2c.overall_mshr_miss_latency::cpu1.data 808087000 # number of overall MSHR miss cycles 3537system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of overall MSHR miss cycles 3538system.l2c.overall_mshr_miss_latency::total 21540052738 # number of overall MSHR miss cycles |
| 3512system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles | 3539system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles |
| 3513system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5849372000 # number of ReadReq MSHR uncacheable cycles 3514system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7087000 # number of ReadReq MSHR uncacheable cycles 3515system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 311625000 # number of ReadReq MSHR uncacheable cycles 3516system.l2c.ReadReq_mshr_uncacheable_latency::total 6379025500 # number of ReadReq MSHR uncacheable cycles | 3540system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4060149000 # number of ReadReq MSHR uncacheable cycles 3541system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6923000 # number of ReadReq MSHR uncacheable cycles 3542system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2100456000 # number of ReadReq MSHR uncacheable cycles 3543system.l2c.ReadReq_mshr_uncacheable_latency::total 6378469500 # number of ReadReq MSHR uncacheable cycles |
| 3517system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles | 3544system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles |
| 3518system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5849372000 # number of overall MSHR uncacheable cycles 3519system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7087000 # number of overall MSHR uncacheable cycles 3520system.l2c.overall_mshr_uncacheable_latency::cpu1.data 311625000 # number of overall MSHR uncacheable cycles 3521system.l2c.overall_mshr_uncacheable_latency::total 6379025500 # number of overall MSHR uncacheable cycles | 3545system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4060149000 # number of overall MSHR uncacheable cycles 3546system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6923000 # number of overall MSHR uncacheable cycles 3547system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2100456000 # number of overall MSHR uncacheable cycles 3548system.l2c.overall_mshr_uncacheable_latency::total 6378469500 # number of overall MSHR uncacheable cycles |
| 3522system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3523system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 3549system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3550system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 3524system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012471 # mshr miss rate for UpgradeReq accesses 3525system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.054145 # mshr miss rate for UpgradeReq accesses 3526system.l2c.UpgradeReq_mshr_miss_rate::total 0.016929 # mshr miss rate for UpgradeReq accesses 3527system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018855 # mshr miss rate for SCUpgradeReq accesses 3528system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.036957 # mshr miss rate for SCUpgradeReq accesses 3529system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.027053 # mshr miss rate for SCUpgradeReq accesses 3530system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.735638 # mshr miss rate for ReadExReq accesses 3531system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.838598 # mshr miss rate for ReadExReq accesses 3532system.l2c.ReadExReq_mshr_miss_rate::total 0.776294 # mshr miss rate for ReadExReq accesses 3533system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for ReadSharedReq accesses 3534system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for ReadSharedReq accesses 3535system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for ReadSharedReq accesses 3536system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.141262 # mshr miss rate for ReadSharedReq accesses 3537system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for ReadSharedReq accesses 3538system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for ReadSharedReq accesses 3539system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for ReadSharedReq accesses 3540system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for ReadSharedReq accesses 3541system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.075291 # mshr miss rate for ReadSharedReq accesses 3542system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for ReadSharedReq accesses 3543system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470816 # mshr miss rate for ReadSharedReq accesses 3544system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for demand accesses 3545system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for demand accesses 3546system.l2c.demand_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for demand accesses 3547system.l2c.demand_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for demand accesses 3548system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for demand accesses 3549system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for demand accesses 3550system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for demand accesses 3551system.l2c.demand_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for demand accesses 3552system.l2c.demand_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for demand accesses 3553system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for demand accesses 3554system.l2c.demand_mshr_miss_rate::total 0.490363 # mshr miss rate for demand accesses 3555system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for overall accesses 3556system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for overall accesses 3557system.l2c.overall_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for overall accesses 3558system.l2c.overall_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for overall accesses 3559system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for overall accesses 3560system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for overall accesses 3561system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for overall accesses 3562system.l2c.overall_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for overall accesses 3563system.l2c.overall_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for overall accesses 3564system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for overall accesses 3565system.l2c.overall_mshr_miss_rate::total 0.490363 # mshr miss rate for overall accesses 3566system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22813.333333 # average UpgradeReq mshr miss latency 3567system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23065.934066 # average UpgradeReq mshr miss latency 3568system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22899.749373 # average UpgradeReq mshr miss latency 3569system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26150.943396 # average SCUpgradeReq mshr miss latency 3570system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22703.488372 # average SCUpgradeReq mshr miss latency 3571system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24017.985612 # average SCUpgradeReq mshr miss latency 3572system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138870.074114 # average ReadExReq mshr miss latency 3573system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84763.304982 # average ReadExReq mshr miss latency 3574system.l2c.ReadExReq_avg_mshr_miss_latency::total 115790.427076 # average ReadExReq mshr miss latency 3575system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average ReadSharedReq mshr miss latency 3576system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average ReadSharedReq mshr miss latency 3577system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average ReadSharedReq mshr miss latency 3578system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 107581.058217 # average ReadSharedReq mshr miss latency 3579system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average ReadSharedReq mshr miss latency 3580system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average ReadSharedReq mshr miss latency 3581system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average ReadSharedReq mshr miss latency 3582system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average ReadSharedReq mshr miss latency 3583system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 112417.902542 # average ReadSharedReq mshr miss latency 3584system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average ReadSharedReq mshr miss latency 3585system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112248.821870 # average ReadSharedReq mshr miss latency 3586system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency 3587system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency 3588system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency 3589system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency 3590system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency 3591system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency 3592system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency 3593system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency 3594system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency 3595system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency 3596system.l2c.demand_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency 3597system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency 3598system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency 3599system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency 3600system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency 3601system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency 3602system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency 3603system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency 3604system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency 3605system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency 3606system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency 3607system.l2c.overall_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency | 3551system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010794 # mshr miss rate for UpgradeReq accesses 3552system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055035 # mshr miss rate for UpgradeReq accesses 3553system.l2c.UpgradeReq_mshr_miss_rate::total 0.015608 # mshr miss rate for UpgradeReq accesses 3554system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.035612 # mshr miss rate for SCUpgradeReq accesses 3555system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034424 # mshr miss rate for SCUpgradeReq accesses 3556system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035067 # mshr miss rate for SCUpgradeReq accesses 3557system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737370 # mshr miss rate for ReadExReq accesses 3558system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.840981 # mshr miss rate for ReadExReq accesses 3559system.l2c.ReadExReq_mshr_miss_rate::total 0.777991 # mshr miss rate for ReadExReq accesses 3560system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for ReadSharedReq accesses 3561system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for ReadSharedReq accesses 3562system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for ReadSharedReq accesses 3563system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.140279 # mshr miss rate for ReadSharedReq accesses 3564system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for ReadSharedReq accesses 3565system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for ReadSharedReq accesses 3566system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for ReadSharedReq accesses 3567system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for ReadSharedReq accesses 3568system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.080558 # mshr miss rate for ReadSharedReq accesses 3569system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for ReadSharedReq accesses 3570system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470776 # mshr miss rate for ReadSharedReq accesses 3571system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for demand accesses 3572system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for demand accesses 3573system.l2c.demand_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for demand accesses 3574system.l2c.demand_mshr_miss_rate::cpu0.data 0.251398 # mshr miss rate for demand accesses 3575system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for demand accesses 3576system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for demand accesses 3577system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for demand accesses 3578system.l2c.demand_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for demand accesses 3579system.l2c.demand_mshr_miss_rate::cpu1.data 0.412331 # mshr miss rate for demand accesses 3580system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for demand accesses 3581system.l2c.demand_mshr_miss_rate::total 0.490603 # mshr miss rate for demand accesses 3582system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for overall accesses 3583system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for overall accesses 3584system.l2c.overall_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for overall accesses 3585system.l2c.overall_mshr_miss_rate::cpu0.data 0.251398 # mshr miss rate for overall accesses 3586system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for overall accesses 3587system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for overall accesses 3588system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for overall accesses 3589system.l2c.overall_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for overall accesses 3590system.l2c.overall_mshr_miss_rate::cpu1.data 0.412331 # mshr miss rate for overall accesses 3591system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for overall accesses 3592system.l2c.overall_mshr_miss_rate::total 0.490603 # mshr miss rate for overall accesses 3593system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22671.081678 # average UpgradeReq mshr miss latency 3594system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23398.936170 # average UpgradeReq mshr miss latency 3595system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22950.340136 # average UpgradeReq mshr miss latency 3596system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26323.232323 # average SCUpgradeReq mshr miss latency 3597system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22111.111111 # average SCUpgradeReq mshr miss latency 3598system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24427.777778 # average SCUpgradeReq mshr miss latency 3599system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136765.237210 # average ReadExReq mshr miss latency 3600system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84575.187515 # average ReadExReq mshr miss latency 3601system.l2c.ReadExReq_avg_mshr_miss_latency::total 114647.680133 # average ReadExReq mshr miss latency 3602system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average ReadSharedReq mshr miss latency 3603system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency 3604system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average ReadSharedReq mshr miss latency 3605system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105736.338360 # average ReadSharedReq mshr miss latency 3606system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average ReadSharedReq mshr miss latency 3607system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average ReadSharedReq mshr miss latency 3608system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency 3609system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average ReadSharedReq mshr miss latency 3610system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106538.123167 # average ReadSharedReq mshr miss latency 3611system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average ReadSharedReq mshr miss latency 3612system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112833.902672 # average ReadSharedReq mshr miss latency 3613system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average overall mshr miss latency 3614system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 3615system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average overall mshr miss latency 3616system.l2c.demand_avg_mshr_miss_latency::cpu0.data 122673.385187 # average overall mshr miss latency 3617system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average overall mshr miss latency 3618system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average overall mshr miss latency 3619system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency 3620system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average overall mshr miss latency 3621system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86993.971364 # average overall mshr miss latency 3622system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average overall mshr miss latency 3623system.l2c.demand_avg_mshr_miss_latency::total 113019.527764 # average overall mshr miss latency 3624system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average overall mshr miss latency 3625system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 3626system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average overall mshr miss latency 3627system.l2c.overall_avg_mshr_miss_latency::cpu0.data 122673.385187 # average overall mshr miss latency 3628system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average overall mshr miss latency 3629system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average overall mshr miss latency 3630system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency 3631system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average overall mshr miss latency 3632system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86993.971364 # average overall mshr miss latency 3633system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average overall mshr miss latency 3634system.l2c.overall_avg_mshr_miss_latency::total 113019.527764 # average overall mshr miss latency |
| 3608system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency | 3635system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency |
| 3609system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182747.188203 # average ReadReq mshr uncacheable latency 3610system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average ReadReq mshr uncacheable latency 3611system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108315.954119 # average ReadReq mshr uncacheable latency 3612system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167895.601937 # average ReadReq mshr uncacheable latency | 3636system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197314.914711 # average ReadReq mshr uncacheable latency 3637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average ReadReq mshr uncacheable latency 3638system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146772.133324 # average ReadReq mshr uncacheable latency 3639system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167867.713241 # average ReadReq mshr uncacheable latency |
| 3613system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency | 3640system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency |
| 3614system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96381.150107 # average overall mshr uncacheable latency 3615system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average overall mshr uncacheable latency 3616system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 61019.189348 # average overall mshr uncacheable latency 3617system.l2c.overall_avg_mshr_uncacheable_latency::total 92575.762633 # average overall mshr uncacheable latency 3618system.membus.snoop_filter.tot_requests 504615 # Total number of requests made to the snoop filter. 3619system.membus.snoop_filter.hit_single_requests 283930 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 3641system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101896.024695 # average overall mshr uncacheable latency 3642system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average overall mshr uncacheable latency 3643system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80914.364960 # average overall mshr uncacheable latency 3644system.l2c.overall_avg_mshr_uncacheable_latency::total 92556.947790 # average overall mshr uncacheable latency 3645system.membus.snoop_filter.tot_requests 505078 # Total number of requests made to the snoop filter. 3646system.membus.snoop_filter.hit_single_requests 284284 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 3620system.membus.snoop_filter.hit_multi_requests 621 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3621system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3622system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3623system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3647system.membus.snoop_filter.hit_multi_requests 621 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3648system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3649system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3650system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3624system.membus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3625system.membus.trans_dist::ReadReq 37994 # Transaction distribution 3626system.membus.trans_dist::ReadResp 209423 # Transaction distribution 3627system.membus.trans_dist::WriteReq 30912 # Transaction distribution 3628system.membus.trans_dist::WriteResp 30912 # Transaction distribution 3629system.membus.trans_dist::WritebackDirty 137105 # Transaction distribution 3630system.membus.trans_dist::CleanEvict 16916 # Transaction distribution 3631system.membus.trans_dist::UpgradeReq 65086 # Transaction distribution 3632system.membus.trans_dist::SCUpgradeReq 38844 # Transaction distribution | 3651system.membus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3652system.membus.trans_dist::ReadReq 37997 # Transaction distribution 3653system.membus.trans_dist::ReadResp 209330 # Transaction distribution 3654system.membus.trans_dist::WriteReq 30917 # Transaction distribution 3655system.membus.trans_dist::WriteResp 30917 # Transaction distribution 3656system.membus.trans_dist::WritebackDirty 137351 # Transaction distribution 3657system.membus.trans_dist::CleanEvict 16880 # Transaction distribution 3658system.membus.trans_dist::UpgradeReq 65170 # Transaction distribution 3659system.membus.trans_dist::SCUpgradeReq 38916 # Transaction distribution |
| 3633system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 3634system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution | 3660system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 3661system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution |
| 3635system.membus.trans_dist::ReadExReq 38910 # Transaction distribution 3636system.membus.trans_dist::ReadExResp 19275 # Transaction distribution 3637system.membus.trans_dist::ReadSharedReq 171430 # Transaction distribution | 3662system.membus.trans_dist::ReadExReq 39129 # Transaction distribution 3663system.membus.trans_dist::ReadExResp 19493 # Transaction distribution 3664system.membus.trans_dist::ReadSharedReq 171334 # Transaction distribution |
| 3638system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution | 3665system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution |
| 3639system.membus.trans_dist::InvalidateResp 4600 # Transaction distribution | 3666system.membus.trans_dist::InvalidateResp 4604 # Transaction distribution |
| 3640system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) 3641system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) | 3667system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) 3668system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) |
| 3642system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) 3643system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 637823 # Packet count per connected master and slave (bytes) 3644system.membus.pkt_count_system.l2c.mem_side::total 759513 # Packet count per connected master and slave (bytes) | 3669system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13758 # Packet count per connected master and slave (bytes) 3670system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638434 # Packet count per connected master and slave (bytes) 3671system.membus.pkt_count_system.l2c.mem_side::total 760140 # Packet count per connected master and slave (bytes) |
| 3645system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3646system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) | 3672system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3673system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) |
| 3647system.membus.pkt_count::total 832462 # Packet count per connected master and slave (bytes) | 3674system.membus.pkt_count::total 833089 # Packet count per connected master and slave (bytes) |
| 3648system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) 3649system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) | 3675system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) 3676system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) |
| 3650system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) 3651system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18694600 # Cumulative packet size per connected master and slave (bytes) 3652system.membus.pkt_size_system.l2c.mem_side::total 18885164 # Cumulative packet size per connected master and slave (bytes) | 3677system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27516 # Cumulative packet size per connected master and slave (bytes) 3678system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718152 # Cumulative packet size per connected master and slave (bytes) 3679system.membus.pkt_size_system.l2c.mem_side::total 18908748 # Cumulative packet size per connected master and slave (bytes) |
| 3653system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3654system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) | 3680system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3681system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) |
| 3655system.membus.pkt_size::total 21203308 # Cumulative packet size per connected master and slave (bytes) 3656system.membus.snoops 127782 # Total snoops (count) | 3682system.membus.pkt_size::total 21226892 # Cumulative packet size per connected master and slave (bytes) 3683system.membus.snoops 127972 # Total snoops (count) |
| 3657system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) | 3684system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) |
| 3658system.membus.snoop_fanout::samples 419404 # Request fanout histogram 3659system.membus.snoop_fanout::mean 0.012453 # Request fanout histogram 3660system.membus.snoop_fanout::stdev 0.110898 # Request fanout histogram | 3685system.membus.snoop_fanout::samples 419691 # Request fanout histogram 3686system.membus.snoop_fanout::mean 0.012454 # Request fanout histogram 3687system.membus.snoop_fanout::stdev 0.110902 # Request fanout histogram |
| 3661system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3688system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3662system.membus.snoop_fanout::0 414181 98.75% 98.75% # Request fanout histogram 3663system.membus.snoop_fanout::1 5223 1.25% 100.00% # Request fanout histogram | 3689system.membus.snoop_fanout::0 414464 98.75% 98.75% # Request fanout histogram 3690system.membus.snoop_fanout::1 5227 1.25% 100.00% # Request fanout histogram |
| 3664system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3665system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3666system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3667system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3691system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3692system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3693system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3694system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3668system.membus.snoop_fanout::total 419404 # Request fanout histogram 3669system.membus.reqLayer0.occupancy 81639999 # Layer occupancy (ticks) | 3695system.membus.snoop_fanout::total 419691 # Request fanout histogram 3696system.membus.reqLayer0.occupancy 81605499 # Layer occupancy (ticks) |
| 3670system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3671system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3672system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3697system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3698system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3699system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3673system.membus.reqLayer2.occupancy 11433500 # Layer occupancy (ticks) | 3700system.membus.reqLayer2.occupancy 11449000 # Layer occupancy (ticks) |
| 3674system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3701system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3675system.membus.reqLayer5.occupancy 984876925 # Layer occupancy (ticks) | 3702system.membus.reqLayer5.occupancy 986014542 # Layer occupancy (ticks) |
| 3676system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 3703system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 3677system.membus.respLayer2.occupancy 1099184232 # Layer occupancy (ticks) | 3704system.membus.respLayer2.occupancy 1099737525 # Layer occupancy (ticks) |
| 3678system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 3705system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 3679system.membus.respLayer3.occupancy 7225285 # Layer occupancy (ticks) | 3706system.membus.respLayer3.occupancy 7231369 # Layer occupancy (ticks) |
| 3680system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 3707system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3681system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3682system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3683system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3684system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3685system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3686system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3687system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 3708system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3709system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3710system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3711system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3712system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3713system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3714system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 3688system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3689system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3690system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3691system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3692system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3693system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3715system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3716system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3717system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3718system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3719system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3720system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3694system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3695system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 3721system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3722system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 3696system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3697system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3698system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3699system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3700system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3701system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3702system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3703system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3719system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3720system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3721system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3722system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3723system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3724system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3725system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3726system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3723system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3724system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3725system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3726system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3727system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3728system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3729system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3730system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3746system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3747system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3748system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3749system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3750system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3751system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3752system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3753system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3727system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3728system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3729system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3730system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3731system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3732system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3733system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states | 3754system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3755system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3756system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3757system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3758system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3759system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3760system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states |
| 3734system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3735system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3736system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3737system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3761system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3762system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3763system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3764system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3738system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3739system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3740system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3741system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3742system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3743system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3744system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3745system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3746system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3747system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3748system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3749system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3750system.toL2Bus.snoop_filter.tot_requests 1044885 # Total number of requests made to the snoop filter. 3751system.toL2Bus.snoop_filter.hit_single_requests 541195 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3752system.toL2Bus.snoop_filter.hit_multi_requests 200373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3753system.toL2Bus.snoop_filter.tot_snoops 29262 # Total number of snoops made to the snoop filter. 3754system.toL2Bus.snoop_filter.hit_single_snoops 27938 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3755system.toL2Bus.snoop_filter.hit_multi_snoops 1324 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3756system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states 3757system.toL2Bus.trans_dist::ReadReq 37997 # Transaction distribution 3758system.toL2Bus.trans_dist::ReadResp 522881 # Transaction distribution 3759system.toL2Bus.trans_dist::WriteReq 30912 # Transaction distribution 3760system.toL2Bus.trans_dist::WriteResp 30912 # Transaction distribution 3761system.toL2Bus.trans_dist::WritebackDirty 362121 # Transaction distribution 3762system.toL2Bus.trans_dist::CleanEvict 129726 # Transaction distribution 3763system.toL2Bus.trans_dist::UpgradeReq 111408 # Transaction distribution 3764system.toL2Bus.trans_dist::SCUpgradeReq 43843 # Transaction distribution 3765system.toL2Bus.trans_dist::UpgradeResp 155251 # Transaction distribution | 3765system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3766system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3767system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3768system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3769system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3770system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3771system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3772system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3773system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3774system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3775system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3776system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3777system.toL2Bus.snoop_filter.tot_requests 1045202 # Total number of requests made to the snoop filter. 3778system.toL2Bus.snoop_filter.hit_single_requests 540825 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3779system.toL2Bus.snoop_filter.hit_multi_requests 201129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3780system.toL2Bus.snoop_filter.tot_snoops 29372 # Total number of snoops made to the snoop filter. 3781system.toL2Bus.snoop_filter.hit_single_snoops 28126 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3782system.toL2Bus.snoop_filter.hit_multi_snoops 1246 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3783system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states 3784system.toL2Bus.trans_dist::ReadReq 38000 # Transaction distribution 3785system.toL2Bus.trans_dist::ReadResp 522906 # Transaction distribution 3786system.toL2Bus.trans_dist::WriteReq 30917 # Transaction distribution 3787system.toL2Bus.trans_dist::WriteResp 30917 # Transaction distribution 3788system.toL2Bus.trans_dist::WritebackDirty 362294 # Transaction distribution 3789system.toL2Bus.trans_dist::CleanEvict 129646 # Transaction distribution 3790system.toL2Bus.trans_dist::UpgradeReq 111513 # Transaction distribution 3791system.toL2Bus.trans_dist::SCUpgradeReq 43869 # Transaction distribution 3792system.toL2Bus.trans_dist::UpgradeResp 155382 # Transaction distribution |
| 3766system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution 3767system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution | 3793system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution 3794system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution |
| 3768system.toL2Bus.trans_dist::ReadExReq 50410 # Transaction distribution 3769system.toL2Bus.trans_dist::ReadExResp 50410 # Transaction distribution 3770system.toL2Bus.trans_dist::ReadSharedReq 484889 # Transaction distribution 3771system.toL2Bus.trans_dist::InvalidateReq 4647 # Transaction distribution 3772system.toL2Bus.trans_dist::InvalidateResp 3467 # Transaction distribution 3773system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1304964 # Packet count per connected master and slave (bytes) 3774system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322117 # Packet count per connected master and slave (bytes) 3775system.toL2Bus.pkt_count::total 1627081 # Packet count per connected master and slave (bytes) 3776system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36107224 # Cumulative packet size per connected master and slave (bytes) 3777system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5745684 # Cumulative packet size per connected master and slave (bytes) 3778system.toL2Bus.pkt_size::total 41852908 # Cumulative packet size per connected master and slave (bytes) 3779system.toL2Bus.snoops 395541 # Total snoops (count) 3780system.toL2Bus.snoopTraffic 15858252 # Total snoop traffic (bytes) 3781system.toL2Bus.snoop_fanout::samples 901455 # Request fanout histogram 3782system.toL2Bus.snoop_fanout::mean 0.406700 # Request fanout histogram 3783system.toL2Bus.snoop_fanout::stdev 0.494199 # Request fanout histogram | 3795system.toL2Bus.trans_dist::ReadExReq 50631 # Transaction distribution 3796system.toL2Bus.trans_dist::ReadExResp 50631 # Transaction distribution 3797system.toL2Bus.trans_dist::ReadSharedReq 484911 # Transaction distribution 3798system.toL2Bus.trans_dist::InvalidateReq 4651 # Transaction distribution 3799system.toL2Bus.trans_dist::InvalidateResp 3495 # Transaction distribution 3800system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1260717 # Packet count per connected master and slave (bytes) 3801system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 366727 # Packet count per connected master and slave (bytes) 3802system.toL2Bus.pkt_count::total 1627444 # Packet count per connected master and slave (bytes) 3803system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35956648 # Cumulative packet size per connected master and slave (bytes) 3804system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5894436 # Cumulative packet size per connected master and slave (bytes) 3805system.toL2Bus.pkt_size::total 41851084 # Cumulative packet size per connected master and slave (bytes) 3806system.toL2Bus.snoops 396095 # Total snoops (count) 3807system.toL2Bus.snoopTraffic 15886732 # Total snoop traffic (bytes) 3808system.toL2Bus.snoop_fanout::samples 901981 # Request fanout histogram 3809system.toL2Bus.snoop_fanout::mean 0.407509 # Request fanout histogram 3810system.toL2Bus.snoop_fanout::stdev 0.494174 # Request fanout histogram |
| 3784system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3811system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3785system.toL2Bus.snoop_fanout::0 536157 59.48% 59.48% # Request fanout histogram 3786system.toL2Bus.snoop_fanout::1 363974 40.38% 99.85% # Request fanout histogram 3787system.toL2Bus.snoop_fanout::2 1324 0.15% 100.00% # Request fanout histogram | 3812system.toL2Bus.snoop_fanout::0 535662 59.39% 59.39% # Request fanout histogram 3813system.toL2Bus.snoop_fanout::1 365073 40.47% 99.86% # Request fanout histogram 3814system.toL2Bus.snoop_fanout::2 1246 0.14% 100.00% # Request fanout histogram |
| 3788system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3789system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3790system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3815system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3816system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3817system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3791system.toL2Bus.snoop_fanout::total 901455 # Request fanout histogram 3792system.toL2Bus.reqLayer0.occupancy 896599840 # Layer occupancy (ticks) | 3818system.toL2Bus.snoop_fanout::total 901981 # Request fanout histogram 3819system.toL2Bus.reqLayer0.occupancy 896811514 # Layer occupancy (ticks) |
| 3793system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3820system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3794system.toL2Bus.snoopLayer0.occupancy 2176474 # Layer occupancy (ticks) | 3821system.toL2Bus.snoopLayer0.occupancy 2185239 # Layer occupancy (ticks) |
| 3795system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3822system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3796system.toL2Bus.respLayer0.occupancy 692364962 # Layer occupancy (ticks) | 3823system.toL2Bus.respLayer0.occupancy 675176627 # Layer occupancy (ticks) |
| 3797system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3824system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3798system.toL2Bus.respLayer1.occupancy 244002323 # Layer occupancy (ticks) | 3825system.toL2Bus.respLayer1.occupancy 261628851 # Layer occupancy (ticks) |
| 3799system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3800system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3801system.cpu0.kern.inst.quiesce 1835 # number of quiesce instructions executed 3802system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3826system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3827system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3828system.cpu0.kern.inst.quiesce 1835 # number of quiesce instructions executed 3829system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 3803system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed | 3830system.cpu1.kern.inst.quiesce 2792 # number of quiesce instructions executed |
| 3804 3805---------- End Simulation Statistics ---------- | 3831 3832---------- End Simulation Statistics ---------- |