| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.826111 # Number of seconds simulated 4sim_ticks 2826111083000 # Number of ticks simulated 5final_tick 2826111083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.826595 # Number of seconds simulated 4sim_ticks 2826594924500 # Number of ticks simulated 5final_tick 2826594924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 93135 # Simulator instruction rate (inst/s) 8host_op_rate 112984 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2190118612 # Simulator tick rate (ticks/s) 10host_mem_usage 627176 # Number of bytes of host memory used 11host_seconds 1290.39 # Real time elapsed on the host 12sim_insts 120180681 # Number of instructions simulated 13sim_ops 145794019 # Number of ops (including micro ops) simulated | 7host_inst_rate 79087 # Simulator instruction rate (inst/s) 8host_op_rate 95944 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1861516367 # Simulator tick rate (ticks/s) 10host_mem_usage 623016 # Number of bytes of host memory used 11host_seconds 1518.44 # Real time elapsed on the host 12sim_insts 120088860 # Number of instructions simulated 13sim_ops 145685275 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1920 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu0.inst 1301824 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1315176 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8404800 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu0.inst 1324752 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1304168 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8428096 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory | 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::cpu1.inst 186528 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 599252 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 416192 # Number of bytes read from this memory | 24system.physmem.bytes_read::cpu1.inst 175008 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 427200 # Number of bytes read from this memory |
| 27system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 27system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 28system.physmem.bytes_read::total 12227420 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 1301824 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 186528 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 1488352 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 8794944 # Number of bytes written to this memory | 28system.physmem.bytes_read::total 12249452 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 1324752 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 175008 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 1499760 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 8803008 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 33system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 35system.physmem.bytes_written::total 8812508 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 30 # Number of read requests responded to by this memory | 35system.physmem.bytes_written::total 8820572 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory | 37system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::cpu0.inst 22588 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 21070 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 131325 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory | 38system.physmem.num_reads::cpu0.inst 22950 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 20898 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 131689 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory |
| 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory | 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::cpu1.inst 2982 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 9384 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 6503 # Number of read requests responded to by this memory | 43system.physmem.num_reads::cpu1.inst 2802 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 6675 # Number of read requests responded to by this memory |
| 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 47system.physmem.num_reads::total 193909 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 137421 # Number of write requests responded to by this memory | 47system.physmem.num_reads::total 194257 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 137547 # Number of write requests responded to by this memory |
| 49system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 49system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 51system.physmem.num_writes::total 141812 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 679 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.num_writes::total 141938 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) |
| 53system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) |
| 54system.physmem.bw_read::cpu0.inst 460641 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 465366 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 2973981 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 181 # Total read bandwidth from this memory (bytes/s) | 54system.physmem.bw_read::cpu0.inst 468674 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 461392 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 2981713 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::cpu1.inst 66002 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 212041 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 147267 # Total read bandwidth from this memory (bytes/s) | 59system.physmem.bw_read::cpu1.inst 61915 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 207635 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 151136 # Total read bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) | 62system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_read::total 4326589 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 460641 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 66002 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 526643 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 3112031 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) | 63system.physmem.bw_read::total 4333643 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 468674 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 61915 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 530589 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 3114351 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 69system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 70system.physmem.bw_write::total 3118245 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 3112031 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 679 # Total bandwidth to/from this memory (bytes/s) | 70system.physmem.bw_write::total 3120565 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 3114351 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) |
| 73system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) | 73system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) |
| 74system.physmem.bw_total::cpu0.inst 460641 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 471567 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 2973981 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 181 # Total bandwidth to/from this memory (bytes/s) | 74system.physmem.bw_total::cpu0.inst 468674 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 467592 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 2981713 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) |
| 78system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) | 78system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) |
| 79system.physmem.bw_total::cpu1.inst 66002 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 212055 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 147267 # Total bandwidth to/from this memory (bytes/s) | 79system.physmem.bw_total::cpu1.inst 61915 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 207649 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 151136 # Total bandwidth to/from this memory (bytes/s) |
| 82system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) | 82system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) |
| 83system.physmem.bw_total::total 7444834 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 193910 # Number of read requests accepted 85system.physmem.writeReqs 141812 # Number of write requests accepted 86system.physmem.readBursts 193910 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 141812 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 12399936 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue 90system.physmem.bytesWritten 8824960 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 12227484 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 8812508 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one | 83system.physmem.bw_total::total 7454207 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 194258 # Number of read requests accepted 85system.physmem.writeReqs 141938 # Number of write requests accepted 86system.physmem.readBursts 194258 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 141938 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 12422976 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 90system.physmem.bytesWritten 8833536 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 12249516 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 8820572 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one |
| 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 96system.physmem.perBankRdBursts::0 12140 # Per bank write bursts 97system.physmem.perBankRdBursts::1 12135 # Per bank write bursts 98system.physmem.perBankRdBursts::2 12398 # Per bank write bursts 99system.physmem.perBankRdBursts::3 12886 # Per bank write bursts 100system.physmem.perBankRdBursts::4 14558 # Per bank write bursts 101system.physmem.perBankRdBursts::5 12353 # Per bank write bursts 102system.physmem.perBankRdBursts::6 12494 # Per bank write bursts 103system.physmem.perBankRdBursts::7 12590 # Per bank write bursts 104system.physmem.perBankRdBursts::8 12207 # Per bank write bursts 105system.physmem.perBankRdBursts::9 12490 # Per bank write bursts 106system.physmem.perBankRdBursts::10 11644 # Per bank write bursts 107system.physmem.perBankRdBursts::11 10772 # Per bank write bursts 108system.physmem.perBankRdBursts::12 11273 # Per bank write bursts 109system.physmem.perBankRdBursts::13 11534 # Per bank write bursts 110system.physmem.perBankRdBursts::14 11359 # Per bank write bursts 111system.physmem.perBankRdBursts::15 10916 # Per bank write bursts 112system.physmem.perBankWrBursts::0 8885 # Per bank write bursts 113system.physmem.perBankWrBursts::1 8987 # Per bank write bursts 114system.physmem.perBankWrBursts::2 9257 # Per bank write bursts 115system.physmem.perBankWrBursts::3 9509 # Per bank write bursts 116system.physmem.perBankWrBursts::4 8433 # Per bank write bursts 117system.physmem.perBankWrBursts::5 8902 # Per bank write bursts 118system.physmem.perBankWrBursts::6 9078 # Per bank write bursts 119system.physmem.perBankWrBursts::7 8908 # Per bank write bursts 120system.physmem.perBankWrBursts::8 8674 # Per bank write bursts 121system.physmem.perBankWrBursts::9 9007 # Per bank write bursts 122system.physmem.perBankWrBursts::10 8474 # Per bank write bursts 123system.physmem.perBankWrBursts::11 8031 # Per bank write bursts 124system.physmem.perBankWrBursts::12 8318 # Per bank write bursts 125system.physmem.perBankWrBursts::13 8000 # Per bank write bursts 126system.physmem.perBankWrBursts::14 7983 # Per bank write bursts 127system.physmem.perBankWrBursts::15 7444 # Per bank write bursts | 96system.physmem.perBankRdBursts::0 12130 # Per bank write bursts 97system.physmem.perBankRdBursts::1 12140 # Per bank write bursts 98system.physmem.perBankRdBursts::2 12480 # Per bank write bursts 99system.physmem.perBankRdBursts::3 12151 # Per bank write bursts 100system.physmem.perBankRdBursts::4 14882 # Per bank write bursts 101system.physmem.perBankRdBursts::5 12677 # Per bank write bursts 102system.physmem.perBankRdBursts::6 12709 # Per bank write bursts 103system.physmem.perBankRdBursts::7 12606 # Per bank write bursts 104system.physmem.perBankRdBursts::8 11844 # Per bank write bursts 105system.physmem.perBankRdBursts::9 11522 # Per bank write bursts 106system.physmem.perBankRdBursts::10 11334 # Per bank write bursts 107system.physmem.perBankRdBursts::11 10175 # Per bank write bursts 108system.physmem.perBankRdBursts::12 11497 # Per bank write bursts 109system.physmem.perBankRdBursts::13 12486 # Per bank write bursts 110system.physmem.perBankRdBursts::14 11961 # Per bank write bursts 111system.physmem.perBankRdBursts::15 11515 # Per bank write bursts 112system.physmem.perBankWrBursts::0 8842 # Per bank write bursts 113system.physmem.perBankWrBursts::1 8923 # Per bank write bursts 114system.physmem.perBankWrBursts::2 9151 # Per bank write bursts 115system.physmem.perBankWrBursts::3 8834 # Per bank write bursts 116system.physmem.perBankWrBursts::4 8743 # Per bank write bursts 117system.physmem.perBankWrBursts::5 9257 # Per bank write bursts 118system.physmem.perBankWrBursts::6 9174 # Per bank write bursts 119system.physmem.perBankWrBursts::7 9022 # Per bank write bursts 120system.physmem.perBankWrBursts::8 8380 # Per bank write bursts 121system.physmem.perBankWrBursts::9 8199 # Per bank write bursts 122system.physmem.perBankWrBursts::10 8228 # Per bank write bursts 123system.physmem.perBankWrBursts::11 7543 # Per bank write bursts 124system.physmem.perBankWrBursts::12 8493 # Per bank write bursts 125system.physmem.perBankWrBursts::13 8795 # Per bank write bursts 126system.physmem.perBankWrBursts::14 8486 # Per bank write bursts 127system.physmem.perBankWrBursts::15 7954 # Per bank write bursts |
| 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 129system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 130system.physmem.totGap 2826110796000 # Total gap between requests | 129system.physmem.numWrRetry 65 # Number of times write queue was full causing retry 130system.physmem.totGap 2826594637500 # Total gap between requests |
| 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 551 # Read request sizes (log2) 134system.physmem.readPktSize::3 28 # Read request sizes (log2) | 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 551 # Read request sizes (log2) 134system.physmem.readPktSize::3 28 # Read request sizes (log2) |
| 135system.physmem.readPktSize::4 3086 # Read request sizes (log2) | 135system.physmem.readPktSize::4 3091 # Read request sizes (log2) |
| 136system.physmem.readPktSize::5 0 # Read request sizes (log2) | 136system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 137system.physmem.readPktSize::6 190245 # Read request sizes (log2) | 137system.physmem.readPktSize::6 190588 # Read request sizes (log2) |
| 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 4391 # Write request sizes (log2) 141system.physmem.writePktSize::3 0 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) | 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 4391 # Write request sizes (log2) 141system.physmem.writePktSize::3 0 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 144system.physmem.writePktSize::6 137421 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 59620 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 70390 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 15526 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 12745 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 8439 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 7276 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 6358 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 5209 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 4584 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 1421 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 930 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 679 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 302 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 262 # What read queue length does an incoming req see | 144system.physmem.writePktSize::6 137547 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 58416 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 70500 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 15616 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 12705 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 8571 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 7500 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 6655 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 5421 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 4753 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 1522 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1119 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 307 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see |
| 159system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 159system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 192system.physmem.wrQLenPdf::15 2582 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 3484 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 4772 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 5590 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 5845 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 6981 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 7513 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 8598 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 8675 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 9940 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 10692 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 9261 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 9309 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 10995 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 8918 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 8250 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 7922 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 642 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 501 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 228 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 122 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 84734 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 250.487785 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 142.325533 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 306.970890 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 42837 50.55% 50.55% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 17738 20.93% 71.49% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 6168 7.28% 78.77% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 3519 4.15% 82.92% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 2713 3.20% 86.12% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 1549 1.83% 87.95% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 945 1.12% 89.07% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 1056 1.25% 90.31% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 8209 9.69% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 84734 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 6846 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 28.300175 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 562.386287 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-2047 6844 99.97% 99.97% # Reads before turning the bus around for writes | 192system.physmem.wrQLenPdf::15 2470 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 3315 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 3918 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 4463 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 5299 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 5685 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 6574 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 7253 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 8275 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 8191 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 9581 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 10090 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 8838 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 8671 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 9296 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 10600 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 8664 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 8349 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 1058 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 743 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 518 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 422 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 326 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 239 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 249 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 249 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 241 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 208 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 200 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 200 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 170 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 181 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 210 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 207 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 84597 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 251.267917 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 142.709069 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 307.432600 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 42654 50.42% 50.42% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 17739 20.97% 71.39% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 6092 7.20% 78.59% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 3470 4.10% 82.69% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 2903 3.43% 86.12% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 1534 1.81% 87.94% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 962 1.14% 89.07% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 998 1.18% 90.25% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 8245 9.75% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 84597 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 6823 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 28.448923 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 563.375084 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-2047 6821 99.97% 99.97% # Reads before turning the bus around for writes |
| 259system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes | 259system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::total 6846 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 6846 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.141689 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.636499 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 12.164291 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 5708 83.38% 83.38% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 378 5.52% 88.90% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 91 1.33% 90.23% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 47 0.69% 90.91% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 276 4.03% 94.95% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 33 0.48% 95.43% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 21 0.31% 95.73% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 23 0.34% 96.07% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 19 0.28% 96.35% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 10 0.15% 96.49% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 2 0.03% 96.52% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 9 0.13% 96.65% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 166 2.42% 99.08% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 9 0.13% 99.21% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 4 0.06% 99.27% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 11 0.16% 99.43% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 6 0.09% 99.52% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 2 0.03% 99.55% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 3 0.04% 99.59% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 2 0.03% 99.62% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::108-111 3 0.04% 99.68% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::116-119 2 0.03% 99.71% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::120-123 3 0.04% 99.75% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 7 0.10% 99.85% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::140-143 2 0.03% 99.88% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::144-147 2 0.03% 99.91% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::172-175 3 0.04% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::total 6846 # Writes before turning the bus around for reads 297system.physmem.totQLat 6600075879 # Total ticks spent queuing 298system.physmem.totMemAccLat 10232869629 # Total ticks spent from burst creation until serviced by the DRAM 299system.physmem.totBusLat 968745000 # Total ticks spent in databus transfers 300system.physmem.avgQLat 34065.08 # Average queueing delay per DRAM burst 301system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 302system.physmem.avgMemAccLat 52815.08 # Average memory access latency per DRAM burst 303system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s 304system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s | 261system.physmem.rdPerTurnAround::total 6823 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 6823 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.229225 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.516304 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 14.191757 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 5762 84.45% 84.45% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 386 5.66% 90.11% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 77 1.13% 91.24% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 44 0.64% 91.88% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 244 3.58% 95.46% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 18 0.26% 95.72% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 14 0.21% 95.93% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 12 0.18% 96.10% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 17 0.25% 96.35% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 2 0.03% 96.38% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 5 0.07% 96.45% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 8 0.12% 96.57% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 140 2.05% 98.62% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 6 0.09% 98.71% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 5 0.07% 98.78% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 10 0.15% 98.93% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 12 0.18% 99.11% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 1 0.01% 99.12% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 3 0.04% 99.16% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 2 0.03% 99.19% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 4 0.06% 99.25% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 3 0.04% 99.30% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 1 0.01% 99.31% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 8 0.12% 99.43% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::120-123 2 0.03% 99.46% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::124-127 2 0.03% 99.49% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::128-131 13 0.19% 99.68% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::132-135 1 0.01% 99.69% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::136-139 1 0.01% 99.71% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 2 0.03% 99.74% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::148-151 2 0.03% 99.77% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::160-163 4 0.06% 99.85% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::176-179 4 0.06% 99.91% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::total 6823 # Writes before turning the bus around for reads 304system.physmem.totQLat 10063104165 # Total ticks spent queuing 305system.physmem.totMemAccLat 13702647915 # Total ticks spent from burst creation until serviced by the DRAM 306system.physmem.totBusLat 970545000 # Total ticks spent in databus transfers 307system.physmem.avgQLat 51842.28 # Average queueing delay per DRAM burst 308system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst 309system.physmem.avgMemAccLat 70592.18 # Average memory access latency per DRAM burst 310system.physmem.avgRdBW 4.40 # Average DRAM read bandwidth in MiByte/s 311system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s |
| 305system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s 306system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s 307system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 308system.physmem.busUtil 0.06 # Data bus utilization in percentage 309system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 310system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 312system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s 313system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s 314system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 315system.physmem.busUtil 0.06 # Data bus utilization in percentage 316system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 317system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 311system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 312system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing 313system.physmem.readRowHits 161373 # Number of row buffer hits during reads 314system.physmem.writeRowHits 85531 # Number of row buffer hits during writes 315system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads 316system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes 317system.physmem.avgGap 8418008.94 # Average gap between requests 318system.physmem.pageHitRate 74.44 # Row buffer hit rate, read and write combined 319system.physmem_0.actEnergy 338612400 # Energy for activate commands per rank (pJ) 320system.physmem_0.preEnergy 184758750 # Energy for precharge commands per rank (pJ) 321system.physmem_0.readEnergy 792121200 # Energy for read commands per rank (pJ) 322system.physmem_0.writeEnergy 466294320 # Energy for write commands per rank (pJ) 323system.physmem_0.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) 324system.physmem_0.actBackEnergy 79311033765 # Energy for active background per rank (pJ) 325system.physmem_0.preBackEnergy 1626092117250 # Energy for precharge background per rank (pJ) 326system.physmem_0.totalEnergy 1891772383845 # Total energy per rank (pJ) 327system.physmem_0.averagePower 669.392029 # Core power per rank (mW) 328system.physmem_0.memoryStateTime::IDLE 2705053539598 # Time in different power states 329system.physmem_0.memoryStateTime::REF 94369860000 # Time in different power states 330system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 331system.physmem_0.memoryStateTime::ACT 26681946652 # Time in different power states 332system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 333system.physmem_1.actEnergy 301976640 # Energy for activate commands per rank (pJ) 334system.physmem_1.preEnergy 164769000 # Energy for precharge commands per rank (pJ) 335system.physmem_1.readEnergy 719113200 # Energy for read commands per rank (pJ) 336system.physmem_1.writeEnergy 427232880 # Energy for write commands per rank (pJ) 337system.physmem_1.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) 338system.physmem_1.actBackEnergy 78534447525 # Energy for active background per rank (pJ) 339system.physmem_1.preBackEnergy 1626773333250 # Energy for precharge background per rank (pJ) 340system.physmem_1.totalEnergy 1891508318655 # Total energy per rank (pJ) 341system.physmem_1.averagePower 669.298592 # Core power per rank (mW) 342system.physmem_1.memoryStateTime::IDLE 2706191706230 # Time in different power states 343system.physmem_1.memoryStateTime::REF 94369860000 # Time in different power states 344system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 345system.physmem_1.memoryStateTime::ACT 25549496770 # Time in different power states 346system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 347system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 318system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 319system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing 320system.physmem.readRowHits 161915 # Number of row buffer hits during reads 321system.physmem.writeRowHits 85621 # Number of row buffer hits during writes 322system.physmem.readRowHitRate 83.41 # Row buffer hit rate for reads 323system.physmem.writeRowHitRate 62.03 # Row buffer hit rate for writes 324system.physmem.avgGap 8407579.62 # Average gap between requests 325system.physmem.pageHitRate 74.52 # Row buffer hit rate, read and write combined 326system.physmem_0.actEnergy 318172680 # Energy for activate commands per rank (pJ) 327system.physmem_0.preEnergy 169112790 # Energy for precharge commands per rank (pJ) 328system.physmem_0.readEnergy 726673500 # Energy for read commands per rank (pJ) 329system.physmem_0.writeEnergy 375558120 # Energy for write commands per rank (pJ) 330system.physmem_0.refreshEnergy 4535428560.000001 # Energy for refresh commands per rank (pJ) 331system.physmem_0.actBackEnergy 4774700760 # Energy for active background per rank (pJ) 332system.physmem_0.preBackEnergy 244257600 # Energy for precharge background per rank (pJ) 333system.physmem_0.actPowerDownEnergy 9148762200 # Energy for active power-down per rank (pJ) 334system.physmem_0.prePowerDownEnergy 6477825120 # Energy for precharge power-down per rank (pJ) 335system.physmem_0.selfRefreshEnergy 667571113185 # Energy for self refresh per rank (pJ) 336system.physmem_0.totalEnergy 694343780025 # Total energy per rank (pJ) 337system.physmem_0.averagePower 245.646723 # Core power per rank (mW) 338system.physmem_0.totalIdleTime 2815396783365 # Total Idle time Per DRAM Rank 339system.physmem_0.memoryStateTime::IDLE 428149701 # Time in different power states 340system.physmem_0.memoryStateTime::REF 1926538000 # Time in different power states 341system.physmem_0.memoryStateTime::SREF 2778550744250 # Time in different power states 342system.physmem_0.memoryStateTime::PRE_PDN 16869300047 # Time in different power states 343system.physmem_0.memoryStateTime::ACT 8757031934 # Time in different power states 344system.physmem_0.memoryStateTime::ACT_PDN 20063160568 # Time in different power states 345system.physmem_1.actEnergy 285849900 # Energy for activate commands per rank (pJ) 346system.physmem_1.preEnergy 151932825 # Energy for precharge commands per rank (pJ) 347system.physmem_1.readEnergy 659264760 # Energy for read commands per rank (pJ) 348system.physmem_1.writeEnergy 344927160 # Energy for write commands per rank (pJ) 349system.physmem_1.refreshEnergy 4569848400.000001 # Energy for refresh commands per rank (pJ) 350system.physmem_1.actBackEnergy 4671042840 # Energy for active background per rank (pJ) 351system.physmem_1.preBackEnergy 250741920 # Energy for precharge background per rank (pJ) 352system.physmem_1.actPowerDownEnergy 8727797820 # Energy for active power-down per rank (pJ) 353system.physmem_1.prePowerDownEnergy 6816319680 # Energy for precharge power-down per rank (pJ) 354system.physmem_1.selfRefreshEnergy 667684488600 # Energy for self refresh per rank (pJ) 355system.physmem_1.totalEnergy 694164121065 # Total energy per rank (pJ) 356system.physmem_1.averagePower 245.583162 # Core power per rank (mW) 357system.physmem_1.totalIdleTime 2815694283339 # Total Idle time Per DRAM Rank 358system.physmem_1.memoryStateTime::IDLE 440101951 # Time in different power states 359system.physmem_1.memoryStateTime::REF 1941710000 # Time in different power states 360system.physmem_1.memoryStateTime::SREF 2778803468000 # Time in different power states 361system.physmem_1.memoryStateTime::PRE_PDN 17750764755 # Time in different power states 362system.physmem_1.memoryStateTime::ACT 8518829210 # Time in different power states 363system.physmem_1.memoryStateTime::ACT_PDN 19140050584 # Time in different power states 364system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 348system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 349system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 351system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 352system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 353system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 354system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 355system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 356system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 357system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 364system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 365system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) | 365system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 366system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 367system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 368system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 369system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 370system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 371system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 372system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 373system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 374system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 379system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 380system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 381system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) |
| 366system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 367system.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 368system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 383system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 384system.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 385system.bridge.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 369system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 370system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 371system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 372system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 373system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 374system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 386system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 387system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 388system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 389system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 390system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 391system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 375system.cpu0.branchPred.lookups 23913557 # Number of BP lookups 376system.cpu0.branchPred.condPredicted 15655751 # Number of conditional branches predicted 377system.cpu0.branchPred.condIncorrect 926443 # Number of conditional branches incorrect 378system.cpu0.branchPred.BTBLookups 14584665 # Number of BTB lookups 379system.cpu0.branchPred.BTBHits 9536401 # Number of BTB hits | 392system.cpu0.branchPred.lookups 53161527 # Number of BP lookups 393system.cpu0.branchPred.condPredicted 24432585 # Number of conditional branches predicted 394system.cpu0.branchPred.condIncorrect 935077 # Number of conditional branches incorrect 395system.cpu0.branchPred.BTBLookups 32150468 # Number of BTB lookups 396system.cpu0.branchPred.BTBHits 13984916 # Number of BTB hits |
| 380system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 397system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 381system.cpu0.branchPred.BTBHitPct 65.386493 # BTB Hit Percentage 382system.cpu0.branchPred.usedRAS 3854213 # Number of times the RAS was used to get a target. 383system.cpu0.branchPred.RASInCorrect 33180 # Number of incorrect RAS predictions. 384system.cpu0.branchPred.indirectLookups 1360238 # Number of indirect predictor lookups. 385system.cpu0.branchPred.indirectHits 1204672 # Number of indirect target hits. 386system.cpu0.branchPred.indirectMisses 155566 # Number of indirect misses. 387system.cpu0.branchPredindirectMispredicted 48773 # Number of mispredicted indirect branches. | 398system.cpu0.branchPred.BTBHitPct 43.498328 # BTB Hit Percentage 399system.cpu0.branchPred.usedRAS 15489494 # Number of times the RAS was used to get a target. 400system.cpu0.branchPred.RASInCorrect 33173 # Number of incorrect RAS predictions. 401system.cpu0.branchPred.indirectLookups 10133739 # Number of indirect predictor lookups. 402system.cpu0.branchPred.indirectHits 9977658 # Number of indirect target hits. 403system.cpu0.branchPred.indirectMisses 156081 # Number of indirect misses. 404system.cpu0.branchPredindirectMispredicted 49006 # Number of mispredicted indirect branches. |
| 388system.cpu_clk_domain.clock 500 # Clock period in ticks | 405system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 389system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 406system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 411system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 414system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 415system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 416system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 417system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 418system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 428system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 429system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 430system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 431system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 432system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 433system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 434system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 435system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 419system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 420system.cpu0.dtb.walker.walks 65918 # Table walker walks requested 421system.cpu0.dtb.walker.walksShort 65918 # Table walker walks initiated with short descriptors 422system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25327 # Level at which table walker walks with short descriptors terminate 423system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18922 # Level at which table walker walks with short descriptors terminate 424system.cpu0.dtb.walker.walksSquashedBefore 21669 # Table walks squashed before starting 425system.cpu0.dtb.walker.walkWaitTime::samples 44249 # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::mean 506.926710 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::stdev 3129.335275 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::0-8191 43005 97.19% 97.19% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::8192-16383 929 2.10% 99.29% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.33% 99.62% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.87% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::32768-40959 23 0.05% 99.92% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 100.00% # Table walker wait (enqueue to first request) latency | 436system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 437system.cpu0.dtb.walker.walks 66483 # Table walker walks requested 438system.cpu0.dtb.walker.walksShort 66483 # Table walker walks initiated with short descriptors 439system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25519 # Level at which table walker walks with short descriptors terminate 440system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19054 # Level at which table walker walks with short descriptors terminate 441system.cpu0.dtb.walker.walksSquashedBefore 21910 # Table walks squashed before starting 442system.cpu0.dtb.walker.walkWaitTime::samples 44573 # Table walker wait (enqueue to first request) latency 443system.cpu0.dtb.walker.walkWaitTime::mean 499.046508 # Table walker wait (enqueue to first request) latency 444system.cpu0.dtb.walker.walkWaitTime::stdev 3114.296115 # Table walker wait (enqueue to first request) latency 445system.cpu0.dtb.walker.walkWaitTime::0-8191 43354 97.27% 97.27% # Table walker wait (enqueue to first request) latency 446system.cpu0.dtb.walker.walkWaitTime::8192-16383 917 2.06% 99.32% # Table walker wait (enqueue to first request) latency 447system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.60% # Table walker wait (enqueue to first request) latency 448system.cpu0.dtb.walker.walkWaitTime::24576-32767 116 0.26% 99.86% # Table walker wait (enqueue to first request) latency 449system.cpu0.dtb.walker.walkWaitTime::32768-40959 24 0.05% 99.92% # Table walker wait (enqueue to first request) latency 450system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency 451system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency |
| 436system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 452system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 453system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 438system.cpu0.dtb.walker.walkWaitTime::total 44249 # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkCompletionTime::samples 16055 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022 # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::gmean 9898.999015 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::stdev 6813.334576 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::0-16383 14595 90.91% 90.91% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1294 8.06% 98.97% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::32768-49151 134 0.83% 99.80% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::49152-65535 9 0.06% 99.86% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.88% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::98304-114687 17 0.11% 99.99% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::total 16055 # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walksPending::samples 85920956152 # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::mean 0.541941 # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::stdev 0.508329 # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::0-1 85862493152 99.93% 99.93% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::2-3 40323000 0.05% 99.98% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::4-5 8212500 0.01% 99.99% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::6-7 5190500 0.01% 99.99% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::8-9 2626000 0.00% 100.00% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::12-13 886000 0.00% 100.00% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::14-15 336500 0.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::16-17 44000 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::total 85920956152 # Table walker pending requests distribution 465system.cpu0.dtb.walker.walkPageSizes::4K 5102 78.63% 78.63% # Table walker page sizes translated 466system.cpu0.dtb.walker.walkPageSizes::1M 1387 21.37% 100.00% # Table walker page sizes translated 467system.cpu0.dtb.walker.walkPageSizes::total 6489 # Table walker page sizes translated 468system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65918 # Table walker requests started/completed, data/inst | 454system.cpu0.dtb.walker.walkWaitTime::total 44573 # Table walker wait (enqueue to first request) latency 455system.cpu0.dtb.walker.walkCompletionTime::samples 16394 # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::mean 11498.017567 # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::gmean 9809.718618 # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::stdev 10152.442305 # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walkCompletionTime::0-16383 14883 90.78% 90.78% # Table walker service (enqueue to completion) latency 460system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1339 8.17% 98.95% # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walkCompletionTime::32768-49151 129 0.79% 99.74% # Table walker service (enqueue to completion) latency 462system.cpu0.dtb.walker.walkCompletionTime::49152-65535 18 0.11% 99.85% # Table walker service (enqueue to completion) latency 463system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.01% 99.86% # Table walker service (enqueue to completion) latency 464system.cpu0.dtb.walker.walkCompletionTime::114688-131071 6 0.04% 99.90% # Table walker service (enqueue to completion) latency 465system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.90% # Table walker service (enqueue to completion) latency 466system.cpu0.dtb.walker.walkCompletionTime::245760-262143 16 0.10% 100.00% # Table walker service (enqueue to completion) latency 467system.cpu0.dtb.walker.walkCompletionTime::total 16394 # Table walker service (enqueue to completion) latency 468system.cpu0.dtb.walker.walksPending::samples 86404933652 # Table walker pending requests distribution 469system.cpu0.dtb.walker.walksPending::mean 0.566419 # Table walker pending requests distribution 470system.cpu0.dtb.walker.walksPending::stdev 0.506005 # Table walker pending requests distribution 471system.cpu0.dtb.walker.walksPending::0-1 86345641152 99.93% 99.93% # Table walker pending requests distribution 472system.cpu0.dtb.walker.walksPending::2-3 41095500 0.05% 99.98% # Table walker pending requests distribution 473system.cpu0.dtb.walker.walksPending::4-5 8202000 0.01% 99.99% # Table walker pending requests distribution 474system.cpu0.dtb.walker.walksPending::6-7 4970000 0.01% 99.99% # Table walker pending requests distribution 475system.cpu0.dtb.walker.walksPending::8-9 2695000 0.00% 100.00% # Table walker pending requests distribution 476system.cpu0.dtb.walker.walksPending::10-11 946000 0.00% 100.00% # Table walker pending requests distribution 477system.cpu0.dtb.walker.walksPending::12-13 940000 0.00% 100.00% # Table walker pending requests distribution 478system.cpu0.dtb.walker.walksPending::14-15 429500 0.00% 100.00% # Table walker pending requests distribution 479system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution 480system.cpu0.dtb.walker.walksPending::total 86404933652 # Table walker pending requests distribution 481system.cpu0.dtb.walker.walkPageSizes::4K 5203 78.33% 78.33% # Table walker page sizes translated 482system.cpu0.dtb.walker.walkPageSizes::1M 1439 21.67% 100.00% # Table walker page sizes translated 483system.cpu0.dtb.walker.walkPageSizes::total 6642 # Table walker page sizes translated 484system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66483 # Table walker requests started/completed, data/inst |
| 469system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 485system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 470system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65918 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6489 # Table walker requests started/completed, data/inst | 486system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66483 # Table walker requests started/completed, data/inst 487system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6642 # Table walker requests started/completed, data/inst |
| 472system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 488system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 473system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6489 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin::total 72407 # Table walker requests started/completed, data/inst | 489system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6642 # Table walker requests started/completed, data/inst 490system.cpu0.dtb.walker.walkRequestOrigin::total 73125 # Table walker requests started/completed, data/inst |
| 475system.cpu0.dtb.inst_hits 0 # ITB inst hits 476system.cpu0.dtb.inst_misses 0 # ITB inst misses | 491system.cpu0.dtb.inst_hits 0 # ITB inst hits 492system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 477system.cpu0.dtb.read_hits 17729387 # DTB read hits 478system.cpu0.dtb.read_misses 55806 # DTB read misses 479system.cpu0.dtb.write_hits 14606301 # DTB write hits 480system.cpu0.dtb.write_misses 10112 # DTB write misses | 493system.cpu0.dtb.read_hits 23680324 # DTB read hits 494system.cpu0.dtb.read_misses 56461 # DTB read misses 495system.cpu0.dtb.write_hits 17598903 # DTB write hits 496system.cpu0.dtb.write_misses 10022 # DTB write misses |
| 481system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 482system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 483system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 484system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 497system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 498system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 499system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 485system.cpu0.dtb.flush_entries 3431 # Number of entries that have been flushed from TLB 486system.cpu0.dtb.align_faults 353 # Number of TLB faults due to alignment restrictions 487system.cpu0.dtb.prefetch_faults 2188 # Number of TLB faults due to prefetch | 501system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB 502system.cpu0.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions 503system.cpu0.dtb.prefetch_faults 2246 # Number of TLB faults due to prefetch |
| 488system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 504system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 489system.cpu0.dtb.perms_faults 939 # Number of TLB faults due to permissions restrictions 490system.cpu0.dtb.read_accesses 17785193 # DTB read accesses 491system.cpu0.dtb.write_accesses 14616413 # DTB write accesses | 505system.cpu0.dtb.perms_faults 902 # Number of TLB faults due to permissions restrictions 506system.cpu0.dtb.read_accesses 23736785 # DTB read accesses 507system.cpu0.dtb.write_accesses 17608925 # DTB write accesses |
| 492system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 508system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 493system.cpu0.dtb.hits 32335688 # DTB hits 494system.cpu0.dtb.misses 65918 # DTB misses 495system.cpu0.dtb.accesses 32401606 # DTB accesses 496system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 509system.cpu0.dtb.hits 41279227 # DTB hits 510system.cpu0.dtb.misses 66483 # DTB misses 511system.cpu0.dtb.accesses 41345710 # DTB accesses 512system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 497system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 518system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 519system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 520system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 521system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 522system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 523system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 524system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 525system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 513system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 514system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 515system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 516system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 517system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 518system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 519system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 520system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 534system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 535system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 536system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 537system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 538system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 539system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 540system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 541system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 526system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 527system.cpu0.itb.walker.walks 10845 # Table walker walks requested 528system.cpu0.itb.walker.walksShort 10845 # Table walker walks initiated with short descriptors 529system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3752 # Level at which table walker walks with short descriptors terminate 530system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6021 # Level at which table walker walks with short descriptors terminate 531system.cpu0.itb.walker.walksSquashedBefore 1072 # Table walks squashed before starting 532system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::mean 438.606364 # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::stdev 2276.348067 # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::0-4095 9409 96.28% 96.28% # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.92% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::8192-12287 121 1.24% 99.16% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::12288-16383 47 0.48% 99.64% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.71% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::20480-24575 16 0.16% 99.88% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::24576-28671 6 0.06% 99.94% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkCompletionTime::samples 3657 # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837 # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595 # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::stdev 4878.254960 # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::0-8191 514 14.06% 14.06% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::8192-16383 2884 78.86% 92.92% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::16384-24575 170 4.65% 97.57% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::24576-32767 55 1.50% 99.07% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::32768-40959 31 0.85% 99.92% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::total 3657 # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walksPending::samples 21495635712 # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::mean 0.820169 # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::stdev 0.384194 # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::0 3866725500 17.99% 17.99% # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::1 17627832712 82.01% 99.99% # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::2 1008500 0.00% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::3 69000 0.00% 100.00% # Table walker pending requests distribution 565system.cpu0.itb.walker.walksPending::total 21495635712 # Table walker pending requests distribution 566system.cpu0.itb.walker.walkPageSizes::4K 2254 87.20% 87.20% # Table walker page sizes translated 567system.cpu0.itb.walker.walkPageSizes::1M 331 12.80% 100.00% # Table walker page sizes translated 568system.cpu0.itb.walker.walkPageSizes::total 2585 # Table walker page sizes translated | 542system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 543system.cpu0.itb.walker.walks 11041 # Table walker walks requested 544system.cpu0.itb.walker.walksShort 11041 # Table walker walks initiated with short descriptors 545system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4028 # Level at which table walker walks with short descriptors terminate 546system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5930 # Level at which table walker walks with short descriptors terminate 547system.cpu0.itb.walker.walksSquashedBefore 1083 # Table walks squashed before starting 548system.cpu0.itb.walker.walkWaitTime::samples 9958 # Table walker wait (enqueue to first request) latency 549system.cpu0.itb.walker.walkWaitTime::mean 410.574413 # Table walker wait (enqueue to first request) latency 550system.cpu0.itb.walker.walkWaitTime::stdev 2129.037976 # Table walker wait (enqueue to first request) latency 551system.cpu0.itb.walker.walkWaitTime::0-4095 9588 96.28% 96.28% # Table walker wait (enqueue to first request) latency 552system.cpu0.itb.walker.walkWaitTime::4096-8191 186 1.87% 98.15% # Table walker wait (enqueue to first request) latency 553system.cpu0.itb.walker.walkWaitTime::8192-12287 118 1.18% 99.34% # Table walker wait (enqueue to first request) latency 554system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.38% 99.72% # Table walker wait (enqueue to first request) latency 555system.cpu0.itb.walker.walkWaitTime::16384-20479 5 0.05% 99.77% # Table walker wait (enqueue to first request) latency 556system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.92% # Table walker wait (enqueue to first request) latency 557system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency 558system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency 559system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 560system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 561system.cpu0.itb.walker.walkWaitTime::total 9958 # Table walker wait (enqueue to first request) latency 562system.cpu0.itb.walker.walkCompletionTime::samples 3663 # Table walker service (enqueue to completion) latency 563system.cpu0.itb.walker.walkCompletionTime::mean 12262.353262 # Table walker service (enqueue to completion) latency 564system.cpu0.itb.walker.walkCompletionTime::gmean 11250.035596 # Table walker service (enqueue to completion) latency 565system.cpu0.itb.walker.walkCompletionTime::stdev 5522.553888 # Table walker service (enqueue to completion) latency 566system.cpu0.itb.walker.walkCompletionTime::0-8191 663 18.10% 18.10% # Table walker service (enqueue to completion) latency 567system.cpu0.itb.walker.walkCompletionTime::8192-16383 2695 73.57% 91.67% # Table walker service (enqueue to completion) latency 568system.cpu0.itb.walker.walkCompletionTime::16384-24575 173 4.72% 96.40% # Table walker service (enqueue to completion) latency 569system.cpu0.itb.walker.walkCompletionTime::24576-32767 79 2.16% 98.55% # Table walker service (enqueue to completion) latency 570system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.89% # Table walker service (enqueue to completion) latency 571system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.97% # Table walker service (enqueue to completion) latency 572system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 573system.cpu0.itb.walker.walkCompletionTime::total 3663 # Table walker service (enqueue to completion) latency 574system.cpu0.itb.walker.walksPending::samples 21980185712 # Table walker pending requests distribution 575system.cpu0.itb.walker.walksPending::mean 0.834654 # Table walker pending requests distribution 576system.cpu0.itb.walker.walksPending::stdev 0.371618 # Table walker pending requests distribution 577system.cpu0.itb.walker.walksPending::0 3635314000 16.54% 16.54% # Table walker pending requests distribution 578system.cpu0.itb.walker.walksPending::1 18343952712 83.46% 100.00% # Table walker pending requests distribution 579system.cpu0.itb.walker.walksPending::2 868500 0.00% 100.00% # Table walker pending requests distribution 580system.cpu0.itb.walker.walksPending::3 50500 0.00% 100.00% # Table walker pending requests distribution 581system.cpu0.itb.walker.walksPending::total 21980185712 # Table walker pending requests distribution 582system.cpu0.itb.walker.walkPageSizes::4K 2243 86.94% 86.94% # Table walker page sizes translated 583system.cpu0.itb.walker.walkPageSizes::1M 337 13.06% 100.00% # Table walker page sizes translated 584system.cpu0.itb.walker.walkPageSizes::total 2580 # Table walker page sizes translated |
| 569system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 585system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 570system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10845 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10845 # Table walker requests started/completed, data/inst | 586system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11041 # Table walker requests started/completed, data/inst 587system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11041 # Table walker requests started/completed, data/inst |
| 572system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 588system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 573system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2585 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2585 # Table walker requests started/completed, data/inst 575system.cpu0.itb.walker.walkRequestOrigin::total 13430 # Table walker requests started/completed, data/inst 576system.cpu0.itb.inst_hits 37503849 # ITB inst hits 577system.cpu0.itb.inst_misses 10845 # ITB inst misses | 589system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2580 # Table walker requests started/completed, data/inst 590system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2580 # Table walker requests started/completed, data/inst 591system.cpu0.itb.walker.walkRequestOrigin::total 13621 # Table walker requests started/completed, data/inst 592system.cpu0.itb.inst_hits 72829698 # ITB inst hits 593system.cpu0.itb.inst_misses 11041 # ITB inst misses |
| 578system.cpu0.itb.read_hits 0 # DTB read hits 579system.cpu0.itb.read_misses 0 # DTB read misses 580system.cpu0.itb.write_hits 0 # DTB write hits 581system.cpu0.itb.write_misses 0 # DTB write misses 582system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 583system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 584system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 585system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 594system.cpu0.itb.read_hits 0 # DTB read hits 595system.cpu0.itb.read_misses 0 # DTB read misses 596system.cpu0.itb.write_hits 0 # DTB write hits 597system.cpu0.itb.write_misses 0 # DTB write misses 598system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 599system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 600system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 601system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 586system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB | 602system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB |
| 587system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 588system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 589system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 603system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 604system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 605system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 590system.cpu0.itb.perms_faults 1944 # Number of TLB faults due to permissions restrictions | 606system.cpu0.itb.perms_faults 1929 # Number of TLB faults due to permissions restrictions |
| 591system.cpu0.itb.read_accesses 0 # DTB read accesses 592system.cpu0.itb.write_accesses 0 # DTB write accesses | 607system.cpu0.itb.read_accesses 0 # DTB read accesses 608system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 593system.cpu0.itb.inst_accesses 37514694 # ITB inst accesses 594system.cpu0.itb.hits 37503849 # DTB hits 595system.cpu0.itb.misses 10845 # DTB misses 596system.cpu0.itb.accesses 37514694 # DTB accesses 597system.cpu0.numPwrStateTransitions 3712 # Number of power state transitions 598system.cpu0.pwrStateClkGateDist::samples 1856 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::mean 1487215700.959052 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::stdev 23895599673.728432 # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::underflows 1080 58.19% 58.19% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::1000-5e+10 769 41.43% 99.62% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state | 609system.cpu0.itb.inst_accesses 72840739 # ITB inst accesses 610system.cpu0.itb.hits 72829698 # DTB hits 611system.cpu0.itb.misses 11041 # DTB misses 612system.cpu0.itb.accesses 72840739 # DTB accesses 613system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions 614system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state 615system.cpu0.pwrStateClkGateDist::mean 1456796210.372727 # Distribution of time spent in the clock gated state 616system.cpu0.pwrStateClkGateDist::stdev 23672658216.113400 # Distribution of time spent in the clock gated state 617system.cpu0.pwrStateClkGateDist::underflows 1093 58.45% 58.45% # Distribution of time spent in the clock gated state 618system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.28% 99.73% # Distribution of time spent in the clock gated state 619system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state 620system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state |
| 606system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 621system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 607system.cpu0.pwrStateClkGateDist::max_value 499971395296 # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::total 1856 # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateResidencyTicks::ON 65838742020 # Cumulative time (in ticks) in various power states 610system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980 # Cumulative time (in ticks) in various power states 611system.cpu0.numCycles 131678547 # number of cpu cycles simulated | 622system.cpu0.pwrStateClkGateDist::max_value 499970757520 # Distribution of time spent in the clock gated state 623system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state 624system.cpu0.pwrStateResidencyTicks::ON 102386011103 # Cumulative time (in ticks) in various power states 625system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724208913397 # Cumulative time (in ticks) in various power states 626system.cpu0.numCycles 204773026 # number of cpu cycles simulated |
| 612system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 613system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 627system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 628system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 614system.cpu0.fetch.icacheStallCycles 19262499 # Number of cycles fetch is stalled on an Icache miss 615system.cpu0.fetch.Insts 112028029 # Number of instructions fetch has processed 616system.cpu0.fetch.Branches 23913557 # Number of branches that fetch encountered 617system.cpu0.fetch.predictedBranches 14595286 # Number of branches that fetch has predicted taken 618system.cpu0.fetch.Cycles 106047706 # Number of cycles fetch has run and was not squashing or blocked 619system.cpu0.fetch.SquashCycles 2739238 # Number of cycles fetch has spent squashing 620system.cpu0.fetch.TlbCycles 149116 # Number of cycles fetch has spent waiting for tlb 621system.cpu0.fetch.MiscStallCycles 57008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 622system.cpu0.fetch.PendingTrapStallCycles 423158 # Number of stall cycles due to pending traps 623system.cpu0.fetch.PendingQuiesceStallCycles 407524 # Number of stall cycles due to pending quiesce instructions 624system.cpu0.fetch.IcacheWaitRetryStallCycles 94244 # Number of stall cycles due to full MSHR 625system.cpu0.fetch.CacheLines 37503537 # Number of cache lines fetched 626system.cpu0.fetch.IcacheSquashes 259263 # Number of outstanding Icache misses that were squashed 627system.cpu0.fetch.ItlbSquashes 5228 # Number of outstanding ITLB misses that were squashed 628system.cpu0.fetch.rateDist::samples 127810874 # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.rateDist::mean 1.056272 # Number of instructions fetched each cycle (Total) 630system.cpu0.fetch.rateDist::stdev 1.258048 # Number of instructions fetched each cycle (Total) | 629system.cpu0.fetch.icacheStallCycles 20714269 # Number of cycles fetch is stalled on an Icache miss 630system.cpu0.fetch.Insts 196101622 # Number of instructions fetch has processed 631system.cpu0.fetch.Branches 53161527 # Number of branches that fetch encountered 632system.cpu0.fetch.predictedBranches 39452068 # Number of branches that fetch has predicted taken 633system.cpu0.fetch.Cycles 175603283 # Number of cycles fetch has run and was not squashing or blocked 634system.cpu0.fetch.SquashCycles 5698298 # Number of cycles fetch has spent squashing 635system.cpu0.fetch.TlbCycles 148281 # Number of cycles fetch has spent waiting for tlb 636system.cpu0.fetch.MiscStallCycles 57647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 637system.cpu0.fetch.PendingTrapStallCycles 420719 # Number of stall cycles due to pending traps 638system.cpu0.fetch.PendingQuiesceStallCycles 418648 # Number of stall cycles due to pending quiesce instructions 639system.cpu0.fetch.IcacheWaitRetryStallCycles 100050 # Number of stall cycles due to full MSHR 640system.cpu0.fetch.CacheLines 72829386 # Number of cache lines fetched 641system.cpu0.fetch.IcacheSquashes 258768 # Number of outstanding Icache misses that were squashed 642system.cpu0.fetch.ItlbSquashes 5384 # Number of outstanding ITLB misses that were squashed 643system.cpu0.fetch.rateDist::samples 200312046 # Number of instructions fetched each cycle (Total) 644system.cpu0.fetch.rateDist::mean 1.196487 # Number of instructions fetched each cycle (Total) 645system.cpu0.fetch.rateDist::stdev 1.307164 # Number of instructions fetched each cycle (Total) |
| 631system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 646system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 632system.cpu0.fetch.rateDist::0 65678610 51.39% 51.39% # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::1 21331326 16.69% 68.08% # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::2 8731054 6.83% 74.91% # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::3 32069884 25.09% 100.00% # Number of instructions fetched each cycle (Total) | 647system.cpu0.fetch.rateDist::0 95293979 47.57% 47.57% # Number of instructions fetched each cycle (Total) 648system.cpu0.fetch.rateDist::1 30393228 15.17% 62.75% # Number of instructions fetched each cycle (Total) 649system.cpu0.fetch.rateDist::2 14596992 7.29% 70.03% # Number of instructions fetched each cycle (Total) 650system.cpu0.fetch.rateDist::3 60027847 29.97% 100.00% # Number of instructions fetched each cycle (Total) |
| 636system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 651system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 652system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 653system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 639system.cpu0.fetch.rateDist::total 127810874 # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.branchRate 0.181606 # Number of branch fetches per cycle 641system.cpu0.fetch.rate 0.850769 # Number of inst fetches per cycle 642system.cpu0.decode.IdleCycles 19867897 # Number of cycles decode is idle 643system.cpu0.decode.BlockedCycles 60850603 # Number of cycles decode is blocked 644system.cpu0.decode.RunCycles 41086114 # Number of cycles decode is running 645system.cpu0.decode.UnblockCycles 4967748 # Number of cycles decode is unblocking 646system.cpu0.decode.SquashCycles 1038512 # Number of cycles decode is squashing 647system.cpu0.decode.BranchResolved 3035925 # Number of times decode resolved a branch 648system.cpu0.decode.BranchMispred 335186 # Number of times decode detected a branch misprediction 649system.cpu0.decode.DecodedInsts 110135169 # Number of instructions handled by decode 650system.cpu0.decode.SquashedInsts 3776324 # Number of squashed instructions handled by decode 651system.cpu0.rename.SquashCycles 1038512 # Number of cycles rename is squashing 652system.cpu0.rename.IdleCycles 25520251 # Number of cycles rename is idle 653system.cpu0.rename.BlockCycles 12577304 # Number of cycles rename is blocking 654system.cpu0.rename.serializeStallCycles 37369361 # count of cycles rename stalled for serializing inst 655system.cpu0.rename.RunCycles 40264186 # Number of cycles rename is running 656system.cpu0.rename.UnblockCycles 11041260 # Number of cycles rename is unblocking 657system.cpu0.rename.RenamedInsts 105172145 # Number of instructions processed by rename 658system.cpu0.rename.SquashedInsts 1006076 # Number of squashed instructions processed by rename 659system.cpu0.rename.ROBFullEvents 1476626 # Number of times rename has blocked due to ROB full 660system.cpu0.rename.IQFullEvents 165177 # Number of times rename has blocked due to IQ full 661system.cpu0.rename.LQFullEvents 58768 # Number of times rename has blocked due to LQ full 662system.cpu0.rename.SQFullEvents 6832387 # Number of times rename has blocked due to SQ full 663system.cpu0.rename.RenamedOperands 109365921 # Number of destination operands rename has renamed 664system.cpu0.rename.RenameLookups 480109573 # Number of register rename lookups that rename has made 665system.cpu0.rename.int_rename_lookups 120259513 # Number of integer rename lookups 666system.cpu0.rename.fp_rename_lookups 9447 # Number of floating rename lookups 667system.cpu0.rename.CommittedMaps 98266494 # Number of HB maps that are committed 668system.cpu0.rename.UndoneMaps 11099416 # Number of HB maps that are undone due to squashing 669system.cpu0.rename.serializingInsts 1228555 # count of serializing insts renamed 670system.cpu0.rename.tempSerializingInsts 1085594 # count of temporary serializing insts renamed 671system.cpu0.rename.skidInsts 12372656 # count of insts added to the skid buffer 672system.cpu0.memDep0.insertedLoads 18663457 # Number of loads inserted to the mem dependence unit. 673system.cpu0.memDep0.insertedStores 16076197 # Number of stores inserted to the mem dependence unit. 674system.cpu0.memDep0.conflictingLoads 1697816 # Number of conflicting loads. 675system.cpu0.memDep0.conflictingStores 2228906 # Number of conflicting stores. 676system.cpu0.iq.iqInstsAdded 102290291 # Number of instructions added to the IQ (excludes non-spec) 677system.cpu0.iq.iqNonSpecInstsAdded 1693186 # Number of non-speculative instructions added to the IQ 678system.cpu0.iq.iqInstsIssued 100457201 # Number of instructions issued 679system.cpu0.iq.iqSquashedInstsIssued 451571 # Number of squashed instructions issued 680system.cpu0.iq.iqSquashedInstsExamined 9045594 # Number of squashed instructions iterated over during squash; mainly for profiling 681system.cpu0.iq.iqSquashedOperandsExamined 21384310 # Number of squashed operands that are examined and possibly removed from graph 682system.cpu0.iq.iqSquashedNonSpecRemoved 120136 # Number of squashed non-spec instructions that were removed 683system.cpu0.iq.issued_per_cycle::samples 127810874 # Number of insts issued each cycle 684system.cpu0.iq.issued_per_cycle::mean 0.785983 # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::stdev 1.028831 # Number of insts issued each cycle | 654system.cpu0.fetch.rateDist::total 200312046 # Number of instructions fetched each cycle (Total) 655system.cpu0.fetch.branchRate 0.259612 # Number of branch fetches per cycle 656system.cpu0.fetch.rate 0.957654 # Number of inst fetches per cycle 657system.cpu0.decode.IdleCycles 25714917 # Number of cycles decode is idle 658system.cpu0.decode.BlockedCycles 108196913 # Number of cycles decode is blocked 659system.cpu0.decode.RunCycles 58914772 # Number of cycles decode is running 660system.cpu0.decode.UnblockCycles 4966892 # Number of cycles decode is unblocking 661system.cpu0.decode.SquashCycles 2518552 # Number of cycles decode is squashing 662system.cpu0.decode.BranchResolved 3065050 # Number of times decode resolved a branch 663system.cpu0.decode.BranchMispred 334861 # Number of times decode detected a branch misprediction 664system.cpu0.decode.DecodedInsts 154468947 # Number of instructions handled by decode 665system.cpu0.decode.SquashedInsts 3822056 # Number of squashed instructions handled by decode 666system.cpu0.rename.SquashCycles 2518552 # Number of cycles rename is squashing 667system.cpu0.rename.IdleCycles 34338225 # Number of cycles rename is idle 668system.cpu0.rename.BlockCycles 12857218 # Number of cycles rename is blocking 669system.cpu0.rename.serializeStallCycles 83619486 # count of cycles rename stalled for serializing inst 670system.cpu0.rename.RunCycles 55122113 # Number of cycles rename is running 671system.cpu0.rename.UnblockCycles 11856452 # Number of cycles rename is unblocking 672system.cpu0.rename.RenamedInsts 137773765 # Number of instructions processed by rename 673system.cpu0.rename.SquashedInsts 1037168 # Number of squashed instructions processed by rename 674system.cpu0.rename.ROBFullEvents 1494015 # Number of times rename has blocked due to ROB full 675system.cpu0.rename.IQFullEvents 163408 # Number of times rename has blocked due to IQ full 676system.cpu0.rename.LQFullEvents 59807 # Number of times rename has blocked due to LQ full 677system.cpu0.rename.SQFullEvents 7647937 # Number of times rename has blocked due to SQ full 678system.cpu0.rename.RenamedOperands 141868428 # Number of destination operands rename has renamed 679system.cpu0.rename.RenameLookups 635547314 # Number of register rename lookups that rename has made 680system.cpu0.rename.int_rename_lookups 152852010 # Number of integer rename lookups 681system.cpu0.rename.fp_rename_lookups 9442 # Number of floating rename lookups 682system.cpu0.rename.CommittedMaps 130675877 # Number of HB maps that are committed 683system.cpu0.rename.UndoneMaps 11192540 # Number of HB maps that are undone due to squashing 684system.cpu0.rename.serializingInsts 2699923 # count of serializing insts renamed 685system.cpu0.rename.tempSerializingInsts 2556575 # count of temporary serializing insts renamed 686system.cpu0.rename.skidInsts 22590232 # count of insts added to the skid buffer 687system.cpu0.memDep0.insertedLoads 24607184 # Number of loads inserted to the mem dependence unit. 688system.cpu0.memDep0.insertedStores 19088589 # Number of stores inserted to the mem dependence unit. 689system.cpu0.memDep0.conflictingLoads 1696558 # Number of conflicting loads. 690system.cpu0.memDep0.conflictingStores 2229617 # Number of conflicting stores. 691system.cpu0.iq.iqInstsAdded 134839557 # Number of instructions added to the IQ (excludes non-spec) 692system.cpu0.iq.iqNonSpecInstsAdded 1714900 # Number of non-speculative instructions added to the IQ 693system.cpu0.iq.iqInstsIssued 132985122 # Number of instructions issued 694system.cpu0.iq.iqSquashedInstsIssued 452743 # Number of squashed instructions issued 695system.cpu0.iq.iqSquashedInstsExamined 10598058 # Number of squashed instructions iterated over during squash; mainly for profiling 696system.cpu0.iq.iqSquashedOperandsExamined 21682682 # Number of squashed operands that are examined and possibly removed from graph 697system.cpu0.iq.iqSquashedNonSpecRemoved 119247 # Number of squashed non-spec instructions that were removed 698system.cpu0.iq.issued_per_cycle::samples 200312046 # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::mean 0.663890 # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::stdev 0.961819 # Number of insts issued each cycle |
| 686system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 701system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 687system.cpu0.iq.issued_per_cycle::0 71664386 56.07% 56.07% # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::1 23315575 18.24% 74.31% # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::2 22454220 17.57% 91.88% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::3 9273638 7.26% 99.14% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::4 1103003 0.86% 100.00% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::5 52 0.00% 100.00% # Number of insts issued each cycle | 702system.cpu0.iq.issued_per_cycle::0 123495652 61.65% 61.65% # Number of insts issued each cycle 703system.cpu0.iq.issued_per_cycle::1 33655276 16.80% 78.45% # Number of insts issued each cycle 704system.cpu0.iq.issued_per_cycle::2 31282184 15.62% 94.07% # Number of insts issued each cycle 705system.cpu0.iq.issued_per_cycle::3 10750314 5.37% 99.44% # Number of insts issued each cycle 706system.cpu0.iq.issued_per_cycle::4 1128564 0.56% 100.00% # Number of insts issued each cycle 707system.cpu0.iq.issued_per_cycle::5 56 0.00% 100.00% # Number of insts issued each cycle |
| 693system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 708system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 709system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 710system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 711system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 712system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 713system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 699system.cpu0.iq.issued_per_cycle::total 127810874 # Number of insts issued each cycle | 714system.cpu0.iq.issued_per_cycle::total 200312046 # Number of insts issued each cycle |
| 700system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 715system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 701system.cpu0.iq.fu_full::IntAlu 9324082 40.55% 40.55% # attempts to use FU when none available 702system.cpu0.iq.fu_full::IntMult 74 0.00% 40.55% # attempts to use FU when none available 703system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available 704system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available 705system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available 706system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available 707system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available 708system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available 730system.cpu0.iq.fu_full::MemRead 5582954 24.28% 64.83% # attempts to use FU when none available 731system.cpu0.iq.fu_full::MemWrite 8086742 35.17% 100.00% # attempts to use FU when none available | 716system.cpu0.iq.fu_full::IntAlu 10816144 43.95% 43.95% # attempts to use FU when none available 717system.cpu0.iq.fu_full::IntMult 73 0.00% 43.95% # attempts to use FU when none available 718system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.95% # attempts to use FU when none available 719system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.95% # attempts to use FU when none available 720system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.95% # attempts to use FU when none available 721system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.95% # attempts to use FU when none available 722system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.95% # attempts to use FU when none available 723system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.95% # attempts to use FU when none available 724system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.95% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.95% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.95% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.95% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.95% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.95% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.95% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.95% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.95% # attempts to use FU when none available 733system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.95% # attempts to use FU when none available 734system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.95% # attempts to use FU when none available 735system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.95% # attempts to use FU when none available 736system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.95% # attempts to use FU when none available 737system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.95% # attempts to use FU when none available 738system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.95% # attempts to use FU when none available 739system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.95% # attempts to use FU when none available 740system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.95% # attempts to use FU when none available 741system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.95% # attempts to use FU when none available 742system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.95% # attempts to use FU when none available 743system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available 744system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.95% # attempts to use FU when none available 745system.cpu0.iq.fu_full::MemRead 5628152 22.87% 66.82% # attempts to use FU when none available 746system.cpu0.iq.fu_full::MemWrite 8167261 33.18% 100.00% # attempts to use FU when none available |
| 732system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 733system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 734system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued | 747system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 748system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 749system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued |
| 735system.cpu0.iq.FU_type_0::IntAlu 66279940 65.98% 65.98% # Type of FU issued 736system.cpu0.iq.FU_type_0::IntMult 93468 0.09% 66.07% # Type of FU issued 737system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued 738system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.07% # Type of FU issued 739system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.07% # Type of FU issued 740system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.07% # Type of FU issued 741system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.07% # Type of FU issued 742system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.07% # Type of FU issued 743system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.07% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.07% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.07% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.07% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.07% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.07% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.07% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.07% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.07% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.07% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.07% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.07% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.07% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.07% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.07% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.07% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.07% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatMisc 8018 0.01% 66.08% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued 764system.cpu0.iq.FU_type_0::MemRead 18419781 18.34% 84.42% # Type of FU issued 765system.cpu0.iq.FU_type_0::MemWrite 15653721 15.58% 100.00% # Type of FU issued | 750system.cpu0.iq.FU_type_0::IntAlu 89847428 67.56% 67.56% # Type of FU issued 751system.cpu0.iq.FU_type_0::IntMult 110447 0.08% 67.65% # Type of FU issued 752system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued 753system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued 754system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued 755system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued 756system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued 757system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued 758system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 67.65% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued 767system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued 768system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued 769system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued 770system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued 771system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued 772system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued 773system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued 774system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.65% # Type of FU issued 775system.cpu0.iq.FU_type_0::SimdFloatMisc 7864 0.01% 67.65% # Type of FU issued 776system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued 777system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.65% # Type of FU issued 778system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued 779system.cpu0.iq.FU_type_0::MemRead 24369410 18.32% 85.98% # Type of FU issued 780system.cpu0.iq.FU_type_0::MemWrite 18647698 14.02% 100.00% # Type of FU issued |
| 766system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 767system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 781system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 782system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 768system.cpu0.iq.FU_type_0::total 100457201 # Type of FU issued 769system.cpu0.iq.rate 0.762897 # Inst issue rate 770system.cpu0.iq.fu_busy_cnt 22993852 # FU busy when requested 771system.cpu0.iq.fu_busy_rate 0.228892 # FU busy rate (busy events/executed inst) 772system.cpu0.iq.int_inst_queue_reads 352138149 # Number of integer instruction queue reads 773system.cpu0.iq.int_inst_queue_writes 113036952 # Number of integer instruction queue writes 774system.cpu0.iq.int_inst_queue_wakeup_accesses 98428366 # Number of integer instruction queue wakeup accesses 775system.cpu0.iq.fp_inst_queue_reads 32549 # Number of floating instruction queue reads 776system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes 777system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses 778system.cpu0.iq.int_alu_accesses 123427553 # Number of integer alu accesses 779system.cpu0.iq.fp_alu_accesses 21227 # Number of floating point alu accesses 780system.cpu0.iew.lsq.thread0.forwLoads 365954 # Number of loads that had data forwarded from stores | 783system.cpu0.iq.FU_type_0::total 132985122 # Type of FU issued 784system.cpu0.iq.rate 0.649427 # Inst issue rate 785system.cpu0.iq.fu_busy_cnt 24611630 # FU busy when requested 786system.cpu0.iq.fu_busy_rate 0.185071 # FU busy rate (busy events/executed inst) 787system.cpu0.iq.int_inst_queue_reads 491314323 # Number of integer instruction queue reads 788system.cpu0.iq.int_inst_queue_writes 147160457 # Number of integer instruction queue writes 789system.cpu0.iq.int_inst_queue_wakeup_accesses 129454820 # Number of integer instruction queue wakeup accesses 790system.cpu0.iq.fp_inst_queue_reads 32339 # Number of floating instruction queue reads 791system.cpu0.iq.fp_inst_queue_writes 11262 # Number of floating instruction queue writes 792system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses 793system.cpu0.iq.int_alu_accesses 157573424 # Number of integer alu accesses 794system.cpu0.iq.fp_alu_accesses 21055 # Number of floating point alu accesses 795system.cpu0.iew.lsq.thread0.forwLoads 367821 # Number of loads that had data forwarded from stores |
| 781system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 796system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 782system.cpu0.iew.lsq.thread0.squashedLoads 1901526 # Number of loads squashed 783system.cpu0.iew.lsq.thread0.ignoredResponses 2478 # Number of memory responses ignored because the instruction is squashed 784system.cpu0.iew.lsq.thread0.memOrderViolation 19250 # Number of memory ordering violations 785system.cpu0.iew.lsq.thread0.squashedStores 882682 # Number of stores squashed | 797system.cpu0.iew.lsq.thread0.squashedLoads 1916447 # Number of loads squashed 798system.cpu0.iew.lsq.thread0.ignoredResponses 2461 # Number of memory responses ignored because the instruction is squashed 799system.cpu0.iew.lsq.thread0.memOrderViolation 19267 # Number of memory ordering violations 800system.cpu0.iew.lsq.thread0.squashedStores 901714 # Number of stores squashed |
| 786system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 787system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 801system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 802system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 788system.cpu0.iew.lsq.thread0.rescheduledLoads 110051 # Number of loads that were rescheduled 789system.cpu0.iew.lsq.thread0.cacheBlocked 360569 # Number of times an access to memory failed due to the cache being blocked | 803system.cpu0.iew.lsq.thread0.rescheduledLoads 120909 # Number of loads that were rescheduled 804system.cpu0.iew.lsq.thread0.cacheBlocked 362204 # Number of times an access to memory failed due to the cache being blocked |
| 790system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 805system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 791system.cpu0.iew.iewSquashCycles 1038512 # Number of cycles IEW is squashing 792system.cpu0.iew.iewBlockCycles 1592668 # Number of cycles IEW is blocking 793system.cpu0.iew.iewUnblockCycles 210705 # Number of cycles IEW is unblocking 794system.cpu0.iew.iewDispatchedInsts 104136429 # Number of instructions dispatched to IQ | 806system.cpu0.iew.iewSquashCycles 2518552 # Number of cycles IEW is squashing 807system.cpu0.iew.iewBlockCycles 1651189 # Number of cycles IEW is blocking 808system.cpu0.iew.iewUnblockCycles 246744 # Number of cycles IEW is unblocking 809system.cpu0.iew.iewDispatchedInsts 136707359 # Number of instructions dispatched to IQ |
| 795system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 810system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 796system.cpu0.iew.iewDispLoadInsts 18663457 # Number of dispatched load instructions 797system.cpu0.iew.iewDispStoreInsts 16076197 # Number of dispatched store instructions 798system.cpu0.iew.iewDispNonSpecInsts 876152 # Number of dispatched non-speculative instructions 799system.cpu0.iew.iewIQFullEvents 28505 # Number of times the IQ has become full, causing a stall 800system.cpu0.iew.iewLSQFullEvents 158159 # Number of times the LSQ has become full, causing a stall 801system.cpu0.iew.memOrderViolationEvents 19250 # Number of memory order violations 802system.cpu0.iew.predictedTakenIncorrect 253073 # Number of branches that were predicted taken incorrectly 803system.cpu0.iew.predictedNotTakenIncorrect 398879 # Number of branches that were predicted not taken incorrectly 804system.cpu0.iew.branchMispredicts 651952 # Number of branch mispredicts detected at execute 805system.cpu0.iew.iewExecutedInsts 99436169 # Number of executed instructions 806system.cpu0.iew.iewExecLoadInsts 17977378 # Number of load instructions executed 807system.cpu0.iew.iewExecSquashedInsts 955231 # Number of squashed instructions skipped in execute | 811system.cpu0.iew.iewDispLoadInsts 24607184 # Number of dispatched load instructions 812system.cpu0.iew.iewDispStoreInsts 19088589 # Number of dispatched store instructions 813system.cpu0.iew.iewDispNonSpecInsts 876464 # Number of dispatched non-speculative instructions 814system.cpu0.iew.iewIQFullEvents 27795 # Number of times the IQ has become full, causing a stall 815system.cpu0.iew.iewLSQFullEvents 194810 # Number of times the LSQ has become full, causing a stall 816system.cpu0.iew.memOrderViolationEvents 19267 # Number of memory order violations 817system.cpu0.iew.predictedTakenIncorrect 261439 # Number of branches that were predicted taken incorrectly 818system.cpu0.iew.predictedNotTakenIncorrect 400306 # Number of branches that were predicted not taken incorrectly 819system.cpu0.iew.branchMispredicts 661745 # Number of branch mispredicts detected at execute 820system.cpu0.iew.iewExecutedInsts 131953488 # Number of executed instructions 821system.cpu0.iew.iewExecLoadInsts 23926851 # Number of load instructions executed 822system.cpu0.iew.iewExecSquashedInsts 965273 # Number of squashed instructions skipped in execute |
| 808system.cpu0.iew.exec_swp 0 # number of swp insts executed | 823system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 809system.cpu0.iew.exec_nop 152952 # number of nop insts executed 810system.cpu0.iew.exec_refs 33471315 # number of memory reference insts executed 811system.cpu0.iew.exec_branches 16838084 # Number of branches executed 812system.cpu0.iew.exec_stores 15493937 # Number of stores executed 813system.cpu0.iew.exec_rate 0.755143 # Inst execution rate 814system.cpu0.iew.wb_sent 98890175 # cumulative count of insts sent to commit 815system.cpu0.iew.wb_count 98438082 # cumulative count of insts written-back 816system.cpu0.iew.wb_producers 51269761 # num instructions producing a value 817system.cpu0.iew.wb_consumers 84681895 # num instructions consuming a value 818system.cpu0.iew.wb_rate 0.747564 # insts written-back per cycle 819system.cpu0.iew.wb_fanout 0.605439 # average fanout of values written-back 820system.cpu0.commit.commitSquashedInsts 8044326 # The number of squashed insts skipped by commit 821system.cpu0.commit.commitNonSpecStalls 1573050 # The number of times commit has been forced to stall to communicate backwards 822system.cpu0.commit.branchMispredicts 595336 # The number of times a branch was mispredicted 823system.cpu0.commit.committed_per_cycle::samples 126126769 # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::mean 0.753686 # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::stdev 1.472161 # Number of insts commited each cycle | 824system.cpu0.iew.exec_nop 152902 # number of nop insts executed 825system.cpu0.iew.exec_refs 42414312 # number of memory reference insts executed 826system.cpu0.iew.exec_branches 25613561 # Number of branches executed 827system.cpu0.iew.exec_stores 18487461 # Number of stores executed 828system.cpu0.iew.exec_rate 0.644389 # Inst execution rate 829system.cpu0.iew.wb_sent 131398393 # cumulative count of insts sent to commit 830system.cpu0.iew.wb_count 129464537 # cumulative count of insts written-back 831system.cpu0.iew.wb_producers 66052971 # num instructions producing a value 832system.cpu0.iew.wb_consumers 106772912 # num instructions consuming a value 833system.cpu0.iew.wb_rate 0.632234 # insts written-back per cycle 834system.cpu0.iew.wb_fanout 0.618630 # average fanout of values written-back 835system.cpu0.commit.commitSquashedInsts 9569777 # The number of squashed insts skipped by commit 836system.cpu0.commit.commitNonSpecStalls 1595653 # The number of times commit has been forced to stall to communicate backwards 837system.cpu0.commit.branchMispredicts 604480 # The number of times a branch was mispredicted 838system.cpu0.commit.committed_per_cycle::samples 197147849 # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::mean 0.639512 # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::stdev 1.336739 # Number of insts commited each cycle |
| 826system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 841system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 827system.cpu0.commit.committed_per_cycle::0 81783872 64.84% 64.84% # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::1 24707932 19.59% 84.43% # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::2 8259395 6.55% 90.98% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::3 3211630 2.55% 93.53% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::4 3438301 2.73% 96.25% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::5 1493917 1.18% 97.44% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::6 1163537 0.92% 98.36% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::7 551177 0.44% 98.80% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::8 1517008 1.20% 100.00% # Number of insts commited each cycle | 842system.cpu0.commit.committed_per_cycle::0 136598241 69.29% 69.29% # Number of insts commited each cycle 843system.cpu0.commit.committed_per_cycle::1 33559109 17.02% 86.31% # Number of insts commited each cycle 844system.cpu0.commit.committed_per_cycle::2 12649949 6.42% 92.73% # Number of insts commited each cycle 845system.cpu0.commit.committed_per_cycle::3 3238672 1.64% 94.37% # Number of insts commited each cycle 846system.cpu0.commit.committed_per_cycle::4 4912875 2.49% 96.86% # Number of insts commited each cycle 847system.cpu0.commit.committed_per_cycle::5 2898818 1.47% 98.33% # Number of insts commited each cycle 848system.cpu0.commit.committed_per_cycle::6 1203082 0.61% 98.94% # Number of insts commited each cycle 849system.cpu0.commit.committed_per_cycle::7 557487 0.28% 99.22% # Number of insts commited each cycle 850system.cpu0.commit.committed_per_cycle::8 1529616 0.78% 100.00% # Number of insts commited each cycle |
| 836system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 851system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 852system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 853system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 839system.cpu0.commit.committed_per_cycle::total 126126769 # Number of insts commited each cycle 840system.cpu0.commit.committedInsts 79016795 # Number of instructions committed 841system.cpu0.commit.committedOps 95059926 # Number of ops (including micro ops) committed | 854system.cpu0.commit.committed_per_cycle::total 197147849 # Number of insts commited each cycle 855system.cpu0.commit.committedInsts 104125280 # Number of instructions committed 856system.cpu0.commit.committedOps 126078442 # Number of ops (including micro ops) committed |
| 842system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 857system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 843system.cpu0.commit.refs 31955445 # Number of memory references committed 844system.cpu0.commit.loads 16761930 # Number of loads committed 845system.cpu0.commit.membars 647782 # Number of memory barriers committed 846system.cpu0.commit.branches 16235143 # Number of branches committed | 858system.cpu0.commit.refs 40877611 # Number of memory references committed 859system.cpu0.commit.loads 22690736 # Number of loads committed 860system.cpu0.commit.membars 648887 # Number of memory barriers committed 861system.cpu0.commit.branches 25008531 # Number of branches committed |
| 847system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. | 862system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. |
| 848system.cpu0.commit.int_insts 81982870 # Number of committed integer instructions. 849system.cpu0.commit.function_calls 1931434 # Number of function calls committed. | 863system.cpu0.commit.int_insts 110051272 # Number of committed integer instructions. 864system.cpu0.commit.function_calls 4840996 # Number of function calls committed. |
| 850system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 865system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 851system.cpu0.commit.op_class_0::IntAlu 63005341 66.28% 66.28% # Class of committed instruction 852system.cpu0.commit.op_class_0::IntMult 91123 0.10% 66.38% # Class of committed instruction 853system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 854system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 855system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 856system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 857system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 858system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 859system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatMisc 8017 0.01% 66.38% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction 880system.cpu0.commit.op_class_0::MemRead 16761930 17.63% 84.02% # Class of committed instruction 881system.cpu0.commit.op_class_0::MemWrite 15193515 15.98% 100.00% # Class of committed instruction | 866system.cpu0.commit.op_class_0::IntAlu 85084925 67.49% 67.49% # Class of committed instruction 867system.cpu0.commit.op_class_0::IntMult 108043 0.09% 67.57% # Class of committed instruction 868system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction 869system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction 870system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction 871system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction 872system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction 873system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction 874system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction 883system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction 884system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction 885system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction 886system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction 887system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction 888system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction 889system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction 890system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction 891system.cpu0.commit.op_class_0::SimdFloatMisc 7863 0.01% 67.58% # Class of committed instruction 892system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction 893system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction 894system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction 895system.cpu0.commit.op_class_0::MemRead 22690736 18.00% 85.57% # Class of committed instruction 896system.cpu0.commit.op_class_0::MemWrite 18186875 14.43% 100.00% # Class of committed instruction |
| 882system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 883system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 897system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 898system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 884system.cpu0.commit.op_class_0::total 95059926 # Class of committed instruction 885system.cpu0.commit.bw_lim_events 1517008 # number cycles where commit BW limit reached 886system.cpu0.rob.rob_reads 223519030 # The number of ROB reads 887system.cpu0.rob.rob_writes 207883288 # The number of ROB writes 888system.cpu0.timesIdled 136700 # Number of times that the entire CPU went into an idle state and unscheduled itself 889system.cpu0.idleCycles 3867673 # Total number of cycles that the CPU has spent unscheduled due to idling 890system.cpu0.quiesceCycles 5520543918 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 891system.cpu0.committedInsts 78894743 # Number of Instructions Simulated 892system.cpu0.committedOps 94937874 # Number of Ops (including micro ops) Simulated 893system.cpu0.cpi 1.669041 # CPI: Cycles Per Instruction 894system.cpu0.cpi_total 1.669041 # CPI: Total CPI of All Threads 895system.cpu0.ipc 0.599147 # IPC: Instructions Per Cycle 896system.cpu0.ipc_total 0.599147 # IPC: Total IPC of All Threads 897system.cpu0.int_regfile_reads 110427579 # number of integer regfile reads 898system.cpu0.int_regfile_writes 59611828 # number of integer regfile writes 899system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads | 899system.cpu0.commit.op_class_0::total 126078442 # Class of committed instruction 900system.cpu0.commit.bw_lim_events 1529616 # number cycles where commit BW limit reached 901system.cpu0.rob.rob_reads 307952651 # The number of ROB reads 902system.cpu0.rob.rob_writes 274451297 # The number of ROB writes 903system.cpu0.timesIdled 137106 # Number of times that the entire CPU went into an idle state and unscheduled itself 904system.cpu0.idleCycles 4460980 # Total number of cycles that the CPU has spent unscheduled due to idling 905system.cpu0.quiesceCycles 5448417066 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 906system.cpu0.committedInsts 104003228 # Number of Instructions Simulated 907system.cpu0.committedOps 125956390 # Number of Ops (including micro ops) Simulated 908system.cpu0.cpi 1.968910 # CPI: Cycles Per Instruction 909system.cpu0.cpi_total 1.968910 # CPI: Total CPI of All Threads 910system.cpu0.ipc 0.507895 # IPC: Instructions Per Cycle 911system.cpu0.ipc_total 0.507895 # IPC: Total IPC of All Threads 912system.cpu0.int_regfile_reads 142940096 # number of integer regfile reads 913system.cpu0.int_regfile_writes 81795281 # number of integer regfile writes 914system.cpu0.fp_regfile_reads 8203 # number of floating regfile reads |
| 900system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes | 915system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes |
| 901system.cpu0.cc_regfile_reads 350340790 # number of cc regfile reads 902system.cpu0.cc_regfile_writes 41062621 # number of cc regfile writes 903system.cpu0.misc_regfile_reads 252371624 # number of misc regfile reads 904system.cpu0.misc_regfile_writes 1225237 # number of misc regfile writes 905system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 906system.cpu0.dcache.tags.replacements 711089 # number of replacements 907system.cpu0.dcache.tags.tagsinuse 494.347987 # Cycle average of tags in use 908system.cpu0.dcache.tags.total_refs 28802334 # Total number of references to valid blocks. 909system.cpu0.dcache.tags.sampled_refs 711601 # Sample count of references to valid blocks. 910system.cpu0.dcache.tags.avg_refs 40.475398 # Average number of references to valid blocks. 911system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. 912system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.347987 # Average occupied blocks per requestor 913system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965523 # Average percentage of cache occupancy 914system.cpu0.dcache.tags.occ_percent::total 0.965523 # Average percentage of cache occupancy | 916system.cpu0.cc_regfile_reads 465685863 # number of cc regfile reads 917system.cpu0.cc_regfile_writes 49834738 # number of cc regfile writes 918system.cpu0.misc_regfile_reads 394201906 # number of misc regfile reads 919system.cpu0.misc_regfile_writes 1226279 # number of misc regfile writes 920system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 921system.cpu0.dcache.tags.replacements 711042 # number of replacements 922system.cpu0.dcache.tags.tagsinuse 497.782039 # Cycle average of tags in use 923system.cpu0.dcache.tags.total_refs 37710898 # Total number of references to valid blocks. 924system.cpu0.dcache.tags.sampled_refs 711554 # Sample count of references to valid blocks. 925system.cpu0.dcache.tags.avg_refs 52.997943 # Average number of references to valid blocks. 926system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. 927system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.782039 # Average occupied blocks per requestor 928system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972231 # Average percentage of cache occupancy 929system.cpu0.dcache.tags.occ_percent::total 0.972231 # Average percentage of cache occupancy |
| 915system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 930system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 916system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 917system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 918system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id | 931system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 932system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 933system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id |
| 919system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 934system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 920system.cpu0.dcache.tags.tag_accesses 63463455 # Number of tag accesses 921system.cpu0.dcache.tags.data_accesses 63463455 # Number of data accesses 922system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 923system.cpu0.dcache.ReadReq_hits::cpu0.data 15558905 # number of ReadReq hits 924system.cpu0.dcache.ReadReq_hits::total 15558905 # number of ReadReq hits 925system.cpu0.dcache.WriteReq_hits::cpu0.data 12019658 # number of WriteReq hits 926system.cpu0.dcache.WriteReq_hits::total 12019658 # number of WriteReq hits 927system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308619 # number of SoftPFReq hits 928system.cpu0.dcache.SoftPFReq_hits::total 308619 # number of SoftPFReq hits 929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363044 # number of LoadLockedReq hits 930system.cpu0.dcache.LoadLockedReq_hits::total 363044 # number of LoadLockedReq hits 931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361281 # number of StoreCondReq hits 932system.cpu0.dcache.StoreCondReq_hits::total 361281 # number of StoreCondReq hits 933system.cpu0.dcache.demand_hits::cpu0.data 27578563 # number of demand (read+write) hits 934system.cpu0.dcache.demand_hits::total 27578563 # number of demand (read+write) hits 935system.cpu0.dcache.overall_hits::cpu0.data 27887182 # number of overall hits 936system.cpu0.dcache.overall_hits::total 27887182 # number of overall hits 937system.cpu0.dcache.ReadReq_misses::cpu0.data 648058 # number of ReadReq misses 938system.cpu0.dcache.ReadReq_misses::total 648058 # number of ReadReq misses 939system.cpu0.dcache.WriteReq_misses::cpu0.data 1895809 # number of WriteReq misses 940system.cpu0.dcache.WriteReq_misses::total 1895809 # number of WriteReq misses 941system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147818 # number of SoftPFReq misses 942system.cpu0.dcache.SoftPFReq_misses::total 147818 # number of SoftPFReq misses 943system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25317 # number of LoadLockedReq misses 944system.cpu0.dcache.LoadLockedReq_misses::total 25317 # number of LoadLockedReq misses 945system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20174 # number of StoreCondReq misses 946system.cpu0.dcache.StoreCondReq_misses::total 20174 # number of StoreCondReq misses 947system.cpu0.dcache.demand_misses::cpu0.data 2543867 # number of demand (read+write) misses 948system.cpu0.dcache.demand_misses::total 2543867 # number of demand (read+write) misses 949system.cpu0.dcache.overall_misses::cpu0.data 2691685 # number of overall misses 950system.cpu0.dcache.overall_misses::total 2691685 # number of overall misses 951system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8928091500 # number of ReadReq miss cycles 952system.cpu0.dcache.ReadReq_miss_latency::total 8928091500 # number of ReadReq miss cycles 953system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29690163364 # number of WriteReq miss cycles 954system.cpu0.dcache.WriteReq_miss_latency::total 29690163364 # number of WriteReq miss cycles 955system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 404195500 # number of LoadLockedReq miss cycles 956system.cpu0.dcache.LoadLockedReq_miss_latency::total 404195500 # number of LoadLockedReq miss cycles 957system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 475433000 # number of StoreCondReq miss cycles 958system.cpu0.dcache.StoreCondReq_miss_latency::total 475433000 # number of StoreCondReq miss cycles 959system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 570500 # number of StoreCondFailReq miss cycles 960system.cpu0.dcache.StoreCondFailReq_miss_latency::total 570500 # number of StoreCondFailReq miss cycles 961system.cpu0.dcache.demand_miss_latency::cpu0.data 38618254864 # number of demand (read+write) miss cycles 962system.cpu0.dcache.demand_miss_latency::total 38618254864 # number of demand (read+write) miss cycles 963system.cpu0.dcache.overall_miss_latency::cpu0.data 38618254864 # number of overall miss cycles 964system.cpu0.dcache.overall_miss_latency::total 38618254864 # number of overall miss cycles 965system.cpu0.dcache.ReadReq_accesses::cpu0.data 16206963 # number of ReadReq accesses(hits+misses) 966system.cpu0.dcache.ReadReq_accesses::total 16206963 # number of ReadReq accesses(hits+misses) 967system.cpu0.dcache.WriteReq_accesses::cpu0.data 13915467 # number of WriteReq accesses(hits+misses) 968system.cpu0.dcache.WriteReq_accesses::total 13915467 # number of WriteReq accesses(hits+misses) 969system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456437 # number of SoftPFReq accesses(hits+misses) 970system.cpu0.dcache.SoftPFReq_accesses::total 456437 # number of SoftPFReq accesses(hits+misses) 971system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388361 # number of LoadLockedReq accesses(hits+misses) 972system.cpu0.dcache.LoadLockedReq_accesses::total 388361 # number of LoadLockedReq accesses(hits+misses) 973system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381455 # number of StoreCondReq accesses(hits+misses) 974system.cpu0.dcache.StoreCondReq_accesses::total 381455 # number of StoreCondReq accesses(hits+misses) 975system.cpu0.dcache.demand_accesses::cpu0.data 30122430 # number of demand (read+write) accesses 976system.cpu0.dcache.demand_accesses::total 30122430 # number of demand (read+write) accesses 977system.cpu0.dcache.overall_accesses::cpu0.data 30578867 # number of overall (read+write) accesses 978system.cpu0.dcache.overall_accesses::total 30578867 # number of overall (read+write) accesses 979system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039986 # miss rate for ReadReq accesses 980system.cpu0.dcache.ReadReq_miss_rate::total 0.039986 # miss rate for ReadReq accesses 981system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136238 # miss rate for WriteReq accesses 982system.cpu0.dcache.WriteReq_miss_rate::total 0.136238 # miss rate for WriteReq accesses 983system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323852 # miss rate for SoftPFReq accesses 984system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323852 # miss rate for SoftPFReq accesses 985system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065189 # miss rate for LoadLockedReq accesses 986system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065189 # miss rate for LoadLockedReq accesses 987system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052887 # miss rate for StoreCondReq accesses 988system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052887 # miss rate for StoreCondReq accesses 989system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084451 # miss rate for demand accesses 990system.cpu0.dcache.demand_miss_rate::total 0.084451 # miss rate for demand accesses 991system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088024 # miss rate for overall accesses 992system.cpu0.dcache.overall_miss_rate::total 0.088024 # miss rate for overall accesses 993system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883 # average ReadReq miss latency 994system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883 # average ReadReq miss latency 995system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522 # average WriteReq miss latency 996system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522 # average WriteReq miss latency 997system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994 # average LoadLockedReq miss latency 998system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994 # average LoadLockedReq miss latency 999system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402 # average StoreCondReq miss latency 1000system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402 # average StoreCondReq miss latency | 935system.cpu0.dcache.tags.tag_accesses 81278285 # Number of tag accesses 936system.cpu0.dcache.tags.data_accesses 81278285 # Number of data accesses 937system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 938system.cpu0.dcache.ReadReq_hits::cpu0.data 21483760 # number of ReadReq hits 939system.cpu0.dcache.ReadReq_hits::total 21483760 # number of ReadReq hits 940system.cpu0.dcache.WriteReq_hits::cpu0.data 15003255 # number of WriteReq hits 941system.cpu0.dcache.WriteReq_hits::total 15003255 # number of WriteReq hits 942system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307803 # number of SoftPFReq hits 943system.cpu0.dcache.SoftPFReq_hits::total 307803 # number of SoftPFReq hits 944system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363087 # number of LoadLockedReq hits 945system.cpu0.dcache.LoadLockedReq_hits::total 363087 # number of LoadLockedReq hits 946system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361616 # number of StoreCondReq hits 947system.cpu0.dcache.StoreCondReq_hits::total 361616 # number of StoreCondReq hits 948system.cpu0.dcache.demand_hits::cpu0.data 36487015 # number of demand (read+write) hits 949system.cpu0.dcache.demand_hits::total 36487015 # number of demand (read+write) hits 950system.cpu0.dcache.overall_hits::cpu0.data 36794818 # number of overall hits 951system.cpu0.dcache.overall_hits::total 36794818 # number of overall hits 952system.cpu0.dcache.ReadReq_misses::cpu0.data 647587 # number of ReadReq misses 953system.cpu0.dcache.ReadReq_misses::total 647587 # number of ReadReq misses 954system.cpu0.dcache.WriteReq_misses::cpu0.data 1894796 # number of WriteReq misses 955system.cpu0.dcache.WriteReq_misses::total 1894796 # number of WriteReq misses 956system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148778 # number of SoftPFReq misses 957system.cpu0.dcache.SoftPFReq_misses::total 148778 # number of SoftPFReq misses 958system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25560 # number of LoadLockedReq misses 959system.cpu0.dcache.LoadLockedReq_misses::total 25560 # number of LoadLockedReq misses 960system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20165 # number of StoreCondReq misses 961system.cpu0.dcache.StoreCondReq_misses::total 20165 # number of StoreCondReq misses 962system.cpu0.dcache.demand_misses::cpu0.data 2542383 # number of demand (read+write) misses 963system.cpu0.dcache.demand_misses::total 2542383 # number of demand (read+write) misses 964system.cpu0.dcache.overall_misses::cpu0.data 2691161 # number of overall misses 965system.cpu0.dcache.overall_misses::total 2691161 # number of overall misses 966system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9361035000 # number of ReadReq miss cycles 967system.cpu0.dcache.ReadReq_miss_latency::total 9361035000 # number of ReadReq miss cycles 968system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33017805879 # number of WriteReq miss cycles 969system.cpu0.dcache.WriteReq_miss_latency::total 33017805879 # number of WriteReq miss cycles 970system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412521000 # number of LoadLockedReq miss cycles 971system.cpu0.dcache.LoadLockedReq_miss_latency::total 412521000 # number of LoadLockedReq miss cycles 972system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 476921000 # number of StoreCondReq miss cycles 973system.cpu0.dcache.StoreCondReq_miss_latency::total 476921000 # number of StoreCondReq miss cycles 974system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 443000 # number of StoreCondFailReq miss cycles 975system.cpu0.dcache.StoreCondFailReq_miss_latency::total 443000 # number of StoreCondFailReq miss cycles 976system.cpu0.dcache.demand_miss_latency::cpu0.data 42378840879 # number of demand (read+write) miss cycles 977system.cpu0.dcache.demand_miss_latency::total 42378840879 # number of demand (read+write) miss cycles 978system.cpu0.dcache.overall_miss_latency::cpu0.data 42378840879 # number of overall miss cycles 979system.cpu0.dcache.overall_miss_latency::total 42378840879 # number of overall miss cycles 980system.cpu0.dcache.ReadReq_accesses::cpu0.data 22131347 # number of ReadReq accesses(hits+misses) 981system.cpu0.dcache.ReadReq_accesses::total 22131347 # number of ReadReq accesses(hits+misses) 982system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898051 # number of WriteReq accesses(hits+misses) 983system.cpu0.dcache.WriteReq_accesses::total 16898051 # number of WriteReq accesses(hits+misses) 984system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456581 # number of SoftPFReq accesses(hits+misses) 985system.cpu0.dcache.SoftPFReq_accesses::total 456581 # number of SoftPFReq accesses(hits+misses) 986system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388647 # number of LoadLockedReq accesses(hits+misses) 987system.cpu0.dcache.LoadLockedReq_accesses::total 388647 # number of LoadLockedReq accesses(hits+misses) 988system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381781 # number of StoreCondReq accesses(hits+misses) 989system.cpu0.dcache.StoreCondReq_accesses::total 381781 # number of StoreCondReq accesses(hits+misses) 990system.cpu0.dcache.demand_accesses::cpu0.data 39029398 # number of demand (read+write) accesses 991system.cpu0.dcache.demand_accesses::total 39029398 # number of demand (read+write) accesses 992system.cpu0.dcache.overall_accesses::cpu0.data 39485979 # number of overall (read+write) accesses 993system.cpu0.dcache.overall_accesses::total 39485979 # number of overall (read+write) accesses 994system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029261 # miss rate for ReadReq accesses 995system.cpu0.dcache.ReadReq_miss_rate::total 0.029261 # miss rate for ReadReq accesses 996system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112131 # miss rate for WriteReq accesses 997system.cpu0.dcache.WriteReq_miss_rate::total 0.112131 # miss rate for WriteReq accesses 998system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325852 # miss rate for SoftPFReq accesses 999system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325852 # miss rate for SoftPFReq accesses 1000system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065767 # miss rate for LoadLockedReq accesses 1001system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065767 # miss rate for LoadLockedReq accesses 1002system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052818 # miss rate for StoreCondReq accesses 1003system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052818 # miss rate for StoreCondReq accesses 1004system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065140 # miss rate for demand accesses 1005system.cpu0.dcache.demand_miss_rate::total 0.065140 # miss rate for demand accesses 1006system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068155 # miss rate for overall accesses 1007system.cpu0.dcache.overall_miss_rate::total 0.068155 # miss rate for overall accesses 1008system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14455.254661 # average ReadReq miss latency 1009system.cpu0.dcache.ReadReq_avg_miss_latency::total 14455.254661 # average ReadReq miss latency 1010system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17425.520150 # average WriteReq miss latency 1011system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.520150 # average WriteReq miss latency 1012system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16139.319249 # average LoadLockedReq miss latency 1013system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16139.319249 # average LoadLockedReq miss latency 1014system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23650.929829 # average StoreCondReq miss latency 1015system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23650.929829 # average StoreCondReq miss latency |
| 1001system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1002system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1016system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1017system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1003system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286 # average overall miss latency 1004system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286 # average overall miss latency 1005system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547 # average overall miss latency 1006system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547 # average overall miss latency 1007system.cpu0.dcache.blocked_cycles::no_mshrs 1034 # number of cycles access was blocked 1008system.cpu0.dcache.blocked_cycles::no_targets 4271446 # number of cycles access was blocked 1009system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked 1010system.cpu0.dcache.blocked::no_targets 202383 # number of cycles access was blocked 1011system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.541667 # average number of cycles each access was blocked 1012system.cpu0.dcache.avg_blocked_cycles::no_targets 21.105755 # average number of cycles each access was blocked 1013system.cpu0.dcache.writebacks::writebacks 711089 # number of writebacks 1014system.cpu0.dcache.writebacks::total 711089 # number of writebacks 1015system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260039 # number of ReadReq MSHR hits 1016system.cpu0.dcache.ReadReq_mshr_hits::total 260039 # number of ReadReq MSHR hits 1017system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570278 # number of WriteReq MSHR hits 1018system.cpu0.dcache.WriteReq_mshr_hits::total 1570278 # number of WriteReq MSHR hits 1019system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18696 # number of LoadLockedReq MSHR hits 1020system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18696 # number of LoadLockedReq MSHR hits 1021system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830317 # number of demand (read+write) MSHR hits 1022system.cpu0.dcache.demand_mshr_hits::total 1830317 # number of demand (read+write) MSHR hits 1023system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830317 # number of overall MSHR hits 1024system.cpu0.dcache.overall_mshr_hits::total 1830317 # number of overall MSHR hits 1025system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388019 # number of ReadReq MSHR misses 1026system.cpu0.dcache.ReadReq_mshr_misses::total 388019 # number of ReadReq MSHR misses 1027system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325531 # number of WriteReq MSHR misses 1028system.cpu0.dcache.WriteReq_mshr_misses::total 325531 # number of WriteReq MSHR misses 1029system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101607 # number of SoftPFReq MSHR misses 1030system.cpu0.dcache.SoftPFReq_mshr_misses::total 101607 # number of SoftPFReq MSHR misses 1031system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6621 # number of LoadLockedReq MSHR misses 1032system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6621 # number of LoadLockedReq MSHR misses 1033system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20174 # number of StoreCondReq MSHR misses 1034system.cpu0.dcache.StoreCondReq_mshr_misses::total 20174 # number of StoreCondReq MSHR misses 1035system.cpu0.dcache.demand_mshr_misses::cpu0.data 713550 # number of demand (read+write) MSHR misses 1036system.cpu0.dcache.demand_mshr_misses::total 713550 # number of demand (read+write) MSHR misses 1037system.cpu0.dcache.overall_mshr_misses::cpu0.data 815157 # number of overall MSHR misses 1038system.cpu0.dcache.overall_mshr_misses::total 815157 # number of overall MSHR misses 1039system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable 1040system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20336 # number of ReadReq MSHR uncacheable 1041system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable 1042system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable 1043system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses 1044system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39368 # number of overall MSHR uncacheable misses 1045system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4833813000 # number of ReadReq MSHR miss cycles 1046system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4833813000 # number of ReadReq MSHR miss cycles 1047system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5968230399 # number of WriteReq MSHR miss cycles 1048system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5968230399 # number of WriteReq MSHR miss cycles 1049system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1672759500 # number of SoftPFReq MSHR miss cycles 1050system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672759500 # number of SoftPFReq MSHR miss cycles 1051system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104692000 # number of LoadLockedReq MSHR miss cycles 1052system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104692000 # number of LoadLockedReq MSHR miss cycles 1053system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 455274000 # number of StoreCondReq MSHR miss cycles 1054system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 455274000 # number of StoreCondReq MSHR miss cycles 1055system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 555500 # number of StoreCondFailReq MSHR miss cycles 1056system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 555500 # number of StoreCondFailReq MSHR miss cycles 1057system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10802043399 # number of demand (read+write) MSHR miss cycles 1058system.cpu0.dcache.demand_mshr_miss_latency::total 10802043399 # number of demand (read+write) MSHR miss cycles 1059system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12474802899 # number of overall MSHR miss cycles 1060system.cpu0.dcache.overall_mshr_miss_latency::total 12474802899 # number of overall MSHR miss cycles 1061system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534406000 # number of ReadReq MSHR uncacheable cycles 1062system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534406000 # number of ReadReq MSHR uncacheable cycles 1063system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534406000 # number of overall MSHR uncacheable cycles 1064system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534406000 # number of overall MSHR uncacheable cycles 1065system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023941 # mshr miss rate for ReadReq accesses 1066system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023941 # mshr miss rate for ReadReq accesses 1067system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023393 # mshr miss rate for WriteReq accesses 1068system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023393 # mshr miss rate for WriteReq accesses 1069system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222609 # mshr miss rate for SoftPFReq accesses 1070system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222609 # mshr miss rate for SoftPFReq accesses 1071system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017049 # mshr miss rate for LoadLockedReq accesses 1072system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017049 # mshr miss rate for LoadLockedReq accesses 1073system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052887 # mshr miss rate for StoreCondReq accesses 1074system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052887 # mshr miss rate for StoreCondReq accesses 1075system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023688 # mshr miss rate for demand accesses 1076system.cpu0.dcache.demand_mshr_miss_rate::total 0.023688 # mshr miss rate for demand accesses 1077system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026658 # mshr miss rate for overall accesses 1078system.cpu0.dcache.overall_mshr_miss_rate::total 0.026658 # mshr miss rate for overall accesses 1079system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887 # average ReadReq mshr miss latency 1080system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887 # average ReadReq mshr miss latency 1081system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184 # average WriteReq mshr miss latency 1082system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184 # average WriteReq mshr miss latency 1083system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043 # average SoftPFReq mshr miss latency 1084system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043 # average SoftPFReq mshr miss latency 1085system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974 # average LoadLockedReq mshr miss latency 1086system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974 # average LoadLockedReq mshr miss latency 1087system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934 # average StoreCondReq mshr miss latency 1088system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934 # average StoreCondReq mshr miss latency | 1018system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16668.944403 # average overall miss latency 1019system.cpu0.dcache.demand_avg_miss_latency::total 16668.944403 # average overall miss latency 1020system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15747.419377 # average overall miss latency 1021system.cpu0.dcache.overall_avg_miss_latency::total 15747.419377 # average overall miss latency 1022system.cpu0.dcache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked 1023system.cpu0.dcache.blocked_cycles::no_targets 4996394 # number of cycles access was blocked 1024system.cpu0.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 1025system.cpu0.dcache.blocked::no_targets 202489 # number of cycles access was blocked 1026system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked 1027system.cpu0.dcache.avg_blocked_cycles::no_targets 24.674891 # average number of cycles each access was blocked 1028system.cpu0.dcache.writebacks::writebacks 711042 # number of writebacks 1029system.cpu0.dcache.writebacks::total 711042 # number of writebacks 1030system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260652 # number of ReadReq MSHR hits 1031system.cpu0.dcache.ReadReq_mshr_hits::total 260652 # number of ReadReq MSHR hits 1032system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569869 # number of WriteReq MSHR hits 1033system.cpu0.dcache.WriteReq_mshr_hits::total 1569869 # number of WriteReq MSHR hits 1034system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18798 # number of LoadLockedReq MSHR hits 1035system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18798 # number of LoadLockedReq MSHR hits 1036system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830521 # number of demand (read+write) MSHR hits 1037system.cpu0.dcache.demand_mshr_hits::total 1830521 # number of demand (read+write) MSHR hits 1038system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830521 # number of overall MSHR hits 1039system.cpu0.dcache.overall_mshr_hits::total 1830521 # number of overall MSHR hits 1040system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386935 # number of ReadReq MSHR misses 1041system.cpu0.dcache.ReadReq_mshr_misses::total 386935 # number of ReadReq MSHR misses 1042system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324927 # number of WriteReq MSHR misses 1043system.cpu0.dcache.WriteReq_mshr_misses::total 324927 # number of WriteReq MSHR misses 1044system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102518 # number of SoftPFReq MSHR misses 1045system.cpu0.dcache.SoftPFReq_mshr_misses::total 102518 # number of SoftPFReq MSHR misses 1046system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6762 # number of LoadLockedReq MSHR misses 1047system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6762 # number of LoadLockedReq MSHR misses 1048system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20165 # number of StoreCondReq MSHR misses 1049system.cpu0.dcache.StoreCondReq_mshr_misses::total 20165 # number of StoreCondReq MSHR misses 1050system.cpu0.dcache.demand_mshr_misses::cpu0.data 711862 # number of demand (read+write) MSHR misses 1051system.cpu0.dcache.demand_mshr_misses::total 711862 # number of demand (read+write) MSHR misses 1052system.cpu0.dcache.overall_mshr_misses::cpu0.data 814380 # number of overall MSHR misses 1053system.cpu0.dcache.overall_mshr_misses::total 814380 # number of overall MSHR misses 1054system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable 1055system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable 1056system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable 1057system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28457 # number of WriteReq MSHR uncacheable 1058system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses 1059system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60239 # number of overall MSHR uncacheable misses 1060system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5003581000 # number of ReadReq MSHR miss cycles 1061system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5003581000 # number of ReadReq MSHR miss cycles 1062system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626488404 # number of WriteReq MSHR miss cycles 1063system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626488404 # number of WriteReq MSHR miss cycles 1064system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1706140000 # number of SoftPFReq MSHR miss cycles 1065system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1706140000 # number of SoftPFReq MSHR miss cycles 1066system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107183000 # number of LoadLockedReq MSHR miss cycles 1067system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107183000 # number of LoadLockedReq MSHR miss cycles 1068system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 456767000 # number of StoreCondReq MSHR miss cycles 1069system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 456767000 # number of StoreCondReq MSHR miss cycles 1070system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 432000 # number of StoreCondFailReq MSHR miss cycles 1071system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 432000 # number of StoreCondFailReq MSHR miss cycles 1072system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11630069404 # number of demand (read+write) MSHR miss cycles 1073system.cpu0.dcache.demand_mshr_miss_latency::total 11630069404 # number of demand (read+write) MSHR miss cycles 1074system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13336209404 # number of overall MSHR miss cycles 1075system.cpu0.dcache.overall_mshr_miss_latency::total 13336209404 # number of overall MSHR miss cycles 1076system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6624172500 # number of ReadReq MSHR uncacheable cycles 1077system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6624172500 # number of ReadReq MSHR uncacheable cycles 1078system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6624172500 # number of overall MSHR uncacheable cycles 1079system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6624172500 # number of overall MSHR uncacheable cycles 1080system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017484 # mshr miss rate for ReadReq accesses 1081system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017484 # mshr miss rate for ReadReq accesses 1082system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019229 # mshr miss rate for WriteReq accesses 1083system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019229 # mshr miss rate for WriteReq accesses 1084system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224534 # mshr miss rate for SoftPFReq accesses 1085system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224534 # mshr miss rate for SoftPFReq accesses 1086system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017399 # mshr miss rate for LoadLockedReq accesses 1087system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017399 # mshr miss rate for LoadLockedReq accesses 1088system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052818 # mshr miss rate for StoreCondReq accesses 1089system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052818 # mshr miss rate for StoreCondReq accesses 1090system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for demand accesses 1091system.cpu0.dcache.demand_mshr_miss_rate::total 0.018239 # mshr miss rate for demand accesses 1092system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020625 # mshr miss rate for overall accesses 1093system.cpu0.dcache.overall_mshr_miss_rate::total 0.020625 # mshr miss rate for overall accesses 1094system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12931.321798 # average ReadReq mshr miss latency 1095system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12931.321798 # average ReadReq mshr miss latency 1096system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20393.775845 # average WriteReq mshr miss latency 1097system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20393.775845 # average WriteReq mshr miss latency 1098system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16642.345734 # average SoftPFReq mshr miss latency 1099system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16642.345734 # average SoftPFReq mshr miss latency 1100system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15850.783792 # average LoadLockedReq mshr miss latency 1101system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15850.783792 # average LoadLockedReq mshr miss latency 1102system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22651.475329 # average StoreCondReq mshr miss latency 1103system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22651.475329 # average StoreCondReq mshr miss latency |
| 1089system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1090system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1104system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1105system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1091system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366 # average overall mshr miss latency 1092system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366 # average overall mshr miss latency 1093system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577 # average overall mshr miss latency 1094system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577 # average overall mshr miss latency 1095system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235 # average ReadReq mshr uncacheable latency 1096system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235 # average ReadReq mshr uncacheable latency 1097system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904 # average overall mshr uncacheable latency 1098system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904 # average overall mshr uncacheable latency 1099system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1100system.cpu0.icache.tags.replacements 1254577 # number of replacements 1101system.cpu0.icache.tags.tagsinuse 511.762789 # Cycle average of tags in use 1102system.cpu0.icache.tags.total_refs 36189840 # Total number of references to valid blocks. 1103system.cpu0.icache.tags.sampled_refs 1255088 # Sample count of references to valid blocks. 1104system.cpu0.icache.tags.avg_refs 28.834504 # Average number of references to valid blocks. 1105system.cpu0.icache.tags.warmup_cycle 6511134000 # Cycle when the warmup percentage was hit. 1106system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762789 # Average occupied blocks per requestor 1107system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy 1108system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy | 1106system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16337.533685 # average overall mshr miss latency 1107system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16337.533685 # average overall mshr miss latency 1108system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16375.904865 # average overall mshr miss latency 1109system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16375.904865 # average overall mshr miss latency 1110system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208425.287899 # average ReadReq mshr uncacheable latency 1111system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208425.287899 # average ReadReq mshr uncacheable latency 1112system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109964.848354 # average overall mshr uncacheable latency 1113system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109964.848354 # average overall mshr uncacheable latency 1114system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1115system.cpu0.icache.tags.replacements 1252192 # number of replacements 1116system.cpu0.icache.tags.tagsinuse 511.757674 # Cycle average of tags in use 1117system.cpu0.icache.tags.total_refs 71518552 # Total number of references to valid blocks. 1118system.cpu0.icache.tags.sampled_refs 1252703 # Sample count of references to valid blocks. 1119system.cpu0.icache.tags.avg_refs 57.091387 # Average number of references to valid blocks. 1120system.cpu0.icache.tags.warmup_cycle 6585004000 # Cycle when the warmup percentage was hit. 1121system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757674 # Average occupied blocks per requestor 1122system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy 1123system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy |
| 1109system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1110system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id | 1124system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1125system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id |
| 1111system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id 1112system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id | 1126system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 1127system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id |
| 1113system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 1128system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 1114system.cpu0.icache.tags.tag_accesses 76255085 # Number of tag accesses 1115system.cpu0.icache.tags.data_accesses 76255085 # Number of data accesses 1116system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1117system.cpu0.icache.ReadReq_hits::cpu0.inst 36189843 # number of ReadReq hits 1118system.cpu0.icache.ReadReq_hits::total 36189843 # number of ReadReq hits 1119system.cpu0.icache.demand_hits::cpu0.inst 36189843 # number of demand (read+write) hits 1120system.cpu0.icache.demand_hits::total 36189843 # number of demand (read+write) hits 1121system.cpu0.icache.overall_hits::cpu0.inst 36189843 # number of overall hits 1122system.cpu0.icache.overall_hits::total 36189843 # number of overall hits 1123system.cpu0.icache.ReadReq_misses::cpu0.inst 1310126 # number of ReadReq misses 1124system.cpu0.icache.ReadReq_misses::total 1310126 # number of ReadReq misses 1125system.cpu0.icache.demand_misses::cpu0.inst 1310126 # number of demand (read+write) misses 1126system.cpu0.icache.demand_misses::total 1310126 # number of demand (read+write) misses 1127system.cpu0.icache.overall_misses::cpu0.inst 1310126 # number of overall misses 1128system.cpu0.icache.overall_misses::total 1310126 # number of overall misses 1129system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13674177457 # number of ReadReq miss cycles 1130system.cpu0.icache.ReadReq_miss_latency::total 13674177457 # number of ReadReq miss cycles 1131system.cpu0.icache.demand_miss_latency::cpu0.inst 13674177457 # number of demand (read+write) miss cycles 1132system.cpu0.icache.demand_miss_latency::total 13674177457 # number of demand (read+write) miss cycles 1133system.cpu0.icache.overall_miss_latency::cpu0.inst 13674177457 # number of overall miss cycles 1134system.cpu0.icache.overall_miss_latency::total 13674177457 # number of overall miss cycles 1135system.cpu0.icache.ReadReq_accesses::cpu0.inst 37499969 # number of ReadReq accesses(hits+misses) 1136system.cpu0.icache.ReadReq_accesses::total 37499969 # number of ReadReq accesses(hits+misses) 1137system.cpu0.icache.demand_accesses::cpu0.inst 37499969 # number of demand (read+write) accesses 1138system.cpu0.icache.demand_accesses::total 37499969 # number of demand (read+write) accesses 1139system.cpu0.icache.overall_accesses::cpu0.inst 37499969 # number of overall (read+write) accesses 1140system.cpu0.icache.overall_accesses::total 37499969 # number of overall (read+write) accesses 1141system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034937 # miss rate for ReadReq accesses 1142system.cpu0.icache.ReadReq_miss_rate::total 0.034937 # miss rate for ReadReq accesses 1143system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034937 # miss rate for demand accesses 1144system.cpu0.icache.demand_miss_rate::total 0.034937 # miss rate for demand accesses 1145system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034937 # miss rate for overall accesses 1146system.cpu0.icache.overall_miss_rate::total 0.034937 # miss rate for overall accesses 1147system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509 # average ReadReq miss latency 1148system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509 # average ReadReq miss latency 1149system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency 1150system.cpu0.icache.demand_avg_miss_latency::total 10437.299509 # average overall miss latency 1151system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency 1152system.cpu0.icache.overall_avg_miss_latency::total 10437.299509 # average overall miss latency 1153system.cpu0.icache.blocked_cycles::no_mshrs 1615389 # number of cycles access was blocked 1154system.cpu0.icache.blocked_cycles::no_targets 855 # number of cycles access was blocked 1155system.cpu0.icache.blocked::no_mshrs 113956 # number of cycles access was blocked 1156system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked 1157system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.175550 # average number of cycles each access was blocked 1158system.cpu0.icache.avg_blocked_cycles::no_targets 85.500000 # average number of cycles each access was blocked 1159system.cpu0.icache.writebacks::writebacks 1254577 # number of writebacks 1160system.cpu0.icache.writebacks::total 1254577 # number of writebacks 1161system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54978 # number of ReadReq MSHR hits 1162system.cpu0.icache.ReadReq_mshr_hits::total 54978 # number of ReadReq MSHR hits 1163system.cpu0.icache.demand_mshr_hits::cpu0.inst 54978 # number of demand (read+write) MSHR hits 1164system.cpu0.icache.demand_mshr_hits::total 54978 # number of demand (read+write) MSHR hits 1165system.cpu0.icache.overall_mshr_hits::cpu0.inst 54978 # number of overall MSHR hits 1166system.cpu0.icache.overall_mshr_hits::total 54978 # number of overall MSHR hits 1167system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1255148 # number of ReadReq MSHR misses 1168system.cpu0.icache.ReadReq_mshr_misses::total 1255148 # number of ReadReq MSHR misses 1169system.cpu0.icache.demand_mshr_misses::cpu0.inst 1255148 # number of demand (read+write) MSHR misses 1170system.cpu0.icache.demand_mshr_misses::total 1255148 # number of demand (read+write) MSHR misses 1171system.cpu0.icache.overall_mshr_misses::cpu0.inst 1255148 # number of overall MSHR misses 1172system.cpu0.icache.overall_mshr_misses::total 1255148 # number of overall MSHR misses 1173system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1174system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1175system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1176system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1177system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12423139434 # number of ReadReq MSHR miss cycles 1178system.cpu0.icache.ReadReq_mshr_miss_latency::total 12423139434 # number of ReadReq MSHR miss cycles 1179system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12423139434 # number of demand (read+write) MSHR miss cycles 1180system.cpu0.icache.demand_mshr_miss_latency::total 12423139434 # number of demand (read+write) MSHR miss cycles 1181system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12423139434 # number of overall MSHR miss cycles 1182system.cpu0.icache.overall_mshr_miss_latency::total 12423139434 # number of overall MSHR miss cycles 1183system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles 1184system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles 1185system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles 1186system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles 1187system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for ReadReq accesses 1188system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033471 # mshr miss rate for ReadReq accesses 1189system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for demand accesses 1190system.cpu0.icache.demand_mshr_miss_rate::total 0.033471 # mshr miss rate for demand accesses 1191system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for overall accesses 1192system.cpu0.icache.overall_mshr_miss_rate::total 0.033471 # mshr miss rate for overall accesses 1193system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average ReadReq mshr miss latency 1194system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9897.748659 # average ReadReq mshr miss latency 1195system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency 1196system.cpu0.icache.demand_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency 1197system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency 1198system.cpu0.icache.overall_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency 1199system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency 1200system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency 1201system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency 1202system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency 1203system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1204system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846782 # number of hwpf issued 1205system.cpu0.l2cache.prefetcher.pfIdentified 1849282 # number of prefetch candidates identified 1206system.cpu0.l2cache.prefetcher.pfBufferHit 2270 # number of redundant prefetches already in prefetch queue | 1129system.cpu0.icache.tags.tag_accesses 146904258 # Number of tag accesses 1130system.cpu0.icache.tags.data_accesses 146904258 # Number of data accesses 1131system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1132system.cpu0.icache.ReadReq_hits::cpu0.inst 71518555 # number of ReadReq hits 1133system.cpu0.icache.ReadReq_hits::total 71518555 # number of ReadReq hits 1134system.cpu0.icache.demand_hits::cpu0.inst 71518555 # number of demand (read+write) hits 1135system.cpu0.icache.demand_hits::total 71518555 # number of demand (read+write) hits 1136system.cpu0.icache.overall_hits::cpu0.inst 71518555 # number of overall hits 1137system.cpu0.icache.overall_hits::total 71518555 # number of overall hits 1138system.cpu0.icache.ReadReq_misses::cpu0.inst 1307201 # number of ReadReq misses 1139system.cpu0.icache.ReadReq_misses::total 1307201 # number of ReadReq misses 1140system.cpu0.icache.demand_misses::cpu0.inst 1307201 # number of demand (read+write) misses 1141system.cpu0.icache.demand_misses::total 1307201 # number of demand (read+write) misses 1142system.cpu0.icache.overall_misses::cpu0.inst 1307201 # number of overall misses 1143system.cpu0.icache.overall_misses::total 1307201 # number of overall misses 1144system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14223203310 # number of ReadReq miss cycles 1145system.cpu0.icache.ReadReq_miss_latency::total 14223203310 # number of ReadReq miss cycles 1146system.cpu0.icache.demand_miss_latency::cpu0.inst 14223203310 # number of demand (read+write) miss cycles 1147system.cpu0.icache.demand_miss_latency::total 14223203310 # number of demand (read+write) miss cycles 1148system.cpu0.icache.overall_miss_latency::cpu0.inst 14223203310 # number of overall miss cycles 1149system.cpu0.icache.overall_miss_latency::total 14223203310 # number of overall miss cycles 1150system.cpu0.icache.ReadReq_accesses::cpu0.inst 72825756 # number of ReadReq accesses(hits+misses) 1151system.cpu0.icache.ReadReq_accesses::total 72825756 # number of ReadReq accesses(hits+misses) 1152system.cpu0.icache.demand_accesses::cpu0.inst 72825756 # number of demand (read+write) accesses 1153system.cpu0.icache.demand_accesses::total 72825756 # number of demand (read+write) accesses 1154system.cpu0.icache.overall_accesses::cpu0.inst 72825756 # number of overall (read+write) accesses 1155system.cpu0.icache.overall_accesses::total 72825756 # number of overall (read+write) accesses 1156system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017950 # miss rate for ReadReq accesses 1157system.cpu0.icache.ReadReq_miss_rate::total 0.017950 # miss rate for ReadReq accesses 1158system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017950 # miss rate for demand accesses 1159system.cpu0.icache.demand_miss_rate::total 0.017950 # miss rate for demand accesses 1160system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017950 # miss rate for overall accesses 1161system.cpu0.icache.overall_miss_rate::total 0.017950 # miss rate for overall accesses 1162system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10880.655163 # average ReadReq miss latency 1163system.cpu0.icache.ReadReq_avg_miss_latency::total 10880.655163 # average ReadReq miss latency 1164system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency 1165system.cpu0.icache.demand_avg_miss_latency::total 10880.655163 # average overall miss latency 1166system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency 1167system.cpu0.icache.overall_avg_miss_latency::total 10880.655163 # average overall miss latency 1168system.cpu0.icache.blocked_cycles::no_mshrs 1774060 # number of cycles access was blocked 1169system.cpu0.icache.blocked_cycles::no_targets 1996 # number of cycles access was blocked 1170system.cpu0.icache.blocked::no_mshrs 116060 # number of cycles access was blocked 1171system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked 1172system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.285714 # average number of cycles each access was blocked 1173system.cpu0.icache.avg_blocked_cycles::no_targets 153.538462 # average number of cycles each access was blocked 1174system.cpu0.icache.writebacks::writebacks 1252192 # number of writebacks 1175system.cpu0.icache.writebacks::total 1252192 # number of writebacks 1176system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54454 # number of ReadReq MSHR hits 1177system.cpu0.icache.ReadReq_mshr_hits::total 54454 # number of ReadReq MSHR hits 1178system.cpu0.icache.demand_mshr_hits::cpu0.inst 54454 # number of demand (read+write) MSHR hits 1179system.cpu0.icache.demand_mshr_hits::total 54454 # number of demand (read+write) MSHR hits 1180system.cpu0.icache.overall_mshr_hits::cpu0.inst 54454 # number of overall MSHR hits 1181system.cpu0.icache.overall_mshr_hits::total 54454 # number of overall MSHR hits 1182system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1252747 # number of ReadReq MSHR misses 1183system.cpu0.icache.ReadReq_mshr_misses::total 1252747 # number of ReadReq MSHR misses 1184system.cpu0.icache.demand_mshr_misses::cpu0.inst 1252747 # number of demand (read+write) MSHR misses 1185system.cpu0.icache.demand_mshr_misses::total 1252747 # number of demand (read+write) MSHR misses 1186system.cpu0.icache.overall_mshr_misses::cpu0.inst 1252747 # number of overall MSHR misses 1187system.cpu0.icache.overall_mshr_misses::total 1252747 # number of overall MSHR misses 1188system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable 1189system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable 1190system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses 1191system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses 1192system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12840860811 # number of ReadReq MSHR miss cycles 1193system.cpu0.icache.ReadReq_mshr_miss_latency::total 12840860811 # number of ReadReq MSHR miss cycles 1194system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12840860811 # number of demand (read+write) MSHR miss cycles 1195system.cpu0.icache.demand_mshr_miss_latency::total 12840860811 # number of demand (read+write) MSHR miss cycles 1196system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12840860811 # number of overall MSHR miss cycles 1197system.cpu0.icache.overall_mshr_miss_latency::total 12840860811 # number of overall MSHR miss cycles 1198system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles 1199system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles 1200system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles 1201system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles 1202system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for ReadReq accesses 1203system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017202 # mshr miss rate for ReadReq accesses 1204system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for demand accesses 1205system.cpu0.icache.demand_mshr_miss_rate::total 0.017202 # mshr miss rate for demand accesses 1206system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for overall accesses 1207system.cpu0.icache.overall_mshr_miss_rate::total 0.017202 # mshr miss rate for overall accesses 1208system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average ReadReq mshr miss latency 1209system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10250.162891 # average ReadReq mshr miss latency 1210system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency 1211system.cpu0.icache.demand_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency 1212system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency 1213system.cpu0.icache.overall_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency 1214system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency 1215system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency 1216system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency 1217system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency 1218system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1219system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846192 # number of hwpf issued 1220system.cpu0.l2cache.prefetcher.pfIdentified 1848788 # number of prefetch candidates identified 1221system.cpu0.l2cache.prefetcher.pfBufferHit 2354 # number of redundant prefetches already in prefetch queue |
| 1207system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1208system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1222system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1223system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1209system.cpu0.l2cache.prefetcher.pfSpanPage 236718 # number of prefetches not generated due to page crossing 1210system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1211system.cpu0.l2cache.tags.replacements 273792 # number of replacements 1212system.cpu0.l2cache.tags.tagsinuse 15633.615902 # Cycle average of tags in use 1213system.cpu0.l2cache.tags.total_refs 1886952 # Total number of references to valid blocks. 1214system.cpu0.l2cache.tags.sampled_refs 289401 # Sample count of references to valid blocks. 1215system.cpu0.l2cache.tags.avg_refs 6.520199 # Average number of references to valid blocks. | 1224system.cpu0.l2cache.prefetcher.pfSpanPage 238916 # number of prefetches not generated due to page crossing 1225system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1226system.cpu0.l2cache.tags.replacements 272116 # number of replacements 1227system.cpu0.l2cache.tags.tagsinuse 15645.226913 # Cycle average of tags in use 1228system.cpu0.l2cache.tags.total_refs 1883031 # Total number of references to valid blocks. 1229system.cpu0.l2cache.tags.sampled_refs 287760 # Sample count of references to valid blocks. 1230system.cpu0.l2cache.tags.avg_refs 6.543755 # Average number of references to valid blocks. |
| 1216system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1231system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1217system.cpu0.l2cache.tags.occ_blocks::writebacks 14449.190897 # Average occupied blocks per requestor 1218system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.342760 # Average occupied blocks per requestor 1219system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.746834 # Average occupied blocks per requestor 1220system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.335411 # Average occupied blocks per requestor 1221system.cpu0.l2cache.tags.occ_percent::writebacks 0.881909 # Average percentage of cache occupancy 1222system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000753 # Average percentage of cache occupancy 1223system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy 1224system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071493 # Average percentage of cache occupancy 1225system.cpu0.l2cache.tags.occ_percent::total 0.954200 # Average percentage of cache occupancy 1226system.cpu0.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id | 1232system.cpu0.l2cache.tags.occ_blocks::writebacks 14543.018555 # Average occupied blocks per requestor 1233system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.670469 # Average occupied blocks per requestor 1234system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.025524 # Average occupied blocks per requestor 1235system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1089.512365 # Average occupied blocks per requestor 1236system.cpu0.l2cache.tags.occ_percent::writebacks 0.887635 # Average percentage of cache occupancy 1237system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000712 # Average percentage of cache occupancy 1238system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy 1239system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066499 # Average percentage of cache occupancy 1240system.cpu0.l2cache.tags.occ_percent::total 0.954909 # Average percentage of cache occupancy 1241system.cpu0.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id |
| 1227system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id | 1242system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id |
| 1228system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15328 # Occupied blocks per task id 1229system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 1230system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id | 1243system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15373 # Occupied blocks per task id 1244system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 1245system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id |
| 1231system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id | 1246system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id |
| 1232system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 81 # Occupied blocks per task id 1233system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 1234system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1235system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 1236system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 311 # Occupied blocks per task id 1237system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1438 # Occupied blocks per task id 1238system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7629 # Occupied blocks per task id 1239system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4500 # Occupied blocks per task id 1240system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1450 # Occupied blocks per task id 1241system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id | 1247system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id 1248system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1249system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1250system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 1251system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 318 # Occupied blocks per task id 1252system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1446 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7384 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4965 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1260 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id |
| 1242system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id | 1257system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id |
| 1243system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.935547 # Percentage of cache occupancy per task id 1244system.cpu0.l2cache.tags.tag_accesses 67735071 # Number of tag accesses 1245system.cpu0.l2cache.tags.data_accesses 67735071 # Number of data accesses 1246system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1247system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55557 # number of ReadReq hits 1248system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13221 # number of ReadReq hits 1249system.cpu0.l2cache.ReadReq_hits::total 68778 # number of ReadReq hits 1250system.cpu0.l2cache.WritebackDirty_hits::writebacks 483131 # number of WritebackDirty hits 1251system.cpu0.l2cache.WritebackDirty_hits::total 483131 # number of WritebackDirty hits 1252system.cpu0.l2cache.WritebackClean_hits::writebacks 1451301 # number of WritebackClean hits 1253system.cpu0.l2cache.WritebackClean_hits::total 1451301 # number of WritebackClean hits 1254system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4 # number of UpgradeReq hits 1255system.cpu0.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 1256system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221119 # number of ReadExReq hits 1257system.cpu0.l2cache.ReadExReq_hits::total 221119 # number of ReadExReq hits 1258system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1183848 # number of ReadCleanReq hits 1259system.cpu0.l2cache.ReadCleanReq_hits::total 1183848 # number of ReadCleanReq hits 1260system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 387908 # number of ReadSharedReq hits 1261system.cpu0.l2cache.ReadSharedReq_hits::total 387908 # number of ReadSharedReq hits 1262system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55557 # number of demand (read+write) hits 1263system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13221 # number of demand (read+write) hits 1264system.cpu0.l2cache.demand_hits::cpu0.inst 1183848 # number of demand (read+write) hits 1265system.cpu0.l2cache.demand_hits::cpu0.data 609027 # number of demand (read+write) hits 1266system.cpu0.l2cache.demand_hits::total 1861653 # number of demand (read+write) hits 1267system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55557 # number of overall hits 1268system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13221 # number of overall hits 1269system.cpu0.l2cache.overall_hits::cpu0.inst 1183848 # number of overall hits 1270system.cpu0.l2cache.overall_hits::cpu0.data 609027 # number of overall hits 1271system.cpu0.l2cache.overall_hits::total 1861653 # number of overall hits 1272system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 499 # number of ReadReq misses 1273system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 185 # number of ReadReq misses 1274system.cpu0.l2cache.ReadReq_misses::total 684 # number of ReadReq misses 1275system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55776 # number of UpgradeReq misses 1276system.cpu0.l2cache.UpgradeReq_misses::total 55776 # number of UpgradeReq misses 1277system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20170 # number of SCUpgradeReq misses 1278system.cpu0.l2cache.SCUpgradeReq_misses::total 20170 # number of SCUpgradeReq misses 1279system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 1280system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1281system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48817 # number of ReadExReq misses 1282system.cpu0.l2cache.ReadExReq_misses::total 48817 # number of ReadExReq misses 1283system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 71252 # number of ReadCleanReq misses 1284system.cpu0.l2cache.ReadCleanReq_misses::total 71252 # number of ReadCleanReq misses 1285system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 108229 # number of ReadSharedReq misses 1286system.cpu0.l2cache.ReadSharedReq_misses::total 108229 # number of ReadSharedReq misses 1287system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 499 # number of demand (read+write) misses 1288system.cpu0.l2cache.demand_misses::cpu0.itb.walker 185 # number of demand (read+write) misses 1289system.cpu0.l2cache.demand_misses::cpu0.inst 71252 # number of demand (read+write) misses 1290system.cpu0.l2cache.demand_misses::cpu0.data 157046 # number of demand (read+write) misses 1291system.cpu0.l2cache.demand_misses::total 228982 # number of demand (read+write) misses 1292system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 499 # number of overall misses 1293system.cpu0.l2cache.overall_misses::cpu0.itb.walker 185 # number of overall misses 1294system.cpu0.l2cache.overall_misses::cpu0.inst 71252 # number of overall misses 1295system.cpu0.l2cache.overall_misses::cpu0.data 157046 # number of overall misses 1296system.cpu0.l2cache.overall_misses::total 228982 # number of overall misses 1297system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14052000 # number of ReadReq miss cycles 1298system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4306000 # number of ReadReq miss cycles 1299system.cpu0.l2cache.ReadReq_miss_latency::total 18358000 # number of ReadReq miss cycles 1300system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 37654000 # number of UpgradeReq miss cycles 1301system.cpu0.l2cache.UpgradeReq_miss_latency::total 37654000 # number of UpgradeReq miss cycles 1302system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9570500 # number of SCUpgradeReq miss cycles 1303system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9570500 # number of SCUpgradeReq miss cycles 1304system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 531998 # number of SCUpgradeFailReq miss cycles 1305system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 531998 # number of SCUpgradeFailReq miss cycles 1306system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2721932500 # number of ReadExReq miss cycles 1307system.cpu0.l2cache.ReadExReq_miss_latency::total 2721932500 # number of ReadExReq miss cycles 1308system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3344074000 # number of ReadCleanReq miss cycles 1309system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3344074000 # number of ReadCleanReq miss cycles 1310system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3294040496 # number of ReadSharedReq miss cycles 1311system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3294040496 # number of ReadSharedReq miss cycles 1312system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14052000 # number of demand (read+write) miss cycles 1313system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4306000 # number of demand (read+write) miss cycles 1314system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3344074000 # number of demand (read+write) miss cycles 1315system.cpu0.l2cache.demand_miss_latency::cpu0.data 6015972996 # number of demand (read+write) miss cycles 1316system.cpu0.l2cache.demand_miss_latency::total 9378404996 # number of demand (read+write) miss cycles 1317system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14052000 # number of overall miss cycles 1318system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4306000 # number of overall miss cycles 1319system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3344074000 # number of overall miss cycles 1320system.cpu0.l2cache.overall_miss_latency::cpu0.data 6015972996 # number of overall miss cycles 1321system.cpu0.l2cache.overall_miss_latency::total 9378404996 # number of overall miss cycles 1322system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 56056 # number of ReadReq accesses(hits+misses) 1323system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13406 # number of ReadReq accesses(hits+misses) 1324system.cpu0.l2cache.ReadReq_accesses::total 69462 # number of ReadReq accesses(hits+misses) 1325system.cpu0.l2cache.WritebackDirty_accesses::writebacks 483131 # number of WritebackDirty accesses(hits+misses) 1326system.cpu0.l2cache.WritebackDirty_accesses::total 483131 # number of WritebackDirty accesses(hits+misses) 1327system.cpu0.l2cache.WritebackClean_accesses::writebacks 1451301 # number of WritebackClean accesses(hits+misses) 1328system.cpu0.l2cache.WritebackClean_accesses::total 1451301 # number of WritebackClean accesses(hits+misses) 1329system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55780 # number of UpgradeReq accesses(hits+misses) 1330system.cpu0.l2cache.UpgradeReq_accesses::total 55780 # number of UpgradeReq accesses(hits+misses) 1331system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20170 # number of SCUpgradeReq accesses(hits+misses) 1332system.cpu0.l2cache.SCUpgradeReq_accesses::total 20170 # number of SCUpgradeReq accesses(hits+misses) 1333system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1334system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1335system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269936 # number of ReadExReq accesses(hits+misses) 1336system.cpu0.l2cache.ReadExReq_accesses::total 269936 # number of ReadExReq accesses(hits+misses) 1337system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1255100 # number of ReadCleanReq accesses(hits+misses) 1338system.cpu0.l2cache.ReadCleanReq_accesses::total 1255100 # number of ReadCleanReq accesses(hits+misses) 1339system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 496137 # number of ReadSharedReq accesses(hits+misses) 1340system.cpu0.l2cache.ReadSharedReq_accesses::total 496137 # number of ReadSharedReq accesses(hits+misses) 1341system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 56056 # number of demand (read+write) accesses 1342system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13406 # number of demand (read+write) accesses 1343system.cpu0.l2cache.demand_accesses::cpu0.inst 1255100 # number of demand (read+write) accesses 1344system.cpu0.l2cache.demand_accesses::cpu0.data 766073 # number of demand (read+write) accesses 1345system.cpu0.l2cache.demand_accesses::total 2090635 # number of demand (read+write) accesses 1346system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 56056 # number of overall (read+write) accesses 1347system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13406 # number of overall (read+write) accesses 1348system.cpu0.l2cache.overall_accesses::cpu0.inst 1255100 # number of overall (read+write) accesses 1349system.cpu0.l2cache.overall_accesses::cpu0.data 766073 # number of overall (read+write) accesses 1350system.cpu0.l2cache.overall_accesses::total 2090635 # number of overall (read+write) accesses 1351system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008902 # miss rate for ReadReq accesses 1352system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013800 # miss rate for ReadReq accesses 1353system.cpu0.l2cache.ReadReq_miss_rate::total 0.009847 # miss rate for ReadReq accesses 1354system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999928 # miss rate for UpgradeReq accesses 1355system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999928 # miss rate for UpgradeReq accesses | 1258system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.938293 # Percentage of cache occupancy per task id 1259system.cpu0.l2cache.tags.tag_accesses 67637085 # Number of tag accesses 1260system.cpu0.l2cache.tags.data_accesses 67637085 # Number of data accesses 1261system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1262system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55351 # number of ReadReq hits 1263system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13068 # number of ReadReq hits 1264system.cpu0.l2cache.ReadReq_hits::total 68419 # number of ReadReq hits 1265system.cpu0.l2cache.WritebackDirty_hits::writebacks 481133 # number of WritebackDirty hits 1266system.cpu0.l2cache.WritebackDirty_hits::total 481133 # number of WritebackDirty hits 1267system.cpu0.l2cache.WritebackClean_hits::writebacks 1450737 # number of WritebackClean hits 1268system.cpu0.l2cache.WritebackClean_hits::total 1450737 # number of WritebackClean hits 1269system.cpu0.l2cache.ReadExReq_hits::cpu0.data 220760 # number of ReadExReq hits 1270system.cpu0.l2cache.ReadExReq_hits::total 220760 # number of ReadExReq hits 1271system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1181751 # number of ReadCleanReq hits 1272system.cpu0.l2cache.ReadCleanReq_hits::total 1181751 # number of ReadCleanReq hits 1273system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 388592 # number of ReadSharedReq hits 1274system.cpu0.l2cache.ReadSharedReq_hits::total 388592 # number of ReadSharedReq hits 1275system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55351 # number of demand (read+write) hits 1276system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13068 # number of demand (read+write) hits 1277system.cpu0.l2cache.demand_hits::cpu0.inst 1181751 # number of demand (read+write) hits 1278system.cpu0.l2cache.demand_hits::cpu0.data 609352 # number of demand (read+write) hits 1279system.cpu0.l2cache.demand_hits::total 1859522 # number of demand (read+write) hits 1280system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55351 # number of overall hits 1281system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13068 # number of overall hits 1282system.cpu0.l2cache.overall_hits::cpu0.inst 1181751 # number of overall hits 1283system.cpu0.l2cache.overall_hits::cpu0.data 609352 # number of overall hits 1284system.cpu0.l2cache.overall_hits::total 1859522 # number of overall hits 1285system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses 1286system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 200 # number of ReadReq misses 1287system.cpu0.l2cache.ReadReq_misses::total 707 # number of ReadReq misses 1288system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55745 # number of UpgradeReq misses 1289system.cpu0.l2cache.UpgradeReq_misses::total 55745 # number of UpgradeReq misses 1290system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20165 # number of SCUpgradeReq misses 1291system.cpu0.l2cache.SCUpgradeReq_misses::total 20165 # number of SCUpgradeReq misses 1292system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48603 # number of ReadExReq misses 1293system.cpu0.l2cache.ReadExReq_misses::total 48603 # number of ReadExReq misses 1294system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70953 # number of ReadCleanReq misses 1295system.cpu0.l2cache.ReadCleanReq_misses::total 70953 # number of ReadCleanReq misses 1296system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107504 # number of ReadSharedReq misses 1297system.cpu0.l2cache.ReadSharedReq_misses::total 107504 # number of ReadSharedReq misses 1298system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 507 # number of demand (read+write) misses 1299system.cpu0.l2cache.demand_misses::cpu0.itb.walker 200 # number of demand (read+write) misses 1300system.cpu0.l2cache.demand_misses::cpu0.inst 70953 # number of demand (read+write) misses 1301system.cpu0.l2cache.demand_misses::cpu0.data 156107 # number of demand (read+write) misses 1302system.cpu0.l2cache.demand_misses::total 227767 # number of demand (read+write) misses 1303system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses 1304system.cpu0.l2cache.overall_misses::cpu0.itb.walker 200 # number of overall misses 1305system.cpu0.l2cache.overall_misses::cpu0.inst 70953 # number of overall misses 1306system.cpu0.l2cache.overall_misses::cpu0.data 156107 # number of overall misses 1307system.cpu0.l2cache.overall_misses::total 227767 # number of overall misses 1308system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15335000 # number of ReadReq miss cycles 1309system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4771500 # number of ReadReq miss cycles 1310system.cpu0.l2cache.ReadReq_miss_latency::total 20106500 # number of ReadReq miss cycles 1311system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 35671000 # number of UpgradeReq miss cycles 1312system.cpu0.l2cache.UpgradeReq_miss_latency::total 35671000 # number of UpgradeReq miss cycles 1313system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9320000 # number of SCUpgradeReq miss cycles 1314system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9320000 # number of SCUpgradeReq miss cycles 1315system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 415000 # number of SCUpgradeFailReq miss cycles 1316system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 415000 # number of SCUpgradeFailReq miss cycles 1317system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3386740000 # number of ReadExReq miss cycles 1318system.cpu0.l2cache.ReadExReq_miss_latency::total 3386740000 # number of ReadExReq miss cycles 1319system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3777812500 # number of ReadCleanReq miss cycles 1320system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3777812500 # number of ReadCleanReq miss cycles 1321system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3493890998 # number of ReadSharedReq miss cycles 1322system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3493890998 # number of ReadSharedReq miss cycles 1323system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15335000 # number of demand (read+write) miss cycles 1324system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4771500 # number of demand (read+write) miss cycles 1325system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3777812500 # number of demand (read+write) miss cycles 1326system.cpu0.l2cache.demand_miss_latency::cpu0.data 6880630998 # number of demand (read+write) miss cycles 1327system.cpu0.l2cache.demand_miss_latency::total 10678549998 # number of demand (read+write) miss cycles 1328system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15335000 # number of overall miss cycles 1329system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4771500 # number of overall miss cycles 1330system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3777812500 # number of overall miss cycles 1331system.cpu0.l2cache.overall_miss_latency::cpu0.data 6880630998 # number of overall miss cycles 1332system.cpu0.l2cache.overall_miss_latency::total 10678549998 # number of overall miss cycles 1333system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55858 # number of ReadReq accesses(hits+misses) 1334system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13268 # number of ReadReq accesses(hits+misses) 1335system.cpu0.l2cache.ReadReq_accesses::total 69126 # number of ReadReq accesses(hits+misses) 1336system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481133 # number of WritebackDirty accesses(hits+misses) 1337system.cpu0.l2cache.WritebackDirty_accesses::total 481133 # number of WritebackDirty accesses(hits+misses) 1338system.cpu0.l2cache.WritebackClean_accesses::writebacks 1450737 # number of WritebackClean accesses(hits+misses) 1339system.cpu0.l2cache.WritebackClean_accesses::total 1450737 # number of WritebackClean accesses(hits+misses) 1340system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses) 1341system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses) 1342system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20165 # number of SCUpgradeReq accesses(hits+misses) 1343system.cpu0.l2cache.SCUpgradeReq_accesses::total 20165 # number of SCUpgradeReq accesses(hits+misses) 1344system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269363 # number of ReadExReq accesses(hits+misses) 1345system.cpu0.l2cache.ReadExReq_accesses::total 269363 # number of ReadExReq accesses(hits+misses) 1346system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1252704 # number of ReadCleanReq accesses(hits+misses) 1347system.cpu0.l2cache.ReadCleanReq_accesses::total 1252704 # number of ReadCleanReq accesses(hits+misses) 1348system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 496096 # number of ReadSharedReq accesses(hits+misses) 1349system.cpu0.l2cache.ReadSharedReq_accesses::total 496096 # number of ReadSharedReq accesses(hits+misses) 1350system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55858 # number of demand (read+write) accesses 1351system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13268 # number of demand (read+write) accesses 1352system.cpu0.l2cache.demand_accesses::cpu0.inst 1252704 # number of demand (read+write) accesses 1353system.cpu0.l2cache.demand_accesses::cpu0.data 765459 # number of demand (read+write) accesses 1354system.cpu0.l2cache.demand_accesses::total 2087289 # number of demand (read+write) accesses 1355system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55858 # number of overall (read+write) accesses 1356system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13268 # number of overall (read+write) accesses 1357system.cpu0.l2cache.overall_accesses::cpu0.inst 1252704 # number of overall (read+write) accesses 1358system.cpu0.l2cache.overall_accesses::cpu0.data 765459 # number of overall (read+write) accesses 1359system.cpu0.l2cache.overall_accesses::total 2087289 # number of overall (read+write) accesses 1360system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for ReadReq accesses 1361system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015074 # miss rate for ReadReq accesses 1362system.cpu0.l2cache.ReadReq_miss_rate::total 0.010228 # miss rate for ReadReq accesses 1363system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1364system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1356system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1357system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1365system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1366system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1358system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1359system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1360system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180847 # miss rate for ReadExReq accesses 1361system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180847 # miss rate for ReadExReq accesses 1362system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056770 # miss rate for ReadCleanReq accesses 1363system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056770 # miss rate for ReadCleanReq accesses 1364system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.218143 # miss rate for ReadSharedReq accesses 1365system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.218143 # miss rate for ReadSharedReq accesses 1366system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008902 # miss rate for demand accesses 1367system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013800 # miss rate for demand accesses 1368system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056770 # miss rate for demand accesses 1369system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.205001 # miss rate for demand accesses 1370system.cpu0.l2cache.demand_miss_rate::total 0.109527 # miss rate for demand accesses 1371system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008902 # miss rate for overall accesses 1372system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013800 # miss rate for overall accesses 1373system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056770 # miss rate for overall accesses 1374system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.205001 # miss rate for overall accesses 1375system.cpu0.l2cache.overall_miss_rate::total 0.109527 # miss rate for overall accesses 1376system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28160.320641 # average ReadReq miss latency 1377system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23275.675676 # average ReadReq miss latency 1378system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26839.181287 # average ReadReq miss latency 1379system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 675.093230 # average UpgradeReq miss latency 1380system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 675.093230 # average UpgradeReq miss latency 1381system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 474.491820 # average SCUpgradeReq miss latency 1382system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 474.491820 # average SCUpgradeReq miss latency 1383system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 132999.500000 # average SCUpgradeFailReq miss latency 1384system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 132999.500000 # average SCUpgradeFailReq miss latency 1385system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55757.881476 # average ReadExReq miss latency 1386system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55757.881476 # average ReadExReq miss latency 1387system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 46933.054511 # average ReadCleanReq miss latency 1388system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 46933.054511 # average ReadCleanReq miss latency 1389system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30435.839710 # average ReadSharedReq miss latency 1390system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30435.839710 # average ReadSharedReq miss latency 1391system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28160.320641 # average overall miss latency 1392system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23275.675676 # average overall miss latency 1393system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46933.054511 # average overall miss latency 1394system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38307.075608 # average overall miss latency 1395system.cpu0.l2cache.demand_avg_miss_latency::total 40956.952931 # average overall miss latency 1396system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28160.320641 # average overall miss latency 1397system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23275.675676 # average overall miss latency 1398system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46933.054511 # average overall miss latency 1399system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38307.075608 # average overall miss latency 1400system.cpu0.l2cache.overall_avg_miss_latency::total 40956.952931 # average overall miss latency 1401system.cpu0.l2cache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked | 1367system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180437 # miss rate for ReadExReq accesses 1368system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180437 # miss rate for ReadExReq accesses 1369system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056640 # miss rate for ReadCleanReq accesses 1370system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056640 # miss rate for ReadCleanReq accesses 1371system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216700 # miss rate for ReadSharedReq accesses 1372system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216700 # miss rate for ReadSharedReq accesses 1373system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for demand accesses 1374system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015074 # miss rate for demand accesses 1375system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056640 # miss rate for demand accesses 1376system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203939 # miss rate for demand accesses 1377system.cpu0.l2cache.demand_miss_rate::total 0.109121 # miss rate for demand accesses 1378system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for overall accesses 1379system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015074 # miss rate for overall accesses 1380system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056640 # miss rate for overall accesses 1381system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203939 # miss rate for overall accesses 1382system.cpu0.l2cache.overall_miss_rate::total 0.109121 # miss rate for overall accesses 1383system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average ReadReq miss latency 1384system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.500000 # average ReadReq miss latency 1385system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28439.179632 # average ReadReq miss latency 1386system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 639.895955 # average UpgradeReq miss latency 1387system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 639.895955 # average UpgradeReq miss latency 1388system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 462.186958 # average SCUpgradeReq miss latency 1389system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 462.186958 # average SCUpgradeReq miss latency 1390system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1391system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1392system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69681.706891 # average ReadExReq miss latency 1393system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69681.706891 # average ReadExReq miss latency 1394system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53243.872704 # average ReadCleanReq miss latency 1395system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53243.872704 # average ReadCleanReq miss latency 1396system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32500.102303 # average ReadSharedReq miss latency 1397system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32500.102303 # average ReadSharedReq miss latency 1398system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average overall miss latency 1399system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.500000 # average overall miss latency 1400system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53243.872704 # average overall miss latency 1401system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44076.377088 # average overall miss latency 1402system.cpu0.l2cache.demand_avg_miss_latency::total 46883.657413 # average overall miss latency 1403system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average overall miss latency 1404system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.500000 # average overall miss latency 1405system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53243.872704 # average overall miss latency 1406system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44076.377088 # average overall miss latency 1407system.cpu0.l2cache.overall_avg_miss_latency::total 46883.657413 # average overall miss latency 1408system.cpu0.l2cache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked |
| 1402system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1409system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1403system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked | 1410system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked |
| 1404system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1411system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1405system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 33.500000 # average number of cycles each access was blocked | 1412system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked |
| 1406system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1413system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1407system.cpu0.l2cache.unused_prefetches 10619 # number of HardPF blocks evicted w/o reference 1408system.cpu0.l2cache.writebacks::writebacks 231332 # number of writebacks 1409system.cpu0.l2cache.writebacks::total 231332 # number of writebacks 1410system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1411system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits 1412system.cpu0.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 1413system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5717 # number of ReadExReq MSHR hits 1414system.cpu0.l2cache.ReadExReq_mshr_hits::total 5717 # number of ReadExReq MSHR hits | 1414system.cpu0.l2cache.unused_prefetches 10599 # number of HardPF blocks evicted w/o reference 1415system.cpu0.l2cache.writebacks::writebacks 230738 # number of writebacks 1416system.cpu0.l2cache.writebacks::total 230738 # number of writebacks 1417system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 1418system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1419system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5942 # number of ReadExReq MSHR hits 1420system.cpu0.l2cache.ReadExReq_mshr_hits::total 5942 # number of ReadExReq MSHR hits |
| 1415system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 36 # number of ReadCleanReq MSHR hits 1416system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 36 # number of ReadCleanReq MSHR hits | 1421system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 36 # number of ReadCleanReq MSHR hits 1422system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 36 # number of ReadCleanReq MSHR hits |
| 1417system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 739 # number of ReadSharedReq MSHR hits 1418system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 739 # number of ReadSharedReq MSHR hits 1419system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1420system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits | 1423system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 741 # number of ReadSharedReq MSHR hits 1424system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 741 # number of ReadSharedReq MSHR hits 1425system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits |
| 1421system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 36 # number of demand (read+write) MSHR hits | 1426system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 36 # number of demand (read+write) MSHR hits |
| 1422system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6456 # number of demand (read+write) MSHR hits 1423system.cpu0.l2cache.demand_mshr_hits::total 6497 # number of demand (read+write) MSHR hits 1424system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1425system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits | 1427system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6683 # number of demand (read+write) MSHR hits 1428system.cpu0.l2cache.demand_mshr_hits::total 6721 # number of demand (read+write) MSHR hits 1429system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits |
| 1426system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 36 # number of overall MSHR hits | 1430system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 36 # number of overall MSHR hits |
| 1427system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6456 # number of overall MSHR hits 1428system.cpu0.l2cache.overall_mshr_hits::total 6497 # number of overall MSHR hits 1429system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 498 # number of ReadReq MSHR misses 1430system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 181 # number of ReadReq MSHR misses 1431system.cpu0.l2cache.ReadReq_mshr_misses::total 679 # number of ReadReq MSHR misses 1432system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265620 # number of HardPFReq MSHR misses 1433system.cpu0.l2cache.HardPFReq_mshr_misses::total 265620 # number of HardPFReq MSHR misses 1434system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55776 # number of UpgradeReq MSHR misses 1435system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55776 # number of UpgradeReq MSHR misses 1436system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20170 # number of SCUpgradeReq MSHR misses 1437system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20170 # number of SCUpgradeReq MSHR misses 1438system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1439system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1440system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43100 # number of ReadExReq MSHR misses 1441system.cpu0.l2cache.ReadExReq_mshr_misses::total 43100 # number of ReadExReq MSHR misses 1442system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 71216 # number of ReadCleanReq MSHR misses 1443system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 71216 # number of ReadCleanReq MSHR misses 1444system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 107490 # number of ReadSharedReq MSHR misses 1445system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 107490 # number of ReadSharedReq MSHR misses 1446system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 498 # number of demand (read+write) MSHR misses 1447system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 181 # number of demand (read+write) MSHR misses 1448system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 71216 # number of demand (read+write) MSHR misses 1449system.cpu0.l2cache.demand_mshr_misses::cpu0.data 150590 # number of demand (read+write) MSHR misses 1450system.cpu0.l2cache.demand_mshr_misses::total 222485 # number of demand (read+write) MSHR misses 1451system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 498 # number of overall MSHR misses 1452system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 181 # number of overall MSHR misses 1453system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 71216 # number of overall MSHR misses 1454system.cpu0.l2cache.overall_mshr_misses::cpu0.data 150590 # number of overall MSHR misses 1455system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265620 # number of overall MSHR misses 1456system.cpu0.l2cache.overall_mshr_misses::total 488105 # number of overall MSHR misses 1457system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1458system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable 1459system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23339 # number of ReadReq MSHR uncacheable 1460system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable 1461system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable 1462system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1463system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses 1464system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42371 # number of overall MSHR uncacheable misses 1465system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11046000 # number of ReadReq MSHR miss cycles 1466system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3157500 # number of ReadReq MSHR miss cycles 1467system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 14203500 # number of ReadReq MSHR miss cycles 1468system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15282370178 # number of HardPFReq MSHR miss cycles 1469system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15282370178 # number of HardPFReq MSHR miss cycles 1470system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 964881000 # number of UpgradeReq MSHR miss cycles 1471system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 964881000 # number of UpgradeReq MSHR miss cycles 1472system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 302897000 # number of SCUpgradeReq MSHR miss cycles 1473system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 302897000 # number of SCUpgradeReq MSHR miss cycles 1474system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 441998 # number of SCUpgradeFailReq MSHR miss cycles 1475system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 441998 # number of SCUpgradeFailReq MSHR miss cycles 1476system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1759055000 # number of ReadExReq MSHR miss cycles 1477system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1759055000 # number of ReadExReq MSHR miss cycles 1478system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2915623000 # number of ReadCleanReq MSHR miss cycles 1479system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2915623000 # number of ReadCleanReq MSHR miss cycles 1480system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2607419996 # number of ReadSharedReq MSHR miss cycles 1481system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2607419996 # number of ReadSharedReq MSHR miss cycles 1482system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 11046000 # number of demand (read+write) MSHR miss cycles 1483system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3157500 # number of demand (read+write) MSHR miss cycles 1484system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2915623000 # number of demand (read+write) MSHR miss cycles 1485system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4366474996 # number of demand (read+write) MSHR miss cycles 1486system.cpu0.l2cache.demand_mshr_miss_latency::total 7296301496 # number of demand (read+write) MSHR miss cycles 1487system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 11046000 # number of overall MSHR miss cycles 1488system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3157500 # number of overall MSHR miss cycles 1489system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2915623000 # number of overall MSHR miss cycles 1490system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4366474996 # number of overall MSHR miss cycles 1491system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15282370178 # number of overall MSHR miss cycles 1492system.cpu0.l2cache.overall_mshr_miss_latency::total 22578671674 # number of overall MSHR miss cycles 1493system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles 1494system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4371369500 # number of ReadReq MSHR uncacheable cycles 1495system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4617990500 # number of ReadReq MSHR uncacheable cycles 1496system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles 1497system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4371369500 # number of overall MSHR uncacheable cycles 1498system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4617990500 # number of overall MSHR uncacheable cycles 1499system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for ReadReq accesses 1500system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for ReadReq accesses 1501system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009775 # mshr miss rate for ReadReq accesses | 1431system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6683 # number of overall MSHR hits 1432system.cpu0.l2cache.overall_mshr_hits::total 6721 # number of overall MSHR hits 1433system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 507 # number of ReadReq MSHR misses 1434system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 198 # number of ReadReq MSHR misses 1435system.cpu0.l2cache.ReadReq_mshr_misses::total 705 # number of ReadReq MSHR misses 1436system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262695 # number of HardPFReq MSHR misses 1437system.cpu0.l2cache.HardPFReq_mshr_misses::total 262695 # number of HardPFReq MSHR misses 1438system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55745 # number of UpgradeReq MSHR misses 1439system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55745 # number of UpgradeReq MSHR misses 1440system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20165 # number of SCUpgradeReq MSHR misses 1441system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20165 # number of SCUpgradeReq MSHR misses 1442system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42661 # number of ReadExReq MSHR misses 1443system.cpu0.l2cache.ReadExReq_mshr_misses::total 42661 # number of ReadExReq MSHR misses 1444system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70917 # number of ReadCleanReq MSHR misses 1445system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70917 # number of ReadCleanReq MSHR misses 1446system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106763 # number of ReadSharedReq MSHR misses 1447system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106763 # number of ReadSharedReq MSHR misses 1448system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 507 # number of demand (read+write) MSHR misses 1449system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 198 # number of demand (read+write) MSHR misses 1450system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70917 # number of demand (read+write) MSHR misses 1451system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149424 # number of demand (read+write) MSHR misses 1452system.cpu0.l2cache.demand_mshr_misses::total 221046 # number of demand (read+write) MSHR misses 1453system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 507 # number of overall MSHR misses 1454system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 198 # number of overall MSHR misses 1455system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70917 # number of overall MSHR misses 1456system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149424 # number of overall MSHR misses 1457system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262695 # number of overall MSHR misses 1458system.cpu0.l2cache.overall_mshr_misses::total 483741 # number of overall MSHR misses 1459system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable 1460system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable 1461system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34790 # number of ReadReq MSHR uncacheable 1462system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable 1463system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28457 # number of WriteReq MSHR uncacheable 1464system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses 1465system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses 1466system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63247 # number of overall MSHR uncacheable misses 1467system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of ReadReq MSHR miss cycles 1468system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3546000 # number of ReadReq MSHR miss cycles 1469system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 15839000 # number of ReadReq MSHR miss cycles 1470system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17363724717 # number of HardPFReq MSHR miss cycles 1471system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17363724717 # number of HardPFReq MSHR miss cycles 1472system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 962038500 # number of UpgradeReq MSHR miss cycles 1473system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 962038500 # number of UpgradeReq MSHR miss cycles 1474system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304268499 # number of SCUpgradeReq MSHR miss cycles 1475system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304268499 # number of SCUpgradeReq MSHR miss cycles 1476system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 349000 # number of SCUpgradeFailReq MSHR miss cycles 1477system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 349000 # number of SCUpgradeFailReq MSHR miss cycles 1478system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2236694000 # number of ReadExReq MSHR miss cycles 1479system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2236694000 # number of ReadExReq MSHR miss cycles 1480system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3350952500 # number of ReadCleanReq MSHR miss cycles 1481system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3350952500 # number of ReadCleanReq MSHR miss cycles 1482system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2808325998 # number of ReadSharedReq MSHR miss cycles 1483system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2808325998 # number of ReadSharedReq MSHR miss cycles 1484system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of demand (read+write) MSHR miss cycles 1485system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3546000 # number of demand (read+write) MSHR miss cycles 1486system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3350952500 # number of demand (read+write) MSHR miss cycles 1487system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5045019998 # number of demand (read+write) MSHR miss cycles 1488system.cpu0.l2cache.demand_mshr_miss_latency::total 8411811498 # number of demand (read+write) MSHR miss cycles 1489system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of overall MSHR miss cycles 1490system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3546000 # number of overall MSHR miss cycles 1491system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3350952500 # number of overall MSHR miss cycles 1492system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5045019998 # number of overall MSHR miss cycles 1493system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17363724717 # number of overall MSHR miss cycles 1494system.cpu0.l2cache.overall_mshr_miss_latency::total 25775536215 # number of overall MSHR miss cycles 1495system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles 1496system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369584000 # number of ReadReq MSHR uncacheable cycles 1497system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6634670000 # number of ReadReq MSHR uncacheable cycles 1498system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles 1499system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6369584000 # number of overall MSHR uncacheable cycles 1500system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6634670000 # number of overall MSHR uncacheable cycles 1501system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for ReadReq accesses 1502system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for ReadReq accesses 1503system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010199 # mshr miss rate for ReadReq accesses |
| 1502system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1503system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1504system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1505system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1504system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999928 # mshr miss rate for UpgradeReq accesses 1505system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999928 # mshr miss rate for UpgradeReq accesses | 1506system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1507system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1506system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1507system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1508system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1509system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1508system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1509system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1510system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159667 # mshr miss rate for ReadExReq accesses 1511system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159667 # mshr miss rate for ReadExReq accesses 1512system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for ReadCleanReq accesses 1513system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056741 # mshr miss rate for ReadCleanReq accesses 1514system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216654 # mshr miss rate for ReadSharedReq accesses 1515system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216654 # mshr miss rate for ReadSharedReq accesses 1516system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for demand accesses 1517system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for demand accesses 1518system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for demand accesses 1519system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for demand accesses 1520system.cpu0.l2cache.demand_mshr_miss_rate::total 0.106420 # mshr miss rate for demand accesses 1521system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for overall accesses 1522system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for overall accesses 1523system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for overall accesses 1524system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for overall accesses | 1510system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158377 # mshr miss rate for ReadExReq accesses 1511system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158377 # mshr miss rate for ReadExReq accesses 1512system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for ReadCleanReq accesses 1513system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056611 # mshr miss rate for ReadCleanReq accesses 1514system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215206 # mshr miss rate for ReadSharedReq accesses 1515system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.215206 # mshr miss rate for ReadSharedReq accesses 1516system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for demand accesses 1517system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for demand accesses 1518system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for demand accesses 1519system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for demand accesses 1520system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105901 # mshr miss rate for demand accesses 1521system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for overall accesses 1522system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for overall accesses 1523system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for overall accesses 1524system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for overall accesses |
| 1525system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1525system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1526system.cpu0.l2cache.overall_mshr_miss_rate::total 0.233472 # mshr miss rate for overall accesses 1527system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average ReadReq mshr miss latency 1528system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average ReadReq mshr miss latency 1529system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150 # average ReadReq mshr miss latency 1530system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average HardPFReq mshr miss latency 1531system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912 # average HardPFReq mshr miss latency 1532system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716 # average UpgradeReq mshr miss latency 1533system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716 # average UpgradeReq mshr miss latency 1534system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768 # average SCUpgradeReq mshr miss latency 1535system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768 # average SCUpgradeReq mshr miss latency 1536system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000 # average SCUpgradeFailReq mshr miss latency 1537system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000 # average SCUpgradeFailReq mshr miss latency 1538system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067 # average ReadExReq mshr miss latency 1539system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067 # average ReadExReq mshr miss latency 1540system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average ReadCleanReq mshr miss latency 1541system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110 # average ReadCleanReq mshr miss latency 1542system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226 # average ReadSharedReq mshr miss latency 1543system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226 # average ReadSharedReq mshr miss latency 1544system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency 1545system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency 1546system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency 1547system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency 1548system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145 # average overall mshr miss latency 1549system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency 1550system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency 1551system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency 1552system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency 1553system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average overall mshr miss latency 1554system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810 # average overall mshr miss latency 1555system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency 1556system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138 # average ReadReq mshr uncacheable latency 1557system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442 # average ReadReq mshr uncacheable latency 1558system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency 1559system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141 # average overall mshr uncacheable latency 1560system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930 # average overall mshr uncacheable latency 1561system.cpu0.toL2Bus.snoop_filter.tot_requests 4083931 # Total number of requests made to the snoop filter. 1562system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2062737 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1563system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1564system.cpu0.toL2Bus.snoop_filter.tot_snoops 216422 # Total number of snoops made to the snoop filter. 1565system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 214567 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1566system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1567system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1568system.cpu0.toL2Bus.trans_dist::ReadReq 102316 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::ReadResp 1901889 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::WriteReq 19032 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::WriteResp 19032 # Transaction distribution 1572system.cpu0.toL2Bus.trans_dist::WritebackDirty 714747 # Transaction distribution 1573system.cpu0.toL2Bus.trans_dist::WritebackClean 1482534 # Transaction distribution 1574system.cpu0.toL2Bus.trans_dist::CleanEvict 90142 # Transaction distribution 1575system.cpu0.toL2Bus.trans_dist::HardPFReq 335134 # Transaction distribution 1576system.cpu0.toL2Bus.trans_dist::UpgradeReq 87548 # Transaction distribution 1577system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42677 # Transaction distribution 1578system.cpu0.toL2Bus.trans_dist::UpgradeResp 113494 # Transaction distribution 1579system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution 1580system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution 1581system.cpu0.toL2Bus.trans_dist::ReadExReq 288350 # Transaction distribution 1582system.cpu0.toL2Bus.trans_dist::ReadExResp 285091 # Transaction distribution 1583system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1255148 # Transaction distribution 1584system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586492 # Transaction distribution 1585system.cpu0.toL2Bus.trans_dist::InvalidateReq 3253 # Transaction distribution 1586system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3770830 # Packet count per connected master and slave (bytes) 1587system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2574893 # Packet count per connected master and slave (bytes) 1588system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29200 # Packet count per connected master and slave (bytes) 1589system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119227 # Packet count per connected master and slave (bytes) 1590system.cpu0.toL2Bus.pkt_count::total 6494150 # Packet count per connected master and slave (bytes) 1591system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160667312 # Cumulative packet size per connected master and slave (bytes) 1592system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98708808 # Cumulative packet size per connected master and slave (bytes) 1593system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53624 # Cumulative packet size per connected master and slave (bytes) 1594system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 224224 # Cumulative packet size per connected master and slave (bytes) 1595system.cpu0.toL2Bus.pkt_size::total 259653968 # Cumulative packet size per connected master and slave (bytes) 1596system.cpu0.toL2Bus.snoops 933771 # Total snoops (count) 1597system.cpu0.toL2Bus.snoopTraffic 18925704 # Total snoop traffic (bytes) 1598system.cpu0.toL2Bus.snoop_fanout::samples 3041721 # Request fanout histogram 1599system.cpu0.toL2Bus.snoop_fanout::mean 0.089004 # Request fanout histogram 1600system.cpu0.toL2Bus.snoop_fanout::stdev 0.286883 # Request fanout histogram | 1526system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231756 # mshr miss rate for overall accesses 1527system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average ReadReq mshr miss latency 1528system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average ReadReq mshr miss latency 1529system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22466.666667 # average ReadReq mshr miss latency 1530system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average HardPFReq mshr miss latency 1531system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66098.421047 # average HardPFReq mshr miss latency 1532system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.843753 # average UpgradeReq mshr miss latency 1533system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.843753 # average UpgradeReq mshr miss latency 1534system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15088.941185 # average SCUpgradeReq mshr miss latency 1535system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15088.941185 # average SCUpgradeReq mshr miss latency 1536system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1537system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1538system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52429.478915 # average ReadExReq mshr miss latency 1539system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52429.478915 # average ReadExReq mshr miss latency 1540system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average ReadCleanReq mshr miss latency 1541system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47251.752048 # average ReadCleanReq mshr miss latency 1542system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26304.300160 # average ReadSharedReq mshr miss latency 1543system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26304.300160 # average ReadSharedReq mshr miss latency 1544system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency 1545system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency 1546system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency 1547system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency 1548system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38054.574604 # average overall mshr miss latency 1549system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency 1550system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency 1551system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency 1552system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency 1553system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average overall mshr miss latency 1554system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53283.753527 # average overall mshr miss latency 1555system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency 1556system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200414.826002 # average ReadReq mshr uncacheable latency 1557system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190706.237425 # average ReadReq mshr uncacheable latency 1558system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency 1559system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105738.541476 # average overall mshr uncacheable latency 1560system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104900.943918 # average overall mshr uncacheable latency 1561system.cpu0.toL2Bus.snoop_filter.tot_requests 4079155 # Total number of requests made to the snoop filter. 1562system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2060991 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1563system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31388 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1564system.cpu0.toL2Bus.snoop_filter.tot_snoops 213571 # Total number of snoops made to the snoop filter. 1565system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 211819 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1566system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1752 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1567system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1568system.cpu0.toL2Bus.trans_dist::ReadReq 114320 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::ReadResp 1911393 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::WriteReq 28457 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::WriteResp 28457 # Transaction distribution 1572system.cpu0.toL2Bus.trans_dist::WritebackDirty 712151 # Transaction distribution 1573system.cpu0.toL2Bus.trans_dist::WritebackClean 1482098 # Transaction distribution 1574system.cpu0.toL2Bus.trans_dist::CleanEvict 89271 # Transaction distribution 1575system.cpu0.toL2Bus.trans_dist::HardPFReq 330960 # Transaction distribution 1576system.cpu0.toL2Bus.trans_dist::UpgradeReq 87226 # Transaction distribution 1577system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42590 # Transaction distribution 1578system.cpu0.toL2Bus.trans_dist::UpgradeResp 113358 # Transaction distribution 1579system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution 1580system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution 1581system.cpu0.toL2Bus.trans_dist::ReadExReq 287646 # Transaction distribution 1582system.cpu0.toL2Bus.trans_dist::ReadExResp 284122 # Transaction distribution 1583system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1252747 # Transaction distribution 1584system.cpu0.toL2Bus.trans_dist::ReadSharedReq 585259 # Transaction distribution 1585system.cpu0.toL2Bus.trans_dist::InvalidateReq 3214 # Transaction distribution 1586system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3763658 # Packet count per connected master and slave (bytes) 1587system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2614734 # Packet count per connected master and slave (bytes) 1588system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29156 # Packet count per connected master and slave (bytes) 1589system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119485 # Packet count per connected master and slave (bytes) 1590system.cpu0.toL2Bus.pkt_count::total 6527033 # Packet count per connected master and slave (bytes) 1591system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160361408 # Cumulative packet size per connected master and slave (bytes) 1592system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98721444 # Cumulative packet size per connected master and slave (bytes) 1593system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53072 # Cumulative packet size per connected master and slave (bytes) 1594system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223432 # Cumulative packet size per connected master and slave (bytes) 1595system.cpu0.toL2Bus.pkt_size::total 259359356 # Cumulative packet size per connected master and slave (bytes) 1596system.cpu0.toL2Bus.snoops 926756 # Total snoops (count) 1597system.cpu0.toL2Bus.snoopTraffic 18862496 # Total snoop traffic (bytes) 1598system.cpu0.toL2Bus.snoop_fanout::samples 3052726 # Request fanout histogram 1599system.cpu0.toL2Bus.snoop_fanout::mean 0.087981 # Request fanout histogram 1600system.cpu0.toL2Bus.snoop_fanout::stdev 0.285286 # Request fanout histogram |
| 1601system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1601system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1602system.cpu0.toL2Bus.snoop_fanout::0 2772852 91.16% 91.16% # Request fanout histogram 1603system.cpu0.toL2Bus.snoop_fanout::1 267014 8.78% 99.94% # Request fanout histogram 1604system.cpu0.toL2Bus.snoop_fanout::2 1855 0.06% 100.00% # Request fanout histogram | 1602system.cpu0.toL2Bus.snoop_fanout::0 2785896 91.26% 91.26% # Request fanout histogram 1603system.cpu0.toL2Bus.snoop_fanout::1 265078 8.68% 99.94% # Request fanout histogram 1604system.cpu0.toL2Bus.snoop_fanout::2 1752 0.06% 100.00% # Request fanout histogram |
| 1605system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1606system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1607system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1605system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1606system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1607system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1608system.cpu0.toL2Bus.snoop_fanout::total 3041721 # Request fanout histogram 1609system.cpu0.toL2Bus.reqLayer0.occupancy 4067278494 # Layer occupancy (ticks) | 1608system.cpu0.toL2Bus.snoop_fanout::total 3052726 # Request fanout histogram 1609system.cpu0.toL2Bus.reqLayer0.occupancy 4077518993 # Layer occupancy (ticks) |
| 1610system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1610system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1611system.cpu0.toL2Bus.snoopLayer0.occupancy 114026414 # Layer occupancy (ticks) | 1611system.cpu0.toL2Bus.snoopLayer0.occupancy 113316466 # Layer occupancy (ticks) |
| 1612system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1612system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1613system.cpu0.toL2Bus.respLayer0.occupancy 1886176090 # Layer occupancy (ticks) | 1613system.cpu0.toL2Bus.respLayer0.occupancy 1882577097 # Layer occupancy (ticks) |
| 1614system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1614system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1615system.cpu0.toL2Bus.respLayer1.occupancy 1218391120 # Layer occupancy (ticks) | 1615system.cpu0.toL2Bus.respLayer1.occupancy 1233739845 # Layer occupancy (ticks) |
| 1616system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1616system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1617system.cpu0.toL2Bus.respLayer2.occupancy 15802982 # Layer occupancy (ticks) | 1617system.cpu0.toL2Bus.respLayer2.occupancy 15895485 # Layer occupancy (ticks) |
| 1618system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1618system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1619system.cpu0.toL2Bus.respLayer3.occupancy 63205426 # Layer occupancy (ticks) | 1619system.cpu0.toL2Bus.respLayer3.occupancy 63655441 # Layer occupancy (ticks) |
| 1620system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1620system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1621system.cpu1.branchPred.lookups 33853439 # Number of BP lookups 1622system.cpu1.branchPred.condPredicted 11509465 # Number of conditional branches predicted 1623system.cpu1.branchPred.condIncorrect 280542 # Number of conditional branches incorrect 1624system.cpu1.branchPred.BTBLookups 18730917 # Number of BTB lookups 1625system.cpu1.branchPred.BTBHits 5987349 # Number of BTB hits | 1621system.cpu1.branchPred.lookups 4630228 # Number of BP lookups 1622system.cpu1.branchPred.condPredicted 2728889 # Number of conditional branches predicted 1623system.cpu1.branchPred.condIncorrect 266806 # Number of conditional branches incorrect 1624system.cpu1.branchPred.BTBLookups 2406642 # Number of BTB lookups 1625system.cpu1.branchPred.BTBHits 1541904 # Number of BTB hits |
| 1626system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1626system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1627system.cpu1.branchPred.BTBHitPct 31.965061 # BTB Hit Percentage 1628system.cpu1.branchPred.usedRAS 12496464 # Number of times the RAS was used to get a target. 1629system.cpu1.branchPred.RASInCorrect 7318 # Number of incorrect RAS predictions. 1630system.cpu1.branchPred.indirectLookups 9007806 # Number of indirect predictor lookups. 1631system.cpu1.branchPred.indirectHits 8970953 # Number of indirect target hits. 1632system.cpu1.branchPred.indirectMisses 36853 # Number of indirect misses. 1633system.cpu1.branchPredindirectMispredicted 10907 # Number of mispredicted indirect branches. 1634system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 1627system.cpu1.branchPred.BTBHitPct 64.068690 # BTB Hit Percentage 1628system.cpu1.branchPred.usedRAS 874664 # Number of times the RAS was used to get a target. 1629system.cpu1.branchPred.RASInCorrect 7405 # Number of incorrect RAS predictions. 1630system.cpu1.branchPred.indirectLookups 249240 # Number of indirect predictor lookups. 1631system.cpu1.branchPred.indirectHits 213278 # Number of indirect target hits. 1632system.cpu1.branchPred.indirectMisses 35962 # Number of indirect misses. 1633system.cpu1.branchPredindirectMispredicted 10619 # Number of mispredicted indirect branches. 1634system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 1635system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1641system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1642system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1656system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1657system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1658system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1659system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1660system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1661system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1662system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1663system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1635system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1641system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1642system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1656system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1657system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1658system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1659system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1660system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1661system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1662system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1663system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1664system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1665system.cpu1.dtb.walker.walks 21636 # Table walker walks requested 1666system.cpu1.dtb.walker.walksShort 21636 # Table walker walks initiated with short descriptors 1667system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8665 # Level at which table walker walks with short descriptors terminate 1668system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5933 # Level at which table walker walks with short descriptors terminate 1669system.cpu1.dtb.walker.walksSquashedBefore 7038 # Table walks squashed before starting 1670system.cpu1.dtb.walker.walkWaitTime::samples 14598 # Table walker wait (enqueue to first request) latency 1671system.cpu1.dtb.walker.walkWaitTime::mean 649.780792 # Table walker wait (enqueue to first request) latency 1672system.cpu1.dtb.walker.walkWaitTime::stdev 3376.631612 # Table walker wait (enqueue to first request) latency 1673system.cpu1.dtb.walker.walkWaitTime::0-4095 13908 95.27% 95.27% # Table walker wait (enqueue to first request) latency 1674system.cpu1.dtb.walker.walkWaitTime::4096-8191 186 1.27% 96.55% # Table walker wait (enqueue to first request) latency 1675system.cpu1.dtb.walker.walkWaitTime::8192-12287 234 1.60% 98.15% # Table walker wait (enqueue to first request) latency 1676system.cpu1.dtb.walker.walkWaitTime::12288-16383 108 0.74% 98.89% # Table walker wait (enqueue to first request) latency 1677system.cpu1.dtb.walker.walkWaitTime::16384-20479 46 0.32% 99.21% # Table walker wait (enqueue to first request) latency 1678system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.21% 99.41% # Table walker wait (enqueue to first request) latency 1679system.cpu1.dtb.walker.walkWaitTime::24576-28671 8 0.05% 99.47% # Table walker wait (enqueue to first request) latency 1680system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.92% # Table walker wait (enqueue to first request) latency 1681system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency 1682system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency 1683system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency | 1664system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1665system.cpu1.dtb.walker.walks 21137 # Table walker walks requested 1666system.cpu1.dtb.walker.walksShort 21137 # Table walker walks initiated with short descriptors 1667system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8393 # Level at which table walker walks with short descriptors terminate 1668system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5852 # Level at which table walker walks with short descriptors terminate 1669system.cpu1.dtb.walker.walksSquashedBefore 6892 # Table walks squashed before starting 1670system.cpu1.dtb.walker.walkWaitTime::samples 14245 # Table walker wait (enqueue to first request) latency 1671system.cpu1.dtb.walker.walkWaitTime::mean 645.419445 # Table walker wait (enqueue to first request) latency 1672system.cpu1.dtb.walker.walkWaitTime::stdev 3393.467484 # Table walker wait (enqueue to first request) latency 1673system.cpu1.dtb.walker.walkWaitTime::0-4095 13571 95.27% 95.27% # Table walker wait (enqueue to first request) latency 1674system.cpu1.dtb.walker.walkWaitTime::4096-8191 196 1.38% 96.64% # Table walker wait (enqueue to first request) latency 1675system.cpu1.dtb.walker.walkWaitTime::8192-12287 230 1.61% 98.26% # Table walker wait (enqueue to first request) latency 1676system.cpu1.dtb.walker.walkWaitTime::12288-16383 102 0.72% 98.98% # Table walker wait (enqueue to first request) latency 1677system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.20% 99.17% # Table walker wait (enqueue to first request) latency 1678system.cpu1.dtb.walker.walkWaitTime::20480-24575 27 0.19% 99.36% # Table walker wait (enqueue to first request) latency 1679system.cpu1.dtb.walker.walkWaitTime::24576-28671 10 0.07% 99.43% # Table walker wait (enqueue to first request) latency 1680system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.45% 99.88% # Table walker wait (enqueue to first request) latency 1681system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.92% # Table walker wait (enqueue to first request) latency 1682system.cpu1.dtb.walker.walkWaitTime::36864-40959 10 0.07% 99.99% # Table walker wait (enqueue to first request) latency |
| 1684system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency | 1683system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency |
| 1685system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1686system.cpu1.dtb.walker.walkWaitTime::total 14598 # Table walker wait (enqueue to first request) latency 1687system.cpu1.dtb.walker.walkCompletionTime::samples 5531 # Table walker service (enqueue to completion) latency 1688system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712 # Table walker service (enqueue to completion) latency 1689system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860 # Table walker service (enqueue to completion) latency 1690system.cpu1.dtb.walker.walkCompletionTime::stdev 6336.393968 # Table walker service (enqueue to completion) latency 1691system.cpu1.dtb.walker.walkCompletionTime::0-8191 1833 33.14% 33.14% # Table walker service (enqueue to completion) latency 1692system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3041 54.98% 88.12% # Table walker service (enqueue to completion) latency 1693system.cpu1.dtb.walker.walkCompletionTime::16384-24575 457 8.26% 96.38% # Table walker service (enqueue to completion) latency 1694system.cpu1.dtb.walker.walkCompletionTime::24576-32767 138 2.50% 98.88% # Table walker service (enqueue to completion) latency 1695system.cpu1.dtb.walker.walkCompletionTime::32768-40959 31 0.56% 99.44% # Table walker service (enqueue to completion) latency 1696system.cpu1.dtb.walker.walkCompletionTime::40960-49151 23 0.42% 99.86% # Table walker service (enqueue to completion) latency 1697system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.93% # Table walker service (enqueue to completion) latency 1698system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.96% # Table walker service (enqueue to completion) latency 1699system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 1700system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1701system.cpu1.dtb.walker.walkCompletionTime::total 5531 # Table walker service (enqueue to completion) latency 1702system.cpu1.dtb.walker.walksPending::samples 68460974968 # Table walker pending requests distribution 1703system.cpu1.dtb.walker.walksPending::mean 0.179525 # Table walker pending requests distribution 1704system.cpu1.dtb.walker.walksPending::stdev 0.388721 # Table walker pending requests distribution 1705system.cpu1.dtb.walker.walksPending::0-1 68438733968 99.97% 99.97% # Table walker pending requests distribution 1706system.cpu1.dtb.walker.walksPending::2-3 17027000 0.02% 99.99% # Table walker pending requests distribution 1707system.cpu1.dtb.walker.walksPending::4-5 2383000 0.00% 100.00% # Table walker pending requests distribution 1708system.cpu1.dtb.walker.walksPending::6-7 1817500 0.00% 100.00% # Table walker pending requests distribution 1709system.cpu1.dtb.walker.walksPending::8-9 437500 0.00% 100.00% # Table walker pending requests distribution 1710system.cpu1.dtb.walker.walksPending::10-11 205000 0.00% 100.00% # Table walker pending requests distribution 1711system.cpu1.dtb.walker.walksPending::12-13 153500 0.00% 100.00% # Table walker pending requests distribution 1712system.cpu1.dtb.walker.walksPending::14-15 216500 0.00% 100.00% # Table walker pending requests distribution 1713system.cpu1.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution 1714system.cpu1.dtb.walker.walksPending::total 68460974968 # Table walker pending requests distribution 1715system.cpu1.dtb.walker.walkPageSizes::4K 1927 75.51% 75.51% # Table walker page sizes translated 1716system.cpu1.dtb.walker.walkPageSizes::1M 625 24.49% 100.00% # Table walker page sizes translated 1717system.cpu1.dtb.walker.walkPageSizes::total 2552 # Table walker page sizes translated 1718system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21636 # Table walker requests started/completed, data/inst | 1684system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1685system.cpu1.dtb.walker.walkWaitTime::total 14245 # Table walker wait (enqueue to first request) latency 1686system.cpu1.dtb.walker.walkCompletionTime::samples 5483 # Table walker service (enqueue to completion) latency 1687system.cpu1.dtb.walker.walkCompletionTime::mean 11374.338866 # Table walker service (enqueue to completion) latency 1688system.cpu1.dtb.walker.walkCompletionTime::gmean 9975.216104 # Table walker service (enqueue to completion) latency 1689system.cpu1.dtb.walker.walkCompletionTime::stdev 6340.433585 # Table walker service (enqueue to completion) latency 1690system.cpu1.dtb.walker.walkCompletionTime::0-8191 1893 34.52% 34.52% # Table walker service (enqueue to completion) latency 1691system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2927 53.38% 87.91% # Table walker service (enqueue to completion) latency 1692system.cpu1.dtb.walker.walkCompletionTime::16384-24575 431 7.86% 95.77% # Table walker service (enqueue to completion) latency 1693system.cpu1.dtb.walker.walkCompletionTime::24576-32767 169 3.08% 98.85% # Table walker service (enqueue to completion) latency 1694system.cpu1.dtb.walker.walkCompletionTime::32768-40959 33 0.60% 99.45% # Table walker service (enqueue to completion) latency 1695system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.44% 99.89% # Table walker service (enqueue to completion) latency 1696system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.98% # Table walker service (enqueue to completion) latency 1697system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1698system.cpu1.dtb.walker.walkCompletionTime::total 5483 # Table walker service (enqueue to completion) latency 1699system.cpu1.dtb.walker.walksPending::samples 77531116060 # Table walker pending requests distribution 1700system.cpu1.dtb.walker.walksPending::mean 0.220578 # Table walker pending requests distribution 1701system.cpu1.dtb.walker.walksPending::stdev 0.418371 # Table walker pending requests distribution 1702system.cpu1.dtb.walker.walksPending::0 60476667848 78.00% 78.00% # Table walker pending requests distribution 1703system.cpu1.dtb.walker.walksPending::1 17032378712 21.97% 99.97% # Table walker pending requests distribution 1704system.cpu1.dtb.walker.walksPending::2 12865500 0.02% 99.99% # Table walker pending requests distribution 1705system.cpu1.dtb.walker.walksPending::3 4248000 0.01% 99.99% # Table walker pending requests distribution 1706system.cpu1.dtb.walker.walksPending::4 1183000 0.00% 100.00% # Table walker pending requests distribution 1707system.cpu1.dtb.walker.walksPending::5 1086000 0.00% 100.00% # Table walker pending requests distribution 1708system.cpu1.dtb.walker.walksPending::6 1322500 0.00% 100.00% # Table walker pending requests distribution 1709system.cpu1.dtb.walker.walksPending::7 461500 0.00% 100.00% # Table walker pending requests distribution 1710system.cpu1.dtb.walker.walksPending::8 217000 0.00% 100.00% # Table walker pending requests distribution 1711system.cpu1.dtb.walker.walksPending::9 174500 0.00% 100.00% # Table walker pending requests distribution 1712system.cpu1.dtb.walker.walksPending::10 136000 0.00% 100.00% # Table walker pending requests distribution 1713system.cpu1.dtb.walker.walksPending::11 33500 0.00% 100.00% # Table walker pending requests distribution 1714system.cpu1.dtb.walker.walksPending::12 198000 0.00% 100.00% # Table walker pending requests distribution 1715system.cpu1.dtb.walker.walksPending::13 27000 0.00% 100.00% # Table walker pending requests distribution 1716system.cpu1.dtb.walker.walksPending::14 21000 0.00% 100.00% # Table walker pending requests distribution 1717system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution 1718system.cpu1.dtb.walker.walksPending::total 77531116060 # Table walker pending requests distribution 1719system.cpu1.dtb.walker.walkPageSizes::4K 1915 74.80% 74.80% # Table walker page sizes translated 1720system.cpu1.dtb.walker.walkPageSizes::1M 645 25.20% 100.00% # Table walker page sizes translated 1721system.cpu1.dtb.walker.walkPageSizes::total 2560 # Table walker page sizes translated 1722system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21137 # Table walker requests started/completed, data/inst |
| 1719system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1723system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1720system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21636 # Table walker requests started/completed, data/inst 1721system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2552 # Table walker requests started/completed, data/inst | 1724system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21137 # Table walker requests started/completed, data/inst 1725system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2560 # Table walker requests started/completed, data/inst |
| 1722system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1726system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1723system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2552 # Table walker requests started/completed, data/inst 1724system.cpu1.dtb.walker.walkRequestOrigin::total 24188 # Table walker requests started/completed, data/inst | 1727system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2560 # Table walker requests started/completed, data/inst 1728system.cpu1.dtb.walker.walkRequestOrigin::total 23697 # Table walker requests started/completed, data/inst |
| 1725system.cpu1.dtb.inst_hits 0 # ITB inst hits 1726system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1729system.cpu1.dtb.inst_hits 0 # ITB inst hits 1730system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1727system.cpu1.dtb.read_hits 10130487 # DTB read hits 1728system.cpu1.dtb.read_misses 18672 # DTB read misses 1729system.cpu1.dtb.write_hits 6476473 # DTB write hits 1730system.cpu1.dtb.write_misses 2964 # DTB write misses | 1731system.cpu1.dtb.read_hits 4149269 # DTB read hits 1732system.cpu1.dtb.read_misses 18244 # DTB read misses 1733system.cpu1.dtb.write_hits 3464998 # DTB write hits 1734system.cpu1.dtb.write_misses 2893 # DTB write misses |
| 1731system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1732system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1733system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1734system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1735system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1736system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1737system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1738system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1735system.cpu1.dtb.flush_entries 1961 # Number of entries that have been flushed from TLB 1736system.cpu1.dtb.align_faults 63 # Number of TLB faults due to alignment restrictions 1737system.cpu1.dtb.prefetch_faults 385 # Number of TLB faults due to prefetch | 1739system.cpu1.dtb.flush_entries 1955 # Number of entries that have been flushed from TLB 1740system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions 1741system.cpu1.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch |
| 1738system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1742system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1739system.cpu1.dtb.perms_faults 370 # Number of TLB faults due to permissions restrictions 1740system.cpu1.dtb.read_accesses 10149159 # DTB read accesses 1741system.cpu1.dtb.write_accesses 6479437 # DTB write accesses | 1743system.cpu1.dtb.perms_faults 410 # Number of TLB faults due to permissions restrictions 1744system.cpu1.dtb.read_accesses 4167513 # DTB read accesses 1745system.cpu1.dtb.write_accesses 3467891 # DTB write accesses |
| 1742system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1746system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1743system.cpu1.dtb.hits 16606960 # DTB hits 1744system.cpu1.dtb.misses 21636 # DTB misses 1745system.cpu1.dtb.accesses 16628596 # DTB accesses 1746system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 1747system.cpu1.dtb.hits 7614267 # DTB hits 1748system.cpu1.dtb.misses 21137 # DTB misses 1749system.cpu1.dtb.accesses 7635404 # DTB accesses 1750system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 1747system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1748system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1749system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1750system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1751system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1752system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1753system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1754system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1768system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1769system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1770system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1771system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1772system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1773system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1774system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1775system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1751system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1752system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1753system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1754system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1755system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1756system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1757system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1758system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1772system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1773system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1774system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1775system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1776system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1777system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1778system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1779system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1776system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 1777system.cpu1.itb.walker.walks 6064 # Table walker walks requested 1778system.cpu1.itb.walker.walksShort 6064 # Table walker walks initiated with short descriptors 1779system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2840 # Level at which table walker walks with short descriptors terminate 1780system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2623 # Level at which table walker walks with short descriptors terminate 1781system.cpu1.itb.walker.walksSquashedBefore 601 # Table walks squashed before starting 1782system.cpu1.itb.walker.walkWaitTime::samples 5463 # Table walker wait (enqueue to first request) latency 1783system.cpu1.itb.walker.walkWaitTime::mean 343.950211 # Table walker wait (enqueue to first request) latency 1784system.cpu1.itb.walker.walkWaitTime::stdev 2166.504505 # Table walker wait (enqueue to first request) latency 1785system.cpu1.itb.walker.walkWaitTime::0-4095 5312 97.24% 97.24% # Table walker wait (enqueue to first request) latency 1786system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.04% 98.28% # Table walker wait (enqueue to first request) latency 1787system.cpu1.itb.walker.walkWaitTime::8192-12287 43 0.79% 99.07% # Table walker wait (enqueue to first request) latency 1788system.cpu1.itb.walker.walkWaitTime::12288-16383 29 0.53% 99.60% # Table walker wait (enqueue to first request) latency 1789system.cpu1.itb.walker.walkWaitTime::16384-20479 6 0.11% 99.71% # Table walker wait (enqueue to first request) latency 1790system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.09% 99.80% # Table walker wait (enqueue to first request) latency 1791system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.89% # Table walker wait (enqueue to first request) latency 1792system.cpu1.itb.walker.walkWaitTime::28672-32767 5 0.09% 99.98% # Table walker wait (enqueue to first request) latency 1793system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1794system.cpu1.itb.walker.walkWaitTime::total 5463 # Table walker wait (enqueue to first request) latency 1795system.cpu1.itb.walker.walkCompletionTime::samples 1764 # Table walker service (enqueue to completion) latency 1796system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844 # Table walker service (enqueue to completion) latency 1797system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882 # Table walker service (enqueue to completion) latency 1798system.cpu1.itb.walker.walkCompletionTime::stdev 5636.944380 # Table walker service (enqueue to completion) latency 1799system.cpu1.itb.walker.walkCompletionTime::0-8191 277 15.70% 15.70% # Table walker service (enqueue to completion) latency 1800system.cpu1.itb.walker.walkCompletionTime::8192-16383 1298 73.58% 89.29% # Table walker service (enqueue to completion) latency 1801system.cpu1.itb.walker.walkCompletionTime::16384-24575 111 6.29% 95.58% # Table walker service (enqueue to completion) latency 1802system.cpu1.itb.walker.walkCompletionTime::24576-32767 59 3.34% 98.92% # Table walker service (enqueue to completion) latency 1803system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.51% 99.43% # Table walker service (enqueue to completion) latency 1804system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.40% 99.83% # Table walker service (enqueue to completion) latency 1805system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.11% 99.94% # Table walker service (enqueue to completion) latency | 1780system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 1781system.cpu1.itb.walker.walks 5745 # Table walker walks requested 1782system.cpu1.itb.walker.walksShort 5745 # Table walker walks initiated with short descriptors 1783system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2522 # Level at which table walker walks with short descriptors terminate 1784system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2644 # Level at which table walker walks with short descriptors terminate 1785system.cpu1.itb.walker.walksSquashedBefore 579 # Table walks squashed before starting 1786system.cpu1.itb.walker.walkWaitTime::samples 5166 # Table walker wait (enqueue to first request) latency 1787system.cpu1.itb.walker.walkWaitTime::mean 354.045683 # Table walker wait (enqueue to first request) latency 1788system.cpu1.itb.walker.walkWaitTime::stdev 2100.129090 # Table walker wait (enqueue to first request) latency 1789system.cpu1.itb.walker.walkWaitTime::0-2047 4967 96.15% 96.15% # Table walker wait (enqueue to first request) latency 1790system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.83% 96.98% # Table walker wait (enqueue to first request) latency 1791system.cpu1.itb.walker.walkWaitTime::4096-6143 47 0.91% 97.89% # Table walker wait (enqueue to first request) latency 1792system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.41% 98.30% # Table walker wait (enqueue to first request) latency 1793system.cpu1.itb.walker.walkWaitTime::8192-10239 19 0.37% 98.66% # Table walker wait (enqueue to first request) latency 1794system.cpu1.itb.walker.walkWaitTime::10240-12287 23 0.45% 99.11% # Table walker wait (enqueue to first request) latency 1795system.cpu1.itb.walker.walkWaitTime::12288-14335 19 0.37% 99.48% # Table walker wait (enqueue to first request) latency 1796system.cpu1.itb.walker.walkWaitTime::14336-16383 7 0.14% 99.61% # Table walker wait (enqueue to first request) latency 1797system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.12% 99.73% # Table walker wait (enqueue to first request) latency 1798system.cpu1.itb.walker.walkWaitTime::18432-20479 1 0.02% 99.75% # Table walker wait (enqueue to first request) latency 1799system.cpu1.itb.walker.walkWaitTime::20480-22527 4 0.08% 99.83% # Table walker wait (enqueue to first request) latency 1800system.cpu1.itb.walker.walkWaitTime::22528-24575 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency 1801system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.88% # Table walker wait (enqueue to first request) latency 1802system.cpu1.itb.walker.walkWaitTime::26624-28671 3 0.06% 99.94% # Table walker wait (enqueue to first request) latency 1803system.cpu1.itb.walker.walkWaitTime::28672-30719 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency 1804system.cpu1.itb.walker.walkWaitTime::total 5166 # Table walker wait (enqueue to first request) latency 1805system.cpu1.itb.walker.walkCompletionTime::samples 1734 # Table walker service (enqueue to completion) latency 1806system.cpu1.itb.walker.walkCompletionTime::mean 12119.088812 # Table walker service (enqueue to completion) latency 1807system.cpu1.itb.walker.walkCompletionTime::gmean 10982.617612 # Table walker service (enqueue to completion) latency 1808system.cpu1.itb.walker.walkCompletionTime::stdev 5990.262254 # Table walker service (enqueue to completion) latency 1809system.cpu1.itb.walker.walkCompletionTime::0-8191 321 18.51% 18.51% # Table walker service (enqueue to completion) latency 1810system.cpu1.itb.walker.walkCompletionTime::8192-16383 1223 70.53% 89.04% # Table walker service (enqueue to completion) latency 1811system.cpu1.itb.walker.walkCompletionTime::16384-24575 108 6.23% 95.27% # Table walker service (enqueue to completion) latency 1812system.cpu1.itb.walker.walkCompletionTime::24576-32767 58 3.34% 98.62% # Table walker service (enqueue to completion) latency 1813system.cpu1.itb.walker.walkCompletionTime::32768-40959 14 0.81% 99.42% # Table walker service (enqueue to completion) latency 1814system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.65% # Table walker service (enqueue to completion) latency 1815system.cpu1.itb.walker.walkCompletionTime::49152-57343 5 0.29% 99.94% # Table walker service (enqueue to completion) latency |
| 1806system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency | 1816system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency |
| 1807system.cpu1.itb.walker.walkCompletionTime::total 1764 # Table walker service (enqueue to completion) latency 1808system.cpu1.itb.walker.walksPending::samples 16901758916 # Table walker pending requests distribution 1809system.cpu1.itb.walker.walksPending::mean 0.861276 # Table walker pending requests distribution 1810system.cpu1.itb.walker.walksPending::stdev 0.345783 # Table walker pending requests distribution 1811system.cpu1.itb.walker.walksPending::0 2345411264 13.88% 13.88% # Table walker pending requests distribution 1812system.cpu1.itb.walker.walksPending::1 14555617152 86.12% 100.00% # Table walker pending requests distribution 1813system.cpu1.itb.walker.walksPending::2 730500 0.00% 100.00% # Table walker pending requests distribution 1814system.cpu1.itb.walker.walksPending::total 16901758916 # Table walker pending requests distribution 1815system.cpu1.itb.walker.walkPageSizes::4K 989 85.04% 85.04% # Table walker page sizes translated 1816system.cpu1.itb.walker.walkPageSizes::1M 174 14.96% 100.00% # Table walker page sizes translated 1817system.cpu1.itb.walker.walkPageSizes::total 1163 # Table walker page sizes translated | 1817system.cpu1.itb.walker.walkCompletionTime::total 1734 # Table walker service (enqueue to completion) latency 1818system.cpu1.itb.walker.walksPending::samples 17381208916 # Table walker pending requests distribution 1819system.cpu1.itb.walker.walksPending::mean 0.871345 # Table walker pending requests distribution 1820system.cpu1.itb.walker.walksPending::stdev 0.334946 # Table walker pending requests distribution 1821system.cpu1.itb.walker.walksPending::0 2236929264 12.87% 12.87% # Table walker pending requests distribution 1822system.cpu1.itb.walker.walksPending::1 15143532152 87.13% 100.00% # Table walker pending requests distribution 1823system.cpu1.itb.walker.walksPending::2 747500 0.00% 100.00% # Table walker pending requests distribution 1824system.cpu1.itb.walker.walksPending::total 17381208916 # Table walker pending requests distribution 1825system.cpu1.itb.walker.walkPageSizes::4K 985 85.28% 85.28% # Table walker page sizes translated 1826system.cpu1.itb.walker.walkPageSizes::1M 170 14.72% 100.00% # Table walker page sizes translated 1827system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated |
| 1818system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1828system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1819system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6064 # Table walker requests started/completed, data/inst 1820system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6064 # Table walker requests started/completed, data/inst | 1829system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5745 # Table walker requests started/completed, data/inst 1830system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5745 # Table walker requests started/completed, data/inst |
| 1821system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1831system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1822system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1163 # Table walker requests started/completed, data/inst 1823system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1163 # Table walker requests started/completed, data/inst 1824system.cpu1.itb.walker.walkRequestOrigin::total 7227 # Table walker requests started/completed, data/inst 1825system.cpu1.itb.inst_hits 43493383 # ITB inst hits 1826system.cpu1.itb.inst_misses 6064 # ITB inst misses | 1832system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst 1833system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst 1834system.cpu1.itb.walker.walkRequestOrigin::total 6900 # Table walker requests started/completed, data/inst 1835system.cpu1.itb.inst_hits 8164971 # ITB inst hits 1836system.cpu1.itb.inst_misses 5745 # ITB inst misses |
| 1827system.cpu1.itb.read_hits 0 # DTB read hits 1828system.cpu1.itb.read_misses 0 # DTB read misses 1829system.cpu1.itb.write_hits 0 # DTB write hits 1830system.cpu1.itb.write_misses 0 # DTB write misses 1831system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1832system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1833system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1834system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1837system.cpu1.itb.read_hits 0 # DTB read hits 1838system.cpu1.itb.read_misses 0 # DTB read misses 1839system.cpu1.itb.write_hits 0 # DTB write hits 1840system.cpu1.itb.write_misses 0 # DTB write misses 1841system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1842system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1843system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1844system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1835system.cpu1.itb.flush_entries 1129 # Number of entries that have been flushed from TLB | 1845system.cpu1.itb.flush_entries 1122 # Number of entries that have been flushed from TLB |
| 1836system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1837system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1838system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1846system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1847system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1848system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1839system.cpu1.itb.perms_faults 581 # Number of TLB faults due to permissions restrictions | 1849system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions |
| 1840system.cpu1.itb.read_accesses 0 # DTB read accesses 1841system.cpu1.itb.write_accesses 0 # DTB write accesses | 1850system.cpu1.itb.read_accesses 0 # DTB read accesses 1851system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1842system.cpu1.itb.inst_accesses 43499447 # ITB inst accesses 1843system.cpu1.itb.hits 43493383 # DTB hits 1844system.cpu1.itb.misses 6064 # DTB misses 1845system.cpu1.itb.accesses 43499447 # DTB accesses 1846system.cpu1.numPwrStateTransitions 5513 # Number of power state transitions 1847system.cpu1.pwrStateClkGateDist::samples 2757 # Distribution of time spent in the clock gated state 1848system.cpu1.pwrStateClkGateDist::mean 1005805033.413856 # Distribution of time spent in the clock gated state 1849system.cpu1.pwrStateClkGateDist::stdev 25768715425.209221 # Distribution of time spent in the clock gated state 1850system.cpu1.pwrStateClkGateDist::underflows 1955 70.91% 70.91% # Distribution of time spent in the clock gated state 1851system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.94% 99.85% # Distribution of time spent in the clock gated state 1852system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state | 1852system.cpu1.itb.inst_accesses 8170716 # ITB inst accesses 1853system.cpu1.itb.hits 8164971 # DTB hits 1854system.cpu1.itb.misses 5745 # DTB misses 1855system.cpu1.itb.accesses 8170716 # DTB accesses 1856system.cpu1.numPwrStateTransitions 5463 # Number of power state transitions 1857system.cpu1.pwrStateClkGateDist::samples 2732 # Distribution of time spent in the clock gated state 1858system.cpu1.pwrStateClkGateDist::mean 1028238405.084919 # Distribution of time spent in the clock gated state 1859system.cpu1.pwrStateClkGateDist::stdev 25963867647.326580 # Distribution of time spent in the clock gated state 1860system.cpu1.pwrStateClkGateDist::underflows 1944 71.16% 71.16% # Distribution of time spent in the clock gated state 1861system.cpu1.pwrStateClkGateDist::1000-5e+10 782 28.62% 99.78% # Distribution of time spent in the clock gated state 1862system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1863system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state |
| 1853system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1854system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1855system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state | 1864system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1865system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1866system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state |
| 1856system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 1857system.cpu1.pwrStateClkGateDist::max_value 959983620244 # Distribution of time spent in the clock gated state 1858system.cpu1.pwrStateClkGateDist::total 2757 # Distribution of time spent in the clock gated state 1859system.cpu1.pwrStateResidencyTicks::ON 53106605878 # Cumulative time (in ticks) in various power states 1860system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122 # Cumulative time (in ticks) in various power states 1861system.cpu1.numCycles 106214002 # number of cpu cycles simulated | 1867system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1868system.cpu1.pwrStateClkGateDist::max_value 959984033604 # Distribution of time spent in the clock gated state 1869system.cpu1.pwrStateClkGateDist::total 2732 # Distribution of time spent in the clock gated state 1870system.cpu1.pwrStateResidencyTicks::ON 17447601808 # Cumulative time (in ticks) in various power states 1871system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809147322692 # Cumulative time (in ticks) in various power states 1872system.cpu1.numCycles 34895980 # number of cpu cycles simulated |
| 1862system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1863system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1873system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1874system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1864system.cpu1.fetch.icacheStallCycles 10283907 # Number of cycles fetch is stalled on an Icache miss 1865system.cpu1.fetch.Insts 108683336 # Number of instructions fetch has processed 1866system.cpu1.fetch.Branches 33853439 # Number of branches that fetch encountered 1867system.cpu1.fetch.predictedBranches 27454766 # Number of branches that fetch has predicted taken 1868system.cpu1.fetch.Cycles 92513470 # Number of cycles fetch has run and was not squashing or blocked 1869system.cpu1.fetch.SquashCycles 3739662 # Number of cycles fetch has spent squashing 1870system.cpu1.fetch.TlbCycles 81877 # Number of cycles fetch has spent waiting for tlb 1871system.cpu1.fetch.MiscStallCycles 30058 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1872system.cpu1.fetch.PendingTrapStallCycles 180666 # Number of stall cycles due to pending traps 1873system.cpu1.fetch.PendingQuiesceStallCycles 303073 # Number of stall cycles due to pending quiesce instructions 1874system.cpu1.fetch.IcacheWaitRetryStallCycles 23077 # Number of stall cycles due to full MSHR 1875system.cpu1.fetch.CacheLines 43492215 # Number of cache lines fetched 1876system.cpu1.fetch.IcacheSquashes 108878 # Number of outstanding Icache misses that were squashed 1877system.cpu1.fetch.ItlbSquashes 2205 # Number of outstanding ITLB misses that were squashed 1878system.cpu1.fetch.rateDist::samples 105285959 # Number of instructions fetched each cycle (Total) 1879system.cpu1.fetch.rateDist::mean 1.278787 # Number of instructions fetched each cycle (Total) 1880system.cpu1.fetch.rateDist::stdev 1.339334 # Number of instructions fetched each cycle (Total) | 1875system.cpu1.fetch.icacheStallCycles 8706814 # Number of cycles fetch is stalled on an Icache miss 1876system.cpu1.fetch.Insts 24545743 # Number of instructions fetch has processed 1877system.cpu1.fetch.Branches 4630228 # Number of branches that fetch encountered 1878system.cpu1.fetch.predictedBranches 2629846 # Number of branches that fetch has predicted taken 1879system.cpu1.fetch.Cycles 24236084 # Number of cycles fetch has run and was not squashing or blocked 1880system.cpu1.fetch.SquashCycles 776070 # Number of cycles fetch has spent squashing 1881system.cpu1.fetch.TlbCycles 77763 # Number of cycles fetch has spent waiting for tlb 1882system.cpu1.fetch.MiscStallCycles 35252 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1883system.cpu1.fetch.PendingTrapStallCycles 165739 # Number of stall cycles due to pending traps 1884system.cpu1.fetch.PendingQuiesceStallCycles 299959 # Number of stall cycles due to pending quiesce instructions 1885system.cpu1.fetch.IcacheWaitRetryStallCycles 23654 # Number of stall cycles due to full MSHR 1886system.cpu1.fetch.CacheLines 8163829 # Number of cache lines fetched 1887system.cpu1.fetch.IcacheSquashes 107624 # Number of outstanding Icache misses that were squashed 1888system.cpu1.fetch.ItlbSquashes 2029 # Number of outstanding ITLB misses that were squashed 1889system.cpu1.fetch.rateDist::samples 33933300 # Number of instructions fetched each cycle (Total) 1890system.cpu1.fetch.rateDist::mean 0.881300 # Number of instructions fetched each cycle (Total) 1891system.cpu1.fetch.rateDist::stdev 1.218696 # Number of instructions fetched each cycle (Total) |
| 1881system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1892system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1882system.cpu1.fetch.rateDist::0 48617714 46.18% 46.18% # Number of instructions fetched each cycle (Total) 1883system.cpu1.fetch.rateDist::1 13927599 13.23% 59.41% # Number of instructions fetched each cycle (Total) 1884system.cpu1.fetch.rateDist::2 7511266 7.13% 66.54% # Number of instructions fetched each cycle (Total) 1885system.cpu1.fetch.rateDist::3 35229380 33.46% 100.00% # Number of instructions fetched each cycle (Total) | 1893system.cpu1.fetch.rateDist::0 20192419 59.51% 59.51% # Number of instructions fetched each cycle (Total) 1894system.cpu1.fetch.rateDist::1 4836103 14.25% 73.76% # Number of instructions fetched each cycle (Total) 1895system.cpu1.fetch.rateDist::2 1645003 4.85% 78.61% # Number of instructions fetched each cycle (Total) 1896system.cpu1.fetch.rateDist::3 7259775 21.39% 100.00% # Number of instructions fetched each cycle (Total) |
| 1886system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1887system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1888system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1897system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1898system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1899system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1889system.cpu1.fetch.rateDist::total 105285959 # Number of instructions fetched each cycle (Total) 1890system.cpu1.fetch.branchRate 0.318729 # Number of branch fetches per cycle 1891system.cpu1.fetch.rate 1.023249 # Number of inst fetches per cycle 1892system.cpu1.decode.IdleCycles 13161149 # Number of cycles decode is idle 1893system.cpu1.decode.BlockedCycles 62754723 # Number of cycles decode is blocked 1894system.cpu1.decode.RunCycles 26539387 # Number of cycles decode is running 1895system.cpu1.decode.UnblockCycles 1087783 # Number of cycles decode is unblocking 1896system.cpu1.decode.SquashCycles 1742917 # Number of cycles decode is squashing 1897system.cpu1.decode.BranchResolved 736717 # Number of times decode resolved a branch 1898system.cpu1.decode.BranchMispred 129511 # Number of times decode detected a branch misprediction 1899system.cpu1.decode.DecodedInsts 67619846 # Number of instructions handled by decode 1900system.cpu1.decode.SquashedInsts 1094387 # Number of squashed instructions handled by decode 1901system.cpu1.rename.SquashCycles 1742917 # Number of cycles rename is squashing 1902system.cpu1.rename.IdleCycles 17542611 # Number of cycles rename is idle 1903system.cpu1.rename.BlockCycles 2352209 # Number of cycles rename is blocking 1904system.cpu1.rename.serializeStallCycles 57806856 # count of cycles rename stalled for serializing inst 1905system.cpu1.rename.RunCycles 23225004 # Number of cycles rename is running 1906system.cpu1.rename.UnblockCycles 2616362 # Number of cycles rename is unblocking 1907system.cpu1.rename.RenamedInsts 54744976 # Number of instructions processed by rename 1908system.cpu1.rename.SquashedInsts 213737 # Number of squashed instructions processed by rename 1909system.cpu1.rename.ROBFullEvents 258070 # Number of times rename has blocked due to ROB full 1910system.cpu1.rename.IQFullEvents 37169 # Number of times rename has blocked due to IQ full 1911system.cpu1.rename.LQFullEvents 15433 # Number of times rename has blocked due to LQ full 1912system.cpu1.rename.SQFullEvents 1611507 # Number of times rename has blocked due to SQ full 1913system.cpu1.rename.RenamedOperands 54654605 # Number of destination operands rename has renamed 1914system.cpu1.rename.RenameLookups 258629758 # Number of register rename lookups that rename has made 1915system.cpu1.rename.int_rename_lookups 58168286 # Number of integer rename lookups | 1900system.cpu1.fetch.rateDist::total 33933300 # Number of instructions fetched each cycle (Total) 1901system.cpu1.fetch.branchRate 0.132687 # Number of branch fetches per cycle 1902system.cpu1.fetch.rate 0.703397 # Number of inst fetches per cycle 1903system.cpu1.decode.IdleCycles 7185713 # Number of cycles decode is idle 1904system.cpu1.decode.BlockedCycles 16755217 # Number of cycles decode is blocked 1905system.cpu1.decode.RunCycles 8648276 # Number of cycles decode is running 1906system.cpu1.decode.UnblockCycles 1081250 # Number of cycles decode is unblocking 1907system.cpu1.decode.SquashCycles 262844 # Number of cycles decode is squashing 1908system.cpu1.decode.BranchResolved 705359 # Number of times decode resolved a branch 1909system.cpu1.decode.BranchMispred 127834 # Number of times decode detected a branch misprediction 1910system.cpu1.decode.DecodedInsts 23145137 # Number of instructions handled by decode 1911system.cpu1.decode.SquashedInsts 1030723 # Number of squashed instructions handled by decode 1912system.cpu1.rename.SquashCycles 262844 # Number of cycles rename is squashing 1913system.cpu1.rename.IdleCycles 8592488 # Number of cycles rename is idle 1914system.cpu1.rename.BlockCycles 2388926 # Number of cycles rename is blocking 1915system.cpu1.rename.serializeStallCycles 11714810 # count of cycles rename stalled for serializing inst 1916system.cpu1.rename.RunCycles 8302740 # Number of cycles rename is running 1917system.cpu1.rename.UnblockCycles 2671492 # Number of cycles rename is unblocking 1918system.cpu1.rename.RenamedInsts 21985761 # Number of instructions processed by rename 1919system.cpu1.rename.SquashedInsts 184128 # Number of squashed instructions processed by rename 1920system.cpu1.rename.ROBFullEvents 260119 # Number of times rename has blocked due to ROB full 1921system.cpu1.rename.IQFullEvents 36299 # Number of times rename has blocked due to IQ full 1922system.cpu1.rename.LQFullEvents 16259 # Number of times rename has blocked due to LQ full 1923system.cpu1.rename.SQFullEvents 1667149 # Number of times rename has blocked due to SQ full 1924system.cpu1.rename.RenamedOperands 21955593 # Number of destination operands rename has renamed 1925system.cpu1.rename.RenameLookups 102445019 # Number of register rename lookups that rename has made 1926system.cpu1.rename.int_rename_lookups 25352022 # Number of integer rename lookups |
| 1916system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups | 1927system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups |
| 1917system.cpu1.rename.CommittedMaps 52142746 # Number of HB maps that are committed 1918system.cpu1.rename.UndoneMaps 2511859 # Number of HB maps that are undone due to squashing 1919system.cpu1.rename.serializingInsts 1875660 # count of serializing insts renamed 1920system.cpu1.rename.tempSerializingInsts 1802517 # count of temporary serializing insts renamed 1921system.cpu1.rename.skidInsts 13071586 # count of insts added to the skid buffer 1922system.cpu1.memDep0.insertedLoads 10382439 # Number of loads inserted to the mem dependence unit. 1923system.cpu1.memDep0.insertedStores 6812181 # Number of stores inserted to the mem dependence unit. 1924system.cpu1.memDep0.conflictingLoads 622946 # Number of conflicting loads. 1925system.cpu1.memDep0.conflictingStores 790955 # Number of conflicting stores. 1926system.cpu1.iq.iqInstsAdded 53883918 # Number of instructions added to the IQ (excludes non-spec) 1927system.cpu1.iq.iqNonSpecInstsAdded 580977 # Number of non-speculative instructions added to the IQ 1928system.cpu1.iq.iqInstsIssued 53654093 # Number of instructions issued 1929system.cpu1.iq.iqSquashedInstsIssued 93763 # Number of squashed instructions issued 1930system.cpu1.iq.iqSquashedInstsExamined 3608749 # Number of squashed instructions iterated over during squash; mainly for profiling 1931system.cpu1.iq.iqSquashedOperandsExamined 5111945 # Number of squashed operands that are examined and possibly removed from graph 1932system.cpu1.iq.iqSquashedNonSpecRemoved 44050 # Number of squashed non-spec instructions that were removed 1933system.cpu1.iq.issued_per_cycle::samples 105285959 # Number of insts issued each cycle 1934system.cpu1.iq.issued_per_cycle::mean 0.509603 # Number of insts issued each cycle 1935system.cpu1.iq.issued_per_cycle::stdev 0.847754 # Number of insts issued each cycle | 1928system.cpu1.rename.CommittedMaps 19598713 # Number of HB maps that are committed 1929system.cpu1.rename.UndoneMaps 2356880 # Number of HB maps that are undone due to squashing 1930system.cpu1.rename.serializingInsts 406325 # count of serializing insts renamed 1931system.cpu1.rename.tempSerializingInsts 333389 # count of temporary serializing insts renamed 1932system.cpu1.rename.skidInsts 2861472 # count of insts added to the skid buffer 1933system.cpu1.memDep0.insertedLoads 4400097 # Number of loads inserted to the mem dependence unit. 1934system.cpu1.memDep0.insertedStores 3772059 # Number of stores inserted to the mem dependence unit. 1935system.cpu1.memDep0.conflictingLoads 619281 # Number of conflicting loads. 1936system.cpu1.memDep0.conflictingStores 624174 # Number of conflicting stores. 1937system.cpu1.iq.iqInstsAdded 21175375 # Number of instructions added to the IQ (excludes non-spec) 1938system.cpu1.iq.iqNonSpecInstsAdded 559463 # Number of non-speculative instructions added to the IQ 1939system.cpu1.iq.iqInstsIssued 20999121 # Number of instructions issued 1940system.cpu1.iq.iqSquashedInstsIssued 90560 # Number of squashed instructions issued 1941system.cpu1.iq.iqSquashedInstsExamined 2005952 # Number of squashed instructions iterated over during squash; mainly for profiling 1942system.cpu1.iq.iqSquashedOperandsExamined 4627057 # Number of squashed operands that are examined and possibly removed from graph 1943system.cpu1.iq.iqSquashedNonSpecRemoved 43664 # Number of squashed non-spec instructions that were removed 1944system.cpu1.iq.issued_per_cycle::samples 33933300 # Number of insts issued each cycle 1945system.cpu1.iq.issued_per_cycle::mean 0.618835 # Number of insts issued each cycle 1946system.cpu1.iq.issued_per_cycle::stdev 0.947092 # Number of insts issued each cycle |
| 1936system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1947system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1937system.cpu1.iq.issued_per_cycle::0 72150462 68.53% 68.53% # Number of insts issued each cycle 1938system.cpu1.iq.issued_per_cycle::1 16497460 15.67% 84.20% # Number of insts issued each cycle 1939system.cpu1.iq.issued_per_cycle::2 13036209 12.38% 96.58% # Number of insts issued each cycle 1940system.cpu1.iq.issued_per_cycle::3 3323109 3.16% 99.74% # Number of insts issued each cycle 1941system.cpu1.iq.issued_per_cycle::4 278707 0.26% 100.00% # Number of insts issued each cycle 1942system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle | 1948system.cpu1.iq.issued_per_cycle::0 21549433 63.51% 63.51% # Number of insts issued each cycle 1949system.cpu1.iq.issued_per_cycle::1 6114741 18.02% 81.53% # Number of insts issued each cycle 1950system.cpu1.iq.issued_per_cycle::2 4178352 12.31% 93.84% # Number of insts issued each cycle 1951system.cpu1.iq.issued_per_cycle::3 1835426 5.41% 99.25% # Number of insts issued each cycle 1952system.cpu1.iq.issued_per_cycle::4 255342 0.75% 100.00% # Number of insts issued each cycle 1953system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle |
| 1943system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1944system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1945system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1946system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1947system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1948system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1954system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1955system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1956system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1957system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1958system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1959system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1949system.cpu1.iq.issued_per_cycle::total 105285959 # Number of insts issued each cycle | 1960system.cpu1.iq.issued_per_cycle::total 33933300 # Number of insts issued each cycle |
| 1950system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1961system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1951system.cpu1.iq.fu_full::IntAlu 2901953 45.47% 45.47% # attempts to use FU when none available 1952system.cpu1.iq.fu_full::IntMult 671 0.01% 45.48% # attempts to use FU when none available 1953system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.48% # attempts to use FU when none available 1954system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.48% # attempts to use FU when none available 1955system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.48% # attempts to use FU when none available 1956system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.48% # attempts to use FU when none available 1957system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.48% # attempts to use FU when none available 1958system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.48% # attempts to use FU when none available 1959system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.48% # attempts to use FU when none available 1960system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.48% # attempts to use FU when none available 1961system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.48% # attempts to use FU when none available 1962system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.48% # attempts to use FU when none available 1963system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.48% # attempts to use FU when none available 1964system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.48% # attempts to use FU when none available 1965system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.48% # attempts to use FU when none available 1966system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.48% # attempts to use FU when none available 1967system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.48% # attempts to use FU when none available 1968system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.48% # attempts to use FU when none available 1969system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.48% # attempts to use FU when none available 1970system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.48% # attempts to use FU when none available 1971system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.48% # attempts to use FU when none available 1972system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.48% # attempts to use FU when none available 1973system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.48% # attempts to use FU when none available 1974system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.48% # attempts to use FU when none available 1975system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.48% # attempts to use FU when none available 1976system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.48% # attempts to use FU when none available 1977system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.48% # attempts to use FU when none available 1978system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.48% # attempts to use FU when none available 1979system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.48% # attempts to use FU when none available 1980system.cpu1.iq.fu_full::MemRead 1666030 26.11% 71.59% # attempts to use FU when none available 1981system.cpu1.iq.fu_full::MemWrite 1813313 28.41% 100.00% # attempts to use FU when none available | 1962system.cpu1.iq.fu_full::IntAlu 1405486 29.50% 29.50% # attempts to use FU when none available 1963system.cpu1.iq.fu_full::IntMult 669 0.01% 29.52% # attempts to use FU when none available 1964system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.52% # attempts to use FU when none available 1965system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.52% # attempts to use FU when none available 1966system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.52% # attempts to use FU when none available 1967system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.52% # attempts to use FU when none available 1968system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.52% # attempts to use FU when none available 1969system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.52% # attempts to use FU when none available 1970system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.52% # attempts to use FU when none available 1971system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.52% # attempts to use FU when none available 1972system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.52% # attempts to use FU when none available 1973system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.52% # attempts to use FU when none available 1974system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.52% # attempts to use FU when none available 1975system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.52% # attempts to use FU when none available 1976system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.52% # attempts to use FU when none available 1977system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.52% # attempts to use FU when none available 1978system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.52% # attempts to use FU when none available 1979system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.52% # attempts to use FU when none available 1980system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.52% # attempts to use FU when none available 1981system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.52% # attempts to use FU when none available 1982system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.52% # attempts to use FU when none available 1983system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.52% # attempts to use FU when none available 1984system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.52% # attempts to use FU when none available 1985system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.52% # attempts to use FU when none available 1986system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.52% # attempts to use FU when none available 1987system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.52% # attempts to use FU when none available 1988system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.52% # attempts to use FU when none available 1989system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available 1990system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.52% # attempts to use FU when none available 1991system.cpu1.iq.fu_full::MemRead 1602534 33.64% 63.16% # attempts to use FU when none available 1992system.cpu1.iq.fu_full::MemWrite 1754875 36.84% 100.00% # attempts to use FU when none available |
| 1982system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1983system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1984system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued | 1993system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1994system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1995system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued |
| 1985system.cpu1.iq.FU_type_0::IntAlu 36596131 68.21% 68.21% # Type of FU issued 1986system.cpu1.iq.FU_type_0::IntMult 45838 0.09% 68.29% # Type of FU issued 1987system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued 1988system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued 1989system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued 1990system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued 1991system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued 1992system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued 1993system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued 1994system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued 1995system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued 1996system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued 1997system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued 1998system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued 1999system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued 2000system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued 2001system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued 2002system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued 2003system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued 2004system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued 2005system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.29% # Type of FU issued 2006system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued 2007system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.29% # Type of FU issued 2008system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.29% # Type of FU issued 2009system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued 2010system.cpu1.iq.FU_type_0::SimdFloatMisc 3311 0.01% 68.30% # Type of FU issued 2011system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued 2012system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued 2013system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued 2014system.cpu1.iq.FU_type_0::MemRead 10338451 19.27% 87.57% # Type of FU issued 2015system.cpu1.iq.FU_type_0::MemWrite 6670296 12.43% 100.00% # Type of FU issued | 1996system.cpu1.iq.FU_type_0::IntAlu 12960054 61.72% 61.72% # Type of FU issued 1997system.cpu1.iq.FU_type_0::IntMult 27621 0.13% 61.85% # Type of FU issued 1998system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.85% # Type of FU issued 1999system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.85% # Type of FU issued 2000system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.85% # Type of FU issued 2001system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.85% # Type of FU issued 2002system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.85% # Type of FU issued 2003system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.85% # Type of FU issued 2004system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.85% # Type of FU issued 2005system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.85% # Type of FU issued 2006system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.85% # Type of FU issued 2007system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.85% # Type of FU issued 2008system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.85% # Type of FU issued 2009system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.85% # Type of FU issued 2010system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.85% # Type of FU issued 2011system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.85% # Type of FU issued 2012system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.85% # Type of FU issued 2013system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.85% # Type of FU issued 2014system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.85% # Type of FU issued 2015system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.85% # Type of FU issued 2016system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.85% # Type of FU issued 2017system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.85% # Type of FU issued 2018system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.85% # Type of FU issued 2019system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.85% # Type of FU issued 2020system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.85% # Type of FU issued 2021system.cpu1.iq.FU_type_0::SimdFloatMisc 3265 0.02% 61.86% # Type of FU issued 2022system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued 2023system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued 2024system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued 2025system.cpu1.iq.FU_type_0::MemRead 4356029 20.74% 82.61% # Type of FU issued 2026system.cpu1.iq.FU_type_0::MemWrite 3652086 17.39% 100.00% # Type of FU issued |
| 2016system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2017system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2027system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2028system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2018system.cpu1.iq.FU_type_0::total 53654093 # Type of FU issued 2019system.cpu1.iq.rate 0.505151 # Inst issue rate 2020system.cpu1.iq.fu_busy_cnt 6381967 # FU busy when requested 2021system.cpu1.iq.fu_busy_rate 0.118947 # FU busy rate (busy events/executed inst) 2022system.cpu1.iq.int_inst_queue_reads 219063644 # Number of integer instruction queue reads 2023system.cpu1.iq.int_inst_queue_writes 58081406 # Number of integer instruction queue writes 2024system.cpu1.iq.int_inst_queue_wakeup_accesses 51689844 # Number of integer instruction queue wakeup accesses 2025system.cpu1.iq.fp_inst_queue_reads 6231 # Number of floating instruction queue reads 2026system.cpu1.iq.fp_inst_queue_writes 2072 # Number of floating instruction queue writes 2027system.cpu1.iq.fp_inst_queue_wakeup_accesses 1788 # Number of floating instruction queue wakeup accesses 2028system.cpu1.iq.int_alu_accesses 60031897 # Number of integer alu accesses 2029system.cpu1.iq.fp_alu_accesses 4097 # Number of floating point alu accesses 2030system.cpu1.iew.lsq.thread0.forwLoads 89933 # Number of loads that had data forwarded from stores | 2029system.cpu1.iq.FU_type_0::total 20999121 # Type of FU issued 2030system.cpu1.iq.rate 0.601763 # Inst issue rate 2031system.cpu1.iq.fu_busy_cnt 4763564 # FU busy when requested 2032system.cpu1.iq.fu_busy_rate 0.226846 # FU busy rate (busy events/executed inst) 2033system.cpu1.iq.int_inst_queue_reads 80779382 # Number of integer instruction queue reads 2034system.cpu1.iq.int_inst_queue_writes 23748142 # Number of integer instruction queue writes 2035system.cpu1.iq.int_inst_queue_wakeup_accesses 20541259 # Number of integer instruction queue wakeup accesses 2036system.cpu1.iq.fp_inst_queue_reads 6284 # Number of floating instruction queue reads 2037system.cpu1.iq.fp_inst_queue_writes 2076 # Number of floating instruction queue writes 2038system.cpu1.iq.fp_inst_queue_wakeup_accesses 1790 # Number of floating instruction queue wakeup accesses 2039system.cpu1.iq.int_alu_accesses 25758471 # Number of integer alu accesses 2040system.cpu1.iq.fp_alu_accesses 4148 # Number of floating point alu accesses 2041system.cpu1.iew.lsq.thread0.forwLoads 87109 # Number of loads that had data forwarded from stores |
| 2031system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2042system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2032system.cpu1.iew.lsq.thread0.squashedLoads 434041 # Number of loads squashed 2033system.cpu1.iew.lsq.thread0.ignoredResponses 639 # Number of memory responses ignored because the instruction is squashed 2034system.cpu1.iew.lsq.thread0.memOrderViolation 9872 # Number of memory ordering violations 2035system.cpu1.iew.lsq.thread0.squashedStores 275866 # Number of stores squashed | 2043system.cpu1.iew.lsq.thread0.squashedLoads 405898 # Number of loads squashed 2044system.cpu1.iew.lsq.thread0.ignoredResponses 640 # Number of memory responses ignored because the instruction is squashed 2045system.cpu1.iew.lsq.thread0.memOrderViolation 9457 # Number of memory ordering violations 2046system.cpu1.iew.lsq.thread0.squashedStores 249525 # Number of stores squashed |
| 2036system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2037system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2047system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2048system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2038system.cpu1.iew.lsq.thread0.rescheduledLoads 52151 # Number of loads that were rescheduled 2039system.cpu1.iew.lsq.thread0.cacheBlocked 77961 # Number of times an access to memory failed due to the cache being blocked | 2049system.cpu1.iew.lsq.thread0.rescheduledLoads 40585 # Number of loads that were rescheduled 2050system.cpu1.iew.lsq.thread0.cacheBlocked 76754 # Number of times an access to memory failed due to the cache being blocked |
| 2040system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2051system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2041system.cpu1.iew.iewSquashCycles 1742917 # Number of cycles IEW is squashing 2042system.cpu1.iew.iewBlockCycles 520776 # Number of cycles IEW is blocking 2043system.cpu1.iew.iewUnblockCycles 103336 # Number of cycles IEW is unblocking 2044system.cpu1.iew.iewDispatchedInsts 54505946 # Number of instructions dispatched to IQ | 2052system.cpu1.iew.iewSquashCycles 262844 # Number of cycles IEW is squashing 2053system.cpu1.iew.iewBlockCycles 543765 # Number of cycles IEW is blocking 2054system.cpu1.iew.iewUnblockCycles 103558 # Number of cycles IEW is unblocking 2055system.cpu1.iew.iewDispatchedInsts 21775845 # Number of instructions dispatched to IQ |
| 2045system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 2056system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 2046system.cpu1.iew.iewDispLoadInsts 10382439 # Number of dispatched load instructions 2047system.cpu1.iew.iewDispStoreInsts 6812181 # Number of dispatched store instructions 2048system.cpu1.iew.iewDispNonSpecInsts 296650 # Number of dispatched non-speculative instructions 2049system.cpu1.iew.iewIQFullEvents 7746 # Number of times the IQ has become full, causing a stall 2050system.cpu1.iew.iewLSQFullEvents 89089 # Number of times the LSQ has become full, causing a stall 2051system.cpu1.iew.memOrderViolationEvents 9872 # Number of memory order violations 2052system.cpu1.iew.predictedTakenIncorrect 44543 # Number of branches that were predicted taken incorrectly 2053system.cpu1.iew.predictedNotTakenIncorrect 120099 # Number of branches that were predicted not taken incorrectly 2054system.cpu1.iew.branchMispredicts 164642 # Number of branch mispredicts detected at execute 2055system.cpu1.iew.iewExecutedInsts 53411917 # Number of executed instructions 2056system.cpu1.iew.iewExecLoadInsts 10242028 # Number of load instructions executed 2057system.cpu1.iew.iewExecSquashedInsts 220561 # Number of squashed instructions skipped in execute | 2057system.cpu1.iew.iewDispLoadInsts 4400097 # Number of dispatched load instructions 2058system.cpu1.iew.iewDispStoreInsts 3772059 # Number of dispatched store instructions 2059system.cpu1.iew.iewDispNonSpecInsts 296163 # Number of dispatched non-speculative instructions 2060system.cpu1.iew.iewIQFullEvents 7694 # Number of times the IQ has become full, causing a stall 2061system.cpu1.iew.iewLSQFullEvents 88949 # Number of times the LSQ has become full, causing a stall 2062system.cpu1.iew.memOrderViolationEvents 9457 # Number of memory order violations 2063system.cpu1.iew.predictedTakenIncorrect 34239 # Number of branches that were predicted taken incorrectly 2064system.cpu1.iew.predictedNotTakenIncorrect 118390 # Number of branches that were predicted not taken incorrectly 2065system.cpu1.iew.branchMispredicts 152629 # Number of branch mispredicts detected at execute 2066system.cpu1.iew.iewExecutedInsts 20771745 # Number of executed instructions 2067system.cpu1.iew.iewExecLoadInsts 4261184 # Number of load instructions executed 2068system.cpu1.iew.iewExecSquashedInsts 206260 # Number of squashed instructions skipped in execute |
| 2058system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2069system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2059system.cpu1.iew.exec_nop 41051 # number of nop insts executed 2060system.cpu1.iew.exec_refs 16861277 # number of memory reference insts executed 2061system.cpu1.iew.exec_branches 11793508 # Number of branches executed 2062system.cpu1.iew.exec_stores 6619249 # Number of stores executed 2063system.cpu1.iew.exec_rate 0.502871 # Inst execution rate 2064system.cpu1.iew.wb_sent 53270244 # cumulative count of insts sent to commit 2065system.cpu1.iew.wb_count 51691632 # cumulative count of insts written-back 2066system.cpu1.iew.wb_producers 25129407 # num instructions producing a value 2067system.cpu1.iew.wb_consumers 38339279 # num instructions consuming a value 2068system.cpu1.iew.wb_rate 0.486674 # insts written-back per cycle 2069system.cpu1.iew.wb_fanout 0.655448 # average fanout of values written-back 2070system.cpu1.commit.commitSquashedInsts 3369485 # The number of squashed insts skipped by commit 2071system.cpu1.commit.commitNonSpecStalls 536927 # The number of times commit has been forced to stall to communicate backwards 2072system.cpu1.commit.branchMispredicts 153628 # The number of times a branch was mispredicted 2073system.cpu1.commit.committed_per_cycle::samples 103395222 # Number of insts commited each cycle 2074system.cpu1.commit.committed_per_cycle::mean 0.492179 # Number of insts commited each cycle 2075system.cpu1.commit.committed_per_cycle::stdev 1.152090 # Number of insts commited each cycle | 2070system.cpu1.iew.exec_nop 41007 # number of nop insts executed 2071system.cpu1.iew.exec_refs 7864490 # number of memory reference insts executed 2072system.cpu1.iew.exec_branches 3010595 # Number of branches executed 2073system.cpu1.iew.exec_stores 3603306 # Number of stores executed 2074system.cpu1.iew.exec_rate 0.595248 # Inst execution rate 2075system.cpu1.iew.wb_sent 20641556 # cumulative count of insts sent to commit 2076system.cpu1.iew.wb_count 20543049 # cumulative count of insts written-back 2077system.cpu1.iew.wb_producers 10275425 # num instructions producing a value 2078system.cpu1.iew.wb_consumers 16109782 # num instructions consuming a value 2079system.cpu1.iew.wb_rate 0.588694 # insts written-back per cycle 2080system.cpu1.iew.wb_fanout 0.637838 # average fanout of values written-back 2081system.cpu1.commit.commitSquashedInsts 1795274 # The number of squashed insts skipped by commit 2082system.cpu1.commit.commitNonSpecStalls 515799 # The number of times commit has been forced to stall to communicate backwards 2083system.cpu1.commit.branchMispredicts 141615 # The number of times a branch was mispredicted 2084system.cpu1.commit.committed_per_cycle::samples 33527734 # Number of insts commited each cycle 2085system.cpu1.commit.committed_per_cycle::mean 0.589415 # Number of insts commited each cycle 2086system.cpu1.commit.committed_per_cycle::stdev 1.349112 # Number of insts commited each cycle |
| 2076system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2087system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2077system.cpu1.commit.committed_per_cycle::0 77830115 75.27% 75.27% # Number of insts commited each cycle 2078system.cpu1.commit.committed_per_cycle::1 14293086 13.82% 89.10% # Number of insts commited each cycle 2079system.cpu1.commit.committed_per_cycle::2 6071280 5.87% 94.97% # Number of insts commited each cycle 2080system.cpu1.commit.committed_per_cycle::3 693599 0.67% 95.64% # Number of insts commited each cycle 2081system.cpu1.commit.committed_per_cycle::4 1980010 1.91% 97.56% # Number of insts commited each cycle 2082system.cpu1.commit.committed_per_cycle::5 1625143 1.57% 99.13% # Number of insts commited each cycle 2083system.cpu1.commit.committed_per_cycle::6 382099 0.37% 99.50% # Number of insts commited each cycle 2084system.cpu1.commit.committed_per_cycle::7 124911 0.12% 99.62% # Number of insts commited each cycle 2085system.cpu1.commit.committed_per_cycle::8 394979 0.38% 100.00% # Number of insts commited each cycle | 2088system.cpu1.commit.committed_per_cycle::0 24087304 71.84% 71.84% # Number of insts commited each cycle 2089system.cpu1.commit.committed_per_cycle::1 5545630 16.54% 88.38% # Number of insts commited each cycle 2090system.cpu1.commit.committed_per_cycle::2 1675188 5.00% 93.38% # Number of insts commited each cycle 2091system.cpu1.commit.committed_per_cycle::3 660381 1.97% 95.35% # Number of insts commited each cycle 2092system.cpu1.commit.committed_per_cycle::4 508267 1.52% 96.87% # Number of insts commited each cycle 2093system.cpu1.commit.committed_per_cycle::5 330740 0.99% 97.85% # Number of insts commited each cycle 2094system.cpu1.commit.committed_per_cycle::6 223183 0.67% 98.52% # Number of insts commited each cycle 2095system.cpu1.commit.committed_per_cycle::7 117603 0.35% 98.87% # Number of insts commited each cycle 2096system.cpu1.commit.committed_per_cycle::8 379438 1.13% 100.00% # Number of insts commited each cycle |
| 2086system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2087system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2088system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2097system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2098system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2099system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2089system.cpu1.commit.committed_per_cycle::total 103395222 # Number of insts commited each cycle 2090system.cpu1.commit.committedInsts 41318794 # Number of instructions committed 2091system.cpu1.commit.committedOps 50889001 # Number of ops (including micro ops) committed | 2100system.cpu1.commit.committed_per_cycle::total 33527734 # Number of insts commited each cycle 2101system.cpu1.commit.committedInsts 16118487 # Number of instructions committed 2102system.cpu1.commit.committedOps 19761740 # Number of ops (including micro ops) committed |
| 2092system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2103system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2093system.cpu1.commit.refs 16484713 # Number of memory references committed 2094system.cpu1.commit.loads 9948398 # Number of loads committed 2095system.cpu1.commit.membars 208127 # Number of memory barriers committed 2096system.cpu1.commit.branches 11637916 # Number of branches committed | 2104system.cpu1.commit.refs 7516733 # Number of memory references committed 2105system.cpu1.commit.loads 3994199 # Number of loads committed 2106system.cpu1.commit.membars 208310 # Number of memory barriers committed 2107system.cpu1.commit.branches 2858693 # Number of branches committed |
| 2097system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. | 2108system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. |
| 2098system.cpu1.commit.int_insts 45745086 # Number of committed integer instructions. 2099system.cpu1.commit.function_calls 3368055 # Number of function calls committed. | 2109system.cpu1.commit.int_insts 17575462 # Number of committed integer instructions. 2110system.cpu1.commit.function_calls 459876 # Number of function calls committed. |
| 2100system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 2111system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 2101system.cpu1.commit.op_class_0::IntAlu 34356210 67.51% 67.51% # Class of committed instruction 2102system.cpu1.commit.op_class_0::IntMult 44767 0.09% 67.60% # Class of committed instruction 2103system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction 2104system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction 2105system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction 2106system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction 2107system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction 2108system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction 2109system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction 2110system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction 2111system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction 2112system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction 2113system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction 2114system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction 2115system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction 2116system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction 2117system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction 2118system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction 2119system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction 2120system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction 2121system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction 2122system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction 2123system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction 2124system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction 2125system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction 2126system.cpu1.commit.op_class_0::SimdFloatMisc 3311 0.01% 67.61% # Class of committed instruction 2127system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.61% # Class of committed instruction 2128system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.61% # Class of committed instruction 2129system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.61% # Class of committed instruction 2130system.cpu1.commit.op_class_0::MemRead 9948398 19.55% 87.16% # Class of committed instruction 2131system.cpu1.commit.op_class_0::MemWrite 6536315 12.84% 100.00% # Class of committed instruction | 2112system.cpu1.commit.op_class_0::IntAlu 12215165 61.81% 61.81% # Class of committed instruction 2113system.cpu1.commit.op_class_0::IntMult 26577 0.13% 61.95% # Class of committed instruction 2114system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 2115system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 2116system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 2117system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 2118system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 2119system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 2120system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 2121system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 2122system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 2123system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 2124system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 2125system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 2126system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 2127system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 2128system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 2129system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 2130system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 2131system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 2132system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 2133system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 2134system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 2135system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 2136system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 2137system.cpu1.commit.op_class_0::SimdFloatMisc 3265 0.02% 61.96% # Class of committed instruction 2138system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.96% # Class of committed instruction 2139system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.96% # Class of committed instruction 2140system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.96% # Class of committed instruction 2141system.cpu1.commit.op_class_0::MemRead 3994199 20.21% 82.17% # Class of committed instruction 2142system.cpu1.commit.op_class_0::MemWrite 3522534 17.83% 100.00% # Class of committed instruction |
| 2132system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2133system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2143system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2144system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2134system.cpu1.commit.op_class_0::total 50889001 # Class of committed instruction 2135system.cpu1.commit.bw_lim_events 394979 # number cycles where commit BW limit reached 2136system.cpu1.rob.rob_reads 137189075 # The number of ROB reads 2137system.cpu1.rob.rob_writes 110398979 # The number of ROB writes 2138system.cpu1.timesIdled 58975 # Number of times that the entire CPU went into an idle state and unscheduled itself 2139system.cpu1.idleCycles 928043 # Total number of cycles that the CPU has spent unscheduled due to idling 2140system.cpu1.quiesceCycles 5545446856 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2141system.cpu1.committedInsts 41285938 # Number of Instructions Simulated 2142system.cpu1.committedOps 50856145 # Number of Ops (including micro ops) Simulated 2143system.cpu1.cpi 2.572644 # CPI: Cycles Per Instruction 2144system.cpu1.cpi_total 2.572644 # CPI: Total CPI of All Threads 2145system.cpu1.ipc 0.388705 # IPC: Instructions Per Cycle 2146system.cpu1.ipc_total 0.388705 # IPC: Total IPC of All Threads 2147system.cpu1.int_regfile_reads 55995090 # number of integer regfile reads 2148system.cpu1.int_regfile_writes 35603094 # number of integer regfile writes 2149system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads | 2145system.cpu1.commit.op_class_0::total 19761740 # Class of committed instruction 2146system.cpu1.commit.bw_lim_events 379438 # number cycles where commit BW limit reached 2147system.cpu1.rob.rob_reads 53719965 # The number of ROB reads 2148system.cpu1.rob.rob_writes 43510270 # The number of ROB writes 2149system.cpu1.timesIdled 58110 # Number of times that the entire CPU went into an idle state and unscheduled itself 2150system.cpu1.idleCycles 962680 # Total number of cycles that the CPU has spent unscheduled due to idling 2151system.cpu1.quiesceCycles 5617725351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2152system.cpu1.committedInsts 16085632 # Number of Instructions Simulated 2153system.cpu1.committedOps 19728885 # Number of Ops (including micro ops) Simulated 2154system.cpu1.cpi 2.169388 # CPI: Cycles Per Instruction 2155system.cpu1.cpi_total 2.169388 # CPI: Total CPI of All Threads 2156system.cpu1.ipc 0.460959 # IPC: Instructions Per Cycle 2157system.cpu1.ipc_total 0.460959 # IPC: Total IPC of All Threads 2158system.cpu1.int_regfile_reads 23317955 # number of integer regfile reads 2159system.cpu1.int_regfile_writes 13332838 # number of integer regfile writes 2160system.cpu1.fp_regfile_reads 1403 # number of floating regfile reads |
| 2150system.cpu1.fp_regfile_writes 516 # number of floating regfile writes | 2161system.cpu1.fp_regfile_writes 516 # number of floating regfile writes |
| 2151system.cpu1.cc_regfile_reads 190376100 # number of cc regfile reads 2152system.cpu1.cc_regfile_writes 15518701 # number of cc regfile writes 2153system.cpu1.misc_regfile_reads 209095836 # number of misc regfile reads 2154system.cpu1.misc_regfile_writes 386203 # number of misc regfile writes 2155system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2156system.cpu1.dcache.tags.replacements 187149 # number of replacements 2157system.cpu1.dcache.tags.tagsinuse 469.748213 # Cycle average of tags in use 2158system.cpu1.dcache.tags.total_refs 15687000 # Total number of references to valid blocks. 2159system.cpu1.dcache.tags.sampled_refs 187502 # Sample count of references to valid blocks. 2160system.cpu1.dcache.tags.avg_refs 83.663108 # Average number of references to valid blocks. 2161system.cpu1.dcache.tags.warmup_cycle 93899473000 # Cycle when the warmup percentage was hit. 2162system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.748213 # Average occupied blocks per requestor 2163system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917477 # Average percentage of cache occupancy 2164system.cpu1.dcache.tags.occ_percent::total 0.917477 # Average percentage of cache occupancy 2165system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id 2166system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id 2167system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 2168system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id 2169system.cpu1.dcache.tags.tag_accesses 32860265 # Number of tag accesses 2170system.cpu1.dcache.tags.data_accesses 32860265 # Number of data accesses 2171system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2172system.cpu1.dcache.ReadReq_hits::cpu1.data 9540081 # number of ReadReq hits 2173system.cpu1.dcache.ReadReq_hits::total 9540081 # number of ReadReq hits 2174system.cpu1.dcache.WriteReq_hits::cpu1.data 5893568 # number of WriteReq hits 2175system.cpu1.dcache.WriteReq_hits::total 5893568 # number of WriteReq hits 2176system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48959 # number of SoftPFReq hits 2177system.cpu1.dcache.SoftPFReq_hits::total 48959 # number of SoftPFReq hits 2178system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77987 # number of LoadLockedReq hits 2179system.cpu1.dcache.LoadLockedReq_hits::total 77987 # number of LoadLockedReq hits 2180system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70168 # number of StoreCondReq hits 2181system.cpu1.dcache.StoreCondReq_hits::total 70168 # number of StoreCondReq hits 2182system.cpu1.dcache.demand_hits::cpu1.data 15433649 # number of demand (read+write) hits 2183system.cpu1.dcache.demand_hits::total 15433649 # number of demand (read+write) hits 2184system.cpu1.dcache.overall_hits::cpu1.data 15482608 # number of overall hits 2185system.cpu1.dcache.overall_hits::total 15482608 # number of overall hits 2186system.cpu1.dcache.ReadReq_misses::cpu1.data 215586 # number of ReadReq misses 2187system.cpu1.dcache.ReadReq_misses::total 215586 # number of ReadReq misses 2188system.cpu1.dcache.WriteReq_misses::cpu1.data 396166 # number of WriteReq misses 2189system.cpu1.dcache.WriteReq_misses::total 396166 # number of WriteReq misses 2190system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30156 # number of SoftPFReq misses 2191system.cpu1.dcache.SoftPFReq_misses::total 30156 # number of SoftPFReq misses 2192system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18335 # number of LoadLockedReq misses 2193system.cpu1.dcache.LoadLockedReq_misses::total 18335 # number of LoadLockedReq misses 2194system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23429 # number of StoreCondReq misses 2195system.cpu1.dcache.StoreCondReq_misses::total 23429 # number of StoreCondReq misses 2196system.cpu1.dcache.demand_misses::cpu1.data 611752 # number of demand (read+write) misses 2197system.cpu1.dcache.demand_misses::total 611752 # number of demand (read+write) misses 2198system.cpu1.dcache.overall_misses::cpu1.data 641908 # number of overall misses 2199system.cpu1.dcache.overall_misses::total 641908 # number of overall misses 2200system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3514528500 # number of ReadReq miss cycles 2201system.cpu1.dcache.ReadReq_miss_latency::total 3514528500 # number of ReadReq miss cycles 2202system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9742278459 # number of WriteReq miss cycles 2203system.cpu1.dcache.WriteReq_miss_latency::total 9742278459 # number of WriteReq miss cycles 2204system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360181500 # number of LoadLockedReq miss cycles 2205system.cpu1.dcache.LoadLockedReq_miss_latency::total 360181500 # number of LoadLockedReq miss cycles 2206system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551095500 # number of StoreCondReq miss cycles 2207system.cpu1.dcache.StoreCondReq_miss_latency::total 551095500 # number of StoreCondReq miss cycles 2208system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 166500 # number of StoreCondFailReq miss cycles 2209system.cpu1.dcache.StoreCondFailReq_miss_latency::total 166500 # number of StoreCondFailReq miss cycles 2210system.cpu1.dcache.demand_miss_latency::cpu1.data 13256806959 # number of demand (read+write) miss cycles 2211system.cpu1.dcache.demand_miss_latency::total 13256806959 # number of demand (read+write) miss cycles 2212system.cpu1.dcache.overall_miss_latency::cpu1.data 13256806959 # number of overall miss cycles 2213system.cpu1.dcache.overall_miss_latency::total 13256806959 # number of overall miss cycles 2214system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755667 # number of ReadReq accesses(hits+misses) 2215system.cpu1.dcache.ReadReq_accesses::total 9755667 # number of ReadReq accesses(hits+misses) 2216system.cpu1.dcache.WriteReq_accesses::cpu1.data 6289734 # number of WriteReq accesses(hits+misses) 2217system.cpu1.dcache.WriteReq_accesses::total 6289734 # number of WriteReq accesses(hits+misses) 2218system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79115 # number of SoftPFReq accesses(hits+misses) 2219system.cpu1.dcache.SoftPFReq_accesses::total 79115 # number of SoftPFReq accesses(hits+misses) 2220system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96322 # number of LoadLockedReq accesses(hits+misses) 2221system.cpu1.dcache.LoadLockedReq_accesses::total 96322 # number of LoadLockedReq accesses(hits+misses) 2222system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93597 # number of StoreCondReq accesses(hits+misses) 2223system.cpu1.dcache.StoreCondReq_accesses::total 93597 # number of StoreCondReq accesses(hits+misses) 2224system.cpu1.dcache.demand_accesses::cpu1.data 16045401 # number of demand (read+write) accesses 2225system.cpu1.dcache.demand_accesses::total 16045401 # number of demand (read+write) accesses 2226system.cpu1.dcache.overall_accesses::cpu1.data 16124516 # number of overall (read+write) accesses 2227system.cpu1.dcache.overall_accesses::total 16124516 # number of overall (read+write) accesses 2228system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022099 # miss rate for ReadReq accesses 2229system.cpu1.dcache.ReadReq_miss_rate::total 0.022099 # miss rate for ReadReq accesses 2230system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062986 # miss rate for WriteReq accesses 2231system.cpu1.dcache.WriteReq_miss_rate::total 0.062986 # miss rate for WriteReq accesses 2232system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381167 # miss rate for SoftPFReq accesses 2233system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381167 # miss rate for SoftPFReq accesses 2234system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190351 # miss rate for LoadLockedReq accesses 2235system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190351 # miss rate for LoadLockedReq accesses 2236system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250318 # miss rate for StoreCondReq accesses 2237system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250318 # miss rate for StoreCondReq accesses 2238system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038126 # miss rate for demand accesses 2239system.cpu1.dcache.demand_miss_rate::total 0.038126 # miss rate for demand accesses 2240system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039809 # miss rate for overall accesses 2241system.cpu1.dcache.overall_miss_rate::total 0.039809 # miss rate for overall accesses 2242system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183 # average ReadReq miss latency 2243system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183 # average ReadReq miss latency 2244system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762 # average WriteReq miss latency 2245system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762 # average WriteReq miss latency 2246system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775 # average LoadLockedReq miss latency 2247system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775 # average LoadLockedReq miss latency 2248system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623 # average StoreCondReq miss latency 2249system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623 # average StoreCondReq miss latency | 2162system.cpu1.cc_regfile_reads 74580678 # number of cc regfile reads 2163system.cpu1.cc_regfile_writes 6681708 # number of cc regfile writes 2164system.cpu1.misc_regfile_reads 69976526 # number of misc regfile reads 2165system.cpu1.misc_regfile_writes 387406 # number of misc regfile writes 2166system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2167system.cpu1.dcache.tags.replacements 185136 # number of replacements 2168system.cpu1.dcache.tags.tagsinuse 468.617373 # Cycle average of tags in use 2169system.cpu1.dcache.tags.total_refs 6737062 # Total number of references to valid blocks. 2170system.cpu1.dcache.tags.sampled_refs 185477 # Sample count of references to valid blocks. 2171system.cpu1.dcache.tags.avg_refs 36.322897 # Average number of references to valid blocks. 2172system.cpu1.dcache.tags.warmup_cycle 89354157500 # Cycle when the warmup percentage was hit. 2173system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.617373 # Average occupied blocks per requestor 2174system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915268 # Average percentage of cache occupancy 2175system.cpu1.dcache.tags.occ_percent::total 0.915268 # Average percentage of cache occupancy 2176system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id 2177system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id 2178system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id 2179system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id 2180system.cpu1.dcache.tags.tag_accesses 14947542 # Number of tag accesses 2181system.cpu1.dcache.tags.data_accesses 14947542 # Number of data accesses 2182system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2183system.cpu1.dcache.ReadReq_hits::cpu1.data 3587773 # number of ReadReq hits 2184system.cpu1.dcache.ReadReq_hits::total 3587773 # number of ReadReq hits 2185system.cpu1.dcache.WriteReq_hits::cpu1.data 2897885 # number of WriteReq hits 2186system.cpu1.dcache.WriteReq_hits::total 2897885 # number of WriteReq hits 2187system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49072 # number of SoftPFReq hits 2188system.cpu1.dcache.SoftPFReq_hits::total 49072 # number of SoftPFReq hits 2189system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78768 # number of LoadLockedReq hits 2190system.cpu1.dcache.LoadLockedReq_hits::total 78768 # number of LoadLockedReq hits 2191system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70845 # number of StoreCondReq hits 2192system.cpu1.dcache.StoreCondReq_hits::total 70845 # number of StoreCondReq hits 2193system.cpu1.dcache.demand_hits::cpu1.data 6485658 # number of demand (read+write) hits 2194system.cpu1.dcache.demand_hits::total 6485658 # number of demand (read+write) hits 2195system.cpu1.dcache.overall_hits::cpu1.data 6534730 # number of overall hits 2196system.cpu1.dcache.overall_hits::total 6534730 # number of overall hits 2197system.cpu1.dcache.ReadReq_misses::cpu1.data 212319 # number of ReadReq misses 2198system.cpu1.dcache.ReadReq_misses::total 212319 # number of ReadReq misses 2199system.cpu1.dcache.WriteReq_misses::cpu1.data 390908 # number of WriteReq misses 2200system.cpu1.dcache.WriteReq_misses::total 390908 # number of WriteReq misses 2201system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29887 # number of SoftPFReq misses 2202system.cpu1.dcache.SoftPFReq_misses::total 29887 # number of SoftPFReq misses 2203system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18355 # number of LoadLockedReq misses 2204system.cpu1.dcache.LoadLockedReq_misses::total 18355 # number of LoadLockedReq misses 2205system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23465 # number of StoreCondReq misses 2206system.cpu1.dcache.StoreCondReq_misses::total 23465 # number of StoreCondReq misses 2207system.cpu1.dcache.demand_misses::cpu1.data 603227 # number of demand (read+write) misses 2208system.cpu1.dcache.demand_misses::total 603227 # number of demand (read+write) misses 2209system.cpu1.dcache.overall_misses::cpu1.data 633114 # number of overall misses 2210system.cpu1.dcache.overall_misses::total 633114 # number of overall misses 2211system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3545506500 # number of ReadReq miss cycles 2212system.cpu1.dcache.ReadReq_miss_latency::total 3545506500 # number of ReadReq miss cycles 2213system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9944995958 # number of WriteReq miss cycles 2214system.cpu1.dcache.WriteReq_miss_latency::total 9944995958 # number of WriteReq miss cycles 2215system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362846000 # number of LoadLockedReq miss cycles 2216system.cpu1.dcache.LoadLockedReq_miss_latency::total 362846000 # number of LoadLockedReq miss cycles 2217system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551070500 # number of StoreCondReq miss cycles 2218system.cpu1.dcache.StoreCondReq_miss_latency::total 551070500 # number of StoreCondReq miss cycles 2219system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 640500 # number of StoreCondFailReq miss cycles 2220system.cpu1.dcache.StoreCondFailReq_miss_latency::total 640500 # number of StoreCondFailReq miss cycles 2221system.cpu1.dcache.demand_miss_latency::cpu1.data 13490502458 # number of demand (read+write) miss cycles 2222system.cpu1.dcache.demand_miss_latency::total 13490502458 # number of demand (read+write) miss cycles 2223system.cpu1.dcache.overall_miss_latency::cpu1.data 13490502458 # number of overall miss cycles 2224system.cpu1.dcache.overall_miss_latency::total 13490502458 # number of overall miss cycles 2225system.cpu1.dcache.ReadReq_accesses::cpu1.data 3800092 # number of ReadReq accesses(hits+misses) 2226system.cpu1.dcache.ReadReq_accesses::total 3800092 # number of ReadReq accesses(hits+misses) 2227system.cpu1.dcache.WriteReq_accesses::cpu1.data 3288793 # number of WriteReq accesses(hits+misses) 2228system.cpu1.dcache.WriteReq_accesses::total 3288793 # number of WriteReq accesses(hits+misses) 2229system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 78959 # number of SoftPFReq accesses(hits+misses) 2230system.cpu1.dcache.SoftPFReq_accesses::total 78959 # number of SoftPFReq accesses(hits+misses) 2231system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97123 # number of LoadLockedReq accesses(hits+misses) 2232system.cpu1.dcache.LoadLockedReq_accesses::total 97123 # number of LoadLockedReq accesses(hits+misses) 2233system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94310 # number of StoreCondReq accesses(hits+misses) 2234system.cpu1.dcache.StoreCondReq_accesses::total 94310 # number of StoreCondReq accesses(hits+misses) 2235system.cpu1.dcache.demand_accesses::cpu1.data 7088885 # number of demand (read+write) accesses 2236system.cpu1.dcache.demand_accesses::total 7088885 # number of demand (read+write) accesses 2237system.cpu1.dcache.overall_accesses::cpu1.data 7167844 # number of overall (read+write) accesses 2238system.cpu1.dcache.overall_accesses::total 7167844 # number of overall (read+write) accesses 2239system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055872 # miss rate for ReadReq accesses 2240system.cpu1.dcache.ReadReq_miss_rate::total 0.055872 # miss rate for ReadReq accesses 2241system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118861 # miss rate for WriteReq accesses 2242system.cpu1.dcache.WriteReq_miss_rate::total 0.118861 # miss rate for WriteReq accesses 2243system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378513 # miss rate for SoftPFReq accesses 2244system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378513 # miss rate for SoftPFReq accesses 2245system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188987 # miss rate for LoadLockedReq accesses 2246system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188987 # miss rate for LoadLockedReq accesses 2247system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248807 # miss rate for StoreCondReq accesses 2248system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248807 # miss rate for StoreCondReq accesses 2249system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085095 # miss rate for demand accesses 2250system.cpu1.dcache.demand_miss_rate::total 0.085095 # miss rate for demand accesses 2251system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088327 # miss rate for overall accesses 2252system.cpu1.dcache.overall_miss_rate::total 0.088327 # miss rate for overall accesses 2253system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16698.960055 # average ReadReq miss latency 2254system.cpu1.dcache.ReadReq_avg_miss_latency::total 16698.960055 # average ReadReq miss latency 2255system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25440.758332 # average WriteReq miss latency 2256system.cpu1.dcache.WriteReq_avg_miss_latency::total 25440.758332 # average WriteReq miss latency 2257system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19768.237537 # average LoadLockedReq miss latency 2258system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19768.237537 # average LoadLockedReq miss latency 2259system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23484.785851 # average StoreCondReq miss latency 2260system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23484.785851 # average StoreCondReq miss latency |
| 2250system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2251system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2261system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2262system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2252system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680 # average overall miss latency 2253system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680 # average overall miss latency 2254system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527 # average overall miss latency 2255system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527 # average overall miss latency 2256system.cpu1.dcache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked 2257system.cpu1.dcache.blocked_cycles::no_targets 1431753 # number of cycles access was blocked 2258system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked 2259system.cpu1.dcache.blocked::no_targets 39808 # number of cycles access was blocked 2260system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.210526 # average number of cycles each access was blocked 2261system.cpu1.dcache.avg_blocked_cycles::no_targets 35.966464 # average number of cycles each access was blocked 2262system.cpu1.dcache.writebacks::writebacks 187150 # number of writebacks 2263system.cpu1.dcache.writebacks::total 187150 # number of writebacks 2264system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79090 # number of ReadReq MSHR hits 2265system.cpu1.dcache.ReadReq_mshr_hits::total 79090 # number of ReadReq MSHR hits 2266system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306284 # number of WriteReq MSHR hits 2267system.cpu1.dcache.WriteReq_mshr_hits::total 306284 # number of WriteReq MSHR hits 2268system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13036 # number of LoadLockedReq MSHR hits 2269system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13036 # number of LoadLockedReq MSHR hits 2270system.cpu1.dcache.demand_mshr_hits::cpu1.data 385374 # number of demand (read+write) MSHR hits 2271system.cpu1.dcache.demand_mshr_hits::total 385374 # number of demand (read+write) MSHR hits 2272system.cpu1.dcache.overall_mshr_hits::cpu1.data 385374 # number of overall MSHR hits 2273system.cpu1.dcache.overall_mshr_hits::total 385374 # number of overall MSHR hits 2274system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136496 # number of ReadReq MSHR misses 2275system.cpu1.dcache.ReadReq_mshr_misses::total 136496 # number of ReadReq MSHR misses 2276system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89882 # number of WriteReq MSHR misses 2277system.cpu1.dcache.WriteReq_mshr_misses::total 89882 # number of WriteReq MSHR misses 2278system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28741 # number of SoftPFReq MSHR misses 2279system.cpu1.dcache.SoftPFReq_mshr_misses::total 28741 # number of SoftPFReq MSHR misses 2280system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5299 # number of LoadLockedReq MSHR misses 2281system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5299 # number of LoadLockedReq MSHR misses 2282system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23429 # number of StoreCondReq MSHR misses 2283system.cpu1.dcache.StoreCondReq_mshr_misses::total 23429 # number of StoreCondReq MSHR misses 2284system.cpu1.dcache.demand_mshr_misses::cpu1.data 226378 # number of demand (read+write) MSHR misses 2285system.cpu1.dcache.demand_mshr_misses::total 226378 # number of demand (read+write) MSHR misses 2286system.cpu1.dcache.overall_mshr_misses::cpu1.data 255119 # number of overall MSHR misses 2287system.cpu1.dcache.overall_mshr_misses::total 255119 # number of overall MSHR misses 2288system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable 2289system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14517 # number of ReadReq MSHR uncacheable 2290system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable 2291system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable 2292system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses 2293system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26372 # number of overall MSHR uncacheable misses 2294system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1963325500 # number of ReadReq MSHR miss cycles 2295system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1963325500 # number of ReadReq MSHR miss cycles 2296system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2363104967 # number of WriteReq MSHR miss cycles 2297system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2363104967 # number of WriteReq MSHR miss cycles 2298system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488593500 # number of SoftPFReq MSHR miss cycles 2299system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488593500 # number of SoftPFReq MSHR miss cycles 2300system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93065000 # number of LoadLockedReq MSHR miss cycles 2301system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93065000 # number of LoadLockedReq MSHR miss cycles 2302system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527670500 # number of StoreCondReq MSHR miss cycles 2303system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527670500 # number of StoreCondReq MSHR miss cycles 2304system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 162500 # number of StoreCondFailReq MSHR miss cycles 2305system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 162500 # number of StoreCondFailReq MSHR miss cycles 2306system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326430467 # number of demand (read+write) MSHR miss cycles 2307system.cpu1.dcache.demand_mshr_miss_latency::total 4326430467 # number of demand (read+write) MSHR miss cycles 2308system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4815023967 # number of overall MSHR miss cycles 2309system.cpu1.dcache.overall_mshr_miss_latency::total 4815023967 # number of overall MSHR miss cycles 2310system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2528366000 # number of ReadReq MSHR uncacheable cycles 2311system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2528366000 # number of ReadReq MSHR uncacheable cycles 2312system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2528366000 # number of overall MSHR uncacheable cycles 2313system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2528366000 # number of overall MSHR uncacheable cycles 2314system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013991 # mshr miss rate for ReadReq accesses 2315system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013991 # mshr miss rate for ReadReq accesses 2316system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014290 # mshr miss rate for WriteReq accesses 2317system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014290 # mshr miss rate for WriteReq accesses 2318system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.363281 # mshr miss rate for SoftPFReq accesses 2319system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.363281 # mshr miss rate for SoftPFReq accesses 2320system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055013 # mshr miss rate for LoadLockedReq accesses 2321system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055013 # mshr miss rate for LoadLockedReq accesses 2322system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250318 # mshr miss rate for StoreCondReq accesses 2323system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250318 # mshr miss rate for StoreCondReq accesses 2324system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014109 # mshr miss rate for demand accesses 2325system.cpu1.dcache.demand_mshr_miss_rate::total 0.014109 # mshr miss rate for demand accesses 2326system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015822 # mshr miss rate for overall accesses 2327system.cpu1.dcache.overall_mshr_miss_rate::total 0.015822 # mshr miss rate for overall accesses 2328system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498 # average ReadReq mshr miss latency 2329system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498 # average ReadReq mshr miss latency 2330system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530 # average WriteReq mshr miss latency 2331system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530 # average WriteReq mshr miss latency 2332system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223 # average SoftPFReq mshr miss latency 2333system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223 # average SoftPFReq mshr miss latency 2334system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688 # average LoadLockedReq mshr miss latency 2335system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688 # average LoadLockedReq mshr miss latency 2336system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352 # average StoreCondReq mshr miss latency 2337system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352 # average StoreCondReq mshr miss latency | 2263system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22363.890307 # average overall miss latency 2264system.cpu1.dcache.demand_avg_miss_latency::total 22363.890307 # average overall miss latency 2265system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21308.172711 # average overall miss latency 2266system.cpu1.dcache.overall_avg_miss_latency::total 21308.172711 # average overall miss latency 2267system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked 2268system.cpu1.dcache.blocked_cycles::no_targets 1473013 # number of cycles access was blocked 2269system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked 2270system.cpu1.dcache.blocked::no_targets 39225 # number of cycles access was blocked 2271system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked 2272system.cpu1.dcache.avg_blocked_cycles::no_targets 37.552913 # average number of cycles each access was blocked 2273system.cpu1.dcache.writebacks::writebacks 185136 # number of writebacks 2274system.cpu1.dcache.writebacks::total 185136 # number of writebacks 2275system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 77580 # number of ReadReq MSHR hits 2276system.cpu1.dcache.ReadReq_mshr_hits::total 77580 # number of ReadReq MSHR hits 2277system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 301933 # number of WriteReq MSHR hits 2278system.cpu1.dcache.WriteReq_mshr_hits::total 301933 # number of WriteReq MSHR hits 2279system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13088 # number of LoadLockedReq MSHR hits 2280system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13088 # number of LoadLockedReq MSHR hits 2281system.cpu1.dcache.demand_mshr_hits::cpu1.data 379513 # number of demand (read+write) MSHR hits 2282system.cpu1.dcache.demand_mshr_hits::total 379513 # number of demand (read+write) MSHR hits 2283system.cpu1.dcache.overall_mshr_hits::cpu1.data 379513 # number of overall MSHR hits 2284system.cpu1.dcache.overall_mshr_hits::total 379513 # number of overall MSHR hits 2285system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134739 # number of ReadReq MSHR misses 2286system.cpu1.dcache.ReadReq_mshr_misses::total 134739 # number of ReadReq MSHR misses 2287system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 88975 # number of WriteReq MSHR misses 2288system.cpu1.dcache.WriteReq_mshr_misses::total 88975 # number of WriteReq MSHR misses 2289system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28539 # number of SoftPFReq MSHR misses 2290system.cpu1.dcache.SoftPFReq_mshr_misses::total 28539 # number of SoftPFReq MSHR misses 2291system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5267 # number of LoadLockedReq MSHR misses 2292system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5267 # number of LoadLockedReq MSHR misses 2293system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23465 # number of StoreCondReq MSHR misses 2294system.cpu1.dcache.StoreCondReq_mshr_misses::total 23465 # number of StoreCondReq MSHR misses 2295system.cpu1.dcache.demand_mshr_misses::cpu1.data 223714 # number of demand (read+write) MSHR misses 2296system.cpu1.dcache.demand_mshr_misses::total 223714 # number of demand (read+write) MSHR misses 2297system.cpu1.dcache.overall_mshr_misses::cpu1.data 252253 # number of overall MSHR misses 2298system.cpu1.dcache.overall_mshr_misses::total 252253 # number of overall MSHR misses 2299system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable 2300system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3386 # number of ReadReq MSHR uncacheable 2301system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable 2302system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable 2303system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses 2304system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6126 # number of overall MSHR uncacheable misses 2305system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1970715500 # number of ReadReq MSHR miss cycles 2306system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1970715500 # number of ReadReq MSHR miss cycles 2307system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2395378969 # number of WriteReq MSHR miss cycles 2308system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2395378969 # number of WriteReq MSHR miss cycles 2309system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 480267000 # number of SoftPFReq MSHR miss cycles 2310system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 480267000 # number of SoftPFReq MSHR miss cycles 2311system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94406500 # number of LoadLockedReq MSHR miss cycles 2312system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94406500 # number of LoadLockedReq MSHR miss cycles 2313system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527620500 # number of StoreCondReq MSHR miss cycles 2314system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527620500 # number of StoreCondReq MSHR miss cycles 2315system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 625500 # number of StoreCondFailReq MSHR miss cycles 2316system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles 2317system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4366094469 # number of demand (read+write) MSHR miss cycles 2318system.cpu1.dcache.demand_mshr_miss_latency::total 4366094469 # number of demand (read+write) MSHR miss cycles 2319system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846361469 # number of overall MSHR miss cycles 2320system.cpu1.dcache.overall_mshr_miss_latency::total 4846361469 # number of overall MSHR miss cycles 2321system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 459425000 # number of ReadReq MSHR uncacheable cycles 2322system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 459425000 # number of ReadReq MSHR uncacheable cycles 2323system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 459425000 # number of overall MSHR uncacheable cycles 2324system.cpu1.dcache.overall_mshr_uncacheable_latency::total 459425000 # number of overall MSHR uncacheable cycles 2325system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035457 # mshr miss rate for ReadReq accesses 2326system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035457 # mshr miss rate for ReadReq accesses 2327system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027054 # mshr miss rate for WriteReq accesses 2328system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027054 # mshr miss rate for WriteReq accesses 2329system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361441 # mshr miss rate for SoftPFReq accesses 2330system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361441 # mshr miss rate for SoftPFReq accesses 2331system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054230 # mshr miss rate for LoadLockedReq accesses 2332system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054230 # mshr miss rate for LoadLockedReq accesses 2333system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248807 # mshr miss rate for StoreCondReq accesses 2334system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248807 # mshr miss rate for StoreCondReq accesses 2335system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031558 # mshr miss rate for demand accesses 2336system.cpu1.dcache.demand_mshr_miss_rate::total 0.031558 # mshr miss rate for demand accesses 2337system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035192 # mshr miss rate for overall accesses 2338system.cpu1.dcache.overall_mshr_miss_rate::total 0.035192 # mshr miss rate for overall accesses 2339system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14626.169854 # average ReadReq mshr miss latency 2340system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14626.169854 # average ReadReq mshr miss latency 2341system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26921.932779 # average WriteReq mshr miss latency 2342system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26921.932779 # average WriteReq mshr miss latency 2343system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16828.445285 # average SoftPFReq mshr miss latency 2344system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16828.445285 # average SoftPFReq mshr miss latency 2345system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17924.150370 # average LoadLockedReq mshr miss latency 2346system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17924.150370 # average LoadLockedReq mshr miss latency 2347system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22485.425101 # average StoreCondReq mshr miss latency 2348system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22485.425101 # average StoreCondReq mshr miss latency |
| 2338system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2339system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2349system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2350system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2340system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335 # average overall mshr miss latency 2341system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335 # average overall mshr miss latency 2342system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231 # average overall mshr miss latency 2343system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231 # average overall mshr miss latency 2344system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492 # average ReadReq mshr uncacheable latency 2345system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492 # average ReadReq mshr uncacheable latency 2346system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009 # average overall mshr uncacheable latency 2347system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009 # average overall mshr uncacheable latency 2348system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2349system.cpu1.icache.tags.replacements 589510 # number of replacements 2350system.cpu1.icache.tags.tagsinuse 499.449637 # Cycle average of tags in use 2351system.cpu1.icache.tags.total_refs 42880129 # Total number of references to valid blocks. 2352system.cpu1.icache.tags.sampled_refs 590022 # Sample count of references to valid blocks. 2353system.cpu1.icache.tags.avg_refs 72.675475 # Average number of references to valid blocks. 2354system.cpu1.icache.tags.warmup_cycle 79021423000 # Cycle when the warmup percentage was hit. 2355system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.449637 # Average occupied blocks per requestor 2356system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975488 # Average percentage of cache occupancy 2357system.cpu1.icache.tags.occ_percent::total 0.975488 # Average percentage of cache occupancy | 2351system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19516.411440 # average overall mshr miss latency 2352system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19516.411440 # average overall mshr miss latency 2353system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19212.304587 # average overall mshr miss latency 2354system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19212.304587 # average overall mshr miss latency 2355system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135683.697578 # average ReadReq mshr uncacheable latency 2356system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 135683.697578 # average ReadReq mshr uncacheable latency 2357system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 74995.919034 # average overall mshr uncacheable latency 2358system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 74995.919034 # average overall mshr uncacheable latency 2359system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2360system.cpu1.icache.tags.replacements 583486 # number of replacements 2361system.cpu1.icache.tags.tagsinuse 499.437314 # Cycle average of tags in use 2362system.cpu1.icache.tags.total_refs 7557735 # Total number of references to valid blocks. 2363system.cpu1.icache.tags.sampled_refs 583998 # Sample count of references to valid blocks. 2364system.cpu1.icache.tags.avg_refs 12.941371 # Average number of references to valid blocks. 2365system.cpu1.icache.tags.warmup_cycle 79127078000 # Cycle when the warmup percentage was hit. 2366system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.437314 # Average occupied blocks per requestor 2367system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975464 # Average percentage of cache occupancy 2368system.cpu1.icache.tags.occ_percent::total 0.975464 # Average percentage of cache occupancy |
| 2358system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2359system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id 2360system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2361system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2369system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2370system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id 2371system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2372system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2362system.cpu1.icache.tags.tag_accesses 87573930 # Number of tag accesses 2363system.cpu1.icache.tags.data_accesses 87573930 # Number of data accesses 2364system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2365system.cpu1.icache.ReadReq_hits::cpu1.inst 42880129 # number of ReadReq hits 2366system.cpu1.icache.ReadReq_hits::total 42880129 # number of ReadReq hits 2367system.cpu1.icache.demand_hits::cpu1.inst 42880129 # number of demand (read+write) hits 2368system.cpu1.icache.demand_hits::total 42880129 # number of demand (read+write) hits 2369system.cpu1.icache.overall_hits::cpu1.inst 42880129 # number of overall hits 2370system.cpu1.icache.overall_hits::total 42880129 # number of overall hits 2371system.cpu1.icache.ReadReq_misses::cpu1.inst 611823 # number of ReadReq misses 2372system.cpu1.icache.ReadReq_misses::total 611823 # number of ReadReq misses 2373system.cpu1.icache.demand_misses::cpu1.inst 611823 # number of demand (read+write) misses 2374system.cpu1.icache.demand_misses::total 611823 # number of demand (read+write) misses 2375system.cpu1.icache.overall_misses::cpu1.inst 611823 # number of overall misses 2376system.cpu1.icache.overall_misses::total 611823 # number of overall misses 2377system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5700309356 # number of ReadReq miss cycles 2378system.cpu1.icache.ReadReq_miss_latency::total 5700309356 # number of ReadReq miss cycles 2379system.cpu1.icache.demand_miss_latency::cpu1.inst 5700309356 # number of demand (read+write) miss cycles 2380system.cpu1.icache.demand_miss_latency::total 5700309356 # number of demand (read+write) miss cycles 2381system.cpu1.icache.overall_miss_latency::cpu1.inst 5700309356 # number of overall miss cycles 2382system.cpu1.icache.overall_miss_latency::total 5700309356 # number of overall miss cycles 2383system.cpu1.icache.ReadReq_accesses::cpu1.inst 43491952 # number of ReadReq accesses(hits+misses) 2384system.cpu1.icache.ReadReq_accesses::total 43491952 # number of ReadReq accesses(hits+misses) 2385system.cpu1.icache.demand_accesses::cpu1.inst 43491952 # number of demand (read+write) accesses 2386system.cpu1.icache.demand_accesses::total 43491952 # number of demand (read+write) accesses 2387system.cpu1.icache.overall_accesses::cpu1.inst 43491952 # number of overall (read+write) accesses 2388system.cpu1.icache.overall_accesses::total 43491952 # number of overall (read+write) accesses 2389system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014067 # miss rate for ReadReq accesses 2390system.cpu1.icache.ReadReq_miss_rate::total 0.014067 # miss rate for ReadReq accesses 2391system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014067 # miss rate for demand accesses 2392system.cpu1.icache.demand_miss_rate::total 0.014067 # miss rate for demand accesses 2393system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014067 # miss rate for overall accesses 2394system.cpu1.icache.overall_miss_rate::total 0.014067 # miss rate for overall accesses 2395system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9316.925575 # average ReadReq miss latency 2396system.cpu1.icache.ReadReq_avg_miss_latency::total 9316.925575 # average ReadReq miss latency 2397system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency 2398system.cpu1.icache.demand_avg_miss_latency::total 9316.925575 # average overall miss latency 2399system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency 2400system.cpu1.icache.overall_avg_miss_latency::total 9316.925575 # average overall miss latency 2401system.cpu1.icache.blocked_cycles::no_mshrs 502398 # number of cycles access was blocked | 2373system.cpu1.icache.tags.tag_accesses 16911139 # Number of tag accesses 2374system.cpu1.icache.tags.data_accesses 16911139 # Number of data accesses 2375system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2376system.cpu1.icache.ReadReq_hits::cpu1.inst 7557735 # number of ReadReq hits 2377system.cpu1.icache.ReadReq_hits::total 7557735 # number of ReadReq hits 2378system.cpu1.icache.demand_hits::cpu1.inst 7557735 # number of demand (read+write) hits 2379system.cpu1.icache.demand_hits::total 7557735 # number of demand (read+write) hits 2380system.cpu1.icache.overall_hits::cpu1.inst 7557735 # number of overall hits 2381system.cpu1.icache.overall_hits::total 7557735 # number of overall hits 2382system.cpu1.icache.ReadReq_misses::cpu1.inst 605833 # number of ReadReq misses 2383system.cpu1.icache.ReadReq_misses::total 605833 # number of ReadReq misses 2384system.cpu1.icache.demand_misses::cpu1.inst 605833 # number of demand (read+write) misses 2385system.cpu1.icache.demand_misses::total 605833 # number of demand (read+write) misses 2386system.cpu1.icache.overall_misses::cpu1.inst 605833 # number of overall misses 2387system.cpu1.icache.overall_misses::total 605833 # number of overall misses 2388system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5683938295 # number of ReadReq miss cycles 2389system.cpu1.icache.ReadReq_miss_latency::total 5683938295 # number of ReadReq miss cycles 2390system.cpu1.icache.demand_miss_latency::cpu1.inst 5683938295 # number of demand (read+write) miss cycles 2391system.cpu1.icache.demand_miss_latency::total 5683938295 # number of demand (read+write) miss cycles 2392system.cpu1.icache.overall_miss_latency::cpu1.inst 5683938295 # number of overall miss cycles 2393system.cpu1.icache.overall_miss_latency::total 5683938295 # number of overall miss cycles 2394system.cpu1.icache.ReadReq_accesses::cpu1.inst 8163568 # number of ReadReq accesses(hits+misses) 2395system.cpu1.icache.ReadReq_accesses::total 8163568 # number of ReadReq accesses(hits+misses) 2396system.cpu1.icache.demand_accesses::cpu1.inst 8163568 # number of demand (read+write) accesses 2397system.cpu1.icache.demand_accesses::total 8163568 # number of demand (read+write) accesses 2398system.cpu1.icache.overall_accesses::cpu1.inst 8163568 # number of overall (read+write) accesses 2399system.cpu1.icache.overall_accesses::total 8163568 # number of overall (read+write) accesses 2400system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074212 # miss rate for ReadReq accesses 2401system.cpu1.icache.ReadReq_miss_rate::total 0.074212 # miss rate for ReadReq accesses 2402system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074212 # miss rate for demand accesses 2403system.cpu1.icache.demand_miss_rate::total 0.074212 # miss rate for demand accesses 2404system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074212 # miss rate for overall accesses 2405system.cpu1.icache.overall_miss_rate::total 0.074212 # miss rate for overall accesses 2406system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9382.021605 # average ReadReq miss latency 2407system.cpu1.icache.ReadReq_avg_miss_latency::total 9382.021605 # average ReadReq miss latency 2408system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency 2409system.cpu1.icache.demand_avg_miss_latency::total 9382.021605 # average overall miss latency 2410system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency 2411system.cpu1.icache.overall_avg_miss_latency::total 9382.021605 # average overall miss latency 2412system.cpu1.icache.blocked_cycles::no_mshrs 514122 # number of cycles access was blocked |
| 2402system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2413system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2403system.cpu1.icache.blocked::no_mshrs 42118 # number of cycles access was blocked | 2414system.cpu1.icache.blocked::no_mshrs 41357 # number of cycles access was blocked |
| 2404system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 2415system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 2405system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.928344 # average number of cycles each access was blocked | 2416system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.431318 # average number of cycles each access was blocked |
| 2406system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2417system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2407system.cpu1.icache.writebacks::writebacks 589510 # number of writebacks 2408system.cpu1.icache.writebacks::total 589510 # number of writebacks 2409system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21797 # number of ReadReq MSHR hits 2410system.cpu1.icache.ReadReq_mshr_hits::total 21797 # number of ReadReq MSHR hits 2411system.cpu1.icache.demand_mshr_hits::cpu1.inst 21797 # number of demand (read+write) MSHR hits 2412system.cpu1.icache.demand_mshr_hits::total 21797 # number of demand (read+write) MSHR hits 2413system.cpu1.icache.overall_mshr_hits::cpu1.inst 21797 # number of overall MSHR hits 2414system.cpu1.icache.overall_mshr_hits::total 21797 # number of overall MSHR hits 2415system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 590026 # number of ReadReq MSHR misses 2416system.cpu1.icache.ReadReq_mshr_misses::total 590026 # number of ReadReq MSHR misses 2417system.cpu1.icache.demand_mshr_misses::cpu1.inst 590026 # number of demand (read+write) MSHR misses 2418system.cpu1.icache.demand_mshr_misses::total 590026 # number of demand (read+write) MSHR misses 2419system.cpu1.icache.overall_mshr_misses::cpu1.inst 590026 # number of overall MSHR misses 2420system.cpu1.icache.overall_mshr_misses::total 590026 # number of overall MSHR misses | 2418system.cpu1.icache.writebacks::writebacks 583486 # number of writebacks 2419system.cpu1.icache.writebacks::total 583486 # number of writebacks 2420system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21830 # number of ReadReq MSHR hits 2421system.cpu1.icache.ReadReq_mshr_hits::total 21830 # number of ReadReq MSHR hits 2422system.cpu1.icache.demand_mshr_hits::cpu1.inst 21830 # number of demand (read+write) MSHR hits 2423system.cpu1.icache.demand_mshr_hits::total 21830 # number of demand (read+write) MSHR hits 2424system.cpu1.icache.overall_mshr_hits::cpu1.inst 21830 # number of overall MSHR hits 2425system.cpu1.icache.overall_mshr_hits::total 21830 # number of overall MSHR hits 2426system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 584003 # number of ReadReq MSHR misses 2427system.cpu1.icache.ReadReq_mshr_misses::total 584003 # number of ReadReq MSHR misses 2428system.cpu1.icache.demand_mshr_misses::cpu1.inst 584003 # number of demand (read+write) MSHR misses 2429system.cpu1.icache.demand_mshr_misses::total 584003 # number of demand (read+write) MSHR misses 2430system.cpu1.icache.overall_mshr_misses::cpu1.inst 584003 # number of overall MSHR misses 2431system.cpu1.icache.overall_mshr_misses::total 584003 # number of overall MSHR misses |
| 2421system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable 2422system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable 2423system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses 2424system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses | 2432system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable 2433system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable 2434system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses 2435system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses |
| 2425system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5243631193 # number of ReadReq MSHR miss cycles 2426system.cpu1.icache.ReadReq_mshr_miss_latency::total 5243631193 # number of ReadReq MSHR miss cycles 2427system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5243631193 # number of demand (read+write) MSHR miss cycles 2428system.cpu1.icache.demand_mshr_miss_latency::total 5243631193 # number of demand (read+write) MSHR miss cycles 2429system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5243631193 # number of overall MSHR miss cycles 2430system.cpu1.icache.overall_mshr_miss_latency::total 5243631193 # number of overall MSHR miss cycles 2431system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8747999 # number of ReadReq MSHR uncacheable cycles 2432system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8747999 # number of ReadReq MSHR uncacheable cycles 2433system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8747999 # number of overall MSHR uncacheable cycles 2434system.cpu1.icache.overall_mshr_uncacheable_latency::total 8747999 # number of overall MSHR uncacheable cycles 2435system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for ReadReq accesses 2436system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013566 # mshr miss rate for ReadReq accesses 2437system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for demand accesses 2438system.cpu1.icache.demand_mshr_miss_rate::total 0.013566 # mshr miss rate for demand accesses 2439system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for overall accesses 2440system.cpu1.icache.overall_mshr_miss_rate::total 0.013566 # mshr miss rate for overall accesses 2441system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average ReadReq mshr miss latency 2442system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8887.118861 # average ReadReq mshr miss latency 2443system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency 2444system.cpu1.icache.demand_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency 2445system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency 2446system.cpu1.icache.overall_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency 2447system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average ReadReq mshr uncacheable latency 2448system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485 # average ReadReq mshr uncacheable latency 2449system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average overall mshr uncacheable latency 2450system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485 # average overall mshr uncacheable latency 2451system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2452system.cpu1.l2cache.prefetcher.num_hwpf_issued 195371 # number of hwpf issued 2453system.cpu1.l2cache.prefetcher.pfIdentified 196016 # number of prefetch candidates identified 2454system.cpu1.l2cache.prefetcher.pfBufferHit 576 # number of redundant prefetches already in prefetch queue | 2436system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5223422114 # number of ReadReq MSHR miss cycles 2437system.cpu1.icache.ReadReq_mshr_miss_latency::total 5223422114 # number of ReadReq MSHR miss cycles 2438system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5223422114 # number of demand (read+write) MSHR miss cycles 2439system.cpu1.icache.demand_mshr_miss_latency::total 5223422114 # number of demand (read+write) MSHR miss cycles 2440system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5223422114 # number of overall MSHR miss cycles 2441system.cpu1.icache.overall_mshr_miss_latency::total 5223422114 # number of overall MSHR miss cycles 2442system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9321999 # number of ReadReq MSHR uncacheable cycles 2443system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9321999 # number of ReadReq MSHR uncacheable cycles 2444system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9321999 # number of overall MSHR uncacheable cycles 2445system.cpu1.icache.overall_mshr_uncacheable_latency::total 9321999 # number of overall MSHR uncacheable cycles 2446system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for ReadReq accesses 2447system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071538 # mshr miss rate for ReadReq accesses 2448system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for demand accesses 2449system.cpu1.icache.demand_mshr_miss_rate::total 0.071538 # mshr miss rate for demand accesses 2450system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for overall accesses 2451system.cpu1.icache.overall_mshr_miss_rate::total 0.071538 # mshr miss rate for overall accesses 2452system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average ReadReq mshr miss latency 2453system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8944.170003 # average ReadReq mshr miss latency 2454system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency 2455system.cpu1.icache.demand_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency 2456system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency 2457system.cpu1.icache.overall_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency 2458system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average ReadReq mshr uncacheable latency 2459system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92297.019802 # average ReadReq mshr uncacheable latency 2460system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average overall mshr uncacheable latency 2461system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92297.019802 # average overall mshr uncacheable latency 2462system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2463system.cpu1.l2cache.prefetcher.num_hwpf_issued 192037 # number of hwpf issued 2464system.cpu1.l2cache.prefetcher.pfIdentified 192612 # number of prefetch candidates identified 2465system.cpu1.l2cache.prefetcher.pfBufferHit 514 # number of redundant prefetches already in prefetch queue |
| 2455system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2456system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 2466system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2467system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 2457system.cpu1.l2cache.prefetcher.pfSpanPage 57640 # number of prefetches not generated due to page crossing 2458system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2459system.cpu1.l2cache.tags.replacements 44567 # number of replacements 2460system.cpu1.l2cache.tags.tagsinuse 14592.313259 # Cycle average of tags in use 2461system.cpu1.l2cache.tags.total_refs 696647 # Total number of references to valid blocks. 2462system.cpu1.l2cache.tags.sampled_refs 58721 # Sample count of references to valid blocks. 2463system.cpu1.l2cache.tags.avg_refs 11.863677 # Average number of references to valid blocks. | 2468system.cpu1.l2cache.prefetcher.pfSpanPage 57820 # number of prefetches not generated due to page crossing 2469system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2470system.cpu1.l2cache.tags.replacements 43247 # number of replacements 2471system.cpu1.l2cache.tags.tagsinuse 14634.111672 # Cycle average of tags in use 2472system.cpu1.l2cache.tags.total_refs 688069 # Total number of references to valid blocks. 2473system.cpu1.l2cache.tags.sampled_refs 57318 # Sample count of references to valid blocks. 2474system.cpu1.l2cache.tags.avg_refs 12.004414 # Average number of references to valid blocks. |
| 2464system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2475system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2465system.cpu1.l2cache.tags.occ_blocks::writebacks 14188.463877 # Average occupied blocks per requestor 2466system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.825483 # Average occupied blocks per requestor 2467system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.061403 # Average occupied blocks per requestor 2468system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 390.962497 # Average occupied blocks per requestor 2469system.cpu1.l2cache.tags.occ_percent::writebacks 0.865995 # Average percentage of cache occupancy 2470system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy 2471system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy 2472system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023862 # Average percentage of cache occupancy 2473system.cpu1.l2cache.tags.occ_percent::total 0.890644 # Average percentage of cache occupancy 2474system.cpu1.l2cache.tags.occ_task_id_blocks::1022 294 # Occupied blocks per task id 2475system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id 2476system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13830 # Occupied blocks per task id 2477system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id 2478system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id 2479system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 105 # Occupied blocks per task id | 2476system.cpu1.l2cache.tags.occ_blocks::writebacks 14183.524826 # Average occupied blocks per requestor 2477system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.708728 # Average occupied blocks per requestor 2478system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.055002 # Average occupied blocks per requestor 2479system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 436.823115 # Average occupied blocks per requestor 2480system.cpu1.l2cache.tags.occ_percent::writebacks 0.865694 # Average percentage of cache occupancy 2481system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000715 # Average percentage of cache occupancy 2482system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy 2483system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026662 # Average percentage of cache occupancy 2484system.cpu1.l2cache.tags.occ_percent::total 0.893195 # Average percentage of cache occupancy 2485system.cpu1.l2cache.tags.occ_task_id_blocks::1022 321 # Occupied blocks per task id 2486system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id 2487system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id 2488system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id 2489system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 183 # Occupied blocks per task id 2490system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id |
| 2480system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id | 2491system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id |
| 2481system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 2482system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2483system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id 2484system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8625 # Occupied blocks per task id 2485system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3420 # Occupied blocks per task id 2486system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017944 # Percentage of cache occupancy per task id 2487system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id 2488system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.844116 # Percentage of cache occupancy per task id 2489system.cpu1.l2cache.tags.tag_accesses 27388422 # Number of tag accesses 2490system.cpu1.l2cache.tags.data_accesses 27388422 # Number of data accesses 2491system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2492system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17107 # number of ReadReq hits 2493system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6359 # number of ReadReq hits 2494system.cpu1.l2cache.ReadReq_hits::total 23466 # number of ReadReq hits 2495system.cpu1.l2cache.WritebackDirty_hits::writebacks 113848 # number of WritebackDirty hits 2496system.cpu1.l2cache.WritebackDirty_hits::total 113848 # number of WritebackDirty hits 2497system.cpu1.l2cache.WritebackClean_hits::writebacks 650456 # number of WritebackClean hits 2498system.cpu1.l2cache.WritebackClean_hits::total 650456 # number of WritebackClean hits 2499system.cpu1.l2cache.ReadExReq_hits::cpu1.data 26908 # number of ReadExReq hits 2500system.cpu1.l2cache.ReadExReq_hits::total 26908 # number of ReadExReq hits 2501system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 565476 # number of ReadCleanReq hits 2502system.cpu1.l2cache.ReadCleanReq_hits::total 565476 # number of ReadCleanReq hits 2503system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99207 # number of ReadSharedReq hits 2504system.cpu1.l2cache.ReadSharedReq_hits::total 99207 # number of ReadSharedReq hits 2505system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17107 # number of demand (read+write) hits 2506system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6359 # number of demand (read+write) hits 2507system.cpu1.l2cache.demand_hits::cpu1.inst 565476 # number of demand (read+write) hits 2508system.cpu1.l2cache.demand_hits::cpu1.data 126115 # number of demand (read+write) hits 2509system.cpu1.l2cache.demand_hits::total 715057 # number of demand (read+write) hits 2510system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17107 # number of overall hits 2511system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6359 # number of overall hits 2512system.cpu1.l2cache.overall_hits::cpu1.inst 565476 # number of overall hits 2513system.cpu1.l2cache.overall_hits::cpu1.data 126115 # number of overall hits 2514system.cpu1.l2cache.overall_hits::total 715057 # number of overall hits 2515system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 487 # number of ReadReq misses 2516system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 295 # number of ReadReq misses 2517system.cpu1.l2cache.ReadReq_misses::total 782 # number of ReadReq misses 2518system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29684 # number of UpgradeReq misses 2519system.cpu1.l2cache.UpgradeReq_misses::total 29684 # number of UpgradeReq misses 2520system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23429 # number of SCUpgradeReq misses 2521system.cpu1.l2cache.SCUpgradeReq_misses::total 23429 # number of SCUpgradeReq misses 2522system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33964 # number of ReadExReq misses 2523system.cpu1.l2cache.ReadExReq_misses::total 33964 # number of ReadExReq misses 2524system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 24548 # number of ReadCleanReq misses 2525system.cpu1.l2cache.ReadCleanReq_misses::total 24548 # number of ReadCleanReq misses 2526system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71313 # number of ReadSharedReq misses 2527system.cpu1.l2cache.ReadSharedReq_misses::total 71313 # number of ReadSharedReq misses 2528system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 487 # number of demand (read+write) misses 2529system.cpu1.l2cache.demand_misses::cpu1.itb.walker 295 # number of demand (read+write) misses 2530system.cpu1.l2cache.demand_misses::cpu1.inst 24548 # number of demand (read+write) misses 2531system.cpu1.l2cache.demand_misses::cpu1.data 105277 # number of demand (read+write) misses 2532system.cpu1.l2cache.demand_misses::total 130607 # number of demand (read+write) misses 2533system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 487 # number of overall misses 2534system.cpu1.l2cache.overall_misses::cpu1.itb.walker 295 # number of overall misses 2535system.cpu1.l2cache.overall_misses::cpu1.inst 24548 # number of overall misses 2536system.cpu1.l2cache.overall_misses::cpu1.data 105277 # number of overall misses 2537system.cpu1.l2cache.overall_misses::total 130607 # number of overall misses 2538system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10682500 # number of ReadReq miss cycles 2539system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6004000 # number of ReadReq miss cycles 2540system.cpu1.l2cache.ReadReq_miss_latency::total 16686500 # number of ReadReq miss cycles 2541system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13705500 # number of UpgradeReq miss cycles 2542system.cpu1.l2cache.UpgradeReq_miss_latency::total 13705500 # number of UpgradeReq miss cycles 2543system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 20860500 # number of SCUpgradeReq miss cycles 2544system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 20860500 # number of SCUpgradeReq miss cycles 2545system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 156500 # number of SCUpgradeFailReq miss cycles 2546system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 156500 # number of SCUpgradeFailReq miss cycles 2547system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1388167997 # number of ReadExReq miss cycles 2548system.cpu1.l2cache.ReadExReq_miss_latency::total 1388167997 # number of ReadExReq miss cycles 2549system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 916991000 # number of ReadCleanReq miss cycles 2550system.cpu1.l2cache.ReadCleanReq_miss_latency::total 916991000 # number of ReadCleanReq miss cycles 2551system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1624894996 # number of ReadSharedReq miss cycles 2552system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1624894996 # number of ReadSharedReq miss cycles 2553system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10682500 # number of demand (read+write) miss cycles 2554system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6004000 # number of demand (read+write) miss cycles 2555system.cpu1.l2cache.demand_miss_latency::cpu1.inst 916991000 # number of demand (read+write) miss cycles 2556system.cpu1.l2cache.demand_miss_latency::cpu1.data 3013062993 # number of demand (read+write) miss cycles 2557system.cpu1.l2cache.demand_miss_latency::total 3946740493 # number of demand (read+write) miss cycles 2558system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10682500 # number of overall miss cycles 2559system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6004000 # number of overall miss cycles 2560system.cpu1.l2cache.overall_miss_latency::cpu1.inst 916991000 # number of overall miss cycles 2561system.cpu1.l2cache.overall_miss_latency::cpu1.data 3013062993 # number of overall miss cycles 2562system.cpu1.l2cache.overall_miss_latency::total 3946740493 # number of overall miss cycles 2563system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17594 # number of ReadReq accesses(hits+misses) 2564system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6654 # number of ReadReq accesses(hits+misses) 2565system.cpu1.l2cache.ReadReq_accesses::total 24248 # number of ReadReq accesses(hits+misses) 2566system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113848 # number of WritebackDirty accesses(hits+misses) 2567system.cpu1.l2cache.WritebackDirty_accesses::total 113848 # number of WritebackDirty accesses(hits+misses) 2568system.cpu1.l2cache.WritebackClean_accesses::writebacks 650456 # number of WritebackClean accesses(hits+misses) 2569system.cpu1.l2cache.WritebackClean_accesses::total 650456 # number of WritebackClean accesses(hits+misses) 2570system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29684 # number of UpgradeReq accesses(hits+misses) 2571system.cpu1.l2cache.UpgradeReq_accesses::total 29684 # number of UpgradeReq accesses(hits+misses) 2572system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23429 # number of SCUpgradeReq accesses(hits+misses) 2573system.cpu1.l2cache.SCUpgradeReq_accesses::total 23429 # number of SCUpgradeReq accesses(hits+misses) 2574system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60872 # number of ReadExReq accesses(hits+misses) 2575system.cpu1.l2cache.ReadExReq_accesses::total 60872 # number of ReadExReq accesses(hits+misses) 2576system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 590024 # number of ReadCleanReq accesses(hits+misses) 2577system.cpu1.l2cache.ReadCleanReq_accesses::total 590024 # number of ReadCleanReq accesses(hits+misses) 2578system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 170520 # number of ReadSharedReq accesses(hits+misses) 2579system.cpu1.l2cache.ReadSharedReq_accesses::total 170520 # number of ReadSharedReq accesses(hits+misses) 2580system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17594 # number of demand (read+write) accesses 2581system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6654 # number of demand (read+write) accesses 2582system.cpu1.l2cache.demand_accesses::cpu1.inst 590024 # number of demand (read+write) accesses 2583system.cpu1.l2cache.demand_accesses::cpu1.data 231392 # number of demand (read+write) accesses 2584system.cpu1.l2cache.demand_accesses::total 845664 # number of demand (read+write) accesses 2585system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17594 # number of overall (read+write) accesses 2586system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6654 # number of overall (read+write) accesses 2587system.cpu1.l2cache.overall_accesses::cpu1.inst 590024 # number of overall (read+write) accesses 2588system.cpu1.l2cache.overall_accesses::cpu1.data 231392 # number of overall (read+write) accesses 2589system.cpu1.l2cache.overall_accesses::total 845664 # number of overall (read+write) accesses 2590system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.027680 # miss rate for ReadReq accesses 2591system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.044334 # miss rate for ReadReq accesses 2592system.cpu1.l2cache.ReadReq_miss_rate::total 0.032250 # miss rate for ReadReq accesses | 2492system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id 2493system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 2494system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id 2495system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8668 # Occupied blocks per task id 2496system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3318 # Occupied blocks per task id 2497system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019592 # Percentage of cache occupancy per task id 2498system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001648 # Percentage of cache occupancy per task id 2499system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.837585 # Percentage of cache occupancy per task id 2500system.cpu1.l2cache.tags.tag_accesses 27096059 # Number of tag accesses 2501system.cpu1.l2cache.tags.data_accesses 27096059 # Number of data accesses 2502system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2503system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16526 # number of ReadReq hits 2504system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5997 # number of ReadReq hits 2505system.cpu1.l2cache.ReadReq_hits::total 22523 # number of ReadReq hits 2506system.cpu1.l2cache.WritebackDirty_hits::writebacks 112708 # number of WritebackDirty hits 2507system.cpu1.l2cache.WritebackDirty_hits::total 112708 # number of WritebackDirty hits 2508system.cpu1.l2cache.WritebackClean_hits::writebacks 643666 # number of WritebackClean hits 2509system.cpu1.l2cache.WritebackClean_hits::total 643666 # number of WritebackClean hits 2510system.cpu1.l2cache.ReadExReq_hits::cpu1.data 26963 # number of ReadExReq hits 2511system.cpu1.l2cache.ReadExReq_hits::total 26963 # number of ReadExReq hits 2512system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 560151 # number of ReadCleanReq hits 2513system.cpu1.l2cache.ReadCleanReq_hits::total 560151 # number of ReadCleanReq hits 2514system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97699 # number of ReadSharedReq hits 2515system.cpu1.l2cache.ReadSharedReq_hits::total 97699 # number of ReadSharedReq hits 2516system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16526 # number of demand (read+write) hits 2517system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5997 # number of demand (read+write) hits 2518system.cpu1.l2cache.demand_hits::cpu1.inst 560151 # number of demand (read+write) hits 2519system.cpu1.l2cache.demand_hits::cpu1.data 124662 # number of demand (read+write) hits 2520system.cpu1.l2cache.demand_hits::total 707336 # number of demand (read+write) hits 2521system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16526 # number of overall hits 2522system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5997 # number of overall hits 2523system.cpu1.l2cache.overall_hits::cpu1.inst 560151 # number of overall hits 2524system.cpu1.l2cache.overall_hits::cpu1.data 124662 # number of overall hits 2525system.cpu1.l2cache.overall_hits::total 707336 # number of overall hits 2526system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 498 # number of ReadReq misses 2527system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 291 # number of ReadReq misses 2528system.cpu1.l2cache.ReadReq_misses::total 789 # number of ReadReq misses 2529system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29191 # number of UpgradeReq misses 2530system.cpu1.l2cache.UpgradeReq_misses::total 29191 # number of UpgradeReq misses 2531system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23465 # number of SCUpgradeReq misses 2532system.cpu1.l2cache.SCUpgradeReq_misses::total 23465 # number of SCUpgradeReq misses 2533system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33482 # number of ReadExReq misses 2534system.cpu1.l2cache.ReadExReq_misses::total 33482 # number of ReadExReq misses 2535system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 23849 # number of ReadCleanReq misses 2536system.cpu1.l2cache.ReadCleanReq_misses::total 23849 # number of ReadCleanReq misses 2537system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70829 # number of ReadSharedReq misses 2538system.cpu1.l2cache.ReadSharedReq_misses::total 70829 # number of ReadSharedReq misses 2539system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 498 # number of demand (read+write) misses 2540system.cpu1.l2cache.demand_misses::cpu1.itb.walker 291 # number of demand (read+write) misses 2541system.cpu1.l2cache.demand_misses::cpu1.inst 23849 # number of demand (read+write) misses 2542system.cpu1.l2cache.demand_misses::cpu1.data 104311 # number of demand (read+write) misses 2543system.cpu1.l2cache.demand_misses::total 128949 # number of demand (read+write) misses 2544system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 498 # number of overall misses 2545system.cpu1.l2cache.overall_misses::cpu1.itb.walker 291 # number of overall misses 2546system.cpu1.l2cache.overall_misses::cpu1.inst 23849 # number of overall misses 2547system.cpu1.l2cache.overall_misses::cpu1.data 104311 # number of overall misses 2548system.cpu1.l2cache.overall_misses::total 128949 # number of overall misses 2549system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11142500 # number of ReadReq miss cycles 2550system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5993500 # number of ReadReq miss cycles 2551system.cpu1.l2cache.ReadReq_miss_latency::total 17136000 # number of ReadReq miss cycles 2552system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12596500 # number of UpgradeReq miss cycles 2553system.cpu1.l2cache.UpgradeReq_miss_latency::total 12596500 # number of UpgradeReq miss cycles 2554system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 19283000 # number of SCUpgradeReq miss cycles 2555system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 19283000 # number of SCUpgradeReq miss cycles 2556system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 603000 # number of SCUpgradeFailReq miss cycles 2557system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 603000 # number of SCUpgradeFailReq miss cycles 2558system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1436185500 # number of ReadExReq miss cycles 2559system.cpu1.l2cache.ReadExReq_miss_latency::total 1436185500 # number of ReadExReq miss cycles 2560system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 937727500 # number of ReadCleanReq miss cycles 2561system.cpu1.l2cache.ReadCleanReq_miss_latency::total 937727500 # number of ReadCleanReq miss cycles 2562system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1638546999 # number of ReadSharedReq miss cycles 2563system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1638546999 # number of ReadSharedReq miss cycles 2564system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11142500 # number of demand (read+write) miss cycles 2565system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5993500 # number of demand (read+write) miss cycles 2566system.cpu1.l2cache.demand_miss_latency::cpu1.inst 937727500 # number of demand (read+write) miss cycles 2567system.cpu1.l2cache.demand_miss_latency::cpu1.data 3074732499 # number of demand (read+write) miss cycles 2568system.cpu1.l2cache.demand_miss_latency::total 4029595999 # number of demand (read+write) miss cycles 2569system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11142500 # number of overall miss cycles 2570system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5993500 # number of overall miss cycles 2571system.cpu1.l2cache.overall_miss_latency::cpu1.inst 937727500 # number of overall miss cycles 2572system.cpu1.l2cache.overall_miss_latency::cpu1.data 3074732499 # number of overall miss cycles 2573system.cpu1.l2cache.overall_miss_latency::total 4029595999 # number of overall miss cycles 2574system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17024 # number of ReadReq accesses(hits+misses) 2575system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6288 # number of ReadReq accesses(hits+misses) 2576system.cpu1.l2cache.ReadReq_accesses::total 23312 # number of ReadReq accesses(hits+misses) 2577system.cpu1.l2cache.WritebackDirty_accesses::writebacks 112708 # number of WritebackDirty accesses(hits+misses) 2578system.cpu1.l2cache.WritebackDirty_accesses::total 112708 # number of WritebackDirty accesses(hits+misses) 2579system.cpu1.l2cache.WritebackClean_accesses::writebacks 643666 # number of WritebackClean accesses(hits+misses) 2580system.cpu1.l2cache.WritebackClean_accesses::total 643666 # number of WritebackClean accesses(hits+misses) 2581system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29191 # number of UpgradeReq accesses(hits+misses) 2582system.cpu1.l2cache.UpgradeReq_accesses::total 29191 # number of UpgradeReq accesses(hits+misses) 2583system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23465 # number of SCUpgradeReq accesses(hits+misses) 2584system.cpu1.l2cache.SCUpgradeReq_accesses::total 23465 # number of SCUpgradeReq accesses(hits+misses) 2585system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60445 # number of ReadExReq accesses(hits+misses) 2586system.cpu1.l2cache.ReadExReq_accesses::total 60445 # number of ReadExReq accesses(hits+misses) 2587system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 584000 # number of ReadCleanReq accesses(hits+misses) 2588system.cpu1.l2cache.ReadCleanReq_accesses::total 584000 # number of ReadCleanReq accesses(hits+misses) 2589system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168528 # number of ReadSharedReq accesses(hits+misses) 2590system.cpu1.l2cache.ReadSharedReq_accesses::total 168528 # number of ReadSharedReq accesses(hits+misses) 2591system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17024 # number of demand (read+write) accesses 2592system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6288 # number of demand (read+write) accesses 2593system.cpu1.l2cache.demand_accesses::cpu1.inst 584000 # number of demand (read+write) accesses 2594system.cpu1.l2cache.demand_accesses::cpu1.data 228973 # number of demand (read+write) accesses 2595system.cpu1.l2cache.demand_accesses::total 836285 # number of demand (read+write) accesses 2596system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17024 # number of overall (read+write) accesses 2597system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6288 # number of overall (read+write) accesses 2598system.cpu1.l2cache.overall_accesses::cpu1.inst 584000 # number of overall (read+write) accesses 2599system.cpu1.l2cache.overall_accesses::cpu1.data 228973 # number of overall (read+write) accesses 2600system.cpu1.l2cache.overall_accesses::total 836285 # number of overall (read+write) accesses 2601system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for ReadReq accesses 2602system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046279 # miss rate for ReadReq accesses 2603system.cpu1.l2cache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses |
| 2593system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2594system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2595system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2596system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 2604system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2605system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2606system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2607system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 2597system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.557958 # miss rate for ReadExReq accesses 2598system.cpu1.l2cache.ReadExReq_miss_rate::total 0.557958 # miss rate for ReadExReq accesses 2599system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.041605 # miss rate for ReadCleanReq accesses 2600system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.041605 # miss rate for ReadCleanReq accesses 2601system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.418209 # miss rate for ReadSharedReq accesses 2602system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.418209 # miss rate for ReadSharedReq accesses 2603system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.027680 # miss rate for demand accesses 2604system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.044334 # miss rate for demand accesses 2605system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041605 # miss rate for demand accesses 2606system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.454973 # miss rate for demand accesses 2607system.cpu1.l2cache.demand_miss_rate::total 0.154443 # miss rate for demand accesses 2608system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.027680 # miss rate for overall accesses 2609system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.044334 # miss rate for overall accesses 2610system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041605 # miss rate for overall accesses 2611system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.454973 # miss rate for overall accesses 2612system.cpu1.l2cache.overall_miss_rate::total 0.154443 # miss rate for overall accesses 2613system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21935.318275 # average ReadReq miss latency 2614system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20352.542373 # average ReadReq miss latency 2615system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21338.235294 # average ReadReq miss latency 2616system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 461.713381 # average UpgradeReq miss latency 2617system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 461.713381 # average UpgradeReq miss latency 2618system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 890.370908 # average SCUpgradeReq miss latency 2619system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 890.370908 # average SCUpgradeReq miss latency | 2608system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.553925 # miss rate for ReadExReq accesses 2609system.cpu1.l2cache.ReadExReq_miss_rate::total 0.553925 # miss rate for ReadExReq accesses 2610system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040837 # miss rate for ReadCleanReq accesses 2611system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040837 # miss rate for ReadCleanReq accesses 2612system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.420280 # miss rate for ReadSharedReq accesses 2613system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.420280 # miss rate for ReadSharedReq accesses 2614system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for demand accesses 2615system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046279 # miss rate for demand accesses 2616system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040837 # miss rate for demand accesses 2617system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.455560 # miss rate for demand accesses 2618system.cpu1.l2cache.demand_miss_rate::total 0.154193 # miss rate for demand accesses 2619system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for overall accesses 2620system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046279 # miss rate for overall accesses 2621system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040837 # miss rate for overall accesses 2622system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.455560 # miss rate for overall accesses 2623system.cpu1.l2cache.overall_miss_rate::total 0.154193 # miss rate for overall accesses 2624system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average ReadReq miss latency 2625system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20596.219931 # average ReadReq miss latency 2626system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21718.631179 # average ReadReq miss latency 2627system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 431.519989 # average UpgradeReq miss latency 2628system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 431.519989 # average UpgradeReq miss latency 2629system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 821.777115 # average SCUpgradeReq miss latency 2630system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 821.777115 # average SCUpgradeReq miss latency |
| 2620system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2621system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 2631system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2632system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 2622system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40871.746467 # average ReadExReq miss latency 2623system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40871.746467 # average ReadExReq miss latency 2624system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37355.018739 # average ReadCleanReq miss latency 2625system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37355.018739 # average ReadCleanReq miss latency 2626system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22785.396716 # average ReadSharedReq miss latency 2627system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22785.396716 # average ReadSharedReq miss latency 2628system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21935.318275 # average overall miss latency 2629system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20352.542373 # average overall miss latency 2630system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37355.018739 # average overall miss latency 2631system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28620.334859 # average overall miss latency 2632system.cpu1.l2cache.demand_avg_miss_latency::total 30218.445359 # average overall miss latency 2633system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21935.318275 # average overall miss latency 2634system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20352.542373 # average overall miss latency 2635system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37355.018739 # average overall miss latency 2636system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28620.334859 # average overall miss latency 2637system.cpu1.l2cache.overall_avg_miss_latency::total 30218.445359 # average overall miss latency 2638system.cpu1.l2cache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked | 2633system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42894.256615 # average ReadExReq miss latency 2634system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42894.256615 # average ReadExReq miss latency 2635system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39319.363495 # average ReadCleanReq miss latency 2636system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39319.363495 # average ReadCleanReq miss latency 2637system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23133.843468 # average ReadSharedReq miss latency 2638system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23133.843468 # average ReadSharedReq miss latency 2639system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average overall miss latency 2640system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20596.219931 # average overall miss latency 2641system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39319.363495 # average overall miss latency 2642system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29476.589228 # average overall miss latency 2643system.cpu1.l2cache.demand_avg_miss_latency::total 31249.532753 # average overall miss latency 2644system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average overall miss latency 2645system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20596.219931 # average overall miss latency 2646system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39319.363495 # average overall miss latency 2647system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29476.589228 # average overall miss latency 2648system.cpu1.l2cache.overall_avg_miss_latency::total 31249.532753 # average overall miss latency 2649system.cpu1.l2cache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked |
| 2639system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2650system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2640system.cpu1.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked | 2651system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 2641system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2652system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2642system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked | 2653system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked |
| 2643system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2654system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2644system.cpu1.l2cache.unused_prefetches 797 # number of HardPF blocks evicted w/o reference 2645system.cpu1.l2cache.writebacks::writebacks 31759 # number of writebacks 2646system.cpu1.l2cache.writebacks::total 31759 # number of writebacks 2647system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 2648system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 2649system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 426 # number of ReadExReq MSHR hits 2650system.cpu1.l2cache.ReadExReq_mshr_hits::total 426 # number of ReadExReq MSHR hits | 2655system.cpu1.l2cache.unused_prefetches 817 # number of HardPF blocks evicted w/o reference 2656system.cpu1.l2cache.writebacks::writebacks 30888 # number of writebacks 2657system.cpu1.l2cache.writebacks::total 30888 # number of writebacks 2658system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2659system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2660system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 456 # number of ReadExReq MSHR hits 2661system.cpu1.l2cache.ReadExReq_mshr_hits::total 456 # number of ReadExReq MSHR hits |
| 2651system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits 2652system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits | 2662system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits 2663system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits |
| 2653system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits 2654system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits 2655system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits | 2664system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 69 # number of ReadSharedReq MSHR hits 2665system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 69 # number of ReadSharedReq MSHR hits 2666system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits |
| 2656system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits | 2667system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits |
| 2657system.cpu1.l2cache.demand_mshr_hits::cpu1.data 500 # number of demand (read+write) MSHR hits 2658system.cpu1.l2cache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits 2659system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits | 2668system.cpu1.l2cache.demand_mshr_hits::cpu1.data 525 # number of demand (read+write) MSHR hits 2669system.cpu1.l2cache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits 2670system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits |
| 2660system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits | 2671system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits |
| 2661system.cpu1.l2cache.overall_mshr_hits::cpu1.data 500 # number of overall MSHR hits 2662system.cpu1.l2cache.overall_mshr_hits::total 511 # number of overall MSHR hits 2663system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 487 # number of ReadReq MSHR misses 2664system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 293 # number of ReadReq MSHR misses 2665system.cpu1.l2cache.ReadReq_mshr_misses::total 780 # number of ReadReq MSHR misses 2666system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24893 # number of HardPFReq MSHR misses 2667system.cpu1.l2cache.HardPFReq_mshr_misses::total 24893 # number of HardPFReq MSHR misses 2668system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29684 # number of UpgradeReq MSHR misses 2669system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29684 # number of UpgradeReq MSHR misses 2670system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23429 # number of SCUpgradeReq MSHR misses 2671system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23429 # number of SCUpgradeReq MSHR misses 2672system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33538 # number of ReadExReq MSHR misses 2673system.cpu1.l2cache.ReadExReq_mshr_misses::total 33538 # number of ReadExReq MSHR misses 2674system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 24539 # number of ReadCleanReq MSHR misses 2675system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 24539 # number of ReadCleanReq MSHR misses 2676system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71239 # number of ReadSharedReq MSHR misses 2677system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71239 # number of ReadSharedReq MSHR misses 2678system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 487 # number of demand (read+write) MSHR misses 2679system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 293 # number of demand (read+write) MSHR misses 2680system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 24539 # number of demand (read+write) MSHR misses 2681system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104777 # number of demand (read+write) MSHR misses 2682system.cpu1.l2cache.demand_mshr_misses::total 130096 # number of demand (read+write) MSHR misses 2683system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 487 # number of overall MSHR misses 2684system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 293 # number of overall MSHR misses 2685system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 24539 # number of overall MSHR misses 2686system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104777 # number of overall MSHR misses 2687system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24893 # number of overall MSHR misses 2688system.cpu1.l2cache.overall_mshr_misses::total 154989 # number of overall MSHR misses | 2672system.cpu1.l2cache.overall_mshr_hits::cpu1.data 525 # number of overall MSHR hits 2673system.cpu1.l2cache.overall_mshr_hits::total 535 # number of overall MSHR hits 2674system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 498 # number of ReadReq MSHR misses 2675system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 290 # number of ReadReq MSHR misses 2676system.cpu1.l2cache.ReadReq_mshr_misses::total 788 # number of ReadReq MSHR misses 2677system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25130 # number of HardPFReq MSHR misses 2678system.cpu1.l2cache.HardPFReq_mshr_misses::total 25130 # number of HardPFReq MSHR misses 2679system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29191 # number of UpgradeReq MSHR misses 2680system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29191 # number of UpgradeReq MSHR misses 2681system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23465 # number of SCUpgradeReq MSHR misses 2682system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23465 # number of SCUpgradeReq MSHR misses 2683system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33026 # number of ReadExReq MSHR misses 2684system.cpu1.l2cache.ReadExReq_mshr_misses::total 33026 # number of ReadExReq MSHR misses 2685system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 23840 # number of ReadCleanReq MSHR misses 2686system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 23840 # number of ReadCleanReq MSHR misses 2687system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70760 # number of ReadSharedReq MSHR misses 2688system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70760 # number of ReadSharedReq MSHR misses 2689system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 498 # number of demand (read+write) MSHR misses 2690system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 290 # number of demand (read+write) MSHR misses 2691system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 23840 # number of demand (read+write) MSHR misses 2692system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103786 # number of demand (read+write) MSHR misses 2693system.cpu1.l2cache.demand_mshr_misses::total 128414 # number of demand (read+write) MSHR misses 2694system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 498 # number of overall MSHR misses 2695system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 290 # number of overall MSHR misses 2696system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 23840 # number of overall MSHR misses 2697system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103786 # number of overall MSHR misses 2698system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25130 # number of overall MSHR misses 2699system.cpu1.l2cache.overall_mshr_misses::total 153544 # number of overall MSHR misses |
| 2689system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable | 2700system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable |
| 2690system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable 2691system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14618 # number of ReadReq MSHR uncacheable 2692system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable 2693system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable | 2701system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable 2702system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3487 # number of ReadReq MSHR uncacheable 2703system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable 2704system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable |
| 2694system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses | 2705system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses |
| 2695system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses 2696system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26473 # number of overall MSHR uncacheable misses 2697system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of ReadReq MSHR miss cycles 2698system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4210000 # number of ReadReq MSHR miss cycles 2699system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11970500 # number of ReadReq MSHR miss cycles 2700system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1022179654 # number of HardPFReq MSHR miss cycles 2701system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1022179654 # number of HardPFReq MSHR miss cycles 2702system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 459449500 # number of UpgradeReq MSHR miss cycles 2703system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 459449500 # number of UpgradeReq MSHR miss cycles 2704system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 351583000 # number of SCUpgradeReq MSHR miss cycles 2705system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 351583000 # number of SCUpgradeReq MSHR miss cycles 2706system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 132500 # number of SCUpgradeFailReq MSHR miss cycles 2707system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 132500 # number of SCUpgradeFailReq MSHR miss cycles 2708system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1131738499 # number of ReadExReq MSHR miss cycles 2709system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1131738499 # number of ReadExReq MSHR miss cycles 2710system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 769613500 # number of ReadCleanReq MSHR miss cycles 2711system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 769613500 # number of ReadCleanReq MSHR miss cycles 2712system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1195688496 # number of ReadSharedReq MSHR miss cycles 2713system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1195688496 # number of ReadSharedReq MSHR miss cycles 2714system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of demand (read+write) MSHR miss cycles 2715system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4210000 # number of demand (read+write) MSHR miss cycles 2716system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 769613500 # number of demand (read+write) MSHR miss cycles 2717system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2327426995 # number of demand (read+write) MSHR miss cycles 2718system.cpu1.l2cache.demand_mshr_miss_latency::total 3109010995 # number of demand (read+write) MSHR miss cycles 2719system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of overall MSHR miss cycles 2720system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4210000 # number of overall MSHR miss cycles 2721system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 769613500 # number of overall MSHR miss cycles 2722system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2327426995 # number of overall MSHR miss cycles 2723system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1022179654 # number of overall MSHR miss cycles 2724system.cpu1.l2cache.overall_mshr_miss_latency::total 4131190649 # number of overall MSHR miss cycles 2725system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7990000 # number of ReadReq MSHR uncacheable cycles 2726system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412179500 # number of ReadReq MSHR uncacheable cycles 2727system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2420169500 # number of ReadReq MSHR uncacheable cycles 2728system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7990000 # number of overall MSHR uncacheable cycles 2729system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412179500 # number of overall MSHR uncacheable cycles 2730system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2420169500 # number of overall MSHR uncacheable cycles 2731system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for ReadReq accesses 2732system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for ReadReq accesses 2733system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032168 # mshr miss rate for ReadReq accesses | 2706system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses 2707system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 6227 # number of overall MSHR uncacheable misses 2708system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of ReadReq MSHR miss cycles 2709system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4235000 # number of ReadReq MSHR miss cycles 2710system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12389500 # number of ReadReq MSHR miss cycles 2711system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1120294346 # number of HardPFReq MSHR miss cycles 2712system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1120294346 # number of HardPFReq MSHR miss cycles 2713system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 448208500 # number of UpgradeReq MSHR miss cycles 2714system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 448208500 # number of UpgradeReq MSHR miss cycles 2715system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 351353500 # number of SCUpgradeReq MSHR miss cycles 2716system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 351353500 # number of SCUpgradeReq MSHR miss cycles 2717system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 513000 # number of SCUpgradeFailReq MSHR miss cycles 2718system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 513000 # number of SCUpgradeFailReq MSHR miss cycles 2719system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1175287000 # number of ReadExReq MSHR miss cycles 2720system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1175287000 # number of ReadExReq MSHR miss cycles 2721system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 794529500 # number of ReadCleanReq MSHR miss cycles 2722system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 794529500 # number of ReadCleanReq MSHR miss cycles 2723system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1211572499 # number of ReadSharedReq MSHR miss cycles 2724system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1211572499 # number of ReadSharedReq MSHR miss cycles 2725system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of demand (read+write) MSHR miss cycles 2726system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4235000 # number of demand (read+write) MSHR miss cycles 2727system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 794529500 # number of demand (read+write) MSHR miss cycles 2728system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2386859499 # number of demand (read+write) MSHR miss cycles 2729system.cpu1.l2cache.demand_mshr_miss_latency::total 3193778499 # number of demand (read+write) MSHR miss cycles 2730system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of overall MSHR miss cycles 2731system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4235000 # number of overall MSHR miss cycles 2732system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 794529500 # number of overall MSHR miss cycles 2733system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2386859499 # number of overall MSHR miss cycles 2734system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1120294346 # number of overall MSHR miss cycles 2735system.cpu1.l2cache.overall_mshr_miss_latency::total 4314072845 # number of overall MSHR miss cycles 2736system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8564000 # number of ReadReq MSHR uncacheable cycles 2737system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 432303000 # number of ReadReq MSHR uncacheable cycles 2738system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 440867000 # number of ReadReq MSHR uncacheable cycles 2739system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8564000 # number of overall MSHR uncacheable cycles 2740system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 432303000 # number of overall MSHR uncacheable cycles 2741system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 440867000 # number of overall MSHR uncacheable cycles 2742system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for ReadReq accesses 2743system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for ReadReq accesses 2744system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033802 # mshr miss rate for ReadReq accesses |
| 2734system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2735system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2736system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2737system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2738system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2739system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 2745system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2746system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2747system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2748system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2749system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2750system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 2740system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550959 # mshr miss rate for ReadExReq accesses 2741system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550959 # mshr miss rate for ReadExReq accesses 2742system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for ReadCleanReq accesses 2743system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041590 # mshr miss rate for ReadCleanReq accesses 2744system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.417775 # mshr miss rate for ReadSharedReq accesses 2745system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.417775 # mshr miss rate for ReadSharedReq accesses 2746system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for demand accesses 2747system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for demand accesses 2748system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for demand accesses 2749system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for demand accesses 2750system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153839 # mshr miss rate for demand accesses 2751system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for overall accesses 2752system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for overall accesses 2753system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for overall accesses 2754system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for overall accesses | 2751system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546381 # mshr miss rate for ReadExReq accesses 2752system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546381 # mshr miss rate for ReadExReq accesses 2753system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for ReadCleanReq accesses 2754system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040822 # mshr miss rate for ReadCleanReq accesses 2755system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.419871 # mshr miss rate for ReadSharedReq accesses 2756system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.419871 # mshr miss rate for ReadSharedReq accesses 2757system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for demand accesses 2758system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for demand accesses 2759system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for demand accesses 2760system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for demand accesses 2761system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153553 # mshr miss rate for demand accesses 2762system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for overall accesses 2763system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for overall accesses 2764system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for overall accesses 2765system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for overall accesses |
| 2755system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2766system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2756system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183275 # mshr miss rate for overall accesses 2757system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average ReadReq mshr miss latency 2758system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average ReadReq mshr miss latency 2759system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872 # average ReadReq mshr miss latency 2760system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average HardPFReq mshr miss latency 2761system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524 # average HardPFReq mshr miss latency 2762system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461 # average UpgradeReq mshr miss latency 2763system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461 # average UpgradeReq mshr miss latency 2764system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958 # average SCUpgradeReq mshr miss latency 2765system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958 # average SCUpgradeReq mshr miss latency | 2767system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183602 # mshr miss rate for overall accesses 2768system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average ReadReq mshr miss latency 2769system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average ReadReq mshr miss latency 2770system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15722.715736 # average ReadReq mshr miss latency 2771system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average HardPFReq mshr miss latency 2772system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44579.958058 # average HardPFReq mshr miss latency 2773system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15354.338666 # average UpgradeReq mshr miss latency 2774system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15354.338666 # average UpgradeReq mshr miss latency 2775system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14973.513744 # average SCUpgradeReq mshr miss latency 2776system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14973.513744 # average SCUpgradeReq mshr miss latency |
| 2766system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2767system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 2777system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2778system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 2768system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910 # average ReadExReq mshr miss latency 2769system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910 # average ReadExReq mshr miss latency 2770system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average ReadCleanReq mshr miss latency 2771system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348 # average ReadCleanReq mshr miss latency 2772system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169 # average ReadSharedReq mshr miss latency 2773system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169 # average ReadSharedReq mshr miss latency 2774system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency 2775system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency 2776system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency 2777system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency 2778system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570 # average overall mshr miss latency 2779system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency 2780system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency 2781system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency 2782system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency 2783system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average overall mshr miss latency 2784system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523 # average overall mshr miss latency 2785system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average ReadReq mshr uncacheable latency 2786system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812 # average ReadReq mshr uncacheable latency 2787system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046 # average ReadReq mshr uncacheable latency 2788system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average overall mshr uncacheable latency 2789system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534 # average overall mshr uncacheable latency 2790system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151 # average overall mshr uncacheable latency 2791system.cpu1.toL2Bus.snoop_filter.tot_requests 1661462 # Total number of requests made to the snoop filter. 2792system.cpu1.toL2Bus.snoop_filter.hit_single_requests 840058 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2793system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12360 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2794system.cpu1.toL2Bus.snoop_filter.tot_snoops 115637 # Total number of snoops made to the snoop filter. 2795system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106952 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2796system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8685 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2797system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 2798system.cpu1.toL2Bus.trans_dist::ReadReq 43235 # Transaction distribution 2799system.cpu1.toL2Bus.trans_dist::ReadResp 842502 # Transaction distribution 2800system.cpu1.toL2Bus.trans_dist::WriteReq 11855 # Transaction distribution 2801system.cpu1.toL2Bus.trans_dist::WriteResp 11855 # Transaction distribution 2802system.cpu1.toL2Bus.trans_dist::WritebackDirty 146735 # Transaction distribution 2803system.cpu1.toL2Bus.trans_dist::WritebackClean 662812 # Transaction distribution 2804system.cpu1.toL2Bus.trans_dist::CleanEvict 29649 # Transaction distribution 2805system.cpu1.toL2Bus.trans_dist::HardPFReq 30154 # Transaction distribution 2806system.cpu1.toL2Bus.trans_dist::UpgradeReq 72596 # Transaction distribution 2807system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41626 # Transaction distribution 2808system.cpu1.toL2Bus.trans_dist::UpgradeResp 86297 # Transaction distribution 2809system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution 2810system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution 2811system.cpu1.toL2Bus.trans_dist::ReadExReq 68185 # Transaction distribution 2812system.cpu1.toL2Bus.trans_dist::ReadExResp 65527 # Transaction distribution 2813system.cpu1.toL2Bus.trans_dist::ReadCleanReq 590026 # Transaction distribution 2814system.cpu1.toL2Bus.trans_dist::ReadSharedReq 275295 # Transaction distribution 2815system.cpu1.toL2Bus.trans_dist::InvalidateReq 251 # Transaction distribution 2816system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1769762 # Packet count per connected master and slave (bytes) 2817system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885483 # Packet count per connected master and slave (bytes) 2818system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14740 # Packet count per connected master and slave (bytes) 2819system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38125 # Packet count per connected master and slave (bytes) 2820system.cpu1.toL2Bus.pkt_count::total 2708110 # Packet count per connected master and slave (bytes) 2821system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75491792 # Cumulative packet size per connected master and slave (bytes) 2822system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29665722 # Cumulative packet size per connected master and slave (bytes) 2823system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26616 # Cumulative packet size per connected master and slave (bytes) 2824system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70376 # Cumulative packet size per connected master and slave (bytes) 2825system.cpu1.toL2Bus.pkt_size::total 105254506 # Cumulative packet size per connected master and slave (bytes) 2826system.cpu1.toL2Bus.snoops 347103 # Total snoops (count) 2827system.cpu1.toL2Bus.snoopTraffic 4899396 # Total snoop traffic (bytes) 2828system.cpu1.toL2Bus.snoop_fanout::samples 1195777 # Request fanout histogram 2829system.cpu1.toL2Bus.snoop_fanout::mean 0.122893 # Request fanout histogram 2830system.cpu1.toL2Bus.snoop_fanout::stdev 0.349738 # Request fanout histogram | 2779system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35586.719554 # average ReadExReq mshr miss latency 2780system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35586.719554 # average ReadExReq mshr miss latency 2781system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average ReadCleanReq mshr miss latency 2782system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33327.579698 # average ReadCleanReq mshr miss latency 2783system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17122.279522 # average ReadSharedReq mshr miss latency 2784system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17122.279522 # average ReadSharedReq mshr miss latency 2785system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency 2786system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency 2787system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency 2788system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency 2789system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24870.952536 # average overall mshr miss latency 2790system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency 2791system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency 2792system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency 2793system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency 2794system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average overall mshr miss latency 2795system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28096.655324 # average overall mshr miss latency 2796system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average ReadReq mshr uncacheable latency 2797system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127673.656232 # average ReadReq mshr uncacheable latency 2798system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126431.603097 # average ReadReq mshr uncacheable latency 2799system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average overall mshr uncacheable latency 2800system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 70568.560235 # average overall mshr uncacheable latency 2801system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70799.261282 # average overall mshr uncacheable latency 2802system.cpu1.toL2Bus.snoop_filter.tot_requests 1644268 # Total number of requests made to the snoop filter. 2803system.cpu1.toL2Bus.snoop_filter.hit_single_requests 831312 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2804system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2805system.cpu1.toL2Bus.snoop_filter.tot_snoops 115055 # Total number of snoops made to the snoop filter. 2806system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106415 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2807system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8640 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2808system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 2809system.cpu1.toL2Bus.trans_dist::ReadReq 31394 # Transaction distribution 2810system.cpu1.toL2Bus.trans_dist::ReadResp 822139 # Transaction distribution 2811system.cpu1.toL2Bus.trans_dist::WriteReq 2740 # Transaction distribution 2812system.cpu1.toL2Bus.trans_dist::WriteResp 2740 # Transaction distribution 2813system.cpu1.toL2Bus.trans_dist::WritebackDirty 144852 # Transaction distribution 2814system.cpu1.toL2Bus.trans_dist::WritebackClean 655914 # Transaction distribution 2815system.cpu1.toL2Bus.trans_dist::CleanEvict 29483 # Transaction distribution 2816system.cpu1.toL2Bus.trans_dist::HardPFReq 30330 # Transaction distribution 2817system.cpu1.toL2Bus.trans_dist::UpgradeReq 71834 # Transaction distribution 2818system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution 2819system.cpu1.toL2Bus.trans_dist::UpgradeResp 85505 # Transaction distribution 2820system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution 2821system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution 2822system.cpu1.toL2Bus.trans_dist::ReadExReq 67721 # Transaction distribution 2823system.cpu1.toL2Bus.trans_dist::ReadExResp 64923 # Transaction distribution 2824system.cpu1.toL2Bus.trans_dist::ReadCleanReq 584003 # Transaction distribution 2825system.cpu1.toL2Bus.trans_dist::ReadSharedReq 271211 # Transaction distribution 2826system.cpu1.toL2Bus.trans_dist::InvalidateReq 307 # Transaction distribution 2827system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1751691 # Packet count per connected master and slave (bytes) 2828system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 836213 # Packet count per connected master and slave (bytes) 2829system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14098 # Packet count per connected master and slave (bytes) 2830system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37121 # Packet count per connected master and slave (bytes) 2831system.cpu1.toL2Bus.pkt_count::total 2639123 # Packet count per connected master and slave (bytes) 2832system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74720720 # Cumulative packet size per connected master and slave (bytes) 2833system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29257698 # Cumulative packet size per connected master and slave (bytes) 2834system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25152 # Cumulative packet size per connected master and slave (bytes) 2835system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68096 # Cumulative packet size per connected master and slave (bytes) 2836system.cpu1.toL2Bus.pkt_size::total 104071666 # Cumulative packet size per connected master and slave (bytes) 2837system.cpu1.toL2Bus.snoops 343275 # Total snoops (count) 2838system.cpu1.toL2Bus.snoopTraffic 4808780 # Total snoop traffic (bytes) 2839system.cpu1.toL2Bus.snoop_fanout::samples 1162877 # Request fanout histogram 2840system.cpu1.toL2Bus.snoop_fanout::mean 0.125522 # Request fanout histogram 2841system.cpu1.toL2Bus.snoop_fanout::stdev 0.353024 # Request fanout histogram |
| 2831system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2842system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2832system.cpu1.toL2Bus.snoop_fanout::0 1057509 88.44% 88.44% # Request fanout histogram 2833system.cpu1.toL2Bus.snoop_fanout::1 129583 10.84% 99.27% # Request fanout histogram 2834system.cpu1.toL2Bus.snoop_fanout::2 8685 0.73% 100.00% # Request fanout histogram | 2843system.cpu1.toL2Bus.snoop_fanout::0 1025550 88.19% 88.19% # Request fanout histogram 2844system.cpu1.toL2Bus.snoop_fanout::1 128687 11.07% 99.26% # Request fanout histogram 2845system.cpu1.toL2Bus.snoop_fanout::2 8640 0.74% 100.00% # Request fanout histogram |
| 2835system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2836system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2837system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2846system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2847system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2848system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2838system.cpu1.toL2Bus.snoop_fanout::total 1195777 # Request fanout histogram 2839system.cpu1.toL2Bus.reqLayer0.occupancy 1635737987 # Layer occupancy (ticks) | 2849system.cpu1.toL2Bus.snoop_fanout::total 1162877 # Request fanout histogram 2850system.cpu1.toL2Bus.reqLayer0.occupancy 1604189995 # Layer occupancy (ticks) |
| 2840system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 2851system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 2841system.cpu1.toL2Bus.snoopLayer0.occupancy 81718473 # Layer occupancy (ticks) | 2852system.cpu1.toL2Bus.snoopLayer0.occupancy 80522049 # Layer occupancy (ticks) |
| 2842system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2853system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2843system.cpu1.toL2Bus.respLayer0.occupancy 885241795 # Layer occupancy (ticks) | 2854system.cpu1.toL2Bus.respLayer0.occupancy 876204799 # Layer occupancy (ticks) |
| 2844system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2855system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2845system.cpu1.toL2Bus.respLayer1.occupancy 395391898 # Layer occupancy (ticks) | 2856system.cpu1.toL2Bus.respLayer1.occupancy 375699214 # Layer occupancy (ticks) |
| 2846system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2857system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2847system.cpu1.toL2Bus.respLayer2.occupancy 8093984 # Layer occupancy (ticks) | 2858system.cpu1.toL2Bus.respLayer2.occupancy 7819481 # Layer occupancy (ticks) |
| 2848system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2859system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2849system.cpu1.toL2Bus.respLayer3.occupancy 20543974 # Layer occupancy (ticks) | 2860system.cpu1.toL2Bus.respLayer3.occupancy 20111970 # Layer occupancy (ticks) |
| 2850system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2861system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2851system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 2862system.iobus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 2852system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2853system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2854system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2855system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2856system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2857system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2858system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2859system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 2894system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2895system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2896system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2897system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2898system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) 2899system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2900system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2901system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) | 2863system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2864system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2865system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2866system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2867system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2868system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2869system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2870system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 2905system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2906system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2907system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2908system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2909system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) 2910system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2911system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2912system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) |
| 2902system.iobus.reqLayer0.occupancy 40381000 # Layer occupancy (ticks) | 2913system.iobus.reqLayer0.occupancy 40380000 # Layer occupancy (ticks) |
| 2903system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2914system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2904system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) | 2915system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) |
| 2905system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2916system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2906system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) | 2917system.iobus.reqLayer2.occupancy 328000 # Layer occupancy (ticks) |
| 2907system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2908system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) 2909system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 2918system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2919system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) 2920system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 2910system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) | 2921system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) |
| 2911system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 2922system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 2912system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) | 2923system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) |
| 2913system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 2924system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 2914system.iobus.reqLayer8.occupancy 575500 # Layer occupancy (ticks) | 2925system.iobus.reqLayer8.occupancy 570500 # Layer occupancy (ticks) |
| 2915system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2916system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2917system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2918system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2919system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 2926system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2927system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2928system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2929system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2930system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 2920system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) | 2931system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) |
| 2921system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2922system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2923system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 2932system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2933system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2934system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 2924system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) | 2935system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) |
| 2925system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2926system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2927system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 2936system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2937system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2938system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 2928system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) | 2939system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) |
| 2929system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2930system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2931system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2932system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2933system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2934system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2935system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 2940system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2941system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2942system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2943system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2944system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2945system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2946system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 2936system.iobus.reqLayer23.occupancy 6080500 # Layer occupancy (ticks) | 2947system.iobus.reqLayer23.occupancy 6100500 # Layer occupancy (ticks) |
| 2937system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 2948system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 2938system.iobus.reqLayer24.occupancy 33803000 # Layer occupancy (ticks) | 2949system.iobus.reqLayer24.occupancy 33792000 # Layer occupancy (ticks) |
| 2939system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 2950system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 2940system.iobus.reqLayer25.occupancy 187681355 # Layer occupancy (ticks) | 2951system.iobus.reqLayer25.occupancy 187796551 # Layer occupancy (ticks) |
| 2941system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2942system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) 2943system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2944system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2945system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2952system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2953system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) 2954system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2955system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2956system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2946system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 2957system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 2947system.iocache.tags.replacements 36458 # number of replacements | 2958system.iocache.tags.replacements 36458 # number of replacements |
| 2948system.iocache.tags.tagsinuse 14.555440 # Cycle average of tags in use | 2959system.iocache.tags.tagsinuse 14.553749 # Cycle average of tags in use |
| 2949system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2950system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2951system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2960system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2961system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2962system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2952system.iocache.tags.warmup_cycle 255145986000 # Cycle when the warmup percentage was hit. 2953system.iocache.tags.occ_blocks::realview.ide 14.555440 # Average occupied blocks per requestor 2954system.iocache.tags.occ_percent::realview.ide 0.909715 # Average percentage of cache occupancy 2955system.iocache.tags.occ_percent::total 0.909715 # Average percentage of cache occupancy | 2963system.iocache.tags.warmup_cycle 255488373000 # Cycle when the warmup percentage was hit. 2964system.iocache.tags.occ_blocks::realview.ide 14.553749 # Average occupied blocks per requestor 2965system.iocache.tags.occ_percent::realview.ide 0.909609 # Average percentage of cache occupancy 2966system.iocache.tags.occ_percent::total 0.909609 # Average percentage of cache occupancy |
| 2956system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2957system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2958system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2959system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2960system.iocache.tags.data_accesses 328284 # Number of data accesses | 2967system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2968system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2969system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2970system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2971system.iocache.tags.data_accesses 328284 # Number of data accesses |
| 2961system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 2972system.iocache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 2962system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2963system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2964system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2965system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2966system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2967system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2968system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2969system.iocache.overall_misses::total 36476 # number of overall misses | 2973system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2974system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2975system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2976system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2977system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2978system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2979system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2980system.iocache.overall_misses::total 36476 # number of overall misses |
| 2970system.iocache.ReadReq_miss_latency::realview.ide 32543877 # number of ReadReq miss cycles 2971system.iocache.ReadReq_miss_latency::total 32543877 # number of ReadReq miss cycles 2972system.iocache.WriteLineReq_miss_latency::realview.ide 4303510478 # number of WriteLineReq miss cycles 2973system.iocache.WriteLineReq_miss_latency::total 4303510478 # number of WriteLineReq miss cycles 2974system.iocache.demand_miss_latency::realview.ide 4336054355 # number of demand (read+write) miss cycles 2975system.iocache.demand_miss_latency::total 4336054355 # number of demand (read+write) miss cycles 2976system.iocache.overall_miss_latency::realview.ide 4336054355 # number of overall miss cycles 2977system.iocache.overall_miss_latency::total 4336054355 # number of overall miss cycles | 2981system.iocache.ReadReq_miss_latency::realview.ide 40604377 # number of ReadReq miss cycles 2982system.iocache.ReadReq_miss_latency::total 40604377 # number of ReadReq miss cycles 2983system.iocache.WriteLineReq_miss_latency::realview.ide 4366091174 # number of WriteLineReq miss cycles 2984system.iocache.WriteLineReq_miss_latency::total 4366091174 # number of WriteLineReq miss cycles 2985system.iocache.demand_miss_latency::realview.ide 4406695551 # number of demand (read+write) miss cycles 2986system.iocache.demand_miss_latency::total 4406695551 # number of demand (read+write) miss cycles 2987system.iocache.overall_miss_latency::realview.ide 4406695551 # number of overall miss cycles 2988system.iocache.overall_miss_latency::total 4406695551 # number of overall miss cycles |
| 2978system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2979system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2980system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2981system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2982system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 2983system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 2984system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 2985system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 2986system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2987system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2988system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2989system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2990system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2991system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2992system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2993system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2989system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2990system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2991system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2992system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2993system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 2994system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 2995system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 2996system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 2997system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2998system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2999system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3000system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3001system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3002system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3003system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3004system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2994system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048 # average ReadReq miss latency 2995system.iocache.ReadReq_avg_miss_latency::total 129142.369048 # average ReadReq miss latency 2996system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669 # average WriteLineReq miss latency 2997system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669 # average WriteLineReq miss latency 2998system.iocache.demand_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency 2999system.iocache.demand_avg_miss_latency::total 118874.173566 # average overall miss latency 3000system.iocache.overall_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency 3001system.iocache.overall_avg_miss_latency::total 118874.173566 # average overall miss latency 3002system.iocache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked | 3005system.iocache.ReadReq_avg_miss_latency::realview.ide 161128.480159 # average ReadReq miss latency 3006system.iocache.ReadReq_avg_miss_latency::total 161128.480159 # average ReadReq miss latency 3007system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120530.343805 # average WriteLineReq miss latency 3008system.iocache.WriteLineReq_avg_miss_latency::total 120530.343805 # average WriteLineReq miss latency 3009system.iocache.demand_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency 3010system.iocache.demand_avg_miss_latency::total 120810.822212 # average overall miss latency 3011system.iocache.overall_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency 3012system.iocache.overall_avg_miss_latency::total 120810.822212 # average overall miss latency 3013system.iocache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked |
| 3003system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3014system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3004system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked | 3015system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 3005system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 3016system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 3006system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked | 3017system.iocache.avg_blocked_cycles::no_mshrs 5.750000 # average number of cycles each access was blocked |
| 3007system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3008system.iocache.writebacks::writebacks 36206 # number of writebacks 3009system.iocache.writebacks::total 36206 # number of writebacks 3010system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3011system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3012system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3013system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3014system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 3015system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 3016system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 3017system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses | 3018system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3019system.iocache.writebacks::writebacks 36206 # number of writebacks 3020system.iocache.writebacks::total 36206 # number of writebacks 3021system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3022system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3023system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3024system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3025system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 3026system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 3027system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 3028system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses |
| 3018system.iocache.ReadReq_mshr_miss_latency::realview.ide 19943877 # number of ReadReq MSHR miss cycles 3019system.iocache.ReadReq_mshr_miss_latency::total 19943877 # number of ReadReq MSHR miss cycles 3020system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489987873 # number of WriteLineReq MSHR miss cycles 3021system.iocache.WriteLineReq_mshr_miss_latency::total 2489987873 # number of WriteLineReq MSHR miss cycles 3022system.iocache.demand_mshr_miss_latency::realview.ide 2509931750 # number of demand (read+write) MSHR miss cycles 3023system.iocache.demand_mshr_miss_latency::total 2509931750 # number of demand (read+write) MSHR miss cycles 3024system.iocache.overall_mshr_miss_latency::realview.ide 2509931750 # number of overall MSHR miss cycles 3025system.iocache.overall_mshr_miss_latency::total 2509931750 # number of overall MSHR miss cycles | 3029system.iocache.ReadReq_mshr_miss_latency::realview.ide 28004377 # number of ReadReq MSHR miss cycles 3030system.iocache.ReadReq_mshr_miss_latency::total 28004377 # number of ReadReq MSHR miss cycles 3031system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2552566881 # number of WriteLineReq MSHR miss cycles 3032system.iocache.WriteLineReq_mshr_miss_latency::total 2552566881 # number of WriteLineReq MSHR miss cycles 3033system.iocache.demand_mshr_miss_latency::realview.ide 2580571258 # number of demand (read+write) MSHR miss cycles 3034system.iocache.demand_mshr_miss_latency::total 2580571258 # number of demand (read+write) MSHR miss cycles 3035system.iocache.overall_mshr_miss_latency::realview.ide 2580571258 # number of overall MSHR miss cycles 3036system.iocache.overall_mshr_miss_latency::total 2580571258 # number of overall MSHR miss cycles |
| 3026system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3027system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3028system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3029system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3030system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3031system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3032system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3033system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 3037system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3038system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3039system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3040system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3041system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3042system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3043system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3044system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 3034system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79142.369048 # average ReadReq mshr miss latency 3035system.iocache.ReadReq_avg_mshr_miss_latency::total 79142.369048 # average ReadReq mshr miss latency 3036system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68738.622819 # average WriteLineReq mshr miss latency 3037system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68738.622819 # average WriteLineReq mshr miss latency 3038system.iocache.demand_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency 3039system.iocache.demand_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency 3040system.iocache.overall_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency 3041system.iocache.overall_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency 3042system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3043system.l2c.tags.replacements 136926 # number of replacements 3044system.l2c.tags.tagsinuse 65153.135165 # Cycle average of tags in use 3045system.l2c.tags.total_refs 554455 # Total number of references to valid blocks. 3046system.l2c.tags.sampled_refs 202299 # Sample count of references to valid blocks. 3047system.l2c.tags.avg_refs 2.740770 # Average number of references to valid blocks. 3048system.l2c.tags.warmup_cycle 87124800000 # Cycle when the warmup percentage was hit. 3049system.l2c.tags.occ_blocks::writebacks 6156.009081 # Average occupied blocks per requestor 3050system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.876446 # Average occupied blocks per requestor 3051system.l2c.tags.occ_blocks::cpu0.itb.walker 1.073086 # Average occupied blocks per requestor 3052system.l2c.tags.occ_blocks::cpu0.inst 8059.392106 # Average occupied blocks per requestor 3053system.l2c.tags.occ_blocks::cpu0.data 7027.702710 # Average occupied blocks per requestor 3054system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37061.403814 # Average occupied blocks per requestor 3055system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.474451 # Average occupied blocks per requestor 3056system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906071 # Average occupied blocks per requestor 3057system.l2c.tags.occ_blocks::cpu1.inst 1853.985065 # Average occupied blocks per requestor 3058system.l2c.tags.occ_blocks::cpu1.data 2995.751440 # Average occupied blocks per requestor 3059system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1972.560896 # Average occupied blocks per requestor 3060system.l2c.tags.occ_percent::writebacks 0.093933 # Average percentage of cache occupancy 3061system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000273 # Average percentage of cache occupancy | 3045system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111128.480159 # average ReadReq mshr miss latency 3046system.iocache.ReadReq_avg_mshr_miss_latency::total 111128.480159 # average ReadReq mshr miss latency 3047system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70466.179356 # average WriteLineReq mshr miss latency 3048system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70466.179356 # average WriteLineReq mshr miss latency 3049system.iocache.demand_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency 3050system.iocache.demand_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency 3051system.iocache.overall_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency 3052system.iocache.overall_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency 3053system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3054system.l2c.tags.replacements 137609 # number of replacements 3055system.l2c.tags.tagsinuse 65136.051895 # Cycle average of tags in use 3056system.l2c.tags.total_refs 548833 # Total number of references to valid blocks. 3057system.l2c.tags.sampled_refs 202971 # Sample count of references to valid blocks. 3058system.l2c.tags.avg_refs 2.703997 # Average number of references to valid blocks. 3059system.l2c.tags.warmup_cycle 87466496000 # Cycle when the warmup percentage was hit. 3060system.l2c.tags.occ_blocks::writebacks 5939.611941 # Average occupied blocks per requestor 3061system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.674941 # Average occupied blocks per requestor 3062system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061639 # Average occupied blocks per requestor 3063system.l2c.tags.occ_blocks::cpu0.inst 8089.660546 # Average occupied blocks per requestor 3064system.l2c.tags.occ_blocks::cpu0.data 7047.830837 # Average occupied blocks per requestor 3065system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37514.795432 # Average occupied blocks per requestor 3066system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.739703 # Average occupied blocks per requestor 3067system.l2c.tags.occ_blocks::cpu1.itb.walker 0.908322 # Average occupied blocks per requestor 3068system.l2c.tags.occ_blocks::cpu1.inst 1674.813935 # Average occupied blocks per requestor 3069system.l2c.tags.occ_blocks::cpu1.data 2903.059558 # Average occupied blocks per requestor 3070system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1945.895041 # Average occupied blocks per requestor 3071system.l2c.tags.occ_percent::writebacks 0.090631 # Average percentage of cache occupancy 3072system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000239 # Average percentage of cache occupancy |
| 3062system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy | 3073system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy |
| 3063system.l2c.tags.occ_percent::cpu0.inst 0.122977 # Average percentage of cache occupancy 3064system.l2c.tags.occ_percent::cpu0.data 0.107234 # Average percentage of cache occupancy 3065system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565512 # Average percentage of cache occupancy 3066system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000099 # Average percentage of cache occupancy | 3074system.l2c.tags.occ_percent::cpu0.inst 0.123438 # Average percentage of cache occupancy 3075system.l2c.tags.occ_percent::cpu0.data 0.107541 # Average percentage of cache occupancy 3076system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572430 # Average percentage of cache occupancy 3077system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy |
| 3067system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy | 3078system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy |
| 3068system.l2c.tags.occ_percent::cpu1.inst 0.028290 # Average percentage of cache occupancy 3069system.l2c.tags.occ_percent::cpu1.data 0.045712 # Average percentage of cache occupancy 3070system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030099 # Average percentage of cache occupancy 3071system.l2c.tags.occ_percent::total 0.994158 # Average percentage of cache occupancy 3072system.l2c.tags.occ_task_id_blocks::1022 33193 # Occupied blocks per task id 3073system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id 3074system.l2c.tags.occ_task_id_blocks::1024 32156 # Occupied blocks per task id 3075system.l2c.tags.age_task_id_blocks_1022::2 172 # Occupied blocks per task id 3076system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id 3077system.l2c.tags.age_task_id_blocks_1022::4 27047 # Occupied blocks per task id | 3079system.l2c.tags.occ_percent::cpu1.inst 0.025556 # Average percentage of cache occupancy 3080system.l2c.tags.occ_percent::cpu1.data 0.044297 # Average percentage of cache occupancy 3081system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029692 # Average percentage of cache occupancy 3082system.l2c.tags.occ_percent::total 0.993897 # Average percentage of cache occupancy 3083system.l2c.tags.occ_task_id_blocks::1022 33502 # Occupied blocks per task id 3084system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id 3085system.l2c.tags.occ_task_id_blocks::1024 31839 # Occupied blocks per task id 3086system.l2c.tags.age_task_id_blocks_1022::2 401 # Occupied blocks per task id 3087system.l2c.tags.age_task_id_blocks_1022::3 6111 # Occupied blocks per task id 3088system.l2c.tags.age_task_id_blocks_1022::4 26990 # Occupied blocks per task id |
| 3078system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 3089system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 3079system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id 3080system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 3081system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 3082system.l2c.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id 3083system.l2c.tags.age_task_id_blocks_1024::3 4634 # Occupied blocks per task id 3084system.l2c.tags.age_task_id_blocks_1024::4 27347 # Occupied blocks per task id 3085system.l2c.tags.occ_task_id_percent::1022 0.506485 # Percentage of cache occupancy per task id 3086system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 3087system.l2c.tags.occ_task_id_percent::1024 0.490662 # Percentage of cache occupancy per task id 3088system.l2c.tags.tag_accesses 6339538 # Number of tag accesses 3089system.l2c.tags.data_accesses 6339538 # Number of data accesses 3090system.l2c.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3091system.l2c.WritebackDirty_hits::writebacks 263091 # number of WritebackDirty hits 3092system.l2c.WritebackDirty_hits::total 263091 # number of WritebackDirty hits 3093system.l2c.UpgradeReq_hits::cpu0.data 41407 # number of UpgradeReq hits 3094system.l2c.UpgradeReq_hits::cpu1.data 4842 # number of UpgradeReq hits 3095system.l2c.UpgradeReq_hits::total 46249 # number of UpgradeReq hits 3096system.l2c.SCUpgradeReq_hits::cpu0.data 2692 # number of SCUpgradeReq hits 3097system.l2c.SCUpgradeReq_hits::cpu1.data 2122 # number of SCUpgradeReq hits 3098system.l2c.SCUpgradeReq_hits::total 4814 # number of SCUpgradeReq hits 3099system.l2c.ReadExReq_hits::cpu0.data 3983 # number of ReadExReq hits 3100system.l2c.ReadExReq_hits::cpu1.data 1501 # number of ReadExReq hits 3101system.l2c.ReadExReq_hits::total 5484 # number of ReadExReq hits 3102system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 230 # number of ReadSharedReq hits 3103system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits 3104system.l2c.ReadSharedReq_hits::cpu0.inst 51619 # number of ReadSharedReq hits 3105system.l2c.ReadSharedReq_hits::cpu0.data 58109 # number of ReadSharedReq hits 3106system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47216 # number of ReadSharedReq hits 3107system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 63 # number of ReadSharedReq hits 3108system.l2c.ReadSharedReq_hits::cpu1.itb.walker 17 # number of ReadSharedReq hits 3109system.l2c.ReadSharedReq_hits::cpu1.inst 21642 # number of ReadSharedReq hits 3110system.l2c.ReadSharedReq_hits::cpu1.data 11731 # number of ReadSharedReq hits 3111system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5163 # number of ReadSharedReq hits 3112system.l2c.ReadSharedReq_hits::total 195876 # number of ReadSharedReq hits 3113system.l2c.demand_hits::cpu0.dtb.walker 230 # number of demand (read+write) hits 3114system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits 3115system.l2c.demand_hits::cpu0.inst 51619 # number of demand (read+write) hits 3116system.l2c.demand_hits::cpu0.data 62092 # number of demand (read+write) hits 3117system.l2c.demand_hits::cpu0.l2cache.prefetcher 47216 # number of demand (read+write) hits 3118system.l2c.demand_hits::cpu1.dtb.walker 63 # number of demand (read+write) hits 3119system.l2c.demand_hits::cpu1.itb.walker 17 # number of demand (read+write) hits 3120system.l2c.demand_hits::cpu1.inst 21642 # number of demand (read+write) hits 3121system.l2c.demand_hits::cpu1.data 13232 # number of demand (read+write) hits 3122system.l2c.demand_hits::cpu1.l2cache.prefetcher 5163 # number of demand (read+write) hits 3123system.l2c.demand_hits::total 201360 # number of demand (read+write) hits 3124system.l2c.overall_hits::cpu0.dtb.walker 230 # number of overall hits 3125system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits 3126system.l2c.overall_hits::cpu0.inst 51619 # number of overall hits 3127system.l2c.overall_hits::cpu0.data 62092 # number of overall hits 3128system.l2c.overall_hits::cpu0.l2cache.prefetcher 47216 # number of overall hits 3129system.l2c.overall_hits::cpu1.dtb.walker 63 # number of overall hits 3130system.l2c.overall_hits::cpu1.itb.walker 17 # number of overall hits 3131system.l2c.overall_hits::cpu1.inst 21642 # number of overall hits 3132system.l2c.overall_hits::cpu1.data 13232 # number of overall hits 3133system.l2c.overall_hits::cpu1.l2cache.prefetcher 5163 # number of overall hits 3134system.l2c.overall_hits::total 201360 # number of overall hits 3135system.l2c.UpgradeReq_misses::cpu0.data 609 # number of UpgradeReq misses 3136system.l2c.UpgradeReq_misses::cpu1.data 555 # number of UpgradeReq misses 3137system.l2c.UpgradeReq_misses::total 1164 # number of UpgradeReq misses 3138system.l2c.SCUpgradeReq_misses::cpu0.data 50 # number of SCUpgradeReq misses 3139system.l2c.SCUpgradeReq_misses::cpu1.data 135 # number of SCUpgradeReq misses 3140system.l2c.SCUpgradeReq_misses::total 185 # number of SCUpgradeReq misses 3141system.l2c.ReadExReq_misses::cpu0.data 11314 # number of ReadExReq misses 3142system.l2c.ReadExReq_misses::cpu1.data 8283 # number of ReadExReq misses 3143system.l2c.ReadExReq_misses::total 19597 # number of ReadExReq misses 3144system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 30 # number of ReadSharedReq misses | 3090system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 3091system.l2c.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id 3092system.l2c.tags.age_task_id_blocks_1024::3 4972 # Occupied blocks per task id 3093system.l2c.tags.age_task_id_blocks_1024::4 26706 # Occupied blocks per task id 3094system.l2c.tags.occ_task_id_percent::1022 0.511200 # Percentage of cache occupancy per task id 3095system.l2c.tags.occ_task_id_percent::1023 0.000320 # Percentage of cache occupancy per task id 3096system.l2c.tags.occ_task_id_percent::1024 0.485825 # Percentage of cache occupancy per task id 3097system.l2c.tags.tag_accesses 6298618 # Number of tag accesses 3098system.l2c.tags.data_accesses 6298618 # Number of data accesses 3099system.l2c.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3100system.l2c.WritebackDirty_hits::writebacks 261626 # number of WritebackDirty hits 3101system.l2c.WritebackDirty_hits::total 261626 # number of WritebackDirty hits 3102system.l2c.UpgradeReq_hits::cpu0.data 41310 # number of UpgradeReq hits 3103system.l2c.UpgradeReq_hits::cpu1.data 4699 # number of UpgradeReq hits 3104system.l2c.UpgradeReq_hits::total 46009 # number of UpgradeReq hits 3105system.l2c.SCUpgradeReq_hits::cpu0.data 2684 # number of SCUpgradeReq hits 3106system.l2c.SCUpgradeReq_hits::cpu1.data 2210 # number of SCUpgradeReq hits 3107system.l2c.SCUpgradeReq_hits::total 4894 # number of SCUpgradeReq hits 3108system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits 3109system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits 3110system.l2c.ReadExReq_hits::total 5320 # number of ReadExReq hits 3111system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 248 # number of ReadSharedReq hits 3112system.l2c.ReadSharedReq_hits::cpu0.itb.walker 107 # number of ReadSharedReq hits 3113system.l2c.ReadSharedReq_hits::cpu0.inst 50964 # number of ReadSharedReq hits 3114system.l2c.ReadSharedReq_hits::cpu0.data 57616 # number of ReadSharedReq hits 3115system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46197 # number of ReadSharedReq hits 3116system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 67 # number of ReadSharedReq hits 3117system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits 3118system.l2c.ReadSharedReq_hits::cpu1.inst 21124 # number of ReadSharedReq hits 3119system.l2c.ReadSharedReq_hits::cpu1.data 11550 # number of ReadSharedReq hits 3120system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4807 # number of ReadSharedReq hits 3121system.l2c.ReadSharedReq_hits::total 192709 # number of ReadSharedReq hits 3122system.l2c.demand_hits::cpu0.dtb.walker 248 # number of demand (read+write) hits 3123system.l2c.demand_hits::cpu0.itb.walker 107 # number of demand (read+write) hits 3124system.l2c.demand_hits::cpu0.inst 50964 # number of demand (read+write) hits 3125system.l2c.demand_hits::cpu0.data 61594 # number of demand (read+write) hits 3126system.l2c.demand_hits::cpu0.l2cache.prefetcher 46197 # number of demand (read+write) hits 3127system.l2c.demand_hits::cpu1.dtb.walker 67 # number of demand (read+write) hits 3128system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits 3129system.l2c.demand_hits::cpu1.inst 21124 # number of demand (read+write) hits 3130system.l2c.demand_hits::cpu1.data 12892 # number of demand (read+write) hits 3131system.l2c.demand_hits::cpu1.l2cache.prefetcher 4807 # number of demand (read+write) hits 3132system.l2c.demand_hits::total 198029 # number of demand (read+write) hits 3133system.l2c.overall_hits::cpu0.dtb.walker 248 # number of overall hits 3134system.l2c.overall_hits::cpu0.itb.walker 107 # number of overall hits 3135system.l2c.overall_hits::cpu0.inst 50964 # number of overall hits 3136system.l2c.overall_hits::cpu0.data 61594 # number of overall hits 3137system.l2c.overall_hits::cpu0.l2cache.prefetcher 46197 # number of overall hits 3138system.l2c.overall_hits::cpu1.dtb.walker 67 # number of overall hits 3139system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits 3140system.l2c.overall_hits::cpu1.inst 21124 # number of overall hits 3141system.l2c.overall_hits::cpu1.data 12892 # number of overall hits 3142system.l2c.overall_hits::cpu1.l2cache.prefetcher 4807 # number of overall hits 3143system.l2c.overall_hits::total 198029 # number of overall hits 3144system.l2c.UpgradeReq_misses::cpu0.data 543 # number of UpgradeReq misses 3145system.l2c.UpgradeReq_misses::cpu1.data 291 # number of UpgradeReq misses 3146system.l2c.UpgradeReq_misses::total 834 # number of UpgradeReq misses 3147system.l2c.SCUpgradeReq_misses::cpu0.data 92 # number of SCUpgradeReq misses 3148system.l2c.SCUpgradeReq_misses::cpu1.data 104 # number of SCUpgradeReq misses 3149system.l2c.SCUpgradeReq_misses::total 196 # number of SCUpgradeReq misses 3150system.l2c.ReadExReq_misses::cpu0.data 11177 # number of ReadExReq misses 3151system.l2c.ReadExReq_misses::cpu1.data 8193 # number of ReadExReq misses 3152system.l2c.ReadExReq_misses::total 19370 # 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| 3236system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses) 3237system.l2c.ReadSharedReq_accesses::cpu1.inst 24536 # number of ReadSharedReq accesses(hits+misses) 3238system.l2c.ReadSharedReq_accesses::cpu1.data 12815 # number of ReadSharedReq accesses(hits+misses) 3239system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11666 # number of ReadSharedReq accesses(hits+misses) 3240system.l2c.ReadSharedReq_accesses::total 366870 # number of ReadSharedReq accesses(hits+misses) 3241system.l2c.demand_accesses::cpu0.dtb.walker 260 # number of demand (read+write) accesses 3242system.l2c.demand_accesses::cpu0.itb.walker 89 # number of demand (read+write) accesses 3243system.l2c.demand_accesses::cpu0.inst 71216 # number of demand (read+write) accesses 3244system.l2c.demand_accesses::cpu0.data 82798 # number of demand (read+write) accesses 3245system.l2c.demand_accesses::cpu0.l2cache.prefetcher 178698 # number of demand (read+write) accesses | 3245system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses) 3246system.l2c.ReadSharedReq_accesses::cpu1.inst 23836 # number of ReadSharedReq accesses(hits+misses) 3247system.l2c.ReadSharedReq_accesses::cpu1.data 12531 # number of ReadSharedReq accesses(hits+misses) 3248system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11482 # number of ReadSharedReq accesses(hits+misses) 3249system.l2c.ReadSharedReq_accesses::total 364264 # number of ReadSharedReq accesses(hits+misses) 3250system.l2c.demand_accesses::cpu0.dtb.walker 277 # number of demand (read+write) accesses 3251system.l2c.demand_accesses::cpu0.itb.walker 110 # number of demand (read+write) accesses 3252system.l2c.demand_accesses::cpu0.inst 70917 # number of demand (read+write) accesses 3253system.l2c.demand_accesses::cpu0.data 82122 # number of demand (read+write) accesses 3254system.l2c.demand_accesses::cpu0.l2cache.prefetcher 178043 # number of demand (read+write) accesses |
| 3246system.l2c.demand_accesses::cpu1.dtb.walker 71 # number of demand (read+write) accesses | 3255system.l2c.demand_accesses::cpu1.dtb.walker 71 # number of demand (read+write) accesses |
| 3247system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses 3248system.l2c.demand_accesses::cpu1.inst 24536 # number of demand (read+write) accesses 3249system.l2c.demand_accesses::cpu1.data 22599 # number of demand (read+write) accesses 3250system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11666 # number of demand (read+write) accesses 3251system.l2c.demand_accesses::total 391951 # number of demand (read+write) accesses 3252system.l2c.overall_accesses::cpu0.dtb.walker 260 # number of overall (read+write) accesses 3253system.l2c.overall_accesses::cpu0.itb.walker 89 # number of overall (read+write) accesses 3254system.l2c.overall_accesses::cpu0.inst 71216 # number of overall (read+write) accesses 3255system.l2c.overall_accesses::cpu0.data 82798 # number of overall (read+write) accesses 3256system.l2c.overall_accesses::cpu0.l2cache.prefetcher 178698 # number of overall (read+write) accesses | 3256system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses 3257system.l2c.demand_accesses::cpu1.inst 23836 # number of demand (read+write) accesses 3258system.l2c.demand_accesses::cpu1.data 22066 # number of demand (read+write) accesses 3259system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11482 # number of demand (read+write) accesses 3260system.l2c.demand_accesses::total 388954 # number of demand (read+write) accesses 3261system.l2c.overall_accesses::cpu0.dtb.walker 277 # number of overall (read+write) accesses 3262system.l2c.overall_accesses::cpu0.itb.walker 110 # number of overall (read+write) accesses 3263system.l2c.overall_accesses::cpu0.inst 70917 # number of overall (read+write) accesses 3264system.l2c.overall_accesses::cpu0.data 82122 # number of overall (read+write) accesses 3265system.l2c.overall_accesses::cpu0.l2cache.prefetcher 178043 # number of overall (read+write) accesses |
| 3257system.l2c.overall_accesses::cpu1.dtb.walker 71 # number of overall (read+write) accesses | 3266system.l2c.overall_accesses::cpu1.dtb.walker 71 # number of overall (read+write) accesses |
| 3258system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses 3259system.l2c.overall_accesses::cpu1.inst 24536 # number of overall (read+write) accesses 3260system.l2c.overall_accesses::cpu1.data 22599 # number of overall (read+write) accesses 3261system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11666 # number of overall (read+write) accesses 3262system.l2c.overall_accesses::total 391951 # number of overall (read+write) accesses 3263system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014494 # miss rate for UpgradeReq accesses 3264system.l2c.UpgradeReq_miss_rate::cpu1.data 0.102835 # miss rate for UpgradeReq accesses 3265system.l2c.UpgradeReq_miss_rate::total 0.024550 # miss rate for UpgradeReq accesses 3266system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018235 # miss rate for SCUpgradeReq accesses 3267system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.059814 # miss rate for SCUpgradeReq accesses 3268system.l2c.SCUpgradeReq_miss_rate::total 0.037007 # miss rate for SCUpgradeReq accesses 3269system.l2c.ReadExReq_miss_rate::cpu0.data 0.739622 # miss rate for ReadExReq accesses 3270system.l2c.ReadExReq_miss_rate::cpu1.data 0.846586 # miss rate for ReadExReq accesses 3271system.l2c.ReadExReq_miss_rate::total 0.781348 # miss rate for ReadExReq accesses 3272system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for ReadSharedReq accesses 3273system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.033708 # miss rate for ReadSharedReq accesses 3274system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.275177 # miss rate for ReadSharedReq accesses 3275system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.139139 # miss rate for ReadSharedReq accesses 3276system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735778 # miss rate for ReadSharedReq accesses 3277system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.112676 # miss rate for ReadSharedReq accesses 3278system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.055556 # miss rate for ReadSharedReq accesses 3279system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.117949 # miss rate for ReadSharedReq accesses 3280system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.084588 # miss rate for ReadSharedReq accesses 3281system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.557432 # miss rate for ReadSharedReq accesses 3282system.l2c.ReadSharedReq_miss_rate::total 0.466089 # miss rate for ReadSharedReq accesses 3283system.l2c.demand_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for demand accesses 3284system.l2c.demand_miss_rate::cpu0.itb.walker 0.033708 # miss rate for demand accesses 3285system.l2c.demand_miss_rate::cpu0.inst 0.275177 # miss rate for demand accesses 3286system.l2c.demand_miss_rate::cpu0.data 0.250079 # miss rate for demand accesses 3287system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735778 # miss rate for demand accesses 3288system.l2c.demand_miss_rate::cpu1.dtb.walker 0.112676 # miss rate for demand accesses 3289system.l2c.demand_miss_rate::cpu1.itb.walker 0.055556 # miss rate for demand accesses 3290system.l2c.demand_miss_rate::cpu1.inst 0.117949 # miss rate for demand accesses 3291system.l2c.demand_miss_rate::cpu1.data 0.414487 # miss rate for demand accesses 3292system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.557432 # miss rate for demand accesses 3293system.l2c.demand_miss_rate::total 0.486262 # miss rate for demand accesses 3294system.l2c.overall_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for overall accesses 3295system.l2c.overall_miss_rate::cpu0.itb.walker 0.033708 # miss rate for overall accesses 3296system.l2c.overall_miss_rate::cpu0.inst 0.275177 # miss rate for overall accesses 3297system.l2c.overall_miss_rate::cpu0.data 0.250079 # miss rate for overall accesses 3298system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735778 # miss rate for overall accesses 3299system.l2c.overall_miss_rate::cpu1.dtb.walker 0.112676 # miss rate for overall accesses 3300system.l2c.overall_miss_rate::cpu1.itb.walker 0.055556 # miss rate for overall accesses 3301system.l2c.overall_miss_rate::cpu1.inst 0.117949 # miss rate for overall accesses 3302system.l2c.overall_miss_rate::cpu1.data 0.414487 # miss rate for overall accesses 3303system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.557432 # miss rate for overall accesses 3304system.l2c.overall_miss_rate::total 0.486262 # miss rate for overall accesses 3305system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14554.187192 # average UpgradeReq miss latency 3306system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2906.306306 # average UpgradeReq miss latency 3307system.l2c.UpgradeReq_avg_miss_latency::total 9000.429553 # average UpgradeReq miss latency 3308system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15000 # average SCUpgradeReq miss latency 3309system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1851.851852 # average SCUpgradeReq miss latency 3310system.l2c.SCUpgradeReq_avg_miss_latency::total 5405.405405 # average SCUpgradeReq miss latency 3311system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103715.264274 # average ReadExReq miss latency 3312system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84305.927804 # average ReadExReq miss latency 3313system.l2c.ReadExReq_avg_miss_latency::total 95511.583406 # average ReadExReq miss latency 3314system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 96700 # average ReadSharedReq miss latency 3315system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency 3316system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83942.924937 # average ReadSharedReq miss latency 3317system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92145.389693 # average ReadSharedReq miss latency 3318system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014 # average ReadSharedReq miss latency 3319system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87375 # average ReadSharedReq miss latency 3320system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq miss latency 3321system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85575.673808 # average ReadSharedReq miss latency 3322system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90673.431734 # average ReadSharedReq miss latency 3323system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244 # average ReadSharedReq miss latency 3324system.l2c.ReadSharedReq_avg_miss_latency::total 106405.239698 # average ReadSharedReq miss latency 3325system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96700 # average overall miss latency 3326system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3327system.l2c.demand_avg_miss_latency::cpu0.inst 83942.924937 # average overall miss latency 3328system.l2c.demand_avg_miss_latency::cpu0.data 98467.304163 # average overall miss latency 3329system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014 # average overall miss latency 3330system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87375 # average overall miss latency 3331system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency 3332system.l2c.demand_avg_miss_latency::cpu1.inst 85575.673808 # average overall miss latency 3333system.l2c.demand_avg_miss_latency::cpu1.data 85042.809864 # average overall miss latency 3334system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244 # average overall miss latency 3335system.l2c.demand_avg_miss_latency::total 105285.129188 # average overall miss latency 3336system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96700 # average overall miss latency 3337system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3338system.l2c.overall_avg_miss_latency::cpu0.inst 83942.924937 # average overall miss latency 3339system.l2c.overall_avg_miss_latency::cpu0.data 98467.304163 # average overall miss latency 3340system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014 # average overall miss latency 3341system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87375 # average overall miss latency 3342system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency 3343system.l2c.overall_avg_miss_latency::cpu1.inst 85575.673808 # average overall miss latency 3344system.l2c.overall_avg_miss_latency::cpu1.data 85042.809864 # average overall miss latency 3345system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244 # average overall miss latency 3346system.l2c.overall_avg_miss_latency::total 105285.129188 # average overall miss latency 3347system.l2c.blocked_cycles::no_mshrs 188 # number of cycles access was blocked | 3267system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses 3268system.l2c.overall_accesses::cpu1.inst 23836 # number of overall (read+write) accesses 3269system.l2c.overall_accesses::cpu1.data 22066 # number of overall (read+write) accesses 3270system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11482 # number of overall (read+write) accesses 3271system.l2c.overall_accesses::total 388954 # number of overall (read+write) accesses 3272system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012974 # miss rate for UpgradeReq accesses 3273system.l2c.UpgradeReq_miss_rate::cpu1.data 0.058317 # miss rate for UpgradeReq accesses 3274system.l2c.UpgradeReq_miss_rate::total 0.017804 # miss rate for UpgradeReq accesses 3275system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.033141 # miss rate for SCUpgradeReq accesses 3276system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.044944 # miss rate for SCUpgradeReq accesses 3277system.l2c.SCUpgradeReq_miss_rate::total 0.038507 # miss rate for SCUpgradeReq accesses 3278system.l2c.ReadExReq_miss_rate::cpu0.data 0.737512 # miss rate for ReadExReq accesses 3279system.l2c.ReadExReq_miss_rate::cpu1.data 0.859255 # miss rate for ReadExReq accesses 3280system.l2c.ReadExReq_miss_rate::total 0.784528 # miss rate for ReadExReq accesses 3281system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for ReadSharedReq accesses 3282system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027273 # miss rate for ReadSharedReq accesses 3283system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.281357 # miss rate for ReadSharedReq accesses 3284system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.139636 # miss rate for ReadSharedReq accesses 3285system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for ReadSharedReq accesses 3286system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for ReadSharedReq accesses 3287system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.033333 # miss rate for ReadSharedReq accesses 3288system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.113777 # miss rate for ReadSharedReq accesses 3289system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078286 # miss rate for ReadSharedReq accesses 3290system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for ReadSharedReq accesses 3291system.l2c.ReadSharedReq_miss_rate::total 0.470963 # miss rate for ReadSharedReq accesses 3292system.l2c.demand_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for demand accesses 3293system.l2c.demand_miss_rate::cpu0.itb.walker 0.027273 # miss rate for demand accesses 3294system.l2c.demand_miss_rate::cpu0.inst 0.281357 # miss rate for demand accesses 3295system.l2c.demand_miss_rate::cpu0.data 0.249970 # miss rate for demand accesses 3296system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for demand accesses 3297system.l2c.demand_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for demand accesses 3298system.l2c.demand_miss_rate::cpu1.itb.walker 0.033333 # miss rate for demand accesses 3299system.l2c.demand_miss_rate::cpu1.inst 0.113777 # miss rate for demand accesses 3300system.l2c.demand_miss_rate::cpu1.data 0.415753 # miss rate for demand accesses 3301system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for demand accesses 3302system.l2c.demand_miss_rate::total 0.490868 # miss rate for demand accesses 3303system.l2c.overall_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for overall accesses 3304system.l2c.overall_miss_rate::cpu0.itb.walker 0.027273 # miss rate for overall accesses 3305system.l2c.overall_miss_rate::cpu0.inst 0.281357 # miss rate for overall accesses 3306system.l2c.overall_miss_rate::cpu0.data 0.249970 # miss rate for overall accesses 3307system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for overall accesses 3308system.l2c.overall_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for overall accesses 3309system.l2c.overall_miss_rate::cpu1.itb.walker 0.033333 # miss rate for overall accesses 3310system.l2c.overall_miss_rate::cpu1.inst 0.113777 # miss rate for overall accesses 3311system.l2c.overall_miss_rate::cpu1.data 0.415753 # miss rate for overall accesses 3312system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for overall accesses 3313system.l2c.overall_miss_rate::total 0.490868 # miss rate for overall accesses 3314system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16033.149171 # average UpgradeReq miss latency 3315system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2759.450172 # average UpgradeReq miss latency 3316system.l2c.UpgradeReq_avg_miss_latency::total 11401.678657 # average UpgradeReq miss latency 3317system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7304.347826 # average SCUpgradeReq miss latency 3318system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4908.653846 # average SCUpgradeReq miss latency 3319system.l2c.SCUpgradeReq_avg_miss_latency::total 6033.163265 # average SCUpgradeReq miss latency 3320system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147616.623423 # average ReadExReq miss latency 3321system.l2c.ReadExReq_avg_miss_latency::cpu1.data 91790.674966 # average ReadExReq miss latency 3322system.l2c.ReadExReq_avg_miss_latency::total 124003.717088 # average ReadExReq miss latency 3323system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average ReadSharedReq miss latency 3324system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency 3325system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 104960.707663 # average ReadSharedReq miss latency 3326system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115678.857876 # average ReadSharedReq miss latency 3327system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average ReadSharedReq miss latency 3328system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 225875 # average ReadSharedReq miss latency 3329system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89500 # average ReadSharedReq miss latency 3330system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 106493.362832 # average ReadSharedReq miss latency 3331system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123259.938838 # average ReadSharedReq miss latency 3332system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average ReadSharedReq miss latency 3333system.l2c.ReadSharedReq_avg_miss_latency::total 123151.444452 # average ReadSharedReq miss latency 3334system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average overall miss latency 3335system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 3336system.l2c.demand_avg_miss_latency::cpu0.inst 104960.707663 # average overall miss latency 3337system.l2c.demand_avg_miss_latency::cpu0.data 133068.199532 # average overall miss latency 3338system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average overall miss latency 3339system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 225875 # average overall miss latency 3340system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency 3341system.l2c.demand_avg_miss_latency::cpu1.inst 106493.362832 # average overall miss latency 3342system.l2c.demand_avg_miss_latency::cpu1.data 95155.766296 # average overall miss latency 3343system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average overall miss latency 3344system.l2c.demand_avg_miss_latency::total 123237.910452 # average overall miss latency 3345system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average overall miss latency 3346system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 3347system.l2c.overall_avg_miss_latency::cpu0.inst 104960.707663 # average overall miss latency 3348system.l2c.overall_avg_miss_latency::cpu0.data 133068.199532 # average overall miss latency 3349system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average overall miss latency 3350system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 225875 # average overall miss latency 3351system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency 3352system.l2c.overall_avg_miss_latency::cpu1.inst 106493.362832 # average overall miss latency 3353system.l2c.overall_avg_miss_latency::cpu1.data 95155.766296 # average overall miss latency 3354system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average overall miss latency 3355system.l2c.overall_avg_miss_latency::total 123237.910452 # average overall miss latency 3356system.l2c.blocked_cycles::no_mshrs 225 # number of cycles access was blocked |
| 3348system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3357system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3349system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked | 3358system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked |
| 3350system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 3359system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 3351system.l2c.avg_blocked_cycles::no_mshrs 37.600000 # average number of cycles each access was blocked | 3360system.l2c.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked |
| 3352system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 3361system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
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number of ReadSharedReq MSHR miss cycles 3439system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 988203000 # number of ReadSharedReq MSHR miss cycles 3440system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15207829549 # number of ReadSharedReq MSHR miss cycles 3441system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 863500 # number of ReadSharedReq MSHR miss cycles 3442system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 79500 # number of ReadSharedReq MSHR miss cycles 3443system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 261689501 # number of ReadSharedReq MSHR miss cycles 3444system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111108000 # number of ReadSharedReq MSHR miss cycles 3445system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 943281016 # number of ReadSharedReq MSHR miss cycles 3446system.l2c.ReadSharedReq_mshr_miss_latency::total 19411677070 # number of ReadSharedReq MSHR miss cycles 3447system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of demand (read+write) MSHR miss cycles 3448system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 219000 # number of demand (read+write) MSHR miss cycles 3449system.l2c.demand_mshr_miss_latency::cpu0.inst 1894738504 # number of demand (read+write) MSHR miss cycles 3450system.l2c.demand_mshr_miss_latency::cpu0.data 2526343501 # number of demand (read+write) MSHR miss cycles 3451system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15207829549 # number of demand (read+write) MSHR miss cycles 3452system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 863500 # number of demand (read+write) MSHR miss cycles 3453system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 79500 # number of demand (read+write) MSHR miss cycles 3454system.l2c.demand_mshr_miss_latency::cpu1.inst 261689501 # number of demand (read+write) MSHR miss cycles 3455system.l2c.demand_mshr_miss_latency::cpu1.data 781219000 # number of demand (read+write) MSHR miss cycles 3456system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 943281016 # number of demand (read+write) MSHR miss cycles 3457system.l2c.demand_mshr_miss_latency::total 21619928571 # number of demand (read+write) MSHR miss cycles 3458system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of overall MSHR miss cycles 3459system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 219000 # number of overall MSHR miss cycles 3460system.l2c.overall_mshr_miss_latency::cpu0.inst 1894738504 # number of overall MSHR miss cycles 3461system.l2c.overall_mshr_miss_latency::cpu0.data 2526343501 # number of overall MSHR miss cycles 3462system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15207829549 # number of overall MSHR miss cycles 3463system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 863500 # number of overall MSHR miss cycles 3464system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 79500 # number of overall MSHR miss cycles 3465system.l2c.overall_mshr_miss_latency::cpu1.inst 261689501 # number of overall MSHR miss cycles 3466system.l2c.overall_mshr_miss_latency::cpu1.data 781219000 # number of overall MSHR miss cycles 3467system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 943281016 # number of overall MSHR miss cycles 3468system.l2c.overall_mshr_miss_latency::total 21619928571 # number of overall MSHR miss cycles 3469system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles 3470system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5797437001 # number of ReadReq MSHR uncacheable cycles 3471system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6745000 # number of ReadReq MSHR uncacheable cycles 3472system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 371342000 # number of ReadReq MSHR uncacheable cycles 3473system.l2c.ReadReq_mshr_uncacheable_latency::total 6386465501 # number of ReadReq MSHR uncacheable cycles 3474system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles 3475system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5797437001 # number of overall MSHR uncacheable cycles 3476system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6745000 # number of overall MSHR uncacheable cycles 3477system.l2c.overall_mshr_uncacheable_latency::cpu1.data 371342000 # number of overall MSHR uncacheable cycles 3478system.l2c.overall_mshr_uncacheable_latency::total 6386465501 # number of overall MSHR uncacheable cycles |
| 3473system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3474system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 3479system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3480system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 3475system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014494 # mshr miss rate for UpgradeReq accesses 3476system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.102835 # mshr miss rate for UpgradeReq accesses 3477system.l2c.UpgradeReq_mshr_miss_rate::total 0.024550 # mshr miss rate for UpgradeReq accesses 3478system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018235 # mshr miss rate for SCUpgradeReq accesses 3479system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.059814 # mshr miss rate for SCUpgradeReq accesses 3480system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037007 # mshr miss rate for SCUpgradeReq accesses 3481system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739622 # mshr miss rate for ReadExReq accesses 3482system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.846586 # mshr miss rate for ReadExReq accesses 3483system.l2c.ReadExReq_mshr_miss_rate::total 0.781348 # mshr miss rate for ReadExReq accesses 3484system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for ReadSharedReq accesses 3485system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for ReadSharedReq accesses 3486system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for ReadSharedReq accesses 3487system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.139139 # mshr miss rate for ReadSharedReq accesses 3488system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for ReadSharedReq accesses 3489system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for ReadSharedReq accesses 3490system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for ReadSharedReq accesses 3491system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for ReadSharedReq accesses 3492system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.084588 # mshr miss rate for ReadSharedReq accesses 3493system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for ReadSharedReq accesses 3494system.l2c.ReadSharedReq_mshr_miss_rate::total 0.466078 # mshr miss rate for ReadSharedReq accesses 3495system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for demand accesses 3496system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for demand accesses 3497system.l2c.demand_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for demand accesses 3498system.l2c.demand_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for demand accesses 3499system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for demand accesses 3500system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for demand accesses 3501system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for demand accesses 3502system.l2c.demand_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for demand accesses 3503system.l2c.demand_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for demand accesses 3504system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for demand accesses 3505system.l2c.demand_mshr_miss_rate::total 0.486252 # mshr miss rate for demand accesses 3506system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for overall accesses 3507system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for overall accesses 3508system.l2c.overall_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for overall accesses 3509system.l2c.overall_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for overall accesses 3510system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for overall accesses 3511system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for overall accesses 3512system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for overall accesses 3513system.l2c.overall_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for overall accesses 3514system.l2c.overall_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for overall accesses 3515system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for overall accesses 3516system.l2c.overall_mshr_miss_rate::total 0.486252 # mshr miss rate for overall accesses 3517system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23267.651888 # average UpgradeReq mshr miss latency 3518system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22047.747748 # average UpgradeReq mshr miss latency 3519system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22685.996564 # average UpgradeReq mshr miss latency 3520system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26990 # average SCUpgradeReq mshr miss latency 3521system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23811.111111 # average SCUpgradeReq mshr miss latency 3522system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24670.270270 # average SCUpgradeReq mshr miss latency 3523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93715.264274 # average ReadExReq mshr miss latency 3524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74305.927804 # average ReadExReq mshr miss latency 3525system.l2c.ReadExReq_avg_mshr_miss_latency::total 85511.583406 # average ReadExReq mshr miss latency 3526system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average ReadSharedReq mshr miss latency 3527system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency 3528system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average ReadSharedReq mshr miss latency 3529system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82145.336563 # average ReadSharedReq mshr miss latency 3530system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average ReadSharedReq mshr miss latency 3531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average ReadSharedReq mshr miss latency 3532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency 3533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average ReadSharedReq mshr miss latency 3534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80673.431734 # average ReadSharedReq mshr miss latency 3535system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average ReadSharedReq mshr miss latency 3536system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96406.532990 # average ReadSharedReq mshr miss latency 3537system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency 3538system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3539system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency 3540system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency 3541system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency 3542system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency 3543system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency 3544system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency 3545system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency 3546system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency 3547system.l2c.demand_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency 3548system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency 3549system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3550system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency 3551system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency 3552system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency 3553system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency 3554system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency 3555system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency 3556system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency 3557system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency 3558system.l2c.overall_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency 3559system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency 3560system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726 # average ReadReq mshr uncacheable latency 3561system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average ReadReq mshr uncacheable latency 3562system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991 # average ReadReq mshr uncacheable latency 3563system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471 # average ReadReq mshr uncacheable latency 3564system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency 3565system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470 # average overall mshr uncacheable latency 3566system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average overall mshr uncacheable latency 3567system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703 # average overall mshr uncacheable latency 3568system.l2c.overall_avg_mshr_uncacheable_latency::total 92312.727880 # average overall mshr uncacheable latency 3569system.membus.snoop_filter.tot_requests 505464 # Total number of requests made to the snoop filter. 3570system.membus.snoop_filter.hit_single_requests 284514 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 3481system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012974 # mshr miss rate for UpgradeReq accesses 3482system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.058317 # mshr miss rate for UpgradeReq accesses 3483system.l2c.UpgradeReq_mshr_miss_rate::total 0.017804 # mshr miss rate for UpgradeReq accesses 3484system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033141 # mshr miss rate for SCUpgradeReq accesses 3485system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.044944 # mshr miss rate for SCUpgradeReq accesses 3486system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.038507 # mshr miss rate for SCUpgradeReq accesses 3487system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737512 # mshr miss rate for ReadExReq accesses 3488system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.859255 # mshr miss rate for ReadExReq accesses 3489system.l2c.ReadExReq_mshr_miss_rate::total 0.784528 # mshr miss rate for ReadExReq accesses 3490system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for ReadSharedReq accesses 3491system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for ReadSharedReq accesses 3492system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for ReadSharedReq accesses 3493system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.139636 # mshr miss rate for ReadSharedReq accesses 3494system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for ReadSharedReq accesses 3495system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for ReadSharedReq accesses 3496system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses 3497system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for ReadSharedReq accesses 3498system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078286 # mshr miss rate for ReadSharedReq accesses 3499system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for ReadSharedReq accesses 3500system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470961 # mshr miss rate for ReadSharedReq accesses 3501system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for demand accesses 3502system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for demand accesses 3503system.l2c.demand_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for demand accesses 3504system.l2c.demand_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for demand accesses 3505system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for demand accesses 3506system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for demand accesses 3507system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses 3508system.l2c.demand_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for demand accesses 3509system.l2c.demand_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for demand accesses 3510system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for demand accesses 3511system.l2c.demand_mshr_miss_rate::total 0.490865 # mshr miss rate for demand accesses 3512system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for overall accesses 3513system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for overall accesses 3514system.l2c.overall_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for overall accesses 3515system.l2c.overall_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for overall accesses 3516system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for overall accesses 3517system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for overall accesses 3518system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses 3519system.l2c.overall_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for overall accesses 3520system.l2c.overall_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for overall accesses 3521system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for overall accesses 3522system.l2c.overall_mshr_miss_rate::total 0.490865 # mshr miss rate for overall accesses 3523system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22259.668508 # average UpgradeReq mshr miss latency 3524system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20685.567010 # average UpgradeReq mshr miss latency 3525system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21710.431655 # average UpgradeReq mshr miss latency 3526system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26375 # average SCUpgradeReq mshr miss latency 3527system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22187.500000 # average SCUpgradeReq mshr miss latency 3528system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24153.061224 # average SCUpgradeReq mshr miss latency 3529system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137616.578778 # average ReadExReq mshr miss latency 3530system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 81790.674966 # average ReadExReq mshr miss latency 3531system.l2c.ReadExReq_avg_mshr_miss_latency::total 114003.691327 # average ReadExReq mshr miss latency 3532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average ReadSharedReq mshr miss latency 3533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency 3534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average ReadSharedReq mshr miss latency 3535system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105678.857876 # average ReadSharedReq mshr miss latency 3536system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average ReadSharedReq mshr miss latency 3537system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average ReadSharedReq mshr miss latency 3538system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency 3539system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average ReadSharedReq mshr miss latency 3540system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113259.938838 # average ReadSharedReq mshr miss latency 3541system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average ReadSharedReq mshr miss latency 3542system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113151.993367 # average ReadSharedReq mshr miss latency 3543system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency 3544system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 3545system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency 3546system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency 3547system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency 3548system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency 3549system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency 3550system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency 3551system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency 3552system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency 3553system.l2c.demand_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency 3554system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency 3555system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 3556system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency 3557system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency 3558system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency 3559system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency 3560system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency 3561system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency 3562system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency 3563system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency 3564system.l2c.overall_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency 3565system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency 3566system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182412.592065 # average ReadReq mshr uncacheable latency 3567system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average ReadReq mshr uncacheable latency 3568system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109767.070647 # average ReadReq mshr uncacheable latency 3569system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166861.720777 # average ReadReq mshr uncacheable latency 3570system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency 3571system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96240.591660 # average overall mshr uncacheable latency 3572system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average overall mshr uncacheable latency 3573system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60647.068431 # average overall mshr uncacheable latency 3574system.l2c.overall_avg_mshr_uncacheable_latency::total 91929.949202 # average overall mshr uncacheable latency 3575system.membus.snoop_filter.tot_requests 504773 # Total number of requests made to the snoop filter. 3576system.membus.snoop_filter.hit_single_requests 283620 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 3571system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3572system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3573system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3574system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3577system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3578system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3579system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3580system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3575system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3576system.membus.trans_dist::ReadReq 37954 # Transaction distribution 3577system.membus.trans_dist::ReadResp 209195 # Transaction distribution 3578system.membus.trans_dist::WriteReq 30887 # Transaction distribution 3579system.membus.trans_dist::WriteResp 30887 # Transaction distribution 3580system.membus.trans_dist::WritebackDirty 137421 # Transaction distribution 3581system.membus.trans_dist::CleanEvict 16935 # Transaction distribution 3582system.membus.trans_dist::UpgradeReq 65286 # Transaction distribution 3583system.membus.trans_dist::SCUpgradeReq 38770 # Transaction distribution | 3581system.membus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3582system.membus.trans_dist::ReadReq 38274 # Transaction distribution 3583system.membus.trans_dist::ReadResp 210079 # Transaction distribution 3584system.membus.trans_dist::WriteReq 31197 # Transaction distribution 3585system.membus.trans_dist::WriteResp 31197 # Transaction distribution 3586system.membus.trans_dist::WritebackDirty 137547 # Transaction distribution 3587system.membus.trans_dist::CleanEvict 17007 # Transaction distribution 3588system.membus.trans_dist::UpgradeReq 64594 # Transaction distribution 3589system.membus.trans_dist::SCUpgradeReq 38710 # Transaction distribution |
| 3584system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 3590system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 3585system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3586system.membus.trans_dist::ReadExReq 39566 # Transaction distribution 3587system.membus.trans_dist::ReadExResp 19573 # Transaction distribution 3588system.membus.trans_dist::ReadSharedReq 171242 # Transaction distribution | 3591system.membus.trans_dist::ReadExReq 38808 # Transaction distribution 3592system.membus.trans_dist::ReadExResp 19352 # Transaction distribution 3593system.membus.trans_dist::ReadSharedReq 171806 # Transaction distribution |
| 3589system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3590system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) 3591system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) | 3594system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3595system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) 3596system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) |
| 3592system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13620 # Packet count per connected master and slave (bytes) 3593system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638853 # Packet count per connected master and slave (bytes) 3594system.membus.pkt_count_system.l2c.mem_side::total 760423 # Packet count per connected master and slave (bytes) | 3597system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14870 # Packet count per connected master and slave (bytes) 3598system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638456 # Packet count per connected master and slave (bytes) 3599system.membus.pkt_count_system.l2c.mem_side::total 761276 # Packet count per connected master and slave (bytes) |
| 3595system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3596system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) | 3600system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3601system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) |
| 3597system.membus.pkt_count::total 833372 # Packet count per connected master and slave (bytes) | 3602system.membus.pkt_count::total 834225 # Packet count per connected master and slave (bytes) |
| 3598system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) 3599system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) | 3603system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) 3604system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) |
| 3600system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27240 # Cumulative packet size per connected master and slave (bytes) 3601system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18721784 # Cumulative packet size per connected master and slave (bytes) 3602system.membus.pkt_size_system.l2c.mem_side::total 18912106 # Cumulative packet size per connected master and slave (bytes) | 3605system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29740 # Cumulative packet size per connected master and slave (bytes) 3606system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18751880 # Cumulative packet size per connected master and slave (bytes) 3607system.membus.pkt_size_system.l2c.mem_side::total 18944702 # Cumulative packet size per connected master and slave (bytes) |
| 3603system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3604system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) | 3608system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3609system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) |
| 3605system.membus.pkt_size::total 21230250 # Cumulative packet size per connected master and slave (bytes) 3606system.membus.snoops 123250 # Total snoops (count) | 3610system.membus.pkt_size::total 21262846 # Cumulative packet size per connected master and slave (bytes) 3611system.membus.snoops 122284 # Total snoops (count) |
| 3607system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) | 3612system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) |
| 3608system.membus.snoop_fanout::samples 419934 # Request fanout histogram 3609system.membus.snoop_fanout::mean 0.012350 # Request fanout histogram 3610system.membus.snoop_fanout::stdev 0.110440 # Request fanout histogram | 3613system.membus.snoop_fanout::samples 419616 # Request fanout histogram 3614system.membus.snoop_fanout::mean 0.012440 # Request fanout histogram 3615system.membus.snoop_fanout::stdev 0.110839 # Request fanout histogram |
| 3611system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3616system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3612system.membus.snoop_fanout::0 414748 98.77% 98.77% # Request fanout histogram 3613system.membus.snoop_fanout::1 5186 1.23% 100.00% # Request fanout histogram | 3617system.membus.snoop_fanout::0 414396 98.76% 98.76% # Request fanout histogram 3618system.membus.snoop_fanout::1 5220 1.24% 100.00% # Request fanout histogram |
| 3614system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3615system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3616system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3617system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3619system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3620system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3621system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3622system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3618system.membus.snoop_fanout::total 419934 # Request fanout histogram 3619system.membus.reqLayer0.occupancy 81570000 # Layer occupancy (ticks) | 3623system.membus.snoop_fanout::total 419616 # Request fanout histogram 3624system.membus.reqLayer0.occupancy 81572000 # Layer occupancy (ticks) |
| 3620system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3621system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3622system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3625system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3626system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3627system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3623system.membus.reqLayer2.occupancy 11357000 # Layer occupancy (ticks) | 3628system.membus.reqLayer2.occupancy 12355500 # Layer occupancy (ticks) |
| 3624system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3629system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3625system.membus.reqLayer5.occupancy 987545766 # Layer occupancy (ticks) | 3630system.membus.reqLayer5.occupancy 987789803 # Layer occupancy (ticks) |
| 3626system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 3631system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 3627system.membus.respLayer2.occupancy 1099710840 # Layer occupancy (ticks) | 3632system.membus.respLayer2.occupancy 1102143190 # Layer occupancy (ticks) |
| 3628system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 3633system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 3629system.membus.respLayer3.occupancy 1385881 # Layer occupancy (ticks) | 3634system.membus.respLayer3.occupancy 1335877 # Layer occupancy (ticks) |
| 3630system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 3635system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3631system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3632system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3633system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3634system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3635system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3636system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3637system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 3636system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3637system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3638system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3639system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3640system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3641system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3642system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 3638system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3639system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3640system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3641system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3642system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3643system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3643system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3644system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3645system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3646system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3647system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3648system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3644system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3645system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 3649system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3650system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 3646system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3647system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3648system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3649system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3650system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3651system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3652system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3653system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3669system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3670system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3671system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3672system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3673system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3674system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3675system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3676system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3651system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3652system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3653system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3654system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3655system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3656system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3657system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3658system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3674system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3675system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3676system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3677system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3678system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3679system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3680system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3681system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3677system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3678system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3679system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3680system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3681system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3682system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3683system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states | 3682system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3683system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3684system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3685system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3686system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3687system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3688system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states |
| 3684system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3685system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3686system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3687system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3689system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3690system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3691system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3692system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3688system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3689system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3690system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3691system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3692system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3693system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3694system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3695system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3696system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3697system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3698system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3699system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3700system.toL2Bus.snoop_filter.tot_requests 1051858 # Total number of requests made to the snoop filter. 3701system.toL2Bus.snoop_filter.hit_single_requests 557134 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3702system.toL2Bus.snoop_filter.hit_multi_requests 188416 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3703system.toL2Bus.snoop_filter.tot_snoops 28173 # Total number of snoops made to the snoop filter. 3704system.toL2Bus.snoop_filter.hit_single_snoops 27109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3705system.toL2Bus.snoop_filter.hit_multi_snoops 1064 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3706system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states 3707system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution 3708system.toL2Bus.trans_dist::ReadResp 525508 # Transaction distribution 3709system.toL2Bus.trans_dist::WriteReq 30887 # Transaction distribution 3710system.toL2Bus.trans_dist::WriteResp 30887 # Transaction distribution 3711system.toL2Bus.trans_dist::WritebackDirty 364306 # Transaction distribution 3712system.toL2Bus.trans_dist::CleanEvict 131438 # Transaction distribution 3713system.toL2Bus.trans_dist::UpgradeReq 111511 # Transaction distribution 3714system.toL2Bus.trans_dist::SCUpgradeReq 43584 # Transaction distribution 3715system.toL2Bus.trans_dist::UpgradeResp 155095 # Transaction distribution 3716system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution 3717system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution 3718system.toL2Bus.trans_dist::ReadExReq 50612 # Transaction distribution 3719system.toL2Bus.trans_dist::ReadExResp 50612 # Transaction distribution 3720system.toL2Bus.trans_dist::ReadSharedReq 487554 # Transaction distribution 3721system.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution 3722system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1267106 # Packet count per connected master and slave (bytes) 3723system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 367019 # Packet count per connected master and slave (bytes) 3724system.toL2Bus.pkt_count::total 1634125 # Packet count per connected master and slave (bytes) 3725system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36291756 # Cumulative packet size per connected master and slave (bytes) 3726system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5905726 # Cumulative packet size per connected master and slave (bytes) 3727system.toL2Bus.pkt_size::total 42197482 # Cumulative packet size per connected master and slave (bytes) 3728system.toL2Bus.snoops 390713 # Total snoops (count) 3729system.toL2Bus.snoopTraffic 15836620 # Total snoop traffic (bytes) 3730system.toL2Bus.snoop_fanout::samples 903686 # Request fanout histogram 3731system.toL2Bus.snoop_fanout::mean 0.404217 # Request fanout histogram 3732system.toL2Bus.snoop_fanout::stdev 0.493133 # Request fanout histogram | 3693system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3694system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3695system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3696system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3697system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3698system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3699system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3700system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3701system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3702system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3703system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3704system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3705system.toL2Bus.snoop_filter.tot_requests 1044068 # Total number of requests made to the snoop filter. 3706system.toL2Bus.snoop_filter.hit_single_requests 554075 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3707system.toL2Bus.snoop_filter.hit_multi_requests 185190 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3708system.toL2Bus.snoop_filter.tot_snoops 28829 # Total number of snoops made to the snoop filter. 3709system.toL2Bus.snoop_filter.hit_single_snoops 27647 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3710system.toL2Bus.snoop_filter.hit_multi_snoops 1182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3711system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states 3712system.toL2Bus.trans_dist::ReadReq 38277 # Transaction distribution 3713system.toL2Bus.trans_dist::ReadResp 522605 # Transaction distribution 3714system.toL2Bus.trans_dist::WriteReq 31197 # Transaction distribution 3715system.toL2Bus.trans_dist::WriteResp 31197 # Transaction distribution 3716system.toL2Bus.trans_dist::WritebackDirty 362967 # Transaction distribution 3717system.toL2Bus.trans_dist::CleanEvict 130325 # Transaction distribution 3718system.toL2Bus.trans_dist::UpgradeReq 110585 # Transaction distribution 3719system.toL2Bus.trans_dist::SCUpgradeReq 43604 # Transaction distribution 3720system.toL2Bus.trans_dist::UpgradeResp 154189 # Transaction distribution 3721system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution 3722system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution 3723system.toL2Bus.trans_dist::ReadExReq 50073 # Transaction distribution 3724system.toL2Bus.trans_dist::ReadExResp 50073 # Transaction distribution 3725system.toL2Bus.trans_dist::ReadSharedReq 484331 # Transaction distribution 3726system.toL2Bus.trans_dist::InvalidateReq 4646 # Transaction distribution 3727system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1303151 # Packet count per connected master and slave (bytes) 3728system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320962 # Packet count per connected master and slave (bytes) 3729system.toL2Bus.pkt_count::total 1624113 # Packet count per connected master and slave (bytes) 3730system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36235416 # Cumulative packet size per connected master and slave (bytes) 3731system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5679078 # Cumulative packet size per connected master and slave (bytes) 3732system.toL2Bus.pkt_size::total 41914494 # Cumulative packet size per connected master and slave (bytes) 3733system.toL2Bus.snoops 390245 # Total snoops (count) 3734system.toL2Bus.snoopTraffic 15796172 # Total snoop traffic (bytes) 3735system.toL2Bus.snoop_fanout::samples 900374 # Request fanout histogram 3736system.toL2Bus.snoop_fanout::mean 0.402074 # Request fanout histogram 3737system.toL2Bus.snoop_fanout::stdev 0.492987 # Request fanout histogram |
| 3733system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3738system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3734system.toL2Bus.snoop_fanout::0 539465 59.70% 59.70% # Request fanout histogram 3735system.toL2Bus.snoop_fanout::1 363157 40.19% 99.88% # Request fanout histogram 3736system.toL2Bus.snoop_fanout::2 1064 0.12% 100.00% # Request fanout histogram | 3739system.toL2Bus.snoop_fanout::0 539539 59.92% 59.92% # Request fanout histogram 3740system.toL2Bus.snoop_fanout::1 359653 39.94% 99.87% # Request fanout histogram 3741system.toL2Bus.snoop_fanout::2 1182 0.13% 100.00% # Request fanout histogram |
| 3737system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3738system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3739system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3742system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3743system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3744system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3740system.toL2Bus.snoop_fanout::total 903686 # Request fanout histogram 3741system.toL2Bus.reqLayer0.occupancy 901600874 # Layer occupancy (ticks) | 3745system.toL2Bus.snoop_fanout::total 900374 # Request fanout histogram 3746system.toL2Bus.reqLayer0.occupancy 896925065 # Layer occupancy (ticks) |
| 3742system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3747system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3743system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) | 3748system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) |
| 3744system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3749system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3745system.toL2Bus.respLayer0.occupancy 679704118 # Layer occupancy (ticks) | 3750system.toL2Bus.respLayer0.occupancy 692605391 # Layer occupancy (ticks) |
| 3746system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3751system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3747system.toL2Bus.respLayer1.occupancy 260937433 # Layer occupancy (ticks) | 3752system.toL2Bus.respLayer1.occupancy 242340870 # Layer occupancy (ticks) |
| 3748system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3749system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 3753system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3754system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 3750system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed | 3755system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed |
| 3751system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3756system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 3752system.cpu1.kern.inst.quiesce 2757 # number of quiesce instructions executed | 3757system.cpu1.kern.inst.quiesce 2732 # number of quiesce instructions executed |
| 3753 3754---------- End Simulation Statistics ---------- | 3758 3759---------- End Simulation Statistics ---------- |