| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825960 # Number of seconds simulated 4sim_ticks 2825959731500 # Number of ticks simulated 5final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825960 # Number of seconds simulated 4sim_ticks 2825959731500 # Number of ticks simulated 5final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 153141 # Simulator instruction rate (inst/s) 8host_op_rate 185771 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3602870624 # Simulator tick rate (ticks/s) 10host_mem_usage 666712 # Number of bytes of host memory used 11host_seconds 784.36 # Real time elapsed on the host | 7host_inst_rate 99061 # Simulator instruction rate (inst/s) 8host_op_rate 120168 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2330545961 # Simulator tick rate (ticks/s) 10host_mem_usage 626024 # Number of bytes of host memory used 11host_seconds 1212.57 # Real time elapsed on the host |
| 12sim_insts 120118276 # Number of instructions simulated 13sim_ops 145712235 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory --- 460 unchanged lines hidden (view full) --- 480system.cpu0.dtb.read_hits 23647306 # DTB read hits 481system.cpu0.dtb.read_misses 56401 # DTB read misses 482system.cpu0.dtb.write_hits 17573284 # DTB write hits 483system.cpu0.dtb.write_misses 10854 # DTB write misses 484system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 485system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 12sim_insts 120118276 # Number of instructions simulated 13sim_ops 145712235 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory --- 460 unchanged lines hidden (view full) --- 480system.cpu0.dtb.read_hits 23647306 # DTB read hits 481system.cpu0.dtb.read_misses 56401 # DTB read misses 482system.cpu0.dtb.write_hits 17573284 # DTB write hits 483system.cpu0.dtb.write_misses 10854 # DTB write misses 484system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 485system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 488system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB | 488system.cpu0.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB |
| 489system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions 490system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 23703707 # DTB read accesses 494system.cpu0.dtb.write_accesses 17584138 # DTB write accesses 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 496system.cpu0.dtb.hits 41220590 # DTB hits --- 82 unchanged lines hidden (view full) --- 579system.cpu0.itb.read_hits 0 # DTB read hits 580system.cpu0.itb.read_misses 0 # DTB read misses 581system.cpu0.itb.write_hits 0 # DTB write hits 582system.cpu0.itb.write_misses 0 # DTB write misses 583system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 584system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 585system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 586system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 489system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions 490system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 23703707 # DTB read accesses 494system.cpu0.dtb.write_accesses 17584138 # DTB write accesses 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 496system.cpu0.dtb.hits 41220590 # DTB hits --- 82 unchanged lines hidden (view full) --- 579system.cpu0.itb.read_hits 0 # DTB read hits 580system.cpu0.itb.read_misses 0 # DTB read misses 581system.cpu0.itb.write_hits 0 # DTB write hits 582system.cpu0.itb.write_misses 0 # DTB write misses 583system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 584system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 585system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 586system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 587system.cpu0.itb.flush_entries 2345 # Number of entries that have been flushed from TLB | 587system.cpu0.itb.flush_entries 2281 # Number of entries that have been flushed from TLB |
| 588system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 589system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 590system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 591system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions 592system.cpu0.itb.read_accesses 0 # DTB read accesses 593system.cpu0.itb.write_accesses 0 # DTB write accesses 594system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses 595system.cpu0.itb.hits 72708872 # DTB hits --- 1128 unchanged lines hidden (view full) --- 1724system.cpu1.dtb.read_hits 4195760 # DTB read hits 1725system.cpu1.dtb.read_misses 18440 # DTB read misses 1726system.cpu1.dtb.write_hits 3493575 # DTB write hits 1727system.cpu1.dtb.write_misses 2970 # DTB write misses 1728system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1729system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1730system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1731system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 588system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 589system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 590system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 591system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions 592system.cpu0.itb.read_accesses 0 # DTB read accesses 593system.cpu0.itb.write_accesses 0 # DTB write accesses 594system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses 595system.cpu0.itb.hits 72708872 # DTB hits --- 1128 unchanged lines hidden (view full) --- 1724system.cpu1.dtb.read_hits 4195760 # DTB read hits 1725system.cpu1.dtb.read_misses 18440 # DTB read misses 1726system.cpu1.dtb.write_hits 3493575 # DTB write hits 1727system.cpu1.dtb.write_misses 2970 # DTB write misses 1728system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1729system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1730system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1731system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1732system.cpu1.dtb.flush_entries 2051 # Number of entries that have been flushed from TLB | 1732system.cpu1.dtb.flush_entries 1987 # Number of entries that have been flushed from TLB |
| 1733system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions 1734system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch 1735system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1736system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions 1737system.cpu1.dtb.read_accesses 4214200 # DTB read accesses 1738system.cpu1.dtb.write_accesses 3496545 # DTB write accesses 1739system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1740system.cpu1.dtb.hits 7689335 # DTB hits --- 84 unchanged lines hidden (view full) --- 1825system.cpu1.itb.read_hits 0 # DTB read hits 1826system.cpu1.itb.read_misses 0 # DTB read misses 1827system.cpu1.itb.write_hits 0 # DTB write hits 1828system.cpu1.itb.write_misses 0 # DTB write misses 1829system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1830system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1831system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1832system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1733system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions 1734system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch 1735system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1736system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions 1737system.cpu1.dtb.read_accesses 4214200 # DTB read accesses 1738system.cpu1.dtb.write_accesses 3496545 # DTB write accesses 1739system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1740system.cpu1.dtb.hits 7689335 # DTB hits --- 84 unchanged lines hidden (view full) --- 1825system.cpu1.itb.read_hits 0 # DTB read hits 1826system.cpu1.itb.read_misses 0 # DTB read misses 1827system.cpu1.itb.write_hits 0 # DTB write hits 1828system.cpu1.itb.write_misses 0 # DTB write misses 1829system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1830system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1831system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1832system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1833system.cpu1.itb.flush_entries 1194 # Number of entries that have been flushed from TLB | 1833system.cpu1.itb.flush_entries 1130 # Number of entries that have been flushed from TLB |
| 1834system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1835system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1836system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1837system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions 1838system.cpu1.itb.read_accesses 0 # DTB read accesses 1839system.cpu1.itb.write_accesses 0 # DTB write accesses 1840system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses 1841system.cpu1.itb.hits 8253439 # DTB hits --- 1915 unchanged lines hidden --- | 1834system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1835system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1836system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1837system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions 1838system.cpu1.itb.read_accesses 0 # DTB read accesses 1839system.cpu1.itb.write_accesses 0 # DTB write accesses 1840system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses 1841system.cpu1.itb.hits 8253439 # DTB hits --- 1915 unchanged lines hidden --- |