| stats.txt (11518:7e0f869f8f7e) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825960 # Number of seconds simulated 4sim_ticks 2825959731500 # Number of ticks simulated 5final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825960 # Number of seconds simulated 4sim_ticks 2825959731500 # Number of ticks simulated 5final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 152939 # Simulator instruction rate (inst/s) 8host_op_rate 185526 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3598106166 # Simulator tick rate (ticks/s) 10host_mem_usage 665816 # Number of bytes of host memory used 11host_seconds 785.40 # Real time elapsed on the host | 7host_inst_rate 153141 # Simulator instruction rate (inst/s) 8host_op_rate 185771 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3602870624 # Simulator tick rate (ticks/s) 10host_mem_usage 666712 # Number of bytes of host memory used 11host_seconds 784.36 # Real time elapsed on the host |
| 12sim_insts 120118276 # Number of instructions simulated 13sim_ops 145712235 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 120118276 # Number of instructions simulated 13sim_ops 145712235 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory --- 315 unchanged lines hidden (view full) --- 339system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ) 340system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ) 341system.physmem_1.averagePower 669.369090 # Core power per rank (mW) 342system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states 343system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states 344system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 345system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states 346system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory --- 315 unchanged lines hidden (view full) --- 340system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ) 341system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ) 342system.physmem_1.averagePower 669.369090 # Core power per rank (mW) 343system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states 344system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states 345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 346system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states 347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 348system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 347system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 349system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 352system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 353system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 355system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 356system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 364system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) | 349system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 352system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 355system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 356system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 358system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 365system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 366system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) |
| 367system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 368system.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 369system.bridge.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 365system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 366system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 367system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 368system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 369system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 370system.cf0.dma_write_txs 631 # Number of DMA write transactions. 371system.cpu0.branchPred.lookups 53057105 # Number of BP lookups 372system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 377system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage 378system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target. 379system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions. 380system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups. 381system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits. 382system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. 383system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. 384system.cpu_clk_domain.clock 500 # Clock period in ticks | 370system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 371system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 372system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 373system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 374system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 375system.cf0.dma_write_txs 631 # Number of DMA write transactions. 376system.cpu0.branchPred.lookups 53057105 # Number of BP lookups 377system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 382system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage 383system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target. 384system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions. 385system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups. 386system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits. 387system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. 388system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. 389system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 390system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 406system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 409system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 410system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 411system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 412system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 413system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 420system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 414system.cpu0.dtb.walker.walks 67255 # Table walker walks requested 415system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors 416system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate 417system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate 418system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting 419system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency --- 62 unchanged lines hidden (view full) --- 484system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 485system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions 486system.cpu0.dtb.read_accesses 23703707 # DTB read accesses 487system.cpu0.dtb.write_accesses 17584138 # DTB write accesses 488system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 489system.cpu0.dtb.hits 41220590 # DTB hits 490system.cpu0.dtb.misses 67255 # DTB misses 491system.cpu0.dtb.accesses 41287845 # DTB accesses | 421system.cpu0.dtb.walker.walks 67255 # Table walker walks requested 422system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors 423system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate 424system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate 425system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting 426system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency --- 62 unchanged lines hidden (view full) --- 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 23703707 # DTB read accesses 494system.cpu0.dtb.write_accesses 17584138 # DTB write accesses 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 496system.cpu0.dtb.hits 41220590 # DTB hits 497system.cpu0.dtb.misses 67255 # DTB misses 498system.cpu0.dtb.accesses 41287845 # DTB accesses |
| 499system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 492system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 513system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 514system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 515system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 516system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 517system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 518system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 519system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 520system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 500system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 521system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 524system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 525system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 526system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 527system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 528system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 529system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 521system.cpu0.itb.walker.walks 10944 # Table walker walks requested 522system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors 523system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate 524system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate 525system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting 526system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency --- 52 unchanged lines hidden (view full) --- 581system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 582system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions 583system.cpu0.itb.read_accesses 0 # DTB read accesses 584system.cpu0.itb.write_accesses 0 # DTB write accesses 585system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses 586system.cpu0.itb.hits 72708872 # DTB hits 587system.cpu0.itb.misses 10944 # DTB misses 588system.cpu0.itb.accesses 72719816 # DTB accesses | 530system.cpu0.itb.walker.walks 10944 # Table walker walks requested 531system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors 532system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate 533system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate 534system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting 535system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency --- 52 unchanged lines hidden (view full) --- 590system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 591system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions 592system.cpu0.itb.read_accesses 0 # DTB read accesses 593system.cpu0.itb.write_accesses 0 # DTB write accesses 594system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses 595system.cpu0.itb.hits 72708872 # DTB hits 596system.cpu0.itb.misses 10944 # DTB misses 597system.cpu0.itb.accesses 72719816 # DTB accesses |
| 598system.cpu0.numPwrStateTransitions 3656 # Number of power state transitions 599system.cpu0.pwrStateClkGateDist::samples 1828 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::mean 1490596475.785011 # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::stdev 23949118810.105305 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::underflows 1055 57.71% 57.71% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1000-5e+10 768 42.01% 99.73% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::max_value 499973380096 # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::total 1828 # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateResidencyTicks::ON 101149373765 # Cumulative time (in ticks) in various power states 610system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724810357735 # Cumulative time (in ticks) in various power states |
|
| 589system.cpu0.numCycles 202299816 # number of cpu cycles simulated 590system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 591system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 592system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss 593system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed 594system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered 595system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken 596system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 875system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads 876system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes 877system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads 878system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 879system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads 880system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes 881system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads 882system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes | 611system.cpu0.numCycles 202299816 # number of cpu cycles simulated 612system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 613system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 614system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss 615system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed 616system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered 617system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken 618system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 897system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads 898system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes 899system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads 900system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 901system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads 902system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes 903system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads 904system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes |
| 905system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 883system.cpu0.dcache.tags.replacements 709828 # number of replacements 884system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use 885system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. 886system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks. 887system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks. 888system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. 889system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor 890system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy 891system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy 892system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 893system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 894system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 895system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 896system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 897system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses 898system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses | 906system.cpu0.dcache.tags.replacements 709828 # number of replacements 907system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use 908system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. 909system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks. 910system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks. 911system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. 912system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor 913system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy 914system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy 915system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 916system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 917system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 918system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 919system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 920system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses 921system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses |
| 922system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 899system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits 900system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits 901system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits 902system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits 903system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits 904system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits 905system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits 906system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 1067system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency 1068system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency 1069system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency 1070system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency 1071system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency 1072system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency 1073system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency 1074system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency | 923system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits 924system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits 925system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits 926system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits 927system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits 928system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits 929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits 930system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 1091system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency 1092system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency 1093system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency 1094system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency 1095system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency 1096system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency 1097system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency 1098system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency |
| 1099system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1075system.cpu0.icache.tags.replacements 1253795 # number of replacements 1076system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use 1077system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. 1078system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks. 1079system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks. 1080system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. 1081system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor 1082system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy 1083system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy 1084system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1085system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 1086system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 1087system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id 1088system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1089system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses 1090system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses | 1100system.cpu0.icache.tags.replacements 1253795 # number of replacements 1101system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use 1102system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. 1103system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks. 1104system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks. 1105system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. 1106system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor 1107system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy 1108system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy 1109system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1110system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 1111system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 1112system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id 1113system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1114system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses 1115system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses |
| 1116system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1091system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits 1092system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits 1093system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits 1094system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits 1095system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits 1096system.cpu0.icache.overall_hits::total 71396857 # number of overall hits 1097system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses 1098system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 1169system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1170system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1171system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1172system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1173system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency 1174system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency 1175system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency 1176system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency | 1117system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits 1118system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits 1119system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits 1120system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits 1121system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits 1122system.cpu0.icache.overall_hits::total 71396857 # number of overall hits 1123system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses 1124system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 1195system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1196system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1197system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1198system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1199system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency 1200system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency 1201system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency 1202system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency |
| 1203system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1177system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued 1178system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified 1179system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue 1180system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1181system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1182system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing | 1204system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued 1205system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified 1206system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue 1207system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1208system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1209system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing |
| 1210system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1183system.cpu0.l2cache.tags.replacements 276743 # number of replacements 1184system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use 1185system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. 1186system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks. 1187system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks. 1188system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1189system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor 1190system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor --- 20 unchanged lines hidden (view full) --- 1211system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id 1212system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id 1213system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id 1215system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 1216system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id 1217system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses 1218system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses | 1211system.cpu0.l2cache.tags.replacements 276743 # number of replacements 1212system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use 1213system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. 1214system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks. 1215system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks. 1216system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1217system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor 1218system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor --- 20 unchanged lines hidden (view full) --- 1239system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id 1240system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id 1241system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id 1242system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id 1243system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 1244system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id 1245system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses 1246system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses |
| 1247system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1219system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits 1220system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits 1221system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits 1222system.cpu0.l2cache.WritebackDirty_hits::writebacks 481730 # number of WritebackDirty hits 1223system.cpu0.l2cache.WritebackDirty_hits::total 481730 # number of WritebackDirty hits 1224system.cpu0.l2cache.WritebackClean_hits::writebacks 1450652 # number of WritebackClean hits 1225system.cpu0.l2cache.WritebackClean_hits::total 1450652 # number of WritebackClean hits 1226system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits --- 301 unchanged lines hidden (view full) --- 1528system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency 1529system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency 1530system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter. 1531system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1532system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1533system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. 1534system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1535system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1248system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits 1249system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits 1250system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits 1251system.cpu0.l2cache.WritebackDirty_hits::writebacks 481730 # number of WritebackDirty hits 1252system.cpu0.l2cache.WritebackDirty_hits::total 481730 # number of WritebackDirty hits 1253system.cpu0.l2cache.WritebackClean_hits::writebacks 1450652 # number of WritebackClean hits 1254system.cpu0.l2cache.WritebackClean_hits::total 1450652 # number of WritebackClean hits 1255system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits --- 301 unchanged lines hidden (view full) --- 1557system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency 1558system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency 1559system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter. 1560system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1561system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1562system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. 1563system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1564system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1565system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1536system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution 1537system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution 1538system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution 1539system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution 1540system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution 1541system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution 1542system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution 1543system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 1593system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1594system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage 1595system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target. 1596system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions. 1597system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups. 1598system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. 1599system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. 1600system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. | 1566system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution 1567system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution 1568system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution 1572system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution 1573system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 1623system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1624system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage 1625system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target. 1626system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions. 1627system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups. 1628system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. 1629system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. 1630system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. |
| 1631system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1601system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1602system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1603system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1604system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1605system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1606system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1607system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1608system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1622system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1623system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1624system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1625system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1626system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1627system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1628system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1629system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1632system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1653system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1654system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1655system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1656system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1657system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1658system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1659system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1660system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1661system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1630system.cpu1.dtb.walker.walks 21410 # Table walker walks requested 1631system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors 1632system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate 1633system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate 1634system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting 1635system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency 1636system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency 1637system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency --- 65 unchanged lines hidden (view full) --- 1703system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1704system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions 1705system.cpu1.dtb.read_accesses 4214200 # DTB read accesses 1706system.cpu1.dtb.write_accesses 3496545 # DTB write accesses 1707system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1708system.cpu1.dtb.hits 7689335 # DTB hits 1709system.cpu1.dtb.misses 21410 # DTB misses 1710system.cpu1.dtb.accesses 7710745 # DTB accesses | 1662system.cpu1.dtb.walker.walks 21410 # Table walker walks requested 1663system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors 1664system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate 1665system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate 1666system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting 1667system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency 1668system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency 1669system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency --- 65 unchanged lines hidden (view full) --- 1735system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1736system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions 1737system.cpu1.dtb.read_accesses 4214200 # DTB read accesses 1738system.cpu1.dtb.write_accesses 3496545 # DTB write accesses 1739system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1740system.cpu1.dtb.hits 7689335 # DTB hits 1741system.cpu1.dtb.misses 21410 # DTB misses 1742system.cpu1.dtb.accesses 7710745 # DTB accesses |
| 1743system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1711system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1712system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1713system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1714system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1715system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1716system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1717system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1718system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1732system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1733system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1734system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1735system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1736system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1737system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1738system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1739system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1744system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1748system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1749system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1750system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1751system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1765system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1766system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1767system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1768system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1769system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1770system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1771system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1772system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1773system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 1740system.cpu1.itb.walker.walks 5994 # Table walker walks requested 1741system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors 1742system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate 1743system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate 1744system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting 1745system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency 1746system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency 1747system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency --- 54 unchanged lines hidden (view full) --- 1802system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1803system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions 1804system.cpu1.itb.read_accesses 0 # DTB read accesses 1805system.cpu1.itb.write_accesses 0 # DTB write accesses 1806system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses 1807system.cpu1.itb.hits 8253439 # DTB hits 1808system.cpu1.itb.misses 5994 # DTB misses 1809system.cpu1.itb.accesses 8259433 # DTB accesses | 1774system.cpu1.itb.walker.walks 5994 # Table walker walks requested 1775system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors 1776system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate 1777system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate 1778system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting 1779system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency 1780system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency 1781system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency --- 54 unchanged lines hidden (view full) --- 1836system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1837system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions 1838system.cpu1.itb.read_accesses 0 # DTB read accesses 1839system.cpu1.itb.write_accesses 0 # DTB write accesses 1840system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses 1841system.cpu1.itb.hits 8253439 # DTB hits 1842system.cpu1.itb.misses 5994 # DTB misses 1843system.cpu1.itb.accesses 8259433 # DTB accesses |
| 1844system.cpu1.numPwrStateTransitions 5525 # Number of power state transitions 1845system.cpu1.pwrStateClkGateDist::samples 2763 # Distribution of time spent in the clock gated state 1846system.cpu1.pwrStateClkGateDist::mean 1016473602.620702 # Distribution of time spent in the clock gated state 1847system.cpu1.pwrStateClkGateDist::stdev 25821981878.711128 # Distribution of time spent in the clock gated state 1848system.cpu1.pwrStateClkGateDist::underflows 1969 71.26% 71.26% # Distribution of time spent in the clock gated state 1849system.cpu1.pwrStateClkGateDist::1000-5e+10 788 28.52% 99.78% # Distribution of time spent in the clock gated state 1850system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state 1851system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1852system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1853system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1854system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1855system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1856system.cpu1.pwrStateClkGateDist::max_value 959984667908 # Distribution of time spent in the clock gated state 1857system.cpu1.pwrStateClkGateDist::total 2763 # Distribution of time spent in the clock gated state 1858system.cpu1.pwrStateResidencyTicks::ON 17443167459 # Cumulative time (in ticks) in various power states 1859system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808516564041 # Cumulative time (in ticks) in various power states |
|
| 1810system.cpu1.numCycles 34887121 # number of cpu cycles simulated 1811system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1812system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1813system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss 1814system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed 1815system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered 1816system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken 1817system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 2096system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads 2097system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes 2098system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads 2099system.cpu1.fp_regfile_writes 516 # number of floating regfile writes 2100system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads 2101system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes 2102system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads 2103system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes | 1860system.cpu1.numCycles 34887121 # number of cpu cycles simulated 1861system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1862system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1863system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss 1864system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed 1865system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered 1866system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken 1867system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 2146system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads 2147system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes 2148system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads 2149system.cpu1.fp_regfile_writes 516 # number of floating regfile writes 2150system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads 2151system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes 2152system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads 2153system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes |
| 2154system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2104system.cpu1.dcache.tags.replacements 189214 # number of replacements 2105system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use 2106system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. 2107system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks. 2108system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks. 2109system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit. 2110system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor 2111system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy 2112system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy 2113system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id 2114system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 2115system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2116system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id 2117system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses 2118system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses | 2155system.cpu1.dcache.tags.replacements 189214 # number of replacements 2156system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use 2157system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. 2158system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks. 2159system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks. 2160system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit. 2161system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor 2162system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy 2163system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy 2164system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id 2165system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 2166system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2167system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id 2168system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses 2169system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses |
| 2170system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2119system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits 2120system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits 2121system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits 2122system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits 2123system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits 2124system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits 2125system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits 2126system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 2287system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency 2288system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency 2289system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency 2290system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency 2291system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency 2292system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency 2293system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency 2294system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency | 2171system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits 2172system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits 2173system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits 2174system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits 2175system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits 2176system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits 2177system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits 2178system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 2339system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency 2340system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency 2341system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency 2342system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency 2343system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency 2344system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency 2345system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency 2346system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency |
| 2347system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2295system.cpu1.icache.tags.replacements 585593 # number of replacements 2296system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use 2297system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. 2298system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks. 2299system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks. 2300system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit. 2301system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor 2302system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy 2303system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy 2304system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2305system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2306system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2307system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2308system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses 2309system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses | 2348system.cpu1.icache.tags.replacements 585593 # number of replacements 2349system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use 2350system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. 2351system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks. 2352system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks. 2353system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit. 2354system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor 2355system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy 2356system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy 2357system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2358system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2359system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2360system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2361system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses 2362system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses |
| 2363system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2310system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits 2311system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits 2312system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits 2313system.cpu1.icache.demand_hits::total 7643805 # number of demand (read+write) hits 2314system.cpu1.icache.overall_hits::cpu1.inst 7643805 # number of overall hits 2315system.cpu1.icache.overall_hits::total 7643805 # number of overall hits 2316system.cpu1.icache.ReadReq_misses::cpu1.inst 608184 # number of ReadReq misses 2317system.cpu1.icache.ReadReq_misses::total 608184 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 2388system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2389system.cpu1.icache.demand_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2390system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2391system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2392system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency 2393system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency 2394system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency 2395system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency | 2364system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits 2365system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits 2366system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits 2367system.cpu1.icache.demand_hits::total 7643805 # number of demand (read+write) hits 2368system.cpu1.icache.overall_hits::cpu1.inst 7643805 # number of overall hits 2369system.cpu1.icache.overall_hits::total 7643805 # number of overall hits 2370system.cpu1.icache.ReadReq_misses::cpu1.inst 608184 # number of ReadReq misses 2371system.cpu1.icache.ReadReq_misses::total 608184 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 2442system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2443system.cpu1.icache.demand_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2444system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2445system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2446system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency 2447system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency 2448system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency 2449system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency |
| 2450system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2396system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued 2397system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified 2398system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue 2399system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2400system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2401system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing | 2451system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued 2452system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified 2453system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue 2454system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2455system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2456system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing |
| 2457system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2402system.cpu1.l2cache.tags.replacements 51951 # number of replacements 2403system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use 2404system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks. 2405system.cpu1.l2cache.tags.sampled_refs 66549 # Sample count of references to valid blocks. 2406system.cpu1.l2cache.tags.avg_refs 19.998678 # Average number of references to valid blocks. 2407system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2408system.cpu1.l2cache.tags.occ_blocks::writebacks 14780.960176 # Average occupied blocks per requestor 2409system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.872611 # Average occupied blocks per requestor --- 16 unchanged lines hidden (view full) --- 2426system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 2427system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id 2428system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4388 # Occupied blocks per task id 2429system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id 2430system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 2431system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id 2432system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses 2433system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses | 2458system.cpu1.l2cache.tags.replacements 51951 # number of replacements 2459system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use 2460system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks. 2461system.cpu1.l2cache.tags.sampled_refs 66549 # Sample count of references to valid blocks. 2462system.cpu1.l2cache.tags.avg_refs 19.998678 # Average number of references to valid blocks. 2463system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2464system.cpu1.l2cache.tags.occ_blocks::writebacks 14780.960176 # Average occupied blocks per requestor 2465system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.872611 # Average occupied blocks per requestor --- 16 unchanged lines hidden (view full) --- 2482system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 2483system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id 2484system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4388 # Occupied blocks per task id 2485system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id 2486system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 2487system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id 2488system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses 2489system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses |
| 2490system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2434system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits 2435system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits 2436system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits 2437system.cpu1.l2cache.WritebackDirty_hits::writebacks 115107 # number of WritebackDirty hits 2438system.cpu1.l2cache.WritebackDirty_hits::total 115107 # number of WritebackDirty hits 2439system.cpu1.l2cache.WritebackClean_hits::writebacks 647294 # number of WritebackClean hits 2440system.cpu1.l2cache.WritebackClean_hits::total 647294 # number of WritebackClean hits 2441system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27150 # number of ReadExReq hits --- 295 unchanged lines hidden (view full) --- 2737system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency 2738system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency 2739system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter. 2740system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2741system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2742system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. 2743system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2744system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2491system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits 2492system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits 2493system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits 2494system.cpu1.l2cache.WritebackDirty_hits::writebacks 115107 # number of WritebackDirty hits 2495system.cpu1.l2cache.WritebackDirty_hits::total 115107 # number of WritebackDirty hits 2496system.cpu1.l2cache.WritebackClean_hits::writebacks 647294 # number of WritebackClean hits 2497system.cpu1.l2cache.WritebackClean_hits::total 647294 # number of WritebackClean hits 2498system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27150 # number of ReadExReq hits --- 295 unchanged lines hidden (view full) --- 2794system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency 2795system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency 2796system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter. 2797system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2798system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2799system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. 2800system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2801system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2802system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2745system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution 2746system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution 2747system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution 2748system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution 2749system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution 2750system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution 2751system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution 2752system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 2789system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks) 2790system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2791system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks) 2792system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2793system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks) 2794system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2795system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) 2796system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2803system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution 2804system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution 2805system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution 2806system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution 2807system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution 2808system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution 2809system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution 2810system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 2847system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks) 2848system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2849system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks) 2850system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2851system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks) 2852system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2853system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) 2854system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2855system.iobus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2797system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2798system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2799system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2800system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2801system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2802system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2803system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2804system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 2883system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks) 2884system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2885system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks) 2886system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2887system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) 2888system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2889system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2890system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2856system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2857system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2858system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2859system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2860system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2861system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2862system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2863system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 2942system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks) 2943system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2944system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks) 2945system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2946system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) 2947system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2948system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2949system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2950system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2891system.iocache.tags.replacements 36458 # number of replacements 2892system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use 2893system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2894system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2895system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2896system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit. 2897system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor 2898system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy 2899system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy 2900system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2901system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2902system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2903system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2904system.iocache.tags.data_accesses 328284 # Number of data accesses | 2951system.iocache.tags.replacements 36458 # number of replacements 2952system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use 2953system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2954system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2955system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2956system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit. 2957system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor 2958system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy 2959system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy 2960system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2961system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2962system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2963system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2964system.iocache.tags.data_accesses 328284 # Number of data accesses |
| 2965system.iocache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2905system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2906system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2907system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2908system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2909system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2910system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2911system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2912system.iocache.overall_misses::total 36476 # number of overall misses --- 64 unchanged lines hidden (view full) --- 2977system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency 2978system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency 2979system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency 2980system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency 2981system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 2982system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency 2983system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 2984system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency | 2966system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2967system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2968system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2969system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2970system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2971system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2972system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2973system.iocache.overall_misses::total 36476 # number of overall misses --- 64 unchanged lines hidden (view full) --- 3038system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency 3039system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency 3040system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency 3041system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency 3042system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 3043system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency 3044system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 3045system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency |
| 3046system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 2985system.l2c.tags.replacements 132778 # number of replacements 2986system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use 2987system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. 2988system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks. 2989system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks. 2990system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2991system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor 2992system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor --- 31 unchanged lines hidden (view full) --- 3024system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id 3025system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id 3026system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id 3027system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id 3028system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id 3029system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id 3030system.l2c.tags.tag_accesses 6131058 # Number of tag accesses 3031system.l2c.tags.data_accesses 6131058 # Number of data accesses | 3047system.l2c.tags.replacements 132778 # number of replacements 3048system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use 3049system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. 3050system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks. 3051system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks. 3052system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3053system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor 3054system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor --- 31 unchanged lines hidden (view full) --- 3086system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id 3087system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id 3088system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id 3089system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id 3090system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id 3091system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id 3092system.l2c.tags.tag_accesses 6131058 # Number of tag accesses 3093system.l2c.tags.data_accesses 6131058 # Number of data accesses |
| 3094system.l2c.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 3032system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits 3033system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits 3034system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits 3035system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits 3036system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits 3037system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits 3038system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits 3039system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits --- 468 unchanged lines hidden (view full) --- 3508system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency 3509system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency 3510system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter. 3511system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3512system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3513system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3514system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3515system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3095system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits 3096system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits 3097system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits 3098system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits 3099system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits 3100system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits 3101system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits 3102system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits --- 468 unchanged lines hidden (view full) --- 3571system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency 3572system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency 3573system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter. 3574system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3575system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3576system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3577system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3578system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3579system.membus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 3516system.membus.trans_dist::ReadReq 37951 # Transaction distribution 3517system.membus.trans_dist::ReadResp 212466 # Transaction distribution 3518system.membus.trans_dist::WriteReq 30885 # Transaction distribution 3519system.membus.trans_dist::WriteResp 30885 # Transaction distribution 3520system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution 3521system.membus.trans_dist::CleanEvict 17155 # Transaction distribution 3522system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution 3523system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3562system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks) 3563system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3564system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks) 3565system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3566system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks) 3567system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3568system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) 3569system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 3580system.membus.trans_dist::ReadReq 37951 # Transaction distribution 3581system.membus.trans_dist::ReadResp 212466 # Transaction distribution 3582system.membus.trans_dist::WriteReq 30885 # Transaction distribution 3583system.membus.trans_dist::WriteResp 30885 # Transaction distribution 3584system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution 3585system.membus.trans_dist::CleanEvict 17155 # Transaction distribution 3586system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution 3587system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3626system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks) 3627system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3628system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks) 3629system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3630system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks) 3631system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3632system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) 3633system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3634system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3635system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3636system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3637system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3638system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3639system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3640system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 3570system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3571system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3572system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3573system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3574system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3575system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3641system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3642system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3643system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3644system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3645system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3646system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3647system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3648system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 3576system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3577system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3578system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3579system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3580system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3581system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3582system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3583system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3599system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3600system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3601system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3602system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3603system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3604system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3605system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3606system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3649system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3650system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3651system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3652system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3653system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3654system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3655system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3656system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3672system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3673system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3674system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3675system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3676system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3677system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3678system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3679system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3680system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3681system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3682system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3683system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3684system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3685system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3686system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 3607system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3608system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3609system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3610system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3687system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3688system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3689system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3690system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3691system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3692system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3693system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3694system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3695system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3696system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3697system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3698system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3699system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3700system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3701system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3702system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 3611system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. 3612system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3613system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3614system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. 3615system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3616system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3703system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. 3704system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3705system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3706system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. 3707system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3708system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3709system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states |
|
| 3617system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution 3618system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution 3619system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution 3620system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution 3621system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution 3622system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution 3623system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution 3624system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution --- 39 unchanged lines hidden --- | 3710system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution 3711system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution 3712system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution 3713system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution 3714system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution 3715system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution 3716system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution 3717system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution --- 39 unchanged lines hidden --- |