Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.825406 # Number of seconds simulated
4sim_ticks 2825405893500 # Number of ticks simulated
5final_tick 2825405893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.627261 # Number of seconds simulated
4sim_ticks 2627260787000 # Number of ticks simulated
5final_tick 2627260787000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 67919 # Simulator instruction rate (inst/s)
8host_op_rate 82398 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1596954995 # Simulator tick rate (ticks/s)
10host_mem_usage 650656 # Number of bytes of host memory used
11host_seconds 1769.25 # Real time elapsed on the host
12sim_insts 120165205 # Number of instructions simulated
13sim_ops 145782922 # Number of ops (including micro ops) simulated

7host_inst_rate 87166 # Simulator instruction rate (inst/s)
8host_op_rate 105753 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1901847747 # Simulator tick rate (ticks/s)
10host_mem_usage 660800 # Number of bytes of host memory used
11host_seconds 1381.43 # Real time elapsed on the host
12sim_insts 120413300 # Number of instructions simulated
13sim_ops 146090184 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1275648 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1290856 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427776 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory

16system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1139008 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1190376 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8167488 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory

22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory

23system.physmem.bytes_read::cpu1.inst 182944 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 606480 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 427776 # Number of bytes read from this memory

23system.physmem.bytes_read::cpu1.inst 326368 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 665684 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 594880 # Number of bytes read from this memory

26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory

27system.physmem.bytes_read::total 12214872 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1275648 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 182944 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1458592 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 8756928 # Number of bytes written to this memory

27system.physmem.bytes_read::total 12087580 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1139008 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 326368 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1465376 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 8694784 # Number of bytes written to this memory

32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory

34system.physmem.bytes_written::total 8774492 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 22179 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 20690 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 131684 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory

34system.physmem.bytes_written::total 8712348 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 20044 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 19120 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 127617 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory

41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory

42system.physmem.num_reads::cpu1.inst 2926 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 9496 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 6684 # Number of read requests responded to by this memory

42system.physmem.num_reads::cpu1.inst 5167 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 10422 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 9295 # Number of read requests responded to by this memory

45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory

46system.physmem.num_reads::total 193712 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 136827 # Number of write requests responded to by this memory

46system.physmem.num_reads::total 191724 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 135856 # Number of write requests responded to by this memory

48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory

50system.physmem.num_writes::total 141218 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 451492 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 456875 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 2982855 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 204 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 64750 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 214652 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 151403 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 4323227 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 451492 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 64750 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 516242 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 3099352 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 6202 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 3105569 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 3099352 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 451492 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 463077 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 2982855 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 204 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 64750 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 214667 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 151403 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 7428796 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 193713 # Number of read requests accepted
84system.physmem.writeReqs 141218 # Number of write requests accepted
85system.physmem.readBursts 193713 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 141218 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 12387136 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue
89system.physmem.bytesWritten 8786752 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 12214936 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 8774492 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue

50system.physmem.num_writes::total 140247 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 585 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 433534 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 453086 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 3108747 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 341 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 124224 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 253376 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 226426 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 365 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 4600830 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 433534 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 124224 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 557758 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 3309448 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 6670 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 3316134 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 3309448 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 585 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 433534 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 459756 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 3108747 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 341 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 124224 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 253391 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 226426 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 365 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 7916964 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 191724 # Number of read requests accepted
84system.physmem.writeReqs 140247 # Number of write requests accepted
85system.physmem.readBursts 191724 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 140247 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 12260288 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue
89system.physmem.bytesWritten 8725248 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 12087580 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 8712348 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue

93system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one

94system.physmem.neitherReadNorWriteReqs 49946 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 12421 # Per bank write bursts
96system.physmem.perBankRdBursts::1 11965 # Per bank write bursts
97system.physmem.perBankRdBursts::2 12291 # Per bank write bursts
98system.physmem.perBankRdBursts::3 13088 # Per bank write bursts
99system.physmem.perBankRdBursts::4 14558 # Per bank write bursts
100system.physmem.perBankRdBursts::5 12211 # Per bank write bursts
101system.physmem.perBankRdBursts::6 11940 # Per bank write bursts
102system.physmem.perBankRdBursts::7 12041 # Per bank write bursts
103system.physmem.perBankRdBursts::8 12092 # Per bank write bursts
104system.physmem.perBankRdBursts::9 12171 # Per bank write bursts
105system.physmem.perBankRdBursts::10 11769 # Per bank write bursts
106system.physmem.perBankRdBursts::11 10768 # Per bank write bursts
107system.physmem.perBankRdBursts::12 11340 # Per bank write bursts
108system.physmem.perBankRdBursts::13 12292 # Per bank write bursts
109system.physmem.perBankRdBursts::14 11321 # Per bank write bursts
110system.physmem.perBankRdBursts::15 11281 # Per bank write bursts
111system.physmem.perBankWrBursts::0 9078 # Per bank write bursts
112system.physmem.perBankWrBursts::1 8838 # Per bank write bursts
113system.physmem.perBankWrBursts::2 9120 # Per bank write bursts
114system.physmem.perBankWrBursts::3 9597 # Per bank write bursts
115system.physmem.perBankWrBursts::4 8379 # Per bank write bursts
116system.physmem.perBankWrBursts::5 8806 # Per bank write bursts
117system.physmem.perBankWrBursts::6 8536 # Per bank write bursts
118system.physmem.perBankWrBursts::7 8489 # Per bank write bursts
119system.physmem.perBankWrBursts::8 8658 # Per bank write bursts
120system.physmem.perBankWrBursts::9 8679 # Per bank write bursts
121system.physmem.perBankWrBursts::10 8573 # Per bank write bursts
122system.physmem.perBankWrBursts::11 8021 # Per bank write bursts
123system.physmem.perBankWrBursts::12 8348 # Per bank write bursts
124system.physmem.perBankWrBursts::13 8584 # Per bank write bursts
125system.physmem.perBankWrBursts::14 7909 # Per bank write bursts
126system.physmem.perBankWrBursts::15 7678 # Per bank write bursts

94system.physmem.neitherReadNorWriteReqs 50731 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 11367 # Per bank write bursts
96system.physmem.perBankRdBursts::1 11306 # Per bank write bursts
97system.physmem.perBankRdBursts::2 12534 # Per bank write bursts
98system.physmem.perBankRdBursts::3 11925 # Per bank write bursts
99system.physmem.perBankRdBursts::4 14392 # Per bank write bursts
100system.physmem.perBankRdBursts::5 11995 # Per bank write bursts
101system.physmem.perBankRdBursts::6 12528 # Per bank write bursts
102system.physmem.perBankRdBursts::7 12413 # Per bank write bursts
103system.physmem.perBankRdBursts::8 12465 # Per bank write bursts
104system.physmem.perBankRdBursts::9 12343 # Per bank write bursts
105system.physmem.perBankRdBursts::10 12048 # Per bank write bursts
106system.physmem.perBankRdBursts::11 11291 # Per bank write bursts
107system.physmem.perBankRdBursts::12 11598 # Per bank write bursts
108system.physmem.perBankRdBursts::13 11714 # Per bank write bursts
109system.physmem.perBankRdBursts::14 10851 # Per bank write bursts
110system.physmem.perBankRdBursts::15 10797 # Per bank write bursts
111system.physmem.perBankWrBursts::0 8020 # Per bank write bursts
112system.physmem.perBankWrBursts::1 8176 # Per bank write bursts
113system.physmem.perBankWrBursts::2 9316 # Per bank write bursts
114system.physmem.perBankWrBursts::3 8567 # Per bank write bursts
115system.physmem.perBankWrBursts::4 8317 # Per bank write bursts
116system.physmem.perBankWrBursts::5 8617 # Per bank write bursts
117system.physmem.perBankWrBursts::6 9080 # Per bank write bursts
118system.physmem.perBankWrBursts::7 8981 # Per bank write bursts
119system.physmem.perBankWrBursts::8 9059 # Per bank write bursts
120system.physmem.perBankWrBursts::9 8883 # Per bank write bursts
121system.physmem.perBankWrBursts::10 8732 # Per bank write bursts
122system.physmem.perBankWrBursts::11 8494 # Per bank write bursts
123system.physmem.perBankWrBursts::12 8573 # Per bank write bursts
124system.physmem.perBankWrBursts::13 8275 # Per bank write bursts
125system.physmem.perBankWrBursts::14 7766 # Per bank write bursts
126system.physmem.perBankWrBursts::15 7476 # Per bank write bursts

127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry

128system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
129system.physmem.totGap 2825405630500 # Total gap between requests

128system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
129system.physmem.totGap 2627260507500 # Total gap between requests

130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)

132system.physmem.readPktSize::2 550 # Read request sizes (log2)

132system.physmem.readPktSize::2 551 # Read request sizes (log2)

133system.physmem.readPktSize::3 28 # Read request sizes (log2)
134system.physmem.readPktSize::4 3086 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)

136system.physmem.readPktSize::6 190049 # Read request sizes (log2)

136system.physmem.readPktSize::6 188059 # Read request sizes (log2)

137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 4391 # Write request sizes (log2)
140system.physmem.writePktSize::3 0 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)

143system.physmem.writePktSize::6 136827 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 58643 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 71509 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 15316 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 12788 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 8414 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 7274 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 6278 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 5174 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 4590 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 1392 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 933 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 285 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 252 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see

143system.physmem.writePktSize::6 135856 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 61031 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 73227 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 12933 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 10004 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 8250 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 7158 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 6223 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 5068 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 4443 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 1296 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 829 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 578 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 273 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see

164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see

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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see

191system.physmem.wrQLenPdf::15 2640 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 3080 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 4486 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 5017 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 5343 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 5977 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 8098 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 8572 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 9894 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 9480 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 9411 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 8905 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 10669 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 8786 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 8210 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 7795 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 707 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 426 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 426 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 219 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 216 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 163 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 114 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 124 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 112 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 87370 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 242.346618 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 136.604135 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 304.406981 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 46631 53.37% 53.37% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 17108 19.58% 72.95% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 5841 6.69% 79.64% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 3374 3.86% 83.50% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 2711 3.10% 86.60% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 1534 1.76% 88.36% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 893 1.02% 89.38% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 1014 1.16% 90.54% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 8264 9.46% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 87370 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 6825 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 28.358242 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 561.081040 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-2047 6823 99.97% 99.97% # Reads before turning the bus around for writes

191system.physmem.wrQLenPdf::15 2647 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 3122 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 4091 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 5482 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 5940 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 7239 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 7402 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 8568 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 9044 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 9358 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 10932 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 9335 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 9345 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 10651 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 8993 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 8113 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 7579 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 660 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 427 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 324 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 169 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 117 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 131 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 86 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 74 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 86649 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 242.189431 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 136.582911 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 303.571271 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 46399 53.55% 53.55% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 16583 19.14% 72.69% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 5986 6.91% 79.59% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 3348 3.86% 83.46% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 2763 3.19% 86.65% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 1550 1.79% 88.44% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 1005 1.16% 89.60% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 914 1.05% 90.65% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 8101 9.35% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 86649 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 6686 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 28.651211 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 549.102387 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-2047 6684 99.97% 99.97% # Reads before turning the bus around for writes

258system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes

259system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::total 6825 # Reads before turning the bus around for writes
261system.physmem.wrPerTurnAround::samples 6825 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::mean 20.116190 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::gmean 18.646323 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::stdev 12.038338 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::16-19 5646 82.73% 82.73% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::20-23 406 5.95% 88.67% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::24-27 199 2.92% 91.59% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::28-31 55 0.81% 92.40% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::32-35 78 1.14% 93.54% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::36-39 151 2.21% 95.75% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::40-43 25 0.37% 96.12% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::44-47 11 0.16% 96.28% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::48-51 15 0.22% 96.50% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::52-55 9 0.13% 96.63% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::56-59 8 0.12% 96.75% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::60-63 6 0.09% 96.84% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::64-67 163 2.39% 99.22% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::68-71 7 0.10% 99.33% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::72-75 2 0.03% 99.36% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::76-79 8 0.12% 99.47% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::92-95 2 0.03% 99.55% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::104-107 2 0.03% 99.60% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::112-115 1 0.01% 99.62% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::120-123 2 0.03% 99.65% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::128-131 16 0.23% 99.88% # Writes before turning the bus around for reads

259system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::total 6686 # Reads before turning the bus around for writes
261system.physmem.wrPerTurnAround::samples 6686 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::mean 20.390667 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::gmean 18.828394 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::stdev 12.276627 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::16-19 5432 81.24% 81.24% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::20-23 492 7.36% 88.60% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::24-27 97 1.45% 90.05% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::28-31 153 2.29% 92.34% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::32-35 34 0.51% 92.85% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::36-39 125 1.87% 94.72% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::40-43 42 0.63% 95.35% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::44-47 20 0.30% 95.65% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::48-51 24 0.36% 96.01% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::52-55 25 0.37% 96.38% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::56-59 6 0.09% 96.47% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::60-63 6 0.09% 96.56% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::64-67 159 2.38% 98.94% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::68-71 6 0.09% 99.03% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::72-75 6 0.09% 99.12% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::76-79 24 0.36% 99.48% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::80-83 8 0.12% 99.60% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::84-87 3 0.04% 99.64% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::100-103 2 0.03% 99.70% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::128-131 8 0.12% 99.87% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads

289system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads

290system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::148-151 1 0.01% 99.94% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::152-155 1 0.01% 99.96% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads

290system.physmem.wrPerTurnAround::152-155 1 0.01% 99.93% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::180-183 1 0.01% 99.97% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads

294system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads

295system.physmem.wrPerTurnAround::total 6825 # Writes before turning the bus around for reads
296system.physmem.totQLat 6500326386 # Total ticks spent queuing
297system.physmem.totMemAccLat 10129370136 # Total ticks spent from burst creation until serviced by the DRAM
298system.physmem.totBusLat 967745000 # Total ticks spent in databus transfers
299system.physmem.avgQLat 33584.91 # Average queueing delay per DRAM burst

295system.physmem.wrPerTurnAround::total 6686 # Writes before turning the bus around for reads
296system.physmem.totQLat 6416960776 # Total ticks spent queuing
297system.physmem.totMemAccLat 10008842026 # Total ticks spent from burst creation until serviced by the DRAM
298system.physmem.totBusLat 957835000 # Total ticks spent in databus transfers
299system.physmem.avgQLat 33497.21 # Average queueing delay per DRAM burst

300system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

301system.physmem.avgMemAccLat 52334.91 # Average memory access latency per DRAM burst
302system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s
303system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s
304system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s
305system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s

301system.physmem.avgMemAccLat 52247.21 # Average memory access latency per DRAM burst
302system.physmem.avgRdBW 4.67 # Average DRAM read bandwidth in MiByte/s
303system.physmem.avgWrBW 3.32 # Average achieved write bandwidth in MiByte/s
304system.physmem.avgRdBWSys 4.60 # Average system read bandwidth in MiByte/s
305system.physmem.avgWrBWSys 3.32 # Average system write bandwidth in MiByte/s

306system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
307system.physmem.busUtil 0.06 # Data bus utilization in percentage

308system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
309system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
310system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
311system.physmem.avgWrQLen 27.47 # Average write queue length when enqueuing
312system.physmem.readRowHits 161846 # Number of row buffer hits during reads
313system.physmem.writeRowHits 81625 # Number of row buffer hits during writes
314system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads
315system.physmem.writeRowHitRate 59.44 # Row buffer hit rate for writes
316system.physmem.avgGap 8435784.18 # Average gap between requests
317system.physmem.pageHitRate 73.58 # Row buffer hit rate, read and write combined
318system.physmem_0.actEnergy 343821240 # Energy for activate commands per rank (pJ)
319system.physmem_0.preEnergy 187600875 # Energy for precharge commands per rank (pJ)
320system.physmem_0.readEnergy 784017000 # Energy for read commands per rank (pJ)
321system.physmem_0.writeEnergy 459062640 # Energy for write commands per rank (pJ)
322system.physmem_0.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ)
323system.physmem_0.actBackEnergy 79593993450 # Energy for active background per rank (pJ)
324system.physmem_0.preBackEnergy 1625423449500 # Energy for precharge background per rank (pJ)
325system.physmem_0.totalEnergy 1891333620465 # Total energy per rank (pJ)
326system.physmem_0.averagePower 669.402761 # Core power per rank (mW)
327system.physmem_0.memoryStateTime::IDLE 2703936458200 # Time in different power states
328system.physmem_0.memoryStateTime::REF 94346460000 # Time in different power states

308system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
309system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
310system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
311system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing
312system.physmem.readRowHits 159898 # Number of row buffer hits during reads
313system.physmem.writeRowHits 81351 # Number of row buffer hits during writes
314system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
315system.physmem.writeRowHitRate 59.66 # Row buffer hit rate for writes
316system.physmem.avgGap 7914126.56 # Average gap between requests
317system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined
318system.physmem_0.actEnergy 337168440 # Energy for activate commands per rank (pJ)
319system.physmem_0.preEnergy 183970875 # Energy for precharge commands per rank (pJ)
320system.physmem_0.readEnergy 767988000 # Energy for read commands per rank (pJ)
321system.physmem_0.writeEnergy 447599520 # Energy for write commands per rank (pJ)
322system.physmem_0.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ)
323system.physmem_0.actBackEnergy 75926466675 # Energy for active background per rank (pJ)
324system.physmem_0.preBackEnergy 1509753884250 # Energy for precharge background per rank (pJ)
325system.physmem_0.totalEnergy 1759016918640 # Total energy per rank (pJ)
326system.physmem_0.averagePower 669.525234 # Core power per rank (mW)
327system.physmem_0.memoryStateTime::IDLE 2511501025755 # Time in different power states
328system.physmem_0.memoryStateTime::REF 87729980000 # Time in different power states

329system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

330system.physmem_0.memoryStateTime::ACT 27121665550 # Time in different power states

330system.physmem_0.memoryStateTime::ACT 28029087995 # Time in different power states

331system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states

332system.physmem_1.actEnergy 316695960 # Energy for activate commands per rank (pJ)
333system.physmem_1.preEnergy 172800375 # Energy for precharge commands per rank (pJ)
334system.physmem_1.readEnergy 725657400 # Energy for read commands per rank (pJ)
335system.physmem_1.writeEnergy 430596000 # Energy for write commands per rank (pJ)
336system.physmem_1.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ)
337system.physmem_1.actBackEnergy 78590048175 # Energy for active background per rank (pJ)
338system.physmem_1.preBackEnergy 1626304103250 # Energy for precharge background per rank (pJ)
339system.physmem_1.totalEnergy 1891081576920 # Total energy per rank (pJ)
340system.physmem_1.averagePower 669.313555 # Core power per rank (mW)
341system.physmem_1.memoryStateTime::IDLE 2705408031049 # Time in different power states
342system.physmem_1.memoryStateTime::REF 94346460000 # Time in different power states

332system.physmem_1.actEnergy 317898000 # Energy for activate commands per rank (pJ)
333system.physmem_1.preEnergy 173456250 # Energy for precharge commands per rank (pJ)
334system.physmem_1.readEnergy 726226800 # Energy for read commands per rank (pJ)
335system.physmem_1.writeEnergy 435831840 # Energy for write commands per rank (pJ)
336system.physmem_1.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ)
337system.physmem_1.actBackEnergy 75533290650 # Energy for active background per rank (pJ)
338system.physmem_1.preBackEnergy 1510098775500 # Energy for precharge background per rank (pJ)
339system.physmem_1.totalEnergy 1758885319920 # Total energy per rank (pJ)
340system.physmem_1.averagePower 669.475144 # Core power per rank (mW)
341system.physmem_1.memoryStateTime::IDLE 2512077352355 # Time in different power states
342system.physmem_1.memoryStateTime::REF 87729980000 # Time in different power states

343system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

344system.physmem_1.memoryStateTime::ACT 25651382451 # Time in different power states

344system.physmem_1.memoryStateTime::ACT 27453418145 # Time in different power states

345system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
346system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
347system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
348system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
349system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
350system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
351system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
352system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
353system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
354system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory

355system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
356system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
357system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
358system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
359system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
360system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
361system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
362system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
363system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)

355system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s)
356system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s)
357system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s)
358system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s)
359system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s)
360system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s)
361system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s)
362system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s)
363system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s)

364system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
365system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
366system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
367system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
368system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
369system.cf0.dma_write_txs 631 # Number of DMA write transactions.

370system.cpu0.branchPred.lookups 24021626 # Number of BP lookups
371system.cpu0.branchPred.condPredicted 15717395 # Number of conditional branches predicted
372system.cpu0.branchPred.condIncorrect 977579 # Number of conditional branches incorrect
373system.cpu0.branchPred.BTBLookups 14633586 # Number of BTB lookups
374system.cpu0.branchPred.BTBHits 10784998 # Number of BTB hits

370system.cpu0.branchPred.lookups 22632354 # Number of BP lookups
371system.cpu0.branchPred.condPredicted 14659623 # Number of conditional branches predicted
372system.cpu0.branchPred.condIncorrect 908184 # Number of conditional branches incorrect
373system.cpu0.branchPred.BTBLookups 13749139 # Number of BTB lookups
374system.cpu0.branchPred.BTBHits 10145845 # Number of BTB hits

375system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

376system.cpu0.branchPred.BTBHitPct 73.700308 # BTB Hit Percentage
377system.cpu0.branchPred.usedRAS 3879887 # Number of times the RAS was used to get a target.
378system.cpu0.branchPred.RASInCorrect 32532 # Number of incorrect RAS predictions.

376system.cpu0.branchPred.BTBHitPct 73.792584 # BTB Hit Percentage
377system.cpu0.branchPred.usedRAS 3729563 # Number of times the RAS was used to get a target.
378system.cpu0.branchPred.RASInCorrect 29268 # Number of incorrect RAS predictions.

379system.cpu_clk_domain.clock 500 # Clock period in ticks
380system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

401system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
402system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
403system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
404system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
405system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
406system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
407system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
408system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

409system.cpu0.dtb.walker.walks 65547 # Table walker walks requested
410system.cpu0.dtb.walker.walksShort 65547 # Table walker walks initiated with short descriptors
411system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26411 # Level at which table walker walks with short descriptors terminate
412system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18806 # Level at which table walker walks with short descriptors terminate
413system.cpu0.dtb.walker.walksSquashedBefore 20330 # Table walks squashed before starting
414system.cpu0.dtb.walker.walkWaitTime::samples 45217 # Table walker wait (enqueue to first request) latency
415system.cpu0.dtb.walker.walkWaitTime::mean 420.151713 # Table walker wait (enqueue to first request) latency
416system.cpu0.dtb.walker.walkWaitTime::stdev 2682.973536 # Table walker wait (enqueue to first request) latency
417system.cpu0.dtb.walker.walkWaitTime::0-8191 44150 97.64% 97.64% # Table walker wait (enqueue to first request) latency
418system.cpu0.dtb.walker.walkWaitTime::8192-16383 821 1.82% 99.46% # Table walker wait (enqueue to first request) latency
419system.cpu0.dtb.walker.walkWaitTime::16384-24575 92 0.20% 99.66% # Table walker wait (enqueue to first request) latency
420system.cpu0.dtb.walker.walkWaitTime::24576-32767 122 0.27% 99.93% # Table walker wait (enqueue to first request) latency
421system.cpu0.dtb.walker.walkWaitTime::32768-40959 7 0.02% 99.94% # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::40960-49151 22 0.05% 99.99% # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::total 45217 # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkCompletionTime::samples 15532 # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::mean 9209.084471 # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::gmean 7773.401889 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::stdev 5863.053322 # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::0-16383 14685 94.55% 94.55% # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::16384-32767 794 5.11% 99.66% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.30% 99.96% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::total 15532 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walksPending::samples 89510783948 # Table walker pending requests distribution
438system.cpu0.dtb.walker.walksPending::mean 0.549501 # Table walker pending requests distribution
439system.cpu0.dtb.walker.walksPending::stdev 0.505567 # Table walker pending requests distribution
440system.cpu0.dtb.walker.walksPending::0-1 89461994948 99.95% 99.95% # Table walker pending requests distribution
441system.cpu0.dtb.walker.walksPending::2-3 35577000 0.04% 99.99% # Table walker pending requests distribution
442system.cpu0.dtb.walker.walksPending::4-5 6153500 0.01% 99.99% # Table walker pending requests distribution
443system.cpu0.dtb.walker.walksPending::6-7 3637000 0.00% 100.00% # Table walker pending requests distribution
444system.cpu0.dtb.walker.walksPending::8-9 1264000 0.00% 100.00% # Table walker pending requests distribution
445system.cpu0.dtb.walker.walksPending::10-11 750500 0.00% 100.00% # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::12-13 798000 0.00% 100.00% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::14-15 605000 0.00% 100.00% # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::16-17 4000 0.00% 100.00% # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::total 89510783948 # Table walker pending requests distribution
450system.cpu0.dtb.walker.walkPageSizes::4K 5141 79.20% 79.20% # Table walker page sizes translated
451system.cpu0.dtb.walker.walkPageSizes::1M 1350 20.80% 100.00% # Table walker page sizes translated
452system.cpu0.dtb.walker.walkPageSizes::total 6491 # Table walker page sizes translated
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65547 # Table walker requests started/completed, data/inst

409system.cpu0.dtb.walker.walks 62082 # Table walker walks requested
410system.cpu0.dtb.walker.walksShort 62082 # Table walker walks initiated with short descriptors
411system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23874 # Level at which table walker walks with short descriptors terminate
412system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18654 # Level at which table walker walks with short descriptors terminate
413system.cpu0.dtb.walker.walksSquashedBefore 19554 # Table walks squashed before starting
414system.cpu0.dtb.walker.walkWaitTime::samples 42528 # Table walker wait (enqueue to first request) latency
415system.cpu0.dtb.walker.walkWaitTime::mean 489.830229 # Table walker wait (enqueue to first request) latency
416system.cpu0.dtb.walker.walkWaitTime::stdev 2960.338749 # Table walker wait (enqueue to first request) latency
417system.cpu0.dtb.walker.walkWaitTime::0-8191 41379 97.30% 97.30% # Table walker wait (enqueue to first request) latency
418system.cpu0.dtb.walker.walkWaitTime::8192-16383 822 1.93% 99.23% # Table walker wait (enqueue to first request) latency
419system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.35% 99.58% # Table walker wait (enqueue to first request) latency
420system.cpu0.dtb.walker.walkWaitTime::24576-32767 139 0.33% 99.91% # Table walker wait (enqueue to first request) latency
421system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.94% # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::total 42528 # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkCompletionTime::samples 15147 # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::mean 9846.471248 # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::gmean 8208.075631 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::stdev 8231.250252 # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::0-32767 15054 99.39% 99.39% # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::32768-65535 70 0.46% 99.85% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.14% 99.99% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::total 15147 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walksPending::samples 97524095656 # Table walker pending requests distribution
438system.cpu0.dtb.walker.walksPending::mean 0.460762 # Table walker pending requests distribution
439system.cpu0.dtb.walker.walksPending::stdev 0.504971 # Table walker pending requests distribution
440system.cpu0.dtb.walker.walksPending::0-1 97474132156 99.95% 99.95% # Table walker pending requests distribution
441system.cpu0.dtb.walker.walksPending::2-3 37222000 0.04% 99.99% # Table walker pending requests distribution
442system.cpu0.dtb.walker.walksPending::4-5 6333500 0.01% 99.99% # Table walker pending requests distribution
443system.cpu0.dtb.walker.walksPending::6-7 3452500 0.00% 100.00% # Table walker pending requests distribution
444system.cpu0.dtb.walker.walksPending::8-9 1280500 0.00% 100.00% # Table walker pending requests distribution
445system.cpu0.dtb.walker.walksPending::10-11 673000 0.00% 100.00% # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::12-13 722500 0.00% 100.00% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::14-15 263000 0.00% 100.00% # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::16-17 16500 0.00% 100.00% # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::total 97524095656 # Table walker pending requests distribution
450system.cpu0.dtb.walker.walkPageSizes::4K 5018 79.05% 79.05% # Table walker page sizes translated
451system.cpu0.dtb.walker.walkPageSizes::1M 1330 20.95% 100.00% # Table walker page sizes translated
452system.cpu0.dtb.walker.walkPageSizes::total 6348 # Table walker page sizes translated
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62082 # Table walker requests started/completed, data/inst

454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst

455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65547 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6491 # Table walker requests started/completed, data/inst

455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62082 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6348 # Table walker requests started/completed, data/inst

457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst

458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6491 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.walker.walkRequestOrigin::total 72038 # Table walker requests started/completed, data/inst

458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6348 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.walker.walkRequestOrigin::total 68430 # Table walker requests started/completed, data/inst

460system.cpu0.dtb.inst_hits 0 # ITB inst hits
461system.cpu0.dtb.inst_misses 0 # ITB inst misses

462system.cpu0.dtb.read_hits 17771522 # DTB read hits
463system.cpu0.dtb.read_misses 55962 # DTB read misses
464system.cpu0.dtb.write_hits 14661221 # DTB write hits
465system.cpu0.dtb.write_misses 9585 # DTB write misses

462system.cpu0.dtb.read_hits 16776749 # DTB read hits
463system.cpu0.dtb.read_misses 53234 # DTB read misses
464system.cpu0.dtb.write_hits 13912942 # DTB write hits
465system.cpu0.dtb.write_misses 8848 # DTB write misses

466system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
467system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
468system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
469system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID

470system.cpu0.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB
471system.cpu0.dtb.align_faults 322 # Number of TLB faults due to alignment restrictions
472system.cpu0.dtb.prefetch_faults 2338 # Number of TLB faults due to prefetch

470system.cpu0.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB
471system.cpu0.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions
472system.cpu0.dtb.prefetch_faults 2058 # Number of TLB faults due to prefetch

473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions

474system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions
475system.cpu0.dtb.read_accesses 17827484 # DTB read accesses
476system.cpu0.dtb.write_accesses 14670806 # DTB write accesses

474system.cpu0.dtb.perms_faults 829 # Number of TLB faults due to permissions restrictions
475system.cpu0.dtb.read_accesses 16829983 # DTB read accesses
476system.cpu0.dtb.write_accesses 13921790 # DTB write accesses

477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses

478system.cpu0.dtb.hits 32432743 # DTB hits
479system.cpu0.dtb.misses 65547 # DTB misses
480system.cpu0.dtb.accesses 32498290 # DTB accesses

478system.cpu0.dtb.hits 30689691 # DTB hits
479system.cpu0.dtb.misses 62082 # DTB misses
480system.cpu0.dtb.accesses 30751773 # DTB accesses

481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

510system.cpu0.itb.walker.walks 10460 # Table walker walks requested
511system.cpu0.itb.walker.walksShort 10460 # Table walker walks initiated with short descriptors
512system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4240 # Level at which table walker walks with short descriptors terminate
513system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6125 # Level at which table walker walks with short descriptors terminate
514system.cpu0.itb.walker.walksSquashedBefore 95 # Table walks squashed before starting
515system.cpu0.itb.walker.walkWaitTime::samples 10365 # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkWaitTime::mean 435.745297 # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkWaitTime::stdev 2168.024140 # Table walker wait (enqueue to first request) latency
518system.cpu0.itb.walker.walkWaitTime::0-4095 9957 96.06% 96.06% # Table walker wait (enqueue to first request) latency
519system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.42% 97.48% # Table walker wait (enqueue to first request) latency
520system.cpu0.itb.walker.walkWaitTime::8192-12287 193 1.86% 99.34% # Table walker wait (enqueue to first request) latency
521system.cpu0.itb.walker.walkWaitTime::12288-16383 32 0.31% 99.65% # Table walker wait (enqueue to first request) latency
522system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.76% # Table walker wait (enqueue to first request) latency
523system.cpu0.itb.walker.walkWaitTime::20480-24575 17 0.16% 99.92% # Table walker wait (enqueue to first request) latency
524system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency
525system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
526system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
527system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency
528system.cpu0.itb.walker.walkWaitTime::total 10365 # Table walker wait (enqueue to first request) latency
529system.cpu0.itb.walker.walkCompletionTime::samples 2678 # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::mean 10848.207618 # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::gmean 9582.239797 # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::stdev 5620.252827 # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::0-8191 1037 38.72% 38.72% # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::8192-16383 1516 56.61% 95.33% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::16384-24575 52 1.94% 97.27% # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::24576-32767 65 2.43% 99.70% # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.89% # Table walker service (enqueue to completion) latency
538system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
539system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
540system.cpu0.itb.walker.walkCompletionTime::total 2678 # Table walker service (enqueue to completion) latency
541system.cpu0.itb.walker.walksPending::samples 20779406712 # Table walker pending requests distribution
542system.cpu0.itb.walker.walksPending::mean 0.976236 # Table walker pending requests distribution
543system.cpu0.itb.walker.walksPending::stdev 0.152563 # Table walker pending requests distribution
544system.cpu0.itb.walker.walksPending::0 494503000 2.38% 2.38% # Table walker pending requests distribution
545system.cpu0.itb.walker.walksPending::1 20284294712 97.62% 100.00% # Table walker pending requests distribution
546system.cpu0.itb.walker.walksPending::2 517000 0.00% 100.00% # Table walker pending requests distribution
547system.cpu0.itb.walker.walksPending::3 92000 0.00% 100.00% # Table walker pending requests distribution
548system.cpu0.itb.walker.walksPending::total 20779406712 # Table walker pending requests distribution
549system.cpu0.itb.walker.walkPageSizes::4K 2260 87.50% 87.50% # Table walker page sizes translated
550system.cpu0.itb.walker.walkPageSizes::1M 323 12.50% 100.00% # Table walker page sizes translated
551system.cpu0.itb.walker.walkPageSizes::total 2583 # Table walker page sizes translated

510system.cpu0.itb.walker.walks 10470 # Table walker walks requested
511system.cpu0.itb.walker.walksShort 10470 # Table walker walks initiated with short descriptors
512system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4275 # Level at which table walker walks with short descriptors terminate
513system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6082 # Level at which table walker walks with short descriptors terminate
514system.cpu0.itb.walker.walksSquashedBefore 113 # Table walks squashed before starting
515system.cpu0.itb.walker.walkWaitTime::samples 10357 # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkWaitTime::mean 430.336970 # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkWaitTime::stdev 2100.288015 # Table walker wait (enqueue to first request) latency
518system.cpu0.itb.walker.walkWaitTime::0-4095 9961 96.18% 96.18% # Table walker wait (enqueue to first request) latency
519system.cpu0.itb.walker.walkWaitTime::4096-8191 126 1.22% 97.39% # Table walker wait (enqueue to first request) latency
520system.cpu0.itb.walker.walkWaitTime::8192-12287 203 1.96% 99.35% # Table walker wait (enqueue to first request) latency
521system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.37% 99.72% # Table walker wait (enqueue to first request) latency
522system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.85% # Table walker wait (enqueue to first request) latency
523system.cpu0.itb.walker.walkWaitTime::20480-24575 10 0.10% 99.94% # Table walker wait (enqueue to first request) latency
524system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency
525system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
526system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
527system.cpu0.itb.walker.walkWaitTime::total 10357 # Table walker wait (enqueue to first request) latency
528system.cpu0.itb.walker.walkCompletionTime::samples 2692 # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::mean 11506.129272 # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::gmean 10069.776184 # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::stdev 6522.127356 # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::0-16383 2498 92.79% 92.79% # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::16384-32767 161 5.98% 98.77% # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::32768-49151 32 1.19% 99.96% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::total 2692 # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walksPending::samples 20202424328 # Table walker pending requests distribution
538system.cpu0.itb.walker.walksPending::mean 0.966577 # Table walker pending requests distribution
539system.cpu0.itb.walker.walksPending::stdev 0.179934 # Table walker pending requests distribution
540system.cpu0.itb.walker.walksPending::0 675884500 3.35% 3.35% # Table walker pending requests distribution
541system.cpu0.itb.walker.walksPending::1 19525926328 96.65% 100.00% # Table walker pending requests distribution
542system.cpu0.itb.walker.walksPending::2 564000 0.00% 100.00% # Table walker pending requests distribution
543system.cpu0.itb.walker.walksPending::3 49500 0.00% 100.00% # Table walker pending requests distribution
544system.cpu0.itb.walker.walksPending::total 20202424328 # Table walker pending requests distribution
545system.cpu0.itb.walker.walkPageSizes::4K 2260 87.63% 87.63% # Table walker page sizes translated
546system.cpu0.itb.walker.walkPageSizes::1M 319 12.37% 100.00% # Table walker page sizes translated
547system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated

552system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst

548system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst

553system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10460 # Table walker requests started/completed, data/inst
554system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10460 # Table walker requests started/completed, data/inst

549system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10470 # Table walker requests started/completed, data/inst
550system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10470 # Table walker requests started/completed, data/inst

555system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst

551system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst

556system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2583 # Table walker requests started/completed, data/inst
557system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2583 # Table walker requests started/completed, data/inst
558system.cpu0.itb.walker.walkRequestOrigin::total 13043 # Table walker requests started/completed, data/inst
559system.cpu0.itb.inst_hits 37759439 # ITB inst hits
560system.cpu0.itb.inst_misses 10460 # ITB inst misses

552system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst
553system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst
554system.cpu0.itb.walker.walkRequestOrigin::total 13049 # Table walker requests started/completed, data/inst
555system.cpu0.itb.inst_hits 35710587 # ITB inst hits
556system.cpu0.itb.inst_misses 10470 # ITB inst misses

561system.cpu0.itb.read_hits 0 # DTB read hits
562system.cpu0.itb.read_misses 0 # DTB read misses
563system.cpu0.itb.write_hits 0 # DTB write hits
564system.cpu0.itb.write_misses 0 # DTB write misses
565system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
566system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
567system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
568system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID

557system.cpu0.itb.read_hits 0 # DTB read hits
558system.cpu0.itb.read_misses 0 # DTB read misses
559system.cpu0.itb.write_hits 0 # DTB write hits
560system.cpu0.itb.write_misses 0 # DTB write misses
561system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
562system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
563system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
564system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID

569system.cpu0.itb.flush_entries 2357 # Number of entries that have been flushed from TLB

565system.cpu0.itb.flush_entries 2356 # Number of entries that have been flushed from TLB

570system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
571system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
572system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions

566system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
567system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
568system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions

573system.cpu0.itb.perms_faults 1912 # Number of TLB faults due to permissions restrictions

569system.cpu0.itb.perms_faults 1940 # Number of TLB faults due to permissions restrictions

574system.cpu0.itb.read_accesses 0 # DTB read accesses
575system.cpu0.itb.write_accesses 0 # DTB write accesses

570system.cpu0.itb.read_accesses 0 # DTB read accesses
571system.cpu0.itb.write_accesses 0 # DTB write accesses

576system.cpu0.itb.inst_accesses 37769899 # ITB inst accesses
577system.cpu0.itb.hits 37759439 # DTB hits
578system.cpu0.itb.misses 10460 # DTB misses
579system.cpu0.itb.accesses 37769899 # DTB accesses
580system.cpu0.numCycles 130135672 # number of cpu cycles simulated

572system.cpu0.itb.inst_accesses 35721057 # ITB inst accesses
573system.cpu0.itb.hits 35710587 # DTB hits
574system.cpu0.itb.misses 10470 # DTB misses
575system.cpu0.itb.accesses 35721057 # DTB accesses
576system.cpu0.numCycles 126659372 # number of cpu cycles simulated

581system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
582system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed

577system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
578system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed

583system.cpu0.fetch.icacheStallCycles 18741348 # Number of cycles fetch is stalled on an Icache miss
584system.cpu0.fetch.Insts 112674064 # Number of instructions fetch has processed
585system.cpu0.fetch.Branches 24021626 # Number of branches that fetch encountered
586system.cpu0.fetch.predictedBranches 14664885 # Number of branches that fetch has predicted taken
587system.cpu0.fetch.Cycles 105564363 # Number of cycles fetch has run and was not squashing or blocked
588system.cpu0.fetch.SquashCycles 2824766 # Number of cycles fetch has spent squashing
589system.cpu0.fetch.TlbCycles 148935 # Number of cycles fetch has spent waiting for tlb
590system.cpu0.fetch.MiscStallCycles 59402 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
591system.cpu0.fetch.PendingTrapStallCycles 359448 # Number of stall cycles due to pending traps
592system.cpu0.fetch.PendingQuiesceStallCycles 427042 # Number of stall cycles due to pending quiesce instructions
593system.cpu0.fetch.IcacheWaitRetryStallCycles 91226 # Number of stall cycles due to full MSHR
594system.cpu0.fetch.CacheLines 37760092 # Number of cache lines fetched
595system.cpu0.fetch.IcacheSquashes 271445 # Number of outstanding Icache misses that were squashed
596system.cpu0.fetch.ItlbSquashes 4846 # Number of outstanding ITLB misses that were squashed
597system.cpu0.fetch.rateDist::samples 126804147 # Number of instructions fetched each cycle (Total)
598system.cpu0.fetch.rateDist::mean 1.071967 # Number of instructions fetched each cycle (Total)
599system.cpu0.fetch.rateDist::stdev 1.260919 # Number of instructions fetched each cycle (Total)

579system.cpu0.fetch.icacheStallCycles 17871987 # Number of cycles fetch is stalled on an Icache miss
580system.cpu0.fetch.Insts 106431260 # Number of instructions fetch has processed
581system.cpu0.fetch.Branches 22632354 # Number of branches that fetch encountered
582system.cpu0.fetch.predictedBranches 13875408 # Number of branches that fetch has predicted taken
583system.cpu0.fetch.Cycles 101673133 # Number of cycles fetch has run and was not squashing or blocked
584system.cpu0.fetch.SquashCycles 2651880 # Number of cycles fetch has spent squashing
585system.cpu0.fetch.TlbCycles 146874 # Number of cycles fetch has spent waiting for tlb
586system.cpu0.fetch.MiscStallCycles 68068 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
587system.cpu0.fetch.PendingTrapStallCycles 354842 # Number of stall cycles due to pending traps
588system.cpu0.fetch.PendingQuiesceStallCycles 428688 # Number of stall cycles due to pending quiesce instructions
589system.cpu0.fetch.IcacheWaitRetryStallCycles 93530 # Number of stall cycles due to full MSHR
590system.cpu0.fetch.CacheLines 35711195 # Number of cache lines fetched
591system.cpu0.fetch.IcacheSquashes 256145 # Number of outstanding Icache misses that were squashed
592system.cpu0.fetch.ItlbSquashes 4738 # Number of outstanding ITLB misses that were squashed
593system.cpu0.fetch.rateDist::samples 121963062 # Number of instructions fetched each cycle (Total)
594system.cpu0.fetch.rateDist::mean 1.052824 # Number of instructions fetched each cycle (Total)
595system.cpu0.fetch.rateDist::stdev 1.258485 # Number of instructions fetched each cycle (Total)

600system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

596system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

601system.cpu0.fetch.rateDist::0 64261882 50.68% 50.68% # Number of instructions fetched each cycle (Total)
602system.cpu0.fetch.rateDist::1 21462384 16.93% 67.60% # Number of instructions fetched each cycle (Total)
603system.cpu0.fetch.rateDist::2 8772204 6.92% 74.52% # Number of instructions fetched each cycle (Total)
604system.cpu0.fetch.rateDist::3 32307677 25.48% 100.00% # Number of instructions fetched each cycle (Total)

597system.cpu0.fetch.rateDist::0 62962688 51.62% 51.62% # Number of instructions fetched each cycle (Total)
598system.cpu0.fetch.rateDist::1 20162814 16.53% 68.16% # Number of instructions fetched each cycle (Total)
599system.cpu0.fetch.rateDist::2 8269817 6.78% 74.94% # Number of instructions fetched each cycle (Total)
600system.cpu0.fetch.rateDist::3 30567743 25.06% 100.00% # Number of instructions fetched each cycle (Total)

605system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
606system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
607system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)

601system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
602system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
603system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)

608system.cpu0.fetch.rateDist::total 126804147 # Number of instructions fetched each cycle (Total)
609system.cpu0.fetch.branchRate 0.184589 # Number of branch fetches per cycle
610system.cpu0.fetch.rate 0.865820 # Number of inst fetches per cycle
611system.cpu0.decode.IdleCycles 19721438 # Number of cycles decode is idle
612system.cpu0.decode.BlockedCycles 59617090 # Number of cycles decode is blocked
613system.cpu0.decode.RunCycles 41434685 # Number of cycles decode is running
614system.cpu0.decode.UnblockCycles 4962697 # Number of cycles decode is unblocking
615system.cpu0.decode.SquashCycles 1068237 # Number of cycles decode is squashing
616system.cpu0.decode.BranchResolved 3055964 # Number of times decode resolved a branch
617system.cpu0.decode.BranchMispred 348356 # Number of times decode detected a branch misprediction
618system.cpu0.decode.DecodedInsts 110795648 # Number of instructions handled by decode
619system.cpu0.decode.SquashedInsts 3978318 # Number of squashed instructions handled by decode
620system.cpu0.rename.SquashCycles 1068237 # Number of cycles rename is squashing
621system.cpu0.rename.IdleCycles 25470078 # Number of cycles rename is idle
622system.cpu0.rename.BlockCycles 12211623 # Number of cycles rename is blocking
623system.cpu0.rename.serializeStallCycles 36823403 # count of cycles rename stalled for serializing inst
624system.cpu0.rename.RunCycles 40512045 # Number of cycles rename is running
625system.cpu0.rename.UnblockCycles 10718761 # Number of cycles rename is unblocking
626system.cpu0.rename.RenamedInsts 105720614 # Number of instructions processed by rename
627system.cpu0.rename.SquashedInsts 1057290 # Number of squashed instructions processed by rename
628system.cpu0.rename.ROBFullEvents 1452767 # Number of times rename has blocked due to ROB full
629system.cpu0.rename.IQFullEvents 161700 # Number of times rename has blocked due to IQ full
630system.cpu0.rename.LQFullEvents 58122 # Number of times rename has blocked due to LQ full
631system.cpu0.rename.SQFullEvents 6514709 # Number of times rename has blocked due to SQ full
632system.cpu0.rename.RenamedOperands 109806374 # Number of destination operands rename has renamed
633system.cpu0.rename.RenameLookups 482725120 # Number of register rename lookups that rename has made
634system.cpu0.rename.int_rename_lookups 121004760 # Number of integer rename lookups
635system.cpu0.rename.fp_rename_lookups 9383 # Number of floating rename lookups
636system.cpu0.rename.CommittedMaps 98259136 # Number of HB maps that are committed
637system.cpu0.rename.UndoneMaps 11547235 # Number of HB maps that are undone due to squashing
638system.cpu0.rename.serializingInsts 1229554 # count of serializing insts renamed
639system.cpu0.rename.tempSerializingInsts 1088238 # count of temporary serializing insts renamed
640system.cpu0.rename.skidInsts 12335468 # count of insts added to the skid buffer
641system.cpu0.memDep0.insertedLoads 18754417 # Number of loads inserted to the mem dependence unit.
642system.cpu0.memDep0.insertedStores 16214275 # Number of stores inserted to the mem dependence unit.
643system.cpu0.memDep0.conflictingLoads 1701393 # Number of conflicting loads.
644system.cpu0.memDep0.conflictingStores 2256069 # Number of conflicting stores.
645system.cpu0.iq.iqInstsAdded 102765106 # Number of instructions added to the IQ (excludes non-spec)
646system.cpu0.iq.iqNonSpecInstsAdded 1695392 # Number of non-speculative instructions added to the IQ
647system.cpu0.iq.iqInstsIssued 100794287 # Number of instructions issued
648system.cpu0.iq.iqSquashedInstsIssued 484302 # Number of squashed instructions issued
649system.cpu0.iq.iqSquashedInstsExamined 9532947 # Number of squashed instructions iterated over during squash; mainly for profiling
650system.cpu0.iq.iqSquashedOperandsExamined 22407435 # Number of squashed operands that are examined and possibly removed from graph
651system.cpu0.iq.iqSquashedNonSpecRemoved 122350 # Number of squashed non-spec instructions that were removed
652system.cpu0.iq.issued_per_cycle::samples 126804147 # Number of insts issued each cycle
653system.cpu0.iq.issued_per_cycle::mean 0.794882 # Number of insts issued each cycle
654system.cpu0.iq.issued_per_cycle::stdev 1.031887 # Number of insts issued each cycle

604system.cpu0.fetch.rateDist::total 121963062 # Number of instructions fetched each cycle (Total)
605system.cpu0.fetch.branchRate 0.178687 # Number of branch fetches per cycle
606system.cpu0.fetch.rate 0.840295 # Number of inst fetches per cycle
607system.cpu0.decode.IdleCycles 18684987 # Number of cycles decode is idle
608system.cpu0.decode.BlockedCycles 58693341 # Number of cycles decode is blocked
609system.cpu0.decode.RunCycles 38833256 # Number of cycles decode is running
610system.cpu0.decode.UnblockCycles 4747637 # Number of cycles decode is unblocking
611system.cpu0.decode.SquashCycles 1003841 # Number of cycles decode is squashing
612system.cpu0.decode.BranchResolved 2912386 # Number of times decode resolved a branch
613system.cpu0.decode.BranchMispred 326313 # Number of times decode detected a branch misprediction
614system.cpu0.decode.DecodedInsts 104496141 # Number of instructions handled by decode
615system.cpu0.decode.SquashedInsts 3704345 # Number of squashed instructions handled by decode
616system.cpu0.rename.SquashCycles 1003841 # Number of cycles rename is squashing
617system.cpu0.rename.IdleCycles 24126481 # Number of cycles rename is idle
618system.cpu0.rename.BlockCycles 12572099 # Number of cycles rename is blocking
619system.cpu0.rename.serializeStallCycles 34554184 # count of cycles rename stalled for serializing inst
620system.cpu0.rename.RunCycles 38013567 # Number of cycles rename is running
621system.cpu0.rename.UnblockCycles 11692890 # Number of cycles rename is unblocking
622system.cpu0.rename.RenamedInsts 99684423 # Number of instructions processed by rename
623system.cpu0.rename.SquashedInsts 977099 # Number of squashed instructions processed by rename
624system.cpu0.rename.ROBFullEvents 1404281 # Number of times rename has blocked due to ROB full
625system.cpu0.rename.IQFullEvents 150386 # Number of times rename has blocked due to IQ full
626system.cpu0.rename.LQFullEvents 54053 # Number of times rename has blocked due to LQ full
627system.cpu0.rename.SQFullEvents 7679999 # Number of times rename has blocked due to SQ full
628system.cpu0.rename.RenamedOperands 103244507 # Number of destination operands rename has renamed
629system.cpu0.rename.RenameLookups 455598825 # Number of register rename lookups that rename has made
630system.cpu0.rename.int_rename_lookups 114217475 # Number of integer rename lookups
631system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups
632system.cpu0.rename.CommittedMaps 92488092 # Number of HB maps that are committed
633system.cpu0.rename.UndoneMaps 10756412 # Number of HB maps that are undone due to squashing
634system.cpu0.rename.serializingInsts 1189033 # count of serializing insts renamed
635system.cpu0.rename.tempSerializingInsts 1051673 # count of temporary serializing insts renamed
636system.cpu0.rename.skidInsts 11830745 # count of insts added to the skid buffer
637system.cpu0.memDep0.insertedLoads 17693579 # Number of loads inserted to the mem dependence unit.
638system.cpu0.memDep0.insertedStores 15395073 # Number of stores inserted to the mem dependence unit.
639system.cpu0.memDep0.conflictingLoads 1633265 # Number of conflicting loads.
640system.cpu0.memDep0.conflictingStores 2155883 # Number of conflicting stores.
641system.cpu0.iq.iqInstsAdded 96874005 # Number of instructions added to the IQ (excludes non-spec)
642system.cpu0.iq.iqNonSpecInstsAdded 1635627 # Number of non-speculative instructions added to the IQ
643system.cpu0.iq.iqInstsIssued 95096979 # Number of instructions issued
644system.cpu0.iq.iqSquashedInstsIssued 454397 # Number of squashed instructions issued
645system.cpu0.iq.iqSquashedInstsExamined 8909178 # Number of squashed instructions iterated over during squash; mainly for profiling
646system.cpu0.iq.iqSquashedOperandsExamined 20852751 # Number of squashed operands that are examined and possibly removed from graph
647system.cpu0.iq.iqSquashedNonSpecRemoved 116081 # Number of squashed non-spec instructions that were removed
648system.cpu0.iq.issued_per_cycle::samples 121963062 # Number of insts issued each cycle
649system.cpu0.iq.issued_per_cycle::mean 0.779720 # Number of insts issued each cycle
650system.cpu0.iq.issued_per_cycle::stdev 1.027198 # Number of insts issued each cycle

655system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

651system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

656system.cpu0.iq.issued_per_cycle::0 70515231 55.61% 55.61% # Number of insts issued each cycle
657system.cpu0.iq.issued_per_cycle::1 23338464 18.41% 74.01% # Number of insts issued each cycle
658system.cpu0.iq.issued_per_cycle::2 22507800 17.75% 91.76% # Number of insts issued each cycle
659system.cpu0.iq.issued_per_cycle::3 9330414 7.36% 99.12% # Number of insts issued each cycle
660system.cpu0.iq.issued_per_cycle::4 1112209 0.88% 100.00% # Number of insts issued each cycle

652system.cpu0.iq.issued_per_cycle::0 68765776 56.38% 56.38% # Number of insts issued each cycle
653system.cpu0.iq.issued_per_cycle::1 22213388 18.21% 74.60% # Number of insts issued each cycle
654system.cpu0.iq.issued_per_cycle::2 21122370 17.32% 91.91% # Number of insts issued each cycle
655system.cpu0.iq.issued_per_cycle::3 8807290 7.22% 99.14% # Number of insts issued each cycle
656system.cpu0.iq.issued_per_cycle::4 1054209 0.86% 100.00% # Number of insts issued each cycle

661system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle
662system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
663system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
664system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
665system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
666system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
667system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle

657system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle
658system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
659system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
660system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
661system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
662system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
663system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle

668system.cpu0.iq.issued_per_cycle::total 126804147 # Number of insts issued each cycle

664system.cpu0.iq.issued_per_cycle::total 121963062 # Number of insts issued each cycle

669system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

665system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

670system.cpu0.iq.fu_full::IntAlu 9354884 40.60% 40.60% # attempts to use FU when none available
671system.cpu0.iq.fu_full::IntMult 74 0.00% 40.60% # attempts to use FU when none available
672system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.60% # attempts to use FU when none available
673system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.60% # attempts to use FU when none available
674system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.60% # attempts to use FU when none available
675system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.60% # attempts to use FU when none available
676system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.60% # attempts to use FU when none available
677system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.60% # attempts to use FU when none available
678system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.60% # attempts to use FU when none available
679system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.60% # attempts to use FU when none available
680system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.60% # attempts to use FU when none available
681system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.60% # attempts to use FU when none available
682system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.60% # attempts to use FU when none available
683system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.60% # attempts to use FU when none available
684system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.60% # attempts to use FU when none available
685system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.60% # attempts to use FU when none available
686system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.60% # attempts to use FU when none available
687system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.60% # attempts to use FU when none available
688system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.60% # attempts to use FU when none available
689system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.60% # attempts to use FU when none available
690system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.60% # attempts to use FU when none available
691system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.60% # attempts to use FU when none available
692system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.60% # attempts to use FU when none available
693system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.60% # attempts to use FU when none available
694system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.60% # attempts to use FU when none available
695system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.60% # attempts to use FU when none available
696system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.60% # attempts to use FU when none available
697system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.60% # attempts to use FU when none available
698system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.60% # attempts to use FU when none available
699system.cpu0.iq.fu_full::MemRead 5601126 24.31% 64.90% # attempts to use FU when none available
700system.cpu0.iq.fu_full::MemWrite 8088042 35.10% 100.00% # attempts to use FU when none available

666system.cpu0.iq.fu_full::IntAlu 8813581 40.35% 40.35% # attempts to use FU when none available
667system.cpu0.iq.fu_full::IntMult 132 0.00% 40.35% # attempts to use FU when none available
668system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.35% # attempts to use FU when none available
669system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.35% # attempts to use FU when none available
670system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.35% # attempts to use FU when none available
671system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.35% # attempts to use FU when none available
672system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.35% # attempts to use FU when none available
673system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.35% # attempts to use FU when none available
674system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.35% # attempts to use FU when none available
675system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.35% # attempts to use FU when none available
676system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.35% # attempts to use FU when none available
677system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.35% # attempts to use FU when none available
678system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.35% # attempts to use FU when none available
679system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.35% # attempts to use FU when none available
680system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.35% # attempts to use FU when none available
681system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.35% # attempts to use FU when none available
682system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.35% # attempts to use FU when none available
683system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.35% # attempts to use FU when none available
684system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.35% # attempts to use FU when none available
685system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.35% # attempts to use FU when none available
686system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.35% # attempts to use FU when none available
687system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.35% # attempts to use FU when none available
688system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.35% # attempts to use FU when none available
689system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.35% # attempts to use FU when none available
690system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.35% # attempts to use FU when none available
691system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.35% # attempts to use FU when none available
692system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.35% # attempts to use FU when none available
693system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.35% # attempts to use FU when none available
694system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.35% # attempts to use FU when none available
695system.cpu0.iq.fu_full::MemRead 5351630 24.50% 64.85% # attempts to use FU when none available
696system.cpu0.iq.fu_full::MemWrite 7678552 35.15% 100.00% # attempts to use FU when none available

701system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
702system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

697system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
698system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

703system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
704system.cpu0.iq.FU_type_0::IntAlu 66470143 65.95% 65.95% # Type of FU issued
705system.cpu0.iq.FU_type_0::IntMult 93430 0.09% 66.04% # Type of FU issued
706system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued
707system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.04% # Type of FU issued
708system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued
709system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued
710system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued
711system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued
712system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.04% # Type of FU issued
713system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.04% # Type of FU issued
714system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.04% # Type of FU issued
715system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.04% # Type of FU issued
716system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.04% # Type of FU issued
717system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.04% # Type of FU issued
718system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.04% # Type of FU issued
719system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.04% # Type of FU issued
720system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.04% # Type of FU issued
721system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.04% # Type of FU issued
722system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.04% # Type of FU issued
723system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.04% # Type of FU issued
724system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.04% # Type of FU issued
725system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.04% # Type of FU issued
726system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.04% # Type of FU issued
727system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.04% # Type of FU issued
728system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.04% # Type of FU issued
729system.cpu0.iq.FU_type_0::SimdFloatMisc 8105 0.01% 66.05% # Type of FU issued
730system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued
731system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued
732system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued
733system.cpu0.iq.FU_type_0::MemRead 18478690 18.33% 84.38% # Type of FU issued
734system.cpu0.iq.FU_type_0::MemWrite 15741645 15.62% 100.00% # Type of FU issued

699system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued
700system.cpu0.iq.FU_type_0::IntAlu 62602265 65.83% 65.83% # Type of FU issued
701system.cpu0.iq.FU_type_0::IntMult 87841 0.09% 65.92% # Type of FU issued
702system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued
703system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 65.92% # Type of FU issued
704system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.92% # Type of FU issued
705system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.92% # Type of FU issued
706system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.92% # Type of FU issued
707system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.92% # Type of FU issued
708system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued
709system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued
710system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued
711system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued
712system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued
713system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued
714system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued
715system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued
716system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued
717system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued
718system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued
719system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued
720system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued
721system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued
722system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued
723system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued
724system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued
725system.cpu0.iq.FU_type_0::SimdFloatMisc 7143 0.01% 65.93% # Type of FU issued
726system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.93% # Type of FU issued
727system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.93% # Type of FU issued
728system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.93% # Type of FU issued
729system.cpu0.iq.FU_type_0::MemRead 17444547 18.34% 84.28% # Type of FU issued
730system.cpu0.iq.FU_type_0::MemWrite 14952910 15.72% 100.00% # Type of FU issued

735system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
736system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

731system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
732system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

737system.cpu0.iq.FU_type_0::total 100794287 # Type of FU issued
738system.cpu0.iq.rate 0.774532 # Inst issue rate
739system.cpu0.iq.fu_busy_cnt 23044126 # FU busy when requested
740system.cpu0.iq.fu_busy_rate 0.228625 # FU busy rate (busy events/executed inst)
741system.cpu0.iq.int_inst_queue_reads 351888789 # Number of integer instruction queue reads
742system.cpu0.iq.int_inst_queue_writes 114001116 # Number of integer instruction queue writes
743system.cpu0.iq.int_inst_queue_wakeup_accesses 98678663 # Number of integer instruction queue wakeup accesses
744system.cpu0.iq.fp_inst_queue_reads 32360 # Number of floating instruction queue reads
745system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes
746system.cpu0.iq.fp_inst_queue_wakeup_accesses 9725 # Number of floating instruction queue wakeup accesses
747system.cpu0.iq.int_alu_accesses 123815106 # Number of integer alu accesses
748system.cpu0.iq.fp_alu_accesses 21034 # Number of floating point alu accesses
749system.cpu0.iew.lsq.thread0.forwLoads 363531 # Number of loads that had data forwarded from stores

733system.cpu0.iq.FU_type_0::total 95096979 # Type of FU issued
734system.cpu0.iq.rate 0.750809 # Inst issue rate
735system.cpu0.iq.fu_busy_cnt 21843895 # FU busy when requested
736system.cpu0.iq.fu_busy_rate 0.229701 # FU busy rate (busy events/executed inst)
737system.cpu0.iq.int_inst_queue_reads 334422549 # Number of integer instruction queue reads
738system.cpu0.iq.int_inst_queue_writes 107425966 # Number of integer instruction queue writes
739system.cpu0.iq.int_inst_queue_wakeup_accesses 93117016 # Number of integer instruction queue wakeup accesses
740system.cpu0.iq.fp_inst_queue_reads 32763 # Number of floating instruction queue reads
741system.cpu0.iq.fp_inst_queue_writes 11378 # Number of floating instruction queue writes
742system.cpu0.iq.fp_inst_queue_wakeup_accesses 9790 # Number of floating instruction queue wakeup accesses
743system.cpu0.iq.int_alu_accesses 116917216 # Number of integer alu accesses
744system.cpu0.iq.fp_alu_accesses 21386 # Number of floating point alu accesses
745system.cpu0.iew.lsq.thread0.forwLoads 346137 # Number of loads that had data forwarded from stores

750system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

746system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

751system.cpu0.iew.lsq.thread0.squashedLoads 1999131 # Number of loads squashed
752system.cpu0.iew.lsq.thread0.ignoredResponses 2544 # Number of memory responses ignored because the instruction is squashed
753system.cpu0.iew.lsq.thread0.memOrderViolation 19035 # Number of memory ordering violations
754system.cpu0.iew.lsq.thread0.squashedStores 1014690 # Number of stores squashed

747system.cpu0.iew.lsq.thread0.squashedLoads 1858057 # Number of loads squashed
748system.cpu0.iew.lsq.thread0.ignoredResponses 2517 # Number of memory responses ignored because the instruction is squashed
749system.cpu0.iew.lsq.thread0.memOrderViolation 18608 # Number of memory ordering violations
750system.cpu0.iew.lsq.thread0.squashedStores 952368 # Number of stores squashed

755system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
756system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

751system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
752system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

757system.cpu0.iew.lsq.thread0.rescheduledLoads 107294 # Number of loads that were rescheduled
758system.cpu0.iew.lsq.thread0.cacheBlocked 362990 # Number of times an access to memory failed due to the cache being blocked

753system.cpu0.iew.lsq.thread0.rescheduledLoads 100941 # Number of loads that were rescheduled
754system.cpu0.iew.lsq.thread0.cacheBlocked 343903 # Number of times an access to memory failed due to the cache being blocked

759system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle

755system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle

760system.cpu0.iew.iewSquashCycles 1068237 # Number of cycles IEW is squashing
761system.cpu0.iew.iewBlockCycles 1634305 # Number of cycles IEW is blocking
762system.cpu0.iew.iewUnblockCycles 175316 # Number of cycles IEW is unblocking
763system.cpu0.iew.iewDispatchedInsts 104635112 # Number of instructions dispatched to IQ

756system.cpu0.iew.iewSquashCycles 1003841 # Number of cycles IEW is squashing
757system.cpu0.iew.iewBlockCycles 1765434 # Number of cycles IEW is blocking
758system.cpu0.iew.iewUnblockCycles 210085 # Number of cycles IEW is unblocking
759system.cpu0.iew.iewDispatchedInsts 98680740 # Number of instructions dispatched to IQ

764system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch

760system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch

765system.cpu0.iew.iewDispLoadInsts 18754417 # Number of dispatched load instructions
766system.cpu0.iew.iewDispStoreInsts 16214275 # Number of dispatched store instructions
767system.cpu0.iew.iewDispNonSpecInsts 876681 # Number of dispatched non-speculative instructions
768system.cpu0.iew.iewIQFullEvents 26796 # Number of times the IQ has become full, causing a stall
769system.cpu0.iew.iewLSQFullEvents 125236 # Number of times the LSQ has become full, causing a stall
770system.cpu0.iew.memOrderViolationEvents 19035 # Number of memory order violations
771system.cpu0.iew.predictedTakenIncorrect 291768 # Number of branches that were predicted taken incorrectly
772system.cpu0.iew.predictedNotTakenIncorrect 399939 # Number of branches that were predicted not taken incorrectly
773system.cpu0.iew.branchMispredicts 691707 # Number of branch mispredicts detected at execute
774system.cpu0.iew.iewExecutedInsts 99697701 # Number of executed instructions
775system.cpu0.iew.iewExecLoadInsts 18022679 # Number of load instructions executed
776system.cpu0.iew.iewExecSquashedInsts 1031168 # Number of squashed instructions skipped in execute

761system.cpu0.iew.iewDispLoadInsts 17693579 # Number of dispatched load instructions
762system.cpu0.iew.iewDispStoreInsts 15395073 # Number of dispatched store instructions
763system.cpu0.iew.iewDispNonSpecInsts 848677 # Number of dispatched non-speculative instructions
764system.cpu0.iew.iewIQFullEvents 24988 # Number of times the IQ has become full, causing a stall
765system.cpu0.iew.iewLSQFullEvents 163669 # Number of times the LSQ has become full, causing a stall
766system.cpu0.iew.memOrderViolationEvents 18608 # Number of memory order violations
767system.cpu0.iew.predictedTakenIncorrect 265561 # Number of branches that were predicted taken incorrectly
768system.cpu0.iew.predictedNotTakenIncorrect 373947 # Number of branches that were predicted not taken incorrectly
769system.cpu0.iew.branchMispredicts 639508 # Number of branch mispredicts detected at execute
770system.cpu0.iew.iewExecutedInsts 94079743 # Number of executed instructions
771system.cpu0.iew.iewExecLoadInsts 17020662 # Number of load instructions executed
772system.cpu0.iew.iewExecSquashedInsts 955277 # Number of squashed instructions skipped in execute

777system.cpu0.iew.exec_swp 0 # number of swp insts executed

773system.cpu0.iew.exec_swp 0 # number of swp insts executed

778system.cpu0.iew.exec_nop 174614 # number of nop insts executed
779system.cpu0.iew.exec_refs 33573838 # number of memory reference insts executed
780system.cpu0.iew.exec_branches 16859604 # Number of branches executed
781system.cpu0.iew.exec_stores 15551159 # Number of stores executed
782system.cpu0.iew.exec_rate 0.766106 # Inst execution rate
783system.cpu0.iew.wb_sent 99140543 # cumulative count of insts sent to commit
784system.cpu0.iew.wb_count 98688388 # cumulative count of insts written-back
785system.cpu0.iew.wb_producers 51348142 # num instructions producing a value
786system.cpu0.iew.wb_consumers 84871692 # num instructions consuming a value

774system.cpu0.iew.exec_nop 171108 # number of nop insts executed
775system.cpu0.iew.exec_refs 31795600 # number of memory reference insts executed
776system.cpu0.iew.exec_branches 15818182 # Number of branches executed
777system.cpu0.iew.exec_stores 14774938 # Number of stores executed
778system.cpu0.iew.exec_rate 0.742778 # Inst execution rate
779system.cpu0.iew.wb_sent 93557624 # cumulative count of insts sent to commit
780system.cpu0.iew.wb_count 93126806 # cumulative count of insts written-back
781system.cpu0.iew.wb_producers 48392376 # num instructions producing a value
782system.cpu0.iew.wb_consumers 80015738 # num instructions consuming a value

787system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

783system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

788system.cpu0.iew.wb_rate 0.758350 # insts written-back per cycle
789system.cpu0.iew.wb_fanout 0.605009 # average fanout of values written-back

784system.cpu0.iew.wb_rate 0.735254 # insts written-back per cycle
785system.cpu0.iew.wb_fanout 0.604786 # average fanout of values written-back

790system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

786system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

791system.cpu0.commit.commitSquashedInsts 8492759 # The number of squashed insts skipped by commit
792system.cpu0.commit.commitNonSpecStalls 1573042 # The number of times commit has been forced to stall to communicate backwards
793system.cpu0.commit.branchMispredicts 633433 # The number of times a branch was mispredicted
794system.cpu0.commit.committed_per_cycle::samples 125053157 # Number of insts commited each cycle
795system.cpu0.commit.committed_per_cycle::mean 0.760074 # Number of insts commited each cycle
796system.cpu0.commit.committed_per_cycle::stdev 1.473514 # Number of insts commited each cycle

787system.cpu0.commit.commitSquashedInsts 7942186 # The number of squashed insts skipped by commit
788system.cpu0.commit.commitNonSpecStalls 1519546 # The number of times commit has been forced to stall to communicate backwards
789system.cpu0.commit.branchMispredicts 586085 # The number of times a branch was mispredicted
790system.cpu0.commit.committed_per_cycle::samples 120319586 # Number of insts commited each cycle
791system.cpu0.commit.committed_per_cycle::mean 0.745699 # Number of insts commited each cycle
792system.cpu0.commit.committed_per_cycle::stdev 1.465434 # Number of insts commited each cycle

797system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

793system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

798system.cpu0.commit.committed_per_cycle::0 80626724 64.47% 64.47% # Number of insts commited each cycle
799system.cpu0.commit.committed_per_cycle::1 24772258 19.81% 84.28% # Number of insts commited each cycle
800system.cpu0.commit.committed_per_cycle::2 8266840 6.61% 90.89% # Number of insts commited each cycle
801system.cpu0.commit.committed_per_cycle::3 3238221 2.59% 93.48% # Number of insts commited each cycle
802system.cpu0.commit.committed_per_cycle::4 3432782 2.75% 96.23% # Number of insts commited each cycle
803system.cpu0.commit.committed_per_cycle::5 1539199 1.23% 97.46% # Number of insts commited each cycle
804system.cpu0.commit.committed_per_cycle::6 1134355 0.91% 98.37% # Number of insts commited each cycle
805system.cpu0.commit.committed_per_cycle::7 546479 0.44% 98.80% # Number of insts commited each cycle
806system.cpu0.commit.committed_per_cycle::8 1496299 1.20% 100.00% # Number of insts commited each cycle

794system.cpu0.commit.committed_per_cycle::0 78400270 65.16% 65.16% # Number of insts commited each cycle
795system.cpu0.commit.committed_per_cycle::1 23370127 19.42% 84.58% # Number of insts commited each cycle
796system.cpu0.commit.committed_per_cycle::2 7855137 6.53% 91.11% # Number of insts commited each cycle
797system.cpu0.commit.committed_per_cycle::3 3041175 2.53% 93.64% # Number of insts commited each cycle
798system.cpu0.commit.committed_per_cycle::4 3186617 2.65% 96.29% # Number of insts commited each cycle
799system.cpu0.commit.committed_per_cycle::5 1413825 1.18% 97.46% # Number of insts commited each cycle
800system.cpu0.commit.committed_per_cycle::6 1097896 0.91% 98.38% # Number of insts commited each cycle
801system.cpu0.commit.committed_per_cycle::7 521063 0.43% 98.81% # Number of insts commited each cycle
802system.cpu0.commit.committed_per_cycle::8 1433476 1.19% 100.00% # Number of insts commited each cycle

807system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
808system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
809system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

803system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
804system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
805system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

810system.cpu0.commit.committed_per_cycle::total 125053157 # Number of insts commited each cycle
811system.cpu0.commit.committedInsts 78998098 # Number of instructions committed
812system.cpu0.commit.committedOps 95049599 # Number of ops (including micro ops) committed

806system.cpu0.commit.committed_per_cycle::total 120319586 # Number of insts commited each cycle
807system.cpu0.commit.committedInsts 74552173 # Number of instructions committed
808system.cpu0.commit.committedOps 89722144 # Number of ops (including micro ops) committed

813system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed

809system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed

814system.cpu0.commit.refs 31954871 # Number of memory references committed
815system.cpu0.commit.loads 16755286 # Number of loads committed
816system.cpu0.commit.membars 647733 # Number of memory barriers committed
817system.cpu0.commit.branches 16226575 # Number of branches committed
818system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
819system.cpu0.commit.int_insts 81983360 # Number of committed integer instructions.
820system.cpu0.commit.function_calls 1932291 # Number of function calls committed.

810system.cpu0.commit.refs 30278227 # Number of memory references committed
811system.cpu0.commit.loads 15835522 # Number of loads committed
812system.cpu0.commit.membars 627502 # Number of memory barriers committed
813system.cpu0.commit.branches 15222627 # Number of branches committed
814system.cpu0.commit.fp_insts 9772 # Number of committed floating point instructions.
815system.cpu0.commit.int_insts 77510355 # Number of committed integer instructions.
816system.cpu0.commit.function_calls 1849810 # Number of function calls committed.

821system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction

817system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction

822system.cpu0.commit.op_class_0::IntAlu 62995577 66.28% 66.28% # Class of committed instruction
823system.cpu0.commit.op_class_0::IntMult 91046 0.10% 66.37% # Class of committed instruction
824system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.37% # Class of committed instruction
825system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.37% # Class of committed instruction
826system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.37% # Class of committed instruction
827system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.37% # Class of committed instruction
828system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.37% # Class of committed instruction
829system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.37% # Class of committed instruction
830system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.37% # Class of committed instruction
831system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.37% # Class of committed instruction
832system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.37% # Class of committed instruction
833system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.37% # Class of committed instruction
834system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.37% # Class of committed instruction
835system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.37% # Class of committed instruction
836system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.37% # Class of committed instruction
837system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.37% # Class of committed instruction
838system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.37% # Class of committed instruction
839system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.37% # Class of committed instruction
840system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.37% # Class of committed instruction
841system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.37% # Class of committed instruction
842system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.37% # Class of committed instruction
843system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.37% # Class of committed instruction
844system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.37% # Class of committed instruction
845system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.37% # Class of committed instruction
846system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.37% # Class of committed instruction
847system.cpu0.commit.op_class_0::SimdFloatMisc 8105 0.01% 66.38% # Class of committed instruction
848system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction
849system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction
850system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction
851system.cpu0.commit.op_class_0::MemRead 16755286 17.63% 84.01% # Class of committed instruction
852system.cpu0.commit.op_class_0::MemWrite 15199585 15.99% 100.00% # Class of committed instruction

818system.cpu0.commit.op_class_0::IntAlu 59351234 66.15% 66.15% # Class of committed instruction
819system.cpu0.commit.op_class_0::IntMult 85540 0.10% 66.25% # Class of committed instruction
820system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction
821system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction
822system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction
823system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction
824system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction
825system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction
826system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction
827system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction
828system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction
829system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction
830system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction
831system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction
832system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction
833system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction
834system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction
835system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction
836system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction
837system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction
838system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction
839system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction
840system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction
841system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction
842system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction
843system.cpu0.commit.op_class_0::SimdFloatMisc 7143 0.01% 66.25% # Class of committed instruction
844system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction
845system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction
846system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction
847system.cpu0.commit.op_class_0::MemRead 15835522 17.65% 83.90% # Class of committed instruction
848system.cpu0.commit.op_class_0::MemWrite 14442705 16.10% 100.00% # Class of committed instruction

853system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
854system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

849system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
850system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

855system.cpu0.commit.op_class_0::total 95049599 # Class of committed instruction
856system.cpu0.commit.bw_lim_events 1496299 # number cycles where commit BW limit reached
857system.cpu0.rob.rob_reads 222908078 # The number of ROB reads
858system.cpu0.rob.rob_writes 208834787 # The number of ROB writes
859system.cpu0.timesIdled 129596 # Number of times that the entire CPU went into an idle state and unscheduled itself
860system.cpu0.idleCycles 3331525 # Total number of cycles that the CPU has spent unscheduled due to idling
861system.cpu0.quiesceCycles 5520676264 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
862system.cpu0.committedInsts 78876046 # Number of Instructions Simulated
863system.cpu0.committedOps 94927547 # Number of Ops (including micro ops) Simulated
864system.cpu0.cpi 1.649876 # CPI: Cycles Per Instruction
865system.cpu0.cpi_total 1.649876 # CPI: Total CPI of All Threads
866system.cpu0.ipc 0.606106 # IPC: Instructions Per Cycle
867system.cpu0.ipc_total 0.606106 # IPC: Total IPC of All Threads
868system.cpu0.int_regfile_reads 110754452 # number of integer regfile reads
869system.cpu0.int_regfile_writes 59798186 # number of integer regfile writes
870system.cpu0.fp_regfile_reads 8167 # number of floating regfile reads

851system.cpu0.commit.op_class_0::total 89722144 # Class of committed instruction
852system.cpu0.commit.bw_lim_events 1433476 # number cycles where commit BW limit reached
853system.cpu0.rob.rob_reads 212523033 # The number of ROB reads
854system.cpu0.rob.rob_writes 196970686 # The number of ROB writes
855system.cpu0.timesIdled 126988 # Number of times that the entire CPU went into an idle state and unscheduled itself
856system.cpu0.idleCycles 4696310 # Total number of cycles that the CPU has spent unscheduled due to idling
857system.cpu0.quiesceCycles 5127862528 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
858system.cpu0.committedInsts 74430479 # Number of Instructions Simulated
859system.cpu0.committedOps 89600450 # Number of Ops (including micro ops) Simulated
860system.cpu0.cpi 1.701714 # CPI: Cycles Per Instruction
861system.cpu0.cpi_total 1.701714 # CPI: Total CPI of All Threads
862system.cpu0.ipc 0.587643 # IPC: Instructions Per Cycle
863system.cpu0.ipc_total 0.587643 # IPC: Total IPC of All Threads
864system.cpu0.int_regfile_reads 104622739 # number of integer regfile reads
865system.cpu0.int_regfile_writes 56501496 # number of integer regfile writes
866system.cpu0.fp_regfile_reads 8247 # number of floating regfile reads

871system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes

867system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes

872system.cpu0.cc_regfile_reads 351214590 # number of cc regfile reads
873system.cpu0.cc_regfile_writes 41113323 # number of cc regfile writes
874system.cpu0.misc_regfile_reads 177297499 # number of misc regfile reads
875system.cpu0.misc_regfile_writes 1225193 # number of misc regfile writes
876system.cpu0.dcache.tags.replacements 713718 # number of replacements
877system.cpu0.dcache.tags.tagsinuse 494.250179 # Cycle average of tags in use
878system.cpu0.dcache.tags.total_refs 28854841 # Total number of references to valid blocks.
879system.cpu0.dcache.tags.sampled_refs 714230 # Sample count of references to valid blocks.
880system.cpu0.dcache.tags.avg_refs 40.399929 # Average number of references to valid blocks.
881system.cpu0.dcache.tags.warmup_cycle 274766500 # Cycle when the warmup percentage was hit.
882system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.250179 # Average occupied blocks per requestor
883system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965332 # Average percentage of cache occupancy
884system.cpu0.dcache.tags.occ_percent::total 0.965332 # Average percentage of cache occupancy

868system.cpu0.cc_regfile_reads 331476991 # number of cc regfile reads
869system.cpu0.cc_regfile_writes 38443016 # number of cc regfile writes
870system.cpu0.misc_regfile_reads 169856708 # number of misc regfile reads
871system.cpu0.misc_regfile_writes 1190913 # number of misc regfile writes
872system.cpu0.dcache.tags.replacements 672498 # number of replacements
873system.cpu0.dcache.tags.tagsinuse 485.161129 # Cycle average of tags in use
874system.cpu0.dcache.tags.total_refs 27296512 # Total number of references to valid blocks.
875system.cpu0.dcache.tags.sampled_refs 673010 # Sample count of references to valid blocks.
876system.cpu0.dcache.tags.avg_refs 40.558851 # Average number of references to valid blocks.
877system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit.
878system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.161129 # Average occupied blocks per requestor
879system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947580 # Average percentage of cache occupancy
880system.cpu0.dcache.tags.occ_percent::total 0.947580 # Average percentage of cache occupancy

885system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

881system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

886system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
887system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
888system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id

882system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id
883system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
884system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id

889system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

885system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

890system.cpu0.dcache.tags.tag_accesses 63563549 # Number of tag accesses
891system.cpu0.dcache.tags.data_accesses 63563549 # Number of data accesses
892system.cpu0.dcache.ReadReq_hits::cpu0.data 15604955 # number of ReadReq hits
893system.cpu0.dcache.ReadReq_hits::total 15604955 # number of ReadReq hits
894system.cpu0.dcache.WriteReq_hits::cpu0.data 12027073 # number of WriteReq hits
895system.cpu0.dcache.WriteReq_hits::total 12027073 # number of WriteReq hits
896system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310316 # number of SoftPFReq hits
897system.cpu0.dcache.SoftPFReq_hits::total 310316 # number of SoftPFReq hits
898system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363058 # number of LoadLockedReq hits
899system.cpu0.dcache.LoadLockedReq_hits::total 363058 # number of LoadLockedReq hits
900system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361354 # number of StoreCondReq hits
901system.cpu0.dcache.StoreCondReq_hits::total 361354 # number of StoreCondReq hits
902system.cpu0.dcache.demand_hits::cpu0.data 27632028 # number of demand (read+write) hits
903system.cpu0.dcache.demand_hits::total 27632028 # number of demand (read+write) hits
904system.cpu0.dcache.overall_hits::cpu0.data 27942344 # number of overall hits
905system.cpu0.dcache.overall_hits::total 27942344 # number of overall hits
906system.cpu0.dcache.ReadReq_misses::cpu0.data 644494 # number of ReadReq misses
907system.cpu0.dcache.ReadReq_misses::total 644494 # number of ReadReq misses
908system.cpu0.dcache.WriteReq_misses::cpu0.data 1893203 # number of WriteReq misses
909system.cpu0.dcache.WriteReq_misses::total 1893203 # number of WriteReq misses
910system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147485 # number of SoftPFReq misses
911system.cpu0.dcache.SoftPFReq_misses::total 147485 # number of SoftPFReq misses
912system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25333 # number of LoadLockedReq misses
913system.cpu0.dcache.LoadLockedReq_misses::total 25333 # number of LoadLockedReq misses
914system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20104 # number of StoreCondReq misses
915system.cpu0.dcache.StoreCondReq_misses::total 20104 # number of StoreCondReq misses
916system.cpu0.dcache.demand_misses::cpu0.data 2537697 # number of demand (read+write) misses
917system.cpu0.dcache.demand_misses::total 2537697 # number of demand (read+write) misses
918system.cpu0.dcache.overall_misses::cpu0.data 2685182 # number of overall misses
919system.cpu0.dcache.overall_misses::total 2685182 # number of overall misses
920system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8536879000 # number of ReadReq miss cycles
921system.cpu0.dcache.ReadReq_miss_latency::total 8536879000 # number of ReadReq miss cycles
922system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27482436369 # number of WriteReq miss cycles
923system.cpu0.dcache.WriteReq_miss_latency::total 27482436369 # number of WriteReq miss cycles
924system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389618000 # number of LoadLockedReq miss cycles
925system.cpu0.dcache.LoadLockedReq_miss_latency::total 389618000 # number of LoadLockedReq miss cycles
926system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 450883500 # number of StoreCondReq miss cycles
927system.cpu0.dcache.StoreCondReq_miss_latency::total 450883500 # number of StoreCondReq miss cycles
928system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454000 # number of StoreCondFailReq miss cycles
929system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454000 # number of StoreCondFailReq miss cycles
930system.cpu0.dcache.demand_miss_latency::cpu0.data 36019315369 # number of demand (read+write) miss cycles
931system.cpu0.dcache.demand_miss_latency::total 36019315369 # number of demand (read+write) miss cycles
932system.cpu0.dcache.overall_miss_latency::cpu0.data 36019315369 # number of overall miss cycles
933system.cpu0.dcache.overall_miss_latency::total 36019315369 # number of overall miss cycles
934system.cpu0.dcache.ReadReq_accesses::cpu0.data 16249449 # number of ReadReq accesses(hits+misses)
935system.cpu0.dcache.ReadReq_accesses::total 16249449 # number of ReadReq accesses(hits+misses)
936system.cpu0.dcache.WriteReq_accesses::cpu0.data 13920276 # number of WriteReq accesses(hits+misses)
937system.cpu0.dcache.WriteReq_accesses::total 13920276 # number of WriteReq accesses(hits+misses)
938system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457801 # number of SoftPFReq accesses(hits+misses)
939system.cpu0.dcache.SoftPFReq_accesses::total 457801 # number of SoftPFReq accesses(hits+misses)
940system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388391 # number of LoadLockedReq accesses(hits+misses)
941system.cpu0.dcache.LoadLockedReq_accesses::total 388391 # number of LoadLockedReq accesses(hits+misses)
942system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381458 # number of StoreCondReq accesses(hits+misses)
943system.cpu0.dcache.StoreCondReq_accesses::total 381458 # number of StoreCondReq accesses(hits+misses)
944system.cpu0.dcache.demand_accesses::cpu0.data 30169725 # number of demand (read+write) accesses
945system.cpu0.dcache.demand_accesses::total 30169725 # number of demand (read+write) accesses
946system.cpu0.dcache.overall_accesses::cpu0.data 30627526 # number of overall (read+write) accesses
947system.cpu0.dcache.overall_accesses::total 30627526 # number of overall (read+write) accesses
948system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039663 # miss rate for ReadReq accesses
949system.cpu0.dcache.ReadReq_miss_rate::total 0.039663 # miss rate for ReadReq accesses
950system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136003 # miss rate for WriteReq accesses
951system.cpu0.dcache.WriteReq_miss_rate::total 0.136003 # miss rate for WriteReq accesses
952system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.322160 # miss rate for SoftPFReq accesses
953system.cpu0.dcache.SoftPFReq_miss_rate::total 0.322160 # miss rate for SoftPFReq accesses
954system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065226 # miss rate for LoadLockedReq accesses
955system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065226 # miss rate for LoadLockedReq accesses
956system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052703 # miss rate for StoreCondReq accesses
957system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052703 # miss rate for StoreCondReq accesses
958system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084114 # miss rate for demand accesses
959system.cpu0.dcache.demand_miss_rate::total 0.084114 # miss rate for demand accesses
960system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087672 # miss rate for overall accesses
961system.cpu0.dcache.overall_miss_rate::total 0.087672 # miss rate for overall accesses
962system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13245.862646 # average ReadReq miss latency
963system.cpu0.dcache.ReadReq_avg_miss_latency::total 13245.862646 # average ReadReq miss latency
964system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14516.370600 # average WriteReq miss latency
965system.cpu0.dcache.WriteReq_avg_miss_latency::total 14516.370600 # average WriteReq miss latency
966system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15379.860261 # average LoadLockedReq miss latency
967system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15379.860261 # average LoadLockedReq miss latency
968system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22427.551731 # average StoreCondReq miss latency
969system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22427.551731 # average StoreCondReq miss latency

886system.cpu0.dcache.tags.tag_accesses 60152551 # Number of tag accesses
887system.cpu0.dcache.tags.data_accesses 60152551 # Number of data accesses
888system.cpu0.dcache.ReadReq_hits::cpu0.data 14711290 # number of ReadReq hits
889system.cpu0.dcache.ReadReq_hits::total 14711290 # number of ReadReq hits
890system.cpu0.dcache.WriteReq_hits::cpu0.data 11396766 # number of WriteReq hits
891system.cpu0.dcache.WriteReq_hits::total 11396766 # number of WriteReq hits
892system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295733 # number of SoftPFReq hits
893system.cpu0.dcache.SoftPFReq_hits::total 295733 # number of SoftPFReq hits
894system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354236 # number of LoadLockedReq hits
895system.cpu0.dcache.LoadLockedReq_hits::total 354236 # number of LoadLockedReq hits
896system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350938 # number of StoreCondReq hits
897system.cpu0.dcache.StoreCondReq_hits::total 350938 # number of StoreCondReq hits
898system.cpu0.dcache.demand_hits::cpu0.data 26108056 # number of demand (read+write) hits
899system.cpu0.dcache.demand_hits::total 26108056 # number of demand (read+write) hits
900system.cpu0.dcache.overall_hits::cpu0.data 26403789 # number of overall hits
901system.cpu0.dcache.overall_hits::total 26403789 # number of overall hits
902system.cpu0.dcache.ReadReq_misses::cpu0.data 611234 # number of ReadReq misses
903system.cpu0.dcache.ReadReq_misses::total 611234 # number of ReadReq misses
904system.cpu0.dcache.WriteReq_misses::cpu0.data 1805910 # number of WriteReq misses
905system.cpu0.dcache.WriteReq_misses::total 1805910 # number of WriteReq misses
906system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141308 # number of SoftPFReq misses
907system.cpu0.dcache.SoftPFReq_misses::total 141308 # number of SoftPFReq misses
908system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24174 # number of LoadLockedReq misses
909system.cpu0.dcache.LoadLockedReq_misses::total 24174 # number of LoadLockedReq misses
910system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21176 # number of StoreCondReq misses
911system.cpu0.dcache.StoreCondReq_misses::total 21176 # number of StoreCondReq misses
912system.cpu0.dcache.demand_misses::cpu0.data 2417144 # number of demand (read+write) misses
913system.cpu0.dcache.demand_misses::total 2417144 # number of demand (read+write) misses
914system.cpu0.dcache.overall_misses::cpu0.data 2558452 # number of overall misses
915system.cpu0.dcache.overall_misses::total 2558452 # number of overall misses
916system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9073163500 # number of ReadReq miss cycles
917system.cpu0.dcache.ReadReq_miss_latency::total 9073163500 # number of ReadReq miss cycles
918system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32396978375 # number of WriteReq miss cycles
919system.cpu0.dcache.WriteReq_miss_latency::total 32396978375 # number of WriteReq miss cycles
920system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 391326000 # number of LoadLockedReq miss cycles
921system.cpu0.dcache.LoadLockedReq_miss_latency::total 391326000 # number of LoadLockedReq miss cycles
922system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 534289500 # number of StoreCondReq miss cycles
923system.cpu0.dcache.StoreCondReq_miss_latency::total 534289500 # number of StoreCondReq miss cycles
924system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 728500 # number of StoreCondFailReq miss cycles
925system.cpu0.dcache.StoreCondFailReq_miss_latency::total 728500 # number of StoreCondFailReq miss cycles
926system.cpu0.dcache.demand_miss_latency::cpu0.data 41470141875 # number of demand (read+write) miss cycles
927system.cpu0.dcache.demand_miss_latency::total 41470141875 # number of demand (read+write) miss cycles
928system.cpu0.dcache.overall_miss_latency::cpu0.data 41470141875 # number of overall miss cycles
929system.cpu0.dcache.overall_miss_latency::total 41470141875 # number of overall miss cycles
930system.cpu0.dcache.ReadReq_accesses::cpu0.data 15322524 # number of ReadReq accesses(hits+misses)
931system.cpu0.dcache.ReadReq_accesses::total 15322524 # number of ReadReq accesses(hits+misses)
932system.cpu0.dcache.WriteReq_accesses::cpu0.data 13202676 # number of WriteReq accesses(hits+misses)
933system.cpu0.dcache.WriteReq_accesses::total 13202676 # number of WriteReq accesses(hits+misses)
934system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437041 # number of SoftPFReq accesses(hits+misses)
935system.cpu0.dcache.SoftPFReq_accesses::total 437041 # number of SoftPFReq accesses(hits+misses)
936system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378410 # number of LoadLockedReq accesses(hits+misses)
937system.cpu0.dcache.LoadLockedReq_accesses::total 378410 # number of LoadLockedReq accesses(hits+misses)
938system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372114 # number of StoreCondReq accesses(hits+misses)
939system.cpu0.dcache.StoreCondReq_accesses::total 372114 # number of StoreCondReq accesses(hits+misses)
940system.cpu0.dcache.demand_accesses::cpu0.data 28525200 # number of demand (read+write) accesses
941system.cpu0.dcache.demand_accesses::total 28525200 # number of demand (read+write) accesses
942system.cpu0.dcache.overall_accesses::cpu0.data 28962241 # number of overall (read+write) accesses
943system.cpu0.dcache.overall_accesses::total 28962241 # number of overall (read+write) accesses
944system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039891 # miss rate for ReadReq accesses
945system.cpu0.dcache.ReadReq_miss_rate::total 0.039891 # miss rate for ReadReq accesses
946system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136784 # miss rate for WriteReq accesses
947system.cpu0.dcache.WriteReq_miss_rate::total 0.136784 # miss rate for WriteReq accesses
948system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323329 # miss rate for SoftPFReq accesses
949system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323329 # miss rate for SoftPFReq accesses
950system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063883 # miss rate for LoadLockedReq accesses
951system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063883 # miss rate for LoadLockedReq accesses
952system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056907 # miss rate for StoreCondReq accesses
953system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056907 # miss rate for StoreCondReq accesses
954system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084737 # miss rate for demand accesses
955system.cpu0.dcache.demand_miss_rate::total 0.084737 # miss rate for demand accesses
956system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088338 # miss rate for overall accesses
957system.cpu0.dcache.overall_miss_rate::total 0.088338 # miss rate for overall accesses
958system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14844.009823 # average ReadReq miss latency
959system.cpu0.dcache.ReadReq_avg_miss_latency::total 14844.009823 # average ReadReq miss latency
960system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17939.420223 # average WriteReq miss latency
961system.cpu0.dcache.WriteReq_avg_miss_latency::total 17939.420223 # average WriteReq miss latency
962system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16187.887813 # average LoadLockedReq miss latency
963system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16187.887813 # average LoadLockedReq miss latency
964system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25230.898187 # average StoreCondReq miss latency
965system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25230.898187 # average StoreCondReq miss latency

970system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
971system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency

966system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
967system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency

972system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14193.702152 # average overall miss latency
973system.cpu0.dcache.demand_avg_miss_latency::total 14193.702152 # average overall miss latency
974system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13414.105773 # average overall miss latency
975system.cpu0.dcache.overall_avg_miss_latency::total 13414.105773 # average overall miss latency
976system.cpu0.dcache.blocked_cycles::no_mshrs 682 # number of cycles access was blocked
977system.cpu0.dcache.blocked_cycles::no_targets 4150493 # number of cycles access was blocked
978system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
979system.cpu0.dcache.blocked::no_targets 202595 # number of cycles access was blocked
980system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked
981system.cpu0.dcache.avg_blocked_cycles::no_targets 20.486651 # average number of cycles each access was blocked

968system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17156.669969 # average overall miss latency
969system.cpu0.dcache.demand_avg_miss_latency::total 17156.669969 # average overall miss latency
970system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16209.075595 # average overall miss latency
971system.cpu0.dcache.overall_avg_miss_latency::total 16209.075595 # average overall miss latency
972system.cpu0.dcache.blocked_cycles::no_mshrs 1312 # number of cycles access was blocked
973system.cpu0.dcache.blocked_cycles::no_targets 5225040 # number of cycles access was blocked
974system.cpu0.dcache.blocked::no_mshrs 49 # number of cycles access was blocked
975system.cpu0.dcache.blocked::no_targets 192315 # number of cycles access was blocked
976system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.775510 # average number of cycles each access was blocked
977system.cpu0.dcache.avg_blocked_cycles::no_targets 27.169176 # average number of cycles each access was blocked

982system.cpu0.dcache.fast_writes 0 # number of fast writes performed
983system.cpu0.dcache.cache_copies 0 # number of cache copies performed

978system.cpu0.dcache.fast_writes 0 # number of fast writes performed
979system.cpu0.dcache.cache_copies 0 # number of cache copies performed

984system.cpu0.dcache.writebacks::writebacks 517170 # number of writebacks
985system.cpu0.dcache.writebacks::total 517170 # number of writebacks
986system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 254611 # number of ReadReq MSHR hits
987system.cpu0.dcache.ReadReq_mshr_hits::total 254611 # number of ReadReq MSHR hits
988system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1567828 # number of WriteReq MSHR hits
989system.cpu0.dcache.WriteReq_mshr_hits::total 1567828 # number of WriteReq MSHR hits
990system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18755 # number of LoadLockedReq MSHR hits
991system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18755 # number of LoadLockedReq MSHR hits
992system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822439 # number of demand (read+write) MSHR hits
993system.cpu0.dcache.demand_mshr_hits::total 1822439 # number of demand (read+write) MSHR hits
994system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822439 # number of overall MSHR hits
995system.cpu0.dcache.overall_mshr_hits::total 1822439 # number of overall MSHR hits
996system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 389883 # number of ReadReq MSHR misses
997system.cpu0.dcache.ReadReq_mshr_misses::total 389883 # number of ReadReq MSHR misses
998system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325375 # number of WriteReq MSHR misses
999system.cpu0.dcache.WriteReq_mshr_misses::total 325375 # number of WriteReq MSHR misses
1000system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102048 # number of SoftPFReq MSHR misses
1001system.cpu0.dcache.SoftPFReq_mshr_misses::total 102048 # number of SoftPFReq MSHR misses
1002system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6578 # number of LoadLockedReq MSHR misses
1003system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6578 # number of LoadLockedReq MSHR misses
1004system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20104 # number of StoreCondReq MSHR misses
1005system.cpu0.dcache.StoreCondReq_mshr_misses::total 20104 # number of StoreCondReq MSHR misses
1006system.cpu0.dcache.demand_mshr_misses::cpu0.data 715258 # number of demand (read+write) MSHR misses
1007system.cpu0.dcache.demand_mshr_misses::total 715258 # number of demand (read+write) MSHR misses
1008system.cpu0.dcache.overall_mshr_misses::cpu0.data 817306 # number of overall MSHR misses
1009system.cpu0.dcache.overall_mshr_misses::total 817306 # number of overall MSHR misses
1010system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable
1011system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable
1012system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
1013system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19086 # number of WriteReq MSHR uncacheable
1014system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses
1015system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39472 # number of overall MSHR uncacheable misses
1016system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4555035000 # number of ReadReq MSHR miss cycles
1017system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4555035000 # number of ReadReq MSHR miss cycles
1018system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5512912898 # number of WriteReq MSHR miss cycles
1019system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5512912898 # number of WriteReq MSHR miss cycles
1020system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1660765500 # number of SoftPFReq MSHR miss cycles
1021system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1660765500 # number of SoftPFReq MSHR miss cycles
1022system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101006000 # number of LoadLockedReq MSHR miss cycles
1023system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101006000 # number of LoadLockedReq MSHR miss cycles
1024system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 430792500 # number of StoreCondReq MSHR miss cycles
1025system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 430792500 # number of StoreCondReq MSHR miss cycles
1026system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 441000 # number of StoreCondFailReq MSHR miss cycles
1027system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 441000 # number of StoreCondFailReq MSHR miss cycles
1028system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10067947898 # number of demand (read+write) MSHR miss cycles
1029system.cpu0.dcache.demand_mshr_miss_latency::total 10067947898 # number of demand (read+write) MSHR miss cycles
1030system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11728713398 # number of overall MSHR miss cycles
1031system.cpu0.dcache.overall_mshr_miss_latency::total 11728713398 # number of overall MSHR miss cycles
1032system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4315293000 # number of ReadReq MSHR uncacheable cycles
1033system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4315293000 # number of ReadReq MSHR uncacheable cycles
1034system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3299266500 # number of WriteReq MSHR uncacheable cycles
1035system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3299266500 # number of WriteReq MSHR uncacheable cycles
1036system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7614559500 # number of overall MSHR uncacheable cycles
1037system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7614559500 # number of overall MSHR uncacheable cycles
1038system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023994 # mshr miss rate for ReadReq accesses
1039system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023994 # mshr miss rate for ReadReq accesses
1040system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023374 # mshr miss rate for WriteReq accesses
1041system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023374 # mshr miss rate for WriteReq accesses
1042system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222909 # mshr miss rate for SoftPFReq accesses
1043system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222909 # mshr miss rate for SoftPFReq accesses
1044system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses
1045system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses
1046system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052703 # mshr miss rate for StoreCondReq accesses
1047system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052703 # mshr miss rate for StoreCondReq accesses
1048system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023708 # mshr miss rate for demand accesses
1049system.cpu0.dcache.demand_mshr_miss_rate::total 0.023708 # mshr miss rate for demand accesses
1050system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026685 # mshr miss rate for overall accesses
1051system.cpu0.dcache.overall_mshr_miss_rate::total 0.026685 # mshr miss rate for overall accesses
1052system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11683.081848 # average ReadReq mshr miss latency
1053system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11683.081848 # average ReadReq mshr miss latency
1054system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16943.259003 # average WriteReq mshr miss latency
1055system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16943.259003 # average WriteReq mshr miss latency
1056system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16274.356185 # average SoftPFReq mshr miss latency
1057system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16274.356185 # average SoftPFReq mshr miss latency
1058system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15355.123138 # average LoadLockedReq mshr miss latency
1059system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15355.123138 # average LoadLockedReq mshr miss latency
1060system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21428.198368 # average StoreCondReq mshr miss latency
1061system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21428.198368 # average StoreCondReq mshr miss latency

980system.cpu0.dcache.writebacks::writebacks 490431 # number of writebacks
981system.cpu0.dcache.writebacks::total 490431 # number of writebacks
982system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 244715 # number of ReadReq MSHR hits
983system.cpu0.dcache.ReadReq_mshr_hits::total 244715 # number of ReadReq MSHR hits
984system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493725 # number of WriteReq MSHR hits
985system.cpu0.dcache.WriteReq_mshr_hits::total 1493725 # number of WriteReq MSHR hits
986system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18048 # number of LoadLockedReq MSHR hits
987system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18048 # number of LoadLockedReq MSHR hits
988system.cpu0.dcache.demand_mshr_hits::cpu0.data 1738440 # number of demand (read+write) MSHR hits
989system.cpu0.dcache.demand_mshr_hits::total 1738440 # number of demand (read+write) MSHR hits
990system.cpu0.dcache.overall_mshr_hits::cpu0.data 1738440 # number of overall MSHR hits
991system.cpu0.dcache.overall_mshr_hits::total 1738440 # number of overall MSHR hits
992system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366519 # number of ReadReq MSHR misses
993system.cpu0.dcache.ReadReq_mshr_misses::total 366519 # number of ReadReq MSHR misses
994system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312185 # number of WriteReq MSHR misses
995system.cpu0.dcache.WriteReq_mshr_misses::total 312185 # number of WriteReq MSHR misses
996system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97992 # number of SoftPFReq MSHR misses
997system.cpu0.dcache.SoftPFReq_mshr_misses::total 97992 # number of SoftPFReq MSHR misses
998system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6126 # number of LoadLockedReq MSHR misses
999system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6126 # number of LoadLockedReq MSHR misses
1000system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21176 # number of StoreCondReq MSHR misses
1001system.cpu0.dcache.StoreCondReq_mshr_misses::total 21176 # number of StoreCondReq MSHR misses
1002system.cpu0.dcache.demand_mshr_misses::cpu0.data 678704 # number of demand (read+write) MSHR misses
1003system.cpu0.dcache.demand_mshr_misses::total 678704 # number of demand (read+write) MSHR misses
1004system.cpu0.dcache.overall_mshr_misses::cpu0.data 776696 # number of overall MSHR misses
1005system.cpu0.dcache.overall_mshr_misses::total 776696 # number of overall MSHR misses
1006system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable
1007system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17958 # number of ReadReq MSHR uncacheable
1008system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable
1009system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16709 # number of WriteReq MSHR uncacheable
1010system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses
1011system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34667 # number of overall MSHR uncacheable misses
1012system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4650113000 # number of ReadReq MSHR miss cycles
1013system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4650113000 # number of ReadReq MSHR miss cycles
1014system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6789940400 # number of WriteReq MSHR miss cycles
1015system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6789940400 # number of WriteReq MSHR miss cycles
1016system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1696741500 # number of SoftPFReq MSHR miss cycles
1017system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1696741500 # number of SoftPFReq MSHR miss cycles
1018system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97425500 # number of LoadLockedReq MSHR miss cycles
1019system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97425500 # number of LoadLockedReq MSHR miss cycles
1020system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513125500 # number of StoreCondReq MSHR miss cycles
1021system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513125500 # number of StoreCondReq MSHR miss cycles
1022system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 716500 # number of StoreCondFailReq MSHR miss cycles
1023system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 716500 # number of StoreCondFailReq MSHR miss cycles
1024system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11440053400 # number of demand (read+write) MSHR miss cycles
1025system.cpu0.dcache.demand_mshr_miss_latency::total 11440053400 # number of demand (read+write) MSHR miss cycles
1026system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13136794900 # number of overall MSHR miss cycles
1027system.cpu0.dcache.overall_mshr_miss_latency::total 13136794900 # number of overall MSHR miss cycles
1028system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3760775500 # number of ReadReq MSHR uncacheable cycles
1029system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3760775500 # number of ReadReq MSHR uncacheable cycles
1030system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2938081500 # number of WriteReq MSHR uncacheable cycles
1031system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2938081500 # number of WriteReq MSHR uncacheable cycles
1032system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6698857000 # number of overall MSHR uncacheable cycles
1033system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6698857000 # number of overall MSHR uncacheable cycles
1034system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023920 # mshr miss rate for ReadReq accesses
1035system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023920 # mshr miss rate for ReadReq accesses
1036system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023646 # mshr miss rate for WriteReq accesses
1037system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023646 # mshr miss rate for WriteReq accesses
1038system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224217 # mshr miss rate for SoftPFReq accesses
1039system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224217 # mshr miss rate for SoftPFReq accesses
1040system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016189 # mshr miss rate for LoadLockedReq accesses
1041system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016189 # mshr miss rate for LoadLockedReq accesses
1042system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056907 # mshr miss rate for StoreCondReq accesses
1043system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056907 # mshr miss rate for StoreCondReq accesses
1044system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023793 # mshr miss rate for demand accesses
1045system.cpu0.dcache.demand_mshr_miss_rate::total 0.023793 # mshr miss rate for demand accesses
1046system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026818 # mshr miss rate for overall accesses
1047system.cpu0.dcache.overall_mshr_miss_rate::total 0.026818 # mshr miss rate for overall accesses
1048system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12687.235860 # average ReadReq mshr miss latency
1049system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12687.235860 # average ReadReq mshr miss latency
1050system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21749.733011 # average WriteReq mshr miss latency
1051system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21749.733011 # average WriteReq mshr miss latency
1052system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17315.102253 # average SoftPFReq mshr miss latency
1053system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17315.102253 # average SoftPFReq mshr miss latency
1054system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15903.607574 # average LoadLockedReq mshr miss latency
1055system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15903.607574 # average LoadLockedReq mshr miss latency
1056system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24231.464866 # average StoreCondReq mshr miss latency
1057system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24231.464866 # average StoreCondReq mshr miss latency

1062system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1063system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency

1058system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1059system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency

1064system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14075.966851 # average overall mshr miss latency
1065system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14075.966851 # average overall mshr miss latency
1066system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14350.455518 # average overall mshr miss latency
1067system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14350.455518 # average overall mshr miss latency
1068system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 211679.240655 # average ReadReq mshr uncacheable latency
1069system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211679.240655 # average ReadReq mshr uncacheable latency
1070system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172863.171959 # average WriteReq mshr uncacheable latency
1071system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172863.171959 # average WriteReq mshr uncacheable latency
1072system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 192910.404844 # average overall mshr uncacheable latency
1073system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 192910.404844 # average overall mshr uncacheable latency

1060system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16855.732985 # average overall mshr miss latency
1061system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16855.732985 # average overall mshr miss latency
1062system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16913.689397 # average overall mshr miss latency
1063system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16913.689397 # average overall mshr miss latency
1064system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209420.620336 # average ReadReq mshr uncacheable latency
1065system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209420.620336 # average ReadReq mshr uncacheable latency
1066system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175838.260818 # average WriteReq mshr uncacheable latency
1067system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175838.260818 # average WriteReq mshr uncacheable latency
1068system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193234.401592 # average overall mshr uncacheable latency
1069system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193234.401592 # average overall mshr uncacheable latency

1074system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

1070system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

1075system.cpu0.icache.tags.replacements 1264231 # number of replacements
1076system.cpu0.icache.tags.tagsinuse 511.765651 # Cycle average of tags in use
1077system.cpu0.icache.tags.total_refs 36438607 # Total number of references to valid blocks.
1078system.cpu0.icache.tags.sampled_refs 1264743 # Sample count of references to valid blocks.
1079system.cpu0.icache.tags.avg_refs 28.811076 # Average number of references to valid blocks.
1080system.cpu0.icache.tags.warmup_cycle 6439669000 # Cycle when the warmup percentage was hit.
1081system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.765651 # Average occupied blocks per requestor
1082system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999542 # Average percentage of cache occupancy
1083system.cpu0.icache.tags.occ_percent::total 0.999542 # Average percentage of cache occupancy

1071system.cpu0.icache.tags.replacements 1200820 # number of replacements
1072system.cpu0.icache.tags.tagsinuse 511.709969 # Cycle average of tags in use
1073system.cpu0.icache.tags.total_refs 34456109 # Total number of references to valid blocks.
1074system.cpu0.icache.tags.sampled_refs 1201332 # Sample count of references to valid blocks.
1075system.cpu0.icache.tags.avg_refs 28.681588 # Average number of references to valid blocks.
1076system.cpu0.icache.tags.warmup_cycle 8093069500 # Cycle when the warmup percentage was hit.
1077system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.709969 # Average occupied blocks per requestor
1078system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999434 # Average percentage of cache occupancy
1079system.cpu0.icache.tags.occ_percent::total 0.999434 # Average percentage of cache occupancy

1084system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

1080system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

1085system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
1086system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
1087system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id

1081system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
1082system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
1083system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id

1088system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

1084system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

1089system.cpu0.icache.tags.tag_accesses 76777836 # Number of tag accesses
1090system.cpu0.icache.tags.data_accesses 76777836 # Number of data accesses
1091system.cpu0.icache.ReadReq_hits::cpu0.inst 36438607 # number of ReadReq hits
1092system.cpu0.icache.ReadReq_hits::total 36438607 # number of ReadReq hits
1093system.cpu0.icache.demand_hits::cpu0.inst 36438607 # number of demand (read+write) hits
1094system.cpu0.icache.demand_hits::total 36438607 # number of demand (read+write) hits
1095system.cpu0.icache.overall_hits::cpu0.inst 36438607 # number of overall hits
1096system.cpu0.icache.overall_hits::total 36438607 # number of overall hits
1097system.cpu0.icache.ReadReq_misses::cpu0.inst 1317920 # number of ReadReq misses
1098system.cpu0.icache.ReadReq_misses::total 1317920 # number of ReadReq misses
1099system.cpu0.icache.demand_misses::cpu0.inst 1317920 # number of demand (read+write) misses
1100system.cpu0.icache.demand_misses::total 1317920 # number of demand (read+write) misses
1101system.cpu0.icache.overall_misses::cpu0.inst 1317920 # number of overall misses
1102system.cpu0.icache.overall_misses::total 1317920 # number of overall misses
1103system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13045197783 # number of ReadReq miss cycles
1104system.cpu0.icache.ReadReq_miss_latency::total 13045197783 # number of ReadReq miss cycles
1105system.cpu0.icache.demand_miss_latency::cpu0.inst 13045197783 # number of demand (read+write) miss cycles
1106system.cpu0.icache.demand_miss_latency::total 13045197783 # number of demand (read+write) miss cycles
1107system.cpu0.icache.overall_miss_latency::cpu0.inst 13045197783 # number of overall miss cycles
1108system.cpu0.icache.overall_miss_latency::total 13045197783 # number of overall miss cycles
1109system.cpu0.icache.ReadReq_accesses::cpu0.inst 37756527 # number of ReadReq accesses(hits+misses)
1110system.cpu0.icache.ReadReq_accesses::total 37756527 # number of ReadReq accesses(hits+misses)
1111system.cpu0.icache.demand_accesses::cpu0.inst 37756527 # number of demand (read+write) accesses
1112system.cpu0.icache.demand_accesses::total 37756527 # number of demand (read+write) accesses
1113system.cpu0.icache.overall_accesses::cpu0.inst 37756527 # number of overall (read+write) accesses
1114system.cpu0.icache.overall_accesses::total 37756527 # number of overall (read+write) accesses
1115system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034906 # miss rate for ReadReq accesses
1116system.cpu0.icache.ReadReq_miss_rate::total 0.034906 # miss rate for ReadReq accesses
1117system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034906 # miss rate for demand accesses
1118system.cpu0.icache.demand_miss_rate::total 0.034906 # miss rate for demand accesses
1119system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034906 # miss rate for overall accesses
1120system.cpu0.icache.overall_miss_rate::total 0.034906 # miss rate for overall accesses
1121system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.322951 # average ReadReq miss latency
1122system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.322951 # average ReadReq miss latency
1123system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency
1124system.cpu0.icache.demand_avg_miss_latency::total 9898.322951 # average overall miss latency
1125system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency
1126system.cpu0.icache.overall_avg_miss_latency::total 9898.322951 # average overall miss latency
1127system.cpu0.icache.blocked_cycles::no_mshrs 1585730 # number of cycles access was blocked
1128system.cpu0.icache.blocked_cycles::no_targets 630 # number of cycles access was blocked
1129system.cpu0.icache.blocked::no_mshrs 117915 # number of cycles access was blocked
1130system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
1131system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.448077 # average number of cycles each access was blocked
1132system.cpu0.icache.avg_blocked_cycles::no_targets 57.272727 # average number of cycles each access was blocked

1085system.cpu0.icache.tags.tag_accesses 72616555 # Number of tag accesses
1086system.cpu0.icache.tags.data_accesses 72616555 # Number of data accesses
1087system.cpu0.icache.ReadReq_hits::cpu0.inst 34456109 # number of ReadReq hits
1088system.cpu0.icache.ReadReq_hits::total 34456109 # number of ReadReq hits
1089system.cpu0.icache.demand_hits::cpu0.inst 34456109 # number of demand (read+write) hits
1090system.cpu0.icache.demand_hits::total 34456109 # number of demand (read+write) hits
1091system.cpu0.icache.overall_hits::cpu0.inst 34456109 # number of overall hits
1092system.cpu0.icache.overall_hits::total 34456109 # number of overall hits
1093system.cpu0.icache.ReadReq_misses::cpu0.inst 1251492 # number of ReadReq misses
1094system.cpu0.icache.ReadReq_misses::total 1251492 # number of ReadReq misses
1095system.cpu0.icache.demand_misses::cpu0.inst 1251492 # number of demand (read+write) misses
1096system.cpu0.icache.demand_misses::total 1251492 # number of demand (read+write) misses
1097system.cpu0.icache.overall_misses::cpu0.inst 1251492 # number of overall misses
1098system.cpu0.icache.overall_misses::total 1251492 # number of overall misses
1099system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13477536890 # number of ReadReq miss cycles
1100system.cpu0.icache.ReadReq_miss_latency::total 13477536890 # number of ReadReq miss cycles
1101system.cpu0.icache.demand_miss_latency::cpu0.inst 13477536890 # number of demand (read+write) miss cycles
1102system.cpu0.icache.demand_miss_latency::total 13477536890 # number of demand (read+write) miss cycles
1103system.cpu0.icache.overall_miss_latency::cpu0.inst 13477536890 # number of overall miss cycles
1104system.cpu0.icache.overall_miss_latency::total 13477536890 # number of overall miss cycles
1105system.cpu0.icache.ReadReq_accesses::cpu0.inst 35707601 # number of ReadReq accesses(hits+misses)
1106system.cpu0.icache.ReadReq_accesses::total 35707601 # number of ReadReq accesses(hits+misses)
1107system.cpu0.icache.demand_accesses::cpu0.inst 35707601 # number of demand (read+write) accesses
1108system.cpu0.icache.demand_accesses::total 35707601 # number of demand (read+write) accesses
1109system.cpu0.icache.overall_accesses::cpu0.inst 35707601 # number of overall (read+write) accesses
1110system.cpu0.icache.overall_accesses::total 35707601 # number of overall (read+write) accesses
1111system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035048 # miss rate for ReadReq accesses
1112system.cpu0.icache.ReadReq_miss_rate::total 0.035048 # miss rate for ReadReq accesses
1113system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035048 # miss rate for demand accesses
1114system.cpu0.icache.demand_miss_rate::total 0.035048 # miss rate for demand accesses
1115system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035048 # miss rate for overall accesses
1116system.cpu0.icache.overall_miss_rate::total 0.035048 # miss rate for overall accesses
1117system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10769.175424 # average ReadReq miss latency
1118system.cpu0.icache.ReadReq_avg_miss_latency::total 10769.175424 # average ReadReq miss latency
1119system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency
1120system.cpu0.icache.demand_avg_miss_latency::total 10769.175424 # average overall miss latency
1121system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency
1122system.cpu0.icache.overall_avg_miss_latency::total 10769.175424 # average overall miss latency
1123system.cpu0.icache.blocked_cycles::no_mshrs 1798735 # number of cycles access was blocked
1124system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked
1125system.cpu0.icache.blocked::no_mshrs 112593 # number of cycles access was blocked
1126system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked
1127system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.975549 # average number of cycles each access was blocked
1128system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked

1133system.cpu0.icache.fast_writes 0 # number of fast writes performed
1134system.cpu0.icache.cache_copies 0 # number of cache copies performed

1129system.cpu0.icache.fast_writes 0 # number of fast writes performed
1130system.cpu0.icache.cache_copies 0 # number of cache copies performed

1135system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53136 # number of ReadReq MSHR hits
1136system.cpu0.icache.ReadReq_mshr_hits::total 53136 # number of ReadReq MSHR hits
1137system.cpu0.icache.demand_mshr_hits::cpu0.inst 53136 # number of demand (read+write) MSHR hits
1138system.cpu0.icache.demand_mshr_hits::total 53136 # number of demand (read+write) MSHR hits
1139system.cpu0.icache.overall_mshr_hits::cpu0.inst 53136 # number of overall MSHR hits
1140system.cpu0.icache.overall_mshr_hits::total 53136 # number of overall MSHR hits
1141system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264784 # number of ReadReq MSHR misses
1142system.cpu0.icache.ReadReq_mshr_misses::total 1264784 # number of ReadReq MSHR misses
1143system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264784 # number of demand (read+write) MSHR misses
1144system.cpu0.icache.demand_mshr_misses::total 1264784 # number of demand (read+write) MSHR misses
1145system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264784 # number of overall MSHR misses
1146system.cpu0.icache.overall_mshr_misses::total 1264784 # number of overall MSHR misses

1131system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50137 # number of ReadReq MSHR hits
1132system.cpu0.icache.ReadReq_mshr_hits::total 50137 # number of ReadReq MSHR hits
1133system.cpu0.icache.demand_mshr_hits::cpu0.inst 50137 # number of demand (read+write) MSHR hits
1134system.cpu0.icache.demand_mshr_hits::total 50137 # number of demand (read+write) MSHR hits
1135system.cpu0.icache.overall_mshr_hits::cpu0.inst 50137 # number of overall MSHR hits
1136system.cpu0.icache.overall_mshr_hits::total 50137 # number of overall MSHR hits
1137system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201355 # number of ReadReq MSHR misses
1138system.cpu0.icache.ReadReq_mshr_misses::total 1201355 # number of ReadReq MSHR misses
1139system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201355 # number of demand (read+write) MSHR misses
1140system.cpu0.icache.demand_mshr_misses::total 1201355 # number of demand (read+write) MSHR misses
1141system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201355 # number of overall MSHR misses
1142system.cpu0.icache.overall_mshr_misses::total 1201355 # number of overall MSHR misses

1147system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
1148system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
1149system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
1150system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses

1143system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
1144system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
1145system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
1146system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses

1151system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11837775153 # number of ReadReq MSHR miss cycles
1152system.cpu0.icache.ReadReq_mshr_miss_latency::total 11837775153 # number of ReadReq MSHR miss cycles
1153system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11837775153 # number of demand (read+write) MSHR miss cycles
1154system.cpu0.icache.demand_mshr_miss_latency::total 11837775153 # number of demand (read+write) MSHR miss cycles
1155system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11837775153 # number of overall MSHR miss cycles
1156system.cpu0.icache.overall_mshr_miss_latency::total 11837775153 # number of overall MSHR miss cycles
1157system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265874998 # number of ReadReq MSHR uncacheable cycles
1158system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265874998 # number of ReadReq MSHR uncacheable cycles
1159system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265874998 # number of overall MSHR uncacheable cycles
1160system.cpu0.icache.overall_mshr_uncacheable_latency::total 265874998 # number of overall MSHR uncacheable cycles
1161system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for ReadReq accesses
1162system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033498 # mshr miss rate for ReadReq accesses
1163system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for demand accesses
1164system.cpu0.icache.demand_mshr_miss_rate::total 0.033498 # mshr miss rate for demand accesses
1165system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for overall accesses
1166system.cpu0.icache.overall_mshr_miss_rate::total 0.033498 # mshr miss rate for overall accesses
1167system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average ReadReq mshr miss latency
1168system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9359.523170 # average ReadReq mshr miss latency
1169system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency
1170system.cpu0.icache.demand_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency
1171system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency
1172system.cpu0.icache.overall_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency
1173system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average ReadReq mshr uncacheable latency
1174system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013 # average ReadReq mshr uncacheable latency
1175system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average overall mshr uncacheable latency
1176system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013 # average overall mshr uncacheable latency

1147system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12113813705 # number of ReadReq MSHR miss cycles
1148system.cpu0.icache.ReadReq_mshr_miss_latency::total 12113813705 # number of ReadReq MSHR miss cycles
1149system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12113813705 # number of demand (read+write) MSHR miss cycles
1150system.cpu0.icache.demand_mshr_miss_latency::total 12113813705 # number of demand (read+write) MSHR miss cycles
1151system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12113813705 # number of overall MSHR miss cycles
1152system.cpu0.icache.overall_mshr_miss_latency::total 12113813705 # number of overall MSHR miss cycles
1153system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420637998 # number of ReadReq MSHR uncacheable cycles
1154system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420637998 # number of ReadReq MSHR uncacheable cycles
1155system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420637998 # number of overall MSHR uncacheable cycles
1156system.cpu0.icache.overall_mshr_uncacheable_latency::total 420637998 # number of overall MSHR uncacheable cycles
1157system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for ReadReq accesses
1158system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033644 # mshr miss rate for ReadReq accesses
1159system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for demand accesses
1160system.cpu0.icache.demand_mshr_miss_rate::total 0.033644 # mshr miss rate for demand accesses
1161system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for overall accesses
1162system.cpu0.icache.overall_mshr_miss_rate::total 0.033644 # mshr miss rate for overall accesses
1163system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average ReadReq mshr miss latency
1164system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10083.458849 # average ReadReq mshr miss latency
1165system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency
1166system.cpu0.icache.demand_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency
1167system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency
1168system.cpu0.icache.overall_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency
1169system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average ReadReq mshr uncacheable latency
1170system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140025.964714 # average ReadReq mshr uncacheable latency
1171system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average overall mshr uncacheable latency
1172system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140025.964714 # average overall mshr uncacheable latency

1177system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate

1173system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate

1178system.cpu0.l2cache.prefetcher.num_hwpf_issued 1848695 # number of hwpf issued
1179system.cpu0.l2cache.prefetcher.pfIdentified 1851312 # number of prefetch candidates identified
1180system.cpu0.l2cache.prefetcher.pfBufferHit 2366 # number of redundant prefetches already in prefetch queue

1174system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767941 # number of hwpf issued
1175system.cpu0.l2cache.prefetcher.pfIdentified 1770755 # number of prefetch candidates identified
1176system.cpu0.l2cache.prefetcher.pfBufferHit 2568 # number of redundant prefetches already in prefetch queue

1181system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1182system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size

1177system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1178system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size

1183system.cpu0.l2cache.prefetcher.pfSpanPage 233112 # number of prefetches not generated due to page crossing
1184system.cpu0.l2cache.tags.replacements 279786 # number of replacements
1185system.cpu0.l2cache.tags.tagsinuse 16110.932478 # Cycle average of tags in use
1186system.cpu0.l2cache.tags.total_refs 3625969 # Total number of references to valid blocks.
1187system.cpu0.l2cache.tags.sampled_refs 296031 # Sample count of references to valid blocks.
1188system.cpu0.l2cache.tags.avg_refs 12.248612 # Average number of references to valid blocks.
1189system.cpu0.l2cache.tags.warmup_cycle 2809841331000 # Cycle when the warmup percentage was hit.
1190system.cpu0.l2cache.tags.occ_blocks::writebacks 7402.389300 # Average occupied blocks per requestor
1191system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.896732 # Average occupied blocks per requestor
1192system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.359713 # Average occupied blocks per requestor
1193system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5003.167978 # Average occupied blocks per requestor
1194system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1996.783797 # Average occupied blocks per requestor
1195system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1695.334959 # Average occupied blocks per requestor
1196system.cpu0.l2cache.tags.occ_percent::writebacks 0.451806 # Average percentage of cache occupancy
1197system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000726 # Average percentage of cache occupancy
1198system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000083 # Average percentage of cache occupancy
1199system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.305369 # Average percentage of cache occupancy
1200system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.121874 # Average percentage of cache occupancy
1201system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.103475 # Average percentage of cache occupancy
1202system.cpu0.l2cache.tags.occ_percent::total 0.983333 # Average percentage of cache occupancy
1203system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1041 # Occupied blocks per task id
1204system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
1205system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15195 # Occupied blocks per task id
1206system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id
1207system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id
1208system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 403 # Occupied blocks per task id
1209system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 288 # Occupied blocks per task id
1210system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
1211system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id

1179system.cpu0.l2cache.prefetcher.pfSpanPage 220461 # number of prefetches not generated due to page crossing
1180system.cpu0.l2cache.tags.replacements 267926 # number of replacements
1181system.cpu0.l2cache.tags.tagsinuse 16038.044511 # Cycle average of tags in use
1182system.cpu0.l2cache.tags.total_refs 3405557 # Total number of references to valid blocks.
1183system.cpu0.l2cache.tags.sampled_refs 284162 # Sample count of references to valid blocks.
1184system.cpu0.l2cache.tags.avg_refs 11.984562 # Average number of references to valid blocks.
1185system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1186system.cpu0.l2cache.tags.occ_blocks::writebacks 9237.046322 # Average occupied blocks per requestor
1187system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.824240 # Average occupied blocks per requestor
1188system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.088026 # Average occupied blocks per requestor
1189system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3962.897629 # Average occupied blocks per requestor
1190system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1653.213235 # Average occupied blocks per requestor
1191system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.975059 # Average occupied blocks per requestor
1192system.cpu0.l2cache.tags.occ_percent::writebacks 0.563785 # Average percentage of cache occupancy
1193system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy
1194system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
1195system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.241876 # Average percentage of cache occupancy
1196system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100904 # Average percentage of cache occupancy
1197system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071532 # Average percentage of cache occupancy
1198system.cpu0.l2cache.tags.occ_percent::total 0.978885 # Average percentage of cache occupancy
1199system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1081 # Occupied blocks per task id
1200system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
1201system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15141 # Occupied blocks per task id
1202system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 42 # Occupied blocks per task id
1203system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id
1204system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 429 # Occupied blocks per task id
1205system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 306 # Occupied blocks per task id
1206system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
1207system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
1208system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id

1212system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id

1209system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id

1213system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
1214system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id
1215system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4805 # Occupied blocks per task id
1216system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7004 # Occupied blocks per task id
1217system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2900 # Occupied blocks per task id
1218system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063538 # Percentage of cache occupancy per task id
1219system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
1220system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927429 # Percentage of cache occupancy per task id
1221system.cpu0.l2cache.tags.tag_accesses 66593364 # Number of tag accesses
1222system.cpu0.l2cache.tags.data_accesses 66593364 # Number of data accesses
1223system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 52693 # number of ReadReq hits
1224system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12386 # number of ReadReq hits
1225system.cpu0.l2cache.ReadReq_hits::total 65079 # number of ReadReq hits
1226system.cpu0.l2cache.Writeback_hits::writebacks 517165 # number of Writeback hits
1227system.cpu0.l2cache.Writeback_hits::total 517165 # number of Writeback hits
1228system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28793 # number of UpgradeReq hits
1229system.cpu0.l2cache.UpgradeReq_hits::total 28793 # number of UpgradeReq hits
1230system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1744 # number of SCUpgradeReq hits
1231system.cpu0.l2cache.SCUpgradeReq_hits::total 1744 # number of SCUpgradeReq hits
1232system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223098 # number of ReadExReq hits
1233system.cpu0.l2cache.ReadExReq_hits::total 223098 # number of ReadExReq hits
1234system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1208893 # number of ReadCleanReq hits
1235system.cpu0.l2cache.ReadCleanReq_hits::total 1208893 # number of ReadCleanReq hits
1236system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 400319 # number of ReadSharedReq hits
1237system.cpu0.l2cache.ReadSharedReq_hits::total 400319 # number of ReadSharedReq hits
1238system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 52693 # number of demand (read+write) hits
1239system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12386 # number of demand (read+write) hits
1240system.cpu0.l2cache.demand_hits::cpu0.inst 1208893 # number of demand (read+write) hits
1241system.cpu0.l2cache.demand_hits::cpu0.data 623417 # number of demand (read+write) hits
1242system.cpu0.l2cache.demand_hits::total 1897389 # number of demand (read+write) hits
1243system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 52693 # number of overall hits
1244system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12386 # number of overall hits
1245system.cpu0.l2cache.overall_hits::cpu0.inst 1208893 # number of overall hits
1246system.cpu0.l2cache.overall_hits::cpu0.data 623417 # number of overall hits
1247system.cpu0.l2cache.overall_hits::total 1897389 # number of overall hits
1248system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 398 # number of ReadReq misses
1249system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 157 # number of ReadReq misses
1250system.cpu0.l2cache.ReadReq_misses::total 555 # number of ReadReq misses
1251system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26381 # number of UpgradeReq misses
1252system.cpu0.l2cache.UpgradeReq_misses::total 26381 # number of UpgradeReq misses
1253system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18360 # number of SCUpgradeReq misses
1254system.cpu0.l2cache.SCUpgradeReq_misses::total 18360 # number of SCUpgradeReq misses
1255system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47293 # number of ReadExReq misses
1256system.cpu0.l2cache.ReadExReq_misses::total 47293 # number of ReadExReq misses
1257system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55856 # number of ReadCleanReq misses
1258system.cpu0.l2cache.ReadCleanReq_misses::total 55856 # number of ReadCleanReq misses
1259system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98075 # number of ReadSharedReq misses
1260system.cpu0.l2cache.ReadSharedReq_misses::total 98075 # number of ReadSharedReq misses
1261system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 398 # number of demand (read+write) misses
1262system.cpu0.l2cache.demand_misses::cpu0.itb.walker 157 # number of demand (read+write) misses
1263system.cpu0.l2cache.demand_misses::cpu0.inst 55856 # number of demand (read+write) misses
1264system.cpu0.l2cache.demand_misses::cpu0.data 145368 # number of demand (read+write) misses
1265system.cpu0.l2cache.demand_misses::total 201779 # number of demand (read+write) misses
1266system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 398 # number of overall misses
1267system.cpu0.l2cache.overall_misses::cpu0.itb.walker 157 # number of overall misses
1268system.cpu0.l2cache.overall_misses::cpu0.inst 55856 # number of overall misses
1269system.cpu0.l2cache.overall_misses::cpu0.data 145368 # number of overall misses
1270system.cpu0.l2cache.overall_misses::total 201779 # number of overall misses
1271system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10822500 # number of ReadReq miss cycles
1272system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3611000 # number of ReadReq miss cycles
1273system.cpu0.l2cache.ReadReq_miss_latency::total 14433500 # number of ReadReq miss cycles
1274system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 484495000 # number of UpgradeReq miss cycles
1275system.cpu0.l2cache.UpgradeReq_miss_latency::total 484495000 # number of UpgradeReq miss cycles
1276system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 371083000 # number of SCUpgradeReq miss cycles
1277system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 371083000 # number of SCUpgradeReq miss cycles
1278system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 421500 # number of SCUpgradeFailReq miss cycles
1279system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 421500 # number of SCUpgradeFailReq miss cycles
1280system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2673446497 # number of ReadExReq miss cycles
1281system.cpu0.l2cache.ReadExReq_miss_latency::total 2673446497 # number of ReadExReq miss cycles
1282system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2697437499 # number of ReadCleanReq miss cycles
1283system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2697437499 # number of ReadCleanReq miss cycles
1284system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2928360998 # number of ReadSharedReq miss cycles
1285system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2928360998 # number of ReadSharedReq miss cycles
1286system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10822500 # number of demand (read+write) miss cycles
1287system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3611000 # number of demand (read+write) miss cycles
1288system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2697437499 # number of demand (read+write) miss cycles
1289system.cpu0.l2cache.demand_miss_latency::cpu0.data 5601807495 # number of demand (read+write) miss cycles
1290system.cpu0.l2cache.demand_miss_latency::total 8313678494 # number of demand (read+write) miss cycles
1291system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10822500 # number of overall miss cycles
1292system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3611000 # number of overall miss cycles
1293system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2697437499 # number of overall miss cycles
1294system.cpu0.l2cache.overall_miss_latency::cpu0.data 5601807495 # number of overall miss cycles
1295system.cpu0.l2cache.overall_miss_latency::total 8313678494 # number of overall miss cycles
1296system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 53091 # number of ReadReq accesses(hits+misses)
1297system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12543 # number of ReadReq accesses(hits+misses)
1298system.cpu0.l2cache.ReadReq_accesses::total 65634 # number of ReadReq accesses(hits+misses)
1299system.cpu0.l2cache.Writeback_accesses::writebacks 517165 # number of Writeback accesses(hits+misses)
1300system.cpu0.l2cache.Writeback_accesses::total 517165 # number of Writeback accesses(hits+misses)
1301system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55174 # number of UpgradeReq accesses(hits+misses)
1302system.cpu0.l2cache.UpgradeReq_accesses::total 55174 # number of UpgradeReq accesses(hits+misses)
1303system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20104 # number of SCUpgradeReq accesses(hits+misses)
1304system.cpu0.l2cache.SCUpgradeReq_accesses::total 20104 # number of SCUpgradeReq accesses(hits+misses)
1305system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270391 # number of ReadExReq accesses(hits+misses)
1306system.cpu0.l2cache.ReadExReq_accesses::total 270391 # number of ReadExReq accesses(hits+misses)
1307system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1264749 # number of ReadCleanReq accesses(hits+misses)
1308system.cpu0.l2cache.ReadCleanReq_accesses::total 1264749 # number of ReadCleanReq accesses(hits+misses)
1309system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 498394 # number of ReadSharedReq accesses(hits+misses)
1310system.cpu0.l2cache.ReadSharedReq_accesses::total 498394 # number of ReadSharedReq accesses(hits+misses)
1311system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 53091 # number of demand (read+write) accesses
1312system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12543 # number of demand (read+write) accesses
1313system.cpu0.l2cache.demand_accesses::cpu0.inst 1264749 # number of demand (read+write) accesses
1314system.cpu0.l2cache.demand_accesses::cpu0.data 768785 # number of demand (read+write) accesses
1315system.cpu0.l2cache.demand_accesses::total 2099168 # number of demand (read+write) accesses
1316system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 53091 # number of overall (read+write) accesses
1317system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12543 # number of overall (read+write) accesses
1318system.cpu0.l2cache.overall_accesses::cpu0.inst 1264749 # number of overall (read+write) accesses
1319system.cpu0.l2cache.overall_accesses::cpu0.data 768785 # number of overall (read+write) accesses
1320system.cpu0.l2cache.overall_accesses::total 2099168 # number of overall (read+write) accesses
1321system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for ReadReq accesses
1322system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012517 # miss rate for ReadReq accesses
1323system.cpu0.l2cache.ReadReq_miss_rate::total 0.008456 # miss rate for ReadReq accesses
1324system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478142 # miss rate for UpgradeReq accesses
1325system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478142 # miss rate for UpgradeReq accesses
1326system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.913251 # miss rate for SCUpgradeReq accesses
1327system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.913251 # miss rate for SCUpgradeReq accesses
1328system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174906 # miss rate for ReadExReq accesses
1329system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174906 # miss rate for ReadExReq accesses
1330system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.044164 # miss rate for ReadCleanReq accesses
1331system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.044164 # miss rate for ReadCleanReq accesses
1332system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.196782 # miss rate for ReadSharedReq accesses
1333system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.196782 # miss rate for ReadSharedReq accesses
1334system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for demand accesses
1335system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012517 # miss rate for demand accesses
1336system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.044164 # miss rate for demand accesses
1337system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189088 # miss rate for demand accesses
1338system.cpu0.l2cache.demand_miss_rate::total 0.096123 # miss rate for demand accesses
1339system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for overall accesses
1340system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012517 # miss rate for overall accesses
1341system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.044164 # miss rate for overall accesses
1342system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189088 # miss rate for overall accesses
1343system.cpu0.l2cache.overall_miss_rate::total 0.096123 # miss rate for overall accesses
1344system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average ReadReq miss latency
1345system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23000 # average ReadReq miss latency
1346system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26006.306306 # average ReadReq miss latency
1347system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18365.300785 # average UpgradeReq miss latency
1348system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18365.300785 # average UpgradeReq miss latency
1349system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20211.492375 # average SCUpgradeReq miss latency
1350system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20211.492375 # average SCUpgradeReq miss latency
1351system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
1352system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
1353system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56529.433468 # average ReadExReq miss latency
1354system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56529.433468 # average ReadExReq miss latency
1355system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48292.708017 # average ReadCleanReq miss latency
1356system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48292.708017 # average ReadCleanReq miss latency
1357system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29858.383869 # average ReadSharedReq miss latency
1358system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29858.383869 # average ReadSharedReq miss latency
1359system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average overall miss latency
1360system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23000 # average overall miss latency
1361system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48292.708017 # average overall miss latency
1362system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38535.355064 # average overall miss latency
1363system.cpu0.l2cache.demand_avg_miss_latency::total 41201.901556 # average overall miss latency
1364system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average overall miss latency
1365system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23000 # average overall miss latency
1366system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48292.708017 # average overall miss latency
1367system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38535.355064 # average overall miss latency
1368system.cpu0.l2cache.overall_avg_miss_latency::total 41201.901556 # average overall miss latency
1369system.cpu0.l2cache.blocked_cycles::no_mshrs 214 # number of cycles access was blocked

1210system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
1211system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
1212system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4597 # Occupied blocks per task id
1213system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7301 # Occupied blocks per task id
1214system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2771 # Occupied blocks per task id
1215system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065979 # Percentage of cache occupancy per task id
1216system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
1217system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924133 # Percentage of cache occupancy per task id
1218system.cpu0.l2cache.tags.tag_accesses 63212919 # Number of tag accesses
1219system.cpu0.l2cache.tags.data_accesses 63212919 # Number of data accesses
1220system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49275 # number of ReadReq hits
1221system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12221 # number of ReadReq hits
1222system.cpu0.l2cache.ReadReq_hits::total 61496 # number of ReadReq hits
1223system.cpu0.l2cache.Writeback_hits::writebacks 490428 # number of Writeback hits
1224system.cpu0.l2cache.Writeback_hits::total 490428 # number of Writeback hits
1225system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28559 # number of UpgradeReq hits
1226system.cpu0.l2cache.UpgradeReq_hits::total 28559 # number of UpgradeReq hits
1227system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1634 # number of SCUpgradeReq hits
1228system.cpu0.l2cache.SCUpgradeReq_hits::total 1634 # number of SCUpgradeReq hits
1229system.cpu0.l2cache.ReadExReq_hits::cpu0.data 183915 # number of ReadExReq hits
1230system.cpu0.l2cache.ReadExReq_hits::total 183915 # number of ReadExReq hits
1231system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1150269 # number of ReadCleanReq hits
1232system.cpu0.l2cache.ReadCleanReq_hits::total 1150269 # number of ReadCleanReq hits
1233system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 371621 # number of ReadSharedReq hits
1234system.cpu0.l2cache.ReadSharedReq_hits::total 371621 # number of ReadSharedReq hits
1235system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49275 # number of demand (read+write) hits
1236system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12221 # number of demand (read+write) hits
1237system.cpu0.l2cache.demand_hits::cpu0.inst 1150269 # number of demand (read+write) hits
1238system.cpu0.l2cache.demand_hits::cpu0.data 555536 # number of demand (read+write) hits
1239system.cpu0.l2cache.demand_hits::total 1767301 # number of demand (read+write) hits
1240system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49275 # number of overall hits
1241system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12221 # number of overall hits
1242system.cpu0.l2cache.overall_hits::cpu0.inst 1150269 # number of overall hits
1243system.cpu0.l2cache.overall_hits::cpu0.data 555536 # number of overall hits
1244system.cpu0.l2cache.overall_hits::total 1767301 # number of overall hits
1245system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 406 # number of ReadReq misses
1246system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 160 # number of ReadReq misses
1247system.cpu0.l2cache.ReadReq_misses::total 566 # number of ReadReq misses
1248system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27413 # number of UpgradeReq misses
1249system.cpu0.l2cache.UpgradeReq_misses::total 27413 # number of UpgradeReq misses
1250system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19541 # number of SCUpgradeReq misses
1251system.cpu0.l2cache.SCUpgradeReq_misses::total 19541 # number of SCUpgradeReq misses
1252system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
1253system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
1254system.cpu0.l2cache.ReadExReq_misses::cpu0.data 72546 # number of ReadExReq misses
1255system.cpu0.l2cache.ReadExReq_misses::total 72546 # number of ReadExReq misses
1256system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 51075 # number of ReadCleanReq misses
1257system.cpu0.l2cache.ReadCleanReq_misses::total 51075 # number of ReadCleanReq misses
1258system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98927 # number of ReadSharedReq misses
1259system.cpu0.l2cache.ReadSharedReq_misses::total 98927 # number of ReadSharedReq misses
1260system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 406 # number of demand (read+write) misses
1261system.cpu0.l2cache.demand_misses::cpu0.itb.walker 160 # number of demand (read+write) misses
1262system.cpu0.l2cache.demand_misses::cpu0.inst 51075 # number of demand (read+write) misses
1263system.cpu0.l2cache.demand_misses::cpu0.data 171473 # number of demand (read+write) misses
1264system.cpu0.l2cache.demand_misses::total 223114 # number of demand (read+write) misses
1265system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 406 # number of overall misses
1266system.cpu0.l2cache.overall_misses::cpu0.itb.walker 160 # number of overall misses
1267system.cpu0.l2cache.overall_misses::cpu0.inst 51075 # number of overall misses
1268system.cpu0.l2cache.overall_misses::cpu0.data 171473 # number of overall misses
1269system.cpu0.l2cache.overall_misses::total 223114 # number of overall misses
1270system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 12326500 # number of ReadReq miss cycles
1271system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4195000 # number of ReadReq miss cycles
1272system.cpu0.l2cache.ReadReq_miss_latency::total 16521500 # number of ReadReq miss cycles
1273system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 607087500 # number of UpgradeReq miss cycles
1274system.cpu0.l2cache.UpgradeReq_miss_latency::total 607087500 # number of UpgradeReq miss cycles
1275system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 414982000 # number of SCUpgradeReq miss cycles
1276system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 414982000 # number of SCUpgradeReq miss cycles
1277system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 697999 # number of SCUpgradeFailReq miss cycles
1278system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 697999 # number of SCUpgradeFailReq miss cycles
1279system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3859915499 # number of ReadExReq miss cycles
1280system.cpu0.l2cache.ReadExReq_miss_latency::total 3859915499 # number of ReadExReq miss cycles
1281system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3399489999 # number of ReadCleanReq miss cycles
1282system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3399489999 # number of ReadCleanReq miss cycles
1283system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3280988498 # number of ReadSharedReq miss cycles
1284system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3280988498 # number of ReadSharedReq miss cycles
1285system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 12326500 # number of demand (read+write) miss cycles
1286system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4195000 # number of demand (read+write) miss cycles
1287system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3399489999 # number of demand (read+write) miss cycles
1288system.cpu0.l2cache.demand_miss_latency::cpu0.data 7140903997 # number of demand (read+write) miss cycles
1289system.cpu0.l2cache.demand_miss_latency::total 10556915496 # number of demand (read+write) miss cycles
1290system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 12326500 # number of overall miss cycles
1291system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4195000 # number of overall miss cycles
1292system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3399489999 # number of overall miss cycles
1293system.cpu0.l2cache.overall_miss_latency::cpu0.data 7140903997 # number of overall miss cycles
1294system.cpu0.l2cache.overall_miss_latency::total 10556915496 # number of overall miss cycles
1295system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 49681 # number of ReadReq accesses(hits+misses)
1296system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12381 # number of ReadReq accesses(hits+misses)
1297system.cpu0.l2cache.ReadReq_accesses::total 62062 # number of ReadReq accesses(hits+misses)
1298system.cpu0.l2cache.Writeback_accesses::writebacks 490428 # number of Writeback accesses(hits+misses)
1299system.cpu0.l2cache.Writeback_accesses::total 490428 # number of Writeback accesses(hits+misses)
1300system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55972 # number of UpgradeReq accesses(hits+misses)
1301system.cpu0.l2cache.UpgradeReq_accesses::total 55972 # number of UpgradeReq accesses(hits+misses)
1302system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21175 # number of SCUpgradeReq accesses(hits+misses)
1303system.cpu0.l2cache.SCUpgradeReq_accesses::total 21175 # number of SCUpgradeReq accesses(hits+misses)
1304system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
1305system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
1306system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256461 # number of ReadExReq accesses(hits+misses)
1307system.cpu0.l2cache.ReadExReq_accesses::total 256461 # number of ReadExReq accesses(hits+misses)
1308system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1201344 # number of ReadCleanReq accesses(hits+misses)
1309system.cpu0.l2cache.ReadCleanReq_accesses::total 1201344 # number of ReadCleanReq accesses(hits+misses)
1310system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 470548 # number of ReadSharedReq accesses(hits+misses)
1311system.cpu0.l2cache.ReadSharedReq_accesses::total 470548 # number of ReadSharedReq accesses(hits+misses)
1312system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 49681 # number of demand (read+write) accesses
1313system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12381 # number of demand (read+write) accesses
1314system.cpu0.l2cache.demand_accesses::cpu0.inst 1201344 # number of demand (read+write) accesses
1315system.cpu0.l2cache.demand_accesses::cpu0.data 727009 # number of demand (read+write) accesses
1316system.cpu0.l2cache.demand_accesses::total 1990415 # number of demand (read+write) accesses
1317system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 49681 # number of overall (read+write) accesses
1318system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12381 # number of overall (read+write) accesses
1319system.cpu0.l2cache.overall_accesses::cpu0.inst 1201344 # number of overall (read+write) accesses
1320system.cpu0.l2cache.overall_accesses::cpu0.data 727009 # number of overall (read+write) accesses
1321system.cpu0.l2cache.overall_accesses::total 1990415 # number of overall (read+write) accesses
1322system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008172 # miss rate for ReadReq accesses
1323system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012923 # miss rate for ReadReq accesses
1324system.cpu0.l2cache.ReadReq_miss_rate::total 0.009120 # miss rate for ReadReq accesses
1325system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.489763 # miss rate for UpgradeReq accesses
1326system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.489763 # miss rate for UpgradeReq accesses
1327system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.922834 # miss rate for SCUpgradeReq accesses
1328system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.922834 # miss rate for SCUpgradeReq accesses
1329system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1330system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1331system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.282873 # miss rate for ReadExReq accesses
1332system.cpu0.l2cache.ReadExReq_miss_rate::total 0.282873 # miss rate for ReadExReq accesses
1333system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042515 # miss rate for ReadCleanReq accesses
1334system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042515 # miss rate for ReadCleanReq accesses
1335system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.210238 # miss rate for ReadSharedReq accesses
1336system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.210238 # miss rate for ReadSharedReq accesses
1337system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008172 # miss rate for demand accesses
1338system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012923 # miss rate for demand accesses
1339system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042515 # miss rate for demand accesses
1340system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.235861 # miss rate for demand accesses
1341system.cpu0.l2cache.demand_miss_rate::total 0.112094 # miss rate for demand accesses
1342system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008172 # miss rate for overall accesses
1343system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012923 # miss rate for overall accesses
1344system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042515 # miss rate for overall accesses
1345system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.235861 # miss rate for overall accesses
1346system.cpu0.l2cache.overall_miss_rate::total 0.112094 # miss rate for overall accesses
1347system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30360.837438 # average ReadReq miss latency
1348system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26218.750000 # average ReadReq miss latency
1349system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29189.929329 # average ReadReq miss latency
1350system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22145.970890 # average UpgradeReq miss latency
1351system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22145.970890 # average UpgradeReq miss latency
1352system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21236.477151 # average SCUpgradeReq miss latency
1353system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21236.477151 # average SCUpgradeReq miss latency
1354system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 697999 # average SCUpgradeFailReq miss latency
1355system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 697999 # average SCUpgradeFailReq miss latency
1356system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53206.455201 # average ReadExReq miss latency
1357system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53206.455201 # average ReadExReq miss latency
1358system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 66558.786079 # average ReadCleanReq miss latency
1359system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 66558.786079 # average ReadCleanReq miss latency
1360system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33165.753515 # average ReadSharedReq miss latency
1361system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33165.753515 # average ReadSharedReq miss latency
1362system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30360.837438 # average overall miss latency
1363system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26218.750000 # average overall miss latency
1364system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 66558.786079 # average overall miss latency
1365system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41644.480455 # average overall miss latency
1366system.cpu0.l2cache.demand_avg_miss_latency::total 47316.239662 # average overall miss latency
1367system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30360.837438 # average overall miss latency
1368system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26218.750000 # average overall miss latency
1369system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 66558.786079 # average overall miss latency
1370system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41644.480455 # average overall miss latency
1371system.cpu0.l2cache.overall_avg_miss_latency::total 47316.239662 # average overall miss latency
1372system.cpu0.l2cache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked

1370system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1373system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1371system.cpu0.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked

1374system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked

1372system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked

1375system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked

1373system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked

1376system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked

1374system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1375system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1376system.cpu0.l2cache.cache_copies 0 # number of cache copies performed

1377system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1378system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1379system.cpu0.l2cache.cache_copies 0 # number of cache copies performed

1377system.cpu0.l2cache.writebacks::writebacks 197696 # number of writebacks
1378system.cpu0.l2cache.writebacks::total 197696 # number of writebacks

1380system.cpu0.l2cache.writebacks::writebacks 193883 # number of writebacks
1381system.cpu0.l2cache.writebacks::total 193883 # number of writebacks

1379system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
1380system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits

1382system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
1383system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits

1381system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5476 # number of ReadExReq MSHR hits
1382system.cpu0.l2cache.ReadExReq_mshr_hits::total 5476 # number of ReadExReq MSHR hits
1383system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 32 # number of ReadCleanReq MSHR hits
1384system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 32 # number of ReadCleanReq MSHR hits
1385system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 797 # number of ReadSharedReq MSHR hits
1386system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 797 # number of ReadSharedReq MSHR hits

1384system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 31886 # number of ReadExReq MSHR hits
1385system.cpu0.l2cache.ReadExReq_mshr_hits::total 31886 # number of ReadExReq MSHR hits
1386system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 21 # number of ReadCleanReq MSHR hits
1387system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 21 # number of ReadCleanReq MSHR hits
1388system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 720 # number of ReadSharedReq MSHR hits
1389system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 720 # number of ReadSharedReq MSHR hits

1387system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits

1390system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits

1388system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 32 # number of demand (read+write) MSHR hits
1389system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6273 # number of demand (read+write) MSHR hits
1390system.cpu0.l2cache.demand_mshr_hits::total 6306 # number of demand (read+write) MSHR hits

1391system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 21 # number of demand (read+write) MSHR hits
1392system.cpu0.l2cache.demand_mshr_hits::cpu0.data 32606 # number of demand (read+write) MSHR hits
1393system.cpu0.l2cache.demand_mshr_hits::total 32628 # number of demand (read+write) MSHR hits

1391system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits

1394system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits

1392system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 32 # number of overall MSHR hits
1393system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6273 # number of overall MSHR hits
1394system.cpu0.l2cache.overall_mshr_hits::total 6306 # number of overall MSHR hits
1395system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 398 # number of ReadReq MSHR misses
1396system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 156 # number of ReadReq MSHR misses
1397system.cpu0.l2cache.ReadReq_mshr_misses::total 554 # number of ReadReq MSHR misses
1398system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8991 # number of CleanEvict MSHR misses
1399system.cpu0.l2cache.CleanEvict_mshr_misses::total 8991 # number of CleanEvict MSHR misses
1400system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245693 # number of HardPFReq MSHR misses
1401system.cpu0.l2cache.HardPFReq_mshr_misses::total 245693 # number of HardPFReq MSHR misses
1402system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26381 # number of UpgradeReq MSHR misses
1403system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26381 # number of UpgradeReq MSHR misses
1404system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18360 # number of SCUpgradeReq MSHR misses
1405system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18360 # number of SCUpgradeReq MSHR misses
1406system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41817 # number of ReadExReq MSHR misses
1407system.cpu0.l2cache.ReadExReq_mshr_misses::total 41817 # number of ReadExReq MSHR misses
1408system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55824 # number of ReadCleanReq MSHR misses
1409system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55824 # number of ReadCleanReq MSHR misses
1410system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97278 # number of ReadSharedReq MSHR misses
1411system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97278 # number of ReadSharedReq MSHR misses
1412system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 398 # number of demand (read+write) MSHR misses
1413system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 156 # number of demand (read+write) MSHR misses
1414system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55824 # number of demand (read+write) MSHR misses
1415system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139095 # number of demand (read+write) MSHR misses
1416system.cpu0.l2cache.demand_mshr_misses::total 195473 # number of demand (read+write) MSHR misses
1417system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 398 # number of overall MSHR misses
1418system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 156 # number of overall MSHR misses
1419system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55824 # number of overall MSHR misses
1420system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139095 # number of overall MSHR misses
1421system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245693 # number of overall MSHR misses
1422system.cpu0.l2cache.overall_mshr_misses::total 441166 # number of overall MSHR misses

1395system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 21 # number of overall MSHR hits
1396system.cpu0.l2cache.overall_mshr_hits::cpu0.data 32606 # number of overall MSHR hits
1397system.cpu0.l2cache.overall_mshr_hits::total 32628 # number of overall MSHR hits
1398system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 406 # number of ReadReq MSHR misses
1399system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 159 # number of ReadReq MSHR misses
1400system.cpu0.l2cache.ReadReq_mshr_misses::total 565 # number of ReadReq MSHR misses
1401system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8411 # number of CleanEvict MSHR misses
1402system.cpu0.l2cache.CleanEvict_mshr_misses::total 8411 # number of CleanEvict MSHR misses
1403system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 234452 # number of HardPFReq MSHR misses
1404system.cpu0.l2cache.HardPFReq_mshr_misses::total 234452 # number of HardPFReq MSHR misses
1405system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27413 # number of UpgradeReq MSHR misses
1406system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27413 # number of UpgradeReq MSHR misses
1407system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19541 # number of SCUpgradeReq MSHR misses
1408system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19541 # number of SCUpgradeReq MSHR misses
1409system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
1410system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
1411system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40660 # number of ReadExReq MSHR misses
1412system.cpu0.l2cache.ReadExReq_mshr_misses::total 40660 # number of ReadExReq MSHR misses
1413system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 51054 # number of ReadCleanReq MSHR misses
1414system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 51054 # number of ReadCleanReq MSHR misses
1415system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 98207 # number of ReadSharedReq MSHR misses
1416system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 98207 # number of ReadSharedReq MSHR misses
1417system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 406 # number of demand (read+write) MSHR misses
1418system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 159 # number of demand (read+write) MSHR misses
1419system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 51054 # number of demand (read+write) MSHR misses
1420system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138867 # number of demand (read+write) MSHR misses
1421system.cpu0.l2cache.demand_mshr_misses::total 190486 # number of demand (read+write) MSHR misses
1422system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 406 # number of overall MSHR misses
1423system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 159 # number of overall MSHR misses
1424system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 51054 # number of overall MSHR misses
1425system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138867 # number of overall MSHR misses
1426system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 234452 # number of overall MSHR misses
1427system.cpu0.l2cache.overall_mshr_misses::total 424938 # number of overall MSHR misses

1423system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable

1428system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable

1424system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable
1425system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23390 # number of ReadReq MSHR uncacheable
1426system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
1427system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19086 # number of WriteReq MSHR uncacheable

1429system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable
1430system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20962 # number of ReadReq MSHR uncacheable
1431system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable
1432system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16709 # number of WriteReq MSHR uncacheable

1428system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses

1433system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses

1429system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses
1430system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42476 # number of overall MSHR uncacheable misses
1431system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of ReadReq MSHR miss cycles
1432system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2662500 # number of ReadReq MSHR miss cycles
1433system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11097000 # number of ReadReq MSHR miss cycles
1434system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15042795977 # number of HardPFReq MSHR miss cycles
1435system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15042795977 # number of HardPFReq MSHR miss cycles
1436system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 537912499 # number of UpgradeReq MSHR miss cycles
1437system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 537912499 # number of UpgradeReq MSHR miss cycles
1438system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 278663498 # number of SCUpgradeReq MSHR miss cycles
1439system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 278663498 # number of SCUpgradeReq MSHR miss cycles
1440system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 343500 # number of SCUpgradeFailReq MSHR miss cycles
1441system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 343500 # number of SCUpgradeFailReq MSHR miss cycles
1442system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1730970000 # number of ReadExReq MSHR miss cycles
1443system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1730970000 # number of ReadExReq MSHR miss cycles
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1445system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2361388499 # number of ReadCleanReq MSHR miss cycles
1446system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2303131998 # number of ReadSharedReq MSHR miss cycles
1447system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2303131998 # number of ReadSharedReq MSHR miss cycles
1448system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of demand (read+write) MSHR miss cycles
1449system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2662500 # number of demand (read+write) MSHR miss cycles
1450system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2361388499 # number of demand (read+write) MSHR miss cycles
1451system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4034101998 # number of demand (read+write) MSHR miss cycles
1452system.cpu0.l2cache.demand_mshr_miss_latency::total 6406587497 # number of demand (read+write) MSHR miss cycles
1453system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of overall MSHR miss cycles
1454system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2662500 # number of overall MSHR miss cycles
1455system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2361388499 # number of overall MSHR miss cycles
1456system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4034101998 # number of overall MSHR miss cycles
1457system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15042795977 # number of overall MSHR miss cycles
1458system.cpu0.l2cache.overall_mshr_miss_latency::total 21449383474 # number of overall MSHR miss cycles
1459system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243342000 # number of ReadReq MSHR uncacheable cycles
1460system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4152104000 # number of ReadReq MSHR uncacheable cycles
1461system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4395446000 # number of ReadReq MSHR uncacheable cycles
1462system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3153204958 # number of WriteReq MSHR uncacheable cycles
1463system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3153204958 # number of WriteReq MSHR uncacheable cycles
1464system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243342000 # number of overall MSHR uncacheable cycles
1465system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7305308958 # number of overall MSHR uncacheable cycles
1466system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7548650958 # number of overall MSHR uncacheable cycles
1467system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for ReadReq accesses
1468system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for ReadReq accesses
1469system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008441 # mshr miss rate for ReadReq accesses

1434system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses
1435system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37671 # number of overall MSHR uncacheable misses
1436system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9890500 # number of ReadReq MSHR miss cycles
1437system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3228500 # number of ReadReq MSHR miss cycles
1438system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 13119000 # number of ReadReq MSHR miss cycles
1439system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20996976517 # number of HardPFReq MSHR miss cycles
1440system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20996976517 # number of HardPFReq MSHR miss cycles
1441system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 895938500 # number of UpgradeReq MSHR miss cycles
1442system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 895938500 # number of UpgradeReq MSHR miss cycles
1443system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 352988996 # number of SCUpgradeReq MSHR miss cycles
1444system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 352988996 # number of SCUpgradeReq MSHR miss cycles
1445system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 625999 # number of SCUpgradeFailReq MSHR miss cycles
1446system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 625999 # number of SCUpgradeFailReq MSHR miss cycles
1447system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2326484000 # number of ReadExReq MSHR miss cycles
1448system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2326484000 # number of ReadExReq MSHR miss cycles
1449system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3092587999 # number of ReadCleanReq MSHR miss cycles
1450system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3092587999 # number of ReadCleanReq MSHR miss cycles
1451system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2638772998 # number of ReadSharedReq MSHR miss cycles
1452system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2638772998 # number of ReadSharedReq MSHR miss cycles
1453system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9890500 # number of demand (read+write) MSHR miss cycles
1454system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3228500 # number of demand (read+write) MSHR miss cycles
1455system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3092587999 # number of demand (read+write) MSHR miss cycles
1456system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4965256998 # number of demand (read+write) MSHR miss cycles
1457system.cpu0.l2cache.demand_mshr_miss_latency::total 8070963997 # number of demand (read+write) MSHR miss cycles
1458system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9890500 # number of overall MSHR miss cycles
1459system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3228500 # number of overall MSHR miss cycles
1460system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3092587999 # number of overall MSHR miss cycles
1461system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4965256998 # number of overall MSHR miss cycles
1462system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20996976517 # number of overall MSHR miss cycles
1463system.cpu0.l2cache.overall_mshr_miss_latency::total 29067940514 # number of overall MSHR miss cycles
1464system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398106500 # number of ReadReq MSHR uncacheable cycles
1465system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3617019000 # number of ReadReq MSHR uncacheable cycles
1466system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4015125500 # number of ReadReq MSHR uncacheable cycles
1467system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2810012462 # number of WriteReq MSHR uncacheable cycles
1468system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2810012462 # number of WriteReq MSHR uncacheable cycles
1469system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398106500 # number of overall MSHR uncacheable cycles
1470system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6427031462 # number of overall MSHR uncacheable cycles
1471system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6825137962 # number of overall MSHR uncacheable cycles
1472system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for ReadReq accesses
1473system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for ReadReq accesses
1474system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009104 # mshr miss rate for ReadReq accesses

1470system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1471system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1472system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1473system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses

1475system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1476system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1477system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1478system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses

1474system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478142 # mshr miss rate for UpgradeReq accesses
1475system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478142 # mshr miss rate for UpgradeReq accesses
1476system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.913251 # mshr miss rate for SCUpgradeReq accesses
1477system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.913251 # mshr miss rate for SCUpgradeReq accesses
1478system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154654 # mshr miss rate for ReadExReq accesses
1479system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154654 # mshr miss rate for ReadExReq accesses
1480system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for ReadCleanReq accesses
1481system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044138 # mshr miss rate for ReadCleanReq accesses
1482system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.195183 # mshr miss rate for ReadSharedReq accesses
1483system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.195183 # mshr miss rate for ReadSharedReq accesses
1484system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for demand accesses
1485system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for demand accesses
1486system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for demand accesses
1487system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for demand accesses
1488system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093119 # mshr miss rate for demand accesses
1489system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for overall accesses
1490system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for overall accesses
1491system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for overall accesses
1492system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for overall accesses

1479system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489763 # mshr miss rate for UpgradeReq accesses
1480system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489763 # mshr miss rate for UpgradeReq accesses
1481system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.922834 # mshr miss rate for SCUpgradeReq accesses
1482system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.922834 # mshr miss rate for SCUpgradeReq accesses
1483system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1484system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1485system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158543 # mshr miss rate for ReadExReq accesses
1486system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158543 # mshr miss rate for ReadExReq accesses
1487system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for ReadCleanReq accesses
1488system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042497 # mshr miss rate for ReadCleanReq accesses
1489system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208708 # mshr miss rate for ReadSharedReq accesses
1490system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.208708 # mshr miss rate for ReadSharedReq accesses
1491system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for demand accesses
1492system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for demand accesses
1493system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for demand accesses
1494system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for demand accesses
1495system.cpu0.l2cache.demand_mshr_miss_rate::total 0.095702 # mshr miss rate for demand accesses
1496system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for overall accesses
1497system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for overall accesses
1498system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for overall accesses
1499system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for overall accesses

1493system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses

1500system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses

1494system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210162 # mshr miss rate for overall accesses
1495system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average ReadReq mshr miss latency
1496system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average ReadReq mshr miss latency
1497system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20030.685921 # average ReadReq mshr miss latency
1498system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average HardPFReq mshr miss latency
1499system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61225.985181 # average HardPFReq mshr miss latency
1500system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.148175 # average UpgradeReq mshr miss latency
1501system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20390.148175 # average UpgradeReq mshr miss latency
1502system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15177.750436 # average SCUpgradeReq mshr miss latency
1503system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.750436 # average SCUpgradeReq mshr miss latency
1504system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
1505system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
1506system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41393.930698 # average ReadExReq mshr miss latency
1507system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41393.930698 # average ReadExReq mshr miss latency
1508system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average ReadCleanReq mshr miss latency
1509system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42300.596500 # average ReadCleanReq mshr miss latency
1510system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23675.774564 # average ReadSharedReq mshr miss latency
1511system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23675.774564 # average ReadSharedReq mshr miss latency
1512system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency
1513system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency
1514system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency
1515system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency
1516system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32774.794969 # average overall mshr miss latency
1517system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency
1518system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency
1519system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency
1520system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency
1521system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average overall mshr miss latency
1522system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48619.756450 # average overall mshr miss latency
1523system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average ReadReq mshr uncacheable latency
1524system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203674.286275 # average ReadReq mshr uncacheable latency
1525system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 187919.880291 # average ReadReq mshr uncacheable latency
1526system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165210.361417 # average WriteReq mshr uncacheable latency
1527system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165210.361417 # average WriteReq mshr uncacheable latency
1528system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average overall mshr uncacheable latency
1529system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185075.723500 # average overall mshr uncacheable latency
1530system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 177715.673745 # average overall mshr uncacheable latency

1501system.cpu0.l2cache.overall_mshr_miss_rate::total 0.213492 # mshr miss rate for overall accesses
1502system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average ReadReq mshr miss latency
1503system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average ReadReq mshr miss latency
1504system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23219.469027 # average ReadReq mshr miss latency
1505system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average HardPFReq mshr miss latency
1506system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 89557.677124 # average HardPFReq mshr miss latency
1507system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32682.978879 # average UpgradeReq mshr miss latency
1508system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32682.978879 # average UpgradeReq mshr miss latency
1509system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18064.019037 # average SCUpgradeReq mshr miss latency
1510system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18064.019037 # average SCUpgradeReq mshr miss latency
1511system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 625999 # average SCUpgradeFailReq mshr miss latency
1512system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 625999 # average SCUpgradeFailReq mshr miss latency
1513system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57218.002951 # average ReadExReq mshr miss latency
1514system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57218.002951 # average ReadExReq mshr miss latency
1515system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average ReadCleanReq mshr miss latency
1516system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60574.842304 # average ReadCleanReq mshr miss latency
1517system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26869.500117 # average ReadSharedReq mshr miss latency
1518system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26869.500117 # average ReadSharedReq mshr miss latency
1519system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency
1520system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency
1521system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency
1522system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency
1523system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 42370.378910 # average overall mshr miss latency
1524system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency
1525system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency
1526system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency
1527system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency
1528system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average overall mshr miss latency
1529system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 68405.133252 # average overall mshr miss latency
1530system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average ReadReq mshr uncacheable latency
1531system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201415.469429 # average ReadReq mshr uncacheable latency
1532system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191543.054098 # average ReadReq mshr uncacheable latency
1533system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168173.586810 # average WriteReq mshr uncacheable latency
1534system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168173.586810 # average WriteReq mshr uncacheable latency
1535system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average overall mshr uncacheable latency
1536system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185393.355699 # average overall mshr uncacheable latency
1537system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 181177.509543 # average overall mshr uncacheable latency

1531system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1538system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1532system.cpu0.toL2Bus.trans_dist::ReadReq 118491 # Transaction distribution
1533system.cpu0.toL2Bus.trans_dist::ReadResp 1915950 # Transaction distribution
1534system.cpu0.toL2Bus.trans_dist::WriteReq 30902 # Transaction distribution
1535system.cpu0.toL2Bus.trans_dist::WriteResp 19086 # Transaction distribution
1536system.cpu0.toL2Bus.trans_dist::Writeback 881917 # Transaction distribution
1537system.cpu0.toL2Bus.trans_dist::CleanEvict 1558941 # Transaction distribution
1538system.cpu0.toL2Bus.trans_dist::HardPFReq 295049 # Transaction distribution
1539system.cpu0.toL2Bus.trans_dist::UpgradeReq 88486 # Transaction distribution
1540system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42808 # Transaction distribution
1541system.cpu0.toL2Bus.trans_dist::UpgradeResp 113105 # Transaction distribution
1542system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
1543system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
1544system.cpu0.toL2Bus.trans_dist::ReadExReq 298585 # Transaction distribution
1545system.cpu0.toL2Bus.trans_dist::ReadExResp 285519 # Transaction distribution
1546system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1264784 # Transaction distribution
1547system.cpu0.toL2Bus.trans_dist::ReadSharedReq 601994 # Transaction distribution
1548system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1549system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3774932 # Packet count per connected master and slave (bytes)
1550system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2575467 # Packet count per connected master and slave (bytes)
1551system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29033 # Packet count per connected master and slave (bytes)
1552system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 117114 # Packet count per connected master and slave (bytes)
1553system.cpu0.toL2Bus.pkt_count::total 6496546 # Packet count per connected master and slave (bytes)
1554system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80991872 # Cumulative packet size per connected master and slave (bytes)
1555system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86506920 # Cumulative packet size per connected master and slave (bytes)
1556system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50172 # Cumulative packet size per connected master and slave (bytes)
1557system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 212364 # Cumulative packet size per connected master and slave (bytes)
1558system.cpu0.toL2Bus.pkt_size::total 167761328 # Cumulative packet size per connected master and slave (bytes)
1559system.cpu0.toL2Bus.snoops 1157195 # Total snoops (count)
1560system.cpu0.toL2Bus.snoop_fanout::samples 5250259 # Request fanout histogram
1561system.cpu0.toL2Bus.snoop_fanout::mean 1.213502 # Request fanout histogram
1562system.cpu0.toL2Bus.snoop_fanout::stdev 0.409779 # Request fanout histogram

1539system.cpu0.toL2Bus.snoop_filter.tot_requests 3900428 # Total number of requests made to the snoop filter.
1540system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1972103 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1541system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 30395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1542system.cpu0.toL2Bus.snoop_filter.tot_snoops 166078 # Total number of snoops made to the snoop filter.
1543system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165928 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1544system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 150 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1545system.cpu0.toL2Bus.trans_dist::ReadReq 98608 # Transaction distribution
1546system.cpu0.toL2Bus.trans_dist::ReadResp 1819240 # Transaction distribution
1547system.cpu0.toL2Bus.trans_dist::WriteReq 16709 # Transaction distribution
1548system.cpu0.toL2Bus.trans_dist::WriteResp 16709 # Transaction distribution
1549system.cpu0.toL2Bus.trans_dist::Writeback 685334 # Transaction distribution
1550system.cpu0.toL2Bus.trans_dist::CleanEvict 1450937 # Transaction distribution
1551system.cpu0.toL2Bus.trans_dist::HardPFReq 287419 # Transaction distribution
1552system.cpu0.toL2Bus.trans_dist::UpgradeReq 90627 # Transaction distribution
1553system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43495 # Transaction distribution
1554system.cpu0.toL2Bus.trans_dist::UpgradeResp 114961 # Transaction distribution
1555system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution
1556system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution
1557system.cpu0.toL2Bus.trans_dist::ReadExReq 273601 # Transaction distribution
1558system.cpu0.toL2Bus.trans_dist::ReadExResp 270191 # Transaction distribution
1559system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1201355 # Transaction distribution
1560system.cpu0.toL2Bus.trans_dist::ReadSharedReq 557036 # Transaction distribution
1561system.cpu0.toL2Bus.trans_dist::InvalidateReq 3216 # Transaction distribution
1562system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3585963 # Packet count per connected master and slave (bytes)
1563system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2443651 # Packet count per connected master and slave (bytes)
1564system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28820 # Packet count per connected master and slave (bytes)
1565system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 110863 # Packet count per connected master and slave (bytes)
1566system.cpu0.toL2Bus.pkt_count::total 6169297 # Packet count per connected master and slave (bytes)
1567system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76933952 # Cumulative packet size per connected master and slave (bytes)
1568system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82016191 # Cumulative packet size per connected master and slave (bytes)
1569system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49524 # Cumulative packet size per connected master and slave (bytes)
1570system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 198724 # Cumulative packet size per connected master and slave (bytes)
1571system.cpu0.toL2Bus.pkt_size::total 159198391 # Cumulative packet size per connected master and slave (bytes)
1572system.cpu0.toL2Bus.snoops 860528 # Total snoops (count)
1573system.cpu0.toL2Bus.snoop_fanout::samples 4738789 # Request fanout histogram
1574system.cpu0.toL2Bus.snoop_fanout::mean 0.052471 # Request fanout histogram
1575system.cpu0.toL2Bus.snoop_fanout::stdev 0.223116 # Request fanout histogram

1563system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1576system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1564system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1565system.cpu0.toL2Bus.snoop_fanout::1 4129320 78.65% 78.65% # Request fanout histogram
1566system.cpu0.toL2Bus.snoop_fanout::2 1120939 21.35% 100.00% # Request fanout histogram

1577system.cpu0.toL2Bus.snoop_fanout::0 4490292 94.76% 94.76% # Request fanout histogram
1578system.cpu0.toL2Bus.snoop_fanout::1 248347 5.24% 100.00% # Request fanout histogram
1579system.cpu0.toL2Bus.snoop_fanout::2 150 0.00% 100.00% # Request fanout histogram

1567system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1580system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1568system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

1581system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram

1569system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

1582system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

1570system.cpu0.toL2Bus.snoop_fanout::total 5250259 # Request fanout histogram
1571system.cpu0.toL2Bus.reqLayer0.occupancy 2631653442 # Layer occupancy (ticks)

1583system.cpu0.toL2Bus.snoop_fanout::total 4738789 # Request fanout histogram
1584system.cpu0.toL2Bus.reqLayer0.occupancy 2495889948 # Layer occupancy (ticks)

1572system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)

1585system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)

1573system.cpu0.toL2Bus.snoopLayer0.occupancy 114940499 # Layer occupancy (ticks)

1586system.cpu0.toL2Bus.snoopLayer0.occupancy 112738429 # Layer occupancy (ticks)

1574system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

1587system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

1575system.cpu0.toL2Bus.respLayer0.occupancy 1900515323 # Layer occupancy (ticks)

1588system.cpu0.toL2Bus.respLayer0.occupancy 1805438687 # Layer occupancy (ticks)

1576system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1589system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1577system.cpu0.toL2Bus.respLayer1.occupancy 1221760496 # Layer occupancy (ticks)

1590system.cpu0.toL2Bus.respLayer1.occupancy 1156413493 # Layer occupancy (ticks)

1578system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

1591system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

1579system.cpu0.toL2Bus.respLayer2.occupancy 16493992 # Layer occupancy (ticks)

1592system.cpu0.toL2Bus.respLayer2.occupancy 16448481 # Layer occupancy (ticks)

1580system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)

1593system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)

1581system.cpu0.toL2Bus.respLayer3.occupancy 64044457 # Layer occupancy (ticks)

1594system.cpu0.toL2Bus.respLayer3.occupancy 61214934 # Layer occupancy (ticks)

1582system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

1595system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

1583system.cpu1.branchPred.lookups 33870827 # Number of BP lookups
1584system.cpu1.branchPred.condPredicted 11547618 # Number of conditional branches predicted
1585system.cpu1.branchPred.condIncorrect 303923 # Number of conditional branches incorrect
1586system.cpu1.branchPred.BTBLookups 18735544 # Number of BTB lookups
1587system.cpu1.branchPred.BTBHits 14949091 # Number of BTB hits

1596system.cpu1.branchPred.lookups 35362528 # Number of BP lookups
1597system.cpu1.branchPred.condPredicted 12650645 # Number of conditional branches predicted
1598system.cpu1.branchPred.condIncorrect 376011 # Number of conditional branches incorrect
1599system.cpu1.branchPred.BTBLookups 19640345 # Number of BTB lookups
1600system.cpu1.branchPred.BTBHits 15643376 # Number of BTB hits

1588system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

1601system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

1589system.cpu1.branchPred.BTBHitPct 79.790002 # BTB Hit Percentage
1590system.cpu1.branchPred.usedRAS 12480037 # Number of times the RAS was used to get a target.
1591system.cpu1.branchPred.RASInCorrect 7268 # Number of incorrect RAS predictions.

1602system.cpu1.branchPred.BTBHitPct 79.649191 # BTB Hit Percentage
1603system.cpu1.branchPred.usedRAS 12652559 # Number of times the RAS was used to get a target.
1604system.cpu1.branchPred.RASInCorrect 10779 # Number of incorrect RAS predictions.

1592system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1593system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1594system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1595system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1596system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1597system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1598system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1599system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1613system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1614system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1615system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1616system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1617system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1618system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1619system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1620system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

1605system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1606system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1607system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1608system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1609system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1610system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1611system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1612system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1626system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1627system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1628system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1629system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1630system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1631system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1632system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1633system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

1621system.cpu1.dtb.walker.walks 21101 # Table walker walks requested
1622system.cpu1.dtb.walker.walksShort 21101 # Table walker walks initiated with short descriptors
1623system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8660 # Level at which table walker walks with short descriptors terminate
1624system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5796 # Level at which table walker walks with short descriptors terminate
1625system.cpu1.dtb.walker.walksSquashedBefore 6645 # Table walks squashed before starting
1626system.cpu1.dtb.walker.walkWaitTime::samples 14456 # Table walker wait (enqueue to first request) latency
1627system.cpu1.dtb.walker.walkWaitTime::mean 508.058937 # Table walker wait (enqueue to first request) latency
1628system.cpu1.dtb.walker.walkWaitTime::stdev 2886.331667 # Table walker wait (enqueue to first request) latency
1629system.cpu1.dtb.walker.walkWaitTime::0-4095 13910 96.22% 96.22% # Table walker wait (enqueue to first request) latency
1630system.cpu1.dtb.walker.walkWaitTime::4096-8191 137 0.95% 97.17% # Table walker wait (enqueue to first request) latency
1631system.cpu1.dtb.walker.walkWaitTime::8192-12287 242 1.67% 98.84% # Table walker wait (enqueue to first request) latency
1632system.cpu1.dtb.walker.walkWaitTime::12288-16383 68 0.47% 99.32% # Table walker wait (enqueue to first request) latency
1633system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.14% 99.45% # Table walker wait (enqueue to first request) latency
1634system.cpu1.dtb.walker.walkWaitTime::20480-24575 12 0.08% 99.54% # Table walker wait (enqueue to first request) latency
1635system.cpu1.dtb.walker.walkWaitTime::24576-28671 37 0.26% 99.79% # Table walker wait (enqueue to first request) latency
1636system.cpu1.dtb.walker.walkWaitTime::28672-32767 11 0.08% 99.87% # Table walker wait (enqueue to first request) latency
1637system.cpu1.dtb.walker.walkWaitTime::32768-36863 15 0.10% 99.97% # Table walker wait (enqueue to first request) latency
1638system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency

1634system.cpu1.dtb.walker.walks 24283 # Table walker walks requested
1635system.cpu1.dtb.walker.walksShort 24283 # Table walker walks initiated with short descriptors
1636system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11247 # Level at which table walker walks with short descriptors terminate
1637system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5966 # Level at which table walker walks with short descriptors terminate
1638system.cpu1.dtb.walker.walksSquashedBefore 7070 # Table walks squashed before starting
1639system.cpu1.dtb.walker.walkWaitTime::samples 17213 # Table walker wait (enqueue to first request) latency
1640system.cpu1.dtb.walker.walkWaitTime::mean 473.798873 # Table walker wait (enqueue to first request) latency
1641system.cpu1.dtb.walker.walkWaitTime::stdev 2831.806000 # Table walker wait (enqueue to first request) latency
1642system.cpu1.dtb.walker.walkWaitTime::0-4095 16574 96.29% 96.29% # Table walker wait (enqueue to first request) latency
1643system.cpu1.dtb.walker.walkWaitTime::4096-8191 219 1.27% 97.56% # Table walker wait (enqueue to first request) latency
1644system.cpu1.dtb.walker.walkWaitTime::8192-12287 229 1.33% 98.89% # Table walker wait (enqueue to first request) latency
1645system.cpu1.dtb.walker.walkWaitTime::12288-16383 75 0.44% 99.33% # Table walker wait (enqueue to first request) latency
1646system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.44% # Table walker wait (enqueue to first request) latency
1647system.cpu1.dtb.walker.walkWaitTime::20480-24575 24 0.14% 99.58% # Table walker wait (enqueue to first request) latency
1648system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.04% 99.62% # Table walker wait (enqueue to first request) latency
1649system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.25% 99.87% # Table walker wait (enqueue to first request) latency
1650system.cpu1.dtb.walker.walkWaitTime::32768-36863 17 0.10% 99.97% # Table walker wait (enqueue to first request) latency
1651system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.99% # Table walker wait (enqueue to first request) latency

1639system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency

1652system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency

1640system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1641system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1642system.cpu1.dtb.walker.walkWaitTime::total 14456 # Table walker wait (enqueue to first request) latency
1643system.cpu1.dtb.walker.walkCompletionTime::samples 5194 # Table walker service (enqueue to completion) latency
1644system.cpu1.dtb.walker.walkCompletionTime::mean 9424.913362 # Table walker service (enqueue to completion) latency
1645system.cpu1.dtb.walker.walkCompletionTime::gmean 8003.762670 # Table walker service (enqueue to completion) latency
1646system.cpu1.dtb.walker.walkCompletionTime::stdev 6175.333367 # Table walker service (enqueue to completion) latency
1647system.cpu1.dtb.walker.walkCompletionTime::0-8191 2569 49.46% 49.46% # Table walker service (enqueue to completion) latency
1648system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2132 41.05% 90.51% # Table walker service (enqueue to completion) latency
1649system.cpu1.dtb.walker.walkCompletionTime::16384-24575 361 6.95% 97.46% # Table walker service (enqueue to completion) latency
1650system.cpu1.dtb.walker.walkCompletionTime::24576-32767 99 1.91% 99.36% # Table walker service (enqueue to completion) latency
1651system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.06% 99.42% # Table walker service (enqueue to completion) latency
1652system.cpu1.dtb.walker.walkCompletionTime::40960-49151 27 0.52% 99.94% # Table walker service (enqueue to completion) latency
1653system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency
1654system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
1655system.cpu1.dtb.walker.walkCompletionTime::total 5194 # Table walker service (enqueue to completion) latency
1656system.cpu1.dtb.walker.walksPending::samples 72058045764 # Table walker pending requests distribution
1657system.cpu1.dtb.walker.walksPending::mean 0.162272 # Table walker pending requests distribution
1658system.cpu1.dtb.walker.walksPending::stdev 0.372420 # Table walker pending requests distribution
1659system.cpu1.dtb.walker.walksPending::0 60402096044 83.82% 83.82% # Table walker pending requests distribution
1660system.cpu1.dtb.walker.walksPending::1 11637981720 16.15% 99.98% # Table walker pending requests distribution
1661system.cpu1.dtb.walker.walksPending::2 11426500 0.02% 99.99% # Table walker pending requests distribution
1662system.cpu1.dtb.walker.walksPending::3 2950500 0.00% 100.00% # Table walker pending requests distribution
1663system.cpu1.dtb.walker.walksPending::4 950000 0.00% 100.00% # Table walker pending requests distribution
1664system.cpu1.dtb.walker.walksPending::5 753000 0.00% 100.00% # Table walker pending requests distribution
1665system.cpu1.dtb.walker.walksPending::6 773000 0.00% 100.00% # Table walker pending requests distribution
1666system.cpu1.dtb.walker.walksPending::7 312500 0.00% 100.00% # Table walker pending requests distribution
1667system.cpu1.dtb.walker.walksPending::8 161500 0.00% 100.00% # Table walker pending requests distribution
1668system.cpu1.dtb.walker.walksPending::9 148500 0.00% 100.00% # Table walker pending requests distribution
1669system.cpu1.dtb.walker.walksPending::10 75000 0.00% 100.00% # Table walker pending requests distribution
1670system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution
1671system.cpu1.dtb.walker.walksPending::12 134500 0.00% 100.00% # Table walker pending requests distribution
1672system.cpu1.dtb.walker.walksPending::13 51500 0.00% 100.00% # Table walker pending requests distribution
1673system.cpu1.dtb.walker.walksPending::14 27000 0.00% 100.00% # Table walker pending requests distribution
1674system.cpu1.dtb.walker.walksPending::15 156500 0.00% 100.00% # Table walker pending requests distribution
1675system.cpu1.dtb.walker.walksPending::total 72058045764 # Table walker pending requests distribution
1676system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.91% 75.91% # Table walker page sizes translated
1677system.cpu1.dtb.walker.walkPageSizes::1M 606 24.09% 100.00% # Table walker page sizes translated
1678system.cpu1.dtb.walker.walkPageSizes::total 2516 # Table walker page sizes translated
1679system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21101 # Table walker requests started/completed, data/inst

1653system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1654system.cpu1.dtb.walker.walkWaitTime::total 17213 # Table walker wait (enqueue to first request) latency
1655system.cpu1.dtb.walker.walkCompletionTime::samples 5394 # Table walker service (enqueue to completion) latency
1656system.cpu1.dtb.walker.walkCompletionTime::mean 10976.177234 # Table walker service (enqueue to completion) latency
1657system.cpu1.dtb.walker.walkCompletionTime::gmean 9365.976538 # Table walker service (enqueue to completion) latency
1658system.cpu1.dtb.walker.walkCompletionTime::stdev 8403.035892 # Table walker service (enqueue to completion) latency
1659system.cpu1.dtb.walker.walkCompletionTime::0-16383 4813 89.23% 89.23% # Table walker service (enqueue to completion) latency
1660system.cpu1.dtb.walker.walkCompletionTime::16384-32767 520 9.64% 98.87% # Table walker service (enqueue to completion) latency
1661system.cpu1.dtb.walker.walkCompletionTime::32768-49151 49 0.91% 99.78% # Table walker service (enqueue to completion) latency
1662system.cpu1.dtb.walker.walkCompletionTime::49152-65535 4 0.07% 99.85% # Table walker service (enqueue to completion) latency
1663system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.06% 99.91% # Table walker service (enqueue to completion) latency
1664system.cpu1.dtb.walker.walkCompletionTime::147456-163839 4 0.07% 99.98% # Table walker service (enqueue to completion) latency
1665system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
1666system.cpu1.dtb.walker.walkCompletionTime::total 5394 # Table walker service (enqueue to completion) latency
1667system.cpu1.dtb.walker.walksPending::samples 75766592176 # Table walker pending requests distribution
1668system.cpu1.dtb.walker.walksPending::mean 0.320474 # Table walker pending requests distribution
1669system.cpu1.dtb.walker.walksPending::stdev 0.469554 # Table walker pending requests distribution
1670system.cpu1.dtb.walker.walksPending::0 51526613188 68.01% 68.01% # Table walker pending requests distribution
1671system.cpu1.dtb.walker.walksPending::1 24219637488 31.97% 99.97% # Table walker pending requests distribution
1672system.cpu1.dtb.walker.walksPending::2 12480500 0.02% 99.99% # Table walker pending requests distribution
1673system.cpu1.dtb.walker.walksPending::3 3766000 0.00% 99.99% # Table walker pending requests distribution
1674system.cpu1.dtb.walker.walksPending::4 1197500 0.00% 100.00% # Table walker pending requests distribution
1675system.cpu1.dtb.walker.walksPending::5 815500 0.00% 100.00% # Table walker pending requests distribution
1676system.cpu1.dtb.walker.walksPending::6 985500 0.00% 100.00% # Table walker pending requests distribution
1677system.cpu1.dtb.walker.walksPending::7 293500 0.00% 100.00% # Table walker pending requests distribution
1678system.cpu1.dtb.walker.walksPending::8 146000 0.00% 100.00% # Table walker pending requests distribution
1679system.cpu1.dtb.walker.walksPending::9 224500 0.00% 100.00% # Table walker pending requests distribution
1680system.cpu1.dtb.walker.walksPending::10 83500 0.00% 100.00% # Table walker pending requests distribution
1681system.cpu1.dtb.walker.walksPending::11 76500 0.00% 100.00% # Table walker pending requests distribution
1682system.cpu1.dtb.walker.walksPending::12 137000 0.00% 100.00% # Table walker pending requests distribution
1683system.cpu1.dtb.walker.walksPending::13 18000 0.00% 100.00% # Table walker pending requests distribution
1684system.cpu1.dtb.walker.walksPending::14 22000 0.00% 100.00% # Table walker pending requests distribution
1685system.cpu1.dtb.walker.walksPending::15 95500 0.00% 100.00% # Table walker pending requests distribution
1686system.cpu1.dtb.walker.walksPending::total 75766592176 # Table walker pending requests distribution
1687system.cpu1.dtb.walker.walkPageSizes::4K 1932 75.85% 75.85% # Table walker page sizes translated
1688system.cpu1.dtb.walker.walkPageSizes::1M 615 24.15% 100.00% # Table walker page sizes translated
1689system.cpu1.dtb.walker.walkPageSizes::total 2547 # Table walker page sizes translated
1690system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24283 # Table walker requests started/completed, data/inst

1680system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst

1691system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst

1681system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21101 # Table walker requests started/completed, data/inst
1682system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2516 # Table walker requests started/completed, data/inst

1692system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24283 # Table walker requests started/completed, data/inst
1693system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2547 # Table walker requests started/completed, data/inst

1683system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst

1694system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst

1684system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2516 # Table walker requests started/completed, data/inst
1685system.cpu1.dtb.walker.walkRequestOrigin::total 23617 # Table walker requests started/completed, data/inst

1695system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2547 # Table walker requests started/completed, data/inst
1696system.cpu1.dtb.walker.walkRequestOrigin::total 26830 # Table walker requests started/completed, data/inst

1686system.cpu1.dtb.inst_hits 0 # ITB inst hits
1687system.cpu1.dtb.inst_misses 0 # ITB inst misses

1697system.cpu1.dtb.inst_hits 0 # ITB inst hits
1698system.cpu1.dtb.inst_misses 0 # ITB inst misses

1688system.cpu1.dtb.read_hits 10151644 # DTB read hits
1689system.cpu1.dtb.read_misses 18305 # DTB read misses
1690system.cpu1.dtb.write_hits 6523716 # DTB write hits
1691system.cpu1.dtb.write_misses 2796 # DTB write misses

1699system.cpu1.dtb.read_hits 11209013 # DTB read hits
1700system.cpu1.dtb.read_misses 21079 # DTB read misses
1701system.cpu1.dtb.write_hits 7325054 # DTB write hits
1702system.cpu1.dtb.write_misses 3204 # DTB write misses

1692system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1693system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1694system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1695system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID

1703system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1704system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1705system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1706system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID

1696system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
1697system.cpu1.dtb.align_faults 50 # Number of TLB faults due to alignment restrictions
1698system.cpu1.dtb.prefetch_faults 456 # Number of TLB faults due to prefetch

1707system.cpu1.dtb.flush_entries 2001 # Number of entries that have been flushed from TLB
1708system.cpu1.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions
1709system.cpu1.dtb.prefetch_faults 612 # Number of TLB faults due to prefetch

1699system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions

1710system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions

1700system.cpu1.dtb.perms_faults 384 # Number of TLB faults due to permissions restrictions
1701system.cpu1.dtb.read_accesses 10169949 # DTB read accesses
1702system.cpu1.dtb.write_accesses 6526512 # DTB write accesses

1711system.cpu1.dtb.perms_faults 367 # Number of TLB faults due to permissions restrictions
1712system.cpu1.dtb.read_accesses 11230092 # DTB read accesses
1713system.cpu1.dtb.write_accesses 7328258 # DTB write accesses

1703system.cpu1.dtb.inst_accesses 0 # ITB inst accesses

1714system.cpu1.dtb.inst_accesses 0 # ITB inst accesses

1704system.cpu1.dtb.hits 16675360 # DTB hits
1705system.cpu1.dtb.misses 21101 # DTB misses
1706system.cpu1.dtb.accesses 16696461 # DTB accesses

1715system.cpu1.dtb.hits 18534067 # DTB hits
1716system.cpu1.dtb.misses 24283 # DTB misses
1717system.cpu1.dtb.accesses 18558350 # DTB accesses

1707system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1709system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1710system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1711system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1712system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1713system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1714system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1728system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1729system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1730system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1731system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1732system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1733system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1734system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1735system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

1718system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1719system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1720system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1721system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1722system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1723system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1724system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1725system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1739system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1740system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1741system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1742system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1743system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1744system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1745system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1746system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

1736system.cpu1.itb.walker.walks 6899 # Table walker walks requested
1737system.cpu1.itb.walker.walksShort 6899 # Table walker walks initiated with short descriptors
1738system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4113 # Level at which table walker walks with short descriptors terminate
1739system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2729 # Level at which table walker walks with short descriptors terminate
1740system.cpu1.itb.walker.walksSquashedBefore 57 # Table walks squashed before starting
1741system.cpu1.itb.walker.walkWaitTime::samples 6842 # Table walker wait (enqueue to first request) latency
1742system.cpu1.itb.walker.walkWaitTime::mean 198.333821 # Table walker wait (enqueue to first request) latency
1743system.cpu1.itb.walker.walkWaitTime::stdev 1594.183488 # Table walker wait (enqueue to first request) latency
1744system.cpu1.itb.walker.walkWaitTime::0-4095 6730 98.36% 98.36% # Table walker wait (enqueue to first request) latency
1745system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.86% 99.23% # Table walker wait (enqueue to first request) latency
1746system.cpu1.itb.walker.walkWaitTime::8192-12287 21 0.31% 99.53% # Table walker wait (enqueue to first request) latency
1747system.cpu1.itb.walker.walkWaitTime::12288-16383 14 0.20% 99.74% # Table walker wait (enqueue to first request) latency
1748system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency
1749system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.91% # Table walker wait (enqueue to first request) latency
1750system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.97% # Table walker wait (enqueue to first request) latency
1751system.cpu1.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1752system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1753system.cpu1.itb.walker.walkWaitTime::total 6842 # Table walker wait (enqueue to first request) latency
1754system.cpu1.itb.walker.walkCompletionTime::samples 1221 # Table walker service (enqueue to completion) latency
1755system.cpu1.itb.walker.walkCompletionTime::mean 10738.329238 # Table walker service (enqueue to completion) latency
1756system.cpu1.itb.walker.walkCompletionTime::gmean 9530.760976 # Table walker service (enqueue to completion) latency
1757system.cpu1.itb.walker.walkCompletionTime::stdev 5854.425690 # Table walker service (enqueue to completion) latency
1758system.cpu1.itb.walker.walkCompletionTime::0-4095 35 2.87% 2.87% # Table walker service (enqueue to completion) latency
1759system.cpu1.itb.walker.walkCompletionTime::4096-8191 374 30.63% 33.50% # Table walker service (enqueue to completion) latency
1760system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 40.70% 74.20% # Table walker service (enqueue to completion) latency
1761system.cpu1.itb.walker.walkCompletionTime::12288-16383 243 19.90% 94.10% # Table walker service (enqueue to completion) latency
1762system.cpu1.itb.walker.walkCompletionTime::16384-20479 3 0.25% 94.35% # Table walker service (enqueue to completion) latency
1763system.cpu1.itb.walker.walkCompletionTime::20480-24575 9 0.74% 95.09% # Table walker service (enqueue to completion) latency
1764system.cpu1.itb.walker.walkCompletionTime::24576-28671 37 3.03% 98.12% # Table walker service (enqueue to completion) latency
1765system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.31% 99.43% # Table walker service (enqueue to completion) latency
1766system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.16% 99.59% # Table walker service (enqueue to completion) latency
1767system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.25% 99.84% # Table walker service (enqueue to completion) latency
1768system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
1769system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
1770system.cpu1.itb.walker.walkCompletionTime::total 1221 # Table walker service (enqueue to completion) latency
1771system.cpu1.itb.walker.walksPending::samples 11897679120 # Table walker pending requests distribution
1772system.cpu1.itb.walker.walksPending::mean 0.980675 # Table walker pending requests distribution
1773system.cpu1.itb.walker.walksPending::stdev 0.137806 # Table walker pending requests distribution
1774system.cpu1.itb.walker.walksPending::0 230157764 1.93% 1.93% # Table walker pending requests distribution
1775system.cpu1.itb.walker.walksPending::1 11667291856 98.06% 100.00% # Table walker pending requests distribution
1776system.cpu1.itb.walker.walksPending::2 229500 0.00% 100.00% # Table walker pending requests distribution
1777system.cpu1.itb.walker.walksPending::total 11897679120 # Table walker pending requests distribution
1778system.cpu1.itb.walker.walkPageSizes::4K 997 85.65% 85.65% # Table walker page sizes translated
1779system.cpu1.itb.walker.walkPageSizes::1M 167 14.35% 100.00% # Table walker page sizes translated
1780system.cpu1.itb.walker.walkPageSizes::total 1164 # Table walker page sizes translated

1747system.cpu1.itb.walker.walks 6861 # Table walker walks requested
1748system.cpu1.itb.walker.walksShort 6861 # Table walker walks initiated with short descriptors
1749system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4105 # Level at which table walker walks with short descriptors terminate
1750system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2676 # Level at which table walker walks with short descriptors terminate
1751system.cpu1.itb.walker.walksSquashedBefore 80 # Table walks squashed before starting
1752system.cpu1.itb.walker.walkWaitTime::samples 6781 # Table walker wait (enqueue to first request) latency
1753system.cpu1.itb.walker.walkWaitTime::mean 216.855921 # Table walker wait (enqueue to first request) latency
1754system.cpu1.itb.walker.walkWaitTime::stdev 1684.274104 # Table walker wait (enqueue to first request) latency
1755system.cpu1.itb.walker.walkWaitTime::0-4095 6669 98.35% 98.35% # Table walker wait (enqueue to first request) latency
1756system.cpu1.itb.walker.walkWaitTime::4096-8191 39 0.58% 98.92% # Table walker wait (enqueue to first request) latency
1757system.cpu1.itb.walker.walkWaitTime::8192-12287 44 0.65% 99.57% # Table walker wait (enqueue to first request) latency
1758system.cpu1.itb.walker.walkWaitTime::12288-16383 12 0.18% 99.75% # Table walker wait (enqueue to first request) latency
1759system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.82% # Table walker wait (enqueue to first request) latency
1760system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.90% # Table walker wait (enqueue to first request) latency
1761system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency
1762system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
1763system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency
1764system.cpu1.itb.walker.walkWaitTime::total 6781 # Table walker wait (enqueue to first request) latency
1765system.cpu1.itb.walker.walkCompletionTime::samples 1249 # Table walker service (enqueue to completion) latency
1766system.cpu1.itb.walker.walkCompletionTime::mean 11729.383507 # Table walker service (enqueue to completion) latency
1767system.cpu1.itb.walker.walkCompletionTime::gmean 10507.790303 # Table walker service (enqueue to completion) latency
1768system.cpu1.itb.walker.walkCompletionTime::stdev 6381.189280 # Table walker service (enqueue to completion) latency
1769system.cpu1.itb.walker.walkCompletionTime::0-8191 353 28.26% 28.26% # Table walker service (enqueue to completion) latency
1770system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 65.17% 93.43% # Table walker service (enqueue to completion) latency
1771system.cpu1.itb.walker.walkCompletionTime::16384-24575 24 1.92% 95.36% # Table walker service (enqueue to completion) latency
1772system.cpu1.itb.walker.walkCompletionTime::24576-32767 32 2.56% 97.92% # Table walker service (enqueue to completion) latency
1773system.cpu1.itb.walker.walkCompletionTime::32768-40959 17 1.36% 99.28% # Table walker service (enqueue to completion) latency
1774system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.56% 99.84% # Table walker service (enqueue to completion) latency
1775system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
1776system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
1777system.cpu1.itb.walker.walkCompletionTime::total 1249 # Table walker service (enqueue to completion) latency
1778system.cpu1.itb.walker.walksPending::samples 15604919032 # Table walker pending requests distribution
1779system.cpu1.itb.walker.walksPending::mean 0.958751 # Table walker pending requests distribution
1780system.cpu1.itb.walker.walksPending::stdev 0.198933 # Table walker pending requests distribution
1781system.cpu1.itb.walker.walksPending::0 643875264 4.13% 4.13% # Table walker pending requests distribution
1782system.cpu1.itb.walker.walksPending::1 14960875268 95.87% 100.00% # Table walker pending requests distribution
1783system.cpu1.itb.walker.walksPending::2 148500 0.00% 100.00% # Table walker pending requests distribution
1784system.cpu1.itb.walker.walksPending::3 20000 0.00% 100.00% # Table walker pending requests distribution
1785system.cpu1.itb.walker.walksPending::total 15604919032 # Table walker pending requests distribution
1786system.cpu1.itb.walker.walkPageSizes::4K 997 85.29% 85.29% # Table walker page sizes translated
1787system.cpu1.itb.walker.walkPageSizes::1M 172 14.71% 100.00% # Table walker page sizes translated
1788system.cpu1.itb.walker.walkPageSizes::total 1169 # Table walker page sizes translated

1781system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst

1789system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst

1782system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6899 # Table walker requests started/completed, data/inst
1783system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst

1790system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6861 # Table walker requests started/completed, data/inst
1791system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6861 # Table walker requests started/completed, data/inst

1784system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst

1792system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst

1785system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1164 # Table walker requests started/completed, data/inst
1786system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1164 # Table walker requests started/completed, data/inst
1787system.cpu1.itb.walker.walkRequestOrigin::total 8063 # Table walker requests started/completed, data/inst
1788system.cpu1.itb.inst_hits 43584522 # ITB inst hits
1789system.cpu1.itb.inst_misses 6899 # ITB inst misses

1793system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1169 # Table walker requests started/completed, data/inst
1794system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1169 # Table walker requests started/completed, data/inst
1795system.cpu1.itb.walker.walkRequestOrigin::total 8030 # Table walker requests started/completed, data/inst
1796system.cpu1.itb.inst_hits 45813094 # ITB inst hits
1797system.cpu1.itb.inst_misses 6861 # ITB inst misses

1790system.cpu1.itb.read_hits 0 # DTB read hits
1791system.cpu1.itb.read_misses 0 # DTB read misses
1792system.cpu1.itb.write_hits 0 # DTB write hits
1793system.cpu1.itb.write_misses 0 # DTB write misses
1794system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1795system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1796system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1797system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID

1798system.cpu1.itb.read_hits 0 # DTB read hits
1799system.cpu1.itb.read_misses 0 # DTB read misses
1800system.cpu1.itb.write_hits 0 # DTB write hits
1801system.cpu1.itb.write_misses 0 # DTB write misses
1802system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1803system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1804system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1805system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID

1798system.cpu1.itb.flush_entries 1193 # Number of entries that have been flushed from TLB

1806system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB

1799system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1800system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1801system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions

1807system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1808system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1809system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions

1802system.cpu1.itb.perms_faults 547 # Number of TLB faults due to permissions restrictions

1810system.cpu1.itb.perms_faults 526 # Number of TLB faults due to permissions restrictions

1803system.cpu1.itb.read_accesses 0 # DTB read accesses
1804system.cpu1.itb.write_accesses 0 # DTB write accesses

1811system.cpu1.itb.read_accesses 0 # DTB read accesses
1812system.cpu1.itb.write_accesses 0 # DTB write accesses

1805system.cpu1.itb.inst_accesses 43591421 # ITB inst accesses
1806system.cpu1.itb.hits 43584522 # DTB hits
1807system.cpu1.itb.misses 6899 # DTB misses
1808system.cpu1.itb.accesses 43591421 # DTB accesses
1809system.cpu1.numCycles 105332010 # number of cpu cycles simulated

1813system.cpu1.itb.inst_accesses 45819955 # ITB inst accesses
1814system.cpu1.itb.hits 45813094 # DTB hits
1815system.cpu1.itb.misses 6861 # DTB misses
1816system.cpu1.itb.accesses 45819955 # DTB accesses
1817system.cpu1.numCycles 115872528 # number of cpu cycles simulated

1810system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1811system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed

1818system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1819system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed

1812system.cpu1.fetch.icacheStallCycles 10132151 # Number of cycles fetch is stalled on an Icache miss
1813system.cpu1.fetch.Insts 108981973 # Number of instructions fetch has processed
1814system.cpu1.fetch.Branches 33870827 # Number of branches that fetch encountered
1815system.cpu1.fetch.predictedBranches 27429128 # Number of branches that fetch has predicted taken
1816system.cpu1.fetch.Cycles 92017725 # Number of cycles fetch has run and was not squashing or blocked
1817system.cpu1.fetch.SquashCycles 3770452 # Number of cycles fetch has spent squashing
1818system.cpu1.fetch.TlbCycles 88186 # Number of cycles fetch has spent waiting for tlb
1819system.cpu1.fetch.MiscStallCycles 36483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1820system.cpu1.fetch.PendingTrapStallCycles 195284 # Number of stall cycles due to pending traps
1821system.cpu1.fetch.PendingQuiesceStallCycles 298638 # Number of stall cycles due to pending quiesce instructions
1822system.cpu1.fetch.IcacheWaitRetryStallCycles 22598 # Number of stall cycles due to full MSHR
1823system.cpu1.fetch.CacheLines 43583923 # Number of cache lines fetched
1824system.cpu1.fetch.IcacheSquashes 117443 # Number of outstanding Icache misses that were squashed
1825system.cpu1.fetch.ItlbSquashes 2417 # Number of outstanding ITLB misses that were squashed
1826system.cpu1.fetch.rateDist::samples 104676291 # Number of instructions fetched each cycle (Total)
1827system.cpu1.fetch.rateDist::mean 1.289820 # Number of instructions fetched each cycle (Total)
1828system.cpu1.fetch.rateDist::stdev 1.339564 # Number of instructions fetched each cycle (Total)

1820system.cpu1.fetch.icacheStallCycles 11244647 # Number of cycles fetch is stalled on an Icache miss
1821system.cpu1.fetch.Insts 115696053 # Number of instructions fetch has processed
1822system.cpu1.fetch.Branches 35362528 # Number of branches that fetch encountered
1823system.cpu1.fetch.predictedBranches 28295935 # Number of branches that fetch has predicted taken
1824system.cpu1.fetch.Cycles 100513645 # Number of cycles fetch has run and was not squashing or blocked
1825system.cpu1.fetch.SquashCycles 3955668 # Number of cycles fetch has spent squashing
1826system.cpu1.fetch.TlbCycles 92958 # Number of cycles fetch has spent waiting for tlb
1827system.cpu1.fetch.MiscStallCycles 43827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1828system.cpu1.fetch.PendingTrapStallCycles 218813 # Number of stall cycles due to pending traps
1829system.cpu1.fetch.PendingQuiesceStallCycles 324785 # Number of stall cycles due to pending quiesce instructions
1830system.cpu1.fetch.IcacheWaitRetryStallCycles 35760 # Number of stall cycles due to full MSHR
1831system.cpu1.fetch.CacheLines 45812479 # Number of cache lines fetched
1832system.cpu1.fetch.IcacheSquashes 133633 # Number of outstanding Icache misses that were squashed
1833system.cpu1.fetch.ItlbSquashes 2410 # Number of outstanding ITLB misses that were squashed
1834system.cpu1.fetch.rateDist::samples 114452269 # Number of instructions fetched each cycle (Total)
1835system.cpu1.fetch.rateDist::mean 1.250587 # Number of instructions fetched each cycle (Total)
1836system.cpu1.fetch.rateDist::stdev 1.333322 # Number of instructions fetched each cycle (Total)

1829system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1837system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

1830system.cpu1.fetch.rateDist::0 47827120 45.69% 45.69% # Number of instructions fetched each cycle (Total)
1831system.cpu1.fetch.rateDist::1 14002469 13.38% 59.07% # Number of instructions fetched each cycle (Total)
1832system.cpu1.fetch.rateDist::2 7529046 7.19% 66.26% # Number of instructions fetched each cycle (Total)
1833system.cpu1.fetch.rateDist::3 35317656 33.74% 100.00% # Number of instructions fetched each cycle (Total)

1838system.cpu1.fetch.rateDist::0 53787165 47.00% 47.00% # Number of instructions fetched each cycle (Total)
1839system.cpu1.fetch.rateDist::1 15397458 13.45% 60.45% # Number of instructions fetched each cycle (Total)
1840system.cpu1.fetch.rateDist::2 8067873 7.05% 67.50% # Number of instructions fetched each cycle (Total)
1841system.cpu1.fetch.rateDist::3 37199773 32.50% 100.00% # Number of instructions fetched each cycle (Total)

1834system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1835system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1836system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)

1842system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1843system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1844system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)

1837system.cpu1.fetch.rateDist::total 104676291 # Number of instructions fetched each cycle (Total)
1838system.cpu1.fetch.branchRate 0.321563 # Number of branch fetches per cycle
1839system.cpu1.fetch.rate 1.034652 # Number of inst fetches per cycle
1840system.cpu1.decode.IdleCycles 13137871 # Number of cycles decode is idle
1841system.cpu1.decode.BlockedCycles 61997568 # Number of cycles decode is blocked
1842system.cpu1.decode.RunCycles 26684640 # Number of cycles decode is running
1843system.cpu1.decode.UnblockCycles 1104927 # Number of cycles decode is unblocking
1844system.cpu1.decode.SquashCycles 1751285 # Number of cycles decode is squashing
1845system.cpu1.decode.BranchResolved 750757 # Number of times decode resolved a branch
1846system.cpu1.decode.BranchMispred 136902 # Number of times decode detected a branch misprediction
1847system.cpu1.decode.DecodedInsts 67935331 # Number of instructions handled by decode
1848system.cpu1.decode.SquashedInsts 1160131 # Number of squashed instructions handled by decode
1849system.cpu1.rename.SquashCycles 1751285 # Number of cycles rename is squashing
1850system.cpu1.rename.IdleCycles 17557644 # Number of cycles rename is idle
1851system.cpu1.rename.BlockCycles 2234457 # Number of cycles rename is blocking
1852system.cpu1.rename.serializeStallCycles 57207184 # count of cycles rename stalled for serializing inst
1853system.cpu1.rename.RunCycles 23346153 # Number of cycles rename is running
1854system.cpu1.rename.UnblockCycles 2579568 # Number of cycles rename is unblocking
1855system.cpu1.rename.RenamedInsts 55040039 # Number of instructions processed by rename
1856system.cpu1.rename.SquashedInsts 231549 # Number of squashed instructions processed by rename
1857system.cpu1.rename.ROBFullEvents 250107 # Number of times rename has blocked due to ROB full
1858system.cpu1.rename.IQFullEvents 36576 # Number of times rename has blocked due to IQ full
1859system.cpu1.rename.LQFullEvents 14638 # Number of times rename has blocked due to LQ full
1860system.cpu1.rename.SQFullEvents 1569614 # Number of times rename has blocked due to SQ full
1861system.cpu1.rename.RenamedOperands 54888875 # Number of destination operands rename has renamed
1862system.cpu1.rename.RenameLookups 259969011 # Number of register rename lookups that rename has made
1863system.cpu1.rename.int_rename_lookups 58535420 # Number of integer rename lookups
1864system.cpu1.rename.fp_rename_lookups 1673 # Number of floating rename lookups
1865system.cpu1.rename.CommittedMaps 52136282 # Number of HB maps that are committed
1866system.cpu1.rename.UndoneMaps 2752593 # Number of HB maps that are undone due to squashing
1867system.cpu1.rename.serializingInsts 1876398 # count of serializing insts renamed
1868system.cpu1.rename.tempSerializingInsts 1803595 # count of temporary serializing insts renamed
1869system.cpu1.rename.skidInsts 13068910 # count of insts added to the skid buffer
1870system.cpu1.memDep0.insertedLoads 10432997 # Number of loads inserted to the mem dependence unit.
1871system.cpu1.memDep0.insertedStores 6892596 # Number of stores inserted to the mem dependence unit.
1872system.cpu1.memDep0.conflictingLoads 625658 # Number of conflicting loads.
1873system.cpu1.memDep0.conflictingStores 847753 # Number of conflicting stores.
1874system.cpu1.iq.iqInstsAdded 54148527 # Number of instructions added to the IQ (excludes non-spec)
1875system.cpu1.iq.iqNonSpecInstsAdded 587967 # Number of non-speculative instructions added to the IQ
1876system.cpu1.iq.iqInstsIssued 53807238 # Number of instructions issued
1877system.cpu1.iq.iqSquashedInstsIssued 110933 # Number of squashed instructions issued
1878system.cpu1.iq.iqSquashedInstsExamined 3881118 # Number of squashed instructions iterated over during squash; mainly for profiling
1879system.cpu1.iq.iqSquashedOperandsExamined 5762517 # Number of squashed operands that are examined and possibly removed from graph
1880system.cpu1.iq.iqSquashedNonSpecRemoved 48708 # Number of squashed non-spec instructions that were removed
1881system.cpu1.iq.issued_per_cycle::samples 104676291 # Number of insts issued each cycle
1882system.cpu1.iq.issued_per_cycle::mean 0.514035 # Number of insts issued each cycle
1883system.cpu1.iq.issued_per_cycle::stdev 0.850765 # Number of insts issued each cycle

1845system.cpu1.fetch.rateDist::total 114452269 # Number of instructions fetched each cycle (Total)
1846system.cpu1.fetch.branchRate 0.305185 # Number of branch fetches per cycle
1847system.cpu1.fetch.rate 0.998477 # Number of inst fetches per cycle
1848system.cpu1.decode.IdleCycles 14331089 # Number of cycles decode is idle
1849system.cpu1.decode.BlockedCycles 67536075 # Number of cycles decode is blocked
1850system.cpu1.decode.RunCycles 29425449 # Number of cycles decode is running
1851system.cpu1.decode.UnblockCycles 1338809 # Number of cycles decode is unblocking
1852system.cpu1.decode.SquashCycles 1820847 # Number of cycles decode is squashing
1853system.cpu1.decode.BranchResolved 912295 # Number of times decode resolved a branch
1854system.cpu1.decode.BranchMispred 160061 # Number of times decode detected a branch misprediction
1855system.cpu1.decode.DecodedInsts 74627346 # Number of instructions handled by decode
1856system.cpu1.decode.SquashedInsts 1451044 # Number of squashed instructions handled by decode
1857system.cpu1.rename.SquashCycles 1820847 # Number of cycles rename is squashing
1858system.cpu1.rename.IdleCycles 19084331 # Number of cycles rename is idle
1859system.cpu1.rename.BlockCycles 2925531 # Number of cycles rename is blocking
1860system.cpu1.rename.serializeStallCycles 61205079 # count of cycles rename stalled for serializing inst
1861system.cpu1.rename.RunCycles 25977648 # Number of cycles rename is running
1862system.cpu1.rename.UnblockCycles 3438833 # Number of cycles rename is unblocking
1863system.cpu1.rename.RenamedInsts 61437487 # Number of instructions processed by rename
1864system.cpu1.rename.SquashedInsts 313811 # Number of squashed instructions processed by rename
1865system.cpu1.rename.ROBFullEvents 329328 # Number of times rename has blocked due to ROB full
1866system.cpu1.rename.IQFullEvents 50880 # Number of times rename has blocked due to IQ full
1867system.cpu1.rename.LQFullEvents 21104 # Number of times rename has blocked due to LQ full
1868system.cpu1.rename.SQFullEvents 2227690 # Number of times rename has blocked due to SQ full
1869system.cpu1.rename.RenamedOperands 61781071 # Number of destination operands rename has renamed
1870system.cpu1.rename.RenameLookups 288761968 # Number of register rename lookups that rename has made
1871system.cpu1.rename.int_rename_lookups 65715217 # Number of integer rename lookups
1872system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups
1873system.cpu1.rename.CommittedMaps 58198437 # Number of HB maps that are committed
1874system.cpu1.rename.UndoneMaps 3582634 # Number of HB maps that are undone due to squashing
1875system.cpu1.rename.serializingInsts 1923301 # count of serializing insts renamed
1876system.cpu1.rename.tempSerializingInsts 1845273 # count of temporary serializing insts renamed
1877system.cpu1.rename.skidInsts 13635165 # count of insts added to the skid buffer
1878system.cpu1.memDep0.insertedLoads 11552975 # Number of loads inserted to the mem dependence unit.
1879system.cpu1.memDep0.insertedStores 7780383 # Number of stores inserted to the mem dependence unit.
1880system.cpu1.memDep0.conflictingLoads 701343 # Number of conflicting loads.
1881system.cpu1.memDep0.conflictingStores 925146 # Number of conflicting stores.
1882system.cpu1.iq.iqInstsAdded 60392573 # Number of instructions added to the IQ (excludes non-spec)
1883system.cpu1.iq.iqNonSpecInstsAdded 653667 # Number of non-speculative instructions added to the IQ
1884system.cpu1.iq.iqInstsIssued 59853310 # Number of instructions issued
1885system.cpu1.iq.iqSquashedInstsIssued 146761 # Number of squashed instructions issued
1886system.cpu1.iq.iqSquashedInstsExamined 4556505 # Number of squashed instructions iterated over during squash; mainly for profiling
1887system.cpu1.iq.iqSquashedOperandsExamined 7374621 # Number of squashed operands that are examined and possibly removed from graph
1888system.cpu1.iq.iqSquashedNonSpecRemoved 54925 # Number of squashed non-spec instructions that were removed
1889system.cpu1.iq.issued_per_cycle::samples 114452269 # Number of insts issued each cycle
1890system.cpu1.iq.issued_per_cycle::mean 0.522954 # Number of insts issued each cycle
1891system.cpu1.iq.issued_per_cycle::stdev 0.862457 # Number of insts issued each cycle

1884system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1892system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

1885system.cpu1.iq.issued_per_cycle::0 71469096 68.28% 68.28% # Number of insts issued each cycle
1886system.cpu1.iq.issued_per_cycle::1 16529250 15.79% 84.07% # Number of insts issued each cycle
1887system.cpu1.iq.issued_per_cycle::2 13041841 12.46% 96.53% # Number of insts issued each cycle
1888system.cpu1.iq.issued_per_cycle::3 3350126 3.20% 99.73% # Number of insts issued each cycle
1889system.cpu1.iq.issued_per_cycle::4 285962 0.27% 100.00% # Number of insts issued each cycle
1890system.cpu1.iq.issued_per_cycle::5 16 0.00% 100.00% # Number of insts issued each cycle

1893system.cpu1.iq.issued_per_cycle::0 77949624 68.11% 68.11% # Number of insts issued each cycle
1894system.cpu1.iq.issued_per_cycle::1 17744881 15.50% 83.61% # Number of insts issued each cycle
1895system.cpu1.iq.issued_per_cycle::2 14511556 12.68% 96.29% # Number of insts issued each cycle
1896system.cpu1.iq.issued_per_cycle::3 3899540 3.41% 99.70% # Number of insts issued each cycle
1897system.cpu1.iq.issued_per_cycle::4 346643 0.30% 100.00% # Number of insts issued each cycle
1898system.cpu1.iq.issued_per_cycle::5 25 0.00% 100.00% # Number of insts issued each cycle

1891system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1892system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1893system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1894system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1895system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1896system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle

1899system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1900system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1901system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1902system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1903system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1904system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle

1897system.cpu1.iq.issued_per_cycle::total 104676291 # Number of insts issued each cycle

1905system.cpu1.iq.issued_per_cycle::total 114452269 # Number of insts issued each cycle

1898system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1906system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

1899system.cpu1.iq.fu_full::IntAlu 2912792 45.01% 45.01% # attempts to use FU when none available
1900system.cpu1.iq.fu_full::IntMult 674 0.01% 45.02% # attempts to use FU when none available
1901system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.02% # attempts to use FU when none available
1902system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.02% # attempts to use FU when none available
1903system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.02% # attempts to use FU when none available
1904system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.02% # attempts to use FU when none available
1905system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.02% # attempts to use FU when none available
1906system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.02% # attempts to use FU when none available
1907system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.02% # attempts to use FU when none available
1908system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.02% # attempts to use FU when none available
1909system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.02% # attempts to use FU when none available
1910system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.02% # attempts to use FU when none available
1911system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.02% # attempts to use FU when none available
1912system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.02% # attempts to use FU when none available
1913system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.02% # attempts to use FU when none available
1914system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.02% # attempts to use FU when none available
1915system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.02% # attempts to use FU when none available
1916system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.02% # attempts to use FU when none available
1917system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.02% # attempts to use FU when none available
1918system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.02% # attempts to use FU when none available
1919system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.02% # attempts to use FU when none available
1920system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.02% # attempts to use FU when none available
1921system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.02% # attempts to use FU when none available
1922system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.02% # attempts to use FU when none available
1923system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.02% # attempts to use FU when none available
1924system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.02% # attempts to use FU when none available
1925system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.02% # attempts to use FU when none available
1926system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.02% # attempts to use FU when none available
1927system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.02% # attempts to use FU when none available
1928system.cpu1.iq.fu_full::MemRead 1671813 25.83% 70.85% # attempts to use FU when none available
1929system.cpu1.iq.fu_full::MemWrite 1886405 29.15% 100.00% # attempts to use FU when none available

1907system.cpu1.iq.fu_full::IntAlu 3494882 44.84% 44.84% # attempts to use FU when none available
1908system.cpu1.iq.fu_full::IntMult 604 0.01% 44.85% # attempts to use FU when none available
1909system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.85% # attempts to use FU when none available
1910system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.85% # attempts to use FU when none available
1911system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.85% # attempts to use FU when none available
1912system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.85% # attempts to use FU when none available
1913system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.85% # attempts to use FU when none available
1914system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.85% # attempts to use FU when none available
1915system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.85% # attempts to use FU when none available
1916system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.85% # attempts to use FU when none available
1917system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.85% # attempts to use FU when none available
1918system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.85% # attempts to use FU when none available
1919system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.85% # attempts to use FU when none available
1920system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.85% # attempts to use FU when none available
1921system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.85% # attempts to use FU when none available
1922system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.85% # attempts to use FU when none available
1923system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.85% # attempts to use FU when none available
1924system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.85% # attempts to use FU when none available
1925system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.85% # attempts to use FU when none available
1926system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.85% # attempts to use FU when none available
1927system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.85% # attempts to use FU when none available
1928system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.85% # attempts to use FU when none available
1929system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.85% # attempts to use FU when none available
1930system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.85% # attempts to use FU when none available
1931system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.85% # attempts to use FU when none available
1932system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.85% # attempts to use FU when none available
1933system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.85% # attempts to use FU when none available
1934system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.85% # attempts to use FU when none available
1935system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.85% # attempts to use FU when none available
1936system.cpu1.iq.fu_full::MemRead 1953801 25.07% 69.91% # attempts to use FU when none available
1937system.cpu1.iq.fu_full::MemWrite 2345303 30.09% 100.00% # attempts to use FU when none available

1930system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1931system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

1938system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1939system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available

1932system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
1933system.cpu1.iq.FU_type_0::IntAlu 36660342 68.13% 68.13% # Type of FU issued
1934system.cpu1.iq.FU_type_0::IntMult 45736 0.08% 68.22% # Type of FU issued
1935system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued
1936system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued
1937system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued
1938system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued
1939system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued
1940system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued
1941system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued
1942system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued
1943system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued
1944system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued
1945system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued
1946system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued
1947system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued
1948system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued
1949system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued
1950system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued
1951system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued
1952system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued
1953system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued
1954system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued
1955system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued
1956system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued
1957system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued
1958system.cpu1.iq.FU_type_0::SimdFloatMisc 3323 0.01% 68.22% # Type of FU issued
1959system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
1960system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
1961system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
1962system.cpu1.iq.FU_type_0::MemRead 10366546 19.27% 87.49% # Type of FU issued
1963system.cpu1.iq.FU_type_0::MemWrite 6731225 12.51% 100.00% # Type of FU issued

1940system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued
1941system.cpu1.iq.FU_type_0::IntAlu 40748712 68.08% 68.08% # Type of FU issued
1942system.cpu1.iq.FU_type_0::IntMult 52853 0.09% 68.17% # Type of FU issued
1943system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.17% # Type of FU issued
1944system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.17% # Type of FU issued
1945system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.17% # Type of FU issued
1946system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.17% # Type of FU issued
1947system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.17% # Type of FU issued
1948system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.17% # Type of FU issued
1949system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.17% # Type of FU issued
1950system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.17% # Type of FU issued
1951system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.17% # Type of FU issued
1952system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.17% # Type of FU issued
1953system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.17% # Type of FU issued
1954system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.17% # Type of FU issued
1955system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.17% # Type of FU issued
1956system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.17% # Type of FU issued
1957system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.17% # Type of FU issued
1958system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.17% # Type of FU issued
1959system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.17% # Type of FU issued
1960system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.17% # Type of FU issued
1961system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.17% # Type of FU issued
1962system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.17% # Type of FU issued
1963system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.17% # Type of FU issued
1964system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.17% # Type of FU issued
1965system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.17% # Type of FU issued
1966system.cpu1.iq.FU_type_0::SimdFloatMisc 4129 0.01% 68.18% # Type of FU issued
1967system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.18% # Type of FU issued
1968system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.18% # Type of FU issued
1969system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.18% # Type of FU issued
1970system.cpu1.iq.FU_type_0::MemRead 11462159 19.15% 87.33% # Type of FU issued
1971system.cpu1.iq.FU_type_0::MemWrite 7585390 12.67% 100.00% # Type of FU issued

1964system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1965system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1972system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1973system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

1966system.cpu1.iq.FU_type_0::total 53807238 # Type of FU issued
1967system.cpu1.iq.rate 0.510835 # Inst issue rate
1968system.cpu1.iq.fu_busy_cnt 6471684 # FU busy when requested
1969system.cpu1.iq.fu_busy_rate 0.120275 # FU busy rate (busy events/executed inst)
1970system.cpu1.iq.int_inst_queue_reads 218867204 # Number of integer instruction queue reads
1971system.cpu1.iq.int_inst_queue_writes 58625584 # Number of integer instruction queue writes
1972system.cpu1.iq.int_inst_queue_wakeup_accesses 51813824 # Number of integer instruction queue wakeup accesses
1973system.cpu1.iq.fp_inst_queue_reads 6180 # Number of floating instruction queue reads
1974system.cpu1.iq.fp_inst_queue_writes 2068 # Number of floating instruction queue writes
1975system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses
1976system.cpu1.iq.int_alu_accesses 60274803 # Number of integer alu accesses
1977system.cpu1.iq.fp_alu_accesses 4053 # Number of floating point alu accesses
1978system.cpu1.iew.lsq.thread0.forwLoads 90118 # Number of loads that had data forwarded from stores

1974system.cpu1.iq.FU_type_0::total 59853310 # Type of FU issued
1975system.cpu1.iq.rate 0.516544 # Inst issue rate
1976system.cpu1.iq.fu_busy_cnt 7794590 # FU busy when requested
1977system.cpu1.iq.fu_busy_rate 0.130228 # FU busy rate (busy events/executed inst)
1978system.cpu1.iq.int_inst_queue_reads 242094525 # Number of integer instruction queue reads
1979system.cpu1.iq.int_inst_queue_writes 65611557 # Number of integer instruction queue writes
1980system.cpu1.iq.int_inst_queue_wakeup_accesses 57714006 # Number of integer instruction queue wakeup accesses
1981system.cpu1.iq.fp_inst_queue_reads 5715 # Number of floating instruction queue reads
1982system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes
1983system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses
1984system.cpu1.iq.int_alu_accesses 67644200 # Number of integer alu accesses
1985system.cpu1.iq.fp_alu_accesses 3633 # Number of floating point alu accesses
1986system.cpu1.iew.lsq.thread0.forwLoads 110002 # Number of loads that had data forwarded from stores

1979system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1987system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

1980system.cpu1.iew.lsq.thread0.squashedLoads 483730 # Number of loads squashed
1981system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed
1982system.cpu1.iew.lsq.thread0.memOrderViolation 10069 # Number of memory ordering violations
1983system.cpu1.iew.lsq.thread0.squashedStores 351136 # Number of stores squashed

1988system.cpu1.iew.lsq.thread0.squashedLoads 628284 # Number of loads squashed
1989system.cpu1.iew.lsq.thread0.ignoredResponses 842 # Number of memory responses ignored because the instruction is squashed
1990system.cpu1.iew.lsq.thread0.memOrderViolation 10885 # Number of memory ordering violations
1991system.cpu1.iew.lsq.thread0.squashedStores 426405 # Number of stores squashed

1984system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1985system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

1992system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1993system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding

1986system.cpu1.iew.lsq.thread0.rescheduledLoads 51537 # Number of loads that were rescheduled
1987system.cpu1.iew.lsq.thread0.cacheBlocked 78201 # Number of times an access to memory failed due to the cache being blocked

1994system.cpu1.iew.lsq.thread0.rescheduledLoads 57089 # Number of loads that were rescheduled
1995system.cpu1.iew.lsq.thread0.cacheBlocked 100676 # Number of times an access to memory failed due to the cache being blocked

1988system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1996system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle

1989system.cpu1.iew.iewSquashCycles 1751285 # Number of cycles IEW is squashing
1990system.cpu1.iew.iewBlockCycles 538520 # Number of cycles IEW is blocking
1991system.cpu1.iew.iewUnblockCycles 104583 # Number of cycles IEW is unblocking
1992system.cpu1.iew.iewDispatchedInsts 54788620 # Number of instructions dispatched to IQ

1997system.cpu1.iew.iewSquashCycles 1820847 # Number of cycles IEW is squashing
1998system.cpu1.iew.iewBlockCycles 727831 # Number of cycles IEW is blocking
1999system.cpu1.iew.iewUnblockCycles 179449 # Number of cycles IEW is unblocking
2000system.cpu1.iew.iewDispatchedInsts 61101449 # Number of instructions dispatched to IQ

1993system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch

2001system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch

1994system.cpu1.iew.iewDispLoadInsts 10432997 # Number of dispatched load instructions
1995system.cpu1.iew.iewDispStoreInsts 6892596 # Number of dispatched store instructions
1996system.cpu1.iew.iewDispNonSpecInsts 301008 # Number of dispatched non-speculative instructions
1997system.cpu1.iew.iewIQFullEvents 9394 # Number of times the IQ has become full, causing a stall
1998system.cpu1.iew.iewLSQFullEvents 87795 # Number of times the LSQ has become full, causing a stall
1999system.cpu1.iew.memOrderViolationEvents 10069 # Number of memory order violations
2000system.cpu1.iew.predictedTakenIncorrect 55171 # Number of branches that were predicted taken incorrectly
2001system.cpu1.iew.predictedNotTakenIncorrect 126265 # Number of branches that were predicted not taken incorrectly
2002system.cpu1.iew.branchMispredicts 181436 # Number of branch mispredicts detected at execute
2003system.cpu1.iew.iewExecutedInsts 53538867 # Number of executed instructions
2004system.cpu1.iew.iewExecLoadInsts 10265396 # Number of load instructions executed
2005system.cpu1.iew.iewExecSquashedInsts 247288 # Number of squashed instructions skipped in execute

2002system.cpu1.iew.iewDispLoadInsts 11552975 # Number of dispatched load instructions
2003system.cpu1.iew.iewDispStoreInsts 7780383 # Number of dispatched store instructions
2004system.cpu1.iew.iewDispNonSpecInsts 331927 # Number of dispatched non-speculative instructions
2005system.cpu1.iew.iewIQFullEvents 11154 # Number of times the IQ has become full, causing a stall
2006system.cpu1.iew.iewLSQFullEvents 159363 # Number of times the LSQ has become full, causing a stall
2007system.cpu1.iew.memOrderViolationEvents 10885 # Number of memory order violations
2008system.cpu1.iew.predictedTakenIncorrect 82141 # Number of branches that were predicted taken incorrectly
2009system.cpu1.iew.predictedNotTakenIncorrect 153260 # Number of branches that were predicted not taken incorrectly
2010system.cpu1.iew.branchMispredicts 235401 # Number of branch mispredicts detected at execute
2011system.cpu1.iew.iewExecutedInsts 59500982 # Number of executed instructions
2012system.cpu1.iew.iewExecLoadInsts 11329735 # Number of load instructions executed
2013system.cpu1.iew.iewExecSquashedInsts 328066 # Number of squashed instructions skipped in execute

2006system.cpu1.iew.exec_swp 0 # number of swp insts executed

2014system.cpu1.iew.exec_swp 0 # number of swp insts executed

2007system.cpu1.iew.exec_nop 52126 # number of nop insts executed
2008system.cpu1.iew.exec_refs 16932944 # number of memory reference insts executed
2009system.cpu1.iew.exec_branches 11793778 # Number of branches executed
2010system.cpu1.iew.exec_stores 6667548 # Number of stores executed
2011system.cpu1.iew.exec_rate 0.508287 # Inst execution rate
2012system.cpu1.iew.wb_sent 53390597 # cumulative count of insts sent to commit
2013system.cpu1.iew.wb_count 51815609 # cumulative count of insts written-back
2014system.cpu1.iew.wb_producers 25160275 # num instructions producing a value
2015system.cpu1.iew.wb_consumers 38370093 # num instructions consuming a value

2015system.cpu1.iew.exec_nop 55209 # number of nop insts executed
2016system.cpu1.iew.exec_refs 18836194 # number of memory reference insts executed
2017system.cpu1.iew.exec_branches 12894851 # Number of branches executed
2018system.cpu1.iew.exec_stores 7506459 # Number of stores executed
2019system.cpu1.iew.exec_rate 0.513504 # Inst execution rate
2020system.cpu1.iew.wb_sent 59314333 # cumulative count of insts sent to commit
2021system.cpu1.iew.wb_count 57715790 # cumulative count of insts written-back
2022system.cpu1.iew.wb_producers 28288530 # num instructions producing a value
2023system.cpu1.iew.wb_consumers 43462608 # num instructions consuming a value

2016system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

2024system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

2017system.cpu1.iew.wb_rate 0.491927 # insts written-back per cycle
2018system.cpu1.iew.wb_fanout 0.655726 # average fanout of values written-back

2025system.cpu1.iew.wb_rate 0.498097 # insts written-back per cycle
2026system.cpu1.iew.wb_fanout 0.650871 # average fanout of values written-back

2019system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

2027system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

2020system.cpu1.commit.commitSquashedInsts 3631838 # The number of squashed insts skipped by commit
2021system.cpu1.commit.commitNonSpecStalls 539259 # The number of times commit has been forced to stall to communicate backwards
2022system.cpu1.commit.branchMispredicts 169982 # The number of times a branch was mispredicted
2023system.cpu1.commit.committed_per_cycle::samples 102749355 # Number of insts commited each cycle
2024system.cpu1.commit.committed_per_cycle::mean 0.495266 # Number of insts commited each cycle
2025system.cpu1.commit.committed_per_cycle::stdev 1.156980 # Number of insts commited each cycle

2028system.cpu1.commit.commitSquashedInsts 4228906 # The number of squashed insts skipped by commit
2029system.cpu1.commit.commitNonSpecStalls 598742 # The number of times commit has been forced to stall to communicate backwards
2030system.cpu1.commit.branchMispredicts 219024 # The number of times a branch was mispredicted
2031system.cpu1.commit.committed_per_cycle::samples 112407306 # Number of insts commited each cycle
2032system.cpu1.commit.committed_per_cycle::mean 0.502841 # Number of insts commited each cycle
2033system.cpu1.commit.committed_per_cycle::stdev 1.169324 # Number of insts commited each cycle

2026system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

2034system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

2027system.cpu1.commit.committed_per_cycle::0 77230128 75.16% 75.16% # Number of insts commited each cycle
2028system.cpu1.commit.committed_per_cycle::1 14246960 13.87% 89.03% # Number of insts commited each cycle
2029system.cpu1.commit.committed_per_cycle::2 6071957 5.91% 94.94% # Number of insts commited each cycle
2030system.cpu1.commit.committed_per_cycle::3 703815 0.68% 95.62% # Number of insts commited each cycle
2031system.cpu1.commit.committed_per_cycle::4 1976351 1.92% 97.55% # Number of insts commited each cycle
2032system.cpu1.commit.committed_per_cycle::5 1539288 1.50% 99.05% # Number of insts commited each cycle
2033system.cpu1.commit.committed_per_cycle::6 468880 0.46% 99.50% # Number of insts commited each cycle
2034system.cpu1.commit.committed_per_cycle::7 125021 0.12% 99.62% # Number of insts commited each cycle
2035system.cpu1.commit.committed_per_cycle::8 386955 0.38% 100.00% # Number of insts commited each cycle

2035system.cpu1.commit.committed_per_cycle::0 84196637 74.90% 74.90% # Number of insts commited each cycle
2036system.cpu1.commit.committed_per_cycle::1 15782926 14.04% 88.94% # Number of insts commited each cycle
2037system.cpu1.commit.committed_per_cycle::2 6506905 5.79% 94.73% # Number of insts commited each cycle
2038system.cpu1.commit.committed_per_cycle::3 899885 0.80% 95.53% # Number of insts commited each cycle
2039system.cpu1.commit.committed_per_cycle::4 2238894 1.99% 97.53% # Number of insts commited each cycle
2040system.cpu1.commit.committed_per_cycle::5 1696394 1.51% 99.03% # Number of insts commited each cycle
2041system.cpu1.commit.committed_per_cycle::6 469505 0.42% 99.45% # Number of insts commited each cycle
2042system.cpu1.commit.committed_per_cycle::7 157300 0.14% 99.59% # Number of insts commited each cycle
2043system.cpu1.commit.committed_per_cycle::8 458860 0.41% 100.00% # Number of insts commited each cycle

2036system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2037system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2038system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

2044system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2045system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2046system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

2039system.cpu1.commit.committed_per_cycle::total 102749355 # Number of insts commited each cycle
2040system.cpu1.commit.committedInsts 41322014 # Number of instructions committed
2041system.cpu1.commit.committedOps 50888230 # Number of ops (including micro ops) committed

2047system.cpu1.commit.committed_per_cycle::total 112407306 # Number of insts commited each cycle
2048system.cpu1.commit.committedInsts 46016034 # Number of instructions committed
2049system.cpu1.commit.committedOps 56522947 # Number of ops (including micro ops) committed

2042system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed

2050system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed

2043system.cpu1.commit.refs 16490727 # Number of memory references committed
2044system.cpu1.commit.loads 9949267 # Number of loads committed
2045system.cpu1.commit.membars 209363 # Number of memory barriers committed
2046system.cpu1.commit.branches 11627773 # Number of branches committed

2051system.cpu1.commit.refs 18278669 # Number of memory references committed
2052system.cpu1.commit.loads 10924691 # Number of loads committed
2053system.cpu1.commit.membars 232005 # Number of memory barriers committed
2054system.cpu1.commit.branches 12685356 # Number of branches committed

2047system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.

2055system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.

2048system.cpu1.commit.int_insts 45743033 # Number of committed integer instructions.
2049system.cpu1.commit.function_calls 3362907 # Number of function calls committed.

2056system.cpu1.commit.int_insts 50487985 # Number of committed integer instructions.
2057system.cpu1.commit.function_calls 3456157 # Number of function calls committed.

2050system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction

2058system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction

2051system.cpu1.commit.op_class_0::IntAlu 34349326 67.50% 67.50% # Class of committed instruction
2052system.cpu1.commit.op_class_0::IntMult 44854 0.09% 67.59% # Class of committed instruction
2053system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.59% # Class of committed instruction
2054system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.59% # Class of committed instruction
2055system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.59% # Class of committed instruction
2056system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.59% # Class of committed instruction
2057system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.59% # Class of committed instruction
2058system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.59% # Class of committed instruction
2059system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.59% # Class of committed instruction
2060system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.59% # Class of committed instruction
2061system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.59% # Class of committed instruction
2062system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.59% # Class of committed instruction
2063system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.59% # Class of committed instruction
2064system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.59% # Class of committed instruction
2065system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.59% # Class of committed instruction
2066system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.59% # Class of committed instruction
2067system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.59% # Class of committed instruction
2068system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.59% # Class of committed instruction
2069system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.59% # Class of committed instruction
2070system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.59% # Class of committed instruction
2071system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.59% # Class of committed instruction
2072system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.59% # Class of committed instruction
2073system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.59% # Class of committed instruction
2074system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.59% # Class of committed instruction
2075system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.59% # Class of committed instruction
2076system.cpu1.commit.op_class_0::SimdFloatMisc 3323 0.01% 67.59% # Class of committed instruction
2077system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction
2078system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction
2079system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction
2080system.cpu1.commit.op_class_0::MemRead 9949267 19.55% 87.15% # Class of committed instruction
2081system.cpu1.commit.op_class_0::MemWrite 6541460 12.85% 100.00% # Class of committed instruction

2059system.cpu1.commit.op_class_0::IntAlu 38188356 67.56% 67.56% # Class of committed instruction
2060system.cpu1.commit.op_class_0::IntMult 51793 0.09% 67.65% # Class of committed instruction
2061system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.65% # Class of committed instruction
2062system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.65% # Class of committed instruction
2063system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.65% # Class of committed instruction
2064system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.65% # Class of committed instruction
2065system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.65% # Class of committed instruction
2066system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.65% # Class of committed instruction
2067system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.65% # Class of committed instruction
2068system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.65% # Class of committed instruction
2069system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.65% # Class of committed instruction
2070system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.65% # Class of committed instruction
2071system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.65% # Class of committed instruction
2072system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.65% # Class of committed instruction
2073system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.65% # Class of committed instruction
2074system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.65% # Class of committed instruction
2075system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.65% # Class of committed instruction
2076system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.65% # Class of committed instruction
2077system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.65% # Class of committed instruction
2078system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.65% # Class of committed instruction
2079system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.65% # Class of committed instruction
2080system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.65% # Class of committed instruction
2081system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.65% # Class of committed instruction
2082system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.65% # Class of committed instruction
2083system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.65% # Class of committed instruction
2084system.cpu1.commit.op_class_0::SimdFloatMisc 4129 0.01% 67.66% # Class of committed instruction
2085system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.66% # Class of committed instruction
2086system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.66% # Class of committed instruction
2087system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.66% # Class of committed instruction
2088system.cpu1.commit.op_class_0::MemRead 10924691 19.33% 86.99% # Class of committed instruction
2089system.cpu1.commit.op_class_0::MemWrite 7353978 13.01% 100.00% # Class of committed instruction

2082system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2083system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

2090system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2091system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction

2084system.cpu1.commit.op_class_0::total 50888230 # Class of committed instruction
2085system.cpu1.commit.bw_lim_events 386955 # number cycles where commit BW limit reached
2086system.cpu1.rob.rob_reads 136861200 # The number of ROB reads
2087system.cpu1.rob.rob_writes 110963404 # The number of ROB writes
2088system.cpu1.timesIdled 59136 # Number of times that the entire CPU went into an idle state and unscheduled itself
2089system.cpu1.idleCycles 655719 # Total number of cycles that the CPU has spent unscheduled due to idling
2090system.cpu1.quiesceCycles 5544933026 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2091system.cpu1.committedInsts 41289159 # Number of Instructions Simulated
2092system.cpu1.committedOps 50855375 # Number of Ops (including micro ops) Simulated
2093system.cpu1.cpi 2.551082 # CPI: Cycles Per Instruction
2094system.cpu1.cpi_total 2.551082 # CPI: Total CPI of All Threads
2095system.cpu1.ipc 0.391991 # IPC: Instructions Per Cycle
2096system.cpu1.ipc_total 0.391991 # IPC: Total IPC of All Threads
2097system.cpu1.int_regfile_reads 56164709 # number of integer regfile reads
2098system.cpu1.int_regfile_writes 35664798 # number of integer regfile writes
2099system.cpu1.fp_regfile_reads 1398 # number of floating regfile reads

2092system.cpu1.commit.op_class_0::total 56522947 # Class of committed instruction
2093system.cpu1.commit.bw_lim_events 458860 # number cycles where commit BW limit reached
2094system.cpu1.rob.rob_reads 152481338 # The number of ROB reads
2095system.cpu1.rob.rob_writes 123545319 # The number of ROB writes
2096system.cpu1.timesIdled 68699 # Number of times that the entire CPU went into an idle state and unscheduled itself
2097system.cpu1.idleCycles 1420259 # Total number of cycles that the CPU has spent unscheduled due to idling
2098system.cpu1.quiesceCycles 5138082707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2099system.cpu1.committedInsts 45982821 # Number of Instructions Simulated
2100system.cpu1.committedOps 56489734 # Number of Ops (including micro ops) Simulated
2101system.cpu1.cpi 2.519909 # CPI: Cycles Per Instruction
2102system.cpu1.cpi_total 2.519909 # CPI: Total CPI of All Threads
2103system.cpu1.ipc 0.396840 # IPC: Instructions Per Cycle
2104system.cpu1.ipc_total 0.396840 # IPC: Total IPC of All Threads
2105system.cpu1.int_regfile_reads 62666330 # number of integer regfile reads
2106system.cpu1.int_regfile_writes 39173045 # number of integer regfile writes
2107system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads

2100system.cpu1.fp_regfile_writes 516 # number of floating regfile writes

2108system.cpu1.fp_regfile_writes 516 # number of floating regfile writes

2101system.cpu1.cc_regfile_reads 190801964 # number of cc regfile reads
2102system.cpu1.cc_regfile_writes 15538939 # number of cc regfile writes
2103system.cpu1.misc_regfile_reads 145958777 # number of misc regfile reads
2104system.cpu1.misc_regfile_writes 388038 # number of misc regfile writes
2105system.cpu1.dcache.tags.replacements 188683 # number of replacements
2106system.cpu1.dcache.tags.tagsinuse 469.137779 # Cycle average of tags in use
2107system.cpu1.dcache.tags.total_refs 15712566 # Total number of references to valid blocks.
2108system.cpu1.dcache.tags.sampled_refs 189037 # Sample count of references to valid blocks.
2109system.cpu1.dcache.tags.avg_refs 83.118998 # Average number of references to valid blocks.
2110system.cpu1.dcache.tags.warmup_cycle 93446032500 # Cycle when the warmup percentage was hit.
2111system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.137779 # Average occupied blocks per requestor
2112system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916285 # Average percentage of cache occupancy
2113system.cpu1.dcache.tags.occ_percent::total 0.916285 # Average percentage of cache occupancy
2114system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
2115system.cpu1.dcache.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id
2116system.cpu1.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
2117system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
2118system.cpu1.dcache.tags.tag_accesses 32914145 # Number of tag accesses
2119system.cpu1.dcache.tags.data_accesses 32914145 # Number of data accesses
2120system.cpu1.dcache.ReadReq_hits::cpu1.data 9558582 # number of ReadReq hits
2121system.cpu1.dcache.ReadReq_hits::total 9558582 # number of ReadReq hits
2122system.cpu1.dcache.WriteReq_hits::cpu1.data 5897409 # number of WriteReq hits
2123system.cpu1.dcache.WriteReq_hits::total 5897409 # number of WriteReq hits
2124system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49196 # number of SoftPFReq hits
2125system.cpu1.dcache.SoftPFReq_hits::total 49196 # number of SoftPFReq hits
2126system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78850 # number of LoadLockedReq hits
2127system.cpu1.dcache.LoadLockedReq_hits::total 78850 # number of LoadLockedReq hits
2128system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70461 # number of StoreCondReq hits
2129system.cpu1.dcache.StoreCondReq_hits::total 70461 # number of StoreCondReq hits
2130system.cpu1.dcache.demand_hits::cpu1.data 15455991 # number of demand (read+write) hits
2131system.cpu1.dcache.demand_hits::total 15455991 # number of demand (read+write) hits
2132system.cpu1.dcache.overall_hits::cpu1.data 15505187 # number of overall hits
2133system.cpu1.dcache.overall_hits::total 15505187 # number of overall hits
2134system.cpu1.dcache.ReadReq_misses::cpu1.data 218229 # number of ReadReq misses
2135system.cpu1.dcache.ReadReq_misses::total 218229 # number of ReadReq misses
2136system.cpu1.dcache.WriteReq_misses::cpu1.data 396239 # number of WriteReq misses
2137system.cpu1.dcache.WriteReq_misses::total 396239 # number of WriteReq misses
2138system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29850 # number of SoftPFReq misses
2139system.cpu1.dcache.SoftPFReq_misses::total 29850 # number of SoftPFReq misses
2140system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18125 # number of LoadLockedReq misses
2141system.cpu1.dcache.LoadLockedReq_misses::total 18125 # number of LoadLockedReq misses
2142system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23674 # number of StoreCondReq misses
2143system.cpu1.dcache.StoreCondReq_misses::total 23674 # number of StoreCondReq misses
2144system.cpu1.dcache.demand_misses::cpu1.data 614468 # number of demand (read+write) misses
2145system.cpu1.dcache.demand_misses::total 614468 # number of demand (read+write) misses
2146system.cpu1.dcache.overall_misses::cpu1.data 644318 # number of overall misses
2147system.cpu1.dcache.overall_misses::total 644318 # number of overall misses
2148system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3487669000 # number of ReadReq miss cycles
2149system.cpu1.dcache.ReadReq_miss_latency::total 3487669000 # number of ReadReq miss cycles
2150system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9663134455 # number of WriteReq miss cycles
2151system.cpu1.dcache.WriteReq_miss_latency::total 9663134455 # number of WriteReq miss cycles
2152system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 358154500 # number of LoadLockedReq miss cycles
2153system.cpu1.dcache.LoadLockedReq_miss_latency::total 358154500 # number of LoadLockedReq miss cycles
2154system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554726500 # number of StoreCondReq miss cycles
2155system.cpu1.dcache.StoreCondReq_miss_latency::total 554726500 # number of StoreCondReq miss cycles
2156system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 887500 # number of StoreCondFailReq miss cycles
2157system.cpu1.dcache.StoreCondFailReq_miss_latency::total 887500 # number of StoreCondFailReq miss cycles
2158system.cpu1.dcache.demand_miss_latency::cpu1.data 13150803455 # number of demand (read+write) miss cycles
2159system.cpu1.dcache.demand_miss_latency::total 13150803455 # number of demand (read+write) miss cycles
2160system.cpu1.dcache.overall_miss_latency::cpu1.data 13150803455 # number of overall miss cycles
2161system.cpu1.dcache.overall_miss_latency::total 13150803455 # number of overall miss cycles
2162system.cpu1.dcache.ReadReq_accesses::cpu1.data 9776811 # number of ReadReq accesses(hits+misses)
2163system.cpu1.dcache.ReadReq_accesses::total 9776811 # number of ReadReq accesses(hits+misses)
2164system.cpu1.dcache.WriteReq_accesses::cpu1.data 6293648 # number of WriteReq accesses(hits+misses)
2165system.cpu1.dcache.WriteReq_accesses::total 6293648 # number of WriteReq accesses(hits+misses)
2166system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79046 # number of SoftPFReq accesses(hits+misses)
2167system.cpu1.dcache.SoftPFReq_accesses::total 79046 # number of SoftPFReq accesses(hits+misses)
2168system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96975 # number of LoadLockedReq accesses(hits+misses)
2169system.cpu1.dcache.LoadLockedReq_accesses::total 96975 # number of LoadLockedReq accesses(hits+misses)
2170system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94135 # number of StoreCondReq accesses(hits+misses)
2171system.cpu1.dcache.StoreCondReq_accesses::total 94135 # number of StoreCondReq accesses(hits+misses)
2172system.cpu1.dcache.demand_accesses::cpu1.data 16070459 # number of demand (read+write) accesses
2173system.cpu1.dcache.demand_accesses::total 16070459 # number of demand (read+write) accesses
2174system.cpu1.dcache.overall_accesses::cpu1.data 16149505 # number of overall (read+write) accesses
2175system.cpu1.dcache.overall_accesses::total 16149505 # number of overall (read+write) accesses
2176system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022321 # miss rate for ReadReq accesses
2177system.cpu1.dcache.ReadReq_miss_rate::total 0.022321 # miss rate for ReadReq accesses
2178system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062959 # miss rate for WriteReq accesses
2179system.cpu1.dcache.WriteReq_miss_rate::total 0.062959 # miss rate for WriteReq accesses
2180system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377628 # miss rate for SoftPFReq accesses
2181system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377628 # miss rate for SoftPFReq accesses
2182system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186904 # miss rate for LoadLockedReq accesses
2183system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186904 # miss rate for LoadLockedReq accesses
2184system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.251490 # miss rate for StoreCondReq accesses
2185system.cpu1.dcache.StoreCondReq_miss_rate::total 0.251490 # miss rate for StoreCondReq accesses
2186system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038236 # miss rate for demand accesses
2187system.cpu1.dcache.demand_miss_rate::total 0.038236 # miss rate for demand accesses
2188system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039897 # miss rate for overall accesses
2189system.cpu1.dcache.overall_miss_rate::total 0.039897 # miss rate for overall accesses
2190system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15981.693542 # average ReadReq miss latency
2191system.cpu1.dcache.ReadReq_avg_miss_latency::total 15981.693542 # average ReadReq miss latency
2192system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24387.136185 # average WriteReq miss latency
2193system.cpu1.dcache.WriteReq_avg_miss_latency::total 24387.136185 # average WriteReq miss latency
2194system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19760.248276 # average LoadLockedReq miss latency
2195system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19760.248276 # average LoadLockedReq miss latency
2196system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23431.887303 # average StoreCondReq miss latency
2197system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.887303 # average StoreCondReq miss latency

2109system.cpu1.cc_regfile_reads 211754483 # number of cc regfile reads
2110system.cpu1.cc_regfile_writes 18307351 # number of cc regfile writes
2111system.cpu1.misc_regfile_reads 158297998 # number of misc regfile reads
2112system.cpu1.misc_regfile_writes 426234 # number of misc regfile writes
2113system.cpu1.dcache.tags.replacements 227119 # number of replacements
2114system.cpu1.dcache.tags.tagsinuse 480.780000 # Cycle average of tags in use
2115system.cpu1.dcache.tags.total_refs 17377933 # Total number of references to valid blocks.
2116system.cpu1.dcache.tags.sampled_refs 227440 # Sample count of references to valid blocks.
2117system.cpu1.dcache.tags.avg_refs 76.406670 # Average number of references to valid blocks.
2118system.cpu1.dcache.tags.warmup_cycle 89481619000 # Cycle when the warmup percentage was hit.
2119system.cpu1.dcache.tags.occ_blocks::cpu1.data 480.780000 # Average occupied blocks per requestor
2120system.cpu1.dcache.tags.occ_percent::cpu1.data 0.939023 # Average percentage of cache occupancy
2121system.cpu1.dcache.tags.occ_percent::total 0.939023 # Average percentage of cache occupancy
2122system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id
2123system.cpu1.dcache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id
2124system.cpu1.dcache.tags.age_task_id_blocks_1024::3 24 # Occupied blocks per task id
2125system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id
2126system.cpu1.dcache.tags.tag_accesses 36531516 # Number of tag accesses
2127system.cpu1.dcache.tags.data_accesses 36531516 # Number of data accesses
2128system.cpu1.dcache.ReadReq_hits::cpu1.data 10502192 # number of ReadReq hits
2129system.cpu1.dcache.ReadReq_hits::total 10502192 # number of ReadReq hits
2130system.cpu1.dcache.WriteReq_hits::cpu1.data 6578620 # number of WriteReq hits
2131system.cpu1.dcache.WriteReq_hits::total 6578620 # number of WriteReq hits
2132system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65191 # number of SoftPFReq hits
2133system.cpu1.dcache.SoftPFReq_hits::total 65191 # number of SoftPFReq hits
2134system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88541 # number of LoadLockedReq hits
2135system.cpu1.dcache.LoadLockedReq_hits::total 88541 # number of LoadLockedReq hits
2136system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80577 # number of StoreCondReq hits
2137system.cpu1.dcache.StoreCondReq_hits::total 80577 # number of StoreCondReq hits
2138system.cpu1.dcache.demand_hits::cpu1.data 17080812 # number of demand (read+write) hits
2139system.cpu1.dcache.demand_hits::total 17080812 # number of demand (read+write) hits
2140system.cpu1.dcache.overall_hits::cpu1.data 17146003 # number of overall hits
2141system.cpu1.dcache.overall_hits::total 17146003 # number of overall hits
2142system.cpu1.dcache.ReadReq_misses::cpu1.data 257246 # number of ReadReq misses
2143system.cpu1.dcache.ReadReq_misses::total 257246 # number of ReadReq misses
2144system.cpu1.dcache.WriteReq_misses::cpu1.data 477990 # number of WriteReq misses
2145system.cpu1.dcache.WriteReq_misses::total 477990 # number of WriteReq misses
2146system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35676 # number of SoftPFReq misses
2147system.cpu1.dcache.SoftPFReq_misses::total 35676 # number of SoftPFReq misses
2148system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19120 # number of LoadLockedReq misses
2149system.cpu1.dcache.LoadLockedReq_misses::total 19120 # number of LoadLockedReq misses
2150system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23513 # number of StoreCondReq misses
2151system.cpu1.dcache.StoreCondReq_misses::total 23513 # number of StoreCondReq misses
2152system.cpu1.dcache.demand_misses::cpu1.data 735236 # number of demand (read+write) misses
2153system.cpu1.dcache.demand_misses::total 735236 # number of demand (read+write) misses
2154system.cpu1.dcache.overall_misses::cpu1.data 770912 # number of overall misses
2155system.cpu1.dcache.overall_misses::total 770912 # number of overall misses
2156system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4397234500 # number of ReadReq miss cycles
2157system.cpu1.dcache.ReadReq_miss_latency::total 4397234500 # number of ReadReq miss cycles
2158system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13204055417 # number of WriteReq miss cycles
2159system.cpu1.dcache.WriteReq_miss_latency::total 13204055417 # number of WriteReq miss cycles
2160system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 384125500 # number of LoadLockedReq miss cycles
2161system.cpu1.dcache.LoadLockedReq_miss_latency::total 384125500 # number of LoadLockedReq miss cycles
2162system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615714500 # number of StoreCondReq miss cycles
2163system.cpu1.dcache.StoreCondReq_miss_latency::total 615714500 # number of StoreCondReq miss cycles
2164system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2019500 # number of StoreCondFailReq miss cycles
2165system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2019500 # number of StoreCondFailReq miss cycles
2166system.cpu1.dcache.demand_miss_latency::cpu1.data 17601289917 # number of demand (read+write) miss cycles
2167system.cpu1.dcache.demand_miss_latency::total 17601289917 # number of demand (read+write) miss cycles
2168system.cpu1.dcache.overall_miss_latency::cpu1.data 17601289917 # number of overall miss cycles
2169system.cpu1.dcache.overall_miss_latency::total 17601289917 # number of overall miss cycles
2170system.cpu1.dcache.ReadReq_accesses::cpu1.data 10759438 # number of ReadReq accesses(hits+misses)
2171system.cpu1.dcache.ReadReq_accesses::total 10759438 # number of ReadReq accesses(hits+misses)
2172system.cpu1.dcache.WriteReq_accesses::cpu1.data 7056610 # number of WriteReq accesses(hits+misses)
2173system.cpu1.dcache.WriteReq_accesses::total 7056610 # number of WriteReq accesses(hits+misses)
2174system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100867 # number of SoftPFReq accesses(hits+misses)
2175system.cpu1.dcache.SoftPFReq_accesses::total 100867 # number of SoftPFReq accesses(hits+misses)
2176system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107661 # number of LoadLockedReq accesses(hits+misses)
2177system.cpu1.dcache.LoadLockedReq_accesses::total 107661 # number of LoadLockedReq accesses(hits+misses)
2178system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104090 # number of StoreCondReq accesses(hits+misses)
2179system.cpu1.dcache.StoreCondReq_accesses::total 104090 # number of StoreCondReq accesses(hits+misses)
2180system.cpu1.dcache.demand_accesses::cpu1.data 17816048 # number of demand (read+write) accesses
2181system.cpu1.dcache.demand_accesses::total 17816048 # number of demand (read+write) accesses
2182system.cpu1.dcache.overall_accesses::cpu1.data 17916915 # number of overall (read+write) accesses
2183system.cpu1.dcache.overall_accesses::total 17916915 # number of overall (read+write) accesses
2184system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023909 # miss rate for ReadReq accesses
2185system.cpu1.dcache.ReadReq_miss_rate::total 0.023909 # miss rate for ReadReq accesses
2186system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067736 # miss rate for WriteReq accesses
2187system.cpu1.dcache.WriteReq_miss_rate::total 0.067736 # miss rate for WriteReq accesses
2188system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353693 # miss rate for SoftPFReq accesses
2189system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353693 # miss rate for SoftPFReq accesses
2190system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177594 # miss rate for LoadLockedReq accesses
2191system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177594 # miss rate for LoadLockedReq accesses
2192system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225891 # miss rate for StoreCondReq accesses
2193system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225891 # miss rate for StoreCondReq accesses
2194system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041268 # miss rate for demand accesses
2195system.cpu1.dcache.demand_miss_rate::total 0.041268 # miss rate for demand accesses
2196system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043027 # miss rate for overall accesses
2197system.cpu1.dcache.overall_miss_rate::total 0.043027 # miss rate for overall accesses
2198system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17093.499996 # average ReadReq miss latency
2199system.cpu1.dcache.ReadReq_avg_miss_latency::total 17093.499996 # average ReadReq miss latency
2200system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27624.124808 # average WriteReq miss latency
2201system.cpu1.dcache.WriteReq_avg_miss_latency::total 27624.124808 # average WriteReq miss latency
2202system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20090.245816 # average LoadLockedReq miss latency
2203system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20090.245816 # average LoadLockedReq miss latency
2204system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26186.131076 # average StoreCondReq miss latency
2205system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26186.131076 # average StoreCondReq miss latency

2198system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2199system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency

2206system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2207system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency

2200system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21401.933795 # average overall miss latency
2201system.cpu1.dcache.demand_avg_miss_latency::total 21401.933795 # average overall miss latency
2202system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20410.423820 # average overall miss latency
2203system.cpu1.dcache.overall_avg_miss_latency::total 20410.423820 # average overall miss latency
2204system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked
2205system.cpu1.dcache.blocked_cycles::no_targets 1417697 # number of cycles access was blocked
2206system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
2207system.cpu1.dcache.blocked::no_targets 39735 # number of cycles access was blocked
2208system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked
2209system.cpu1.dcache.avg_blocked_cycles::no_targets 35.678797 # average number of cycles each access was blocked

2208system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23939.646477 # average overall miss latency
2209system.cpu1.dcache.demand_avg_miss_latency::total 23939.646477 # average overall miss latency
2210system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22831.775763 # average overall miss latency
2211system.cpu1.dcache.overall_avg_miss_latency::total 22831.775763 # average overall miss latency
2212system.cpu1.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked
2213system.cpu1.dcache.blocked_cycles::no_targets 1982545 # number of cycles access was blocked
2214system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked
2215system.cpu1.dcache.blocked::no_targets 49131 # number of cycles access was blocked
2216system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.243243 # average number of cycles each access was blocked
2217system.cpu1.dcache.avg_blocked_cycles::no_targets 40.352222 # average number of cycles each access was blocked

2210system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2211system.cpu1.dcache.cache_copies 0 # number of cache copies performed

2218system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2219system.cpu1.dcache.cache_copies 0 # number of cache copies performed

2212system.cpu1.dcache.writebacks::writebacks 116769 # number of writebacks
2213system.cpu1.dcache.writebacks::total 116769 # number of writebacks
2214system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80049 # number of ReadReq MSHR hits
2215system.cpu1.dcache.ReadReq_mshr_hits::total 80049 # number of ReadReq MSHR hits
2216system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306072 # number of WriteReq MSHR hits
2217system.cpu1.dcache.WriteReq_mshr_hits::total 306072 # number of WriteReq MSHR hits
2218system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13108 # number of LoadLockedReq MSHR hits
2219system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13108 # number of LoadLockedReq MSHR hits
2220system.cpu1.dcache.demand_mshr_hits::cpu1.data 386121 # number of demand (read+write) MSHR hits
2221system.cpu1.dcache.demand_mshr_hits::total 386121 # number of demand (read+write) MSHR hits
2222system.cpu1.dcache.overall_mshr_hits::cpu1.data 386121 # number of overall MSHR hits
2223system.cpu1.dcache.overall_mshr_hits::total 386121 # number of overall MSHR hits
2224system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 138180 # number of ReadReq MSHR misses
2225system.cpu1.dcache.ReadReq_mshr_misses::total 138180 # number of ReadReq MSHR misses
2226system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90167 # number of WriteReq MSHR misses
2227system.cpu1.dcache.WriteReq_mshr_misses::total 90167 # number of WriteReq MSHR misses
2228system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28614 # number of SoftPFReq MSHR misses
2229system.cpu1.dcache.SoftPFReq_mshr_misses::total 28614 # number of SoftPFReq MSHR misses
2230system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5017 # number of LoadLockedReq MSHR misses
2231system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5017 # number of LoadLockedReq MSHR misses
2232system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23674 # number of StoreCondReq MSHR misses
2233system.cpu1.dcache.StoreCondReq_mshr_misses::total 23674 # number of StoreCondReq MSHR misses
2234system.cpu1.dcache.demand_mshr_misses::cpu1.data 228347 # number of demand (read+write) MSHR misses
2235system.cpu1.dcache.demand_mshr_misses::total 228347 # number of demand (read+write) MSHR misses
2236system.cpu1.dcache.overall_mshr_misses::cpu1.data 256961 # number of overall MSHR misses
2237system.cpu1.dcache.overall_mshr_misses::total 256961 # number of overall MSHR misses
2238system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable
2239system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14486 # number of ReadReq MSHR uncacheable
2240system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
2241system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable
2242system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses
2243system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26301 # number of overall MSHR uncacheable misses
2244system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1915104500 # number of ReadReq MSHR miss cycles
2245system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1915104500 # number of ReadReq MSHR miss cycles
2246system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2355138466 # number of WriteReq MSHR miss cycles
2247system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2355138466 # number of WriteReq MSHR miss cycles
2248system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 482351500 # number of SoftPFReq MSHR miss cycles
2249system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 482351500 # number of SoftPFReq MSHR miss cycles
2250system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90011000 # number of LoadLockedReq MSHR miss cycles
2251system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90011000 # number of LoadLockedReq MSHR miss cycles
2252system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531068500 # number of StoreCondReq MSHR miss cycles
2253system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531068500 # number of StoreCondReq MSHR miss cycles
2254system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 871500 # number of StoreCondFailReq MSHR miss cycles
2255system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 871500 # number of StoreCondFailReq MSHR miss cycles
2256system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4270242966 # number of demand (read+write) MSHR miss cycles
2257system.cpu1.dcache.demand_mshr_miss_latency::total 4270242966 # number of demand (read+write) MSHR miss cycles
2258system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4752594466 # number of overall MSHR miss cycles
2259system.cpu1.dcache.overall_mshr_miss_latency::total 4752594466 # number of overall MSHR miss cycles
2260system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2349248500 # number of ReadReq MSHR uncacheable cycles
2261system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2349248500 # number of ReadReq MSHR uncacheable cycles
2262system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1864740000 # number of WriteReq MSHR uncacheable cycles
2263system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1864740000 # number of WriteReq MSHR uncacheable cycles
2264system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4213988500 # number of overall MSHR uncacheable cycles
2265system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4213988500 # number of overall MSHR uncacheable cycles
2266system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014133 # mshr miss rate for ReadReq accesses
2267system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014133 # mshr miss rate for ReadReq accesses
2268system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014327 # mshr miss rate for WriteReq accesses
2269system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014327 # mshr miss rate for WriteReq accesses
2270system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361992 # mshr miss rate for SoftPFReq accesses
2271system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361992 # mshr miss rate for SoftPFReq accesses
2272system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051735 # mshr miss rate for LoadLockedReq accesses
2273system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051735 # mshr miss rate for LoadLockedReq accesses
2274system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.251490 # mshr miss rate for StoreCondReq accesses
2275system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.251490 # mshr miss rate for StoreCondReq accesses
2276system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014209 # mshr miss rate for demand accesses
2277system.cpu1.dcache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses
2278system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015911 # mshr miss rate for overall accesses
2279system.cpu1.dcache.overall_mshr_miss_rate::total 0.015911 # mshr miss rate for overall accesses
2280system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.491243 # average ReadReq mshr miss latency
2281system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.491243 # average ReadReq mshr miss latency
2282system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26119.738552 # average WriteReq mshr miss latency
2283system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26119.738552 # average WriteReq mshr miss latency
2284system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16857.185294 # average SoftPFReq mshr miss latency
2285system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16857.185294 # average SoftPFReq mshr miss latency
2286system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17941.199920 # average LoadLockedReq mshr miss latency
2287system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17941.199920 # average LoadLockedReq mshr miss latency
2288system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22432.563149 # average StoreCondReq mshr miss latency
2289system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22432.563149 # average StoreCondReq mshr miss latency

2220system.cpu1.dcache.writebacks::writebacks 137800 # number of writebacks
2221system.cpu1.dcache.writebacks::total 137800 # number of writebacks
2222system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 93990 # number of ReadReq MSHR hits
2223system.cpu1.dcache.ReadReq_mshr_hits::total 93990 # number of ReadReq MSHR hits
2224system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 374320 # number of WriteReq MSHR hits
2225system.cpu1.dcache.WriteReq_mshr_hits::total 374320 # number of WriteReq MSHR hits
2226system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13607 # number of LoadLockedReq MSHR hits
2227system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13607 # number of LoadLockedReq MSHR hits
2228system.cpu1.dcache.demand_mshr_hits::cpu1.data 468310 # number of demand (read+write) MSHR hits
2229system.cpu1.dcache.demand_mshr_hits::total 468310 # number of demand (read+write) MSHR hits
2230system.cpu1.dcache.overall_mshr_hits::cpu1.data 468310 # number of overall MSHR hits
2231system.cpu1.dcache.overall_mshr_hits::total 468310 # number of overall MSHR hits
2232system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163256 # number of ReadReq MSHR misses
2233system.cpu1.dcache.ReadReq_mshr_misses::total 163256 # number of ReadReq MSHR misses
2234system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103670 # number of WriteReq MSHR misses
2235system.cpu1.dcache.WriteReq_mshr_misses::total 103670 # number of WriteReq MSHR misses
2236system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32269 # number of SoftPFReq MSHR misses
2237system.cpu1.dcache.SoftPFReq_mshr_misses::total 32269 # number of SoftPFReq MSHR misses
2238system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5513 # number of LoadLockedReq MSHR misses
2239system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5513 # number of LoadLockedReq MSHR misses
2240system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23513 # number of StoreCondReq MSHR misses
2241system.cpu1.dcache.StoreCondReq_mshr_misses::total 23513 # number of StoreCondReq MSHR misses
2242system.cpu1.dcache.demand_mshr_misses::cpu1.data 266926 # number of demand (read+write) MSHR misses
2243system.cpu1.dcache.demand_mshr_misses::total 266926 # number of demand (read+write) MSHR misses
2244system.cpu1.dcache.overall_mshr_misses::cpu1.data 299195 # number of overall MSHR misses
2245system.cpu1.dcache.overall_mshr_misses::total 299195 # number of overall MSHR misses
2246system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17062 # number of ReadReq MSHR uncacheable
2247system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17062 # number of ReadReq MSHR uncacheable
2248system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
2249system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable
2250system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31403 # number of overall MSHR uncacheable misses
2251system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31403 # number of overall MSHR uncacheable misses
2252system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2326061500 # number of ReadReq MSHR miss cycles
2253system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2326061500 # number of ReadReq MSHR miss cycles
2254system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3203086933 # number of WriteReq MSHR miss cycles
2255system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3203086933 # number of WriteReq MSHR miss cycles
2256system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 553503000 # number of SoftPFReq MSHR miss cycles
2257system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 553503000 # number of SoftPFReq MSHR miss cycles
2258system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 109001000 # number of LoadLockedReq MSHR miss cycles
2259system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 109001000 # number of LoadLockedReq MSHR miss cycles
2260system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592222500 # number of StoreCondReq MSHR miss cycles
2261system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592222500 # number of StoreCondReq MSHR miss cycles
2262system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq MSHR miss cycles
2263system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1998500 # number of StoreCondFailReq MSHR miss cycles
2264system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5529148433 # number of demand (read+write) MSHR miss cycles
2265system.cpu1.dcache.demand_mshr_miss_latency::total 5529148433 # number of demand (read+write) MSHR miss cycles
2266system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6082651433 # number of overall MSHR miss cycles
2267system.cpu1.dcache.overall_mshr_miss_latency::total 6082651433 # number of overall MSHR miss cycles
2268system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2940631000 # number of ReadReq MSHR uncacheable cycles
2269system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2940631000 # number of ReadReq MSHR uncacheable cycles
2270system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2452626000 # number of WriteReq MSHR uncacheable cycles
2271system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2452626000 # number of WriteReq MSHR uncacheable cycles
2272system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5393257000 # number of overall MSHR uncacheable cycles
2273system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5393257000 # number of overall MSHR uncacheable cycles
2274system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015173 # mshr miss rate for ReadReq accesses
2275system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015173 # mshr miss rate for ReadReq accesses
2276system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014691 # mshr miss rate for WriteReq accesses
2277system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014691 # mshr miss rate for WriteReq accesses
2278system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319916 # mshr miss rate for SoftPFReq accesses
2279system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319916 # mshr miss rate for SoftPFReq accesses
2280system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051207 # mshr miss rate for LoadLockedReq accesses
2281system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051207 # mshr miss rate for LoadLockedReq accesses
2282system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225891 # mshr miss rate for StoreCondReq accesses
2283system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225891 # mshr miss rate for StoreCondReq accesses
2284system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014982 # mshr miss rate for demand accesses
2285system.cpu1.dcache.demand_mshr_miss_rate::total 0.014982 # mshr miss rate for demand accesses
2286system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016699 # mshr miss rate for overall accesses
2287system.cpu1.dcache.overall_mshr_miss_rate::total 0.016699 # mshr miss rate for overall accesses
2288system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14247.938820 # average ReadReq mshr miss latency
2289system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14247.938820 # average ReadReq mshr miss latency
2290system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30896.951220 # average WriteReq mshr miss latency
2291system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30896.951220 # average WriteReq mshr miss latency
2292system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17152.778208 # average SoftPFReq mshr miss latency
2293system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17152.778208 # average SoftPFReq mshr miss latency
2294system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19771.630691 # average LoadLockedReq mshr miss latency
2295system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19771.630691 # average LoadLockedReq mshr miss latency
2296system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25187.024199 # average StoreCondReq mshr miss latency
2297system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25187.024199 # average StoreCondReq mshr miss latency

2290system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2291system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency

2298system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2299system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency

2292system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18700.674701 # average overall mshr miss latency
2293system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18700.674701 # average overall mshr miss latency
2294system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18495.392165 # average overall mshr miss latency
2295system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18495.392165 # average overall mshr miss latency
2296system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162173.719453 # average ReadReq mshr uncacheable latency
2297system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162173.719453 # average ReadReq mshr uncacheable latency
2298system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157828.184511 # average WriteReq mshr uncacheable latency
2299system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157828.184511 # average WriteReq mshr uncacheable latency
2300system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160221.607543 # average overall mshr uncacheable latency
2301system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160221.607543 # average overall mshr uncacheable latency

2300system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20714.162101 # average overall mshr miss latency
2301system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20714.162101 # average overall mshr miss latency
2302system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20330.057097 # average overall mshr miss latency
2303system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20330.057097 # average overall mshr miss latency
2304system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172349.724534 # average ReadReq mshr uncacheable latency
2305system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172349.724534 # average ReadReq mshr uncacheable latency
2306system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171021.964995 # average WriteReq mshr uncacheable latency
2307system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171021.964995 # average WriteReq mshr uncacheable latency
2308system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171743.368468 # average overall mshr uncacheable latency
2309system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171743.368468 # average overall mshr uncacheable latency

2302system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

2310system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

2303system.cpu1.icache.tags.replacements 603214 # number of replacements
2304system.cpu1.icache.tags.tagsinuse 499.475238 # Cycle average of tags in use
2305system.cpu1.icache.tags.total_refs 42957427 # Total number of references to valid blocks.
2306system.cpu1.icache.tags.sampled_refs 603726 # Sample count of references to valid blocks.
2307system.cpu1.icache.tags.avg_refs 71.153846 # Average number of references to valid blocks.
2308system.cpu1.icache.tags.warmup_cycle 78885354000 # Cycle when the warmup percentage was hit.
2309system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.475238 # Average occupied blocks per requestor
2310system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975538 # Average percentage of cache occupancy
2311system.cpu1.icache.tags.occ_percent::total 0.975538 # Average percentage of cache occupancy

2311system.cpu1.icache.tags.replacements 672301 # number of replacements
2312system.cpu1.icache.tags.tagsinuse 498.450521 # Cycle average of tags in use
2313system.cpu1.icache.tags.total_refs 45113050 # Total number of references to valid blocks.
2314system.cpu1.icache.tags.sampled_refs 672813 # Sample count of references to valid blocks.
2315system.cpu1.icache.tags.avg_refs 67.051395 # Average number of references to valid blocks.
2316system.cpu1.icache.tags.warmup_cycle 79271830500 # Cycle when the warmup percentage was hit.
2317system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.450521 # Average occupied blocks per requestor
2318system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973536 # Average percentage of cache occupancy
2319system.cpu1.icache.tags.occ_percent::total 0.973536 # Average percentage of cache occupancy

2312system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

2320system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id

2313system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
2314system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id

2321system.cpu1.icache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
2322system.cpu1.icache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id

2315system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

2323system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

2316system.cpu1.icache.tags.tag_accesses 87771063 # Number of tag accesses
2317system.cpu1.icache.tags.data_accesses 87771063 # Number of data accesses
2318system.cpu1.icache.ReadReq_hits::cpu1.inst 42957427 # number of ReadReq hits
2319system.cpu1.icache.ReadReq_hits::total 42957427 # number of ReadReq hits
2320system.cpu1.icache.demand_hits::cpu1.inst 42957427 # number of demand (read+write) hits
2321system.cpu1.icache.demand_hits::total 42957427 # number of demand (read+write) hits
2322system.cpu1.icache.overall_hits::cpu1.inst 42957427 # number of overall hits
2323system.cpu1.icache.overall_hits::total 42957427 # number of overall hits
2324system.cpu1.icache.ReadReq_misses::cpu1.inst 626240 # number of ReadReq misses
2325system.cpu1.icache.ReadReq_misses::total 626240 # number of ReadReq misses
2326system.cpu1.icache.demand_misses::cpu1.inst 626240 # number of demand (read+write) misses
2327system.cpu1.icache.demand_misses::total 626240 # number of demand (read+write) misses
2328system.cpu1.icache.overall_misses::cpu1.inst 626240 # number of overall misses
2329system.cpu1.icache.overall_misses::total 626240 # number of overall misses
2330system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5487739407 # number of ReadReq miss cycles
2331system.cpu1.icache.ReadReq_miss_latency::total 5487739407 # number of ReadReq miss cycles
2332system.cpu1.icache.demand_miss_latency::cpu1.inst 5487739407 # number of demand (read+write) miss cycles
2333system.cpu1.icache.demand_miss_latency::total 5487739407 # number of demand (read+write) miss cycles
2334system.cpu1.icache.overall_miss_latency::cpu1.inst 5487739407 # number of overall miss cycles
2335system.cpu1.icache.overall_miss_latency::total 5487739407 # number of overall miss cycles
2336system.cpu1.icache.ReadReq_accesses::cpu1.inst 43583667 # number of ReadReq accesses(hits+misses)
2337system.cpu1.icache.ReadReq_accesses::total 43583667 # number of ReadReq accesses(hits+misses)
2338system.cpu1.icache.demand_accesses::cpu1.inst 43583667 # number of demand (read+write) accesses
2339system.cpu1.icache.demand_accesses::total 43583667 # number of demand (read+write) accesses
2340system.cpu1.icache.overall_accesses::cpu1.inst 43583667 # number of overall (read+write) accesses
2341system.cpu1.icache.overall_accesses::total 43583667 # number of overall (read+write) accesses
2342system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014369 # miss rate for ReadReq accesses
2343system.cpu1.icache.ReadReq_miss_rate::total 0.014369 # miss rate for ReadReq accesses
2344system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014369 # miss rate for demand accesses
2345system.cpu1.icache.demand_miss_rate::total 0.014369 # miss rate for demand accesses
2346system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014369 # miss rate for overall accesses
2347system.cpu1.icache.overall_miss_rate::total 0.014369 # miss rate for overall accesses
2348system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8762.997265 # average ReadReq miss latency
2349system.cpu1.icache.ReadReq_avg_miss_latency::total 8762.997265 # average ReadReq miss latency
2350system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency
2351system.cpu1.icache.demand_avg_miss_latency::total 8762.997265 # average overall miss latency
2352system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency
2353system.cpu1.icache.overall_avg_miss_latency::total 8762.997265 # average overall miss latency
2354system.cpu1.icache.blocked_cycles::no_mshrs 503899 # number of cycles access was blocked
2355system.cpu1.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked
2356system.cpu1.icache.blocked::no_mshrs 46132 # number of cycles access was blocked
2357system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
2358system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.922982 # average number of cycles each access was blocked
2359system.cpu1.icache.avg_blocked_cycles::no_targets 26 # average number of cycles each access was blocked

2324system.cpu1.icache.tags.tag_accesses 92297132 # Number of tag accesses
2325system.cpu1.icache.tags.data_accesses 92297132 # Number of data accesses
2326system.cpu1.icache.ReadReq_hits::cpu1.inst 45113050 # number of ReadReq hits
2327system.cpu1.icache.ReadReq_hits::total 45113050 # number of ReadReq hits
2328system.cpu1.icache.demand_hits::cpu1.inst 45113050 # number of demand (read+write) hits
2329system.cpu1.icache.demand_hits::total 45113050 # number of demand (read+write) hits
2330system.cpu1.icache.overall_hits::cpu1.inst 45113050 # number of overall hits
2331system.cpu1.icache.overall_hits::total 45113050 # number of overall hits
2332system.cpu1.icache.ReadReq_misses::cpu1.inst 699105 # number of ReadReq misses
2333system.cpu1.icache.ReadReq_misses::total 699105 # number of ReadReq misses
2334system.cpu1.icache.demand_misses::cpu1.inst 699105 # number of demand (read+write) misses
2335system.cpu1.icache.demand_misses::total 699105 # number of demand (read+write) misses
2336system.cpu1.icache.overall_misses::cpu1.inst 699105 # number of overall misses
2337system.cpu1.icache.overall_misses::total 699105 # number of overall misses
2338system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6808598319 # number of ReadReq miss cycles
2339system.cpu1.icache.ReadReq_miss_latency::total 6808598319 # number of ReadReq miss cycles
2340system.cpu1.icache.demand_miss_latency::cpu1.inst 6808598319 # number of demand (read+write) miss cycles
2341system.cpu1.icache.demand_miss_latency::total 6808598319 # number of demand (read+write) miss cycles
2342system.cpu1.icache.overall_miss_latency::cpu1.inst 6808598319 # number of overall miss cycles
2343system.cpu1.icache.overall_miss_latency::total 6808598319 # number of overall miss cycles
2344system.cpu1.icache.ReadReq_accesses::cpu1.inst 45812155 # number of ReadReq accesses(hits+misses)
2345system.cpu1.icache.ReadReq_accesses::total 45812155 # number of ReadReq accesses(hits+misses)
2346system.cpu1.icache.demand_accesses::cpu1.inst 45812155 # number of demand (read+write) accesses
2347system.cpu1.icache.demand_accesses::total 45812155 # number of demand (read+write) accesses
2348system.cpu1.icache.overall_accesses::cpu1.inst 45812155 # number of overall (read+write) accesses
2349system.cpu1.icache.overall_accesses::total 45812155 # number of overall (read+write) accesses
2350system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses
2351system.cpu1.icache.ReadReq_miss_rate::total 0.015260 # miss rate for ReadReq accesses
2352system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses
2353system.cpu1.icache.demand_miss_rate::total 0.015260 # miss rate for demand accesses
2354system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses
2355system.cpu1.icache.overall_miss_rate::total 0.015260 # miss rate for overall accesses
2356system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9739.021061 # average ReadReq miss latency
2357system.cpu1.icache.ReadReq_avg_miss_latency::total 9739.021061 # average ReadReq miss latency
2358system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency
2359system.cpu1.icache.demand_avg_miss_latency::total 9739.021061 # average overall miss latency
2360system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency
2361system.cpu1.icache.overall_avg_miss_latency::total 9739.021061 # average overall miss latency
2362system.cpu1.icache.blocked_cycles::no_mshrs 778427 # number of cycles access was blocked
2363system.cpu1.icache.blocked_cycles::no_targets 223 # number of cycles access was blocked
2364system.cpu1.icache.blocked::no_mshrs 55737 # number of cycles access was blocked
2365system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked
2366system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.966073 # average number of cycles each access was blocked
2367system.cpu1.icache.avg_blocked_cycles::no_targets 111.500000 # average number of cycles each access was blocked

2360system.cpu1.icache.fast_writes 0 # number of fast writes performed
2361system.cpu1.icache.cache_copies 0 # number of cache copies performed

2368system.cpu1.icache.fast_writes 0 # number of fast writes performed
2369system.cpu1.icache.cache_copies 0 # number of cache copies performed

2362system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22511 # number of ReadReq MSHR hits
2363system.cpu1.icache.ReadReq_mshr_hits::total 22511 # number of ReadReq MSHR hits
2364system.cpu1.icache.demand_mshr_hits::cpu1.inst 22511 # number of demand (read+write) MSHR hits
2365system.cpu1.icache.demand_mshr_hits::total 22511 # number of demand (read+write) MSHR hits
2366system.cpu1.icache.overall_mshr_hits::cpu1.inst 22511 # number of overall MSHR hits
2367system.cpu1.icache.overall_mshr_hits::total 22511 # number of overall MSHR hits
2368system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 603729 # number of ReadReq MSHR misses
2369system.cpu1.icache.ReadReq_mshr_misses::total 603729 # number of ReadReq MSHR misses
2370system.cpu1.icache.demand_mshr_misses::cpu1.inst 603729 # number of demand (read+write) MSHR misses
2371system.cpu1.icache.demand_mshr_misses::total 603729 # number of demand (read+write) MSHR misses
2372system.cpu1.icache.overall_mshr_misses::cpu1.inst 603729 # number of overall MSHR misses
2373system.cpu1.icache.overall_mshr_misses::total 603729 # number of overall MSHR misses

2370system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 26283 # number of ReadReq MSHR hits
2371system.cpu1.icache.ReadReq_mshr_hits::total 26283 # number of ReadReq MSHR hits
2372system.cpu1.icache.demand_mshr_hits::cpu1.inst 26283 # number of demand (read+write) MSHR hits
2373system.cpu1.icache.demand_mshr_hits::total 26283 # number of demand (read+write) MSHR hits
2374system.cpu1.icache.overall_mshr_hits::cpu1.inst 26283 # number of overall MSHR hits
2375system.cpu1.icache.overall_mshr_hits::total 26283 # number of overall MSHR hits
2376system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672822 # number of ReadReq MSHR misses
2377system.cpu1.icache.ReadReq_mshr_misses::total 672822 # number of ReadReq MSHR misses
2378system.cpu1.icache.demand_mshr_misses::cpu1.inst 672822 # number of demand (read+write) MSHR misses
2379system.cpu1.icache.demand_mshr_misses::total 672822 # number of demand (read+write) MSHR misses
2380system.cpu1.icache.overall_mshr_misses::cpu1.inst 672822 # number of overall MSHR misses
2381system.cpu1.icache.overall_mshr_misses::total 672822 # number of overall MSHR misses

2374system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2375system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
2376system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2377system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses

2382system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2383system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
2384system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2385system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses

2378system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5031797233 # number of ReadReq MSHR miss cycles
2379system.cpu1.icache.ReadReq_mshr_miss_latency::total 5031797233 # number of ReadReq MSHR miss cycles
2380system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5031797233 # number of demand (read+write) MSHR miss cycles
2381system.cpu1.icache.demand_mshr_miss_latency::total 5031797233 # number of demand (read+write) MSHR miss cycles
2382system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5031797233 # number of overall MSHR miss cycles
2383system.cpu1.icache.overall_mshr_miss_latency::total 5031797233 # number of overall MSHR miss cycles
2384system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9110000 # number of ReadReq MSHR uncacheable cycles
2385system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9110000 # number of ReadReq MSHR uncacheable cycles
2386system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9110000 # number of overall MSHR uncacheable cycles
2387system.cpu1.icache.overall_mshr_uncacheable_latency::total 9110000 # number of overall MSHR uncacheable cycles
2388system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for ReadReq accesses
2389system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013852 # mshr miss rate for ReadReq accesses
2390system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for demand accesses
2391system.cpu1.icache.demand_mshr_miss_rate::total 0.013852 # mshr miss rate for demand accesses
2392system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for overall accesses
2393system.cpu1.icache.overall_mshr_miss_rate::total 0.013852 # mshr miss rate for overall accesses
2394system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average ReadReq mshr miss latency
2395system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8334.529620 # average ReadReq mshr miss latency
2396system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency
2397system.cpu1.icache.demand_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency
2398system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency
2399system.cpu1.icache.overall_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency
2400system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average ReadReq mshr uncacheable latency
2401system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89313.725490 # average ReadReq mshr uncacheable latency
2402system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average overall mshr uncacheable latency
2403system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89313.725490 # average overall mshr uncacheable latency

2386system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6167077156 # number of ReadReq MSHR miss cycles
2387system.cpu1.icache.ReadReq_mshr_miss_latency::total 6167077156 # number of ReadReq MSHR miss cycles
2388system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6167077156 # number of demand (read+write) MSHR miss cycles
2389system.cpu1.icache.demand_mshr_miss_latency::total 6167077156 # number of demand (read+write) MSHR miss cycles
2390system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6167077156 # number of overall MSHR miss cycles
2391system.cpu1.icache.overall_mshr_miss_latency::total 6167077156 # number of overall MSHR miss cycles
2392system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13506000 # number of ReadReq MSHR uncacheable cycles
2393system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13506000 # number of ReadReq MSHR uncacheable cycles
2394system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13506000 # number of overall MSHR uncacheable cycles
2395system.cpu1.icache.overall_mshr_uncacheable_latency::total 13506000 # number of overall MSHR uncacheable cycles
2396system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for ReadReq accesses
2397system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014687 # mshr miss rate for ReadReq accesses
2398system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for demand accesses
2399system.cpu1.icache.demand_mshr_miss_rate::total 0.014687 # mshr miss rate for demand accesses
2400system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for overall accesses
2401system.cpu1.icache.overall_mshr_miss_rate::total 0.014687 # mshr miss rate for overall accesses
2402system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average ReadReq mshr miss latency
2403system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9165.986184 # average ReadReq mshr miss latency
2404system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency
2405system.cpu1.icache.demand_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency
2406system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency
2407system.cpu1.icache.overall_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency
2408system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average ReadReq mshr uncacheable latency
2409system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132411.764706 # average ReadReq mshr uncacheable latency
2410system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average overall mshr uncacheable latency
2411system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132411.764706 # average overall mshr uncacheable latency

2404system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate

2412system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate

2405system.cpu1.l2cache.prefetcher.num_hwpf_issued 189065 # number of hwpf issued
2406system.cpu1.l2cache.prefetcher.pfIdentified 189671 # number of prefetch candidates identified
2407system.cpu1.l2cache.prefetcher.pfBufferHit 541 # number of redundant prefetches already in prefetch queue

2413system.cpu1.l2cache.prefetcher.num_hwpf_issued 262736 # number of hwpf issued
2414system.cpu1.l2cache.prefetcher.pfIdentified 263407 # number of prefetch candidates identified
2415system.cpu1.l2cache.prefetcher.pfBufferHit 604 # number of redundant prefetches already in prefetch queue

2408system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2409system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size

2416system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2417system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size

2410system.cpu1.l2cache.prefetcher.pfSpanPage 56769 # number of prefetches not generated due to page crossing
2411system.cpu1.l2cache.tags.replacements 48663 # number of replacements
2412system.cpu1.l2cache.tags.tagsinuse 15171.630527 # Cycle average of tags in use
2413system.cpu1.l2cache.tags.total_refs 1474911 # Total number of references to valid blocks.
2414system.cpu1.l2cache.tags.sampled_refs 63236 # Sample count of references to valid blocks.
2415system.cpu1.l2cache.tags.avg_refs 23.323914 # Average number of references to valid blocks.

2418system.cpu1.l2cache.prefetcher.pfSpanPage 68017 # number of prefetches not generated due to page crossing
2419system.cpu1.l2cache.tags.replacements 62303 # number of replacements
2420system.cpu1.l2cache.tags.tagsinuse 15536.648070 # Cycle average of tags in use
2421system.cpu1.l2cache.tags.total_refs 1677232 # Total number of references to valid blocks.
2422system.cpu1.l2cache.tags.sampled_refs 76854 # Sample count of references to valid blocks.
2423system.cpu1.l2cache.tags.avg_refs 21.823614 # Average number of references to valid blocks.

2416system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2424system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

2417system.cpu1.l2cache.tags.occ_blocks::writebacks 8232.224686 # Average occupied blocks per requestor
2418system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.332834 # Average occupied blocks per requestor
2419system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.684874 # Average occupied blocks per requestor
2420system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3831.793838 # Average occupied blocks per requestor
2421system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2451.411988 # Average occupied blocks per requestor
2422system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 641.182307 # Average occupied blocks per requestor
2423system.cpu1.l2cache.tags.occ_percent::writebacks 0.502455 # Average percentage of cache occupancy
2424system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000692 # Average percentage of cache occupancy
2425system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000225 # Average percentage of cache occupancy
2426system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233874 # Average percentage of cache occupancy
2427system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.149622 # Average percentage of cache occupancy
2428system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.039135 # Average percentage of cache occupancy
2429system.cpu1.l2cache.tags.occ_percent::total 0.926003 # Average percentage of cache occupancy
2430system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1118 # Occupied blocks per task id
2431system.cpu1.l2cache.tags.occ_task_id_blocks::1023 35 # Occupied blocks per task id
2432system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13420 # Occupied blocks per task id
2433system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id
2434system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 930 # Occupied blocks per task id
2435system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 167 # Occupied blocks per task id
2436system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
2437system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
2438system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
2439system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
2440system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8633 # Occupied blocks per task id
2441system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4319 # Occupied blocks per task id
2442system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068237 # Percentage of cache occupancy per task id
2443system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002136 # Percentage of cache occupancy per task id
2444system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819092 # Percentage of cache occupancy per task id
2445system.cpu1.l2cache.tags.tag_accesses 27275895 # Number of tag accesses
2446system.cpu1.l2cache.tags.data_accesses 27275895 # Number of data accesses
2447system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 15350 # number of ReadReq hits
2448system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7200 # number of ReadReq hits
2449system.cpu1.l2cache.ReadReq_hits::total 22550 # number of ReadReq hits
2450system.cpu1.l2cache.Writeback_hits::writebacks 116768 # number of Writeback hits
2451system.cpu1.l2cache.Writeback_hits::total 116768 # number of Writeback hits
2452system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1559 # number of UpgradeReq hits
2453system.cpu1.l2cache.UpgradeReq_hits::total 1559 # number of UpgradeReq hits
2454system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 954 # number of SCUpgradeReq hits
2455system.cpu1.l2cache.SCUpgradeReq_hits::total 954 # number of SCUpgradeReq hits
2456system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27353 # number of ReadExReq hits
2457system.cpu1.l2cache.ReadExReq_hits::total 27353 # number of ReadExReq hits
2458system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 586865 # number of ReadCleanReq hits
2459system.cpu1.l2cache.ReadCleanReq_hits::total 586865 # number of ReadCleanReq hits
2460system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101704 # number of ReadSharedReq hits
2461system.cpu1.l2cache.ReadSharedReq_hits::total 101704 # number of ReadSharedReq hits
2462system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 15350 # number of demand (read+write) hits
2463system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7200 # number of demand (read+write) hits
2464system.cpu1.l2cache.demand_hits::cpu1.inst 586865 # number of demand (read+write) hits
2465system.cpu1.l2cache.demand_hits::cpu1.data 129057 # number of demand (read+write) hits
2466system.cpu1.l2cache.demand_hits::total 738472 # number of demand (read+write) hits
2467system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 15350 # number of overall hits
2468system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7200 # number of overall hits
2469system.cpu1.l2cache.overall_hits::cpu1.inst 586865 # number of overall hits
2470system.cpu1.l2cache.overall_hits::cpu1.data 129057 # number of overall hits
2471system.cpu1.l2cache.overall_hits::total 738472 # number of overall hits
2472system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 400 # number of ReadReq misses
2473system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 278 # number of ReadReq misses
2474system.cpu1.l2cache.ReadReq_misses::total 678 # number of ReadReq misses

2425system.cpu1.l2cache.tags.occ_blocks::writebacks 6569.267487 # Average occupied blocks per requestor
2426system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.374590 # Average occupied blocks per requestor
2427system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.390464 # Average occupied blocks per requestor
2428system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4943.655897 # Average occupied blocks per requestor
2429system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2538.739672 # Average occupied blocks per requestor
2430system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1470.219959 # Average occupied blocks per requestor
2431system.cpu1.l2cache.tags.occ_percent::writebacks 0.400956 # Average percentage of cache occupancy
2432system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000877 # Average percentage of cache occupancy
2433system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000024 # Average percentage of cache occupancy
2434system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301737 # Average percentage of cache occupancy
2435system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.154952 # Average percentage of cache occupancy
2436system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.089735 # Average percentage of cache occupancy
2437system.cpu1.l2cache.tags.occ_percent::total 0.948282 # Average percentage of cache occupancy
2438system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1250 # Occupied blocks per task id
2439system.cpu1.l2cache.tags.occ_task_id_blocks::1023 33 # Occupied blocks per task id
2440system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13268 # Occupied blocks per task id
2441system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id
2442system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 890 # Occupied blocks per task id
2443system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 342 # Occupied blocks per task id
2444system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
2445system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id
2446system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
2447system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
2448system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8543 # Occupied blocks per task id
2449system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4263 # Occupied blocks per task id
2450system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076294 # Percentage of cache occupancy per task id
2451system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002014 # Percentage of cache occupancy per task id
2452system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.809814 # Percentage of cache occupancy per task id
2453system.cpu1.l2cache.tags.tag_accesses 30842090 # Number of tag accesses
2454system.cpu1.l2cache.tags.data_accesses 30842090 # Number of data accesses
2455system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19102 # number of ReadReq hits
2456system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7340 # number of ReadReq hits
2457system.cpu1.l2cache.ReadReq_hits::total 26442 # number of ReadReq hits
2458system.cpu1.l2cache.Writeback_hits::writebacks 137798 # number of Writeback hits
2459system.cpu1.l2cache.Writeback_hits::total 137798 # number of Writeback hits
2460system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1915 # number of UpgradeReq hits
2461system.cpu1.l2cache.UpgradeReq_hits::total 1915 # number of UpgradeReq hits
2462system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1089 # number of SCUpgradeReq hits
2463system.cpu1.l2cache.SCUpgradeReq_hits::total 1089 # number of SCUpgradeReq hits
2464system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37080 # number of ReadExReq hits
2465system.cpu1.l2cache.ReadExReq_hits::total 37080 # number of ReadExReq hits
2466system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 650319 # number of ReadCleanReq hits
2467system.cpu1.l2cache.ReadCleanReq_hits::total 650319 # number of ReadCleanReq hits
2468system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 128580 # number of ReadSharedReq hits
2469system.cpu1.l2cache.ReadSharedReq_hits::total 128580 # number of ReadSharedReq hits
2470system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19102 # number of demand (read+write) hits
2471system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7340 # number of demand (read+write) hits
2472system.cpu1.l2cache.demand_hits::cpu1.inst 650319 # number of demand (read+write) hits
2473system.cpu1.l2cache.demand_hits::cpu1.data 165660 # number of demand (read+write) hits
2474system.cpu1.l2cache.demand_hits::total 842421 # number of demand (read+write) hits
2475system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19102 # number of overall hits
2476system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7340 # number of overall hits
2477system.cpu1.l2cache.overall_hits::cpu1.inst 650319 # number of overall hits
2478system.cpu1.l2cache.overall_hits::cpu1.data 165660 # number of overall hits
2479system.cpu1.l2cache.overall_hits::total 842421 # number of overall hits
2480system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 434 # number of ReadReq misses
2481system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 283 # number of ReadReq misses
2482system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses

2475system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
2476system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses

2483system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
2484system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses

2477system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28175 # number of UpgradeReq misses
2478system.cpu1.l2cache.UpgradeReq_misses::total 28175 # number of UpgradeReq misses
2479system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22720 # number of SCUpgradeReq misses
2480system.cpu1.l2cache.SCUpgradeReq_misses::total 22720 # number of SCUpgradeReq misses
2481system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33751 # number of ReadExReq misses
2482system.cpu1.l2cache.ReadExReq_misses::total 33751 # number of ReadExReq misses
2483system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16862 # number of ReadCleanReq misses
2484system.cpu1.l2cache.ReadCleanReq_misses::total 16862 # number of ReadCleanReq misses
2485system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70088 # number of ReadSharedReq misses
2486system.cpu1.l2cache.ReadSharedReq_misses::total 70088 # number of ReadSharedReq misses
2487system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 400 # number of demand (read+write) misses
2488system.cpu1.l2cache.demand_misses::cpu1.itb.walker 278 # number of demand (read+write) misses
2489system.cpu1.l2cache.demand_misses::cpu1.inst 16862 # number of demand (read+write) misses
2490system.cpu1.l2cache.demand_misses::cpu1.data 103839 # number of demand (read+write) misses
2491system.cpu1.l2cache.demand_misses::total 121379 # number of demand (read+write) misses
2492system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 400 # number of overall misses
2493system.cpu1.l2cache.overall_misses::cpu1.itb.walker 278 # number of overall misses
2494system.cpu1.l2cache.overall_misses::cpu1.inst 16862 # number of overall misses
2495system.cpu1.l2cache.overall_misses::cpu1.data 103839 # number of overall misses
2496system.cpu1.l2cache.overall_misses::total 121379 # number of overall misses
2497system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8778500 # number of ReadReq miss cycles
2498system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5791500 # number of ReadReq miss cycles
2499system.cpu1.l2cache.ReadReq_miss_latency::total 14570000 # number of ReadReq miss cycles
2500system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536726500 # number of UpgradeReq miss cycles
2501system.cpu1.l2cache.UpgradeReq_miss_latency::total 536726500 # number of UpgradeReq miss cycles
2502system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 459045500 # number of SCUpgradeReq miss cycles
2503system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 459045500 # number of SCUpgradeReq miss cycles
2504system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 847500 # number of SCUpgradeFailReq miss cycles
2505system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 847500 # number of SCUpgradeFailReq miss cycles
2506system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1378926000 # number of ReadExReq miss cycles
2507system.cpu1.l2cache.ReadExReq_miss_latency::total 1378926000 # number of ReadExReq miss cycles
2508system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 607258000 # number of ReadCleanReq miss cycles
2509system.cpu1.l2cache.ReadCleanReq_miss_latency::total 607258000 # number of ReadCleanReq miss cycles
2510system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1556092998 # number of ReadSharedReq miss cycles
2511system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1556092998 # number of ReadSharedReq miss cycles
2512system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8778500 # number of demand (read+write) miss cycles
2513system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5791500 # number of demand (read+write) miss cycles
2514system.cpu1.l2cache.demand_miss_latency::cpu1.inst 607258000 # number of demand (read+write) miss cycles
2515system.cpu1.l2cache.demand_miss_latency::cpu1.data 2935018998 # number of demand (read+write) miss cycles
2516system.cpu1.l2cache.demand_miss_latency::total 3556846998 # number of demand (read+write) miss cycles
2517system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8778500 # number of overall miss cycles
2518system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5791500 # number of overall miss cycles
2519system.cpu1.l2cache.overall_miss_latency::cpu1.inst 607258000 # number of overall miss cycles
2520system.cpu1.l2cache.overall_miss_latency::cpu1.data 2935018998 # number of overall miss cycles
2521system.cpu1.l2cache.overall_miss_latency::total 3556846998 # number of overall miss cycles
2522system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 15750 # number of ReadReq accesses(hits+misses)
2523system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7478 # number of ReadReq accesses(hits+misses)
2524system.cpu1.l2cache.ReadReq_accesses::total 23228 # number of ReadReq accesses(hits+misses)
2525system.cpu1.l2cache.Writeback_accesses::writebacks 116769 # number of Writeback accesses(hits+misses)
2526system.cpu1.l2cache.Writeback_accesses::total 116769 # number of Writeback accesses(hits+misses)
2527system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29734 # number of UpgradeReq accesses(hits+misses)
2528system.cpu1.l2cache.UpgradeReq_accesses::total 29734 # number of UpgradeReq accesses(hits+misses)
2529system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23674 # number of SCUpgradeReq accesses(hits+misses)
2530system.cpu1.l2cache.SCUpgradeReq_accesses::total 23674 # number of SCUpgradeReq accesses(hits+misses)
2531system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61104 # number of ReadExReq accesses(hits+misses)
2532system.cpu1.l2cache.ReadExReq_accesses::total 61104 # number of ReadExReq accesses(hits+misses)
2533system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 603727 # number of ReadCleanReq accesses(hits+misses)
2534system.cpu1.l2cache.ReadCleanReq_accesses::total 603727 # number of ReadCleanReq accesses(hits+misses)
2535system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171792 # number of ReadSharedReq accesses(hits+misses)
2536system.cpu1.l2cache.ReadSharedReq_accesses::total 171792 # number of ReadSharedReq accesses(hits+misses)
2537system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 15750 # number of demand (read+write) accesses
2538system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7478 # number of demand (read+write) accesses
2539system.cpu1.l2cache.demand_accesses::cpu1.inst 603727 # number of demand (read+write) accesses
2540system.cpu1.l2cache.demand_accesses::cpu1.data 232896 # number of demand (read+write) accesses
2541system.cpu1.l2cache.demand_accesses::total 859851 # number of demand (read+write) accesses
2542system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 15750 # number of overall (read+write) accesses
2543system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7478 # number of overall (read+write) accesses
2544system.cpu1.l2cache.overall_accesses::cpu1.inst 603727 # number of overall (read+write) accesses
2545system.cpu1.l2cache.overall_accesses::cpu1.data 232896 # number of overall (read+write) accesses
2546system.cpu1.l2cache.overall_accesses::total 859851 # number of overall (read+write) accesses
2547system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for ReadReq accesses
2548system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037176 # miss rate for ReadReq accesses
2549system.cpu1.l2cache.ReadReq_miss_rate::total 0.029189 # miss rate for ReadReq accesses
2550system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses
2551system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses
2552system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.947568 # miss rate for UpgradeReq accesses
2553system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947568 # miss rate for UpgradeReq accesses
2554system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.959703 # miss rate for SCUpgradeReq accesses
2555system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.959703 # miss rate for SCUpgradeReq accesses
2556system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.552353 # miss rate for ReadExReq accesses
2557system.cpu1.l2cache.ReadExReq_miss_rate::total 0.552353 # miss rate for ReadExReq accesses
2558system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027930 # miss rate for ReadCleanReq accesses
2559system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027930 # miss rate for ReadCleanReq accesses
2560system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.407982 # miss rate for ReadSharedReq accesses
2561system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.407982 # miss rate for ReadSharedReq accesses
2562system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for demand accesses
2563system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037176 # miss rate for demand accesses
2564system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027930 # miss rate for demand accesses
2565system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.445860 # miss rate for demand accesses
2566system.cpu1.l2cache.demand_miss_rate::total 0.141163 # miss rate for demand accesses
2567system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for overall accesses
2568system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037176 # miss rate for overall accesses
2569system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027930 # miss rate for overall accesses
2570system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.445860 # miss rate for overall accesses
2571system.cpu1.l2cache.overall_miss_rate::total 0.141163 # miss rate for overall accesses
2572system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average ReadReq miss latency
2573system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20832.733813 # average ReadReq miss latency
2574system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21489.675516 # average ReadReq miss latency
2575system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19049.742680 # average UpgradeReq miss latency
2576system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19049.742680 # average UpgradeReq miss latency
2577system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20204.467430 # average SCUpgradeReq miss latency
2578system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20204.467430 # average SCUpgradeReq miss latency

2485system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29244 # number of UpgradeReq misses
2486system.cpu1.l2cache.UpgradeReq_misses::total 29244 # number of UpgradeReq misses
2487system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22424 # number of SCUpgradeReq misses
2488system.cpu1.l2cache.SCUpgradeReq_misses::total 22424 # number of SCUpgradeReq misses
2489system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36071 # number of ReadExReq misses
2490system.cpu1.l2cache.ReadExReq_misses::total 36071 # number of ReadExReq misses
2491system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22492 # number of ReadCleanReq misses
2492system.cpu1.l2cache.ReadCleanReq_misses::total 22492 # number of ReadCleanReq misses
2493system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 72430 # number of ReadSharedReq misses
2494system.cpu1.l2cache.ReadSharedReq_misses::total 72430 # number of ReadSharedReq misses
2495system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 434 # number of demand (read+write) misses
2496system.cpu1.l2cache.demand_misses::cpu1.itb.walker 283 # number of demand (read+write) misses
2497system.cpu1.l2cache.demand_misses::cpu1.inst 22492 # number of demand (read+write) misses
2498system.cpu1.l2cache.demand_misses::cpu1.data 108501 # number of demand (read+write) misses
2499system.cpu1.l2cache.demand_misses::total 131710 # number of demand (read+write) misses
2500system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 434 # number of overall misses
2501system.cpu1.l2cache.overall_misses::cpu1.itb.walker 283 # number of overall misses
2502system.cpu1.l2cache.overall_misses::cpu1.inst 22492 # number of overall misses
2503system.cpu1.l2cache.overall_misses::cpu1.data 108501 # number of overall misses
2504system.cpu1.l2cache.overall_misses::total 131710 # number of overall misses
2505system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10853500 # number of ReadReq miss cycles
2506system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5913500 # number of ReadReq miss cycles
2507system.cpu1.l2cache.ReadReq_miss_latency::total 16767000 # number of ReadReq miss cycles
2508system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 593983499 # number of UpgradeReq miss cycles
2509system.cpu1.l2cache.UpgradeReq_miss_latency::total 593983499 # number of UpgradeReq miss cycles
2510system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 472238000 # number of SCUpgradeReq miss cycles
2511system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 472238000 # number of SCUpgradeReq miss cycles
2512system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1967000 # number of SCUpgradeFailReq miss cycles
2513system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1967000 # number of SCUpgradeFailReq miss cycles
2514system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1909781999 # number of ReadExReq miss cycles
2515system.cpu1.l2cache.ReadExReq_miss_latency::total 1909781999 # number of ReadExReq miss cycles
2516system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1248275500 # number of ReadCleanReq miss cycles
2517system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1248275500 # number of ReadCleanReq miss cycles
2518system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1835931492 # number of ReadSharedReq miss cycles
2519system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1835931492 # number of ReadSharedReq miss cycles
2520system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10853500 # number of demand (read+write) miss cycles
2521system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5913500 # number of demand (read+write) miss cycles
2522system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1248275500 # number of demand (read+write) miss cycles
2523system.cpu1.l2cache.demand_miss_latency::cpu1.data 3745713491 # number of demand (read+write) miss cycles
2524system.cpu1.l2cache.demand_miss_latency::total 5010755991 # number of demand (read+write) miss cycles
2525system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10853500 # number of overall miss cycles
2526system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5913500 # number of overall miss cycles
2527system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1248275500 # number of overall miss cycles
2528system.cpu1.l2cache.overall_miss_latency::cpu1.data 3745713491 # number of overall miss cycles
2529system.cpu1.l2cache.overall_miss_latency::total 5010755991 # number of overall miss cycles
2530system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19536 # number of ReadReq accesses(hits+misses)
2531system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7623 # number of ReadReq accesses(hits+misses)
2532system.cpu1.l2cache.ReadReq_accesses::total 27159 # number of ReadReq accesses(hits+misses)
2533system.cpu1.l2cache.Writeback_accesses::writebacks 137799 # number of Writeback accesses(hits+misses)
2534system.cpu1.l2cache.Writeback_accesses::total 137799 # number of Writeback accesses(hits+misses)
2535system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31159 # number of UpgradeReq accesses(hits+misses)
2536system.cpu1.l2cache.UpgradeReq_accesses::total 31159 # number of UpgradeReq accesses(hits+misses)
2537system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23513 # number of SCUpgradeReq accesses(hits+misses)
2538system.cpu1.l2cache.SCUpgradeReq_accesses::total 23513 # number of SCUpgradeReq accesses(hits+misses)
2539system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73151 # number of ReadExReq accesses(hits+misses)
2540system.cpu1.l2cache.ReadExReq_accesses::total 73151 # number of ReadExReq accesses(hits+misses)
2541system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 672811 # number of ReadCleanReq accesses(hits+misses)
2542system.cpu1.l2cache.ReadCleanReq_accesses::total 672811 # number of ReadCleanReq accesses(hits+misses)
2543system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 201010 # number of ReadSharedReq accesses(hits+misses)
2544system.cpu1.l2cache.ReadSharedReq_accesses::total 201010 # number of ReadSharedReq accesses(hits+misses)
2545system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19536 # number of demand (read+write) accesses
2546system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7623 # number of demand (read+write) accesses
2547system.cpu1.l2cache.demand_accesses::cpu1.inst 672811 # number of demand (read+write) accesses
2548system.cpu1.l2cache.demand_accesses::cpu1.data 274161 # number of demand (read+write) accesses
2549system.cpu1.l2cache.demand_accesses::total 974131 # number of demand (read+write) accesses
2550system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19536 # number of overall (read+write) accesses
2551system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7623 # number of overall (read+write) accesses
2552system.cpu1.l2cache.overall_accesses::cpu1.inst 672811 # number of overall (read+write) accesses
2553system.cpu1.l2cache.overall_accesses::cpu1.data 274161 # number of overall (read+write) accesses
2554system.cpu1.l2cache.overall_accesses::total 974131 # number of overall (read+write) accesses
2555system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022215 # miss rate for ReadReq accesses
2556system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037124 # miss rate for ReadReq accesses
2557system.cpu1.l2cache.ReadReq_miss_rate::total 0.026400 # miss rate for ReadReq accesses
2558system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses
2559system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses
2560system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.938541 # miss rate for UpgradeReq accesses
2561system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.938541 # miss rate for UpgradeReq accesses
2562system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.953685 # miss rate for SCUpgradeReq accesses
2563system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.953685 # miss rate for SCUpgradeReq accesses
2564system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.493103 # miss rate for ReadExReq accesses
2565system.cpu1.l2cache.ReadExReq_miss_rate::total 0.493103 # miss rate for ReadExReq accesses
2566system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.033430 # miss rate for ReadCleanReq accesses
2567system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.033430 # miss rate for ReadCleanReq accesses
2568system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.360330 # miss rate for ReadSharedReq accesses
2569system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.360330 # miss rate for ReadSharedReq accesses
2570system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022215 # miss rate for demand accesses
2571system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037124 # miss rate for demand accesses
2572system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033430 # miss rate for demand accesses
2573system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.395757 # miss rate for demand accesses
2574system.cpu1.l2cache.demand_miss_rate::total 0.135208 # miss rate for demand accesses
2575system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022215 # miss rate for overall accesses
2576system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037124 # miss rate for overall accesses
2577system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033430 # miss rate for overall accesses
2578system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.395757 # miss rate for overall accesses
2579system.cpu1.l2cache.overall_miss_rate::total 0.135208 # miss rate for overall accesses
2580system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25008.064516 # average ReadReq miss latency
2581system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20895.759717 # average ReadReq miss latency
2582system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23384.937238 # average ReadReq miss latency
2583system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20311.294590 # average UpgradeReq miss latency
2584system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20311.294590 # average UpgradeReq miss latency
2585system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21059.489832 # average SCUpgradeReq miss latency
2586system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21059.489832 # average SCUpgradeReq miss latency

2579system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
2580system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency

2587system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
2588system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency

2581system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40855.856123 # average ReadExReq miss latency
2582system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40855.856123 # average ReadExReq miss latency
2583system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36013.402918 # average ReadCleanReq miss latency
2584system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36013.402918 # average ReadCleanReq miss latency
2585system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22201.988900 # average ReadSharedReq miss latency
2586system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22201.988900 # average ReadSharedReq miss latency
2587system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average overall miss latency
2588system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20832.733813 # average overall miss latency
2589system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36013.402918 # average overall miss latency
2590system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28265.093058 # average overall miss latency
2591system.cpu1.l2cache.demand_avg_miss_latency::total 29303.643942 # average overall miss latency
2592system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average overall miss latency
2593system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20832.733813 # average overall miss latency
2594system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36013.402918 # average overall miss latency
2595system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28265.093058 # average overall miss latency
2596system.cpu1.l2cache.overall_avg_miss_latency::total 29303.643942 # average overall miss latency
2597system.cpu1.l2cache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked

2589system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52945.080508 # average ReadExReq miss latency
2590system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52945.080508 # average ReadExReq miss latency
2591system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 55498.643962 # average ReadCleanReq miss latency
2592system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 55498.643962 # average ReadCleanReq miss latency
2593system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25347.666602 # average ReadSharedReq miss latency
2594system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25347.666602 # average ReadSharedReq miss latency
2595system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25008.064516 # average overall miss latency
2596system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20895.759717 # average overall miss latency
2597system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 55498.643962 # average overall miss latency
2598system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34522.386807 # average overall miss latency
2599system.cpu1.l2cache.demand_avg_miss_latency::total 38043.853853 # average overall miss latency
2600system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25008.064516 # average overall miss latency
2601system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20895.759717 # average overall miss latency
2602system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 55498.643962 # average overall miss latency
2603system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34522.386807 # average overall miss latency
2604system.cpu1.l2cache.overall_avg_miss_latency::total 38043.853853 # average overall miss latency
2605system.cpu1.l2cache.blocked_cycles::no_mshrs 135 # number of cycles access was blocked

2598system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked

2606system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked

2599system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked

2607system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked

2600system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked

2608system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked

2601system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 22.800000 # average number of cycles each access was blocked

2609system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 22.500000 # average number of cycles each access was blocked

2602system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2603system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2604system.cpu1.l2cache.cache_copies 0 # number of cache copies performed

2610system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2611system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2612system.cpu1.l2cache.cache_copies 0 # number of cache copies performed

2605system.cpu1.l2cache.writebacks::writebacks 30215 # number of writebacks
2606system.cpu1.l2cache.writebacks::total 30215 # number of writebacks
2607system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits

2613system.cpu1.l2cache.writebacks::writebacks 35002 # number of writebacks
2614system.cpu1.l2cache.writebacks::total 35002 # number of writebacks
2615system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
2616system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits

2608system.cpu1.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits

2617system.cpu1.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits

2609system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 420 # number of ReadExReq MSHR hits
2610system.cpu1.l2cache.ReadExReq_mshr_hits::total 420 # number of ReadExReq MSHR hits
2611system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits
2612system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
2613system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 76 # number of ReadSharedReq MSHR hits
2614system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 76 # number of ReadSharedReq MSHR hits
2615system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits
2616system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
2617system.cpu1.l2cache.demand_mshr_hits::cpu1.data 496 # number of demand (read+write) MSHR hits
2618system.cpu1.l2cache.demand_mshr_hits::total 516 # number of demand (read+write) MSHR hits
2619system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits
2620system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
2621system.cpu1.l2cache.overall_mshr_hits::cpu1.data 496 # number of overall MSHR hits
2622system.cpu1.l2cache.overall_mshr_hits::total 516 # number of overall MSHR hits
2623system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 400 # number of ReadReq MSHR misses
2624system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 264 # number of ReadReq MSHR misses
2625system.cpu1.l2cache.ReadReq_mshr_misses::total 664 # number of ReadReq MSHR misses

2618system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1611 # number of ReadExReq MSHR hits
2619system.cpu1.l2cache.ReadExReq_mshr_hits::total 1611 # number of ReadExReq MSHR hits
2620system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 19 # number of ReadCleanReq MSHR hits
2621system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 19 # number of ReadCleanReq MSHR hits
2622system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 165 # number of ReadSharedReq MSHR hits
2623system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 165 # number of ReadSharedReq MSHR hits
2624system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
2625system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits
2626system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 19 # number of demand (read+write) MSHR hits
2627system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1776 # number of demand (read+write) MSHR hits
2628system.cpu1.l2cache.demand_mshr_hits::total 1809 # number of demand (read+write) MSHR hits
2629system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
2630system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits
2631system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 19 # number of overall MSHR hits
2632system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1776 # number of overall MSHR hits
2633system.cpu1.l2cache.overall_mshr_hits::total 1809 # number of overall MSHR hits
2634system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 433 # number of ReadReq MSHR misses
2635system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 270 # number of ReadReq MSHR misses
2636system.cpu1.l2cache.ReadReq_mshr_misses::total 703 # number of ReadReq MSHR misses

2626system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
2627system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses

2637system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
2638system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses

2628system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2169 # number of CleanEvict MSHR misses
2629system.cpu1.l2cache.CleanEvict_mshr_misses::total 2169 # number of CleanEvict MSHR misses
2630system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23681 # number of HardPFReq MSHR misses
2631system.cpu1.l2cache.HardPFReq_mshr_misses::total 23681 # number of HardPFReq MSHR misses
2632system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28175 # number of UpgradeReq MSHR misses
2633system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28175 # number of UpgradeReq MSHR misses
2634system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22720 # number of SCUpgradeReq MSHR misses
2635system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22720 # number of SCUpgradeReq MSHR misses
2636system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33331 # number of ReadExReq MSHR misses
2637system.cpu1.l2cache.ReadExReq_mshr_misses::total 33331 # number of ReadExReq MSHR misses
2638system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16856 # number of ReadCleanReq MSHR misses
2639system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16856 # number of ReadCleanReq MSHR misses
2640system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70012 # number of ReadSharedReq MSHR misses
2641system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70012 # number of ReadSharedReq MSHR misses
2642system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 400 # number of demand (read+write) MSHR misses
2643system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 264 # number of demand (read+write) MSHR misses
2644system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16856 # number of demand (read+write) MSHR misses
2645system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103343 # number of demand (read+write) MSHR misses
2646system.cpu1.l2cache.demand_mshr_misses::total 120863 # number of demand (read+write) MSHR misses
2647system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 400 # number of overall MSHR misses
2648system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 264 # number of overall MSHR misses
2649system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16856 # number of overall MSHR misses
2650system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103343 # number of overall MSHR misses
2651system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23681 # number of overall MSHR misses
2652system.cpu1.l2cache.overall_mshr_misses::total 144544 # number of overall MSHR misses

2639system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2881 # number of CleanEvict MSHR misses
2640system.cpu1.l2cache.CleanEvict_mshr_misses::total 2881 # number of CleanEvict MSHR misses
2641system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35799 # number of HardPFReq MSHR misses
2642system.cpu1.l2cache.HardPFReq_mshr_misses::total 35799 # number of HardPFReq MSHR misses
2643system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29244 # number of UpgradeReq MSHR misses
2644system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29244 # number of UpgradeReq MSHR misses
2645system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22424 # number of SCUpgradeReq MSHR misses
2646system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22424 # number of SCUpgradeReq MSHR misses
2647system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34460 # number of ReadExReq MSHR misses
2648system.cpu1.l2cache.ReadExReq_mshr_misses::total 34460 # number of ReadExReq MSHR misses
2649system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 22473 # number of ReadCleanReq MSHR misses
2650system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 22473 # number of ReadCleanReq MSHR misses
2651system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 72265 # number of ReadSharedReq MSHR misses
2652system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 72265 # number of ReadSharedReq MSHR misses
2653system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 433 # number of demand (read+write) MSHR misses
2654system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 270 # number of demand (read+write) MSHR misses
2655system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22473 # number of demand (read+write) MSHR misses
2656system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106725 # number of demand (read+write) MSHR misses
2657system.cpu1.l2cache.demand_mshr_misses::total 129901 # number of demand (read+write) MSHR misses
2658system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 433 # number of overall MSHR misses
2659system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 270 # number of overall MSHR misses
2660system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22473 # number of overall MSHR misses
2661system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106725 # number of overall MSHR misses
2662system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35799 # number of overall MSHR misses
2663system.cpu1.l2cache.overall_mshr_misses::total 165700 # number of overall MSHR misses

2653system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable

2664system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable

2654system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable
2655system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14588 # number of ReadReq MSHR uncacheable
2656system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
2657system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable

2665system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17062 # number of ReadReq MSHR uncacheable
2666system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17164 # number of ReadReq MSHR uncacheable
2667system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
2668system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable

2658system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses

2669system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses

2659system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses
2660system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26403 # number of overall MSHR uncacheable misses
2661system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of ReadReq MSHR miss cycles
2662system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4031500 # number of ReadReq MSHR miss cycles
2663system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10410000 # number of ReadReq MSHR miss cycles
2664system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1037990412 # number of HardPFReq MSHR miss cycles
2665system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1037990412 # number of HardPFReq MSHR miss cycles
2666system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 463119500 # number of UpgradeReq MSHR miss cycles
2667system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 463119500 # number of UpgradeReq MSHR miss cycles
2668system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 352921500 # number of SCUpgradeReq MSHR miss cycles
2669system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 352921500 # number of SCUpgradeReq MSHR miss cycles
2670system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 751500 # number of SCUpgradeFailReq MSHR miss cycles
2671system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 751500 # number of SCUpgradeFailReq MSHR miss cycles
2672system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1120597500 # number of ReadExReq MSHR miss cycles
2673system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1120597500 # number of ReadExReq MSHR miss cycles
2674system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 506014500 # number of ReadCleanReq MSHR miss cycles
2675system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 506014500 # number of ReadCleanReq MSHR miss cycles
2676system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1134157998 # number of ReadSharedReq MSHR miss cycles
2677system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1134157998 # number of ReadSharedReq MSHR miss cycles
2678system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of demand (read+write) MSHR miss cycles
2679system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4031500 # number of demand (read+write) MSHR miss cycles
2680system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 506014500 # number of demand (read+write) MSHR miss cycles
2681system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2254755498 # number of demand (read+write) MSHR miss cycles
2682system.cpu1.l2cache.demand_mshr_miss_latency::total 2771179998 # number of demand (read+write) MSHR miss cycles
2683system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of overall MSHR miss cycles
2684system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4031500 # number of overall MSHR miss cycles
2685system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 506014500 # number of overall MSHR miss cycles
2686system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2254755498 # number of overall MSHR miss cycles
2687system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1037990412 # number of overall MSHR miss cycles
2688system.cpu1.l2cache.overall_mshr_miss_latency::total 3809170410 # number of overall MSHR miss cycles
2689system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8345000 # number of ReadReq MSHR uncacheable cycles
2690system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2233165500 # number of ReadReq MSHR uncacheable cycles
2691system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2241510500 # number of ReadReq MSHR uncacheable cycles
2692system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1776007998 # number of WriteReq MSHR uncacheable cycles
2693system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1776007998 # number of WriteReq MSHR uncacheable cycles
2694system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8345000 # number of overall MSHR uncacheable cycles
2695system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4009173498 # number of overall MSHR uncacheable cycles
2696system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4017518498 # number of overall MSHR uncacheable cycles
2697system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for ReadReq accesses
2698system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for ReadReq accesses
2699system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028586 # mshr miss rate for ReadReq accesses
2700system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses
2701system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses

2670system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31403 # number of overall MSHR uncacheable misses
2671system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31505 # number of overall MSHR uncacheable misses
2672system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8235500 # number of ReadReq MSHR miss cycles
2673system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4129500 # number of ReadReq MSHR miss cycles
2674system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12365000 # number of ReadReq MSHR miss cycles
2675system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1812441817 # number of HardPFReq MSHR miss cycles
2676system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1812441817 # number of HardPFReq MSHR miss cycles
2677system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 689767998 # number of UpgradeReq MSHR miss cycles
2678system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 689767998 # number of UpgradeReq MSHR miss cycles
2679system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 415217500 # number of SCUpgradeReq MSHR miss cycles
2680system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 415217500 # number of SCUpgradeReq MSHR miss cycles
2681system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1841000 # number of SCUpgradeFailReq MSHR miss cycles
2682system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1841000 # number of SCUpgradeFailReq MSHR miss cycles
2683system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1591439000 # number of ReadExReq MSHR miss cycles
2684system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1591439000 # number of ReadExReq MSHR miss cycles
2685system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1112203000 # number of ReadCleanReq MSHR miss cycles
2686system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1112203000 # number of ReadCleanReq MSHR miss cycles
2687system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1393604492 # number of ReadSharedReq MSHR miss cycles
2688system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1393604492 # number of ReadSharedReq MSHR miss cycles
2689system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8235500 # number of demand (read+write) MSHR miss cycles
2690system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4129500 # number of demand (read+write) MSHR miss cycles
2691system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1112203000 # number of demand (read+write) MSHR miss cycles
2692system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2985043492 # number of demand (read+write) MSHR miss cycles
2693system.cpu1.l2cache.demand_mshr_miss_latency::total 4109611492 # number of demand (read+write) MSHR miss cycles
2694system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8235500 # number of overall MSHR miss cycles
2695system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4129500 # number of overall MSHR miss cycles
2696system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1112203000 # number of overall MSHR miss cycles
2697system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2985043492 # number of overall MSHR miss cycles
2698system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1812441817 # number of overall MSHR miss cycles
2699system.cpu1.l2cache.overall_mshr_miss_latency::total 5922053309 # number of overall MSHR miss cycles
2700system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12741000 # number of ReadReq MSHR uncacheable cycles
2701system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2803854000 # number of ReadReq MSHR uncacheable cycles
2702system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2816595000 # number of ReadReq MSHR uncacheable cycles
2703system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2344848498 # number of WriteReq MSHR uncacheable cycles
2704system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2344848498 # number of WriteReq MSHR uncacheable cycles
2705system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12741000 # number of overall MSHR uncacheable cycles
2706system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5148702498 # number of overall MSHR uncacheable cycles
2707system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5161443498 # number of overall MSHR uncacheable cycles
2708system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for ReadReq accesses
2709system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for ReadReq accesses
2710system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025885 # mshr miss rate for ReadReq accesses
2711system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses
2712system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses

2702system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2703system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2704system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2705system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses

2713system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2714system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2715system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2716system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses

2706system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947568 # mshr miss rate for UpgradeReq accesses
2707system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947568 # mshr miss rate for UpgradeReq accesses
2708system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.959703 # mshr miss rate for SCUpgradeReq accesses
2709system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959703 # mshr miss rate for SCUpgradeReq accesses
2710system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.545480 # mshr miss rate for ReadExReq accesses
2711system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.545480 # mshr miss rate for ReadExReq accesses
2712system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for ReadCleanReq accesses
2713system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027920 # mshr miss rate for ReadCleanReq accesses
2714system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.407539 # mshr miss rate for ReadSharedReq accesses
2715system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.407539 # mshr miss rate for ReadSharedReq accesses
2716system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for demand accesses
2717system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for demand accesses
2718system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for demand accesses
2719system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for demand accesses
2720system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140563 # mshr miss rate for demand accesses
2721system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for overall accesses
2722system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for overall accesses
2723system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for overall accesses
2724system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for overall accesses

2717system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938541 # mshr miss rate for UpgradeReq accesses
2718system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938541 # mshr miss rate for UpgradeReq accesses
2719system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.953685 # mshr miss rate for SCUpgradeReq accesses
2720system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.953685 # mshr miss rate for SCUpgradeReq accesses
2721system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.471080 # mshr miss rate for ReadExReq accesses
2722system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.471080 # mshr miss rate for ReadExReq accesses
2723system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for ReadCleanReq accesses
2724system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadCleanReq accesses
2725system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.359509 # mshr miss rate for ReadSharedReq accesses
2726system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.359509 # mshr miss rate for ReadSharedReq accesses
2727system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for demand accesses
2728system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for demand accesses
2729system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for demand accesses
2730system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for demand accesses
2731system.cpu1.l2cache.demand_mshr_miss_rate::total 0.133351 # mshr miss rate for demand accesses
2732system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for overall accesses
2733system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for overall accesses
2734system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for overall accesses
2735system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for overall accesses

2725system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses

2736system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses

2726system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168104 # mshr miss rate for overall accesses
2727system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average ReadReq mshr miss latency
2728system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average ReadReq mshr miss latency
2729system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15677.710843 # average ReadReq mshr miss latency
2730system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average HardPFReq mshr miss latency
2731system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43832.203539 # average HardPFReq mshr miss latency
2732system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16437.249335 # average UpgradeReq mshr miss latency
2733system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16437.249335 # average UpgradeReq mshr miss latency
2734system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15533.516725 # average SCUpgradeReq mshr miss latency
2735system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15533.516725 # average SCUpgradeReq mshr miss latency

2737system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170100 # mshr miss rate for overall accesses
2738system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average ReadReq mshr miss latency
2739system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average ReadReq mshr miss latency
2740system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17588.904694 # average ReadReq mshr miss latency
2741system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average HardPFReq mshr miss latency
2742system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50628.280594 # average HardPFReq mshr miss latency
2743system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23586.650185 # average UpgradeReq mshr miss latency
2744system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23586.650185 # average UpgradeReq mshr miss latency
2745system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18516.656261 # average SCUpgradeReq mshr miss latency
2746system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18516.656261 # average SCUpgradeReq mshr miss latency

2736system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
2737system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency

2747system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
2748system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency

2738system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33620.278419 # average ReadExReq mshr miss latency
2739system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33620.278419 # average ReadExReq mshr miss latency
2740system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average ReadCleanReq mshr miss latency
2741system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30019.844566 # average ReadCleanReq mshr miss latency
2742system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16199.480061 # average ReadSharedReq mshr miss latency
2743system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16199.480061 # average ReadSharedReq mshr miss latency
2744system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency
2745system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency
2746system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency
2747system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency
2748system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22928.274145 # average overall mshr miss latency
2749system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency
2750system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency
2751system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency
2752system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency
2753system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average overall mshr miss latency
2754system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26353.016452 # average overall mshr miss latency
2755system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average ReadReq mshr uncacheable latency
2756system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154160.258180 # average ReadReq mshr uncacheable latency
2757system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153654.407732 # average ReadReq mshr uncacheable latency
2758system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150318.070080 # average WriteReq mshr uncacheable latency
2759system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150318.070080 # average WriteReq mshr uncacheable latency
2760system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average overall mshr uncacheable latency
2761system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152434.260979 # average overall mshr uncacheable latency
2762system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 152161.439912 # average overall mshr uncacheable latency

2749system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46182.211259 # average ReadExReq mshr miss latency
2750system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46182.211259 # average ReadExReq mshr miss latency
2751system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average ReadCleanReq mshr miss latency
2752system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49490.633204 # average ReadCleanReq mshr miss latency
2753system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19284.639756 # average ReadSharedReq mshr miss latency
2754system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19284.639756 # average ReadSharedReq mshr miss latency
2755system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency
2756system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency
2757system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency
2758system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency
2759system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31636.488495 # average overall mshr miss latency
2760system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency
2761system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency
2762system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency
2763system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency
2764system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average overall mshr miss latency
2765system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35739.609590 # average overall mshr miss latency
2766system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average ReadReq mshr uncacheable latency
2767system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164333.255187 # average ReadReq mshr uncacheable latency
2768system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164098.986250 # average ReadReq mshr uncacheable latency
2769system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163506.624224 # average WriteReq mshr uncacheable latency
2770system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163506.624224 # average WriteReq mshr uncacheable latency
2771system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average overall mshr uncacheable latency
2772system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 163955.752571 # average overall mshr uncacheable latency
2773system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163829.344485 # average overall mshr uncacheable latency

2763system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

2774system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

2764system.cpu1.toL2Bus.trans_dist::ReadReq 67801 # Transaction distribution
2765system.cpu1.toL2Bus.trans_dist::ReadResp 858839 # Transaction distribution
2766system.cpu1.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution
2767system.cpu1.toL2Bus.trans_dist::WriteResp 11815 # Transaction distribution
2768system.cpu1.toL2Bus.trans_dist::Writeback 481520 # Transaction distribution
2769system.cpu1.toL2Bus.trans_dist::CleanEvict 790490 # Transaction distribution
2770system.cpu1.toL2Bus.trans_dist::HardPFReq 28803 # Transaction distribution
2771system.cpu1.toL2Bus.trans_dist::UpgradeReq 75635 # Transaction distribution
2772system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42021 # Transaction distribution
2773system.cpu1.toL2Bus.trans_dist::UpgradeResp 86708 # Transaction distribution
2774system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
2775system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
2776system.cpu1.toL2Bus.trans_dist::ReadExReq 83417 # Transaction distribution
2777system.cpu1.toL2Bus.trans_dist::ReadExResp 65666 # Transaction distribution
2778system.cpu1.toL2Bus.trans_dist::ReadCleanReq 603729 # Transaction distribution
2779system.cpu1.toL2Bus.trans_dist::ReadSharedReq 520017 # Transaction distribution
2780system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2781system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1799792 # Packet count per connected master and slave (bytes)
2782system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 888351 # Packet count per connected master and slave (bytes)
2783system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17049 # Packet count per connected master and slave (bytes)
2784system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 36002 # Packet count per connected master and slave (bytes)
2785system.cpu1.toL2Bus.pkt_count::total 2741194 # Packet count per connected master and slave (bytes)
2786system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38640160 # Cumulative packet size per connected master and slave (bytes)
2787system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25264094 # Cumulative packet size per connected master and slave (bytes)
2788system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29912 # Cumulative packet size per connected master and slave (bytes)
2789system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 63000 # Cumulative packet size per connected master and slave (bytes)
2790system.cpu1.toL2Bus.pkt_size::total 63997166 # Cumulative packet size per connected master and slave (bytes)
2791system.cpu1.toL2Bus.snoops 1119232 # Total snoops (count)
2792system.cpu1.toL2Bus.snoop_fanout::samples 2773999 # Request fanout histogram
2793system.cpu1.toL2Bus.snoop_fanout::mean 1.384160 # Request fanout histogram
2794system.cpu1.toL2Bus.snoop_fanout::stdev 0.486396 # Request fanout histogram

2775system.cpu1.toL2Bus.snoop_filter.tot_requests 1911239 # Total number of requests made to the snoop filter.
2776system.cpu1.toL2Bus.snoop_filter.hit_single_requests 964293 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2777system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 15206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2778system.cpu1.toL2Bus.snoop_filter.tot_snoops 115900 # Total number of snoops made to the snoop filter.
2779system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 115705 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2780system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2781system.cpu1.toL2Bus.trans_dist::ReadReq 49800 # Transaction distribution
2782system.cpu1.toL2Bus.trans_dist::ReadResp 965132 # Transaction distribution
2783system.cpu1.toL2Bus.trans_dist::WriteReq 14341 # Transaction distribution
2784system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution
2785system.cpu1.toL2Bus.trans_dist::Writeback 177279 # Transaction distribution
2786system.cpu1.toL2Bus.trans_dist::CleanEvict 810351 # Transaction distribution
2787system.cpu1.toL2Bus.trans_dist::HardPFReq 43777 # Transaction distribution
2788system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
2789system.cpu1.toL2Bus.trans_dist::UpgradeReq 73201 # Transaction distribution
2790system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution
2791system.cpu1.toL2Bus.trans_dist::UpgradeResp 89676 # Transaction distribution
2792system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
2793system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution
2794system.cpu1.toL2Bus.trans_dist::ReadExReq 81502 # Transaction distribution
2795system.cpu1.toL2Bus.trans_dist::ReadExResp 78977 # Transaction distribution
2796system.cpu1.toL2Bus.trans_dist::ReadCleanReq 672822 # Transaction distribution
2797system.cpu1.toL2Bus.trans_dist::ReadSharedReq 286780 # Transaction distribution
2798system.cpu1.toL2Bus.trans_dist::InvalidateReq 213 # Transaction distribution
2799system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2005740 # Packet count per connected master and slave (bytes)
2800system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1027154 # Packet count per connected master and slave (bytes)
2801system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17080 # Packet count per connected master and slave (bytes)
2802system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42715 # Packet count per connected master and slave (bytes)
2803system.cpu1.toL2Bus.pkt_count::total 3092689 # Packet count per connected master and slave (bytes)
2804system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43061536 # Cumulative packet size per connected master and slave (bytes)
2805system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29508655 # Cumulative packet size per connected master and slave (bytes)
2806system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30492 # Cumulative packet size per connected master and slave (bytes)
2807system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78144 # Cumulative packet size per connected master and slave (bytes)
2808system.cpu1.toL2Bus.pkt_size::total 72678827 # Cumulative packet size per connected master and slave (bytes)
2809system.cpu1.toL2Bus.snoops 390895 # Total snoops (count)
2810system.cpu1.toL2Bus.snoop_fanout::samples 2268265 # Request fanout histogram
2811system.cpu1.toL2Bus.snoop_fanout::mean 0.069071 # Request fanout histogram
2812system.cpu1.toL2Bus.snoop_fanout::stdev 0.253913 # Request fanout histogram

2795system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2813system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

2796system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2797system.cpu1.toL2Bus.snoop_fanout::1 1708339 61.58% 61.58% # Request fanout histogram
2798system.cpu1.toL2Bus.snoop_fanout::2 1065660 38.42% 100.00% # Request fanout histogram

2814system.cpu1.toL2Bus.snoop_fanout::0 2111789 93.10% 93.10% # Request fanout histogram
2815system.cpu1.toL2Bus.snoop_fanout::1 156281 6.89% 99.99% # Request fanout histogram
2816system.cpu1.toL2Bus.snoop_fanout::2 195 0.01% 100.00% # Request fanout histogram

2799system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

2817system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

2800system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

2818system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram

2801system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

2819system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

2802system.cpu1.toL2Bus.snoop_fanout::total 2773999 # Request fanout histogram
2803system.cpu1.toL2Bus.reqLayer0.occupancy 991762490 # Layer occupancy (ticks)

2820system.cpu1.toL2Bus.snoop_fanout::total 2268265 # Request fanout histogram
2821system.cpu1.toL2Bus.reqLayer0.occupancy 1127589981 # Layer occupancy (ticks)

2804system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)

2822system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)

2805system.cpu1.toL2Bus.snoopLayer0.occupancy 81878499 # Layer occupancy (ticks)

2823system.cpu1.toL2Bus.snoopLayer0.occupancy 88549490 # Layer occupancy (ticks)

2806system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

2824system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

2807system.cpu1.toL2Bus.respLayer0.occupancy 905763364 # Layer occupancy (ticks)

2825system.cpu1.toL2Bus.respLayer0.occupancy 1009459749 # Layer occupancy (ticks)

2808system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

2826system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

2809system.cpu1.toL2Bus.respLayer1.occupancy 398007900 # Layer occupancy (ticks)

2827system.cpu1.toL2Bus.respLayer1.occupancy 464204253 # Layer occupancy (ticks)

2810system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

2828system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

2811system.cpu1.toL2Bus.respLayer2.occupancy 9580481 # Layer occupancy (ticks)

2829system.cpu1.toL2Bus.respLayer2.occupancy 9470972 # Layer occupancy (ticks)

2812system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)

2830system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)

2813system.cpu1.toL2Bus.respLayer3.occupancy 20262978 # Layer occupancy (ticks)

2831system.cpu1.toL2Bus.respLayer3.occupancy 23200956 # Layer occupancy (ticks)

2814system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

2832system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

2815system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
2816system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
2817system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
2818system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
2819system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)

2833system.iobus.trans_dist::ReadReq 31010 # Transaction distribution
2834system.iobus.trans_dist::ReadResp 31010 # Transaction distribution
2835system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2836system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
2837system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)

2820system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2821system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2822system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2823system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)

2838system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2839system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2840system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2841system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)

2824system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)

2842system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)

2825system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2826system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2827system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2828system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2829system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2830system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2831system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2832system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2833system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2834system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2835system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2836system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2837system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2838system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2839system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)

2843system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2844system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2845system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2846system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2847system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2848system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2849system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2850system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2851system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2852system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2853system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2854system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2855system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2856system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2857system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)

2840system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes)

2858system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)

2841system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
2842system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)

2859system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
2860system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)

2843system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes)
2844system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)

2861system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes)
2862system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)

2845system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2846system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2847system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2848system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)

2863system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2864system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2865system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2866system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)

2849system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)

2867system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)

2850system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2851system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2852system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2853system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2854system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2855system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2856system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2857system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2858system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2859system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2860system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2861system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2862system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2863system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2864system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2865system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2866system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
2867system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
2868system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes)

2868system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2869system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2870system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2871system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2872system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2873system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2874system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2875system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2876system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2877system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2878system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2879system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2880system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2881system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2882system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2883system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2884system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
2885system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
2886system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes)

2869system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks)

2887system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)

2870system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2871system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2872system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2873system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2874system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2875system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2876system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2877system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
2878system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)

2888system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2889system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2890system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2891system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2892system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2893system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2894system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2895system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
2896system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)

2879system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)

2897system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks)

2880system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2881system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
2882system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2883system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2884system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2885system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2886system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2887system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)

--- 13 unchanged lines hidden (view full) ---

2901system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
2902system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2903system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
2904system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2905system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2906system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2907system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2908system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)

2898system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2899system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
2900system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2901system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2902system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2903system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2904system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2905system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)

--- 13 unchanged lines hidden (view full) ---

2919system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
2920system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2921system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
2922system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2923system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2924system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2925system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2926system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)

2909system.iobus.reqLayer27.occupancy 187554438 # Layer occupancy (ticks)

2927system.iobus.reqLayer27.occupancy 186507978 # Layer occupancy (ticks)

2910system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2911system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2912system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)

2928system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2929system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2930system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)

2913system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks)

2931system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks)

2914system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2915system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2916system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2917system.iocache.tags.replacements 36458 # number of replacements

2932system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2933system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2934system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2935system.iocache.tags.replacements 36458 # number of replacements

2918system.iocache.tags.tagsinuse 14.557293 # Cycle average of tags in use

2936system.iocache.tags.tagsinuse 14.440882 # Cycle average of tags in use

2919system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2920system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2921system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.

2937system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2938system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2939system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.

2922system.iocache.tags.warmup_cycle 254755320000 # Cycle when the warmup percentage was hit.
2923system.iocache.tags.occ_blocks::realview.ide 14.557293 # Average occupied blocks per requestor
2924system.iocache.tags.occ_percent::realview.ide 0.909831 # Average percentage of cache occupancy
2925system.iocache.tags.occ_percent::total 0.909831 # Average percentage of cache occupancy

2940system.iocache.tags.warmup_cycle 256003407000 # Cycle when the warmup percentage was hit.
2941system.iocache.tags.occ_blocks::realview.ide 14.440882 # Average occupied blocks per requestor
2942system.iocache.tags.occ_percent::realview.ide 0.902555 # Average percentage of cache occupancy
2943system.iocache.tags.occ_percent::total 0.902555 # Average percentage of cache occupancy

2926system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2927system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2928system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2929system.iocache.tags.tag_accesses 328284 # Number of tag accesses
2930system.iocache.tags.data_accesses 328284 # Number of data accesses
2931system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
2932system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2933system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2934system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2935system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
2936system.iocache.demand_misses::total 252 # number of demand (read+write) misses
2937system.iocache.overall_misses::realview.ide 252 # number of overall misses
2938system.iocache.overall_misses::total 252 # number of overall misses

2944system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2945system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2946system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2947system.iocache.tags.tag_accesses 328284 # Number of tag accesses
2948system.iocache.tags.data_accesses 328284 # Number of data accesses
2949system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
2950system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2951system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2952system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2953system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
2954system.iocache.demand_misses::total 252 # number of demand (read+write) misses
2955system.iocache.overall_misses::realview.ide 252 # number of overall misses
2956system.iocache.overall_misses::total 252 # number of overall misses

2939system.iocache.ReadReq_miss_latency::realview.ide 32401877 # number of ReadReq miss cycles
2940system.iocache.ReadReq_miss_latency::total 32401877 # number of ReadReq miss cycles
2941system.iocache.WriteLineReq_miss_latency::realview.ide 4274240561 # number of WriteLineReq miss cycles
2942system.iocache.WriteLineReq_miss_latency::total 4274240561 # number of WriteLineReq miss cycles
2943system.iocache.demand_miss_latency::realview.ide 32401877 # number of demand (read+write) miss cycles
2944system.iocache.demand_miss_latency::total 32401877 # number of demand (read+write) miss cycles
2945system.iocache.overall_miss_latency::realview.ide 32401877 # number of overall miss cycles
2946system.iocache.overall_miss_latency::total 32401877 # number of overall miss cycles

2957system.iocache.ReadReq_miss_latency::realview.ide 32773877 # number of ReadReq miss cycles
2958system.iocache.ReadReq_miss_latency::total 32773877 # number of ReadReq miss cycles
2959system.iocache.WriteLineReq_miss_latency::realview.ide 4715888101 # number of WriteLineReq miss cycles
2960system.iocache.WriteLineReq_miss_latency::total 4715888101 # number of WriteLineReq miss cycles
2961system.iocache.demand_miss_latency::realview.ide 32773877 # number of demand (read+write) miss cycles
2962system.iocache.demand_miss_latency::total 32773877 # number of demand (read+write) miss cycles
2963system.iocache.overall_miss_latency::realview.ide 32773877 # number of overall miss cycles
2964system.iocache.overall_miss_latency::total 32773877 # number of overall miss cycles

2947system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
2948system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2949system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2950system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2951system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
2952system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
2953system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
2954system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
2955system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2956system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2957system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2958system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2959system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2960system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2961system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2962system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses

2965system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
2966system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2967system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2968system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2969system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
2970system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
2971system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
2972system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
2973system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2974system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2975system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2976system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2977system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2978system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2979system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2980system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses

2963system.iocache.ReadReq_avg_miss_latency::realview.ide 128578.876984 # average ReadReq miss latency
2964system.iocache.ReadReq_avg_miss_latency::total 128578.876984 # average ReadReq miss latency
2965system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117994.715134 # average WriteLineReq miss latency
2966system.iocache.WriteLineReq_avg_miss_latency::total 117994.715134 # average WriteLineReq miss latency
2967system.iocache.demand_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency
2968system.iocache.demand_avg_miss_latency::total 128578.876984 # average overall miss latency
2969system.iocache.overall_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency
2970system.iocache.overall_avg_miss_latency::total 128578.876984 # average overall miss latency
2971system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

2981system.iocache.ReadReq_avg_miss_latency::realview.ide 130055.067460 # average ReadReq miss latency
2982system.iocache.ReadReq_avg_miss_latency::total 130055.067460 # average ReadReq miss latency
2983system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130186.840244 # average WriteLineReq miss latency
2984system.iocache.WriteLineReq_avg_miss_latency::total 130186.840244 # average WriteLineReq miss latency
2985system.iocache.demand_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency
2986system.iocache.demand_avg_miss_latency::total 130055.067460 # average overall miss latency
2987system.iocache.overall_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency
2988system.iocache.overall_avg_miss_latency::total 130055.067460 # average overall miss latency
2989system.iocache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked

2972system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked

2990system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked

2973system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked

2991system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked

2974system.iocache.blocked::no_targets 0 # number of cycles access was blocked

2992system.iocache.blocked::no_targets 0 # number of cycles access was blocked

2975system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

2993system.iocache.avg_blocked_cycles::no_mshrs 4.200000 # average number of cycles each access was blocked

2976system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2977system.iocache.fast_writes 0 # number of fast writes performed
2978system.iocache.cache_copies 0 # number of cache copies performed
2979system.iocache.writebacks::writebacks 36206 # number of writebacks
2980system.iocache.writebacks::total 36206 # number of writebacks
2981system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
2982system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
2983system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2984system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2985system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
2986system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
2987system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
2988system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses

2994system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2995system.iocache.fast_writes 0 # number of fast writes performed
2996system.iocache.cache_copies 0 # number of cache copies performed
2997system.iocache.writebacks::writebacks 36206 # number of writebacks
2998system.iocache.writebacks::total 36206 # number of writebacks
2999system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
3000system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
3001system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
3002system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
3003system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
3004system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
3005system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
3006system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses

2989system.iocache.ReadReq_mshr_miss_latency::realview.ide 19801877 # number of ReadReq MSHR miss cycles
2990system.iocache.ReadReq_mshr_miss_latency::total 19801877 # number of ReadReq MSHR miss cycles
2991system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463040561 # number of WriteLineReq MSHR miss cycles
2992system.iocache.WriteLineReq_mshr_miss_latency::total 2463040561 # number of WriteLineReq MSHR miss cycles
2993system.iocache.demand_mshr_miss_latency::realview.ide 19801877 # number of demand (read+write) MSHR miss cycles
2994system.iocache.demand_mshr_miss_latency::total 19801877 # number of demand (read+write) MSHR miss cycles
2995system.iocache.overall_mshr_miss_latency::realview.ide 19801877 # number of overall MSHR miss cycles
2996system.iocache.overall_mshr_miss_latency::total 19801877 # number of overall MSHR miss cycles

3007system.iocache.ReadReq_mshr_miss_latency::realview.ide 20173877 # number of ReadReq MSHR miss cycles
3008system.iocache.ReadReq_mshr_miss_latency::total 20173877 # number of ReadReq MSHR miss cycles
3009system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904688101 # number of WriteLineReq MSHR miss cycles
3010system.iocache.WriteLineReq_mshr_miss_latency::total 2904688101 # number of WriteLineReq MSHR miss cycles
3011system.iocache.demand_mshr_miss_latency::realview.ide 20173877 # number of demand (read+write) MSHR miss cycles
3012system.iocache.demand_mshr_miss_latency::total 20173877 # number of demand (read+write) MSHR miss cycles
3013system.iocache.overall_mshr_miss_latency::realview.ide 20173877 # number of overall MSHR miss cycles
3014system.iocache.overall_mshr_miss_latency::total 20173877 # number of overall MSHR miss cycles

2997system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2998system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2999system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3000system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3001system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3002system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3003system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3004system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses

3015system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3016system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3017system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3018system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3019system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3020system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3021system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3022system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses

3005system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78578.876984 # average ReadReq mshr miss latency
3006system.iocache.ReadReq_avg_mshr_miss_latency::total 78578.876984 # average ReadReq mshr miss latency
3007system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67994.715134 # average WriteLineReq mshr miss latency
3008system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67994.715134 # average WriteLineReq mshr miss latency
3009system.iocache.demand_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency
3010system.iocache.demand_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency
3011system.iocache.overall_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency
3012system.iocache.overall_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency

3023system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80055.067460 # average ReadReq mshr miss latency
3024system.iocache.ReadReq_avg_mshr_miss_latency::total 80055.067460 # average ReadReq mshr miss latency
3025system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80186.840244 # average WriteLineReq mshr miss latency
3026system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80186.840244 # average WriteLineReq mshr miss latency
3027system.iocache.demand_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency
3028system.iocache.demand_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency
3029system.iocache.overall_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency
3030system.iocache.overall_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency

3013system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate

3031system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate

3014system.l2c.tags.replacements 130408 # number of replacements
3015system.l2c.tags.tagsinuse 64065.129893 # Cycle average of tags in use
3016system.l2c.tags.total_refs 410009 # Total number of references to valid blocks.
3017system.l2c.tags.sampled_refs 194847 # Sample count of references to valid blocks.
3018system.l2c.tags.avg_refs 2.104261 # Average number of references to valid blocks.

3032system.l2c.tags.replacements 129384 # number of replacements
3033system.l2c.tags.tagsinuse 63948.068698 # Cycle average of tags in use
3034system.l2c.tags.total_refs 411864 # Total number of references to valid blocks.
3035system.l2c.tags.sampled_refs 193785 # Sample count of references to valid blocks.
3036system.l2c.tags.avg_refs 2.125366 # Average number of references to valid blocks.

3019system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

3037system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

3020system.l2c.tags.occ_blocks::writebacks 11642.697009 # Average occupied blocks per requestor
3021system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.974901 # Average occupied blocks per requestor
3022system.l2c.tags.occ_blocks::cpu0.itb.walker 0.090106 # Average occupied blocks per requestor
3023system.l2c.tags.occ_blocks::cpu0.inst 8094.672337 # Average occupied blocks per requestor
3024system.l2c.tags.occ_blocks::cpu0.data 2978.207969 # Average occupied blocks per requestor
3025system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37076.471677 # Average occupied blocks per requestor
3026system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.445472 # Average occupied blocks per requestor
3027system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909924 # Average occupied blocks per requestor
3028system.l2c.tags.occ_blocks::cpu1.inst 1874.720720 # Average occupied blocks per requestor
3029system.l2c.tags.occ_blocks::cpu1.data 683.354796 # Average occupied blocks per requestor
3030system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1693.584982 # Average occupied blocks per requestor
3031system.l2c.tags.occ_percent::writebacks 0.177653 # Average percentage of cache occupancy
3032system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000213 # Average percentage of cache occupancy
3033system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
3034system.l2c.tags.occ_percent::cpu0.inst 0.123515 # Average percentage of cache occupancy
3035system.l2c.tags.occ_percent::cpu0.data 0.045444 # Average percentage of cache occupancy
3036system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565742 # Average percentage of cache occupancy
3037system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy

3038system.l2c.tags.occ_blocks::writebacks 12531.983329 # Average occupied blocks per requestor
3039system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.494639 # Average occupied blocks per requestor
3040system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048364 # Average occupied blocks per requestor
3041system.l2c.tags.occ_blocks::cpu0.inst 6442.782513 # Average occupied blocks per requestor
3042system.l2c.tags.occ_blocks::cpu0.data 2029.980541 # Average occupied blocks per requestor
3043system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34279.633489 # Average occupied blocks per requestor
3044system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.674973 # Average occupied blocks per requestor
3045system.l2c.tags.occ_blocks::cpu1.itb.walker 0.902888 # Average occupied blocks per requestor
3046system.l2c.tags.occ_blocks::cpu1.inst 3492.124605 # Average occupied blocks per requestor
3047system.l2c.tags.occ_blocks::cpu1.data 1459.870620 # Average occupied blocks per requestor
3048system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3683.572737 # Average occupied blocks per requestor
3049system.l2c.tags.occ_percent::writebacks 0.191223 # Average percentage of cache occupancy
3050system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy
3051system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy
3052system.l2c.tags.occ_percent::cpu0.inst 0.098309 # Average percentage of cache occupancy
3053system.l2c.tags.occ_percent::cpu0.data 0.030975 # Average percentage of cache occupancy
3054system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.523066 # Average percentage of cache occupancy
3055system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy

3038system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy

3056system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy

3039system.l2c.tags.occ_percent::cpu1.inst 0.028606 # Average percentage of cache occupancy
3040system.l2c.tags.occ_percent::cpu1.data 0.010427 # Average percentage of cache occupancy
3041system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025842 # Average percentage of cache occupancy
3042system.l2c.tags.occ_percent::total 0.977556 # Average percentage of cache occupancy
3043system.l2c.tags.occ_task_id_blocks::1022 31097 # Occupied blocks per task id
3044system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
3045system.l2c.tags.occ_task_id_blocks::1024 33320 # Occupied blocks per task id
3046system.l2c.tags.age_task_id_blocks_1022::2 200 # Occupied blocks per task id
3047system.l2c.tags.age_task_id_blocks_1022::3 5745 # Occupied blocks per task id
3048system.l2c.tags.age_task_id_blocks_1022::4 25152 # Occupied blocks per task id
3049system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id
3050system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
3051system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
3052system.l2c.tags.age_task_id_blocks_1024::2 514 # Occupied blocks per task id
3053system.l2c.tags.age_task_id_blocks_1024::3 6128 # Occupied blocks per task id
3054system.l2c.tags.age_task_id_blocks_1024::4 26654 # Occupied blocks per task id
3055system.l2c.tags.occ_task_id_percent::1022 0.474503 # Percentage of cache occupancy per task id
3056system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id
3057system.l2c.tags.occ_task_id_percent::1024 0.508423 # Percentage of cache occupancy per task id
3058system.l2c.tags.tag_accesses 5488101 # Number of tag accesses
3059system.l2c.tags.data_accesses 5488101 # Number of data accesses
3060system.l2c.Writeback_hits::writebacks 227912 # number of Writeback hits
3061system.l2c.Writeback_hits::total 227912 # number of Writeback hits
3062system.l2c.UpgradeReq_hits::cpu0.data 2549 # number of UpgradeReq hits
3063system.l2c.UpgradeReq_hits::cpu1.data 581 # number of UpgradeReq hits
3064system.l2c.UpgradeReq_hits::total 3130 # number of UpgradeReq hits
3065system.l2c.SCUpgradeReq_hits::cpu0.data 167 # number of SCUpgradeReq hits
3066system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits
3067system.l2c.SCUpgradeReq_hits::total 333 # number of SCUpgradeReq hits
3068system.l2c.ReadExReq_hits::cpu0.data 3885 # number of ReadExReq hits
3069system.l2c.ReadExReq_hits::cpu1.data 1531 # number of ReadExReq hits
3070system.l2c.ReadExReq_hits::total 5416 # number of ReadExReq hits
3071system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 182 # number of ReadSharedReq hits
3072system.l2c.ReadSharedReq_hits::cpu0.itb.walker 78 # number of ReadSharedReq hits
3073system.l2c.ReadSharedReq_hits::cpu0.inst 36625 # number of ReadSharedReq hits
3074system.l2c.ReadSharedReq_hits::cpu0.data 47695 # number of ReadSharedReq hits
3075system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45738 # number of ReadSharedReq hits
3076system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 45 # number of ReadSharedReq hits
3077system.l2c.ReadSharedReq_hits::cpu1.itb.walker 34 # number of ReadSharedReq hits
3078system.l2c.ReadSharedReq_hits::cpu1.inst 14003 # number of ReadSharedReq hits
3079system.l2c.ReadSharedReq_hits::cpu1.data 9344 # number of ReadSharedReq hits
3080system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4694 # number of ReadSharedReq hits
3081system.l2c.ReadSharedReq_hits::total 158438 # number of ReadSharedReq hits
3082system.l2c.demand_hits::cpu0.dtb.walker 182 # number of demand (read+write) hits
3083system.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits
3084system.l2c.demand_hits::cpu0.inst 36625 # number of demand (read+write) hits
3085system.l2c.demand_hits::cpu0.data 51580 # number of demand (read+write) hits
3086system.l2c.demand_hits::cpu0.l2cache.prefetcher 45738 # number of demand (read+write) hits
3087system.l2c.demand_hits::cpu1.dtb.walker 45 # number of demand (read+write) hits
3088system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits
3089system.l2c.demand_hits::cpu1.inst 14003 # number of demand (read+write) hits
3090system.l2c.demand_hits::cpu1.data 10875 # number of demand (read+write) hits
3091system.l2c.demand_hits::cpu1.l2cache.prefetcher 4694 # number of demand (read+write) hits
3092system.l2c.demand_hits::total 163854 # number of demand (read+write) hits
3093system.l2c.overall_hits::cpu0.dtb.walker 182 # number of overall hits
3094system.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits
3095system.l2c.overall_hits::cpu0.inst 36625 # number of overall hits
3096system.l2c.overall_hits::cpu0.data 51580 # number of overall hits
3097system.l2c.overall_hits::cpu0.l2cache.prefetcher 45738 # number of overall hits
3098system.l2c.overall_hits::cpu1.dtb.walker 45 # number of overall hits
3099system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits
3100system.l2c.overall_hits::cpu1.inst 14003 # number of overall hits
3101system.l2c.overall_hits::cpu1.data 10875 # number of overall hits
3102system.l2c.overall_hits::cpu1.l2cache.prefetcher 4694 # number of overall hits
3103system.l2c.overall_hits::total 163854 # number of overall hits
3104system.l2c.UpgradeReq_misses::cpu0.data 8869 # number of UpgradeReq misses
3105system.l2c.UpgradeReq_misses::cpu1.data 2831 # number of UpgradeReq misses
3106system.l2c.UpgradeReq_misses::total 11700 # number of UpgradeReq misses
3107system.l2c.SCUpgradeReq_misses::cpu0.data 686 # number of SCUpgradeReq misses
3108system.l2c.SCUpgradeReq_misses::cpu1.data 1243 # number of SCUpgradeReq misses
3109system.l2c.SCUpgradeReq_misses::total 1929 # number of SCUpgradeReq misses
3110system.l2c.ReadExReq_misses::cpu0.data 11279 # number of ReadExReq misses
3111system.l2c.ReadExReq_misses::cpu1.data 8332 # number of ReadExReq misses
3112system.l2c.ReadExReq_misses::total 19611 # number of ReadExReq misses
3113system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses
3114system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
3115system.l2c.ReadSharedReq_misses::cpu0.inst 19189 # number of ReadSharedReq misses
3116system.l2c.ReadSharedReq_misses::cpu0.data 9101 # number of ReadSharedReq misses
3117system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131841 # number of ReadSharedReq misses
3118system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 9 # number of ReadSharedReq misses

3057system.l2c.tags.occ_percent::cpu1.inst 0.053286 # Average percentage of cache occupancy
3058system.l2c.tags.occ_percent::cpu1.data 0.022276 # Average percentage of cache occupancy
3059system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.056207 # Average percentage of cache occupancy
3060system.l2c.tags.occ_percent::total 0.975770 # Average percentage of cache occupancy
3061system.l2c.tags.occ_task_id_blocks::1022 30986 # Occupied blocks per task id
3062system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id
3063system.l2c.tags.occ_task_id_blocks::1024 33385 # Occupied blocks per task id
3064system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
3065system.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id
3066system.l2c.tags.age_task_id_blocks_1022::3 6088 # Occupied blocks per task id
3067system.l2c.tags.age_task_id_blocks_1022::4 24764 # Occupied blocks per task id
3068system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id
3069system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
3070system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
3071system.l2c.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id
3072system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id
3073system.l2c.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id
3074system.l2c.tags.occ_task_id_percent::1022 0.472809 # Percentage of cache occupancy per task id
3075system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id
3076system.l2c.tags.occ_task_id_percent::1024 0.509415 # Percentage of cache occupancy per task id
3077system.l2c.tags.tag_accesses 5503227 # Number of tag accesses
3078system.l2c.tags.data_accesses 5503227 # Number of data accesses
3079system.l2c.Writeback_hits::writebacks 228886 # number of Writeback hits
3080system.l2c.Writeback_hits::total 228886 # number of Writeback hits
3081system.l2c.UpgradeReq_hits::cpu0.data 2462 # number of UpgradeReq hits
3082system.l2c.UpgradeReq_hits::cpu1.data 805 # number of UpgradeReq hits
3083system.l2c.UpgradeReq_hits::total 3267 # number of UpgradeReq hits
3084system.l2c.SCUpgradeReq_hits::cpu0.data 259 # number of SCUpgradeReq hits
3085system.l2c.SCUpgradeReq_hits::cpu1.data 106 # number of SCUpgradeReq hits
3086system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits
3087system.l2c.ReadExReq_hits::cpu0.data 3934 # number of ReadExReq hits
3088system.l2c.ReadExReq_hits::cpu1.data 2169 # number of ReadExReq hits
3089system.l2c.ReadExReq_hits::total 6103 # number of ReadExReq hits
3090system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits
3091system.l2c.ReadSharedReq_hits::cpu0.itb.walker 77 # number of ReadSharedReq hits
3092system.l2c.ReadSharedReq_hits::cpu0.inst 33993 # number of ReadSharedReq hits
3093system.l2c.ReadSharedReq_hits::cpu0.data 45721 # number of ReadSharedReq hits
3094system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45094 # number of ReadSharedReq hits
3095system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 77 # number of ReadSharedReq hits
3096system.l2c.ReadSharedReq_hits::cpu1.itb.walker 41 # number of ReadSharedReq hits
3097system.l2c.ReadSharedReq_hits::cpu1.inst 17373 # number of ReadSharedReq hits
3098system.l2c.ReadSharedReq_hits::cpu1.data 11135 # number of ReadSharedReq hits
3099system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 7486 # number of ReadSharedReq hits
3100system.l2c.ReadSharedReq_hits::total 161181 # number of ReadSharedReq hits
3101system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits
3102system.l2c.demand_hits::cpu0.itb.walker 77 # number of demand (read+write) hits
3103system.l2c.demand_hits::cpu0.inst 33993 # number of demand (read+write) hits
3104system.l2c.demand_hits::cpu0.data 49655 # number of demand (read+write) hits
3105system.l2c.demand_hits::cpu0.l2cache.prefetcher 45094 # number of demand (read+write) hits
3106system.l2c.demand_hits::cpu1.dtb.walker 77 # number of demand (read+write) hits
3107system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits
3108system.l2c.demand_hits::cpu1.inst 17373 # number of demand (read+write) hits
3109system.l2c.demand_hits::cpu1.data 13304 # number of demand (read+write) hits
3110system.l2c.demand_hits::cpu1.l2cache.prefetcher 7486 # number of demand (read+write) hits
3111system.l2c.demand_hits::total 167284 # number of demand (read+write) hits
3112system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits
3113system.l2c.overall_hits::cpu0.itb.walker 77 # number of overall hits
3114system.l2c.overall_hits::cpu0.inst 33993 # number of overall hits
3115system.l2c.overall_hits::cpu0.data 49655 # number of overall hits
3116system.l2c.overall_hits::cpu0.l2cache.prefetcher 45094 # number of overall hits
3117system.l2c.overall_hits::cpu1.dtb.walker 77 # number of overall hits
3118system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits
3119system.l2c.overall_hits::cpu1.inst 17373 # number of overall hits
3120system.l2c.overall_hits::cpu1.data 13304 # number of overall hits
3121system.l2c.overall_hits::cpu1.l2cache.prefetcher 7486 # number of overall hits
3122system.l2c.overall_hits::total 167284 # number of overall hits
3123system.l2c.UpgradeReq_misses::cpu0.data 8340 # number of UpgradeReq misses
3124system.l2c.UpgradeReq_misses::cpu1.data 3970 # number of UpgradeReq misses
3125system.l2c.UpgradeReq_misses::total 12310 # number of UpgradeReq misses
3126system.l2c.SCUpgradeReq_misses::cpu0.data 899 # number of SCUpgradeReq misses
3127system.l2c.SCUpgradeReq_misses::cpu1.data 1200 # number of SCUpgradeReq misses
3128system.l2c.SCUpgradeReq_misses::total 2099 # number of SCUpgradeReq misses
3129system.l2c.ReadExReq_misses::cpu0.data 10813 # number of ReadExReq misses
3130system.l2c.ReadExReq_misses::cpu1.data 8272 # number of ReadExReq misses
3131system.l2c.ReadExReq_misses::total 19085 # number of ReadExReq misses
3132system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 24 # number of ReadSharedReq misses
3133system.l2c.ReadSharedReq_misses::cpu0.itb.walker 5 # number of ReadSharedReq misses
3134system.l2c.ReadSharedReq_misses::cpu0.inst 17052 # number of ReadSharedReq misses
3135system.l2c.ReadSharedReq_misses::cpu0.data 7978 # number of ReadSharedReq misses
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3119system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses

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3123system.l2c.ReadSharedReq_misses::total 170863 # number of ReadSharedReq misses
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3139system.l2c.ReadSharedReq_misses::cpu1.inst 5084 # number of ReadSharedReq misses
3140system.l2c.ReadSharedReq_misses::cpu1.data 2174 # number of ReadSharedReq misses
3141system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9295 # number of ReadSharedReq misses
3142system.l2c.ReadSharedReq_misses::total 169401 # number of ReadSharedReq misses
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3145system.l2c.demand_misses::cpu0.inst 17052 # number of demand (read+write) misses
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3147system.l2c.demand_misses::cpu0.l2cache.prefetcher 127774 # number of demand (read+write) misses
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3130system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses

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3131system.l2c.demand_misses::cpu1.inst 2845 # number of demand (read+write) misses
3132system.l2c.demand_misses::cpu1.data 9497 # number of demand (read+write) misses
3133system.l2c.demand_misses::cpu1.l2cache.prefetcher 6684 # number of demand (read+write) misses
3134system.l2c.demand_misses::total 190474 # number of demand (read+write) misses
3135system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses
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3137system.l2c.overall_misses::cpu0.inst 19189 # number of overall misses
3138system.l2c.overall_misses::cpu0.data 20380 # number of overall misses
3139system.l2c.overall_misses::cpu0.l2cache.prefetcher 131841 # number of overall misses
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3150system.l2c.demand_misses::cpu1.inst 5084 # number of demand (read+write) misses
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3153system.l2c.demand_misses::total 188486 # number of demand (read+write) misses
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3145system.l2c.overall_misses::total 190474 # number of overall misses
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3147system.l2c.UpgradeReq_miss_latency::cpu1.data 2028000 # number of UpgradeReq miss cycles
3148system.l2c.UpgradeReq_miss_latency::total 10612000 # number of UpgradeReq miss cycles
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3151system.l2c.SCUpgradeReq_miss_latency::total 2098500 # number of SCUpgradeReq miss cycles
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3161system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 310000 # number of ReadSharedReq miss cycles
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3163system.l2c.ReadSharedReq_miss_latency::cpu1.data 107330500 # number of ReadSharedReq miss cycles
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3165system.l2c.ReadSharedReq_miss_latency::total 17931347537 # number of ReadSharedReq miss cycles
3166system.l2c.demand_miss_latency::cpu0.dtb.walker 2446500 # number of demand (read+write) miss cycles
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3172system.l2c.demand_miss_latency::cpu1.itb.walker 310000 # number of demand (read+write) miss cycles
3173system.l2c.demand_miss_latency::cpu1.inst 240581000 # number of demand (read+write) miss cycles
3174system.l2c.demand_miss_latency::cpu1.data 796923500 # number of demand (read+write) miss cycles
3175system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 936970593 # number of demand (read+write) miss cycles
3176system.l2c.demand_miss_latency::total 19768942037 # number of demand (read+write) miss cycles
3177system.l2c.overall_miss_latency::cpu0.dtb.walker 2446500 # number of overall miss cycles
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3180system.l2c.overall_miss_latency::cpu0.data 1968775500 # number of overall miss cycles
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3187system.l2c.overall_miss_latency::total 19768942037 # number of overall miss cycles
3188system.l2c.Writeback_accesses::writebacks 227912 # number of Writeback accesses(hits+misses)
3189system.l2c.Writeback_accesses::total 227912 # number of Writeback accesses(hits+misses)
3190system.l2c.UpgradeReq_accesses::cpu0.data 11418 # number of UpgradeReq accesses(hits+misses)
3191system.l2c.UpgradeReq_accesses::cpu1.data 3412 # number of UpgradeReq accesses(hits+misses)
3192system.l2c.UpgradeReq_accesses::total 14830 # number of UpgradeReq accesses(hits+misses)
3193system.l2c.SCUpgradeReq_accesses::cpu0.data 853 # number of SCUpgradeReq accesses(hits+misses)
3194system.l2c.SCUpgradeReq_accesses::cpu1.data 1409 # number of SCUpgradeReq accesses(hits+misses)
3195system.l2c.SCUpgradeReq_accesses::total 2262 # number of SCUpgradeReq accesses(hits+misses)
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3202system.l2c.ReadSharedReq_accesses::cpu0.data 56796 # number of ReadSharedReq accesses(hits+misses)
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3206system.l2c.ReadSharedReq_accesses::cpu1.inst 16848 # number of ReadSharedReq accesses(hits+misses)
3207system.l2c.ReadSharedReq_accesses::cpu1.data 10509 # number of ReadSharedReq accesses(hits+misses)
3208system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11378 # number of ReadSharedReq accesses(hits+misses)
3209system.l2c.ReadSharedReq_accesses::total 329301 # number of ReadSharedReq accesses(hits+misses)
3210system.l2c.demand_accesses::cpu0.dtb.walker 207 # number of demand (read+write) accesses
3211system.l2c.demand_accesses::cpu0.itb.walker 81 # number of demand (read+write) accesses
3212system.l2c.demand_accesses::cpu0.inst 55814 # number of demand (read+write) accesses
3213system.l2c.demand_accesses::cpu0.data 71960 # number of demand (read+write) accesses
3214system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177579 # number of demand (read+write) accesses
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3216system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses
3217system.l2c.demand_accesses::cpu1.inst 16848 # number of demand (read+write) accesses
3218system.l2c.demand_accesses::cpu1.data 20372 # number of demand (read+write) accesses
3219system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11378 # number of demand (read+write) accesses
3220system.l2c.demand_accesses::total 354328 # number of demand (read+write) accesses
3221system.l2c.overall_accesses::cpu0.dtb.walker 207 # number of overall (read+write) accesses
3222system.l2c.overall_accesses::cpu0.itb.walker 81 # number of overall (read+write) accesses
3223system.l2c.overall_accesses::cpu0.inst 55814 # number of overall (read+write) accesses
3224system.l2c.overall_accesses::cpu0.data 71960 # number of overall (read+write) accesses
3225system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177579 # number of overall (read+write) accesses
3226system.l2c.overall_accesses::cpu1.dtb.walker 54 # number of overall (read+write) accesses
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3228system.l2c.overall_accesses::cpu1.inst 16848 # number of overall (read+write) accesses
3229system.l2c.overall_accesses::cpu1.data 20372 # number of overall (read+write) accesses
3230system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11378 # number of overall (read+write) accesses
3231system.l2c.overall_accesses::total 354328 # number of overall (read+write) accesses
3232system.l2c.UpgradeReq_miss_rate::cpu0.data 0.776756 # miss rate for UpgradeReq accesses
3233system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829719 # miss rate for UpgradeReq accesses
3234system.l2c.UpgradeReq_miss_rate::total 0.788941 # miss rate for UpgradeReq accesses
3235system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.804220 # miss rate for SCUpgradeReq accesses
3236system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.882186 # miss rate for SCUpgradeReq accesses
3237system.l2c.SCUpgradeReq_miss_rate::total 0.852785 # miss rate for SCUpgradeReq accesses
3238system.l2c.ReadExReq_miss_rate::cpu0.data 0.743801 # miss rate for ReadExReq accesses
3239system.l2c.ReadExReq_miss_rate::cpu1.data 0.844773 # miss rate for ReadExReq accesses
3240system.l2c.ReadExReq_miss_rate::total 0.783594 # miss rate for ReadExReq accesses
3241system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for ReadSharedReq accesses
3242system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.037037 # miss rate for ReadSharedReq accesses
3243system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.343803 # miss rate for ReadSharedReq accesses
3244system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.160240 # miss rate for ReadSharedReq accesses
3245system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for ReadSharedReq accesses
3246system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for ReadSharedReq accesses
3247system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.028571 # miss rate for ReadSharedReq accesses
3248system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.168863 # miss rate for ReadSharedReq accesses
3249system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.110857 # miss rate for ReadSharedReq accesses
3250system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for ReadSharedReq accesses
3251system.l2c.ReadSharedReq_miss_rate::total 0.518866 # miss rate for ReadSharedReq accesses
3252system.l2c.demand_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for demand accesses
3253system.l2c.demand_miss_rate::cpu0.itb.walker 0.037037 # miss rate for demand accesses
3254system.l2c.demand_miss_rate::cpu0.inst 0.343803 # miss rate for demand accesses
3255system.l2c.demand_miss_rate::cpu0.data 0.283213 # miss rate for demand accesses
3256system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for demand accesses
3257system.l2c.demand_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for demand accesses
3258system.l2c.demand_miss_rate::cpu1.itb.walker 0.028571 # miss rate for demand accesses
3259system.l2c.demand_miss_rate::cpu1.inst 0.168863 # miss rate for demand accesses
3260system.l2c.demand_miss_rate::cpu1.data 0.466179 # miss rate for demand accesses
3261system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for demand accesses
3262system.l2c.demand_miss_rate::total 0.537564 # miss rate for demand accesses
3263system.l2c.overall_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for overall accesses
3264system.l2c.overall_miss_rate::cpu0.itb.walker 0.037037 # miss rate for overall accesses
3265system.l2c.overall_miss_rate::cpu0.inst 0.343803 # miss rate for overall accesses
3266system.l2c.overall_miss_rate::cpu0.data 0.283213 # miss rate for overall accesses
3267system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for overall accesses
3268system.l2c.overall_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for overall accesses
3269system.l2c.overall_miss_rate::cpu1.itb.walker 0.028571 # miss rate for overall accesses
3270system.l2c.overall_miss_rate::cpu1.inst 0.168863 # miss rate for overall accesses
3271system.l2c.overall_miss_rate::cpu1.data 0.466179 # miss rate for overall accesses
3272system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for overall accesses
3273system.l2c.overall_miss_rate::total 0.537564 # miss rate for overall accesses
3274system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 967.865599 # average UpgradeReq miss latency
3275system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 716.354645 # average UpgradeReq miss latency
3276system.l2c.UpgradeReq_avg_miss_latency::total 907.008547 # average UpgradeReq miss latency
3277system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1576.530612 # average SCUpgradeReq miss latency
3278system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 818.181818 # average SCUpgradeReq miss latency
3279system.l2c.SCUpgradeReq_avg_miss_latency::total 1087.869362 # average SCUpgradeReq miss latency
3280system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101782.205869 # average ReadExReq miss latency
3281system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.402304 # average ReadExReq miss latency
3282system.l2c.ReadExReq_avg_miss_latency::total 93702.233440 # average ReadExReq miss latency
3283system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 97860 # average ReadSharedReq miss latency
3284system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 82666.666667 # average ReadSharedReq miss latency
3285system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82629.501329 # average ReadSharedReq miss latency
3286system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90185.034612 # average ReadSharedReq miss latency
3287system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314 # average ReadSharedReq miss latency
3288system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91111.111111 # average ReadSharedReq miss latency
3289system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 310000 # average ReadSharedReq miss latency
3290system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84562.741652 # average ReadSharedReq miss latency
3291system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92129.184549 # average ReadSharedReq miss latency
3292system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043 # average ReadSharedReq miss latency
3293system.l2c.ReadSharedReq_avg_miss_latency::total 104945.760855 # average ReadSharedReq miss latency
3294system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 97860 # average overall miss latency
3295system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82666.666667 # average overall miss latency
3296system.l2c.demand_avg_miss_latency::cpu0.inst 82629.501329 # average overall miss latency
3297system.l2c.demand_avg_miss_latency::cpu0.data 96603.312071 # average overall miss latency
3298system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314 # average overall miss latency
3299system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91111.111111 # average overall miss latency
3300system.l2c.demand_avg_miss_latency::cpu1.itb.walker 310000 # average overall miss latency
3301system.l2c.demand_avg_miss_latency::cpu1.inst 84562.741652 # average overall miss latency
3302system.l2c.demand_avg_miss_latency::cpu1.data 83913.183110 # average overall miss latency
3303system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043 # average overall miss latency
3304system.l2c.demand_avg_miss_latency::total 103788.139258 # average overall miss latency
3305system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 97860 # average overall miss latency
3306system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82666.666667 # average overall miss latency
3307system.l2c.overall_avg_miss_latency::cpu0.inst 82629.501329 # average overall miss latency
3308system.l2c.overall_avg_miss_latency::cpu0.data 96603.312071 # average overall miss latency
3309system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314 # average overall miss latency
3310system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91111.111111 # average overall miss latency
3311system.l2c.overall_avg_miss_latency::cpu1.itb.walker 310000 # average overall miss latency
3312system.l2c.overall_avg_miss_latency::cpu1.inst 84562.741652 # average overall miss latency
3313system.l2c.overall_avg_miss_latency::cpu1.data 83913.183110 # average overall miss latency
3314system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043 # average overall miss latency
3315system.l2c.overall_avg_miss_latency::total 103788.139258 # average overall miss latency
3316system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

3161system.l2c.overall_misses::cpu1.inst 5084 # number of overall misses
3162system.l2c.overall_misses::cpu1.data 10446 # number of overall misses
3163system.l2c.overall_misses::cpu1.l2cache.prefetcher 9295 # number of overall misses
3164system.l2c.overall_misses::total 188486 # number of overall misses
3165system.l2c.UpgradeReq_miss_latency::cpu0.data 18505000 # number of UpgradeReq miss cycles
3166system.l2c.UpgradeReq_miss_latency::cpu1.data 12201500 # number of UpgradeReq miss cycles
3167system.l2c.UpgradeReq_miss_latency::total 30706500 # number of UpgradeReq miss cycles
3168system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2576000 # number of SCUpgradeReq miss cycles
3169system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3491000 # number of SCUpgradeReq miss cycles
3170system.l2c.SCUpgradeReq_miss_latency::total 6067000 # number of SCUpgradeReq miss cycles
3171system.l2c.ReadExReq_miss_latency::cpu0.data 1643662000 # number of ReadExReq miss cycles
3172system.l2c.ReadExReq_miss_latency::cpu1.data 1106109000 # number of ReadExReq miss cycles
3173system.l2c.ReadExReq_miss_latency::total 2749771000 # number of ReadExReq miss cycles
3174system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3382000 # number of ReadSharedReq miss cycles
3175system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 654000 # number of ReadSharedReq miss cycles
3176system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2259320501 # number of ReadSharedReq miss cycles
3177system.l2c.ReadSharedReq_miss_latency::cpu0.data 1108395000 # number of ReadSharedReq miss cycles
3178system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20200841109 # number of ReadSharedReq miss cycles
3179system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1916500 # number of ReadSharedReq miss cycles
3180system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132500 # number of ReadSharedReq miss cycles
3181system.l2c.ReadSharedReq_miss_latency::cpu1.inst 687304500 # number of ReadSharedReq miss cycles
3182system.l2c.ReadSharedReq_miss_latency::cpu1.data 302855500 # number of ReadSharedReq miss cycles
3183system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1643216668 # number of ReadSharedReq miss cycles
3184system.l2c.ReadSharedReq_miss_latency::total 26208018278 # number of ReadSharedReq miss cycles
3185system.l2c.demand_miss_latency::cpu0.dtb.walker 3382000 # number of demand (read+write) miss cycles
3186system.l2c.demand_miss_latency::cpu0.itb.walker 654000 # number of demand (read+write) miss cycles
3187system.l2c.demand_miss_latency::cpu0.inst 2259320501 # number of demand (read+write) miss cycles
3188system.l2c.demand_miss_latency::cpu0.data 2752057000 # number of demand (read+write) miss cycles
3189system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20200841109 # number of demand (read+write) miss cycles
3190system.l2c.demand_miss_latency::cpu1.dtb.walker 1916500 # number of demand (read+write) miss cycles
3191system.l2c.demand_miss_latency::cpu1.itb.walker 132500 # number of demand (read+write) miss cycles
3192system.l2c.demand_miss_latency::cpu1.inst 687304500 # number of demand (read+write) miss cycles
3193system.l2c.demand_miss_latency::cpu1.data 1408964500 # number of demand (read+write) miss cycles
3194system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1643216668 # number of demand (read+write) miss cycles
3195system.l2c.demand_miss_latency::total 28957789278 # number of demand (read+write) miss cycles
3196system.l2c.overall_miss_latency::cpu0.dtb.walker 3382000 # number of overall miss cycles
3197system.l2c.overall_miss_latency::cpu0.itb.walker 654000 # number of overall miss cycles
3198system.l2c.overall_miss_latency::cpu0.inst 2259320501 # number of overall miss cycles
3199system.l2c.overall_miss_latency::cpu0.data 2752057000 # number of overall miss cycles
3200system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20200841109 # number of overall miss cycles
3201system.l2c.overall_miss_latency::cpu1.dtb.walker 1916500 # number of overall miss cycles
3202system.l2c.overall_miss_latency::cpu1.itb.walker 132500 # number of overall miss cycles
3203system.l2c.overall_miss_latency::cpu1.inst 687304500 # number of overall miss cycles
3204system.l2c.overall_miss_latency::cpu1.data 1408964500 # number of overall miss cycles
3205system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1643216668 # number of overall miss cycles
3206system.l2c.overall_miss_latency::total 28957789278 # number of overall miss cycles
3207system.l2c.Writeback_accesses::writebacks 228886 # number of Writeback accesses(hits+misses)
3208system.l2c.Writeback_accesses::total 228886 # number of Writeback accesses(hits+misses)
3209system.l2c.UpgradeReq_accesses::cpu0.data 10802 # number of UpgradeReq accesses(hits+misses)
3210system.l2c.UpgradeReq_accesses::cpu1.data 4775 # number of UpgradeReq accesses(hits+misses)
3211system.l2c.UpgradeReq_accesses::total 15577 # number of UpgradeReq accesses(hits+misses)
3212system.l2c.SCUpgradeReq_accesses::cpu0.data 1158 # number of SCUpgradeReq accesses(hits+misses)
3213system.l2c.SCUpgradeReq_accesses::cpu1.data 1306 # number of SCUpgradeReq accesses(hits+misses)
3214system.l2c.SCUpgradeReq_accesses::total 2464 # number of SCUpgradeReq accesses(hits+misses)
3215system.l2c.ReadExReq_accesses::cpu0.data 14747 # number of ReadExReq accesses(hits+misses)
3216system.l2c.ReadExReq_accesses::cpu1.data 10441 # number of ReadExReq accesses(hits+misses)
3217system.l2c.ReadExReq_accesses::total 25188 # number of ReadExReq accesses(hits+misses)
3218system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 208 # number of ReadSharedReq accesses(hits+misses)
3219system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 82 # number of ReadSharedReq accesses(hits+misses)
3220system.l2c.ReadSharedReq_accesses::cpu0.inst 51045 # number of ReadSharedReq accesses(hits+misses)
3221system.l2c.ReadSharedReq_accesses::cpu0.data 53699 # number of ReadSharedReq accesses(hits+misses)
3222system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 172868 # number of ReadSharedReq accesses(hits+misses)
3223system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 91 # number of ReadSharedReq accesses(hits+misses)
3224system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 42 # number of ReadSharedReq accesses(hits+misses)
3225system.l2c.ReadSharedReq_accesses::cpu1.inst 22457 # number of ReadSharedReq accesses(hits+misses)
3226system.l2c.ReadSharedReq_accesses::cpu1.data 13309 # number of ReadSharedReq accesses(hits+misses)
3227system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 16781 # number of ReadSharedReq accesses(hits+misses)
3228system.l2c.ReadSharedReq_accesses::total 330582 # number of ReadSharedReq accesses(hits+misses)
3229system.l2c.demand_accesses::cpu0.dtb.walker 208 # number of demand (read+write) accesses
3230system.l2c.demand_accesses::cpu0.itb.walker 82 # number of demand (read+write) accesses
3231system.l2c.demand_accesses::cpu0.inst 51045 # number of demand (read+write) accesses
3232system.l2c.demand_accesses::cpu0.data 68446 # number of demand (read+write) accesses
3233system.l2c.demand_accesses::cpu0.l2cache.prefetcher 172868 # number of demand (read+write) accesses
3234system.l2c.demand_accesses::cpu1.dtb.walker 91 # number of demand (read+write) accesses
3235system.l2c.demand_accesses::cpu1.itb.walker 42 # number of demand (read+write) accesses
3236system.l2c.demand_accesses::cpu1.inst 22457 # number of demand (read+write) accesses
3237system.l2c.demand_accesses::cpu1.data 23750 # number of demand (read+write) accesses
3238system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16781 # number of demand (read+write) accesses
3239system.l2c.demand_accesses::total 355770 # number of demand (read+write) accesses
3240system.l2c.overall_accesses::cpu0.dtb.walker 208 # number of overall (read+write) accesses
3241system.l2c.overall_accesses::cpu0.itb.walker 82 # number of overall (read+write) accesses
3242system.l2c.overall_accesses::cpu0.inst 51045 # number of overall (read+write) accesses
3243system.l2c.overall_accesses::cpu0.data 68446 # number of overall (read+write) accesses
3244system.l2c.overall_accesses::cpu0.l2cache.prefetcher 172868 # number of overall (read+write) accesses
3245system.l2c.overall_accesses::cpu1.dtb.walker 91 # number of overall (read+write) accesses
3246system.l2c.overall_accesses::cpu1.itb.walker 42 # number of overall (read+write) accesses
3247system.l2c.overall_accesses::cpu1.inst 22457 # number of overall (read+write) accesses
3248system.l2c.overall_accesses::cpu1.data 23750 # number of overall (read+write) accesses
3249system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16781 # number of overall (read+write) accesses
3250system.l2c.overall_accesses::total 355770 # number of overall (read+write) accesses
3251system.l2c.UpgradeReq_miss_rate::cpu0.data 0.772079 # miss rate for UpgradeReq accesses
3252system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831414 # miss rate for UpgradeReq accesses
3253system.l2c.UpgradeReq_miss_rate::total 0.790268 # miss rate for UpgradeReq accesses
3254system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.776339 # miss rate for SCUpgradeReq accesses
3255system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918836 # miss rate for SCUpgradeReq accesses
3256system.l2c.SCUpgradeReq_miss_rate::total 0.851867 # miss rate for SCUpgradeReq accesses
3257system.l2c.ReadExReq_miss_rate::cpu0.data 0.733234 # miss rate for ReadExReq accesses
3258system.l2c.ReadExReq_miss_rate::cpu1.data 0.792261 # miss rate for ReadExReq accesses
3259system.l2c.ReadExReq_miss_rate::total 0.757702 # miss rate for ReadExReq accesses
3260system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for ReadSharedReq accesses
3261system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.060976 # miss rate for ReadSharedReq accesses
3262system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.334058 # miss rate for ReadSharedReq accesses
3263system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.148569 # miss rate for ReadSharedReq accesses
3264system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.739142 # miss rate for ReadSharedReq accesses
3265system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.153846 # miss rate for ReadSharedReq accesses
3266system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.023810 # miss rate for ReadSharedReq accesses
3267system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.226388 # miss rate for ReadSharedReq accesses
3268system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.163348 # miss rate for ReadSharedReq accesses
3269system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.553900 # miss rate for ReadSharedReq accesses
3270system.l2c.ReadSharedReq_miss_rate::total 0.512433 # miss rate for ReadSharedReq accesses
3271system.l2c.demand_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for demand accesses
3272system.l2c.demand_miss_rate::cpu0.itb.walker 0.060976 # miss rate for demand accesses
3273system.l2c.demand_miss_rate::cpu0.inst 0.334058 # miss rate for demand accesses
3274system.l2c.demand_miss_rate::cpu0.data 0.274538 # miss rate for demand accesses
3275system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739142 # miss rate for demand accesses
3276system.l2c.demand_miss_rate::cpu1.dtb.walker 0.153846 # miss rate for demand accesses
3277system.l2c.demand_miss_rate::cpu1.itb.walker 0.023810 # miss rate for demand accesses
3278system.l2c.demand_miss_rate::cpu1.inst 0.226388 # miss rate for demand accesses
3279system.l2c.demand_miss_rate::cpu1.data 0.439832 # miss rate for demand accesses
3280system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.553900 # miss rate for demand accesses
3281system.l2c.demand_miss_rate::total 0.529797 # miss rate for demand accesses
3282system.l2c.overall_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for overall accesses
3283system.l2c.overall_miss_rate::cpu0.itb.walker 0.060976 # miss rate for overall accesses
3284system.l2c.overall_miss_rate::cpu0.inst 0.334058 # miss rate for overall accesses
3285system.l2c.overall_miss_rate::cpu0.data 0.274538 # miss rate for overall accesses
3286system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739142 # miss rate for overall accesses
3287system.l2c.overall_miss_rate::cpu1.dtb.walker 0.153846 # miss rate for overall accesses
3288system.l2c.overall_miss_rate::cpu1.itb.walker 0.023810 # miss rate for overall accesses
3289system.l2c.overall_miss_rate::cpu1.inst 0.226388 # miss rate for overall accesses
3290system.l2c.overall_miss_rate::cpu1.data 0.439832 # miss rate for overall accesses
3291system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.553900 # miss rate for overall accesses
3292system.l2c.overall_miss_rate::total 0.529797 # miss rate for overall accesses
3293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2218.824940 # average UpgradeReq miss latency
3294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3073.425693 # average UpgradeReq miss latency
3295system.l2c.UpgradeReq_avg_miss_latency::total 2494.435418 # average UpgradeReq miss latency
3296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2865.406007 # average SCUpgradeReq miss latency
3297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2909.166667 # average SCUpgradeReq miss latency
3298system.l2c.SCUpgradeReq_avg_miss_latency::total 2890.424011 # average SCUpgradeReq miss latency
3299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 152007.953389 # average ReadExReq miss latency
3300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133717.238878 # average ReadExReq miss latency
3301system.l2c.ReadExReq_avg_miss_latency::total 144080.220068 # average ReadExReq miss latency
3302system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140916.666667 # average ReadSharedReq miss latency
3303system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 130800 # average ReadSharedReq miss latency
3304system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132495.924290 # average ReadSharedReq miss latency
3305system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138931.436450 # average ReadSharedReq miss latency
3306system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 158098.213322 # average ReadSharedReq miss latency
3307system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136892.857143 # average ReadSharedReq miss latency
3308system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 132500 # average ReadSharedReq miss latency
3309system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135189.712825 # average ReadSharedReq miss latency
3310system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139307.957682 # average ReadSharedReq miss latency
3311system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176785.010005 # average ReadSharedReq miss latency
3312system.l2c.ReadSharedReq_avg_miss_latency::total 154709.938418 # average ReadSharedReq miss latency
3313system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140916.666667 # average overall miss latency
3314system.l2c.demand_avg_miss_latency::cpu0.itb.walker 130800 # average overall miss latency
3315system.l2c.demand_avg_miss_latency::cpu0.inst 132495.924290 # average overall miss latency
3316system.l2c.demand_avg_miss_latency::cpu0.data 146456.122612 # average overall miss latency
3317system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 158098.213322 # average overall miss latency
3318system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136892.857143 # average overall miss latency
3319system.l2c.demand_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency
3320system.l2c.demand_avg_miss_latency::cpu1.inst 135189.712825 # average overall miss latency
3321system.l2c.demand_avg_miss_latency::cpu1.data 134880.767758 # average overall miss latency
3322system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 176785.010005 # average overall miss latency
3323system.l2c.demand_avg_miss_latency::total 153633.634742 # average overall miss latency
3324system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140916.666667 # average overall miss latency
3325system.l2c.overall_avg_miss_latency::cpu0.itb.walker 130800 # average overall miss latency
3326system.l2c.overall_avg_miss_latency::cpu0.inst 132495.924290 # average overall miss latency
3327system.l2c.overall_avg_miss_latency::cpu0.data 146456.122612 # average overall miss latency
3328system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 158098.213322 # average overall miss latency
3329system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136892.857143 # average overall miss latency
3330system.l2c.overall_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency
3331system.l2c.overall_avg_miss_latency::cpu1.inst 135189.712825 # average overall miss latency
3332system.l2c.overall_avg_miss_latency::cpu1.data 134880.767758 # average overall miss latency
3333system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 176785.010005 # average overall miss latency
3334system.l2c.overall_avg_miss_latency::total 153633.634742 # average overall miss latency
3335system.l2c.blocked_cycles::no_mshrs 389 # number of cycles access was blocked

3317system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked

3336system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked

3318system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked

3337system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked

3319system.l2c.blocked::no_targets 0 # number of cycles access was blocked

3338system.l2c.blocked::no_targets 0 # number of cycles access was blocked

3320system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

3339system.l2c.avg_blocked_cycles::no_mshrs 129.666667 # average number of cycles each access was blocked

3321system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3322system.l2c.fast_writes 0 # number of fast writes performed
3323system.l2c.cache_copies 0 # number of cache copies performed

3340system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3341system.l2c.fast_writes 0 # number of fast writes performed
3342system.l2c.cache_copies 0 # number of cache copies performed

3324system.l2c.writebacks::writebacks 100621 # number of writebacks
3325system.l2c.writebacks::total 100621 # number of writebacks
3326system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits
3327system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits
3328system.l2c.ReadSharedReq_mshr_hits::total 12 # number of ReadSharedReq MSHR hits
3329system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
3330system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
3331system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
3332system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
3333system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
3334system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits
3335system.l2c.CleanEvict_mshr_misses::writebacks 3122 # number of CleanEvict MSHR misses
3336system.l2c.CleanEvict_mshr_misses::total 3122 # number of CleanEvict MSHR misses
3337system.l2c.UpgradeReq_mshr_misses::cpu0.data 8869 # number of UpgradeReq MSHR misses
3338system.l2c.UpgradeReq_mshr_misses::cpu1.data 2831 # number of UpgradeReq MSHR misses
3339system.l2c.UpgradeReq_mshr_misses::total 11700 # number of UpgradeReq MSHR misses
3340system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 686 # number of SCUpgradeReq MSHR misses
3341system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1243 # number of SCUpgradeReq MSHR misses
3342system.l2c.SCUpgradeReq_mshr_misses::total 1929 # number of SCUpgradeReq MSHR misses
3343system.l2c.ReadExReq_mshr_misses::cpu0.data 11279 # number of ReadExReq MSHR misses
3344system.l2c.ReadExReq_mshr_misses::cpu1.data 8332 # number of ReadExReq MSHR misses
3345system.l2c.ReadExReq_mshr_misses::total 19611 # number of ReadExReq MSHR misses
3346system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadSharedReq MSHR misses
3347system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
3348system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19186 # number of ReadSharedReq MSHR misses
3349system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9101 # number of ReadSharedReq MSHR misses
3350system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131841 # number of ReadSharedReq MSHR misses
3351system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadSharedReq MSHR misses

3343system.l2c.writebacks::writebacks 99650 # number of writebacks
3344system.l2c.writebacks::total 99650 # number of writebacks
3345system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
3346system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 7 # number of ReadSharedReq MSHR hits
3347system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
3348system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
3349system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
3350system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
3351system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
3352system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
3353system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
3354system.l2c.CleanEvict_mshr_misses::writebacks 3259 # number of CleanEvict MSHR misses
3355system.l2c.CleanEvict_mshr_misses::total 3259 # number of CleanEvict MSHR misses
3356system.l2c.UpgradeReq_mshr_misses::cpu0.data 8340 # number of UpgradeReq MSHR misses
3357system.l2c.UpgradeReq_mshr_misses::cpu1.data 3970 # number of UpgradeReq MSHR misses
3358system.l2c.UpgradeReq_mshr_misses::total 12310 # number of UpgradeReq MSHR misses
3359system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 899 # number of SCUpgradeReq MSHR misses
3360system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1200 # number of SCUpgradeReq MSHR misses
3361system.l2c.SCUpgradeReq_mshr_misses::total 2099 # number of SCUpgradeReq MSHR misses
3362system.l2c.ReadExReq_mshr_misses::cpu0.data 10813 # number of ReadExReq MSHR misses
3363system.l2c.ReadExReq_mshr_misses::cpu1.data 8272 # number of ReadExReq MSHR misses
3364system.l2c.ReadExReq_mshr_misses::total 19085 # number of ReadExReq MSHR misses
3365system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 24 # number of ReadSharedReq MSHR misses
3366system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 5 # number of ReadSharedReq MSHR misses
3367system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17050 # number of ReadSharedReq MSHR misses
3368system.l2c.ReadSharedReq_mshr_misses::cpu0.data 7978 # number of ReadSharedReq MSHR misses
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3352system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses

3371system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses

3353system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2836 # number of ReadSharedReq MSHR misses
3354system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1165 # number of ReadSharedReq MSHR misses
3355system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6684 # number of ReadSharedReq MSHR misses
3356system.l2c.ReadSharedReq_mshr_misses::total 170851 # number of ReadSharedReq MSHR misses
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3359system.l2c.demand_mshr_misses::cpu0.inst 19186 # number of demand (read+write) MSHR misses
3360system.l2c.demand_mshr_misses::cpu0.data 20380 # number of demand (read+write) MSHR misses
3361system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131841 # number of demand (read+write) MSHR misses
3362system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses

3372system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5077 # number of ReadSharedReq MSHR misses
3373system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2174 # number of ReadSharedReq MSHR misses
3374system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 9295 # number of ReadSharedReq MSHR misses
3375system.l2c.ReadSharedReq_mshr_misses::total 169392 # number of ReadSharedReq MSHR misses
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3377system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses
3378system.l2c.demand_mshr_misses::cpu0.inst 17050 # number of demand (read+write) MSHR misses
3379system.l2c.demand_mshr_misses::cpu0.data 18791 # number of demand (read+write) MSHR misses
3380system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 127774 # number of demand (read+write) MSHR misses
3381system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses

3363system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses

3382system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses

3364system.l2c.demand_mshr_misses::cpu1.inst 2836 # number of demand (read+write) MSHR misses
3365system.l2c.demand_mshr_misses::cpu1.data 9497 # number of demand (read+write) MSHR misses
3366system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6684 # number of demand (read+write) MSHR misses
3367system.l2c.demand_mshr_misses::total 190462 # number of demand (read+write) MSHR misses
3368system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses
3369system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
3370system.l2c.overall_mshr_misses::cpu0.inst 19186 # number of overall MSHR misses
3371system.l2c.overall_mshr_misses::cpu0.data 20380 # number of overall MSHR misses
3372system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131841 # number of overall MSHR misses
3373system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses

3383system.l2c.demand_mshr_misses::cpu1.inst 5077 # number of demand (read+write) MSHR misses
3384system.l2c.demand_mshr_misses::cpu1.data 10446 # number of demand (read+write) MSHR misses
3385system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9295 # number of demand (read+write) MSHR misses
3386system.l2c.demand_mshr_misses::total 188477 # number of demand (read+write) MSHR misses
3387system.l2c.overall_mshr_misses::cpu0.dtb.walker 24 # number of overall MSHR misses
3388system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses
3389system.l2c.overall_mshr_misses::cpu0.inst 17050 # number of overall MSHR misses
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3374system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses

3393system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses

3375system.l2c.overall_mshr_misses::cpu1.inst 2836 # number of overall MSHR misses
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3378system.l2c.overall_mshr_misses::total 190462 # number of overall MSHR misses

3394system.l2c.overall_mshr_misses::cpu1.inst 5077 # number of overall MSHR misses
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3396system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9295 # number of overall MSHR misses
3397system.l2c.overall_mshr_misses::total 188477 # number of overall MSHR misses

3379system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable

3398system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable

3380system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable

3399system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable

3381system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable

3400system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable

3382system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14482 # number of ReadReq MSHR uncacheable
3383system.l2c.ReadReq_mshr_uncacheable::total 37974 # number of ReadReq MSHR uncacheable
3384system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
3385system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
3386system.l2c.WriteReq_mshr_uncacheable::total 30901 # number of WriteReq MSHR uncacheable

3401system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable
3402system.l2c.ReadReq_mshr_uncacheable::total 38123 # number of ReadReq MSHR uncacheable
3403system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable
3404system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
3405system.l2c.WriteReq_mshr_uncacheable::total 31050 # number of WriteReq MSHR uncacheable

3387system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses

3406system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses

3388system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses

3407system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses

3389system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses

3408system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses

3390system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26297 # number of overall MSHR uncacheable misses
3391system.l2c.overall_mshr_uncacheable_misses::total 68875 # number of overall MSHR uncacheable misses
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3393system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 58746000 # number of UpgradeReq MSHR miss cycles
3394system.l2c.UpgradeReq_mshr_miss_latency::total 242616501 # number of UpgradeReq MSHR miss cycles
3395system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14335002 # number of SCUpgradeReq MSHR miss cycles
3396system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25812000 # number of SCUpgradeReq MSHR miss cycles
3397system.l2c.SCUpgradeReq_mshr_miss_latency::total 40147002 # number of SCUpgradeReq MSHR miss cycles
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3399system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606273000 # number of ReadExReq MSHR miss cycles
3400system.l2c.ReadExReq_mshr_miss_latency::total 1641484500 # number of ReadExReq MSHR miss cycles
3401system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2196500 # number of ReadSharedReq MSHR miss cycles
3402system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 218000 # number of ReadSharedReq MSHR miss cycles
3403system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1393418001 # number of ReadSharedReq MSHR miss cycles
3404system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 729764000 # number of ReadSharedReq MSHR miss cycles
3405system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12917879443 # number of ReadSharedReq MSHR miss cycles
3406system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 730000 # number of ReadSharedReq MSHR miss cycles
3407system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 300000 # number of ReadSharedReq MSHR miss cycles
3408system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 211664500 # number of ReadSharedReq MSHR miss cycles
3409system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 95680500 # number of ReadSharedReq MSHR miss cycles
3410system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 870130593 # number of ReadSharedReq MSHR miss cycles
3411system.l2c.ReadSharedReq_mshr_miss_latency::total 16221981537 # number of ReadSharedReq MSHR miss cycles
3412system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2196500 # number of demand (read+write) MSHR miss cycles
3413system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 218000 # number of demand (read+write) MSHR miss cycles
3414system.l2c.demand_mshr_miss_latency::cpu0.inst 1393418001 # number of demand (read+write) MSHR miss cycles
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3416system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12917879443 # number of demand (read+write) MSHR miss cycles
3417system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 730000 # number of demand (read+write) MSHR miss cycles
3418system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 300000 # number of demand (read+write) MSHR miss cycles
3419system.l2c.demand_mshr_miss_latency::cpu1.inst 211664500 # number of demand (read+write) MSHR miss cycles
3420system.l2c.demand_mshr_miss_latency::cpu1.data 701953500 # number of demand (read+write) MSHR miss cycles
3421system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 870130593 # number of demand (read+write) MSHR miss cycles
3422system.l2c.demand_mshr_miss_latency::total 17863466037 # number of demand (read+write) MSHR miss cycles
3423system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2196500 # number of overall MSHR miss cycles
3424system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 218000 # number of overall MSHR miss cycles
3425system.l2c.overall_mshr_miss_latency::cpu0.inst 1393418001 # number of overall MSHR miss cycles
3426system.l2c.overall_mshr_miss_latency::cpu0.data 1764975500 # number of overall MSHR miss cycles
3427system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12917879443 # number of overall MSHR miss cycles
3428system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 730000 # number of overall MSHR miss cycles
3429system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 300000 # number of overall MSHR miss cycles
3430system.l2c.overall_mshr_miss_latency::cpu1.inst 211664500 # number of overall MSHR miss cycles
3431system.l2c.overall_mshr_miss_latency::cpu1.data 701953500 # number of overall MSHR miss cycles
3432system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 870130593 # number of overall MSHR miss cycles
3433system.l2c.overall_mshr_miss_latency::total 17863466037 # number of overall MSHR miss cycles
3434system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 189269500 # number of ReadReq MSHR uncacheable cycles
3435system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3785154000 # number of ReadReq MSHR uncacheable cycles
3436system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6508000 # number of ReadReq MSHR uncacheable cycles
3437system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1972430500 # number of ReadReq MSHR uncacheable cycles
3438system.l2c.ReadReq_mshr_uncacheable_latency::total 5953362000 # number of ReadReq MSHR uncacheable cycles
3439system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2828697042 # number of WriteReq MSHR uncacheable cycles
3440system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1575146501 # number of WriteReq MSHR uncacheable cycles
3441system.l2c.WriteReq_mshr_uncacheable_latency::total 4403843543 # number of WriteReq MSHR uncacheable cycles
3442system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 189269500 # number of overall MSHR uncacheable cycles
3443system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6613851042 # number of overall MSHR uncacheable cycles
3444system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6508000 # number of overall MSHR uncacheable cycles
3445system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3547577001 # number of overall MSHR uncacheable cycles
3446system.l2c.overall_mshr_uncacheable_latency::total 10357205543 # number of overall MSHR uncacheable cycles

3409system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses
3410system.l2c.overall_mshr_uncacheable_misses::total 69173 # number of overall MSHR uncacheable misses
3411system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 629204500 # number of UpgradeReq MSHR miss cycles
3412system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 299137501 # number of UpgradeReq MSHR miss cycles
3413system.l2c.UpgradeReq_mshr_miss_latency::total 928342001 # number of UpgradeReq MSHR miss cycles
3414system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 69607504 # number of SCUpgradeReq MSHR miss cycles
3415system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 92088000 # number of SCUpgradeReq MSHR miss cycles
3416system.l2c.SCUpgradeReq_mshr_miss_latency::total 161695504 # number of SCUpgradeReq MSHR miss cycles
3417system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1535532000 # number of ReadExReq MSHR miss cycles
3418system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1023389000 # number of ReadExReq MSHR miss cycles
3419system.l2c.ReadExReq_mshr_miss_latency::total 2558921000 # number of ReadExReq MSHR miss cycles
3420system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3142000 # number of ReadSharedReq MSHR miss cycles
3421system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 604000 # number of ReadSharedReq MSHR miss cycles
3422system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2088682501 # number of ReadSharedReq MSHR miss cycles
3423system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1028615000 # number of ReadSharedReq MSHR miss cycles
3424system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18923101109 # number of ReadSharedReq MSHR miss cycles
3425system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1776500 # number of ReadSharedReq MSHR miss cycles
3426system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 122500 # number of ReadSharedReq MSHR miss cycles
3427system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 635761500 # number of ReadSharedReq MSHR miss cycles
3428system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 281115500 # number of ReadSharedReq MSHR miss cycles
3429system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1550266668 # number of ReadSharedReq MSHR miss cycles
3430system.l2c.ReadSharedReq_mshr_miss_latency::total 24513187278 # number of ReadSharedReq MSHR miss cycles
3431system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3142000 # number of demand (read+write) MSHR miss cycles
3432system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 604000 # number of demand (read+write) MSHR miss cycles
3433system.l2c.demand_mshr_miss_latency::cpu0.inst 2088682501 # number of demand (read+write) MSHR miss cycles
3434system.l2c.demand_mshr_miss_latency::cpu0.data 2564147000 # number of demand (read+write) MSHR miss cycles
3435system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18923101109 # number of demand (read+write) MSHR miss cycles
3436system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1776500 # number of demand (read+write) MSHR miss cycles
3437system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) MSHR miss cycles
3438system.l2c.demand_mshr_miss_latency::cpu1.inst 635761500 # number of demand (read+write) MSHR miss cycles
3439system.l2c.demand_mshr_miss_latency::cpu1.data 1304504500 # number of demand (read+write) MSHR miss cycles
3440system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1550266668 # number of demand (read+write) MSHR miss cycles
3441system.l2c.demand_mshr_miss_latency::total 27072108278 # number of demand (read+write) MSHR miss cycles
3442system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3142000 # number of overall MSHR miss cycles
3443system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 604000 # number of overall MSHR miss cycles
3444system.l2c.overall_mshr_miss_latency::cpu0.inst 2088682501 # number of overall MSHR miss cycles
3445system.l2c.overall_mshr_miss_latency::cpu0.data 2564147000 # number of overall MSHR miss cycles
3446system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18923101109 # number of overall MSHR miss cycles
3447system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1776500 # number of overall MSHR miss cycles
3448system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 122500 # number of overall MSHR miss cycles
3449system.l2c.overall_mshr_miss_latency::cpu1.inst 635761500 # number of overall MSHR miss cycles
3450system.l2c.overall_mshr_miss_latency::cpu1.data 1304504500 # number of overall MSHR miss cycles
3451system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1550266668 # number of overall MSHR miss cycles
3452system.l2c.overall_mshr_miss_latency::total 27072108278 # number of overall MSHR miss cycles
3453system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344034000 # number of ReadReq MSHR uncacheable cycles
3454system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3293772500 # number of ReadReq MSHR uncacheable cycles
3455system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10902500 # number of ReadReq MSHR uncacheable cycles
3456system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2496744500 # number of ReadReq MSHR uncacheable cycles
3457system.l2c.ReadReq_mshr_uncacheable_latency::total 6145453500 # number of ReadReq MSHR uncacheable cycles
3458system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2525916538 # number of WriteReq MSHR uncacheable cycles
3459system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2101048002 # number of WriteReq MSHR uncacheable cycles
3460system.l2c.WriteReq_mshr_uncacheable_latency::total 4626964540 # number of WriteReq MSHR uncacheable cycles
3461system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344034000 # number of overall MSHR uncacheable cycles
3462system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5819689038 # number of overall MSHR uncacheable cycles
3463system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10902500 # number of overall MSHR uncacheable cycles
3464system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4597792502 # number of overall MSHR uncacheable cycles
3465system.l2c.overall_mshr_uncacheable_latency::total 10772418040 # number of overall MSHR uncacheable cycles

3447system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3448system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

3466system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3467system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

3449system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.776756 # mshr miss rate for UpgradeReq accesses
3450system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829719 # mshr miss rate for UpgradeReq accesses
3451system.l2c.UpgradeReq_mshr_miss_rate::total 0.788941 # mshr miss rate for UpgradeReq accesses
3452system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.804220 # mshr miss rate for SCUpgradeReq accesses
3453system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.882186 # mshr miss rate for SCUpgradeReq accesses
3454system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.852785 # mshr miss rate for SCUpgradeReq accesses
3455system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743801 # mshr miss rate for ReadExReq accesses
3456system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.844773 # mshr miss rate for ReadExReq accesses
3457system.l2c.ReadExReq_mshr_miss_rate::total 0.783594 # mshr miss rate for ReadExReq accesses
3458system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for ReadSharedReq accesses
3459system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for ReadSharedReq accesses
3460system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for ReadSharedReq accesses
3461system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.160240 # mshr miss rate for ReadSharedReq accesses
3462system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for ReadSharedReq accesses
3463system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for ReadSharedReq accesses
3464system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadSharedReq accesses
3465system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for ReadSharedReq accesses
3466system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110857 # mshr miss rate for ReadSharedReq accesses
3467system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for ReadSharedReq accesses
3468system.l2c.ReadSharedReq_mshr_miss_rate::total 0.518829 # mshr miss rate for ReadSharedReq accesses
3469system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for demand accesses
3470system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for demand accesses
3471system.l2c.demand_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for demand accesses
3472system.l2c.demand_mshr_miss_rate::cpu0.data 0.283213 # mshr miss rate for demand accesses
3473system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for demand accesses
3474system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for demand accesses
3475system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses
3476system.l2c.demand_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for demand accesses
3477system.l2c.demand_mshr_miss_rate::cpu1.data 0.466179 # mshr miss rate for demand accesses
3478system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for demand accesses
3479system.l2c.demand_mshr_miss_rate::total 0.537530 # mshr miss rate for demand accesses
3480system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for overall accesses
3481system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for overall accesses
3482system.l2c.overall_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for overall accesses
3483system.l2c.overall_mshr_miss_rate::cpu0.data 0.283213 # mshr miss rate for overall accesses
3484system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for overall accesses
3485system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for overall accesses
3486system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses
3487system.l2c.overall_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for overall accesses
3488system.l2c.overall_mshr_miss_rate::cpu1.data 0.466179 # mshr miss rate for overall accesses
3489system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for overall accesses
3490system.l2c.overall_mshr_miss_rate::total 0.537530 # mshr miss rate for overall accesses
3491system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20731.818807 # average UpgradeReq mshr miss latency
3492system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20750.971388 # average UpgradeReq mshr miss latency
3493system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20736.453077 # average UpgradeReq mshr miss latency
3494system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20896.504373 # average SCUpgradeReq mshr miss latency
3495system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.888978 # average SCUpgradeReq mshr miss latency
3496system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20812.339036 # average SCUpgradeReq mshr miss latency
3497system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91782.205869 # average ReadExReq mshr miss latency
3498system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72764.402304 # average ReadExReq mshr miss latency
3499system.l2c.ReadExReq_avg_mshr_miss_latency::total 83702.233440 # average ReadExReq mshr miss latency
3500system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average ReadSharedReq mshr miss latency
3501system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average ReadSharedReq mshr miss latency
3502system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average ReadSharedReq mshr miss latency
3503system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80185.034612 # average ReadSharedReq mshr miss latency
3504system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average ReadSharedReq mshr miss latency
3505system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average ReadSharedReq mshr miss latency
3506system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average ReadSharedReq mshr miss latency
3507system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average ReadSharedReq mshr miss latency
3508system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82129.184549 # average ReadSharedReq mshr miss latency
3509system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average ReadSharedReq mshr miss latency
3510system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 94948.121679 # average ReadSharedReq mshr miss latency
3511system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency
3512system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average overall mshr miss latency
3513system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency
3514system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency
3515system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency
3516system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency
3517system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency
3518system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency
3519system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency
3520system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency
3521system.l2c.demand_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency
3522system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency
3523system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average overall mshr miss latency
3524system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency
3525system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency
3526system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency
3527system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency
3528system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency
3529system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency
3530system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency
3531system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency
3532system.l2c.overall_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency
3533system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average ReadReq mshr uncacheable latency
3534system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185674.188168 # average ReadReq mshr uncacheable latency
3535system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average ReadReq mshr uncacheable latency
3536system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136198.763983 # average ReadReq mshr uncacheable latency
3537system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156774.687944 # average ReadReq mshr uncacheable latency
3538system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148207.955674 # average WriteReq mshr uncacheable latency
3539system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133317.520186 # average WriteReq mshr uncacheable latency
3540system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142514.596388 # average WriteReq mshr uncacheable latency
3541system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average overall mshr uncacheable latency
3542system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167558.042207 # average overall mshr uncacheable latency
3543system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average overall mshr uncacheable latency
3544system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134904.247671 # average overall mshr uncacheable latency
3545system.l2c.overall_avg_mshr_uncacheable_latency::total 150376.849989 # average overall mshr uncacheable latency

3468system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772079 # mshr miss rate for UpgradeReq accesses
3469system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.831414 # mshr miss rate for UpgradeReq accesses
3470system.l2c.UpgradeReq_mshr_miss_rate::total 0.790268 # mshr miss rate for UpgradeReq accesses
3471system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.776339 # mshr miss rate for SCUpgradeReq accesses
3472system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.918836 # mshr miss rate for SCUpgradeReq accesses
3473system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.851867 # mshr miss rate for SCUpgradeReq accesses
3474system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733234 # mshr miss rate for ReadExReq accesses
3475system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.792261 # mshr miss rate for ReadExReq accesses
3476system.l2c.ReadExReq_mshr_miss_rate::total 0.757702 # mshr miss rate for ReadExReq accesses
3477system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for ReadSharedReq accesses
3478system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for ReadSharedReq accesses
3479system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for ReadSharedReq accesses
3480system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.148569 # mshr miss rate for ReadSharedReq accesses
3481system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for ReadSharedReq accesses
3482system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for ReadSharedReq accesses
3483system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for ReadSharedReq accesses
3484system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for ReadSharedReq accesses
3485system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.163348 # mshr miss rate for ReadSharedReq accesses
3486system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for ReadSharedReq accesses
3487system.l2c.ReadSharedReq_mshr_miss_rate::total 0.512405 # mshr miss rate for ReadSharedReq accesses
3488system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for demand accesses
3489system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for demand accesses
3490system.l2c.demand_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for demand accesses
3491system.l2c.demand_mshr_miss_rate::cpu0.data 0.274538 # mshr miss rate for demand accesses
3492system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for demand accesses
3493system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for demand accesses
3494system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for demand accesses
3495system.l2c.demand_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for demand accesses
3496system.l2c.demand_mshr_miss_rate::cpu1.data 0.439832 # mshr miss rate for demand accesses
3497system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for demand accesses
3498system.l2c.demand_mshr_miss_rate::total 0.529772 # mshr miss rate for demand accesses
3499system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for overall accesses
3500system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.060976 # mshr miss rate for overall accesses
3501system.l2c.overall_mshr_miss_rate::cpu0.inst 0.334019 # mshr miss rate for overall accesses
3502system.l2c.overall_mshr_miss_rate::cpu0.data 0.274538 # mshr miss rate for overall accesses
3503system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739142 # mshr miss rate for overall accesses
3504system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.153846 # mshr miss rate for overall accesses
3505system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.023810 # mshr miss rate for overall accesses
3506system.l2c.overall_mshr_miss_rate::cpu1.inst 0.226077 # mshr miss rate for overall accesses
3507system.l2c.overall_mshr_miss_rate::cpu1.data 0.439832 # mshr miss rate for overall accesses
3508system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553900 # mshr miss rate for overall accesses
3509system.l2c.overall_mshr_miss_rate::total 0.529772 # mshr miss rate for overall accesses
3510system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75444.184652 # average UpgradeReq mshr miss latency
3511system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75349.496474 # average UpgradeReq mshr miss latency
3512system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75413.647522 # average UpgradeReq mshr miss latency
3513system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77427.701891 # average SCUpgradeReq mshr miss latency
3514system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76740 # average SCUpgradeReq mshr miss latency
3515system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77034.542163 # average SCUpgradeReq mshr miss latency
3516system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 142007.953389 # average ReadExReq mshr miss latency
3517system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123717.238878 # average ReadExReq mshr miss latency
3518system.l2c.ReadExReq_avg_mshr_miss_latency::total 134080.220068 # average ReadExReq mshr miss latency
3519system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average ReadSharedReq mshr miss latency
3520system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average ReadSharedReq mshr miss latency
3521system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average ReadSharedReq mshr miss latency
3522system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128931.436450 # average ReadSharedReq mshr miss latency
3523system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average ReadSharedReq mshr miss latency
3524system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average ReadSharedReq mshr miss latency
3525system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency
3526system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average ReadSharedReq mshr miss latency
3527system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129307.957682 # average ReadSharedReq mshr miss latency
3528system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average ReadSharedReq mshr miss latency
3529system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144712.780285 # average ReadSharedReq mshr miss latency
3530system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency
3531system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency
3532system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency
3533system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency
3534system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency
3535system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency
3536system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
3537system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency
3538system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency
3539system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency
3540system.l2c.demand_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency
3541system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency
3542system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency
3543system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency
3544system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency
3545system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency
3546system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency
3547system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
3548system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency
3549system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency
3550system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency
3551system.l2c.overall_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency
3552system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average ReadReq mshr uncacheable latency
3553system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183415.330215 # average ReadReq mshr uncacheable latency
3554system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average ReadReq mshr uncacheable latency
3555system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146359.370420 # average ReadReq mshr uncacheable latency
3556system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161200.679380 # average ReadReq mshr uncacheable latency
3557system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151171.017895 # average WriteReq mshr uncacheable latency
3558system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146506.380448 # average WriteReq mshr uncacheable latency
3559system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149016.571337 # average WriteReq mshr uncacheable latency
3560system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average overall mshr uncacheable latency
3561system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167874.031154 # average overall mshr uncacheable latency
3562system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average overall mshr uncacheable latency
3563system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146426.512803 # average overall mshr uncacheable latency
3564system.l2c.overall_avg_mshr_uncacheable_latency::total 155731.543232 # average overall mshr uncacheable latency

3546system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate

3565system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate

3547system.membus.trans_dist::ReadReq 37974 # Transaction distribution
3548system.membus.trans_dist::ReadResp 209076 # Transaction distribution
3549system.membus.trans_dist::WriteReq 30901 # Transaction distribution
3550system.membus.trans_dist::WriteResp 30901 # Transaction distribution
3551system.membus.trans_dist::Writeback 136827 # Transaction distribution
3552system.membus.trans_dist::CleanEvict 16300 # Transaction distribution
3553system.membus.trans_dist::UpgradeReq 76178 # Transaction distribution
3554system.membus.trans_dist::SCUpgradeReq 40718 # Transaction distribution
3555system.membus.trans_dist::UpgradeResp 13724 # Transaction distribution
3556system.membus.trans_dist::ReadExReq 39427 # Transaction distribution
3557system.membus.trans_dist::ReadExResp 19516 # Transaction distribution
3558system.membus.trans_dist::ReadSharedReq 171103 # Transaction distribution

3566system.membus.trans_dist::ReadReq 38123 # Transaction distribution
3567system.membus.trans_dist::ReadResp 207766 # Transaction distribution
3568system.membus.trans_dist::WriteReq 31050 # Transaction distribution
3569system.membus.trans_dist::WriteResp 31050 # Transaction distribution
3570system.membus.trans_dist::Writeback 135856 # Transaction distribution
3571system.membus.trans_dist::CleanEvict 15674 # Transaction distribution
3572system.membus.trans_dist::UpgradeReq 78082 # Transaction distribution
3573system.membus.trans_dist::SCUpgradeReq 41568 # Transaction distribution
3574system.membus.trans_dist::UpgradeResp 14509 # Transaction distribution
3575system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
3576system.membus.trans_dist::ReadExReq 38794 # Transaction distribution
3577system.membus.trans_dist::ReadExResp 18985 # Transaction distribution
3578system.membus.trans_dist::ReadSharedReq 169644 # Transaction distribution

3559system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
3560system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution

3579system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
3580system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution

3561system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes)

3581system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)

3562system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)

3582system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)

3563system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes)
3564system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663947 # Packet count per connected master and slave (bytes)
3565system.membus.pkt_count_system.l2c.mem_side::total 785587 # Packet count per connected master and slave (bytes)

3583system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14282 # Packet count per connected master and slave (bytes)
3584system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661810 # Packet count per connected master and slave (bytes)
3585system.membus.pkt_count_system.l2c.mem_side::total 784044 # Packet count per connected master and slave (bytes)

3566system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes)
3567system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes)

3586system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes)
3587system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes)

3568system.membus.pkt_count::total 894521 # Packet count per connected master and slave (bytes)

3588system.membus.pkt_count::total 892978 # Packet count per connected master and slave (bytes)

3569system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
3570system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)

3589system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
3590system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)

3571system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes)
3572system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18671220 # Cumulative packet size per connected master and slave (bytes)
3573system.membus.pkt_size_system.l2c.mem_side::total 18861706 # Cumulative packet size per connected master and slave (bytes)

3591system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28564 # Cumulative packet size per connected master and slave (bytes)
3592system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18481720 # Cumulative packet size per connected master and slave (bytes)
3593system.membus.pkt_size_system.l2c.mem_side::total 18673398 # Cumulative packet size per connected master and slave (bytes)

3574system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
3575system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)

3594system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
3595system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)

3576system.membus.pkt_size::total 21179850 # Cumulative packet size per connected master and slave (bytes)
3577system.membus.snoops 123655 # Total snoops (count)
3578system.membus.snoop_fanout::samples 585907 # Request fanout histogram

3596system.membus.pkt_size::total 20991542 # Cumulative packet size per connected master and slave (bytes)
3597system.membus.snoops 125523 # Total snoops (count)
3598system.membus.snoop_fanout::samples 585264 # Request fanout histogram

3579system.membus.snoop_fanout::mean 1 # Request fanout histogram
3580system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3581system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3582system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

3599system.membus.snoop_fanout::mean 1 # Request fanout histogram
3600system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3601system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3602system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

3583system.membus.snoop_fanout::1 585907 100.00% 100.00% # Request fanout histogram

3603system.membus.snoop_fanout::1 585264 100.00% 100.00% # Request fanout histogram

3584system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3585system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3586system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3587system.membus.snoop_fanout::max_value 1 # Request fanout histogram

3604system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3605system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3606system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3607system.membus.snoop_fanout::max_value 1 # Request fanout histogram

3588system.membus.snoop_fanout::total 585907 # Request fanout histogram
3589system.membus.reqLayer0.occupancy 81623000 # Layer occupancy (ticks)

3608system.membus.snoop_fanout::total 585264 # Request fanout histogram
3609system.membus.reqLayer0.occupancy 81621000 # Layer occupancy (ticks)

3590system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3591system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
3592system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)

3610system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3611system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
3612system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)

3593system.membus.reqLayer2.occupancy 11432490 # Layer occupancy (ticks)

3613system.membus.reqLayer2.occupancy 11798981 # Layer occupancy (ticks)

3594system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)

3614system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)

3595system.membus.reqLayer5.occupancy 989982724 # Layer occupancy (ticks)

3615system.membus.reqLayer5.occupancy 986725496 # Layer occupancy (ticks)

3596system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)

3616system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)

3597system.membus.respLayer2.occupancy 1127040159 # Layer occupancy (ticks)

3617system.membus.respLayer2.occupancy 1119474906 # Layer occupancy (ticks)

3598system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

3618system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

3599system.membus.respLayer3.occupancy 64467297 # Layer occupancy (ticks)

3619system.membus.respLayer3.occupancy 64610767 # Layer occupancy (ticks)

3600system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3601system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3602system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3603system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3604system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3605system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3606system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
3607system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 26 unchanged lines hidden (view full) ---

3634system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
3635system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
3636system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
3637system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
3638system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
3639system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
3640system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
3641system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks

3620system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3621system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3622system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3623system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3624system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3625system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3626system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
3627system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 26 unchanged lines hidden (view full) ---

3654system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
3655system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
3656system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
3657system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
3658system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
3659system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
3660system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
3661system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks

3642system.toL2Bus.trans_dist::ReadReq 37978 # Transaction distribution
3643system.toL2Bus.trans_dist::ReadResp 489550 # Transaction distribution
3644system.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution
3645system.toL2Bus.trans_dist::WriteResp 30901 # Transaction distribution
3646system.toL2Bus.trans_dist::Writeback 364752 # Transaction distribution
3647system.toL2Bus.trans_dist::CleanEvict 88216 # Transaction distribution
3648system.toL2Bus.trans_dist::UpgradeReq 79213 # Transaction distribution
3649system.toL2Bus.trans_dist::SCUpgradeReq 41051 # Transaction distribution
3650system.toL2Bus.trans_dist::UpgradeResp 120264 # Transaction distribution
3651system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution
3652system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
3653system.toL2Bus.trans_dist::ReadExReq 50507 # Transaction distribution
3654system.toL2Bus.trans_dist::ReadExResp 50507 # Transaction distribution
3655system.toL2Bus.trans_dist::ReadSharedReq 451588 # Transaction distribution

3662system.toL2Bus.snoop_filter.tot_requests 957960 # Total number of requests made to the snoop filter.
3663system.toL2Bus.snoop_filter.hit_single_requests 483276 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3664system.toL2Bus.snoop_filter.hit_multi_requests 165836 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3665system.toL2Bus.snoop_filter.tot_snoops 22284 # Total number of snoops made to the snoop filter.
3666system.toL2Bus.snoop_filter.hit_single_snoops 21444 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3667system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3668system.toL2Bus.trans_dist::ReadReq 38126 # Transaction distribution
3669system.toL2Bus.trans_dist::ReadResp 494242 # Transaction distribution
3670system.toL2Bus.trans_dist::WriteReq 31050 # Transaction distribution
3671system.toL2Bus.trans_dist::WriteResp 31050 # Transaction distribution
3672system.toL2Bus.trans_dist::Writeback 364748 # Transaction distribution
3673system.toL2Bus.trans_dist::CleanEvict 86802 # Transaction distribution
3674system.toL2Bus.trans_dist::UpgradeReq 81249 # Transaction distribution
3675system.toL2Bus.trans_dist::SCUpgradeReq 41933 # Transaction distribution
3676system.toL2Bus.trans_dist::UpgradeResp 123182 # Transaction distribution
3677system.toL2Bus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution
3678system.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution
3679system.toL2Bus.trans_dist::ReadExReq 50538 # Transaction distribution
3680system.toL2Bus.trans_dist::ReadExResp 50538 # Transaction distribution
3681system.toL2Bus.trans_dist::ReadSharedReq 456132 # Transaction distribution

3656system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution

3682system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution

3657system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1086474 # Packet count per connected master and slave (bytes)
3658system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 331144 # Packet count per connected master and slave (bytes)
3659system.toL2Bus.pkt_count::total 1417618 # Packet count per connected master and slave (bytes)
3660system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32384412 # Cumulative packet size per connected master and slave (bytes)
3661system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5153902 # Cumulative packet size per connected master and slave (bytes)
3662system.toL2Bus.pkt_size::total 37538314 # Cumulative packet size per connected master and slave (bytes)
3663system.toL2Bus.snoops 454329 # Total snoops (count)
3664system.toL2Bus.snoop_fanout::samples 1220605 # Request fanout histogram
3665system.toL2Bus.snoop_fanout::mean 1.166616 # Request fanout histogram
3666system.toL2Bus.snoop_fanout::stdev 0.372633 # Request fanout histogram

3683system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1043214 # Packet count per connected master and slave (bytes)
3684system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 384499 # Packet count per connected master and slave (bytes)
3685system.toL2Bus.pkt_count::total 1427713 # Packet count per connected master and slave (bytes)
3686system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31299443 # Cumulative packet size per connected master and slave (bytes)
3687system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6394691 # Cumulative packet size per connected master and slave (bytes)
3688system.toL2Bus.pkt_size::total 37694134 # Cumulative packet size per connected master and slave (bytes)
3689system.toL2Bus.snoops 458404 # Total snoops (count)
3690system.toL2Bus.snoop_fanout::samples 1229453 # Request fanout histogram
3691system.toL2Bus.snoop_fanout::mean 0.314167 # Request fanout histogram
3692system.toL2Bus.snoop_fanout::stdev 0.465653 # Request fanout histogram

3667system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

3693system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

3668system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3669system.toL2Bus.snoop_fanout::1 1017233 83.34% 83.34% # Request fanout histogram
3670system.toL2Bus.snoop_fanout::2 203372 16.66% 100.00% # Request fanout histogram

3694system.toL2Bus.snoop_fanout::0 844039 68.65% 68.65% # Request fanout histogram
3695system.toL2Bus.snoop_fanout::1 384574 31.28% 99.93% # Request fanout histogram
3696system.toL2Bus.snoop_fanout::2 840 0.07% 100.00% # Request fanout histogram

3671system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

3697system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

3672system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

3698system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram

3673system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

3699system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

3674system.toL2Bus.snoop_fanout::total 1220605 # Request fanout histogram
3675system.toL2Bus.reqLayer0.occupancy 824158889 # Layer occupancy (ticks)

3700system.toL2Bus.snoop_fanout::total 1229453 # Request fanout histogram
3701system.toL2Bus.reqLayer0.occupancy 827244513 # Layer occupancy (ticks)

3676system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)

3702system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)

3677system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks)

3703system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks)

3678system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

3704system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

3679system.toL2Bus.respLayer0.occupancy 620803562 # Layer occupancy (ticks)

3705system.toL2Bus.respLayer0.occupancy 603608816 # Layer occupancy (ticks)

3680system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

3706system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)

3681system.toL2Bus.respLayer1.occupancy 245897316 # Layer occupancy (ticks)

3707system.toL2Bus.respLayer1.occupancy 273833055 # Layer occupancy (ticks)

3682system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3683system.cpu0.kern.inst.arm 0 # number of arm instructions executed

3708system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3709system.cpu0.kern.inst.arm 0 # number of arm instructions executed

3684system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed

3710system.cpu0.kern.inst.quiesce 2086 # number of quiesce instructions executed

3685system.cpu1.kern.inst.arm 0 # number of arm instructions executed

3711system.cpu1.kern.inst.arm 0 # number of arm instructions executed

3686system.cpu1.kern.inst.quiesce 2769 # number of quiesce instructions executed

3712system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed