| stats.txt (10576:de2979ff873a) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.824366 # Number of seconds simulated 4sim_ticks 2824365837500 # Number of ticks simulated 5final_tick 2824365837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.824570 # Number of seconds simulated 4sim_ticks 2824570221000 # Number of ticks simulated 5final_tick 2824570221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 93434 # Simulator instruction rate (inst/s) 8host_op_rate 113356 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2196532158 # Simulator tick rate (ticks/s) 10host_mem_usage 669668 # Number of bytes of host memory used 11host_seconds 1285.83 # Real time elapsed on the host 12sim_insts 120140086 # Number of instructions simulated 13sim_ops 145755972 # Number of ops (including micro ops) simulated | 7host_inst_rate 42227 # Simulator instruction rate (inst/s) 8host_op_rate 51230 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 992732164 # Simulator tick rate (ticks/s) 10host_mem_usage 776620 # Number of bytes of host memory used 11host_seconds 2845.25 # Real time elapsed on the host 12sim_insts 120145307 # Number of instructions simulated 13sim_ops 145762315 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 286496 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1047804 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10514048 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 286752 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1037180 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10498560 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu1.inst 32208 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 549728 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 1343808 # Number of bytes read from this memory | 23system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 549024 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 1342912 # Number of bytes read from this memory |
| 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 27system.physmem.bytes_read::total 13778252 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 286496 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 32208 # Number of instructions bytes read from this memory | 27system.physmem.bytes_read::total 13750604 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 286752 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory |
| 30system.physmem.bytes_inst_read::total 318704 # Number of instructions bytes read from this memory | 30system.physmem.bytes_inst_read::total 318704 # Number of instructions bytes read from this memory |
| 31system.physmem.bytes_written::writebacks 7259968 # Number of bytes written to this memory | 31system.physmem.bytes_written::writebacks 9574272 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 34system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 35system.physmem.bytes_written::total 9596048 # Number of bytes written to this memory | 34system.physmem.bytes_written::total 9592016 # Number of bytes written to this memory |
| 36system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 6722 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 16897 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 164282 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu0.itb.walker 6 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 6726 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 16731 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 164040 # Number of read requests responded to by this memory |
| 41system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory | 40system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::cpu1.inst 570 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 20997 # Number of read requests responded to by this memory | 42system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 8602 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 20983 # Number of read requests responded to by this memory |
| 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 47system.physmem.num_reads::total 218146 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 113437 # Number of write requests responded to by this memory | 46system.physmem.num_reads::total 217714 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 149598 # Number of write requests responded to by this memory |
| 49system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 48system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 51system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 52system.physmem.num_writes::total 154097 # Number of write requests responded to by this memory | 50system.physmem.num_writes::total 154034 # Number of write requests responded to by this memory |
| 53system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) |
| 54system.physmem.bw_read::cpu0.itb.walker 113 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.inst 101437 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.data 370987 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.l2cache.prefetcher 3722623 # Total read bandwidth from this memory (bytes/s) | 52system.physmem.bw_read::cpu0.itb.walker 136 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 101521 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 367199 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 3716870 # Total read bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) | 56system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) |
| 60system.physmem.bw_read::cpu1.inst 11404 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.data 194638 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.l2cache.prefetcher 475791 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::cpu1.inst 11312 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 194374 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 475439 # Total read bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) | 61system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) |
| 64system.physmem.bw_read::total 4878352 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 101437 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 11404 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 112841 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2570477 # Write bandwidth from this memory (bytes/s) | 62system.physmem.bw_read::total 4868211 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 101521 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 11312 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 112833 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3389639 # Write bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 67system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 71system.physmem.bw_write::realview.ide 820834 # Write bandwidth from this memory (bytes/s) 72system.physmem.bw_write::total 3397594 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2570477 # Total bandwidth to/from this memory (bytes/s) | 69system.physmem.bw_write::total 3395921 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3389639 # Total bandwidth to/from this memory (bytes/s) |
| 74system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) | 71system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) |
| 75system.physmem.bw_total::cpu0.itb.walker 113 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.inst 101437 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.data 377256 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.l2cache.prefetcher 3722623 # Total bandwidth to/from this memory (bytes/s) | 72system.physmem.bw_total::cpu0.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 101521 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 373467 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 3716870 # Total bandwidth to/from this memory (bytes/s) |
| 79system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) | 76system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) |
| 81system.physmem.bw_total::cpu1.inst 11404 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.data 194652 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.l2cache.prefetcher 475791 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::realview.ide 821174 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 8275946 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 218146 # Number of read requests accepted 87system.physmem.writeReqs 154097 # Number of write requests accepted 88system.physmem.readBursts 218146 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 154097 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13946112 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 15232 # Total number of bytes read from write queue 92system.physmem.bytesWritten 9610368 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 13778252 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 9596048 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 238 # Number of DRAM read bursts serviced by the write queue 96system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one 97system.physmem.neitherReadNorWriteReqs 13753 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 13737 # Per bank write bursts 99system.physmem.perBankRdBursts::1 13637 # Per bank write bursts 100system.physmem.perBankRdBursts::2 14389 # Per bank write bursts 101system.physmem.perBankRdBursts::3 14286 # Per bank write bursts 102system.physmem.perBankRdBursts::4 15951 # Per bank write bursts 103system.physmem.perBankRdBursts::5 13008 # Per bank write bursts 104system.physmem.perBankRdBursts::6 13922 # Per bank write bursts 105system.physmem.perBankRdBursts::7 13905 # Per bank write bursts 106system.physmem.perBankRdBursts::8 13614 # Per bank write bursts 107system.physmem.perBankRdBursts::9 13369 # Per bank write bursts 108system.physmem.perBankRdBursts::10 12796 # Per bank write bursts 109system.physmem.perBankRdBursts::11 11719 # Per bank write bursts 110system.physmem.perBankRdBursts::12 13344 # Per bank write bursts | 78system.physmem.bw_total::cpu1.inst 11312 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 194389 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 475439 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 8264132 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 217714 # Number of read requests accepted 84system.physmem.writeReqs 190258 # Number of write requests accepted 85system.physmem.readBursts 217714 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 190258 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 13924352 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue 89system.physmem.bytesWritten 11782272 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 13750604 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 11910352 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 6131 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 13778 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 13720 # Per bank write bursts 96system.physmem.perBankRdBursts::1 13621 # Per bank write bursts 97system.physmem.perBankRdBursts::2 14360 # Per bank write bursts 98system.physmem.perBankRdBursts::3 14230 # Per bank write bursts 99system.physmem.perBankRdBursts::4 15917 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12969 # Per bank write bursts 101system.physmem.perBankRdBursts::6 13917 # Per bank write bursts 102system.physmem.perBankRdBursts::7 13922 # Per bank write bursts 103system.physmem.perBankRdBursts::8 13602 # Per bank write bursts 104system.physmem.perBankRdBursts::9 13356 # Per bank write bursts 105system.physmem.perBankRdBursts::10 12792 # Per bank write bursts 106system.physmem.perBankRdBursts::11 11688 # Per bank write bursts 107system.physmem.perBankRdBursts::12 13275 # Per bank write bursts |
| 111system.physmem.perBankRdBursts::13 14168 # Per bank write bursts | 108system.physmem.perBankRdBursts::13 14168 # Per bank write bursts |
| 112system.physmem.perBankRdBursts::14 13355 # Per bank write bursts 113system.physmem.perBankRdBursts::15 12708 # Per bank write bursts 114system.physmem.perBankWrBursts::0 9678 # Per bank write bursts 115system.physmem.perBankWrBursts::1 9778 # Per bank write bursts 116system.physmem.perBankWrBursts::2 10288 # Per bank write bursts 117system.physmem.perBankWrBursts::3 9945 # Per bank write bursts 118system.physmem.perBankWrBursts::4 9066 # Per bank write bursts 119system.physmem.perBankWrBursts::5 9050 # Per bank write bursts 120system.physmem.perBankWrBursts::6 9464 # Per bank write bursts 121system.physmem.perBankWrBursts::7 9420 # Per bank write bursts 122system.physmem.perBankWrBursts::8 9418 # Per bank write bursts 123system.physmem.perBankWrBursts::9 9295 # Per bank write bursts 124system.physmem.perBankWrBursts::10 9149 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8660 # Per bank write bursts 126system.physmem.perBankWrBursts::12 9452 # Per bank write bursts 127system.physmem.perBankWrBursts::13 9588 # Per bank write bursts 128system.physmem.perBankWrBursts::14 9180 # Per bank write bursts 129system.physmem.perBankWrBursts::15 8731 # Per bank write bursts | 109system.physmem.perBankRdBursts::14 13342 # Per bank write bursts 110system.physmem.perBankRdBursts::15 12689 # Per bank write bursts 111system.physmem.perBankWrBursts::0 11837 # Per bank write bursts 112system.physmem.perBankWrBursts::1 11937 # Per bank write bursts 113system.physmem.perBankWrBursts::2 12245 # Per bank write bursts 114system.physmem.perBankWrBursts::3 12130 # Per bank write bursts 115system.physmem.perBankWrBursts::4 11220 # Per bank write bursts 116system.physmem.perBankWrBursts::5 11075 # Per bank write bursts 117system.physmem.perBankWrBursts::6 11642 # Per bank write bursts 118system.physmem.perBankWrBursts::7 11554 # Per bank write bursts 119system.physmem.perBankWrBursts::8 11490 # Per bank write bursts 120system.physmem.perBankWrBursts::9 11375 # Per bank write bursts 121system.physmem.perBankWrBursts::10 11404 # Per bank write bursts 122system.physmem.perBankWrBursts::11 11050 # Per bank write bursts 123system.physmem.perBankWrBursts::12 11716 # Per bank write bursts 124system.physmem.perBankWrBursts::13 11527 # Per bank write bursts 125system.physmem.perBankWrBursts::14 11100 # Per bank write bursts 126system.physmem.perBankWrBursts::15 10796 # Per bank write bursts |
| 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 131system.physmem.numWrRetry 6 # Number of times write queue was full causing retry 132system.physmem.totGap 2824364779500 # Total gap between requests | 128system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 129system.physmem.totGap 2824568625000 # Total gap between requests |
| 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 559 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 3083 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) | 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 559 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 3083 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 139system.physmem.readPktSize::6 214476 # Read request sizes (log2) | 136system.physmem.readPktSize::6 214044 # Read request sizes (log2) |
| 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) | 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4436 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 146system.physmem.writePktSize::6 149661 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 53531 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 76693 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 20729 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 15217 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 11073 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 9725 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 8854 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 8206 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 7203 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 2475 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 1454 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 1095 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 641 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 479 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 300 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 216 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see | 143system.physmem.writePktSize::6 185822 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 53286 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 76786 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 20725 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 15275 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 11050 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 9711 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 8821 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 8169 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 7162 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 2458 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1453 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1085 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 636 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 285 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 205 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 194system.physmem.wrQLenPdf::15 2958 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3567 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4160 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 4854 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 5584 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 6912 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7776 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8777 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9674 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10921 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 10781 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 10780 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 10773 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 11406 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 9277 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 9241 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 8653 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 876 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 584 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 425 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 224 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 188 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 147 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 88 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 79 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see | 191system.physmem.wrQLenPdf::15 3166 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 4872 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 5834 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 7123 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 8138 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 9675 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 10762 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 11991 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 12258 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 13286 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 12907 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 12909 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 12445 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 12840 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 10514 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 10190 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 10077 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 9379 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1105 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 726 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 520 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 390 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 351 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 302 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 253 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 211 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 104 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 87 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see |
| 235system.physmem.wrQLenPdf::56 23 # What write queue length does an incoming req see | 232system.physmem.wrQLenPdf::56 23 # What write queue length does an incoming req see |
| 236system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 92847 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 253.712882 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 143.703009 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 308.429657 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 46968 50.59% 50.59% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 18903 20.36% 70.95% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6762 7.28% 78.23% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3669 3.95% 82.18% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3165 3.41% 85.59% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 2101 2.26% 87.85% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1261 1.36% 89.21% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1081 1.16% 90.37% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 92847 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 7530 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 28.938645 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 528.498472 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 7529 99.99% 99.99% # Reads before turning the bus around for writes | 233system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 95193 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 270.047419 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 149.647814 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 324.885603 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 47290 49.68% 49.68% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 18811 19.76% 69.44% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 6810 7.15% 76.59% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3608 3.79% 80.38% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 3189 3.35% 83.73% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 2125 2.23% 85.97% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 1286 1.35% 87.32% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 1091 1.15% 88.46% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 10983 11.54% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 95193 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 7956 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 27.345777 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 514.192665 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 7955 99.99% 99.99% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes | 258system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 262system.physmem.rdPerTurnAround::total 7530 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 7530 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 19.941833 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.646034 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 10.689402 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 6119 81.26% 81.26% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 568 7.54% 88.80% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 91 1.21% 90.01% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 218 2.90% 92.91% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 217 2.88% 95.79% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 12 0.16% 95.95% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 20 0.27% 96.22% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 25 0.33% 96.55% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 26 0.35% 96.89% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 6 0.08% 97.08% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 5 0.07% 97.14% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 157 2.08% 99.23% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 8 0.11% 99.43% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 4 0.05% 99.48% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 13 0.17% 99.65% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.01% 99.67% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 1 0.01% 99.68% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 6 0.08% 99.76% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 2 0.03% 99.79% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::108-111 2 0.03% 99.81% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 7 0.09% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 7530 # Writes before turning the bus around for reads 295system.physmem.totQLat 8946488000 # Total ticks spent queuing 296system.physmem.totMemAccLat 13032263000 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 1089540000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 41056.26 # Average queueing delay per DRAM burst | 259system.physmem.rdPerTurnAround::total 7956 # Reads before turning the bus around for writes 260system.physmem.wrPerTurnAround::samples 7956 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::mean 23.139517 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::gmean 19.869319 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::stdev 20.452539 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::16-19 6216 78.13% 78.13% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::20-23 561 7.05% 85.18% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::24-27 92 1.16% 86.34% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::28-31 246 3.09% 89.43% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::32-35 152 1.91% 91.34% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::36-39 55 0.69% 92.03% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::40-43 34 0.43% 92.46% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::44-47 37 0.47% 92.92% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::48-51 126 1.58% 94.51% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::52-55 18 0.23% 94.73% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::56-59 19 0.24% 94.97% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::60-63 9 0.11% 95.09% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::64-67 35 0.44% 95.53% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::68-71 15 0.19% 95.71% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::72-75 9 0.11% 95.83% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::76-79 35 0.44% 96.27% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::80-83 47 0.59% 96.86% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::84-87 11 0.14% 97.00% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::88-91 5 0.06% 97.06% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::92-95 9 0.11% 97.17% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::96-99 88 1.11% 98.28% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::100-103 3 0.04% 98.32% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::104-107 8 0.10% 98.42% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::108-111 2 0.03% 98.44% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 17 0.21% 98.66% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::116-119 6 0.08% 98.73% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::120-123 8 0.10% 98.83% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::124-127 3 0.04% 98.87% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::128-131 29 0.36% 99.23% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::132-135 10 0.13% 99.36% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::136-139 2 0.03% 99.38% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 4 0.05% 99.43% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 7 0.09% 99.52% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::148-151 7 0.09% 99.61% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::152-155 5 0.06% 99.67% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::156-159 2 0.03% 99.70% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::160-163 6 0.08% 99.77% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::164-167 1 0.01% 99.79% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::168-171 3 0.04% 99.82% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::176-179 5 0.06% 99.89% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::180-183 1 0.01% 99.90% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::188-191 1 0.01% 99.91% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::196-199 1 0.01% 99.92% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::200-203 2 0.03% 99.95% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::204-207 2 0.03% 99.97% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::total 7956 # Writes before turning the bus around for reads 312system.physmem.totQLat 8935367250 # Total ticks spent queuing 313system.physmem.totMemAccLat 13014767250 # Total ticks spent from burst creation until serviced by the DRAM 314system.physmem.totBusLat 1087840000 # Total ticks spent in databus transfers 315system.physmem.avgQLat 41069.31 # Average queueing delay per DRAM burst |
| 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 316system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 300system.physmem.avgMemAccLat 59806.26 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s | 317system.physmem.avgMemAccLat 59819.31 # Average memory access latency per DRAM burst 318system.physmem.avgRdBW 4.93 # Average DRAM read bandwidth in MiByte/s 319system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s 320system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s 321system.physmem.avgWrBWSys 4.22 # Average system write bandwidth in MiByte/s |
| 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.07 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 322system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 323system.physmem.busUtil 0.07 # Data bus utilization in percentage 324system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 325system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 309system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 23.08 # Average write queue length when enqueuing 311system.physmem.readRowHits 185273 # Number of row buffer hits during reads 312system.physmem.writeRowHits 89950 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 85.02 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 59.89 # Row buffer hit rate for writes 315system.physmem.avgGap 7587422.14 # Average gap between requests 316system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined 317system.physmem.memoryStateTime::IDLE 2697372741500 # Time in different power states 318system.physmem.memoryStateTime::REF 94311620000 # Time in different power states | 326system.physmem.avgRdQLen 2.29 # Average read queue length when enqueuing 327system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing 328system.physmem.readRowHits 184937 # Number of row buffer hits during reads 329system.physmem.writeRowHits 121536 # Number of row buffer hits during writes 330system.physmem.readRowHitRate 85.00 # Row buffer hit rate for reads 331system.physmem.writeRowHitRate 66.01 # Row buffer hit rate for writes 332system.physmem.avgGap 6923437.45 # Average gap between requests 333system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined 334system.physmem.memoryStateTime::IDLE 2697464747500 # Time in different power states 335system.physmem.memoryStateTime::REF 94318380000 # Time in different power states |
| 319system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 336system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 320system.physmem.memoryStateTime::ACT 32676864750 # Time in different power states | 337system.physmem.memoryStateTime::ACT 32780541250 # Time in different power states |
| 321system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 338system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 322system.physmem.actEnergy::0 364906080 # Energy for activate commands per rank (pJ) 323system.physmem.actEnergy::1 337017240 # Energy for activate commands per rank (pJ) 324system.physmem.preEnergy::0 199105500 # Energy for precharge commands per rank (pJ) 325system.physmem.preEnergy::1 183888375 # Energy for precharge commands per rank (pJ) 326system.physmem.readEnergy::0 880113000 # Energy for read commands per rank (pJ) 327system.physmem.readEnergy::1 819569400 # Energy for read commands per rank (pJ) 328system.physmem.writeEnergy::0 496944720 # Energy for write commands per rank (pJ) 329system.physmem.writeEnergy::1 476105040 # Energy for write commands per rank (pJ) 330system.physmem.refreshEnergy::0 184473528720 # Energy for refresh commands per rank (pJ) 331system.physmem.refreshEnergy::1 184473528720 # Energy for refresh commands per rank (pJ) 332system.physmem.actBackEnergy::0 78935898240 # Energy for active background per rank (pJ) 333system.physmem.actBackEnergy::1 78466357035 # Energy for active background per rank (pJ) 334system.physmem.preBackEnergy::0 1625374711500 # Energy for precharge background per rank (pJ) 335system.physmem.preBackEnergy::1 1625786589750 # Energy for precharge background per rank (pJ) 336system.physmem.totalEnergy::0 1890725207760 # Total energy per rank (pJ) 337system.physmem.totalEnergy::1 1890543055560 # Total energy per rank (pJ) 338system.physmem.averagePower::0 669.434632 # Core power per rank (mW) 339system.physmem.averagePower::1 669.370138 # Core power per rank (mW) | 339system.physmem.actEnergy::0 374477040 # Energy for activate commands per rank (pJ) 340system.physmem.actEnergy::1 345182040 # Energy for activate commands per rank (pJ) 341system.physmem.preEnergy::0 204327750 # Energy for precharge commands per rank (pJ) 342system.physmem.preEnergy::1 188343375 # Energy for precharge commands per rank (pJ) 343system.physmem.readEnergy::0 878716800 # Energy for read commands per rank (pJ) 344system.physmem.readEnergy::1 818313600 # Energy for read commands per rank (pJ) 345system.physmem.writeEnergy::0 606787200 # Energy for write commands per rank (pJ) 346system.physmem.writeEnergy::1 586167840 # Energy for write commands per rank (pJ) 347system.physmem.refreshEnergy::0 184486751280 # Energy for refresh commands per rank (pJ) 348system.physmem.refreshEnergy::1 184486751280 # Energy for refresh commands per rank (pJ) 349system.physmem.actBackEnergy::0 79037968995 # Energy for active background per rank (pJ) 350system.physmem.actBackEnergy::1 78368155155 # Energy for active background per rank (pJ) 351system.physmem.preBackEnergy::0 1625406641250 # Energy for precharge background per rank (pJ) 352system.physmem.preBackEnergy::1 1625994197250 # Energy for precharge background per rank (pJ) 353system.physmem.totalEnergy::0 1890995670315 # Total energy per rank (pJ) 354system.physmem.totalEnergy::1 1890787110540 # Total energy per rank (pJ) 355system.physmem.averagePower::0 669.482406 # Core power per rank (mW) 356system.physmem.averagePower::1 669.408568 # Core power per rank (mW) |
| 340system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 346system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 347system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 356system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) 358system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 359system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 360system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 361system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 362system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 363system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 357system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 362system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 363system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 373system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) 375system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 376system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 377system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 378system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 379system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 380system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 364system.cpu0.branchPred.lookups 24027931 # Number of BP lookups 365system.cpu0.branchPred.condPredicted 15718166 # Number of conditional branches predicted 366system.cpu0.branchPred.condIncorrect 977317 # Number of conditional branches incorrect 367system.cpu0.branchPred.BTBLookups 14657289 # Number of BTB lookups 368system.cpu0.branchPred.BTBHits 10772949 # Number of BTB hits | 381system.cpu0.branchPred.lookups 24032454 # Number of BP lookups 382system.cpu0.branchPred.condPredicted 15719473 # Number of conditional branches predicted 383system.cpu0.branchPred.condIncorrect 977282 # Number of conditional branches incorrect 384system.cpu0.branchPred.BTBLookups 14661590 # Number of BTB lookups 385system.cpu0.branchPred.BTBHits 10774814 # Number of BTB hits |
| 369system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 386system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 370system.cpu0.branchPred.BTBHitPct 73.498919 # BTB Hit Percentage 371system.cpu0.branchPred.usedRAS 3877670 # Number of times the RAS was used to get a target. 372system.cpu0.branchPred.RASInCorrect 32392 # Number of incorrect RAS predictions. | 387system.cpu0.branchPred.BTBHitPct 73.490078 # BTB Hit Percentage 388system.cpu0.branchPred.usedRAS 3879582 # Number of times the RAS was used to get a target. 389system.cpu0.branchPred.RASInCorrect 32449 # Number of incorrect RAS predictions. |
| 373system.cpu_clk_domain.clock 500 # Clock period in ticks 374system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 375system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 376system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 377system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 378system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 379system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 380system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 389system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 395system.cpu0.dtb.inst_hits 0 # ITB inst hits 396system.cpu0.dtb.inst_misses 0 # ITB inst misses | 390system.cpu_clk_domain.clock 500 # Clock period in ticks 391system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 392system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 393system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 394system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 395system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 396system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 406system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 407system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 408system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 409system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 410system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 411system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 412system.cpu0.dtb.inst_hits 0 # ITB inst hits 413system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 397system.cpu0.dtb.read_hits 17722563 # DTB read hits 398system.cpu0.dtb.read_misses 56347 # DTB read misses 399system.cpu0.dtb.write_hits 14648246 # DTB write hits 400system.cpu0.dtb.write_misses 8736 # DTB write misses | 414system.cpu0.dtb.read_hits 17723797 # DTB read hits 415system.cpu0.dtb.read_misses 56461 # DTB read misses 416system.cpu0.dtb.write_hits 14648555 # DTB write hits 417system.cpu0.dtb.write_misses 8741 # DTB write misses |
| 401system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 402system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 403system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 404system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 418system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 419system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 420system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 421system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 405system.cpu0.dtb.flush_entries 3529 # Number of entries that have been flushed from TLB 406system.cpu0.dtb.align_faults 316 # Number of TLB faults due to alignment restrictions 407system.cpu0.dtb.prefetch_faults 2360 # Number of TLB faults due to prefetch | 422system.cpu0.dtb.flush_entries 3527 # Number of entries that have been flushed from TLB 423system.cpu0.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions 424system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch |
| 408system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 425system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 409system.cpu0.dtb.perms_faults 858 # Number of TLB faults due to permissions restrictions 410system.cpu0.dtb.read_accesses 17778910 # DTB read accesses 411system.cpu0.dtb.write_accesses 14656982 # DTB write accesses | 426system.cpu0.dtb.perms_faults 868 # Number of TLB faults due to permissions restrictions 427system.cpu0.dtb.read_accesses 17780258 # DTB read accesses 428system.cpu0.dtb.write_accesses 14657296 # DTB write accesses |
| 412system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 429system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 413system.cpu0.dtb.hits 32370809 # DTB hits 414system.cpu0.dtb.misses 65083 # DTB misses 415system.cpu0.dtb.accesses 32435892 # DTB accesses | 430system.cpu0.dtb.hits 32372352 # DTB hits 431system.cpu0.dtb.misses 65202 # DTB misses 432system.cpu0.dtb.accesses 32437554 # DTB accesses |
| 416system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 417system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 418system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 419system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 420system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 421system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 422system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 423system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 429system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 430system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 431system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 432system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 433system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 434system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 435system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 436system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 433system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 434system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 435system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 436system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 437system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 438system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 439system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 440system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 446system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 448system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 449system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 450system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 451system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 452system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 453system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 437system.cpu0.itb.inst_hits 37749898 # ITB inst hits 438system.cpu0.itb.inst_misses 10270 # ITB inst misses | 454system.cpu0.itb.inst_hits 37754755 # ITB inst hits 455system.cpu0.itb.inst_misses 10287 # ITB inst misses |
| 439system.cpu0.itb.read_hits 0 # DTB read hits 440system.cpu0.itb.read_misses 0 # DTB read misses 441system.cpu0.itb.write_hits 0 # DTB write hits 442system.cpu0.itb.write_misses 0 # DTB write misses 443system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 444system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 456system.cpu0.itb.read_hits 0 # DTB read hits 457system.cpu0.itb.read_misses 0 # DTB read misses 458system.cpu0.itb.write_hits 0 # DTB write hits 459system.cpu0.itb.write_misses 0 # DTB write misses 460system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 461system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 462system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 463system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 447system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB | 464system.cpu0.itb.flush_entries 2369 # Number of entries that have been flushed from TLB |
| 448system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 449system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 450system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 465system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 466system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 467system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 451system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions | 468system.cpu0.itb.perms_faults 1949 # Number of TLB faults due to permissions restrictions |
| 452system.cpu0.itb.read_accesses 0 # DTB read accesses 453system.cpu0.itb.write_accesses 0 # DTB write accesses | 469system.cpu0.itb.read_accesses 0 # DTB read accesses 470system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 454system.cpu0.itb.inst_accesses 37760168 # ITB inst accesses 455system.cpu0.itb.hits 37749898 # DTB hits 456system.cpu0.itb.misses 10270 # DTB misses 457system.cpu0.itb.accesses 37760168 # DTB accesses 458system.cpu0.numCycles 126937172 # number of cpu cycles simulated | 471system.cpu0.itb.inst_accesses 37765042 # ITB inst accesses 472system.cpu0.itb.hits 37754755 # DTB hits 473system.cpu0.itb.misses 10287 # DTB misses 474system.cpu0.itb.accesses 37765042 # DTB accesses 475system.cpu0.numCycles 126967483 # number of cpu cycles simulated |
| 459system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 460system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 476system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 477system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 461system.cpu0.fetch.icacheStallCycles 18140410 # Number of cycles fetch is stalled on an Icache miss 462system.cpu0.fetch.Insts 112713647 # Number of instructions fetch has processed 463system.cpu0.fetch.Branches 24027931 # Number of branches that fetch encountered 464system.cpu0.fetch.predictedBranches 14650619 # Number of branches that fetch has predicted taken 465system.cpu0.fetch.Cycles 104775763 # Number of cycles fetch has run and was not squashing or blocked 466system.cpu0.fetch.SquashCycles 2822832 # Number of cycles fetch has spent squashing 467system.cpu0.fetch.TlbCycles 131776 # Number of cycles fetch has spent waiting for tlb 468system.cpu0.fetch.MiscStallCycles 38634 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 469system.cpu0.fetch.PendingTrapStallCycles 364177 # Number of stall cycles due to pending traps 470system.cpu0.fetch.PendingQuiesceStallCycles 430173 # Number of stall cycles due to pending quiesce instructions 471system.cpu0.fetch.IcacheWaitRetryStallCycles 37568 # Number of stall cycles due to full MSHR 472system.cpu0.fetch.CacheLines 37750515 # Number of cache lines fetched 473system.cpu0.fetch.IcacheSquashes 265085 # Number of outstanding Icache misses that were squashed 474system.cpu0.fetch.ItlbSquashes 3932 # Number of outstanding ITLB misses that were squashed 475system.cpu0.fetch.rateDist::samples 125329917 # Number of instructions fetched each cycle (Total) 476system.cpu0.fetch.rateDist::mean 1.084963 # Number of instructions fetched each cycle (Total) 477system.cpu0.fetch.rateDist::stdev 1.263075 # Number of instructions fetched each cycle (Total) | 478system.cpu0.fetch.icacheStallCycles 18140354 # Number of cycles fetch is stalled on an Icache miss 479system.cpu0.fetch.Insts 112726031 # Number of instructions fetch has processed 480system.cpu0.fetch.Branches 24032454 # Number of branches that fetch encountered 481system.cpu0.fetch.predictedBranches 14654396 # Number of branches that fetch has predicted taken 482system.cpu0.fetch.Cycles 104803073 # Number of cycles fetch has run and was not squashing or blocked 483system.cpu0.fetch.SquashCycles 2823208 # Number of cycles fetch has spent squashing 484system.cpu0.fetch.TlbCycles 134368 # Number of cycles fetch has spent waiting for tlb 485system.cpu0.fetch.MiscStallCycles 38414 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 486system.cpu0.fetch.PendingTrapStallCycles 364228 # Number of stall cycles due to pending traps 487system.cpu0.fetch.PendingQuiesceStallCycles 430065 # Number of stall cycles due to pending quiesce instructions 488system.cpu0.fetch.IcacheWaitRetryStallCycles 37874 # Number of stall cycles due to full MSHR 489system.cpu0.fetch.CacheLines 37755386 # Number of cache lines fetched 490system.cpu0.fetch.IcacheSquashes 265155 # Number of outstanding Icache misses that were squashed 491system.cpu0.fetch.ItlbSquashes 3922 # Number of outstanding ITLB misses that were squashed 492system.cpu0.fetch.rateDist::samples 125359980 # Number of instructions fetched each cycle (Total) 493system.cpu0.fetch.rateDist::mean 1.084816 # Number of instructions fetched each cycle (Total) 494system.cpu0.fetch.rateDist::stdev 1.263057 # Number of instructions fetched each cycle (Total) |
| 478system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 495system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 479system.cpu0.fetch.rateDist::0 62773644 50.09% 50.09% # Number of instructions fetched each cycle (Total) 480system.cpu0.fetch.rateDist::1 21461872 17.12% 67.21% # Number of instructions fetched each cycle (Total) 481system.cpu0.fetch.rateDist::2 8766803 6.99% 74.21% # Number of instructions fetched each cycle (Total) 482system.cpu0.fetch.rateDist::3 32327598 25.79% 100.00% # Number of instructions fetched each cycle (Total) | 496system.cpu0.fetch.rateDist::0 62797458 50.09% 50.09% # Number of instructions fetched each cycle (Total) 497system.cpu0.fetch.rateDist::1 21463892 17.12% 67.22% # Number of instructions fetched each cycle (Total) 498system.cpu0.fetch.rateDist::2 8767294 6.99% 74.21% # Number of instructions fetched each cycle (Total) 499system.cpu0.fetch.rateDist::3 32331336 25.79% 100.00% # Number of instructions fetched each cycle (Total) |
| 483system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 484system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 485system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 500system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 501system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 502system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 486system.cpu0.fetch.rateDist::total 125329917 # Number of instructions fetched each cycle (Total) 487system.cpu0.fetch.branchRate 0.189290 # Number of branch fetches per cycle 488system.cpu0.fetch.rate 0.887948 # Number of inst fetches per cycle 489system.cpu0.decode.IdleCycles 19211260 # Number of cycles decode is idle 490system.cpu0.decode.BlockedCycles 58677383 # Number of cycles decode is blocked 491system.cpu0.decode.RunCycles 41416135 # Number of cycles decode is running 492system.cpu0.decode.UnblockCycles 4957927 # Number of cycles decode is unblocking 493system.cpu0.decode.SquashCycles 1067212 # Number of cycles decode is squashing 494system.cpu0.decode.BranchResolved 3055574 # Number of times decode resolved a branch 495system.cpu0.decode.BranchMispred 348409 # Number of times decode detected a branch misprediction 496system.cpu0.decode.DecodedInsts 110727822 # Number of instructions handled by decode 497system.cpu0.decode.SquashedInsts 3998029 # Number of squashed instructions handled by decode 498system.cpu0.rename.SquashCycles 1067212 # Number of cycles rename is squashing 499system.cpu0.rename.IdleCycles 24961632 # Number of cycles rename is idle 500system.cpu0.rename.BlockCycles 12004838 # Number of cycles rename is blocking 501system.cpu0.rename.serializeStallCycles 36556596 # count of cycles rename stalled for serializing inst 502system.cpu0.rename.RunCycles 40485229 # Number of cycles rename is running 503system.cpu0.rename.UnblockCycles 10254410 # Number of cycles rename is unblocking 504system.cpu0.rename.RenamedInsts 105647594 # Number of instructions processed by rename 505system.cpu0.rename.SquashedInsts 1060765 # Number of squashed instructions processed by rename 506system.cpu0.rename.ROBFullEvents 1435224 # Number of times rename has blocked due to ROB full 507system.cpu0.rename.IQFullEvents 161199 # Number of times rename has blocked due to IQ full 508system.cpu0.rename.LQFullEvents 61281 # Number of times rename has blocked due to LQ full 509system.cpu0.rename.SQFullEvents 6055537 # Number of times rename has blocked due to SQ full 510system.cpu0.rename.RenamedOperands 109729609 # Number of destination operands rename has renamed 511system.cpu0.rename.RenameLookups 482383818 # Number of register rename lookups that rename has made 512system.cpu0.rename.int_rename_lookups 120922156 # Number of integer rename lookups | 503system.cpu0.fetch.rateDist::total 125359980 # Number of instructions fetched each cycle (Total) 504system.cpu0.fetch.branchRate 0.189280 # Number of branch fetches per cycle 505system.cpu0.fetch.rate 0.887834 # Number of inst fetches per cycle 506system.cpu0.decode.IdleCycles 19213877 # Number of cycles decode is idle 507system.cpu0.decode.BlockedCycles 58702572 # Number of cycles decode is blocked 508system.cpu0.decode.RunCycles 41417912 # Number of cycles decode is running 509system.cpu0.decode.UnblockCycles 4958150 # Number of cycles decode is unblocking 510system.cpu0.decode.SquashCycles 1067469 # Number of cycles decode is squashing 511system.cpu0.decode.BranchResolved 3055480 # Number of times decode resolved a branch 512system.cpu0.decode.BranchMispred 348347 # Number of times decode detected a branch misprediction 513system.cpu0.decode.DecodedInsts 110732586 # Number of instructions handled by decode 514system.cpu0.decode.SquashedInsts 3998245 # Number of squashed instructions handled by decode 515system.cpu0.rename.SquashCycles 1067469 # Number of cycles rename is squashing 516system.cpu0.rename.IdleCycles 24964892 # Number of cycles rename is idle 517system.cpu0.rename.BlockCycles 12028946 # Number of cycles rename is blocking 518system.cpu0.rename.serializeStallCycles 36555738 # count of cycles rename stalled for serializing inst 519system.cpu0.rename.RunCycles 40486723 # Number of cycles rename is running 520system.cpu0.rename.UnblockCycles 10256212 # Number of cycles rename is unblocking 521system.cpu0.rename.RenamedInsts 105650222 # Number of instructions processed by rename 522system.cpu0.rename.SquashedInsts 1060720 # Number of squashed instructions processed by rename 523system.cpu0.rename.ROBFullEvents 1433198 # Number of times rename has blocked due to ROB full 524system.cpu0.rename.IQFullEvents 161272 # Number of times rename has blocked due to IQ full 525system.cpu0.rename.LQFullEvents 61252 # Number of times rename has blocked due to LQ full 526system.cpu0.rename.SQFullEvents 6057790 # Number of times rename has blocked due to SQ full 527system.cpu0.rename.RenamedOperands 109732658 # Number of destination operands rename has renamed 528system.cpu0.rename.RenameLookups 482396625 # Number of register rename lookups that rename has made 529system.cpu0.rename.int_rename_lookups 120923658 # Number of integer rename lookups |
| 513system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups | 530system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups |
| 514system.cpu0.rename.CommittedMaps 98138163 # Number of HB maps that are committed 515system.cpu0.rename.UndoneMaps 11591443 # Number of HB maps that are undone due to squashing 516system.cpu0.rename.serializingInsts 1228785 # count of serializing insts renamed 517system.cpu0.rename.tempSerializingInsts 1087461 # count of temporary serializing insts renamed 518system.cpu0.rename.skidInsts 12318010 # count of insts added to the skid buffer 519system.cpu0.memDep0.insertedLoads 18735902 # Number of loads inserted to the mem dependence unit. 520system.cpu0.memDep0.insertedStores 16202980 # Number of stores inserted to the mem dependence unit. 521system.cpu0.memDep0.conflictingLoads 1699572 # Number of conflicting loads. 522system.cpu0.memDep0.conflictingStores 2289990 # Number of conflicting stores. 523system.cpu0.iq.iqInstsAdded 102687216 # Number of instructions added to the IQ (excludes non-spec) 524system.cpu0.iq.iqNonSpecInstsAdded 1694558 # Number of non-speculative instructions added to the IQ 525system.cpu0.iq.iqInstsIssued 100671408 # Number of instructions issued 526system.cpu0.iq.iqSquashedInstsIssued 483936 # Number of squashed instructions issued 527system.cpu0.iq.iqSquashedInstsExamined 9020941 # Number of squashed instructions iterated over during squash; mainly for profiling 528system.cpu0.iq.iqSquashedOperandsExamined 22487287 # Number of squashed operands that are examined and possibly removed from graph 529system.cpu0.iq.iqSquashedNonSpecRemoved 122833 # Number of squashed non-spec instructions that were removed 530system.cpu0.iq.issued_per_cycle::samples 125329917 # Number of insts issued each cycle 531system.cpu0.iq.issued_per_cycle::mean 0.803251 # Number of insts issued each cycle 532system.cpu0.iq.issued_per_cycle::stdev 1.034851 # Number of insts issued each cycle | 531system.cpu0.rename.CommittedMaps 98143798 # Number of HB maps that are committed 532system.cpu0.rename.UndoneMaps 11588857 # Number of HB maps that are undone due to squashing 533system.cpu0.rename.serializingInsts 1229050 # count of serializing insts renamed 534system.cpu0.rename.tempSerializingInsts 1087734 # count of temporary serializing insts renamed 535system.cpu0.rename.skidInsts 12319550 # count of insts added to the skid buffer 536system.cpu0.memDep0.insertedLoads 18736791 # Number of loads inserted to the mem dependence unit. 537system.cpu0.memDep0.insertedStores 16202841 # Number of stores inserted to the mem dependence unit. 538system.cpu0.memDep0.conflictingLoads 1700720 # Number of conflicting loads. 539system.cpu0.memDep0.conflictingStores 2277601 # Number of conflicting stores. 540system.cpu0.iq.iqInstsAdded 102690318 # Number of instructions added to the IQ (excludes non-spec) 541system.cpu0.iq.iqNonSpecInstsAdded 1694621 # Number of non-speculative instructions added to the IQ 542system.cpu0.iq.iqInstsIssued 100676052 # Number of instructions issued 543system.cpu0.iq.iqSquashedInstsIssued 483863 # Number of squashed instructions issued 544system.cpu0.iq.iqSquashedInstsExamined 9017764 # Number of squashed instructions iterated over during squash; mainly for profiling 545system.cpu0.iq.iqSquashedOperandsExamined 22481770 # Number of squashed operands that are examined and possibly removed from graph 546system.cpu0.iq.iqSquashedNonSpecRemoved 122874 # Number of squashed non-spec instructions that were removed 547system.cpu0.iq.issued_per_cycle::samples 125359980 # Number of insts issued each cycle 548system.cpu0.iq.issued_per_cycle::mean 0.803096 # Number of insts issued each cycle 549system.cpu0.iq.issued_per_cycle::stdev 1.034807 # Number of insts issued each cycle |
| 533system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 550system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 534system.cpu0.iq.issued_per_cycle::0 69186063 55.20% 55.20% # Number of insts issued each cycle 535system.cpu0.iq.issued_per_cycle::1 23179586 18.49% 73.70% # Number of insts issued each cycle 536system.cpu0.iq.issued_per_cycle::2 22515563 17.97% 91.66% # Number of insts issued each cycle 537system.cpu0.iq.issued_per_cycle::3 9334163 7.45% 99.11% # Number of insts issued each cycle 538system.cpu0.iq.issued_per_cycle::4 1114503 0.89% 100.00% # Number of insts issued each cycle 539system.cpu0.iq.issued_per_cycle::5 39 0.00% 100.00% # Number of insts issued each cycle | 551system.cpu0.iq.issued_per_cycle::0 69212985 55.21% 55.21% # Number of insts issued each cycle 552system.cpu0.iq.issued_per_cycle::1 23181797 18.49% 73.70% # Number of insts issued each cycle 553system.cpu0.iq.issued_per_cycle::2 22515986 17.96% 91.66% # Number of insts issued each cycle 554system.cpu0.iq.issued_per_cycle::3 9334603 7.45% 99.11% # Number of insts issued each cycle 555system.cpu0.iq.issued_per_cycle::4 1114571 0.89% 100.00% # Number of insts issued each cycle 556system.cpu0.iq.issued_per_cycle::5 38 0.00% 100.00% # Number of insts issued each cycle |
| 540system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 541system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 542system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 543system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 544system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 545system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 557system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 558system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 559system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 560system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 561system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 562system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 546system.cpu0.iq.issued_per_cycle::total 125329917 # Number of insts issued each cycle | 563system.cpu0.iq.issued_per_cycle::total 125359980 # Number of insts issued each cycle |
| 547system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 564system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 548system.cpu0.iq.fu_full::IntAlu 9379139 40.75% 40.75% # attempts to use FU when none available | 565system.cpu0.iq.fu_full::IntAlu 9379077 40.75% 40.75% # attempts to use FU when none available |
| 549system.cpu0.iq.fu_full::IntMult 80 0.00% 40.75% # attempts to use FU when none available 550system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available 551system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available 552system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available 553system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available 554system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available 555system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available 556system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 569system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available 570system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available 571system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available 572system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available 573system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available 574system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available 575system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available 576system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available | 566system.cpu0.iq.fu_full::IntMult 80 0.00% 40.75% # attempts to use FU when none available 567system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available 568system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available 569system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available 570system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available 571system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available 572system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available 573system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 586system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available 587system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available 588system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available 589system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available 590system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available 591system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available 592system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available 593system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available |
| 577system.cpu0.iq.fu_full::MemRead 5583986 24.26% 65.02% # attempts to use FU when none available 578system.cpu0.iq.fu_full::MemWrite 8051096 34.98% 100.00% # attempts to use FU when none available | 594system.cpu0.iq.fu_full::MemRead 5582793 24.26% 65.00% # attempts to use FU when none available 595system.cpu0.iq.fu_full::MemWrite 8054863 35.00% 100.00% # attempts to use FU when none available |
| 579system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 580system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 581system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued | 596system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 597system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 598system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued |
| 582system.cpu0.iq.FU_type_0::IntAlu 66410061 65.97% 65.97% # Type of FU issued 583system.cpu0.iq.FU_type_0::IntMult 93146 0.09% 66.06% # Type of FU issued | 599system.cpu0.iq.FU_type_0::IntAlu 66413118 65.97% 65.97% # Type of FU issued 600system.cpu0.iq.FU_type_0::IntMult 93141 0.09% 66.06% # Type of FU issued |
| 584system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued | 601system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued |
| 585system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued | 602system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.06% # Type of FU issued |
| 586system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 587system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 588system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 589system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 590system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 591system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued 592system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued 593system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 599system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 600system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 601system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 602system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 603system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 604system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 605system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 606system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued | 603system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 604system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 605system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 606system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 607system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 608system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued 609system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued 610system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 616system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 617system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 618system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 619system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 620system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 621system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 622system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 623system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued |
| 607system.cpu0.iq.FU_type_0::SimdFloatMisc 8111 0.01% 66.07% # Type of FU issued | 624system.cpu0.iq.FU_type_0::SimdFloatMisc 8113 0.01% 66.07% # Type of FU issued |
| 608system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued 609system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued 610system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued | 625system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued 626system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued 627system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued |
| 611system.cpu0.iq.FU_type_0::MemRead 18430824 18.31% 84.38% # Type of FU issued 612system.cpu0.iq.FU_type_0::MemWrite 15726990 15.62% 100.00% # Type of FU issued | 628system.cpu0.iq.FU_type_0::MemRead 18432239 18.31% 84.38% # Type of FU issued 629system.cpu0.iq.FU_type_0::MemWrite 15727166 15.62% 100.00% # Type of FU issued |
| 613system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 614system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 630system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 631system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 615system.cpu0.iq.FU_type_0::total 100671408 # Type of FU issued 616system.cpu0.iq.rate 0.793081 # Inst issue rate 617system.cpu0.iq.fu_busy_cnt 23014301 # FU busy when requested 618system.cpu0.iq.fu_busy_rate 0.228608 # FU busy rate (busy events/executed inst) 619system.cpu0.iq.int_inst_queue_reads 350139117 # Number of integer instruction queue reads 620system.cpu0.iq.int_inst_queue_writes 113410576 # Number of integer instruction queue writes 621system.cpu0.iq.int_inst_queue_wakeup_accesses 98583429 # Number of integer instruction queue wakeup accesses 622system.cpu0.iq.fp_inst_queue_reads 31853 # Number of floating instruction queue reads | 632system.cpu0.iq.FU_type_0::total 100676052 # Type of FU issued 633system.cpu0.iq.rate 0.792928 # Inst issue rate 634system.cpu0.iq.fu_busy_cnt 23016813 # FU busy when requested 635system.cpu0.iq.fu_busy_rate 0.228623 # FU busy rate (busy events/executed inst) 636system.cpu0.iq.int_inst_queue_reads 350180984 # Number of integer instruction queue reads 637system.cpu0.iq.int_inst_queue_writes 113410550 # Number of integer instruction queue writes 638system.cpu0.iq.int_inst_queue_wakeup_accesses 98587478 # Number of integer instruction queue wakeup accesses 639system.cpu0.iq.fp_inst_queue_reads 31776 # Number of floating instruction queue reads |
| 623system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes | 640system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes |
| 624system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses 625system.cpu0.iq.int_alu_accesses 123662855 # Number of integer alu accesses 626system.cpu0.iq.fp_alu_accesses 20581 # Number of floating point alu accesses 627system.cpu0.iew.lsq.thread0.forwLoads 365420 # Number of loads that had data forwarded from stores | 641system.cpu0.iq.fp_inst_queue_wakeup_accesses 9721 # Number of floating instruction queue wakeup accesses 642system.cpu0.iq.int_alu_accesses 123670062 # Number of integer alu accesses 643system.cpu0.iq.fp_alu_accesses 20530 # Number of floating point alu accesses 644system.cpu0.iew.lsq.thread0.forwLoads 365459 # Number of loads that had data forwarded from stores |
| 628system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 645system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 629system.cpu0.iew.lsq.thread0.squashedLoads 2006460 # Number of loads squashed 630system.cpu0.iew.lsq.thread0.ignoredResponses 2583 # Number of memory responses ignored because the instruction is squashed 631system.cpu0.iew.lsq.thread0.memOrderViolation 19225 # Number of memory ordering violations 632system.cpu0.iew.lsq.thread0.squashedStores 1022371 # Number of stores squashed | 646system.cpu0.iew.lsq.thread0.squashedLoads 2006136 # Number of loads squashed 647system.cpu0.iew.lsq.thread0.ignoredResponses 2602 # Number of memory responses ignored because the instruction is squashed 648system.cpu0.iew.lsq.thread0.memOrderViolation 19208 # Number of memory ordering violations 649system.cpu0.iew.lsq.thread0.squashedStores 1021760 # Number of stores squashed |
| 633system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 634system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 650system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 651system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 635system.cpu0.iew.lsq.thread0.rescheduledLoads 106487 # Number of loads that were rescheduled 636system.cpu0.iew.lsq.thread0.cacheBlocked 336614 # Number of times an access to memory failed due to the cache being blocked | 652system.cpu0.iew.lsq.thread0.rescheduledLoads 106419 # Number of loads that were rescheduled 653system.cpu0.iew.lsq.thread0.cacheBlocked 336961 # Number of times an access to memory failed due to the cache being blocked |
| 637system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 654system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 638system.cpu0.iew.iewSquashCycles 1067212 # Number of cycles IEW is squashing 639system.cpu0.iew.iewBlockCycles 1617559 # Number of cycles IEW is blocking 640system.cpu0.iew.iewUnblockCycles 190582 # Number of cycles IEW is unblocking 641system.cpu0.iew.iewDispatchedInsts 104556500 # Number of instructions dispatched to IQ | 655system.cpu0.iew.iewSquashCycles 1067469 # Number of cycles IEW is squashing 656system.cpu0.iew.iewBlockCycles 1620814 # Number of cycles IEW is blocking 657system.cpu0.iew.iewUnblockCycles 189225 # Number of cycles IEW is unblocking 658system.cpu0.iew.iewDispatchedInsts 104559654 # Number of instructions dispatched to IQ |
| 642system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 659system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 643system.cpu0.iew.iewDispLoadInsts 18735902 # Number of dispatched load instructions 644system.cpu0.iew.iewDispStoreInsts 16202980 # Number of dispatched store instructions 645system.cpu0.iew.iewDispNonSpecInsts 876211 # Number of dispatched non-speculative instructions 646system.cpu0.iew.iewIQFullEvents 27258 # Number of times the IQ has become full, causing a stall 647system.cpu0.iew.iewLSQFullEvents 139659 # Number of times the LSQ has become full, causing a stall 648system.cpu0.iew.memOrderViolationEvents 19225 # Number of memory order violations 649system.cpu0.iew.predictedTakenIncorrect 291750 # Number of branches that were predicted taken incorrectly 650system.cpu0.iew.predictedNotTakenIncorrect 400567 # Number of branches that were predicted not taken incorrectly 651system.cpu0.iew.branchMispredicts 692317 # Number of branch mispredicts detected at execute 652system.cpu0.iew.iewExecutedInsts 99574081 # Number of executed instructions 653system.cpu0.iew.iewExecLoadInsts 17974103 # Number of load instructions executed 654system.cpu0.iew.iewExecSquashedInsts 1032379 # Number of squashed instructions skipped in execute | 660system.cpu0.iew.iewDispLoadInsts 18736791 # Number of dispatched load instructions 661system.cpu0.iew.iewDispStoreInsts 16202841 # Number of dispatched store instructions 662system.cpu0.iew.iewDispNonSpecInsts 876235 # Number of dispatched non-speculative instructions 663system.cpu0.iew.iewIQFullEvents 27148 # Number of times the IQ has become full, causing a stall 664system.cpu0.iew.iewLSQFullEvents 138418 # Number of times the LSQ has become full, causing a stall 665system.cpu0.iew.memOrderViolationEvents 19208 # Number of memory order violations 666system.cpu0.iew.predictedTakenIncorrect 291783 # Number of branches that were predicted taken incorrectly 667system.cpu0.iew.predictedNotTakenIncorrect 400552 # Number of branches that were predicted not taken incorrectly 668system.cpu0.iew.branchMispredicts 692335 # Number of branch mispredicts detected at execute 669system.cpu0.iew.iewExecutedInsts 99578675 # Number of executed instructions 670system.cpu0.iew.iewExecLoadInsts 17975392 # Number of load instructions executed 671system.cpu0.iew.iewExecSquashedInsts 1032310 # Number of squashed instructions skipped in execute |
| 655system.cpu0.iew.exec_swp 0 # number of swp insts executed | 672system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 656system.cpu0.iew.exec_nop 174726 # number of nop insts executed 657system.cpu0.iew.exec_refs 33509859 # number of memory reference insts executed 658system.cpu0.iew.exec_branches 16843488 # Number of branches executed 659system.cpu0.iew.exec_stores 15535756 # Number of stores executed 660system.cpu0.iew.exec_rate 0.784436 # Inst execution rate 661system.cpu0.iew.wb_sent 99043344 # cumulative count of insts sent to commit 662system.cpu0.iew.wb_count 98593152 # cumulative count of insts written-back 663system.cpu0.iew.wb_producers 51321674 # num instructions producing a value 664system.cpu0.iew.wb_consumers 84801576 # num instructions consuming a value | 673system.cpu0.iew.exec_nop 174715 # number of nop insts executed 674system.cpu0.iew.exec_refs 33511345 # number of memory reference insts executed 675system.cpu0.iew.exec_branches 16844732 # Number of branches executed 676system.cpu0.iew.exec_stores 15535953 # Number of stores executed 677system.cpu0.iew.exec_rate 0.784285 # Inst execution rate 678system.cpu0.iew.wb_sent 99047596 # cumulative count of insts sent to commit 679system.cpu0.iew.wb_count 98597199 # cumulative count of insts written-back 680system.cpu0.iew.wb_producers 51323656 # num instructions producing a value 681system.cpu0.iew.wb_consumers 84802398 # num instructions consuming a value |
| 665system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 682system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 666system.cpu0.iew.wb_rate 0.776708 # insts written-back per cycle 667system.cpu0.iew.wb_fanout 0.605197 # average fanout of values written-back | 683system.cpu0.iew.wb_rate 0.776555 # insts written-back per cycle 684system.cpu0.iew.wb_fanout 0.605215 # average fanout of values written-back |
| 668system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 685system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 669system.cpu0.commit.commitSquashedInsts 8525747 # The number of squashed insts skipped by commit 670system.cpu0.commit.commitNonSpecStalls 1571725 # The number of times commit has been forced to stall to communicate backwards 671system.cpu0.commit.branchMispredicts 633113 # The number of times a branch was mispredicted 672system.cpu0.commit.committed_per_cycle::samples 123576047 # Number of insts commited each cycle 673system.cpu0.commit.committed_per_cycle::mean 0.768210 # Number of insts commited each cycle 674system.cpu0.commit.committed_per_cycle::stdev 1.481297 # Number of insts commited each cycle | 686system.cpu0.commit.commitSquashedInsts 8524425 # The number of squashed insts skipped by commit 687system.cpu0.commit.commitNonSpecStalls 1571747 # The number of times commit has been forced to stall to communicate backwards 688system.cpu0.commit.branchMispredicts 633147 # The number of times a branch was mispredicted 689system.cpu0.commit.committed_per_cycle::samples 123606126 # Number of insts commited each cycle 690system.cpu0.commit.committed_per_cycle::mean 0.768066 # Number of insts commited each cycle 691system.cpu0.commit.committed_per_cycle::stdev 1.480848 # Number of insts commited each cycle |
| 675system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 692system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 676system.cpu0.commit.committed_per_cycle::0 79251877 64.13% 64.13% # Number of insts commited each cycle 677system.cpu0.commit.committed_per_cycle::1 24711108 20.00% 84.13% # Number of insts commited each cycle 678system.cpu0.commit.committed_per_cycle::2 8248464 6.67% 90.80% # Number of insts commited each cycle 679system.cpu0.commit.committed_per_cycle::3 3214478 2.60% 93.40% # Number of insts commited each cycle 680system.cpu0.commit.committed_per_cycle::4 3439388 2.78% 96.19% # Number of insts commited each cycle 681system.cpu0.commit.committed_per_cycle::5 1513562 1.22% 97.41% # Number of insts commited each cycle 682system.cpu0.commit.committed_per_cycle::6 1143910 0.93% 98.34% # Number of insts commited each cycle 683system.cpu0.commit.committed_per_cycle::7 534023 0.43% 98.77% # Number of insts commited each cycle 684system.cpu0.commit.committed_per_cycle::8 1519237 1.23% 100.00% # Number of insts commited each cycle | 693system.cpu0.commit.committed_per_cycle::0 79269760 64.13% 64.13% # Number of insts commited each cycle 694system.cpu0.commit.committed_per_cycle::1 24721020 20.00% 84.13% # Number of insts commited each cycle 695system.cpu0.commit.committed_per_cycle::2 8248963 6.67% 90.80% # Number of insts commited each cycle 696system.cpu0.commit.committed_per_cycle::3 3214548 2.60% 93.40% # Number of insts commited each cycle 697system.cpu0.commit.committed_per_cycle::4 3440916 2.78% 96.19% # Number of insts commited each cycle 698system.cpu0.commit.committed_per_cycle::5 1523839 1.23% 97.42% # Number of insts commited each cycle 699system.cpu0.commit.committed_per_cycle::6 1135185 0.92% 98.34% # Number of insts commited each cycle 700system.cpu0.commit.committed_per_cycle::7 534039 0.43% 98.77% # Number of insts commited each cycle 701system.cpu0.commit.committed_per_cycle::8 1517856 1.23% 100.00% # Number of insts commited each cycle |
| 685system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 686system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 687system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 702system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 703system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 704system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 688system.cpu0.commit.committed_per_cycle::total 123576047 # Number of insts commited each cycle 689system.cpu0.commit.committedInsts 78902307 # Number of instructions committed 690system.cpu0.commit.committedOps 94932349 # Number of ops (including micro ops) committed | 705system.cpu0.commit.committed_per_cycle::total 123606126 # Number of insts commited each cycle 706system.cpu0.commit.committedInsts 78906627 # Number of instructions committed 707system.cpu0.commit.committedOps 94937680 # Number of ops (including micro ops) committed |
| 691system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 708system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 692system.cpu0.commit.refs 31910051 # Number of memory references committed 693system.cpu0.commit.loads 16729442 # Number of loads committed 694system.cpu0.commit.membars 647161 # Number of memory barriers committed 695system.cpu0.commit.branches 16205593 # Number of branches committed | 709system.cpu0.commit.refs 31911736 # Number of memory references committed 710system.cpu0.commit.loads 16730655 # Number of loads committed 711system.cpu0.commit.membars 647181 # Number of memory barriers committed 712system.cpu0.commit.branches 16206992 # Number of branches committed |
| 696system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. | 713system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. |
| 697system.cpu0.commit.int_insts 81881586 # Number of committed integer instructions. 698system.cpu0.commit.function_calls 1929479 # Number of function calls committed. | 714system.cpu0.commit.int_insts 81886422 # Number of committed integer instructions. 715system.cpu0.commit.function_calls 1929931 # Number of function calls committed. |
| 699system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 716system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 700system.cpu0.commit.op_class_0::IntAlu 62923469 66.28% 66.28% # Class of committed instruction 701system.cpu0.commit.op_class_0::IntMult 90718 0.10% 66.38% # Class of committed instruction | 717system.cpu0.commit.op_class_0::IntAlu 62927104 66.28% 66.28% # Class of committed instruction 718system.cpu0.commit.op_class_0::IntMult 90727 0.10% 66.38% # Class of committed instruction |
| 702system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 703system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 704system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 705system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 706system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 707system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 708system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 709system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 717system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 718system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 719system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 720system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 721system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 722system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 723system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 724system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction | 719system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 720system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 721system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 722system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 723system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 724system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 725system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 726system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 734system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 735system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 736system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 737system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 738system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 739system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 740system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 741system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction |
| 725system.cpu0.commit.op_class_0::SimdFloatMisc 8111 0.01% 66.39% # Class of committed instruction | 742system.cpu0.commit.op_class_0::SimdFloatMisc 8113 0.01% 66.39% # Class of committed instruction |
| 726system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction 727system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction 728system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction | 743system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction 744system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction 745system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction |
| 729system.cpu0.commit.op_class_0::MemRead 16729442 17.62% 84.01% # Class of committed instruction 730system.cpu0.commit.op_class_0::MemWrite 15180609 15.99% 100.00% # Class of committed instruction | 746system.cpu0.commit.op_class_0::MemRead 16730655 17.62% 84.01% # Class of committed instruction 747system.cpu0.commit.op_class_0::MemWrite 15181081 15.99% 100.00% # Class of committed instruction |
| 731system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 732system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 748system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 749system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 733system.cpu0.commit.op_class_0::total 94932349 # Class of committed instruction 734system.cpu0.commit.bw_lim_events 1519237 # number cycles where commit BW limit reached | 750system.cpu0.commit.op_class_0::total 94937680 # Class of committed instruction 751system.cpu0.commit.bw_lim_events 1517856 # number cycles where commit BW limit reached |
| 735system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 752system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 736system.cpu0.rob.rob_reads 221333052 # The number of ROB reads 737system.cpu0.rob.rob_writes 208669303 # The number of ROB writes 738system.cpu0.timesIdled 109478 # Number of times that the entire CPU went into an idle state and unscheduled itself 739system.cpu0.idleCycles 1607255 # Total number of cycles that the CPU has spent unscheduled due to idling 740system.cpu0.quiesceCycles 5521794529 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 741system.cpu0.committedInsts 78780256 # Number of Instructions Simulated 742system.cpu0.committedOps 94810298 # Number of Ops (including micro ops) Simulated 743system.cpu0.cpi 1.611282 # CPI: Cycles Per Instruction 744system.cpu0.cpi_total 1.611282 # CPI: Total CPI of All Threads 745system.cpu0.ipc 0.620624 # IPC: Instructions Per Cycle 746system.cpu0.ipc_total 0.620624 # IPC: Total IPC of All Threads 747system.cpu0.int_regfile_reads 110616528 # number of integer regfile reads 748system.cpu0.int_regfile_writes 59738270 # number of integer regfile writes 749system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads 750system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes 751system.cpu0.cc_regfile_reads 350776322 # number of cc regfile reads 752system.cpu0.cc_regfile_writes 41073406 # number of cc regfile writes 753system.cpu0.misc_regfile_reads 245816614 # number of misc regfile reads 754system.cpu0.misc_regfile_writes 1224552 # number of misc regfile writes 755system.cpu0.dcache.tags.replacements 712837 # number of replacements 756system.cpu0.dcache.tags.tagsinuse 493.082878 # Cycle average of tags in use 757system.cpu0.dcache.tags.total_refs 28842463 # Total number of references to valid blocks. 758system.cpu0.dcache.tags.sampled_refs 713349 # Sample count of references to valid blocks. 759system.cpu0.dcache.tags.avg_refs 40.432471 # Average number of references to valid blocks. | 753system.cpu0.rob.rob_reads 221365586 # The number of ROB reads 754system.cpu0.rob.rob_writes 208677314 # The number of ROB writes 755system.cpu0.timesIdled 109557 # Number of times that the entire CPU went into an idle state and unscheduled itself 756system.cpu0.idleCycles 1607503 # Total number of cycles that the CPU has spent unscheduled due to idling 757system.cpu0.quiesceCycles 5522172985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 758system.cpu0.committedInsts 78784576 # Number of Instructions Simulated 759system.cpu0.committedOps 94815629 # Number of Ops (including micro ops) Simulated 760system.cpu0.cpi 1.611578 # CPI: Cycles Per Instruction 761system.cpu0.cpi_total 1.611578 # CPI: Total CPI of All Threads 762system.cpu0.ipc 0.620510 # IPC: Instructions Per Cycle 763system.cpu0.ipc_total 0.620510 # IPC: Total IPC of All Threads 764system.cpu0.int_regfile_reads 110621221 # number of integer regfile reads 765system.cpu0.int_regfile_writes 59741549 # number of integer regfile writes 766system.cpu0.fp_regfile_reads 8143 # number of floating regfile reads 767system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 768system.cpu0.cc_regfile_reads 350793071 # number of cc regfile reads 769system.cpu0.cc_regfile_writes 41074475 # number of cc regfile writes 770system.cpu0.misc_regfile_reads 246484638 # number of misc regfile reads 771system.cpu0.misc_regfile_writes 1224545 # number of misc regfile writes 772system.cpu0.dcache.tags.replacements 712867 # number of replacements 773system.cpu0.dcache.tags.tagsinuse 493.083932 # Cycle average of tags in use 774system.cpu0.dcache.tags.total_refs 28844186 # Total number of references to valid blocks. 775system.cpu0.dcache.tags.sampled_refs 713379 # Sample count of references to valid blocks. 776system.cpu0.dcache.tags.avg_refs 40.433186 # Average number of references to valid blocks. |
| 760system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. | 777system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. |
| 761system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082878 # Average occupied blocks per requestor 762system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy 763system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy | 778system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.083932 # Average occupied blocks per requestor 779system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963055 # Average percentage of cache occupancy 780system.cpu0.dcache.tags.occ_percent::total 0.963055 # Average percentage of cache occupancy |
| 764system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 765system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id 766system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 767system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 768system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 781system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 782system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id 783system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 784system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 785system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 769system.cpu0.dcache.tags.tag_accesses 63484078 # Number of tag accesses 770system.cpu0.dcache.tags.data_accesses 63484078 # Number of data accesses 771system.cpu0.dcache.ReadReq_hits::cpu0.data 15589241 # number of ReadReq hits 772system.cpu0.dcache.ReadReq_hits::total 15589241 # number of ReadReq hits 773system.cpu0.dcache.WriteReq_hits::cpu0.data 12071944 # number of WriteReq hits 774system.cpu0.dcache.WriteReq_hits::total 12071944 # number of WriteReq hits 775system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310964 # number of SoftPFReq hits 776system.cpu0.dcache.SoftPFReq_hits::total 310964 # number of SoftPFReq hits 777system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363200 # number of LoadLockedReq hits 778system.cpu0.dcache.LoadLockedReq_hits::total 363200 # number of LoadLockedReq hits 779system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360654 # number of StoreCondReq hits 780system.cpu0.dcache.StoreCondReq_hits::total 360654 # number of StoreCondReq hits 781system.cpu0.dcache.demand_hits::cpu0.data 27661185 # number of demand (read+write) hits 782system.cpu0.dcache.demand_hits::total 27661185 # number of demand (read+write) hits 783system.cpu0.dcache.overall_hits::cpu0.data 27972149 # number of overall hits 784system.cpu0.dcache.overall_hits::total 27972149 # number of overall hits 785system.cpu0.dcache.ReadReq_misses::cpu0.data 638343 # number of ReadReq misses 786system.cpu0.dcache.ReadReq_misses::total 638343 # number of ReadReq misses 787system.cpu0.dcache.WriteReq_misses::cpu0.data 1832165 # number of WriteReq misses 788system.cpu0.dcache.WriteReq_misses::total 1832165 # number of WriteReq misses 789system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146120 # number of SoftPFReq misses 790system.cpu0.dcache.SoftPFReq_misses::total 146120 # number of SoftPFReq misses 791system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses 792system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses 793system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20612 # number of StoreCondReq misses 794system.cpu0.dcache.StoreCondReq_misses::total 20612 # number of StoreCondReq misses 795system.cpu0.dcache.demand_misses::cpu0.data 2470508 # number of demand (read+write) misses 796system.cpu0.dcache.demand_misses::total 2470508 # number of demand (read+write) misses 797system.cpu0.dcache.overall_misses::cpu0.data 2616628 # number of overall misses 798system.cpu0.dcache.overall_misses::total 2616628 # number of overall misses 799system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8099233830 # number of ReadReq miss cycles 800system.cpu0.dcache.ReadReq_miss_latency::total 8099233830 # number of ReadReq miss cycles 801system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24956974532 # number of WriteReq miss cycles 802system.cpu0.dcache.WriteReq_miss_latency::total 24956974532 # number of WriteReq miss cycles 803system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395327755 # number of LoadLockedReq miss cycles 804system.cpu0.dcache.LoadLockedReq_miss_latency::total 395327755 # number of LoadLockedReq miss cycles 805system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453888287 # number of StoreCondReq miss cycles 806system.cpu0.dcache.StoreCondReq_miss_latency::total 453888287 # number of StoreCondReq miss cycles 807system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 344500 # number of StoreCondFailReq miss cycles 808system.cpu0.dcache.StoreCondFailReq_miss_latency::total 344500 # number of StoreCondFailReq miss cycles 809system.cpu0.dcache.demand_miss_latency::cpu0.data 33056208362 # number of demand (read+write) miss cycles 810system.cpu0.dcache.demand_miss_latency::total 33056208362 # number of demand (read+write) miss cycles 811system.cpu0.dcache.overall_miss_latency::cpu0.data 33056208362 # number of overall miss cycles 812system.cpu0.dcache.overall_miss_latency::total 33056208362 # number of overall miss cycles 813system.cpu0.dcache.ReadReq_accesses::cpu0.data 16227584 # number of ReadReq accesses(hits+misses) 814system.cpu0.dcache.ReadReq_accesses::total 16227584 # number of ReadReq accesses(hits+misses) 815system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904109 # number of WriteReq accesses(hits+misses) 816system.cpu0.dcache.WriteReq_accesses::total 13904109 # number of WriteReq accesses(hits+misses) 817system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457084 # number of SoftPFReq accesses(hits+misses) 818system.cpu0.dcache.SoftPFReq_accesses::total 457084 # number of SoftPFReq accesses(hits+misses) 819system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388176 # number of LoadLockedReq accesses(hits+misses) 820system.cpu0.dcache.LoadLockedReq_accesses::total 388176 # number of LoadLockedReq accesses(hits+misses) 821system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381266 # number of StoreCondReq accesses(hits+misses) 822system.cpu0.dcache.StoreCondReq_accesses::total 381266 # number of StoreCondReq accesses(hits+misses) 823system.cpu0.dcache.demand_accesses::cpu0.data 30131693 # number of demand (read+write) accesses 824system.cpu0.dcache.demand_accesses::total 30131693 # number of demand (read+write) accesses 825system.cpu0.dcache.overall_accesses::cpu0.data 30588777 # number of overall (read+write) accesses 826system.cpu0.dcache.overall_accesses::total 30588777 # number of overall (read+write) accesses 827system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039337 # miss rate for ReadReq accesses 828system.cpu0.dcache.ReadReq_miss_rate::total 0.039337 # miss rate for ReadReq accesses 829system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131771 # miss rate for WriteReq accesses 830system.cpu0.dcache.WriteReq_miss_rate::total 0.131771 # miss rate for WriteReq accesses 831system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319679 # miss rate for SoftPFReq accesses 832system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319679 # miss rate for SoftPFReq accesses 833system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses 834system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses 835system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054062 # miss rate for StoreCondReq accesses 836system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054062 # miss rate for StoreCondReq accesses 837system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081990 # miss rate for demand accesses 838system.cpu0.dcache.demand_miss_rate::total 0.081990 # miss rate for demand accesses 839system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085542 # miss rate for overall accesses 840system.cpu0.dcache.overall_miss_rate::total 0.085542 # miss rate for overall accesses 841system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12687.902632 # average ReadReq miss latency 842system.cpu0.dcache.ReadReq_avg_miss_latency::total 12687.902632 # average ReadReq miss latency 843system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13621.575858 # average WriteReq miss latency 844system.cpu0.dcache.WriteReq_avg_miss_latency::total 13621.575858 # average WriteReq miss latency 845system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15828.305373 # average LoadLockedReq miss latency 846system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15828.305373 # average LoadLockedReq miss latency 847system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22020.584465 # average StoreCondReq miss latency 848system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22020.584465 # average StoreCondReq miss latency | 786system.cpu0.dcache.tags.tag_accesses 63487140 # Number of tag accesses 787system.cpu0.dcache.tags.data_accesses 63487140 # Number of data accesses 788system.cpu0.dcache.ReadReq_hits::cpu0.data 15590249 # number of ReadReq hits 789system.cpu0.dcache.ReadReq_hits::total 15590249 # number of ReadReq hits 790system.cpu0.dcache.WriteReq_hits::cpu0.data 12072536 # number of WriteReq hits 791system.cpu0.dcache.WriteReq_hits::total 12072536 # number of WriteReq hits 792system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311110 # number of SoftPFReq hits 793system.cpu0.dcache.SoftPFReq_hits::total 311110 # number of SoftPFReq hits 794system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363193 # number of LoadLockedReq hits 795system.cpu0.dcache.LoadLockedReq_hits::total 363193 # number of LoadLockedReq hits 796system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360660 # number of StoreCondReq hits 797system.cpu0.dcache.StoreCondReq_hits::total 360660 # number of StoreCondReq hits 798system.cpu0.dcache.demand_hits::cpu0.data 27662785 # number of demand (read+write) hits 799system.cpu0.dcache.demand_hits::total 27662785 # number of demand (read+write) hits 800system.cpu0.dcache.overall_hits::cpu0.data 27973895 # number of overall hits 801system.cpu0.dcache.overall_hits::total 27973895 # number of overall hits 802system.cpu0.dcache.ReadReq_misses::cpu0.data 638253 # number of ReadReq misses 803system.cpu0.dcache.ReadReq_misses::total 638253 # number of ReadReq misses 804system.cpu0.dcache.WriteReq_misses::cpu0.data 1832121 # number of WriteReq misses 805system.cpu0.dcache.WriteReq_misses::total 1832121 # number of WriteReq misses 806system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146008 # number of SoftPFReq misses 807system.cpu0.dcache.SoftPFReq_misses::total 146008 # number of SoftPFReq misses 808system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25001 # number of LoadLockedReq misses 809system.cpu0.dcache.LoadLockedReq_misses::total 25001 # number of LoadLockedReq misses 810system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20609 # number of StoreCondReq misses 811system.cpu0.dcache.StoreCondReq_misses::total 20609 # number of StoreCondReq misses 812system.cpu0.dcache.demand_misses::cpu0.data 2470374 # number of demand (read+write) misses 813system.cpu0.dcache.demand_misses::total 2470374 # number of demand (read+write) misses 814system.cpu0.dcache.overall_misses::cpu0.data 2616382 # number of overall misses 815system.cpu0.dcache.overall_misses::total 2616382 # number of overall misses 816system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8112547038 # number of ReadReq miss cycles 817system.cpu0.dcache.ReadReq_miss_latency::total 8112547038 # number of ReadReq miss cycles 818system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24972133492 # number of WriteReq miss cycles 819system.cpu0.dcache.WriteReq_miss_latency::total 24972133492 # number of WriteReq miss cycles 820system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394969003 # number of LoadLockedReq miss cycles 821system.cpu0.dcache.LoadLockedReq_miss_latency::total 394969003 # number of LoadLockedReq miss cycles 822system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454279790 # number of StoreCondReq miss cycles 823system.cpu0.dcache.StoreCondReq_miss_latency::total 454279790 # number of StoreCondReq miss cycles 824system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 381000 # number of StoreCondFailReq miss cycles 825system.cpu0.dcache.StoreCondFailReq_miss_latency::total 381000 # number of StoreCondFailReq miss cycles 826system.cpu0.dcache.demand_miss_latency::cpu0.data 33084680530 # number of demand (read+write) miss cycles 827system.cpu0.dcache.demand_miss_latency::total 33084680530 # number of demand (read+write) miss cycles 828system.cpu0.dcache.overall_miss_latency::cpu0.data 33084680530 # number of overall miss cycles 829system.cpu0.dcache.overall_miss_latency::total 33084680530 # number of overall miss cycles 830system.cpu0.dcache.ReadReq_accesses::cpu0.data 16228502 # number of ReadReq accesses(hits+misses) 831system.cpu0.dcache.ReadReq_accesses::total 16228502 # number of ReadReq accesses(hits+misses) 832system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904657 # number of WriteReq accesses(hits+misses) 833system.cpu0.dcache.WriteReq_accesses::total 13904657 # number of WriteReq accesses(hits+misses) 834system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457118 # number of SoftPFReq accesses(hits+misses) 835system.cpu0.dcache.SoftPFReq_accesses::total 457118 # number of SoftPFReq accesses(hits+misses) 836system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388194 # number of LoadLockedReq accesses(hits+misses) 837system.cpu0.dcache.LoadLockedReq_accesses::total 388194 # number of LoadLockedReq accesses(hits+misses) 838system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381269 # number of StoreCondReq accesses(hits+misses) 839system.cpu0.dcache.StoreCondReq_accesses::total 381269 # number of StoreCondReq accesses(hits+misses) 840system.cpu0.dcache.demand_accesses::cpu0.data 30133159 # number of demand (read+write) accesses 841system.cpu0.dcache.demand_accesses::total 30133159 # number of demand (read+write) accesses 842system.cpu0.dcache.overall_accesses::cpu0.data 30590277 # number of overall (read+write) accesses 843system.cpu0.dcache.overall_accesses::total 30590277 # number of overall (read+write) accesses 844system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039329 # miss rate for ReadReq accesses 845system.cpu0.dcache.ReadReq_miss_rate::total 0.039329 # miss rate for ReadReq accesses 846system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131763 # miss rate for WriteReq accesses 847system.cpu0.dcache.WriteReq_miss_rate::total 0.131763 # miss rate for WriteReq accesses 848system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319410 # miss rate for SoftPFReq accesses 849system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319410 # miss rate for SoftPFReq accesses 850system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064403 # miss rate for LoadLockedReq accesses 851system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064403 # miss rate for LoadLockedReq accesses 852system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054054 # miss rate for StoreCondReq accesses 853system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054054 # miss rate for StoreCondReq accesses 854system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081982 # miss rate for demand accesses 855system.cpu0.dcache.demand_miss_rate::total 0.081982 # miss rate for demand accesses 856system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085530 # miss rate for overall accesses 857system.cpu0.dcache.overall_miss_rate::total 0.085530 # miss rate for overall accesses 858system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.550578 # average ReadReq miss latency 859system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.550578 # average ReadReq miss latency 860system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13630.176987 # average WriteReq miss latency 861system.cpu0.dcache.WriteReq_avg_miss_latency::total 13630.176987 # average WriteReq miss latency 862system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15798.128195 # average LoadLockedReq miss latency 863system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15798.128195 # average LoadLockedReq miss latency 864system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22042.786647 # average StoreCondReq miss latency 865system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22042.786647 # average StoreCondReq miss latency |
| 849system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 850system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 866system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 867system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 851system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13380.328403 # average overall miss latency 852system.cpu0.dcache.demand_avg_miss_latency::total 13380.328403 # average overall miss latency 853system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12633.132552 # average overall miss latency 854system.cpu0.dcache.overall_avg_miss_latency::total 12633.132552 # average overall miss latency 855system.cpu0.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked 856system.cpu0.dcache.blocked_cycles::no_targets 3366874 # number of cycles access was blocked 857system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked 858system.cpu0.dcache.blocked::no_targets 191323 # number of cycles access was blocked 859system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.357143 # average number of cycles each access was blocked 860system.cpu0.dcache.avg_blocked_cycles::no_targets 17.597853 # average number of cycles each access was blocked | 868system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13392.579638 # average overall miss latency 869system.cpu0.dcache.demand_avg_miss_latency::total 13392.579638 # average overall miss latency 870system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12645.202623 # average overall miss latency 871system.cpu0.dcache.overall_avg_miss_latency::total 12645.202623 # average overall miss latency 872system.cpu0.dcache.blocked_cycles::no_mshrs 1345 # number of cycles access was blocked 873system.cpu0.dcache.blocked_cycles::no_targets 3372122 # number of cycles access was blocked 874system.cpu0.dcache.blocked::no_mshrs 71 # number of cycles access was blocked 875system.cpu0.dcache.blocked::no_targets 191319 # number of cycles access was blocked 876system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.943662 # average number of cycles each access was blocked 877system.cpu0.dcache.avg_blocked_cycles::no_targets 17.625651 # average number of cycles each access was blocked |
| 861system.cpu0.dcache.fast_writes 0 # number of fast writes performed 862system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 878system.cpu0.dcache.fast_writes 0 # number of fast writes performed 879system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 863system.cpu0.dcache.writebacks::writebacks 513073 # number of writebacks 864system.cpu0.dcache.writebacks::total 513073 # number of writebacks 865system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248142 # number of ReadReq MSHR hits 866system.cpu0.dcache.ReadReq_mshr_hits::total 248142 # number of ReadReq MSHR hits 867system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519584 # number of WriteReq MSHR hits 868system.cpu0.dcache.WriteReq_mshr_hits::total 1519584 # number of WriteReq MSHR hits 869system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18421 # number of LoadLockedReq MSHR hits 870system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18421 # number of LoadLockedReq MSHR hits 871system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767726 # number of demand (read+write) MSHR hits 872system.cpu0.dcache.demand_mshr_hits::total 1767726 # number of demand (read+write) MSHR hits 873system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767726 # number of overall MSHR hits 874system.cpu0.dcache.overall_mshr_hits::total 1767726 # number of overall MSHR hits 875system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390201 # number of ReadReq MSHR misses 876system.cpu0.dcache.ReadReq_mshr_misses::total 390201 # number of ReadReq MSHR misses 877system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312581 # number of WriteReq MSHR misses 878system.cpu0.dcache.WriteReq_mshr_misses::total 312581 # number of WriteReq MSHR misses 879system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101511 # number of SoftPFReq MSHR misses 880system.cpu0.dcache.SoftPFReq_mshr_misses::total 101511 # number of SoftPFReq MSHR misses 881system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6555 # number of LoadLockedReq MSHR misses 882system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6555 # number of LoadLockedReq MSHR misses 883system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20612 # number of StoreCondReq MSHR misses 884system.cpu0.dcache.StoreCondReq_mshr_misses::total 20612 # number of StoreCondReq MSHR misses 885system.cpu0.dcache.demand_mshr_misses::cpu0.data 702782 # number of demand (read+write) MSHR misses 886system.cpu0.dcache.demand_mshr_misses::total 702782 # number of demand (read+write) MSHR misses 887system.cpu0.dcache.overall_mshr_misses::cpu0.data 804293 # number of overall MSHR misses 888system.cpu0.dcache.overall_mshr_misses::total 804293 # number of overall MSHR misses 889system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170777489 # number of ReadReq MSHR miss cycles 890system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170777489 # number of ReadReq MSHR miss cycles 891system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4999843092 # number of WriteReq MSHR miss cycles 892system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4999843092 # number of WriteReq MSHR miss cycles 893system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1415062493 # number of SoftPFReq MSHR miss cycles 894system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1415062493 # number of SoftPFReq MSHR miss cycles 895system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97847997 # number of LoadLockedReq MSHR miss cycles 896system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97847997 # number of LoadLockedReq MSHR miss cycles 897system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411963713 # number of StoreCondReq MSHR miss cycles 898system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411963713 # number of StoreCondReq MSHR miss cycles 899system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 324500 # number of StoreCondFailReq MSHR miss cycles 900system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 324500 # number of StoreCondFailReq MSHR miss cycles 901system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9170620581 # number of demand (read+write) MSHR miss cycles 902system.cpu0.dcache.demand_mshr_miss_latency::total 9170620581 # number of demand (read+write) MSHR miss cycles 903system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10585683074 # number of overall MSHR miss cycles 904system.cpu0.dcache.overall_mshr_miss_latency::total 10585683074 # number of overall MSHR miss cycles 905system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217063246 # number of ReadReq MSHR uncacheable cycles 906system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217063246 # number of ReadReq MSHR uncacheable cycles 907system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187063995 # number of WriteReq MSHR uncacheable cycles 908system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187063995 # number of WriteReq MSHR uncacheable cycles 909system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404127241 # number of overall MSHR uncacheable cycles 910system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404127241 # number of overall MSHR uncacheable cycles 911system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses 912system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses 913system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022481 # mshr miss rate for WriteReq accesses 914system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022481 # mshr miss rate for WriteReq accesses 915system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222084 # mshr miss rate for SoftPFReq accesses 916system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222084 # mshr miss rate for SoftPFReq accesses 917system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016887 # mshr miss rate for LoadLockedReq accesses 918system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016887 # mshr miss rate for LoadLockedReq accesses 919system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054062 # mshr miss rate for StoreCondReq accesses 920system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054062 # mshr miss rate for StoreCondReq accesses 921system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023324 # mshr miss rate for demand accesses 922system.cpu0.dcache.demand_mshr_miss_rate::total 0.023324 # mshr miss rate for demand accesses 923system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026294 # mshr miss rate for overall accesses 924system.cpu0.dcache.overall_mshr_miss_rate::total 0.026294 # mshr miss rate for overall accesses 925system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10688.792415 # average ReadReq mshr miss latency 926system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10688.792415 # average ReadReq mshr miss latency 927system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15995.351899 # average WriteReq mshr miss latency 928system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15995.351899 # average WriteReq mshr miss latency 929system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13939.991656 # average SoftPFReq mshr miss latency 930system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13939.991656 # average SoftPFReq mshr miss latency 931system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14927.230664 # average LoadLockedReq mshr miss latency 932system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14927.230664 # average LoadLockedReq mshr miss latency 933system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19986.595818 # average StoreCondReq mshr miss latency 934system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19986.595818 # average StoreCondReq mshr miss latency | 880system.cpu0.dcache.writebacks::writebacks 512814 # number of writebacks 881system.cpu0.dcache.writebacks::total 512814 # number of writebacks 882system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248043 # number of ReadReq MSHR hits 883system.cpu0.dcache.ReadReq_mshr_hits::total 248043 # number of ReadReq MSHR hits 884system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519569 # number of WriteReq MSHR hits 885system.cpu0.dcache.WriteReq_mshr_hits::total 1519569 # number of WriteReq MSHR hits 886system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18426 # number of LoadLockedReq MSHR hits 887system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18426 # number of LoadLockedReq MSHR hits 888system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767612 # number of demand (read+write) MSHR hits 889system.cpu0.dcache.demand_mshr_hits::total 1767612 # number of demand (read+write) MSHR hits 890system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767612 # number of overall MSHR hits 891system.cpu0.dcache.overall_mshr_hits::total 1767612 # number of overall MSHR hits 892system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390210 # number of ReadReq MSHR misses 893system.cpu0.dcache.ReadReq_mshr_misses::total 390210 # number of ReadReq MSHR misses 894system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312552 # number of WriteReq MSHR misses 895system.cpu0.dcache.WriteReq_mshr_misses::total 312552 # number of WriteReq MSHR misses 896system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101508 # number of SoftPFReq MSHR misses 897system.cpu0.dcache.SoftPFReq_mshr_misses::total 101508 # number of SoftPFReq MSHR misses 898system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6575 # number of LoadLockedReq MSHR misses 899system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6575 # number of LoadLockedReq MSHR misses 900system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20609 # number of StoreCondReq MSHR misses 901system.cpu0.dcache.StoreCondReq_mshr_misses::total 20609 # number of StoreCondReq MSHR misses 902system.cpu0.dcache.demand_mshr_misses::cpu0.data 702762 # number of demand (read+write) MSHR misses 903system.cpu0.dcache.demand_mshr_misses::total 702762 # number of demand (read+write) MSHR misses 904system.cpu0.dcache.overall_mshr_misses::cpu0.data 804270 # number of overall MSHR misses 905system.cpu0.dcache.overall_mshr_misses::total 804270 # number of overall MSHR misses 906system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4184101504 # number of ReadReq MSHR miss cycles 907system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4184101504 # number of ReadReq MSHR miss cycles 908system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5001279356 # number of WriteReq MSHR miss cycles 909system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5001279356 # number of WriteReq MSHR miss cycles 910system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1410085492 # number of SoftPFReq MSHR miss cycles 911system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1410085492 # number of SoftPFReq MSHR miss cycles 912system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97668747 # number of LoadLockedReq MSHR miss cycles 913system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97668747 # number of LoadLockedReq MSHR miss cycles 914system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 412365210 # number of StoreCondReq MSHR miss cycles 915system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412365210 # number of StoreCondReq MSHR miss cycles 916system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 359000 # number of StoreCondFailReq MSHR miss cycles 917system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 359000 # number of StoreCondFailReq MSHR miss cycles 918system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9185380860 # number of demand (read+write) MSHR miss cycles 919system.cpu0.dcache.demand_mshr_miss_latency::total 9185380860 # number of demand (read+write) MSHR miss cycles 920system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10595466352 # number of overall MSHR miss cycles 921system.cpu0.dcache.overall_mshr_miss_latency::total 10595466352 # number of overall MSHR miss cycles 922system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216928747 # number of ReadReq MSHR uncacheable cycles 923system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216928747 # number of ReadReq MSHR uncacheable cycles 924system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3186876498 # number of WriteReq MSHR uncacheable cycles 925system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3186876498 # number of WriteReq MSHR uncacheable cycles 926system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403805245 # number of overall MSHR uncacheable cycles 927system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403805245 # number of overall MSHR uncacheable cycles 928system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses 929system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses 930system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022478 # mshr miss rate for WriteReq accesses 931system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022478 # mshr miss rate for WriteReq accesses 932system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222061 # mshr miss rate for SoftPFReq accesses 933system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222061 # mshr miss rate for SoftPFReq accesses 934system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses 935system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses 936system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054054 # mshr miss rate for StoreCondReq accesses 937system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054054 # mshr miss rate for StoreCondReq accesses 938system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023322 # mshr miss rate for demand accesses 939system.cpu0.dcache.demand_mshr_miss_rate::total 0.023322 # mshr miss rate for demand accesses 940system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026292 # mshr miss rate for overall accesses 941system.cpu0.dcache.overall_mshr_miss_rate::total 0.026292 # mshr miss rate for overall accesses 942system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10722.691638 # average ReadReq mshr miss latency 943system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10722.691638 # average ReadReq mshr miss latency 944system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16001.431301 # average WriteReq mshr miss latency 945system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16001.431301 # average WriteReq mshr miss latency 946system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13891.373015 # average SoftPFReq mshr miss latency 947system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13891.373015 # average SoftPFReq mshr miss latency 948system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.562281 # average LoadLockedReq mshr miss latency 949system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.562281 # average LoadLockedReq mshr miss latency 950system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20008.986850 # average StoreCondReq mshr miss latency 951system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20008.986850 # average StoreCondReq mshr miss latency |
| 935system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 936system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 952system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 953system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 937system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13049.025987 # average overall mshr miss latency 938system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13049.025987 # average overall mshr miss latency 939system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13161.476072 # average overall mshr miss latency 940system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13161.476072 # average overall mshr miss latency | 954system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13070.400591 # average overall mshr miss latency 955system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13070.400591 # average overall mshr miss latency 956system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13174.016626 # average overall mshr miss latency 957system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13174.016626 # average overall mshr miss latency |
| 941system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 942system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 943system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 944system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 945system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 946system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 947system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 958system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 959system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 960system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 961system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 962system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 963system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 964system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 948system.cpu0.icache.tags.replacements 1263629 # number of replacements 949system.cpu0.icache.tags.tagsinuse 511.774279 # Cycle average of tags in use 950system.cpu0.icache.tags.total_refs 36446507 # Total number of references to valid blocks. 951system.cpu0.icache.tags.sampled_refs 1264141 # Sample count of references to valid blocks. 952system.cpu0.icache.tags.avg_refs 28.831046 # Average number of references to valid blocks. | 965system.cpu0.icache.tags.replacements 1263628 # number of replacements 966system.cpu0.icache.tags.tagsinuse 511.774293 # Cycle average of tags in use 967system.cpu0.icache.tags.total_refs 36451354 # Total number of references to valid blocks. 968system.cpu0.icache.tags.sampled_refs 1264140 # Sample count of references to valid blocks. 969system.cpu0.icache.tags.avg_refs 28.834903 # Average number of references to valid blocks. |
| 953system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. | 970system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. |
| 954system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774279 # Average occupied blocks per requestor | 971system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774293 # Average occupied blocks per requestor |
| 955system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy 956system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy 957system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 972system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy 973system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy 974system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 958system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 959system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id | 975system.cpu0.icache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id 976system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id |
| 960system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id 961system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 977system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id 978system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 962system.cpu0.icache.tags.tag_accesses 76758780 # Number of tag accesses 963system.cpu0.icache.tags.data_accesses 76758780 # Number of data accesses 964system.cpu0.icache.ReadReq_hits::cpu0.inst 36446507 # number of ReadReq hits 965system.cpu0.icache.ReadReq_hits::total 36446507 # number of ReadReq hits 966system.cpu0.icache.demand_hits::cpu0.inst 36446507 # number of demand (read+write) hits 967system.cpu0.icache.demand_hits::total 36446507 # number of demand (read+write) hits 968system.cpu0.icache.overall_hits::cpu0.inst 36446507 # number of overall hits 969system.cpu0.icache.overall_hits::total 36446507 # number of overall hits 970system.cpu0.icache.ReadReq_misses::cpu0.inst 1300794 # number of ReadReq misses 971system.cpu0.icache.ReadReq_misses::total 1300794 # number of ReadReq misses 972system.cpu0.icache.demand_misses::cpu0.inst 1300794 # number of demand (read+write) misses 973system.cpu0.icache.demand_misses::total 1300794 # number of demand (read+write) misses 974system.cpu0.icache.overall_misses::cpu0.inst 1300794 # number of overall misses 975system.cpu0.icache.overall_misses::total 1300794 # number of overall misses 976system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11016728605 # number of ReadReq miss cycles 977system.cpu0.icache.ReadReq_miss_latency::total 11016728605 # number of ReadReq miss cycles 978system.cpu0.icache.demand_miss_latency::cpu0.inst 11016728605 # number of demand (read+write) miss cycles 979system.cpu0.icache.demand_miss_latency::total 11016728605 # number of demand (read+write) miss cycles 980system.cpu0.icache.overall_miss_latency::cpu0.inst 11016728605 # number of overall miss cycles 981system.cpu0.icache.overall_miss_latency::total 11016728605 # number of overall miss cycles 982system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747301 # number of ReadReq accesses(hits+misses) 983system.cpu0.icache.ReadReq_accesses::total 37747301 # number of ReadReq accesses(hits+misses) 984system.cpu0.icache.demand_accesses::cpu0.inst 37747301 # number of demand (read+write) accesses 985system.cpu0.icache.demand_accesses::total 37747301 # number of demand (read+write) accesses 986system.cpu0.icache.overall_accesses::cpu0.inst 37747301 # number of overall (read+write) accesses 987system.cpu0.icache.overall_accesses::total 37747301 # number of overall (read+write) accesses 988system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034461 # miss rate for ReadReq accesses 989system.cpu0.icache.ReadReq_miss_rate::total 0.034461 # miss rate for ReadReq accesses 990system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034461 # miss rate for demand accesses 991system.cpu0.icache.demand_miss_rate::total 0.034461 # miss rate for demand accesses 992system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034461 # miss rate for overall accesses 993system.cpu0.icache.overall_miss_rate::total 0.034461 # miss rate for overall accesses 994system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8469.233872 # average ReadReq miss latency 995system.cpu0.icache.ReadReq_avg_miss_latency::total 8469.233872 # average ReadReq miss latency 996system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency 997system.cpu0.icache.demand_avg_miss_latency::total 8469.233872 # average overall miss latency 998system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency 999system.cpu0.icache.overall_avg_miss_latency::total 8469.233872 # average overall miss latency 1000system.cpu0.icache.blocked_cycles::no_mshrs 724171 # number of cycles access was blocked | 979system.cpu0.icache.tags.tag_accesses 76768570 # Number of tag accesses 980system.cpu0.icache.tags.data_accesses 76768570 # Number of data accesses 981system.cpu0.icache.ReadReq_hits::cpu0.inst 36451354 # number of ReadReq hits 982system.cpu0.icache.ReadReq_hits::total 36451354 # number of ReadReq hits 983system.cpu0.icache.demand_hits::cpu0.inst 36451354 # number of demand (read+write) hits 984system.cpu0.icache.demand_hits::total 36451354 # number of demand (read+write) hits 985system.cpu0.icache.overall_hits::cpu0.inst 36451354 # number of overall hits 986system.cpu0.icache.overall_hits::total 36451354 # number of overall hits 987system.cpu0.icache.ReadReq_misses::cpu0.inst 1300843 # number of ReadReq misses 988system.cpu0.icache.ReadReq_misses::total 1300843 # number of ReadReq misses 989system.cpu0.icache.demand_misses::cpu0.inst 1300843 # number of demand (read+write) misses 990system.cpu0.icache.demand_misses::total 1300843 # number of demand (read+write) misses 991system.cpu0.icache.overall_misses::cpu0.inst 1300843 # number of overall misses 992system.cpu0.icache.overall_misses::total 1300843 # number of overall misses 993system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11016228057 # number of ReadReq miss cycles 994system.cpu0.icache.ReadReq_miss_latency::total 11016228057 # number of ReadReq miss cycles 995system.cpu0.icache.demand_miss_latency::cpu0.inst 11016228057 # number of demand (read+write) miss cycles 996system.cpu0.icache.demand_miss_latency::total 11016228057 # number of demand (read+write) miss cycles 997system.cpu0.icache.overall_miss_latency::cpu0.inst 11016228057 # number of overall miss cycles 998system.cpu0.icache.overall_miss_latency::total 11016228057 # number of overall miss cycles 999system.cpu0.icache.ReadReq_accesses::cpu0.inst 37752197 # number of ReadReq accesses(hits+misses) 1000system.cpu0.icache.ReadReq_accesses::total 37752197 # number of ReadReq accesses(hits+misses) 1001system.cpu0.icache.demand_accesses::cpu0.inst 37752197 # number of demand (read+write) accesses 1002system.cpu0.icache.demand_accesses::total 37752197 # number of demand (read+write) accesses 1003system.cpu0.icache.overall_accesses::cpu0.inst 37752197 # number of overall (read+write) accesses 1004system.cpu0.icache.overall_accesses::total 37752197 # number of overall (read+write) accesses 1005system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034457 # miss rate for ReadReq accesses 1006system.cpu0.icache.ReadReq_miss_rate::total 0.034457 # miss rate for ReadReq accesses 1007system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034457 # miss rate for demand accesses 1008system.cpu0.icache.demand_miss_rate::total 0.034457 # miss rate for demand accesses 1009system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034457 # miss rate for overall accesses 1010system.cpu0.icache.overall_miss_rate::total 0.034457 # miss rate for overall accesses 1011system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.530066 # average ReadReq miss latency 1012system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.530066 # average ReadReq miss latency 1013system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.530066 # average overall miss latency 1014system.cpu0.icache.demand_avg_miss_latency::total 8468.530066 # average overall miss latency 1015system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.530066 # average overall miss latency 1016system.cpu0.icache.overall_avg_miss_latency::total 8468.530066 # average overall miss latency 1017system.cpu0.icache.blocked_cycles::no_mshrs 721640 # number of cycles access was blocked |
| 1001system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked | 1018system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked |
| 1002system.cpu0.icache.blocked::no_mshrs 96135 # number of cycles access was blocked | 1019system.cpu0.icache.blocked::no_mshrs 96102 # number of cycles access was blocked |
| 1003system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked | 1020system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked |
| 1004system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.532855 # average number of cycles each access was blocked | 1021system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.509105 # average number of cycles each access was blocked |
| 1005system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked 1006system.cpu0.icache.fast_writes 0 # number of fast writes performed 1007system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1022system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked 1023system.cpu0.icache.fast_writes 0 # number of fast writes performed 1024system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1008system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36615 # number of ReadReq MSHR hits 1009system.cpu0.icache.ReadReq_mshr_hits::total 36615 # number of ReadReq MSHR hits 1010system.cpu0.icache.demand_mshr_hits::cpu0.inst 36615 # number of demand (read+write) MSHR hits 1011system.cpu0.icache.demand_mshr_hits::total 36615 # number of demand (read+write) MSHR hits 1012system.cpu0.icache.overall_mshr_hits::cpu0.inst 36615 # number of overall MSHR hits 1013system.cpu0.icache.overall_mshr_hits::total 36615 # number of overall MSHR hits 1014system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264179 # number of ReadReq MSHR misses 1015system.cpu0.icache.ReadReq_mshr_misses::total 1264179 # number of ReadReq MSHR misses 1016system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264179 # number of demand (read+write) MSHR misses 1017system.cpu0.icache.demand_mshr_misses::total 1264179 # number of demand (read+write) MSHR misses 1018system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264179 # number of overall MSHR misses 1019system.cpu0.icache.overall_mshr_misses::total 1264179 # number of overall MSHR misses 1020system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8918143809 # number of ReadReq MSHR miss cycles 1021system.cpu0.icache.ReadReq_mshr_miss_latency::total 8918143809 # number of ReadReq MSHR miss cycles 1022system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8918143809 # number of demand (read+write) MSHR miss cycles 1023system.cpu0.icache.demand_mshr_miss_latency::total 8918143809 # number of demand (read+write) MSHR miss cycles 1024system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8918143809 # number of overall MSHR miss cycles 1025system.cpu0.icache.overall_mshr_miss_latency::total 8918143809 # number of overall MSHR miss cycles | 1025system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36666 # number of ReadReq MSHR hits 1026system.cpu0.icache.ReadReq_mshr_hits::total 36666 # number of ReadReq MSHR hits 1027system.cpu0.icache.demand_mshr_hits::cpu0.inst 36666 # number of demand (read+write) MSHR hits 1028system.cpu0.icache.demand_mshr_hits::total 36666 # number of demand (read+write) MSHR hits 1029system.cpu0.icache.overall_mshr_hits::cpu0.inst 36666 # number of overall MSHR hits 1030system.cpu0.icache.overall_mshr_hits::total 36666 # number of overall MSHR hits 1031system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264177 # number of ReadReq MSHR misses 1032system.cpu0.icache.ReadReq_mshr_misses::total 1264177 # number of ReadReq MSHR misses 1033system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264177 # number of demand (read+write) MSHR misses 1034system.cpu0.icache.demand_mshr_misses::total 1264177 # number of demand (read+write) MSHR misses 1035system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264177 # number of overall MSHR misses 1036system.cpu0.icache.overall_mshr_misses::total 1264177 # number of overall MSHR misses 1037system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8917861032 # number of ReadReq MSHR miss cycles 1038system.cpu0.icache.ReadReq_mshr_miss_latency::total 8917861032 # number of ReadReq MSHR miss cycles 1039system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8917861032 # number of demand (read+write) MSHR miss cycles 1040system.cpu0.icache.demand_mshr_miss_latency::total 8917861032 # number of demand (read+write) MSHR miss cycles 1041system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8917861032 # number of overall MSHR miss cycles 1042system.cpu0.icache.overall_mshr_miss_latency::total 8917861032 # number of overall MSHR miss cycles |
| 1026system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles 1027system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles 1028system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles 1029system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles | 1043system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles 1044system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles 1045system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles 1046system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles |
| 1030system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for ReadReq accesses 1031system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033491 # mshr miss rate for ReadReq accesses 1032system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for demand accesses 1033system.cpu0.icache.demand_mshr_miss_rate::total 0.033491 # mshr miss rate for demand accesses 1034system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for overall accesses 1035system.cpu0.icache.overall_mshr_miss_rate::total 0.033491 # mshr miss rate for overall accesses 1036system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average ReadReq mshr miss latency 1037system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.494505 # average ReadReq mshr miss latency 1038system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency 1039system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency 1040system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency 1041system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency | 1047system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for ReadReq accesses 1048system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033486 # mshr miss rate for ReadReq accesses 1049system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for demand accesses 1050system.cpu0.icache.demand_mshr_miss_rate::total 0.033486 # mshr miss rate for demand accesses 1051system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for overall accesses 1052system.cpu0.icache.overall_mshr_miss_rate::total 0.033486 # mshr miss rate for overall accesses 1053system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average ReadReq mshr miss latency 1054system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.281981 # average ReadReq mshr miss latency 1055system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average overall mshr miss latency 1056system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.281981 # average overall mshr miss latency 1057system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average overall mshr miss latency 1058system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.281981 # average overall mshr miss latency |
| 1042system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1043system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1044system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1045system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1046system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1059system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1060system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1061system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1062system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1063system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1047system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11567606 # number of hwpf identified 1048system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525705 # number of hwpf that were already in mshr 1049system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10416149 # number of hwpf that were already in the cache 1050system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118627 # number of hwpf that were already in the prefetch queue | 1064system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11568415 # number of hwpf identified 1065system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525589 # number of hwpf that were already in mshr 1066system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10417206 # number of hwpf that were already in the cache 1067system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118474 # number of hwpf that were already in the prefetch queue |
| 1051system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1068system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1052system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25546 # number of hwpf removed because MSHR allocated 1053system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 481574 # number of hwpf issued 1054system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 882370 # number of hwpf spanning a virtual page | 1069system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25510 # number of hwpf removed because MSHR allocated 1070system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 481631 # number of hwpf issued 1071system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881553 # number of hwpf spanning a virtual page |
| 1055system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1072system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1056system.cpu0.l2cache.tags.replacements 396542 # number of replacements 1057system.cpu0.l2cache.tags.tagsinuse 16205.769061 # Cycle average of tags in use 1058system.cpu0.l2cache.tags.total_refs 2244815 # Total number of references to valid blocks. 1059system.cpu0.l2cache.tags.sampled_refs 412792 # Sample count of references to valid blocks. 1060system.cpu0.l2cache.tags.avg_refs 5.438126 # Average number of references to valid blocks. 1061system.cpu0.l2cache.tags.warmup_cycle 2809084521500 # Cycle when the warmup percentage was hit. 1062system.cpu0.l2cache.tags.occ_blocks::writebacks 4618.987809 # Average occupied blocks per requestor 1063system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.979975 # Average occupied blocks per requestor 1064system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 2.443926 # Average occupied blocks per requestor 1065system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 942.112111 # Average occupied blocks per requestor 1066system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.719068 # Average occupied blocks per requestor 1067system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9222.526172 # Average occupied blocks per requestor 1068system.cpu0.l2cache.tags.occ_percent::writebacks 0.281921 # Average percentage of cache occupancy 1069system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000548 # Average percentage of cache occupancy 1070system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000149 # Average percentage of cache occupancy 1071system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057502 # Average percentage of cache occupancy 1072system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086103 # Average percentage of cache occupancy 1073system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.562898 # Average percentage of cache occupancy 1074system.cpu0.l2cache.tags.occ_percent::total 0.989122 # Average percentage of cache occupancy 1075system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8075 # Occupied blocks per task id 1076system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 1077system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8170 # Occupied blocks per task id 1078system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id 1079system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 189 # Occupied blocks per task id 1080system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3306 # Occupied blocks per task id 1081system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4046 # Occupied blocks per task id 1082system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 488 # Occupied blocks per task id 1083system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1084system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1085system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1086system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 491 # Occupied blocks per task id 1087system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3813 # Occupied blocks per task id 1088system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id 1089system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id 1090system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.492859 # Percentage of cache occupancy per task id 1091system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id 1092system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.498657 # Percentage of cache occupancy per task id 1093system.cpu0.l2cache.tags.tag_accesses 43582688 # Number of tag accesses 1094system.cpu0.l2cache.tags.data_accesses 43582688 # Number of data accesses 1095system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54105 # number of ReadReq hits 1096system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12184 # number of ReadReq hits 1097system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242379 # number of ReadReq hits 1098system.cpu0.l2cache.ReadReq_hits::cpu0.data 407374 # number of ReadReq hits 1099system.cpu0.l2cache.ReadReq_hits::total 1716042 # number of ReadReq hits 1100system.cpu0.l2cache.Writeback_hits::writebacks 513072 # number of Writeback hits 1101system.cpu0.l2cache.Writeback_hits::total 513072 # number of Writeback hits 1102system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15340 # number of UpgradeReq hits 1103system.cpu0.l2cache.UpgradeReq_hits::total 15340 # number of UpgradeReq hits 1104system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2133 # number of SCUpgradeReq hits 1105system.cpu0.l2cache.SCUpgradeReq_hits::total 2133 # number of SCUpgradeReq hits 1106system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216716 # number of ReadExReq hits 1107system.cpu0.l2cache.ReadExReq_hits::total 216716 # number of ReadExReq hits 1108system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54105 # number of demand (read+write) hits 1109system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12184 # number of demand (read+write) hits 1110system.cpu0.l2cache.demand_hits::cpu0.inst 1242379 # number of demand (read+write) hits 1111system.cpu0.l2cache.demand_hits::cpu0.data 624090 # number of demand (read+write) hits 1112system.cpu0.l2cache.demand_hits::total 1932758 # number of demand (read+write) hits 1113system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54105 # number of overall hits 1114system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12184 # number of overall hits 1115system.cpu0.l2cache.overall_hits::cpu0.inst 1242379 # number of overall hits 1116system.cpu0.l2cache.overall_hits::cpu0.data 624090 # number of overall hits 1117system.cpu0.l2cache.overall_hits::total 1932758 # number of overall hits 1118system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 529 # number of ReadReq misses 1119system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 208 # number of ReadReq misses 1120system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21771 # number of ReadReq misses 1121system.cpu0.l2cache.ReadReq_misses::cpu0.data 90784 # number of ReadReq misses 1122system.cpu0.l2cache.ReadReq_misses::total 113292 # number of ReadReq misses 1123system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1124system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 1125system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27958 # number of UpgradeReq misses 1126system.cpu0.l2cache.UpgradeReq_misses::total 27958 # number of UpgradeReq misses 1127system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses 1128system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses 1129system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52756 # number of ReadExReq misses 1130system.cpu0.l2cache.ReadExReq_misses::total 52756 # number of ReadExReq misses 1131system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 529 # number of demand (read+write) misses 1132system.cpu0.l2cache.demand_misses::cpu0.itb.walker 208 # number of demand (read+write) misses 1133system.cpu0.l2cache.demand_misses::cpu0.inst 21771 # number of demand (read+write) misses 1134system.cpu0.l2cache.demand_misses::cpu0.data 143540 # number of demand (read+write) misses 1135system.cpu0.l2cache.demand_misses::total 166048 # number of demand (read+write) misses 1136system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 529 # number of overall misses 1137system.cpu0.l2cache.overall_misses::cpu0.itb.walker 208 # number of overall misses 1138system.cpu0.l2cache.overall_misses::cpu0.inst 21771 # number of overall misses 1139system.cpu0.l2cache.overall_misses::cpu0.data 143540 # number of overall misses 1140system.cpu0.l2cache.overall_misses::total 166048 # number of overall misses 1141system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 13920749 # number of ReadReq miss cycles 1142system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4946000 # number of ReadReq miss cycles 1143system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 810765185 # number of ReadReq miss cycles 1144system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694797858 # number of ReadReq miss cycles 1145system.cpu0.l2cache.ReadReq_miss_latency::total 3524429792 # number of ReadReq miss cycles 1146system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501186435 # number of UpgradeReq miss cycles 1147system.cpu0.l2cache.UpgradeReq_miss_latency::total 501186435 # number of UpgradeReq miss cycles 1148system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362145290 # number of SCUpgradeReq miss cycles 1149system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362145290 # number of SCUpgradeReq miss cycles 1150system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 314500 # number of SCUpgradeFailReq miss cycles 1151system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 314500 # number of SCUpgradeFailReq miss cycles 1152system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2597613271 # number of ReadExReq miss cycles 1153system.cpu0.l2cache.ReadExReq_miss_latency::total 2597613271 # number of ReadExReq miss cycles 1154system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 13920749 # number of demand (read+write) miss cycles 1155system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4946000 # number of demand (read+write) miss cycles 1156system.cpu0.l2cache.demand_miss_latency::cpu0.inst 810765185 # number of demand (read+write) miss cycles 1157system.cpu0.l2cache.demand_miss_latency::cpu0.data 5292411129 # number of demand (read+write) miss cycles 1158system.cpu0.l2cache.demand_miss_latency::total 6122043063 # number of demand (read+write) miss cycles 1159system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 13920749 # number of overall miss cycles 1160system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4946000 # number of overall miss cycles 1161system.cpu0.l2cache.overall_miss_latency::cpu0.inst 810765185 # number of overall miss cycles 1162system.cpu0.l2cache.overall_miss_latency::cpu0.data 5292411129 # number of overall miss cycles 1163system.cpu0.l2cache.overall_miss_latency::total 6122043063 # number of overall miss cycles 1164system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54634 # number of ReadReq accesses(hits+misses) 1165system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12392 # number of ReadReq accesses(hits+misses) 1166system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264150 # number of ReadReq accesses(hits+misses) 1167system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498158 # number of ReadReq accesses(hits+misses) 1168system.cpu0.l2cache.ReadReq_accesses::total 1829334 # number of ReadReq accesses(hits+misses) 1169system.cpu0.l2cache.Writeback_accesses::writebacks 513073 # number of Writeback accesses(hits+misses) 1170system.cpu0.l2cache.Writeback_accesses::total 513073 # number of Writeback accesses(hits+misses) 1171system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43298 # number of UpgradeReq accesses(hits+misses) 1172system.cpu0.l2cache.UpgradeReq_accesses::total 43298 # number of UpgradeReq accesses(hits+misses) 1173system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20612 # number of SCUpgradeReq accesses(hits+misses) 1174system.cpu0.l2cache.SCUpgradeReq_accesses::total 20612 # number of SCUpgradeReq accesses(hits+misses) 1175system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269472 # number of ReadExReq accesses(hits+misses) 1176system.cpu0.l2cache.ReadExReq_accesses::total 269472 # number of ReadExReq accesses(hits+misses) 1177system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54634 # number of demand (read+write) accesses 1178system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12392 # number of demand (read+write) accesses 1179system.cpu0.l2cache.demand_accesses::cpu0.inst 1264150 # number of demand (read+write) accesses 1180system.cpu0.l2cache.demand_accesses::cpu0.data 767630 # number of demand (read+write) accesses 1181system.cpu0.l2cache.demand_accesses::total 2098806 # number of demand (read+write) accesses 1182system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54634 # number of overall (read+write) accesses 1183system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12392 # number of overall (read+write) accesses 1184system.cpu0.l2cache.overall_accesses::cpu0.inst 1264150 # number of overall (read+write) accesses 1185system.cpu0.l2cache.overall_accesses::cpu0.data 767630 # number of overall (read+write) accesses 1186system.cpu0.l2cache.overall_accesses::total 2098806 # number of overall (read+write) accesses 1187system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009683 # miss rate for ReadReq accesses 1188system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016785 # miss rate for ReadReq accesses 1189system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017222 # miss rate for ReadReq accesses 1190system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182239 # miss rate for ReadReq accesses 1191system.cpu0.l2cache.ReadReq_miss_rate::total 0.061931 # miss rate for ReadReq accesses 1192system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses 1193system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses 1194system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645711 # miss rate for UpgradeReq accesses 1195system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645711 # miss rate for UpgradeReq accesses 1196system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.896517 # miss rate for SCUpgradeReq accesses 1197system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.896517 # miss rate for SCUpgradeReq accesses 1198system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195775 # miss rate for ReadExReq accesses 1199system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195775 # miss rate for ReadExReq accesses 1200system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009683 # miss rate for demand accesses 1201system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016785 # miss rate for demand accesses 1202system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017222 # miss rate for demand accesses 1203system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186991 # miss rate for demand accesses 1204system.cpu0.l2cache.demand_miss_rate::total 0.079115 # miss rate for demand accesses 1205system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009683 # miss rate for overall accesses 1206system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016785 # miss rate for overall accesses 1207system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017222 # miss rate for overall accesses 1208system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186991 # miss rate for overall accesses 1209system.cpu0.l2cache.overall_miss_rate::total 0.079115 # miss rate for overall accesses 1210system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26315.215501 # average ReadReq miss latency 1211system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23778.846154 # average ReadReq miss latency 1212system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37240.603785 # average ReadReq miss latency 1213system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29683.621101 # average ReadReq miss latency 1214system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.255658 # average ReadReq miss latency 1215system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17926.405143 # average UpgradeReq miss latency 1216system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17926.405143 # average UpgradeReq miss latency 1217system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19597.667082 # average SCUpgradeReq miss latency 1218system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19597.667082 # average SCUpgradeReq miss latency | 1073system.cpu0.l2cache.tags.replacements 396536 # number of replacements 1074system.cpu0.l2cache.tags.tagsinuse 16205.751344 # Cycle average of tags in use 1075system.cpu0.l2cache.tags.total_refs 2245612 # Total number of references to valid blocks. 1076system.cpu0.l2cache.tags.sampled_refs 412784 # Sample count of references to valid blocks. 1077system.cpu0.l2cache.tags.avg_refs 5.440162 # Average number of references to valid blocks. 1078system.cpu0.l2cache.tags.warmup_cycle 2809249850500 # Cycle when the warmup percentage was hit. 1079system.cpu0.l2cache.tags.occ_blocks::writebacks 4624.087674 # Average occupied blocks per requestor 1080system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 10.817381 # Average occupied blocks per requestor 1081system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.808377 # Average occupied blocks per requestor 1082system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 942.420690 # Average occupied blocks per requestor 1083system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1398.445665 # Average occupied blocks per requestor 1084system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9228.171558 # Average occupied blocks per requestor 1085system.cpu0.l2cache.tags.occ_percent::writebacks 0.282232 # Average percentage of cache occupancy 1086system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000660 # Average percentage of cache occupancy 1087system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy 1088system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057521 # Average percentage of cache occupancy 1089system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.085354 # Average percentage of cache occupancy 1090system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.563243 # Average percentage of cache occupancy 1091system.cpu0.l2cache.tags.occ_percent::total 0.989121 # Average percentage of cache occupancy 1092system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8089 # Occupied blocks per task id 1093system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1094system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8146 # Occupied blocks per task id 1095system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 44 # Occupied blocks per task id 1096system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 199 # Occupied blocks per task id 1097system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3272 # Occupied blocks per task id 1098system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4134 # Occupied blocks per task id 1099system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 440 # Occupied blocks per task id 1100system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 1101system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1102system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1103system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 1104system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 478 # Occupied blocks per task id 1105system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3751 # Occupied blocks per task id 1106system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3581 # Occupied blocks per task id 1107system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 270 # Occupied blocks per task id 1108system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.493713 # Percentage of cache occupancy per task id 1109system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 1110system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.497192 # Percentage of cache occupancy per task id 1111system.cpu0.l2cache.tags.tag_accesses 43591487 # Number of tag accesses 1112system.cpu0.l2cache.tags.data_accesses 43591487 # Number of data accesses 1113system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54584 # number of ReadReq hits 1114system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12527 # number of ReadReq hits 1115system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242350 # number of ReadReq hits 1116system.cpu0.l2cache.ReadReq_hits::cpu0.data 407474 # number of ReadReq hits 1117system.cpu0.l2cache.ReadReq_hits::total 1716935 # number of ReadReq hits 1118system.cpu0.l2cache.Writeback_hits::writebacks 512814 # number of Writeback hits 1119system.cpu0.l2cache.Writeback_hits::total 512814 # number of Writeback hits 1120system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15317 # number of UpgradeReq hits 1121system.cpu0.l2cache.UpgradeReq_hits::total 15317 # number of UpgradeReq hits 1122system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2112 # number of SCUpgradeReq hits 1123system.cpu0.l2cache.SCUpgradeReq_hits::total 2112 # number of SCUpgradeReq hits 1124system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216670 # number of ReadExReq hits 1125system.cpu0.l2cache.ReadExReq_hits::total 216670 # number of ReadExReq hits 1126system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54584 # number of demand (read+write) hits 1127system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12527 # number of demand (read+write) hits 1128system.cpu0.l2cache.demand_hits::cpu0.inst 1242350 # number of demand (read+write) hits 1129system.cpu0.l2cache.demand_hits::cpu0.data 624144 # number of demand (read+write) hits 1130system.cpu0.l2cache.demand_hits::total 1933605 # number of demand (read+write) hits 1131system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54584 # number of overall hits 1132system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12527 # number of overall hits 1133system.cpu0.l2cache.overall_hits::cpu0.inst 1242350 # number of overall hits 1134system.cpu0.l2cache.overall_hits::cpu0.data 624144 # number of overall hits 1135system.cpu0.l2cache.overall_hits::total 1933605 # number of overall hits 1136system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 547 # number of ReadReq misses 1137system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 204 # number of ReadReq misses 1138system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21799 # number of ReadReq misses 1139system.cpu0.l2cache.ReadReq_misses::cpu0.data 90709 # number of ReadReq misses 1140system.cpu0.l2cache.ReadReq_misses::total 113259 # number of ReadReq misses 1141system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27943 # number of UpgradeReq misses 1142system.cpu0.l2cache.UpgradeReq_misses::total 27943 # number of UpgradeReq misses 1143system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18497 # number of SCUpgradeReq misses 1144system.cpu0.l2cache.SCUpgradeReq_misses::total 18497 # number of SCUpgradeReq misses 1145system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52796 # number of ReadExReq misses 1146system.cpu0.l2cache.ReadExReq_misses::total 52796 # number of ReadExReq misses 1147system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 547 # number of demand (read+write) misses 1148system.cpu0.l2cache.demand_misses::cpu0.itb.walker 204 # number of demand (read+write) misses 1149system.cpu0.l2cache.demand_misses::cpu0.inst 21799 # number of demand (read+write) misses 1150system.cpu0.l2cache.demand_misses::cpu0.data 143505 # number of demand (read+write) misses 1151system.cpu0.l2cache.demand_misses::total 166055 # number of demand (read+write) misses 1152system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 547 # number of overall misses 1153system.cpu0.l2cache.overall_misses::cpu0.itb.walker 204 # number of overall misses 1154system.cpu0.l2cache.overall_misses::cpu0.inst 21799 # number of overall misses 1155system.cpu0.l2cache.overall_misses::cpu0.data 143505 # number of overall misses 1156system.cpu0.l2cache.overall_misses::total 166055 # number of overall misses 1157system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14446999 # number of ReadReq miss cycles 1158system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4916500 # number of ReadReq miss cycles 1159system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 810567190 # number of ReadReq miss cycles 1160system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2703489870 # number of ReadReq miss cycles 1161system.cpu0.l2cache.ReadReq_miss_latency::total 3533420559 # number of ReadReq miss cycles 1162system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501086453 # number of UpgradeReq miss cycles 1163system.cpu0.l2cache.UpgradeReq_miss_latency::total 501086453 # number of UpgradeReq miss cycles 1164system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362300280 # number of SCUpgradeReq miss cycles 1165system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362300280 # number of SCUpgradeReq miss cycles 1166system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 348000 # number of SCUpgradeFailReq miss cycles 1167system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 348000 # number of SCUpgradeFailReq miss cycles 1168system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2600330023 # number of ReadExReq miss cycles 1169system.cpu0.l2cache.ReadExReq_miss_latency::total 2600330023 # number of ReadExReq miss cycles 1170system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14446999 # number of demand (read+write) miss cycles 1171system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4916500 # number of demand (read+write) miss cycles 1172system.cpu0.l2cache.demand_miss_latency::cpu0.inst 810567190 # number of demand (read+write) miss cycles 1173system.cpu0.l2cache.demand_miss_latency::cpu0.data 5303819893 # number of demand (read+write) miss cycles 1174system.cpu0.l2cache.demand_miss_latency::total 6133750582 # number of demand (read+write) miss cycles 1175system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14446999 # number of overall miss cycles 1176system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4916500 # number of overall miss cycles 1177system.cpu0.l2cache.overall_miss_latency::cpu0.inst 810567190 # number of overall miss cycles 1178system.cpu0.l2cache.overall_miss_latency::cpu0.data 5303819893 # number of overall miss cycles 1179system.cpu0.l2cache.overall_miss_latency::total 6133750582 # number of overall miss cycles 1180system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55131 # number of ReadReq accesses(hits+misses) 1181system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12731 # number of ReadReq accesses(hits+misses) 1182system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264149 # number of ReadReq accesses(hits+misses) 1183system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498183 # number of ReadReq accesses(hits+misses) 1184system.cpu0.l2cache.ReadReq_accesses::total 1830194 # number of ReadReq accesses(hits+misses) 1185system.cpu0.l2cache.Writeback_accesses::writebacks 512814 # number of Writeback accesses(hits+misses) 1186system.cpu0.l2cache.Writeback_accesses::total 512814 # number of Writeback accesses(hits+misses) 1187system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43260 # number of UpgradeReq accesses(hits+misses) 1188system.cpu0.l2cache.UpgradeReq_accesses::total 43260 # number of UpgradeReq accesses(hits+misses) 1189system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20609 # number of SCUpgradeReq accesses(hits+misses) 1190system.cpu0.l2cache.SCUpgradeReq_accesses::total 20609 # number of SCUpgradeReq accesses(hits+misses) 1191system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269466 # number of ReadExReq accesses(hits+misses) 1192system.cpu0.l2cache.ReadExReq_accesses::total 269466 # number of ReadExReq accesses(hits+misses) 1193system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55131 # number of demand (read+write) accesses 1194system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12731 # number of demand (read+write) accesses 1195system.cpu0.l2cache.demand_accesses::cpu0.inst 1264149 # number of demand (read+write) accesses 1196system.cpu0.l2cache.demand_accesses::cpu0.data 767649 # number of demand (read+write) accesses 1197system.cpu0.l2cache.demand_accesses::total 2099660 # number of demand (read+write) accesses 1198system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55131 # number of overall (read+write) accesses 1199system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12731 # number of overall (read+write) accesses 1200system.cpu0.l2cache.overall_accesses::cpu0.inst 1264149 # number of overall (read+write) accesses 1201system.cpu0.l2cache.overall_accesses::cpu0.data 767649 # number of overall (read+write) accesses 1202system.cpu0.l2cache.overall_accesses::total 2099660 # number of overall (read+write) accesses 1203system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009922 # miss rate for ReadReq accesses 1204system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016024 # miss rate for ReadReq accesses 1205system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017244 # miss rate for ReadReq accesses 1206system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182080 # miss rate for ReadReq accesses 1207system.cpu0.l2cache.ReadReq_miss_rate::total 0.061884 # miss rate for ReadReq accesses 1208system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645932 # miss rate for UpgradeReq accesses 1209system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645932 # miss rate for UpgradeReq accesses 1210system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.897521 # miss rate for SCUpgradeReq accesses 1211system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.897521 # miss rate for SCUpgradeReq accesses 1212system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195928 # miss rate for ReadExReq accesses 1213system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195928 # miss rate for ReadExReq accesses 1214system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009922 # miss rate for demand accesses 1215system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016024 # miss rate for demand accesses 1216system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017244 # miss rate for demand accesses 1217system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186941 # miss rate for demand accesses 1218system.cpu0.l2cache.demand_miss_rate::total 0.079087 # miss rate for demand accesses 1219system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009922 # miss rate for overall accesses 1220system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016024 # miss rate for overall accesses 1221system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017244 # miss rate for overall accesses 1222system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186941 # miss rate for overall accesses 1223system.cpu0.l2cache.overall_miss_rate::total 0.079087 # miss rate for overall accesses 1224system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26411.332724 # average ReadReq miss latency 1225system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24100.490196 # average ReadReq miss latency 1226system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.686866 # average ReadReq miss latency 1227system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29803.987146 # average ReadReq miss latency 1228system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31197.702249 # average ReadReq miss latency 1229system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17932.450095 # average UpgradeReq miss latency 1230system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17932.450095 # average UpgradeReq miss latency 1231system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19586.975185 # average SCUpgradeReq miss latency 1232system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19586.975185 # average SCUpgradeReq miss latency |
| 1219system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1220system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 1233system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1234system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 1221system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49238.252919 # average ReadExReq miss latency 1222system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49238.252919 # average ReadExReq miss latency 1223system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26315.215501 # average overall miss latency 1224system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23778.846154 # average overall miss latency 1225system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37240.603785 # average overall miss latency 1226system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36870.636262 # average overall miss latency 1227system.cpu0.l2cache.demand_avg_miss_latency::total 36869.116539 # average overall miss latency 1228system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26315.215501 # average overall miss latency 1229system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23778.846154 # average overall miss latency 1230system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37240.603785 # average overall miss latency 1231system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36870.636262 # average overall miss latency 1232system.cpu0.l2cache.overall_avg_miss_latency::total 36869.116539 # average overall miss latency 1233system.cpu0.l2cache.blocked_cycles::no_mshrs 65149 # number of cycles access was blocked | 1235system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49252.405921 # average ReadExReq miss latency 1236system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49252.405921 # average ReadExReq miss latency 1237system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26411.332724 # average overall miss latency 1238system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24100.490196 # average overall miss latency 1239system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.686866 # average overall miss latency 1240system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36959.129598 # average overall miss latency 1241system.cpu0.l2cache.demand_avg_miss_latency::total 36938.066195 # average overall miss latency 1242system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26411.332724 # average overall miss latency 1243system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24100.490196 # average overall miss latency 1244system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.686866 # average overall miss latency 1245system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36959.129598 # average overall miss latency 1246system.cpu0.l2cache.overall_avg_miss_latency::total 36938.066195 # average overall miss latency 1247system.cpu0.l2cache.blocked_cycles::no_mshrs 63742 # number of cycles access was blocked |
| 1234system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1248system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1235system.cpu0.l2cache.blocked::no_mshrs 1474 # number of cycles access was blocked | 1249system.cpu0.l2cache.blocked::no_mshrs 1448 # number of cycles access was blocked |
| 1236system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1250system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1237system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.198779 # average number of cycles each access was blocked | 1251system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.020718 # average number of cycles each access was blocked |
| 1238system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1239system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1240system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1252system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1253system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1254system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1241system.cpu0.l2cache.writebacks::writebacks 211864 # number of writebacks 1242system.cpu0.l2cache.writebacks::total 211864 # number of writebacks | 1255system.cpu0.l2cache.writebacks::writebacks 211838 # number of writebacks 1256system.cpu0.l2cache.writebacks::total 211838 # number of writebacks |
| 1243system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits | 1257system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits |
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| 1249system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits | 1263system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits |
| 1250system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5535 # number of demand (read+write) MSHR hits 1251system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11985 # number of demand (read+write) MSHR hits 1252system.cpu0.l2cache.demand_mshr_hits::total 17521 # number of demand (read+write) MSHR hits | 1264system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5563 # number of demand (read+write) MSHR hits 1265system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12011 # number of demand (read+write) MSHR hits 1266system.cpu0.l2cache.demand_mshr_hits::total 17575 # number of demand (read+write) MSHR hits |
| 1253system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits | 1267system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits |
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| 1259system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16236 # number of ReadReq MSHR misses | 1273system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16236 # number of ReadReq MSHR misses |
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| 1274system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16236 # number of demand (read+write) MSHR misses | 1286system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16236 # number of demand (read+write) MSHR misses |
| 1275system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131555 # number of demand (read+write) MSHR misses 1276system.cpu0.l2cache.demand_mshr_misses::total 148527 # number of demand (read+write) MSHR misses 1277system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 529 # number of overall MSHR misses 1278system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 207 # number of overall MSHR misses | 1287system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131494 # number of demand (read+write) MSHR misses 1288system.cpu0.l2cache.demand_mshr_misses::total 148480 # number of demand (read+write) MSHR misses 1289system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 547 # number of overall MSHR misses 1290system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 203 # number of overall MSHR misses |
| 1279system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16236 # number of overall MSHR misses | 1291system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16236 # number of overall MSHR misses |
| 1280system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131555 # number of overall MSHR misses 1281system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 481571 # number of overall MSHR misses 1282system.cpu0.l2cache.overall_mshr_misses::total 630098 # number of overall MSHR misses 1283system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10212251 # number of ReadReq MSHR miss cycles 1284system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3484000 # number of ReadReq MSHR miss cycles 1285system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 587444763 # number of ReadReq MSHR miss cycles 1286system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2008905945 # number of ReadReq MSHR miss cycles 1287system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2610046959 # number of ReadReq MSHR miss cycles 1288system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21960966186 # number of HardPFReq MSHR miss cycles 1289system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21960966186 # number of HardPFReq MSHR miss cycles 1290system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 481827867 # number of UpgradeReq MSHR miss cycles 1291system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481827867 # number of UpgradeReq MSHR miss cycles 1292system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249217743 # number of SCUpgradeReq MSHR miss cycles 1293system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249217743 # number of SCUpgradeReq MSHR miss cycles 1294system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 244500 # number of SCUpgradeFailReq MSHR miss cycles 1295system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 244500 # number of SCUpgradeFailReq MSHR miss cycles 1296system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1317766861 # number of ReadExReq MSHR miss cycles 1297system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1317766861 # number of ReadExReq MSHR miss cycles 1298system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10212251 # number of demand (read+write) MSHR miss cycles 1299system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3484000 # number of demand (read+write) MSHR miss cycles 1300system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 587444763 # number of demand (read+write) MSHR miss cycles 1301system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3326672806 # number of demand (read+write) MSHR miss cycles 1302system.cpu0.l2cache.demand_mshr_miss_latency::total 3927813820 # number of demand (read+write) MSHR miss cycles 1303system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10212251 # number of overall MSHR miss cycles 1304system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3484000 # number of overall MSHR miss cycles 1305system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 587444763 # number of overall MSHR miss cycles 1306system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3326672806 # number of overall MSHR miss cycles 1307system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21960966186 # number of overall MSHR miss cycles 1308system.cpu0.l2cache.overall_mshr_miss_latency::total 25888780006 # number of overall MSHR miss cycles | 1292system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131494 # number of overall MSHR misses 1293system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 481628 # number of overall MSHR misses 1294system.cpu0.l2cache.overall_mshr_misses::total 630108 # number of overall MSHR misses 1295system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10612999 # number of ReadReq MSHR miss cycles 1296system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3482500 # number of ReadReq MSHR miss cycles 1297system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 588277257 # number of ReadReq MSHR miss cycles 1298system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2016263953 # number of ReadReq MSHR miss cycles 1299system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2618636709 # number of ReadReq MSHR miss cycles 1300system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21954581331 # number of HardPFReq MSHR miss cycles 1301system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21954581331 # number of HardPFReq MSHR miss cycles 1302system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 482225838 # number of UpgradeReq MSHR miss cycles 1303system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 482225838 # number of UpgradeReq MSHR miss cycles 1304system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249631743 # number of SCUpgradeReq MSHR miss cycles 1305system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249631743 # number of SCUpgradeReq MSHR miss cycles 1306system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 271000 # number of SCUpgradeFailReq MSHR miss cycles 1307system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 271000 # number of SCUpgradeFailReq MSHR miss cycles 1308system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1320074621 # number of ReadExReq MSHR miss cycles 1309system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1320074621 # number of ReadExReq MSHR miss cycles 1310system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10612999 # number of demand (read+write) MSHR miss cycles 1311system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3482500 # number of demand (read+write) MSHR miss cycles 1312system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 588277257 # number of demand (read+write) MSHR miss cycles 1313system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3336338574 # number of demand (read+write) MSHR miss cycles 1314system.cpu0.l2cache.demand_mshr_miss_latency::total 3938711330 # number of demand (read+write) MSHR miss cycles 1315system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10612999 # number of overall MSHR miss cycles 1316system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3482500 # number of overall MSHR miss cycles 1317system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 588277257 # number of overall MSHR miss cycles 1318system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3336338574 # number of overall MSHR miss cycles 1319system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21954581331 # number of overall MSHR miss cycles 1320system.cpu0.l2cache.overall_mshr_miss_latency::total 25893292661 # number of overall MSHR miss cycles |
| 1309system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles | 1321system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles |
| 1310system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053860233 # number of ReadReq MSHR uncacheable cycles 1311system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272573983 # number of ReadReq MSHR uncacheable cycles 1312system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040265950 # number of WriteReq MSHR uncacheable cycles 1313system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040265950 # number of WriteReq MSHR uncacheable cycles | 1322system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053750231 # number of ReadReq MSHR uncacheable cycles 1323system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272463981 # number of ReadReq MSHR uncacheable cycles 1324system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040098947 # number of WriteReq MSHR uncacheable cycles 1325system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040098947 # number of WriteReq MSHR uncacheable cycles |
| 1314system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles | 1326system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles |
| 1315system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7094126183 # number of overall MSHR uncacheable cycles 1316system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312839933 # number of overall MSHR uncacheable cycles 1317system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for ReadReq accesses 1318system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for ReadReq accesses | 1327system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7093849178 # number of overall MSHR uncacheable cycles 1328system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312562928 # number of overall MSHR uncacheable cycles 1329system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for ReadReq accesses 1330system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for ReadReq accesses |
| 1319system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for ReadReq accesses | 1331system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for ReadReq accesses |
| 1320system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175860 # mshr miss rate for ReadReq accesses 1321system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057167 # mshr miss rate for ReadReq accesses 1322system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses 1323system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses | 1332system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175694 # mshr miss rate for ReadReq accesses 1333system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057105 # mshr miss rate for ReadReq accesses |
| 1324system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1325system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1334system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1335system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1326system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645711 # mshr miss rate for UpgradeReq accesses 1327system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645711 # mshr miss rate for UpgradeReq accesses 1328system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896517 # mshr miss rate for SCUpgradeReq accesses 1329system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896517 # mshr miss rate for SCUpgradeReq accesses 1330system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163093 # mshr miss rate for ReadExReq accesses 1331system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163093 # mshr miss rate for ReadExReq accesses 1332system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for demand accesses 1333system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for demand accesses | 1336system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645932 # mshr miss rate for UpgradeReq accesses 1337system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645932 # mshr miss rate for UpgradeReq accesses 1338system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.897521 # mshr miss rate for SCUpgradeReq accesses 1339system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.897521 # mshr miss rate for SCUpgradeReq accesses 1340system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163160 # mshr miss rate for ReadExReq accesses 1341system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163160 # mshr miss rate for ReadExReq accesses 1342system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for demand accesses 1343system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for demand accesses |
| 1334system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for demand accesses | 1344system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for demand accesses |
| 1335system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171378 # mshr miss rate for demand accesses 1336system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070767 # mshr miss rate for demand accesses 1337system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for overall accesses 1338system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for overall accesses | 1345system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171294 # mshr miss rate for demand accesses 1346system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses 1347system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for overall accesses 1348system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for overall accesses |
| 1339system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for overall accesses | 1349system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for overall accesses |
| 1340system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171378 # mshr miss rate for overall accesses | 1350system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171294 # mshr miss rate for overall accesses |
| 1341system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1351system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1342system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300217 # mshr miss rate for overall accesses 1343system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average ReadReq mshr miss latency 1344system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average ReadReq mshr miss latency 1345system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average ReadReq mshr miss latency 1346system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22931.145641 # average ReadReq mshr miss latency 1347system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24957.897062 # average ReadReq mshr miss latency 1348system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858 # average HardPFReq mshr miss latency 1349system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45602.758858 # average HardPFReq mshr miss latency 1350system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17233.989091 # average UpgradeReq mshr miss latency 1351system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17233.989091 # average UpgradeReq mshr miss latency 1352system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13486.538395 # average SCUpgradeReq mshr miss latency 1353system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13486.538395 # average SCUpgradeReq mshr miss latency | 1352system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300100 # mshr miss rate for overall accesses 1353system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average ReadReq mshr miss latency 1354system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average ReadReq mshr miss latency 1355system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average ReadReq mshr miss latency 1356system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23035.645199 # average ReadReq mshr miss latency 1357system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25055.367788 # average ReadReq mshr miss latency 1358system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017 # average HardPFReq mshr miss latency 1359system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45584.105017 # average HardPFReq mshr miss latency 1360system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.482661 # average UpgradeReq mshr miss latency 1361system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.482661 # average UpgradeReq mshr miss latency 1362system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13495.796237 # average SCUpgradeReq mshr miss latency 1363system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13495.796237 # average SCUpgradeReq mshr miss latency |
| 1354system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1355system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 1364system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1365system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 1356system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29984.001024 # average ReadExReq mshr miss latency 1357system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29984.001024 # average ReadExReq mshr miss latency 1358system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average overall mshr miss latency 1359system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average overall mshr miss latency 1360system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average overall mshr miss latency 1361system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25287.315617 # average overall mshr miss latency 1362system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26445.116511 # average overall mshr miss latency 1363system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average overall mshr miss latency 1364system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average overall mshr miss latency 1365system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average overall mshr miss latency 1366system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25287.315617 # average overall mshr miss latency 1367system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858 # average overall mshr miss latency 1368system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41086.910300 # average overall mshr miss latency | 1366system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 30024.896989 # average ReadExReq mshr miss latency 1367system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 30024.896989 # average ReadExReq mshr miss latency 1368system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average overall mshr miss latency 1369system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average overall mshr miss latency 1370system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average overall mshr miss latency 1371system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25372.553683 # average overall mshr miss latency 1372system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26526.881263 # average overall mshr miss latency 1373system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average overall mshr miss latency 1374system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average overall mshr miss latency 1375system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average overall mshr miss latency 1376system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25372.553683 # average overall mshr miss latency 1377system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017 # average overall mshr miss latency 1378system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41093.419955 # average overall mshr miss latency |
| 1369system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1370system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1371system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1372system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1373system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1374system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1375system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1376system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1377system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1379system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1380system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1381system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1382system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1383system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1384system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1385system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1386system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1387system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1378system.cpu0.toL2Bus.trans_dist::ReadReq 2021884 # Transaction distribution 1379system.cpu0.toL2Bus.trans_dist::ReadResp 1920690 # Transaction distribution 1380system.cpu0.toL2Bus.trans_dist::WriteReq 19107 # Transaction distribution 1381system.cpu0.toL2Bus.trans_dist::WriteResp 19107 # Transaction distribution 1382system.cpu0.toL2Bus.trans_dist::Writeback 513073 # Transaction distribution 1383system.cpu0.toL2Bus.trans_dist::HardPFReq 646583 # Transaction distribution 1384system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution 1385system.cpu0.toL2Bus.trans_dist::UpgradeReq 80962 # Transaction distribution 1386system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43193 # Transaction distribution 1387system.cpu0.toL2Bus.trans_dist::UpgradeResp 104964 # Transaction distribution | 1388system.cpu0.toL2Bus.trans_dist::ReadReq 2021847 # Transaction distribution 1389system.cpu0.toL2Bus.trans_dist::ReadResp 1920670 # Transaction distribution 1390system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution 1391system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution 1392system.cpu0.toL2Bus.trans_dist::Writeback 512814 # Transaction distribution 1393system.cpu0.toL2Bus.trans_dist::HardPFReq 646384 # Transaction distribution 1394system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1395system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution 1396system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43154 # Transaction distribution 1397system.cpu0.toL2Bus.trans_dist::UpgradeResp 104914 # Transaction distribution |
| 1388system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution | 1398system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution |
| 1389system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 1390system.cpu0.toL2Bus.trans_dist::ReadExReq 291894 # Transaction distribution 1391system.cpu0.toL2Bus.trans_dist::ReadExResp 281156 # Transaction distribution 1392system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534332 # Packet count per connected master and slave (bytes) 1393system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360691 # Packet count per connected master and slave (bytes) 1394system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28712 # Packet count per connected master and slave (bytes) 1395system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120464 # Packet count per connected master and slave (bytes) 1396system.cpu0.toL2Bus.pkt_count::total 5044199 # Packet count per connected master and slave (bytes) 1397system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953568 # Cumulative packet size per connected master and slave (bytes) 1398system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86204446 # Cumulative packet size per connected master and slave (bytes) 1399system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49568 # Cumulative packet size per connected master and slave (bytes) 1400system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218536 # Cumulative packet size per connected master and slave (bytes) 1401system.cpu0.toL2Bus.pkt_size::total 167426118 # Cumulative packet size per connected master and slave (bytes) 1402system.cpu0.toL2Bus.snoops 1040274 # Total snoops (count) 1403system.cpu0.toL2Bus.snoop_fanout::samples 3610797 # Request fanout histogram 1404system.cpu0.toL2Bus.snoop_fanout::mean 5.254659 # Request fanout histogram 1405system.cpu0.toL2Bus.snoop_fanout::stdev 0.435670 # Request fanout histogram | 1399system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution 1400system.cpu0.toL2Bus.trans_dist::ReadExReq 291875 # Transaction distribution 1401system.cpu0.toL2Bus.trans_dist::ReadExResp 281146 # Transaction distribution 1402system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534329 # Packet count per connected master and slave (bytes) 1403system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360353 # Packet count per connected master and slave (bytes) 1404system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29069 # Packet count per connected master and slave (bytes) 1405system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120916 # Packet count per connected master and slave (bytes) 1406system.cpu0.toL2Bus.pkt_count::total 5044667 # Packet count per connected master and slave (bytes) 1407system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953504 # Cumulative packet size per connected master and slave (bytes) 1408system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86188042 # Cumulative packet size per connected master and slave (bytes) 1409system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50924 # Cumulative packet size per connected master and slave (bytes) 1410system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 220524 # Cumulative packet size per connected master and slave (bytes) 1411system.cpu0.toL2Bus.pkt_size::total 167412994 # Cumulative packet size per connected master and slave (bytes) 1412system.cpu0.toL2Bus.snoops 1039110 # Total snoops (count) 1413system.cpu0.toL2Bus.snoop_fanout::samples 3610193 # Request fanout histogram 1414system.cpu0.toL2Bus.snoop_fanout::mean 5.254626 # Request fanout histogram 1415system.cpu0.toL2Bus.snoop_fanout::stdev 0.435651 # Request fanout histogram |
| 1406system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1407system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1408system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1409system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1410system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1411system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1416system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1417system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1418system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1419system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1420system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1421system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1412system.cpu0.toL2Bus.snoop_fanout::5 2691274 74.53% 74.53% # Request fanout histogram 1413system.cpu0.toL2Bus.snoop_fanout::6 919523 25.47% 100.00% # Request fanout histogram | 1422system.cpu0.toL2Bus.snoop_fanout::5 2690945 74.54% 74.54% # Request fanout histogram 1423system.cpu0.toL2Bus.snoop_fanout::6 919248 25.46% 100.00% # Request fanout histogram |
| 1414system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1415system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1416system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1424system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1425system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1426system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1417system.cpu0.toL2Bus.snoop_fanout::total 3610797 # Request fanout histogram 1418system.cpu0.toL2Bus.reqLayer0.occupancy 1890423984 # Layer occupancy (ticks) | 1427system.cpu0.toL2Bus.snoop_fanout::total 3610193 # Request fanout histogram 1428system.cpu0.toL2Bus.reqLayer0.occupancy 1889992000 # Layer occupancy (ticks) |
| 1419system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1429system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1420system.cpu0.toL2Bus.snoopLayer0.occupancy 117333499 # Layer occupancy (ticks) | 1430system.cpu0.toL2Bus.snoopLayer0.occupancy 117303500 # Layer occupancy (ticks) |
| 1421system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1431system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1422system.cpu0.toL2Bus.respLayer0.occupancy 1901305348 # Layer occupancy (ticks) | 1432system.cpu0.toL2Bus.respLayer0.occupancy 1901297082 # Layer occupancy (ticks) |
| 1423system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1433system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1424system.cpu0.toL2Bus.respLayer1.occupancy 1220101128 # Layer occupancy (ticks) | 1434system.cpu0.toL2Bus.respLayer1.occupancy 1220075844 # Layer occupancy (ticks) |
| 1425system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1435system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1426system.cpu0.toL2Bus.respLayer2.occupancy 16329482 # Layer occupancy (ticks) | 1436system.cpu0.toL2Bus.respLayer2.occupancy 16351973 # Layer occupancy (ticks) |
| 1427system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1437system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1428system.cpu0.toL2Bus.respLayer3.occupancy 65866183 # Layer occupancy (ticks) | 1438system.cpu0.toL2Bus.respLayer3.occupancy 65816442 # Layer occupancy (ticks) |
| 1429system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1439system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1430system.cpu1.branchPred.lookups 33911271 # Number of BP lookups 1431system.cpu1.branchPred.condPredicted 11563003 # Number of conditional branches predicted 1432system.cpu1.branchPred.condIncorrect 305102 # Number of conditional branches incorrect 1433system.cpu1.branchPred.BTBLookups 18755199 # Number of BTB lookups 1434system.cpu1.branchPred.BTBHits 14959397 # Number of BTB hits | 1440system.cpu1.branchPred.lookups 33910806 # Number of BP lookups 1441system.cpu1.branchPred.condPredicted 11562772 # Number of conditional branches predicted 1442system.cpu1.branchPred.condIncorrect 305112 # Number of conditional branches incorrect 1443system.cpu1.branchPred.BTBLookups 18755942 # Number of BTB lookups 1444system.cpu1.branchPred.BTBHits 14959399 # Number of BTB hits |
| 1435system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1445system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1436system.cpu1.branchPred.BTBHitPct 79.761334 # BTB Hit Percentage 1437system.cpu1.branchPred.usedRAS 12490268 # Number of times the RAS was used to get a target. 1438system.cpu1.branchPred.RASInCorrect 7230 # Number of incorrect RAS predictions. | 1446system.cpu1.branchPred.BTBHitPct 79.758185 # BTB Hit Percentage 1447system.cpu1.branchPred.usedRAS 12490105 # Number of times the RAS was used to get a target. 1448system.cpu1.branchPred.RASInCorrect 7221 # Number of incorrect RAS predictions. |
| 1439system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1440system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1441system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1442system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1443system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1444system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1445system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1446system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1454system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1455system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1456system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1457system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1458system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1459system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1460system.cpu1.dtb.inst_hits 0 # ITB inst hits 1461system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1449system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1450system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1451system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1452system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1453system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1454system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1455system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1456system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1464system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1465system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1466system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1467system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1468system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1469system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1470system.cpu1.dtb.inst_hits 0 # ITB inst hits 1471system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1462system.cpu1.dtb.read_hits 10163694 # DTB read hits 1463system.cpu1.dtb.read_misses 18763 # DTB read misses 1464system.cpu1.dtb.write_hits 6542250 # DTB write hits 1465system.cpu1.dtb.write_misses 2833 # DTB write misses | 1472system.cpu1.dtb.read_hits 10163643 # DTB read hits 1473system.cpu1.dtb.read_misses 18794 # DTB read misses 1474system.cpu1.dtb.write_hits 6541990 # DTB write hits 1475system.cpu1.dtb.write_misses 2867 # DTB write misses |
| 1466system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1467system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1468system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1469system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1476system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1477system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1478system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1479system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1470system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB 1471system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions | 1480system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB 1481system.cpu1.dtb.align_faults 58 # Number of TLB faults due to alignment restrictions |
| 1472system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch 1473system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1482system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch 1483system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1474system.cpu1.dtb.perms_faults 411 # Number of TLB faults due to permissions restrictions 1475system.cpu1.dtb.read_accesses 10182457 # DTB read accesses 1476system.cpu1.dtb.write_accesses 6545083 # DTB write accesses | 1484system.cpu1.dtb.perms_faults 409 # Number of TLB faults due to permissions restrictions 1485system.cpu1.dtb.read_accesses 10182437 # DTB read accesses 1486system.cpu1.dtb.write_accesses 6544857 # DTB write accesses |
| 1477system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1487system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1478system.cpu1.dtb.hits 16705944 # DTB hits 1479system.cpu1.dtb.misses 21596 # DTB misses 1480system.cpu1.dtb.accesses 16727540 # DTB accesses | 1488system.cpu1.dtb.hits 16705633 # DTB hits 1489system.cpu1.dtb.misses 21661 # DTB misses 1490system.cpu1.dtb.accesses 16727294 # DTB accesses |
| 1481system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1482system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1483system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1484system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1485system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1486system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1487system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1488system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1494system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1495system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1496system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1497system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1498system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1499system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1500system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1501system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1491system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1492system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1493system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1494system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1495system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1496system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1497system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1498system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1504system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1505system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1506system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1507system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1508system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1509system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1510system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1511system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1502system.cpu1.itb.inst_hits 43642438 # ITB inst hits 1503system.cpu1.itb.inst_misses 7000 # ITB inst misses | 1512system.cpu1.itb.inst_hits 43641889 # ITB inst hits 1513system.cpu1.itb.inst_misses 7003 # ITB inst misses |
| 1504system.cpu1.itb.read_hits 0 # DTB read hits 1505system.cpu1.itb.read_misses 0 # DTB read misses 1506system.cpu1.itb.write_hits 0 # DTB write hits 1507system.cpu1.itb.write_misses 0 # DTB write misses 1508system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1509system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1510system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1511system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1512system.cpu1.itb.flush_entries 1205 # Number of entries that have been flushed from TLB 1513system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1514system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1515system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1514system.cpu1.itb.read_hits 0 # DTB read hits 1515system.cpu1.itb.read_misses 0 # DTB read misses 1516system.cpu1.itb.write_hits 0 # DTB write hits 1517system.cpu1.itb.write_misses 0 # DTB write misses 1518system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1519system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1520system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1521system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1522system.cpu1.itb.flush_entries 1205 # Number of entries that have been flushed from TLB 1523system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1524system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1525system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1516system.cpu1.itb.perms_faults 538 # Number of TLB faults due to permissions restrictions | 1526system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions |
| 1517system.cpu1.itb.read_accesses 0 # DTB read accesses 1518system.cpu1.itb.write_accesses 0 # DTB write accesses | 1527system.cpu1.itb.read_accesses 0 # DTB read accesses 1528system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1519system.cpu1.itb.inst_accesses 43649438 # ITB inst accesses 1520system.cpu1.itb.hits 43642438 # DTB hits 1521system.cpu1.itb.misses 7000 # DTB misses 1522system.cpu1.itb.accesses 43649438 # DTB accesses 1523system.cpu1.numCycles 104622324 # number of cpu cycles simulated | 1529system.cpu1.itb.inst_accesses 43648892 # ITB inst accesses 1530system.cpu1.itb.hits 43641889 # DTB hits 1531system.cpu1.itb.misses 7003 # DTB misses 1532system.cpu1.itb.accesses 43648892 # DTB accesses 1533system.cpu1.numCycles 104622935 # number of cpu cycles simulated |
| 1524system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1525system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1534system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1535system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1526system.cpu1.fetch.icacheStallCycles 9983715 # Number of cycles fetch is stalled on an Icache miss 1527system.cpu1.fetch.Insts 109168018 # Number of instructions fetch has processed 1528system.cpu1.fetch.Branches 33911271 # Number of branches that fetch encountered 1529system.cpu1.fetch.predictedBranches 27449665 # Number of branches that fetch has predicted taken 1530system.cpu1.fetch.Cycles 91793931 # Number of cycles fetch has run and was not squashing or blocked 1531system.cpu1.fetch.SquashCycles 3775602 # Number of cycles fetch has spent squashing 1532system.cpu1.fetch.TlbCycles 78298 # Number of cycles fetch has spent waiting for tlb 1533system.cpu1.fetch.MiscStallCycles 31640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1534system.cpu1.fetch.PendingTrapStallCycles 200637 # Number of stall cycles due to pending traps 1535system.cpu1.fetch.PendingQuiesceStallCycles 294928 # Number of stall cycles due to pending quiesce instructions 1536system.cpu1.fetch.IcacheWaitRetryStallCycles 7575 # Number of stall cycles due to full MSHR 1537system.cpu1.fetch.CacheLines 43641835 # Number of cache lines fetched 1538system.cpu1.fetch.IcacheSquashes 116209 # Number of outstanding Icache misses that were squashed 1539system.cpu1.fetch.ItlbSquashes 2258 # Number of outstanding ITLB misses that were squashed 1540system.cpu1.fetch.rateDist::samples 104278525 # Number of instructions fetched each cycle (Total) 1541system.cpu1.fetch.rateDist::mean 1.296897 # Number of instructions fetched each cycle (Total) 1542system.cpu1.fetch.rateDist::stdev 1.339782 # Number of instructions fetched each cycle (Total) | 1536system.cpu1.fetch.icacheStallCycles 9986788 # Number of cycles fetch is stalled on an Icache miss 1537system.cpu1.fetch.Insts 109166158 # Number of instructions fetch has processed 1538system.cpu1.fetch.Branches 33910806 # Number of branches that fetch encountered 1539system.cpu1.fetch.predictedBranches 27449504 # Number of branches that fetch has predicted taken 1540system.cpu1.fetch.Cycles 91794015 # Number of cycles fetch has run and was not squashing or blocked 1541system.cpu1.fetch.SquashCycles 3775656 # Number of cycles fetch has spent squashing 1542system.cpu1.fetch.TlbCycles 78908 # Number of cycles fetch has spent waiting for tlb 1543system.cpu1.fetch.MiscStallCycles 31556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1544system.cpu1.fetch.PendingTrapStallCycles 200392 # Number of stall cycles due to pending traps 1545system.cpu1.fetch.PendingQuiesceStallCycles 294710 # Number of stall cycles due to pending quiesce instructions 1546system.cpu1.fetch.IcacheWaitRetryStallCycles 7499 # Number of stall cycles due to full MSHR 1547system.cpu1.fetch.CacheLines 43641278 # Number of cache lines fetched 1548system.cpu1.fetch.IcacheSquashes 116202 # Number of outstanding Icache misses that were squashed 1549system.cpu1.fetch.ItlbSquashes 2270 # Number of outstanding ITLB misses that were squashed 1550system.cpu1.fetch.rateDist::samples 104281696 # Number of instructions fetched each cycle (Total) 1551system.cpu1.fetch.rateDist::mean 1.296833 # Number of instructions fetched each cycle (Total) 1552system.cpu1.fetch.rateDist::stdev 1.339781 # Number of instructions fetched each cycle (Total) |
| 1543system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1553system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1544system.cpu1.fetch.rateDist::0 47329971 45.39% 45.39% # Number of instructions fetched each cycle (Total) 1545system.cpu1.fetch.rateDist::1 14035379 13.46% 58.85% # Number of instructions fetched each cycle (Total) 1546system.cpu1.fetch.rateDist::2 7536372 7.23% 66.07% # Number of instructions fetched each cycle (Total) 1547system.cpu1.fetch.rateDist::3 35376803 33.93% 100.00% # Number of instructions fetched each cycle (Total) | 1554system.cpu1.fetch.rateDist::0 47334317 45.39% 45.39% # Number of instructions fetched each cycle (Total) 1555system.cpu1.fetch.rateDist::1 14034977 13.46% 58.85% # Number of instructions fetched each cycle (Total) 1556system.cpu1.fetch.rateDist::2 7536210 7.23% 66.08% # Number of instructions fetched each cycle (Total) 1557system.cpu1.fetch.rateDist::3 35376192 33.92% 100.00% # Number of instructions fetched each cycle (Total) |
| 1548system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1549system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1550system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1558system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1559system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1560system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1551system.cpu1.fetch.rateDist::total 104278525 # Number of instructions fetched each cycle (Total) 1552system.cpu1.fetch.branchRate 0.324130 # Number of branch fetches per cycle 1553system.cpu1.fetch.rate 1.043449 # Number of inst fetches per cycle 1554system.cpu1.decode.IdleCycles 13017622 # Number of cycles decode is idle 1555system.cpu1.decode.BlockedCycles 61671390 # Number of cycles decode is blocked 1556system.cpu1.decode.RunCycles 26724772 # Number of cycles decode is running 1557system.cpu1.decode.UnblockCycles 1111637 # Number of cycles decode is unblocking 1558system.cpu1.decode.SquashCycles 1753104 # Number of cycles decode is squashing 1559system.cpu1.decode.BranchResolved 754173 # Number of times decode resolved a branch | 1561system.cpu1.fetch.rateDist::total 104281696 # Number of instructions fetched each cycle (Total) 1562system.cpu1.fetch.branchRate 0.324124 # Number of branch fetches per cycle 1563system.cpu1.fetch.rate 1.043425 # Number of inst fetches per cycle 1564system.cpu1.decode.IdleCycles 13018026 # Number of cycles decode is idle 1565system.cpu1.decode.BlockedCycles 61674095 # Number of cycles decode is blocked 1566system.cpu1.decode.RunCycles 26725105 # Number of cycles decode is running 1567system.cpu1.decode.UnblockCycles 1111367 # Number of cycles decode is unblocking 1568system.cpu1.decode.SquashCycles 1753103 # Number of cycles decode is squashing 1569system.cpu1.decode.BranchResolved 754241 # Number of times decode resolved a branch |
| 1560system.cpu1.decode.BranchMispred 137598 # Number of times decode detected a branch misprediction | 1570system.cpu1.decode.BranchMispred 137598 # Number of times decode detected a branch misprediction |
| 1561system.cpu1.decode.DecodedInsts 68061604 # Number of instructions handled by decode 1562system.cpu1.decode.SquashedInsts 1168958 # Number of squashed instructions handled by decode 1563system.cpu1.rename.SquashCycles 1753104 # Number of cycles rename is squashing 1564system.cpu1.rename.IdleCycles 17450100 # Number of cycles rename is idle 1565system.cpu1.rename.BlockCycles 2254257 # Number of cycles rename is blocking 1566system.cpu1.rename.serializeStallCycles 56981217 # count of cycles rename stalled for serializing inst 1567system.cpu1.rename.RunCycles 23380222 # Number of cycles rename is running 1568system.cpu1.rename.UnblockCycles 2459625 # Number of cycles rename is unblocking 1569system.cpu1.rename.RenamedInsts 55156752 # Number of instructions processed by rename 1570system.cpu1.rename.SquashedInsts 230613 # Number of squashed instructions processed by rename 1571system.cpu1.rename.ROBFullEvents 263389 # Number of times rename has blocked due to ROB full 1572system.cpu1.rename.IQFullEvents 35416 # Number of times rename has blocked due to IQ full 1573system.cpu1.rename.LQFullEvents 18082 # Number of times rename has blocked due to LQ full 1574system.cpu1.rename.SQFullEvents 1432431 # Number of times rename has blocked due to SQ full 1575system.cpu1.rename.RenamedOperands 55002738 # Number of destination operands rename has renamed 1576system.cpu1.rename.RenameLookups 260522478 # Number of register rename lookups that rename has made 1577system.cpu1.rename.int_rename_lookups 58680214 # Number of integer rename lookups 1578system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups 1579system.cpu1.rename.CommittedMaps 52222609 # Number of HB maps that are committed 1580system.cpu1.rename.UndoneMaps 2780129 # Number of HB maps that are undone due to squashing 1581system.cpu1.rename.serializingInsts 1878054 # count of serializing insts renamed 1582system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed 1583system.cpu1.rename.skidInsts 13101359 # count of insts added to the skid buffer 1584system.cpu1.memDep0.insertedLoads 10457131 # Number of loads inserted to the mem dependence unit. 1585system.cpu1.memDep0.insertedStores 6914141 # Number of stores inserted to the mem dependence unit. 1586system.cpu1.memDep0.conflictingLoads 629237 # Number of conflicting loads. 1587system.cpu1.memDep0.conflictingStores 831086 # Number of conflicting stores. 1588system.cpu1.iq.iqInstsAdded 54264809 # Number of instructions added to the IQ (excludes non-spec) 1589system.cpu1.iq.iqNonSpecInstsAdded 589071 # Number of non-speculative instructions added to the IQ 1590system.cpu1.iq.iqInstsIssued 53908897 # Number of instructions issued 1591system.cpu1.iq.iqSquashedInstsIssued 111732 # Number of squashed instructions issued 1592system.cpu1.iq.iqSquashedInstsExamined 2292977 # Number of squashed instructions iterated over during squash; mainly for profiling 1593system.cpu1.iq.iqSquashedOperandsExamined 5809537 # Number of squashed operands that are examined and possibly removed from graph 1594system.cpu1.iq.iqSquashedNonSpecRemoved 48790 # Number of squashed non-spec instructions that were removed 1595system.cpu1.iq.issued_per_cycle::samples 104278525 # Number of insts issued each cycle 1596system.cpu1.iq.issued_per_cycle::mean 0.516970 # Number of insts issued each cycle 1597system.cpu1.iq.issued_per_cycle::stdev 0.852578 # Number of insts issued each cycle | 1571system.cpu1.decode.DecodedInsts 68060945 # Number of instructions handled by decode 1572system.cpu1.decode.SquashedInsts 1169140 # Number of squashed instructions handled by decode 1573system.cpu1.rename.SquashCycles 1753103 # Number of cycles rename is squashing 1574system.cpu1.rename.IdleCycles 17450583 # Number of cycles rename is idle 1575system.cpu1.rename.BlockCycles 2252903 # Number of cycles rename is blocking 1576system.cpu1.rename.serializeStallCycles 56981552 # count of cycles rename stalled for serializing inst 1577system.cpu1.rename.RunCycles 23380155 # Number of cycles rename is running 1578system.cpu1.rename.UnblockCycles 2463400 # Number of cycles rename is unblocking 1579system.cpu1.rename.RenamedInsts 55156301 # Number of instructions processed by rename 1580system.cpu1.rename.SquashedInsts 230486 # Number of squashed instructions processed by rename 1581system.cpu1.rename.ROBFullEvents 263427 # Number of times rename has blocked due to ROB full 1582system.cpu1.rename.IQFullEvents 35391 # Number of times rename has blocked due to IQ full 1583system.cpu1.rename.LQFullEvents 18241 # Number of times rename has blocked due to LQ full 1584system.cpu1.rename.SQFullEvents 1436172 # Number of times rename has blocked due to SQ full 1585system.cpu1.rename.RenamedOperands 55002320 # Number of destination operands rename has renamed 1586system.cpu1.rename.RenameLookups 260520543 # Number of register rename lookups that rename has made 1587system.cpu1.rename.int_rename_lookups 58679791 # Number of integer rename lookups 1588system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups 1589system.cpu1.rename.CommittedMaps 52223668 # Number of HB maps that are committed 1590system.cpu1.rename.UndoneMaps 2778652 # Number of HB maps that are undone due to squashing 1591system.cpu1.rename.serializingInsts 1878098 # count of serializing insts renamed 1592system.cpu1.rename.tempSerializingInsts 1805410 # count of temporary serializing insts renamed 1593system.cpu1.rename.skidInsts 13101415 # count of insts added to the skid buffer 1594system.cpu1.memDep0.insertedLoads 10456972 # Number of loads inserted to the mem dependence unit. 1595system.cpu1.memDep0.insertedStores 6914054 # Number of stores inserted to the mem dependence unit. 1596system.cpu1.memDep0.conflictingLoads 629493 # Number of conflicting loads. 1597system.cpu1.memDep0.conflictingStores 831483 # Number of conflicting stores. 1598system.cpu1.iq.iqInstsAdded 54264321 # Number of instructions added to the IQ (excludes non-spec) 1599system.cpu1.iq.iqNonSpecInstsAdded 589116 # Number of non-speculative instructions added to the IQ 1600system.cpu1.iq.iqInstsIssued 53908666 # Number of instructions issued 1601system.cpu1.iq.iqSquashedInstsIssued 111755 # Number of squashed instructions issued 1602system.cpu1.iq.iqSquashedInstsExamined 2291961 # Number of squashed instructions iterated over during squash; mainly for profiling 1603system.cpu1.iq.iqSquashedOperandsExamined 5808692 # Number of squashed operands that are examined and possibly removed from graph 1604system.cpu1.iq.iqSquashedNonSpecRemoved 48780 # Number of squashed non-spec instructions that were removed 1605system.cpu1.iq.issued_per_cycle::samples 104281696 # Number of insts issued each cycle 1606system.cpu1.iq.issued_per_cycle::mean 0.516952 # Number of insts issued each cycle 1607system.cpu1.iq.issued_per_cycle::stdev 0.852554 # Number of insts issued each cycle |
| 1598system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1608system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1599system.cpu1.iq.issued_per_cycle::0 71027306 68.11% 68.11% # Number of insts issued each cycle 1600system.cpu1.iq.issued_per_cycle::1 16528003 15.85% 83.96% # Number of insts issued each cycle 1601system.cpu1.iq.issued_per_cycle::2 13076309 12.54% 96.50% # Number of insts issued each cycle 1602system.cpu1.iq.issued_per_cycle::3 3359364 3.22% 99.72% # Number of insts issued each cycle 1603system.cpu1.iq.issued_per_cycle::4 287531 0.28% 100.00% # Number of insts issued each cycle | 1609system.cpu1.iq.issued_per_cycle::0 71029795 68.11% 68.11% # Number of insts issued each cycle 1610system.cpu1.iq.issued_per_cycle::1 16529290 15.85% 83.96% # Number of insts issued each cycle 1611system.cpu1.iq.issued_per_cycle::2 13075763 12.54% 96.50% # Number of insts issued each cycle 1612system.cpu1.iq.issued_per_cycle::3 3359554 3.22% 99.72% # Number of insts issued each cycle 1613system.cpu1.iq.issued_per_cycle::4 287282 0.28% 100.00% # Number of insts issued each cycle |
| 1604system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle 1605system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1606system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1607system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1608system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1609system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1610system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1614system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle 1615system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1616system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1617system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1618system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1619system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1620system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1611system.cpu1.iq.issued_per_cycle::total 104278525 # Number of insts issued each cycle | 1621system.cpu1.iq.issued_per_cycle::total 104281696 # Number of insts issued each cycle |
| 1612system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1622system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1613system.cpu1.iq.fu_full::IntAlu 2925381 45.12% 45.12% # attempts to use FU when none available | 1623system.cpu1.iq.fu_full::IntAlu 2925282 45.12% 45.12% # attempts to use FU when none available |
| 1614system.cpu1.iq.fu_full::IntMult 677 0.01% 45.13% # attempts to use FU when none available 1615system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.13% # attempts to use FU when none available 1616system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.13% # attempts to use FU when none available 1617system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.13% # attempts to use FU when none available 1618system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.13% # attempts to use FU when none available 1619system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.13% # attempts to use FU when none available 1620system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.13% # attempts to use FU when none available 1621system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.13% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 1634system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.13% # attempts to use FU when none available 1635system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.13% # attempts to use FU when none available 1636system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.13% # attempts to use FU when none available 1637system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.13% # attempts to use FU when none available 1638system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.13% # attempts to use FU when none available 1639system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.13% # attempts to use FU when none available 1640system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.13% # attempts to use FU when none available 1641system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.13% # attempts to use FU when none available | 1624system.cpu1.iq.fu_full::IntMult 677 0.01% 45.13% # attempts to use FU when none available 1625system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.13% # attempts to use FU when none available 1626system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.13% # attempts to use FU when none available 1627system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.13% # attempts to use FU when none available 1628system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.13% # attempts to use FU when none available 1629system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.13% # attempts to use FU when none available 1630system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.13% # attempts to use FU when none available 1631system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.13% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 1644system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.13% # attempts to use FU when none available 1645system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.13% # attempts to use FU when none available 1646system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.13% # attempts to use FU when none available 1647system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.13% # attempts to use FU when none available 1648system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.13% # attempts to use FU when none available 1649system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.13% # attempts to use FU when none available 1650system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.13% # attempts to use FU when none available 1651system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.13% # attempts to use FU when none available |
| 1642system.cpu1.iq.fu_full::MemRead 1673591 25.81% 70.94% # attempts to use FU when none available 1643system.cpu1.iq.fu_full::MemWrite 1884116 29.06% 100.00% # attempts to use FU when none available | 1652system.cpu1.iq.fu_full::MemRead 1673331 25.81% 70.93% # attempts to use FU when none available 1653system.cpu1.iq.fu_full::MemWrite 1884639 29.07% 100.00% # attempts to use FU when none available |
| 1644system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1645system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1646system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued | 1654system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1655system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1656system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued |
| 1647system.cpu1.iq.FU_type_0::IntAlu 36727260 68.13% 68.13% # Type of FU issued 1648system.cpu1.iq.FU_type_0::IntMult 46535 0.09% 68.21% # Type of FU issued 1649system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued 1650system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued 1651system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued 1652system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued 1653system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued 1654system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued 1655system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued 1656system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued 1657system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued 1658system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued 1659system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued 1660system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued 1661system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued 1662system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued 1663system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued 1664system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued 1665system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued 1666system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued 1667system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued 1668system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued 1669system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued 1670system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued 1671system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued | 1657system.cpu1.iq.FU_type_0::IntAlu 36727327 68.13% 68.13% # Type of FU issued 1658system.cpu1.iq.FU_type_0::IntMult 46544 0.09% 68.22% # Type of FU issued 1659system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued 1660system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued 1661system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued 1662system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued 1663system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued 1664system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued 1665system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued 1666system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued 1667system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued 1668system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued 1669system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued 1670system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued 1671system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued 1672system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued 1673system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued 1674system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued 1675system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued 1676system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued 1677system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued 1678system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued 1679system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued 1680system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued 1681system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued |
| 1672system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued 1673system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 1674system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 1675system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued | 1682system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued 1683system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 1684system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 1685system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued |
| 1676system.cpu1.iq.FU_type_0::MemRead 10380151 19.25% 87.48% # Type of FU issued 1677system.cpu1.iq.FU_type_0::MemWrite 6751543 12.52% 100.00% # Type of FU issued | 1686system.cpu1.iq.FU_type_0::MemRead 10380092 19.25% 87.48% # Type of FU issued 1687system.cpu1.iq.FU_type_0::MemWrite 6751298 12.52% 100.00% # Type of FU issued |
| 1678system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1679system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1688system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1689system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1680system.cpu1.iq.FU_type_0::total 53908897 # Type of FU issued 1681system.cpu1.iq.rate 0.515271 # Inst issue rate 1682system.cpu1.iq.fu_busy_cnt 6483765 # FU busy when requested 1683system.cpu1.iq.fu_busy_rate 0.120273 # FU busy rate (busy events/executed inst) 1684system.cpu1.iq.int_inst_queue_reads 218686026 # Number of integer instruction queue reads 1685system.cpu1.iq.int_inst_queue_writes 57154966 # Number of integer instruction queue writes 1686system.cpu1.iq.int_inst_queue_wakeup_accesses 51920427 # Number of integer instruction queue wakeup accesses 1687system.cpu1.iq.fp_inst_queue_reads 5790 # Number of floating instruction queue reads 1688system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes 1689system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses 1690system.cpu1.iq.int_alu_accesses 60388895 # Number of integer alu accesses 1691system.cpu1.iq.fp_alu_accesses 3701 # Number of floating point alu accesses 1692system.cpu1.iew.lsq.thread0.forwLoads 91393 # Number of loads that had data forwarded from stores | 1690system.cpu1.iq.FU_type_0::total 53908666 # Type of FU issued 1691system.cpu1.iq.rate 0.515266 # Inst issue rate 1692system.cpu1.iq.fu_busy_cnt 6483929 # FU busy when requested 1693system.cpu1.iq.fu_busy_rate 0.120276 # FU busy rate (busy events/executed inst) 1694system.cpu1.iq.int_inst_queue_reads 218688932 # Number of integer instruction queue reads 1695system.cpu1.iq.int_inst_queue_writes 57153517 # Number of integer instruction queue writes 1696system.cpu1.iq.int_inst_queue_wakeup_accesses 51920276 # Number of integer instruction queue wakeup accesses 1697system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads 1698system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes 1699system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses 1700system.cpu1.iq.int_alu_accesses 60388837 # Number of integer alu accesses 1701system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses 1702system.cpu1.iew.lsq.thread0.forwLoads 91402 # Number of loads that had data forwarded from stores |
| 1693system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1703system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1694system.cpu1.iew.lsq.thread0.squashedLoads 490676 # Number of loads squashed 1695system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed 1696system.cpu1.iew.lsq.thread0.memOrderViolation 10193 # Number of memory ordering violations 1697system.cpu1.iew.lsq.thread0.squashedStores 356081 # Number of stores squashed | 1704system.cpu1.iew.lsq.thread0.squashedLoads 490292 # Number of loads squashed 1705system.cpu1.iew.lsq.thread0.ignoredResponses 689 # Number of memory responses ignored because the instruction is squashed 1706system.cpu1.iew.lsq.thread0.memOrderViolation 10197 # Number of memory ordering violations 1707system.cpu1.iew.lsq.thread0.squashedStores 355874 # Number of stores squashed |
| 1698system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1699system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1708system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1709system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1700system.cpu1.iew.lsq.thread0.rescheduledLoads 51970 # Number of loads that were rescheduled 1701system.cpu1.iew.lsq.thread0.cacheBlocked 70495 # Number of times an access to memory failed due to the cache being blocked | 1710system.cpu1.iew.lsq.thread0.rescheduledLoads 52006 # Number of loads that were rescheduled 1711system.cpu1.iew.lsq.thread0.cacheBlocked 70534 # Number of times an access to memory failed due to the cache being blocked |
| 1702system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1712system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1703system.cpu1.iew.iewSquashCycles 1753104 # Number of cycles IEW is squashing 1704system.cpu1.iew.iewBlockCycles 548003 # Number of cycles IEW is blocking 1705system.cpu1.iew.iewUnblockCycles 114295 # Number of cycles IEW is unblocking 1706system.cpu1.iew.iewDispatchedInsts 54906042 # Number of instructions dispatched to IQ | 1713system.cpu1.iew.iewSquashCycles 1753103 # Number of cycles IEW is squashing 1714system.cpu1.iew.iewBlockCycles 547921 # Number of cycles IEW is blocking 1715system.cpu1.iew.iewUnblockCycles 114364 # Number of cycles IEW is unblocking 1716system.cpu1.iew.iewDispatchedInsts 54905583 # Number of instructions dispatched to IQ |
| 1707system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 1717system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 1708system.cpu1.iew.iewDispLoadInsts 10457131 # Number of dispatched load instructions 1709system.cpu1.iew.iewDispStoreInsts 6914141 # Number of dispatched store instructions 1710system.cpu1.iew.iewDispNonSpecInsts 301584 # Number of dispatched non-speculative instructions 1711system.cpu1.iew.iewIQFullEvents 9824 # Number of times the IQ has become full, causing a stall 1712system.cpu1.iew.iewLSQFullEvents 96972 # Number of times the LSQ has become full, causing a stall 1713system.cpu1.iew.memOrderViolationEvents 10193 # Number of memory order violations 1714system.cpu1.iew.predictedTakenIncorrect 54960 # Number of branches that were predicted taken incorrectly 1715system.cpu1.iew.predictedNotTakenIncorrect 127313 # Number of branches that were predicted not taken incorrectly 1716system.cpu1.iew.branchMispredicts 182273 # Number of branch mispredicts detected at execute 1717system.cpu1.iew.iewExecutedInsts 53638837 # Number of executed instructions 1718system.cpu1.iew.iewExecLoadInsts 10278190 # Number of load instructions executed 1719system.cpu1.iew.iewExecSquashedInsts 248481 # Number of squashed instructions skipped in execute | 1718system.cpu1.iew.iewDispLoadInsts 10456972 # Number of dispatched load instructions 1719system.cpu1.iew.iewDispStoreInsts 6914054 # Number of dispatched store instructions 1720system.cpu1.iew.iewDispNonSpecInsts 301613 # Number of dispatched non-speculative instructions 1721system.cpu1.iew.iewIQFullEvents 9861 # Number of times the IQ has become full, causing a stall 1722system.cpu1.iew.iewLSQFullEvents 97001 # Number of times the LSQ has become full, causing a stall 1723system.cpu1.iew.memOrderViolationEvents 10197 # Number of memory order violations 1724system.cpu1.iew.predictedTakenIncorrect 54939 # Number of branches that were predicted taken incorrectly 1725system.cpu1.iew.predictedNotTakenIncorrect 127326 # Number of branches that were predicted not taken incorrectly 1726system.cpu1.iew.branchMispredicts 182265 # Number of branch mispredicts detected at execute 1727system.cpu1.iew.iewExecutedInsts 53638641 # Number of executed instructions 1728system.cpu1.iew.iewExecLoadInsts 10278143 # Number of load instructions executed 1729system.cpu1.iew.iewExecSquashedInsts 248381 # Number of squashed instructions skipped in execute |
| 1720system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1730system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1721system.cpu1.iew.exec_nop 52162 # number of nop insts executed 1722system.cpu1.iew.exec_refs 16965416 # number of memory reference insts executed 1723system.cpu1.iew.exec_branches 11807917 # Number of branches executed 1724system.cpu1.iew.exec_stores 6687226 # Number of stores executed 1725system.cpu1.iew.exec_rate 0.512690 # Inst execution rate 1726system.cpu1.iew.wb_sent 53497875 # cumulative count of insts sent to commit 1727system.cpu1.iew.wb_count 51922213 # cumulative count of insts written-back 1728system.cpu1.iew.wb_producers 25229776 # num instructions producing a value 1729system.cpu1.iew.wb_consumers 38490454 # num instructions consuming a value | 1731system.cpu1.iew.exec_nop 52146 # number of nop insts executed 1732system.cpu1.iew.exec_refs 16965109 # number of memory reference insts executed 1733system.cpu1.iew.exec_branches 11808008 # Number of branches executed 1734system.cpu1.iew.exec_stores 6686966 # Number of stores executed 1735system.cpu1.iew.exec_rate 0.512685 # Inst execution rate 1736system.cpu1.iew.wb_sent 53497702 # cumulative count of insts sent to commit 1737system.cpu1.iew.wb_count 51922060 # cumulative count of insts written-back 1738system.cpu1.iew.wb_producers 25229975 # num instructions producing a value 1739system.cpu1.iew.wb_consumers 38490431 # num instructions consuming a value |
| 1730system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1740system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1731system.cpu1.iew.wb_rate 0.496282 # insts written-back per cycle 1732system.cpu1.iew.wb_fanout 0.655481 # average fanout of values written-back | 1741system.cpu1.iew.wb_rate 0.496278 # insts written-back per cycle 1742system.cpu1.iew.wb_fanout 0.655487 # average fanout of values written-back |
| 1733system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1743system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1734system.cpu1.commit.commitSquashedInsts 3658692 # The number of squashed insts skipped by commit 1735system.cpu1.commit.commitNonSpecStalls 540281 # The number of times commit has been forced to stall to communicate backwards 1736system.cpu1.commit.branchMispredicts 170405 # The number of times a branch was mispredicted 1737system.cpu1.commit.committed_per_cycle::samples 102346479 # Number of insts commited each cycle 1738system.cpu1.commit.committed_per_cycle::mean 0.498098 # Number of insts commited each cycle 1739system.cpu1.commit.committed_per_cycle::stdev 1.159114 # Number of insts commited each cycle | 1744system.cpu1.commit.commitSquashedInsts 3657476 # The number of squashed insts skipped by commit 1745system.cpu1.commit.commitNonSpecStalls 540336 # The number of times commit has been forced to stall to communicate backwards 1746system.cpu1.commit.branchMispredicts 170387 # The number of times a branch was mispredicted 1747system.cpu1.commit.committed_per_cycle::samples 102349842 # Number of insts commited each cycle 1748system.cpu1.commit.committed_per_cycle::mean 0.498091 # Number of insts commited each cycle 1749system.cpu1.commit.committed_per_cycle::stdev 1.159102 # Number of insts commited each cycle |
| 1740system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1750system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1741system.cpu1.commit.committed_per_cycle::0 76767559 75.01% 75.01% # Number of insts commited each cycle 1742system.cpu1.commit.committed_per_cycle::1 14288132 13.96% 88.97% # Number of insts commited each cycle 1743system.cpu1.commit.committed_per_cycle::2 6080244 5.94% 94.91% # Number of insts commited each cycle 1744system.cpu1.commit.committed_per_cycle::3 703970 0.69% 95.60% # Number of insts commited each cycle 1745system.cpu1.commit.committed_per_cycle::4 1980102 1.93% 97.53% # Number of insts commited each cycle 1746system.cpu1.commit.committed_per_cycle::5 1566998 1.53% 99.06% # Number of insts commited each cycle 1747system.cpu1.commit.committed_per_cycle::6 444730 0.43% 99.50% # Number of insts commited each cycle 1748system.cpu1.commit.committed_per_cycle::7 123732 0.12% 99.62% # Number of insts commited each cycle 1749system.cpu1.commit.committed_per_cycle::8 391012 0.38% 100.00% # Number of insts commited each cycle | 1751system.cpu1.commit.committed_per_cycle::0 76769313 75.01% 75.01% # Number of insts commited each cycle 1752system.cpu1.commit.committed_per_cycle::1 14290135 13.96% 88.97% # Number of insts commited each cycle 1753system.cpu1.commit.committed_per_cycle::2 6080073 5.94% 94.91% # Number of insts commited each cycle 1754system.cpu1.commit.committed_per_cycle::3 704006 0.69% 95.60% # Number of insts commited each cycle 1755system.cpu1.commit.committed_per_cycle::4 1980080 1.93% 97.53% # Number of insts commited each cycle 1756system.cpu1.commit.committed_per_cycle::5 1566587 1.53% 99.06% # Number of insts commited each cycle 1757system.cpu1.commit.committed_per_cycle::6 444714 0.43% 99.50% # Number of insts commited each cycle 1758system.cpu1.commit.committed_per_cycle::7 123770 0.12% 99.62% # Number of insts commited each cycle 1759system.cpu1.commit.committed_per_cycle::8 391164 0.38% 100.00% # Number of insts commited each cycle |
| 1750system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1751system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1752system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1760system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1761system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1762system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1753system.cpu1.commit.committed_per_cycle::total 102346479 # Number of insts commited each cycle 1754system.cpu1.commit.committedInsts 41392684 # Number of instructions committed 1755system.cpu1.commit.committedOps 50978528 # Number of ops (including micro ops) committed | 1763system.cpu1.commit.committed_per_cycle::total 102349842 # Number of insts commited each cycle 1764system.cpu1.commit.committedInsts 41393585 # Number of instructions committed 1765system.cpu1.commit.committedOps 50979540 # Number of ops (including micro ops) committed |
| 1756system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1766system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1757system.cpu1.commit.refs 16524515 # Number of memory references committed 1758system.cpu1.commit.loads 9966455 # Number of loads committed 1759system.cpu1.commit.membars 209698 # Number of memory barriers committed 1760system.cpu1.commit.branches 11639872 # Number of branches committed | 1767system.cpu1.commit.refs 16524860 # Number of memory references committed 1768system.cpu1.commit.loads 9966680 # Number of loads committed 1769system.cpu1.commit.membars 209721 # Number of memory barriers committed 1770system.cpu1.commit.branches 11640060 # Number of branches committed |
| 1761system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. | 1771system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. |
| 1762system.cpu1.commit.int_insts 45828467 # Number of committed integer instructions. 1763system.cpu1.commit.function_calls 3366626 # Number of function calls committed. | 1772system.cpu1.commit.int_insts 45829312 # Number of committed integer instructions. 1773system.cpu1.commit.function_calls 3366651 # Number of function calls committed. |
| 1764system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 1774system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 1765system.cpu1.commit.op_class_0::IntAlu 34405041 67.49% 67.49% # Class of committed instruction 1766system.cpu1.commit.op_class_0::IntMult 45633 0.09% 67.58% # Class of committed instruction | 1775system.cpu1.commit.op_class_0::IntAlu 34405704 67.49% 67.49% # Class of committed instruction 1776system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction |
| 1767system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction 1768system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction 1769system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction 1770system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction 1771system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction 1772system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction 1773system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction 1774system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 1786system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction 1787system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction 1788system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction 1789system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction 1790system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction 1791system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction 1792system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction 1793system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction | 1777system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction 1778system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction 1779system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction 1780system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction 1781system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction 1782system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction 1783system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction 1784system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 1796system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction 1797system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction 1798system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction 1799system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction 1800system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction 1801system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction 1802system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction 1803system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction |
| 1794system.cpu1.commit.op_class_0::MemRead 9966455 19.55% 87.14% # Class of committed instruction 1795system.cpu1.commit.op_class_0::MemWrite 6558060 12.86% 100.00% # Class of committed instruction | 1804system.cpu1.commit.op_class_0::MemRead 9966680 19.55% 87.14% # Class of committed instruction 1805system.cpu1.commit.op_class_0::MemWrite 6558180 12.86% 100.00% # Class of committed instruction |
| 1796system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1797system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1806system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1807system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1798system.cpu1.commit.op_class_0::total 50978528 # Class of committed instruction 1799system.cpu1.commit.bw_lim_events 391012 # number cycles where commit BW limit reached | 1808system.cpu1.commit.op_class_0::total 50979540 # Class of committed instruction 1809system.cpu1.commit.bw_lim_events 391164 # number cycles where commit BW limit reached |
| 1800system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1810system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1801system.cpu1.rob.rob_reads 136555973 # The number of ROB reads 1802system.cpu1.rob.rob_writes 111202855 # The number of ROB writes 1803system.cpu1.timesIdled 53415 # Number of times that the entire CPU went into an idle state and unscheduled itself 1804system.cpu1.idleCycles 343799 # Total number of cycles that the CPU has spent unscheduled due to idling 1805system.cpu1.quiesceCycles 5543567058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1806system.cpu1.committedInsts 41359830 # Number of Instructions Simulated 1807system.cpu1.committedOps 50945674 # Number of Ops (including micro ops) Simulated 1808system.cpu1.cpi 2.529564 # CPI: Cycles Per Instruction 1809system.cpu1.cpi_total 2.529564 # CPI: Total CPI of All Threads 1810system.cpu1.ipc 0.395325 # IPC: Instructions Per Cycle 1811system.cpu1.ipc_total 0.395325 # IPC: Total IPC of All Threads 1812system.cpu1.int_regfile_reads 56285102 # number of integer regfile reads 1813system.cpu1.int_regfile_writes 35740910 # number of integer regfile writes 1814system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads 1815system.cpu1.fp_regfile_writes 520 # number of floating regfile writes 1816system.cpu1.cc_regfile_reads 191162273 # number of cc regfile reads 1817system.cpu1.cc_regfile_writes 15560809 # number of cc regfile writes 1818system.cpu1.misc_regfile_reads 205875708 # number of misc regfile reads 1819system.cpu1.misc_regfile_writes 388862 # number of misc regfile writes | 1811system.cpu1.rob.rob_reads 136558924 # The number of ROB reads 1812system.cpu1.rob.rob_writes 111202252 # The number of ROB writes 1813system.cpu1.timesIdled 53311 # Number of times that the entire CPU went into an idle state and unscheduled itself 1814system.cpu1.idleCycles 341239 # Total number of cycles that the CPU has spent unscheduled due to idling 1815system.cpu1.quiesceCycles 5543976372 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1816system.cpu1.committedInsts 41360731 # Number of Instructions Simulated 1817system.cpu1.committedOps 50946686 # Number of Ops (including micro ops) Simulated 1818system.cpu1.cpi 2.529523 # CPI: Cycles Per Instruction 1819system.cpu1.cpi_total 2.529523 # CPI: Total CPI of All Threads 1820system.cpu1.ipc 0.395331 # IPC: Instructions Per Cycle 1821system.cpu1.ipc_total 0.395331 # IPC: Total IPC of All Threads 1822system.cpu1.int_regfile_reads 56284724 # number of integer regfile reads 1823system.cpu1.int_regfile_writes 35740870 # number of integer regfile writes 1824system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads 1825system.cpu1.fp_regfile_writes 516 # number of floating regfile writes 1826system.cpu1.cc_regfile_reads 191161936 # number of cc regfile reads 1827system.cpu1.cc_regfile_writes 15560884 # number of cc regfile writes 1828system.cpu1.misc_regfile_reads 205876605 # number of misc regfile reads 1829system.cpu1.misc_regfile_writes 388900 # number of misc regfile writes |
| 1820system.cpu1.dcache.tags.replacements 191071 # number of replacements | 1830system.cpu1.dcache.tags.replacements 191071 # number of replacements |
| 1821system.cpu1.dcache.tags.tagsinuse 472.558495 # Cycle average of tags in use 1822system.cpu1.dcache.tags.total_refs 15741437 # Total number of references to valid blocks. | 1831system.cpu1.dcache.tags.tagsinuse 472.564441 # Cycle average of tags in use 1832system.cpu1.dcache.tags.total_refs 15741519 # Total number of references to valid blocks. |
| 1823system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. | 1833system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. |
| 1824system.cpu1.dcache.tags.avg_refs 82.245811 # Average number of references to valid blocks. | 1834system.cpu1.dcache.tags.avg_refs 82.246239 # Average number of references to valid blocks. |
| 1825system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. | 1835system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. |
| 1826system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558495 # Average occupied blocks per requestor 1827system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy 1828system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy | 1836system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.564441 # Average occupied blocks per requestor 1837system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922977 # Average percentage of cache occupancy 1838system.cpu1.dcache.tags.occ_percent::total 0.922977 # Average percentage of cache occupancy |
| 1829system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id 1830system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 1831system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1832system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id | 1839system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id 1840system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 1841system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1842system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id |
| 1833system.cpu1.dcache.tags.tag_accesses 32983767 # Number of tag accesses 1834system.cpu1.dcache.tags.data_accesses 32983767 # Number of data accesses 1835system.cpu1.dcache.ReadReq_hits::cpu1.data 9574609 # number of ReadReq hits 1836system.cpu1.dcache.ReadReq_hits::total 9574609 # number of ReadReq hits 1837system.cpu1.dcache.WriteReq_hits::cpu1.data 5910607 # number of WriteReq hits 1838system.cpu1.dcache.WriteReq_hits::total 5910607 # number of WriteReq hits 1839system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49573 # number of SoftPFReq hits 1840system.cpu1.dcache.SoftPFReq_hits::total 49573 # number of SoftPFReq hits 1841system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79145 # number of LoadLockedReq hits 1842system.cpu1.dcache.LoadLockedReq_hits::total 79145 # number of LoadLockedReq hits | 1843system.cpu1.dcache.tags.tag_accesses 32983738 # Number of tag accesses 1844system.cpu1.dcache.tags.data_accesses 32983738 # Number of data accesses 1845system.cpu1.dcache.ReadReq_hits::cpu1.data 9574548 # number of ReadReq hits 1846system.cpu1.dcache.ReadReq_hits::total 9574548 # number of ReadReq hits 1847system.cpu1.dcache.WriteReq_hits::cpu1.data 5910552 # number of WriteReq hits 1848system.cpu1.dcache.WriteReq_hits::total 5910552 # number of WriteReq hits 1849system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49554 # number of SoftPFReq hits 1850system.cpu1.dcache.SoftPFReq_hits::total 49554 # number of SoftPFReq hits 1851system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79147 # number of LoadLockedReq hits 1852system.cpu1.dcache.LoadLockedReq_hits::total 79147 # number of LoadLockedReq hits |
| 1843system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71001 # number of StoreCondReq hits 1844system.cpu1.dcache.StoreCondReq_hits::total 71001 # number of StoreCondReq hits | 1853system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71001 # number of StoreCondReq hits 1854system.cpu1.dcache.StoreCondReq_hits::total 71001 # number of StoreCondReq hits |
| 1845system.cpu1.dcache.demand_hits::cpu1.data 15485216 # number of demand (read+write) hits 1846system.cpu1.dcache.demand_hits::total 15485216 # number of demand (read+write) hits 1847system.cpu1.dcache.overall_hits::cpu1.data 15534789 # number of overall hits 1848system.cpu1.dcache.overall_hits::total 15534789 # number of overall hits 1849system.cpu1.dcache.ReadReq_misses::cpu1.data 219415 # number of ReadReq misses 1850system.cpu1.dcache.ReadReq_misses::total 219415 # number of ReadReq misses 1851system.cpu1.dcache.WriteReq_misses::cpu1.data 398307 # number of WriteReq misses 1852system.cpu1.dcache.WriteReq_misses::total 398307 # number of WriteReq misses 1853system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30093 # number of SoftPFReq misses 1854system.cpu1.dcache.SoftPFReq_misses::total 30093 # number of SoftPFReq misses 1855system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18121 # number of LoadLockedReq misses 1856system.cpu1.dcache.LoadLockedReq_misses::total 18121 # number of LoadLockedReq misses 1857system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23394 # number of StoreCondReq misses 1858system.cpu1.dcache.StoreCondReq_misses::total 23394 # number of StoreCondReq misses 1859system.cpu1.dcache.demand_misses::cpu1.data 617722 # number of demand (read+write) misses 1860system.cpu1.dcache.demand_misses::total 617722 # number of demand (read+write) misses 1861system.cpu1.dcache.overall_misses::cpu1.data 647815 # number of overall misses 1862system.cpu1.dcache.overall_misses::total 647815 # number of overall misses 1863system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3455998019 # number of ReadReq miss cycles 1864system.cpu1.dcache.ReadReq_miss_latency::total 3455998019 # number of ReadReq miss cycles 1865system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8728631208 # number of WriteReq miss cycles 1866system.cpu1.dcache.WriteReq_miss_latency::total 8728631208 # number of WriteReq miss cycles 1867system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363006249 # number of LoadLockedReq miss cycles 1868system.cpu1.dcache.LoadLockedReq_miss_latency::total 363006249 # number of LoadLockedReq miss cycles 1869system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542688316 # number of StoreCondReq miss cycles 1870system.cpu1.dcache.StoreCondReq_miss_latency::total 542688316 # number of StoreCondReq miss cycles 1871system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 504500 # number of StoreCondFailReq miss cycles 1872system.cpu1.dcache.StoreCondFailReq_miss_latency::total 504500 # number of StoreCondFailReq miss cycles 1873system.cpu1.dcache.demand_miss_latency::cpu1.data 12184629227 # number of demand (read+write) miss cycles 1874system.cpu1.dcache.demand_miss_latency::total 12184629227 # number of demand (read+write) miss cycles 1875system.cpu1.dcache.overall_miss_latency::cpu1.data 12184629227 # number of overall miss cycles 1876system.cpu1.dcache.overall_miss_latency::total 12184629227 # number of overall miss cycles 1877system.cpu1.dcache.ReadReq_accesses::cpu1.data 9794024 # number of ReadReq accesses(hits+misses) 1878system.cpu1.dcache.ReadReq_accesses::total 9794024 # number of ReadReq accesses(hits+misses) 1879system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308914 # number of WriteReq accesses(hits+misses) 1880system.cpu1.dcache.WriteReq_accesses::total 6308914 # number of WriteReq accesses(hits+misses) 1881system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79666 # number of SoftPFReq accesses(hits+misses) 1882system.cpu1.dcache.SoftPFReq_accesses::total 79666 # number of SoftPFReq accesses(hits+misses) 1883system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97266 # number of LoadLockedReq accesses(hits+misses) 1884system.cpu1.dcache.LoadLockedReq_accesses::total 97266 # number of LoadLockedReq accesses(hits+misses) 1885system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94395 # number of StoreCondReq accesses(hits+misses) 1886system.cpu1.dcache.StoreCondReq_accesses::total 94395 # number of StoreCondReq accesses(hits+misses) 1887system.cpu1.dcache.demand_accesses::cpu1.data 16102938 # number of demand (read+write) accesses 1888system.cpu1.dcache.demand_accesses::total 16102938 # number of demand (read+write) accesses 1889system.cpu1.dcache.overall_accesses::cpu1.data 16182604 # number of overall (read+write) accesses 1890system.cpu1.dcache.overall_accesses::total 16182604 # number of overall (read+write) accesses 1891system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022403 # miss rate for ReadReq accesses 1892system.cpu1.dcache.ReadReq_miss_rate::total 0.022403 # miss rate for ReadReq accesses 1893system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063134 # miss rate for WriteReq accesses 1894system.cpu1.dcache.WriteReq_miss_rate::total 0.063134 # miss rate for WriteReq accesses 1895system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377740 # miss rate for SoftPFReq accesses 1896system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377740 # miss rate for SoftPFReq accesses 1897system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186304 # miss rate for LoadLockedReq accesses 1898system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186304 # miss rate for LoadLockedReq accesses 1899system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247831 # miss rate for StoreCondReq accesses 1900system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247831 # miss rate for StoreCondReq accesses 1901system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038361 # miss rate for demand accesses 1902system.cpu1.dcache.demand_miss_rate::total 0.038361 # miss rate for demand accesses 1903system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040032 # miss rate for overall accesses 1904system.cpu1.dcache.overall_miss_rate::total 0.040032 # miss rate for overall accesses 1905system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15750.965153 # average ReadReq miss latency 1906system.cpu1.dcache.ReadReq_avg_miss_latency::total 15750.965153 # average ReadReq miss latency 1907system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21914.330424 # average WriteReq miss latency 1908system.cpu1.dcache.WriteReq_avg_miss_latency::total 21914.330424 # average WriteReq miss latency 1909system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20032.351912 # average LoadLockedReq miss latency 1910system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20032.351912 # average LoadLockedReq miss latency 1911system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23197.756519 # average StoreCondReq miss latency 1912system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23197.756519 # average StoreCondReq miss latency | 1855system.cpu1.dcache.demand_hits::cpu1.data 15485100 # number of demand (read+write) hits 1856system.cpu1.dcache.demand_hits::total 15485100 # number of demand (read+write) hits 1857system.cpu1.dcache.overall_hits::cpu1.data 15534654 # number of overall hits 1858system.cpu1.dcache.overall_hits::total 15534654 # number of overall hits 1859system.cpu1.dcache.ReadReq_misses::cpu1.data 219354 # number of ReadReq misses 1860system.cpu1.dcache.ReadReq_misses::total 219354 # number of ReadReq misses 1861system.cpu1.dcache.WriteReq_misses::cpu1.data 398461 # number of WriteReq misses 1862system.cpu1.dcache.WriteReq_misses::total 398461 # number of WriteReq misses 1863system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30111 # number of SoftPFReq misses 1864system.cpu1.dcache.SoftPFReq_misses::total 30111 # number of SoftPFReq misses 1865system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18127 # number of LoadLockedReq misses 1866system.cpu1.dcache.LoadLockedReq_misses::total 18127 # number of LoadLockedReq misses 1867system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23403 # number of StoreCondReq misses 1868system.cpu1.dcache.StoreCondReq_misses::total 23403 # number of StoreCondReq misses 1869system.cpu1.dcache.demand_misses::cpu1.data 617815 # number of demand (read+write) misses 1870system.cpu1.dcache.demand_misses::total 617815 # number of demand (read+write) misses 1871system.cpu1.dcache.overall_misses::cpu1.data 647926 # number of overall misses 1872system.cpu1.dcache.overall_misses::total 647926 # number of overall misses 1873system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453063988 # number of ReadReq miss cycles 1874system.cpu1.dcache.ReadReq_miss_latency::total 3453063988 # number of ReadReq miss cycles 1875system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8746670918 # number of WriteReq miss cycles 1876system.cpu1.dcache.WriteReq_miss_latency::total 8746670918 # number of WriteReq miss cycles 1877system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363087750 # number of LoadLockedReq miss cycles 1878system.cpu1.dcache.LoadLockedReq_miss_latency::total 363087750 # number of LoadLockedReq miss cycles 1879system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542334299 # number of StoreCondReq miss cycles 1880system.cpu1.dcache.StoreCondReq_miss_latency::total 542334299 # number of StoreCondReq miss cycles 1881system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 511000 # number of StoreCondFailReq miss cycles 1882system.cpu1.dcache.StoreCondFailReq_miss_latency::total 511000 # number of StoreCondFailReq miss cycles 1883system.cpu1.dcache.demand_miss_latency::cpu1.data 12199734906 # number of demand (read+write) miss cycles 1884system.cpu1.dcache.demand_miss_latency::total 12199734906 # number of demand (read+write) miss cycles 1885system.cpu1.dcache.overall_miss_latency::cpu1.data 12199734906 # number of overall miss cycles 1886system.cpu1.dcache.overall_miss_latency::total 12199734906 # number of overall miss cycles 1887system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793902 # number of ReadReq accesses(hits+misses) 1888system.cpu1.dcache.ReadReq_accesses::total 9793902 # number of ReadReq accesses(hits+misses) 1889system.cpu1.dcache.WriteReq_accesses::cpu1.data 6309013 # number of WriteReq accesses(hits+misses) 1890system.cpu1.dcache.WriteReq_accesses::total 6309013 # number of WriteReq accesses(hits+misses) 1891system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79665 # number of SoftPFReq accesses(hits+misses) 1892system.cpu1.dcache.SoftPFReq_accesses::total 79665 # number of SoftPFReq accesses(hits+misses) 1893system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97274 # number of LoadLockedReq accesses(hits+misses) 1894system.cpu1.dcache.LoadLockedReq_accesses::total 97274 # number of LoadLockedReq accesses(hits+misses) 1895system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94404 # number of StoreCondReq accesses(hits+misses) 1896system.cpu1.dcache.StoreCondReq_accesses::total 94404 # number of StoreCondReq accesses(hits+misses) 1897system.cpu1.dcache.demand_accesses::cpu1.data 16102915 # number of demand (read+write) accesses 1898system.cpu1.dcache.demand_accesses::total 16102915 # number of demand (read+write) accesses 1899system.cpu1.dcache.overall_accesses::cpu1.data 16182580 # number of overall (read+write) accesses 1900system.cpu1.dcache.overall_accesses::total 16182580 # number of overall (read+write) accesses 1901system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022397 # miss rate for ReadReq accesses 1902system.cpu1.dcache.ReadReq_miss_rate::total 0.022397 # miss rate for ReadReq accesses 1903system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063157 # miss rate for WriteReq accesses 1904system.cpu1.dcache.WriteReq_miss_rate::total 0.063157 # miss rate for WriteReq accesses 1905system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377970 # miss rate for SoftPFReq accesses 1906system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377970 # miss rate for SoftPFReq accesses 1907system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186350 # miss rate for LoadLockedReq accesses 1908system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186350 # miss rate for LoadLockedReq accesses 1909system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247903 # miss rate for StoreCondReq accesses 1910system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247903 # miss rate for StoreCondReq accesses 1911system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038367 # miss rate for demand accesses 1912system.cpu1.dcache.demand_miss_rate::total 0.038367 # miss rate for demand accesses 1913system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040038 # miss rate for overall accesses 1914system.cpu1.dcache.overall_miss_rate::total 0.040038 # miss rate for overall accesses 1915system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15741.969547 # average ReadReq miss latency 1916system.cpu1.dcache.ReadReq_avg_miss_latency::total 15741.969547 # average ReadReq miss latency 1917system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21951.134284 # average WriteReq miss latency 1918system.cpu1.dcache.WriteReq_avg_miss_latency::total 21951.134284 # average WriteReq miss latency 1919system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.217355 # average LoadLockedReq miss latency 1920system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.217355 # average LoadLockedReq miss latency 1921system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.708456 # average StoreCondReq miss latency 1922system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.708456 # average StoreCondReq miss latency |
| 1913system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1914system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1923system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1924system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1915system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19725.101627 # average overall miss latency 1916system.cpu1.dcache.demand_avg_miss_latency::total 19725.101627 # average overall miss latency 1917system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18808.809964 # average overall miss latency 1918system.cpu1.dcache.overall_avg_miss_latency::total 18808.809964 # average overall miss latency 1919system.cpu1.dcache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked 1920system.cpu1.dcache.blocked_cycles::no_targets 1112453 # number of cycles access was blocked 1921system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked 1922system.cpu1.dcache.blocked::no_targets 39616 # number of cycles access was blocked 1923system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.648649 # average number of cycles each access was blocked 1924system.cpu1.dcache.avg_blocked_cycles::no_targets 28.080902 # average number of cycles each access was blocked | 1925system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19746.582563 # average overall miss latency 1926system.cpu1.dcache.demand_avg_miss_latency::total 19746.582563 # average overall miss latency 1927system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18828.901612 # average overall miss latency 1928system.cpu1.dcache.overall_avg_miss_latency::total 18828.901612 # average overall miss latency 1929system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked 1930system.cpu1.dcache.blocked_cycles::no_targets 1116392 # number of cycles access was blocked 1931system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked 1932system.cpu1.dcache.blocked::no_targets 39638 # number of cycles access was blocked 1933system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked 1934system.cpu1.dcache.avg_blocked_cycles::no_targets 28.164690 # average number of cycles each access was blocked |
| 1925system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1926system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1935system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1936system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1927system.cpu1.dcache.writebacks::writebacks 117473 # number of writebacks 1928system.cpu1.dcache.writebacks::total 117473 # number of writebacks 1929system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79558 # number of ReadReq MSHR hits 1930system.cpu1.dcache.ReadReq_mshr_hits::total 79558 # number of ReadReq MSHR hits 1931system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306502 # number of WriteReq MSHR hits 1932system.cpu1.dcache.WriteReq_mshr_hits::total 306502 # number of WriteReq MSHR hits 1933system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits 1934system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits 1935system.cpu1.dcache.demand_mshr_hits::cpu1.data 386060 # number of demand (read+write) MSHR hits 1936system.cpu1.dcache.demand_mshr_hits::total 386060 # number of demand (read+write) MSHR hits 1937system.cpu1.dcache.overall_mshr_hits::cpu1.data 386060 # number of overall MSHR hits 1938system.cpu1.dcache.overall_mshr_hits::total 386060 # number of overall MSHR hits 1939system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139857 # number of ReadReq MSHR misses 1940system.cpu1.dcache.ReadReq_mshr_misses::total 139857 # number of ReadReq MSHR misses 1941system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91805 # number of WriteReq MSHR misses 1942system.cpu1.dcache.WriteReq_mshr_misses::total 91805 # number of WriteReq MSHR misses | 1937system.cpu1.dcache.writebacks::writebacks 117580 # number of writebacks 1938system.cpu1.dcache.writebacks::total 117580 # number of writebacks 1939system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79511 # number of ReadReq MSHR hits 1940system.cpu1.dcache.ReadReq_mshr_hits::total 79511 # number of ReadReq MSHR hits 1941system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306644 # number of WriteReq MSHR hits 1942system.cpu1.dcache.WriteReq_mshr_hits::total 306644 # number of WriteReq MSHR hits 1943system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13188 # number of LoadLockedReq MSHR hits 1944system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13188 # number of LoadLockedReq MSHR hits 1945system.cpu1.dcache.demand_mshr_hits::cpu1.data 386155 # number of demand (read+write) MSHR hits 1946system.cpu1.dcache.demand_mshr_hits::total 386155 # number of demand (read+write) MSHR hits 1947system.cpu1.dcache.overall_mshr_hits::cpu1.data 386155 # number of overall MSHR hits 1948system.cpu1.dcache.overall_mshr_hits::total 386155 # number of overall MSHR hits 1949system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139843 # number of ReadReq MSHR misses 1950system.cpu1.dcache.ReadReq_mshr_misses::total 139843 # number of ReadReq MSHR misses 1951system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91817 # number of WriteReq MSHR misses 1952system.cpu1.dcache.WriteReq_mshr_misses::total 91817 # number of WriteReq MSHR misses |
| 1943system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28628 # number of SoftPFReq MSHR misses 1944system.cpu1.dcache.SoftPFReq_mshr_misses::total 28628 # number of SoftPFReq MSHR misses | 1953system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28628 # number of SoftPFReq MSHR misses 1954system.cpu1.dcache.SoftPFReq_mshr_misses::total 28628 # number of SoftPFReq MSHR misses |
| 1945system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4934 # number of LoadLockedReq MSHR misses 1946system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4934 # number of LoadLockedReq MSHR misses 1947system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23394 # number of StoreCondReq MSHR misses 1948system.cpu1.dcache.StoreCondReq_mshr_misses::total 23394 # number of StoreCondReq MSHR misses 1949system.cpu1.dcache.demand_mshr_misses::cpu1.data 231662 # number of demand (read+write) MSHR misses 1950system.cpu1.dcache.demand_mshr_misses::total 231662 # number of demand (read+write) MSHR misses 1951system.cpu1.dcache.overall_mshr_misses::cpu1.data 260290 # number of overall MSHR misses 1952system.cpu1.dcache.overall_mshr_misses::total 260290 # number of overall MSHR misses 1953system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829354050 # number of ReadReq MSHR miss cycles 1954system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829354050 # number of ReadReq MSHR miss cycles 1955system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2195265722 # number of WriteReq MSHR miss cycles 1956system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2195265722 # number of WriteReq MSHR miss cycles 1957system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493416244 # number of SoftPFReq MSHR miss cycles 1958system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493416244 # number of SoftPFReq MSHR miss cycles 1959system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87143250 # number of LoadLockedReq MSHR miss cycles 1960system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87143250 # number of LoadLockedReq MSHR miss cycles 1961system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494733684 # number of StoreCondReq MSHR miss cycles 1962system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494733684 # number of StoreCondReq MSHR miss cycles 1963system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 482500 # number of StoreCondFailReq MSHR miss cycles 1964system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 482500 # number of StoreCondFailReq MSHR miss cycles 1965system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024619772 # number of demand (read+write) MSHR miss cycles 1966system.cpu1.dcache.demand_mshr_miss_latency::total 4024619772 # number of demand (read+write) MSHR miss cycles 1967system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518036016 # number of overall MSHR miss cycles 1968system.cpu1.dcache.overall_mshr_miss_latency::total 4518036016 # number of overall MSHR miss cycles 1969system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298838492 # number of ReadReq MSHR uncacheable cycles 1970system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298838492 # number of ReadReq MSHR uncacheable cycles 1971system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826630495 # number of WriteReq MSHR uncacheable cycles 1972system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826630495 # number of WriteReq MSHR uncacheable cycles 1973system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125468987 # number of overall MSHR uncacheable cycles 1974system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125468987 # number of overall MSHR uncacheable cycles 1975system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014280 # mshr miss rate for ReadReq accesses 1976system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014280 # mshr miss rate for ReadReq accesses 1977system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014552 # mshr miss rate for WriteReq accesses 1978system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014552 # mshr miss rate for WriteReq accesses 1979system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359350 # mshr miss rate for SoftPFReq accesses 1980system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359350 # mshr miss rate for SoftPFReq accesses 1981system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050727 # mshr miss rate for LoadLockedReq accesses 1982system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050727 # mshr miss rate for LoadLockedReq accesses 1983system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247831 # mshr miss rate for StoreCondReq accesses 1984system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247831 # mshr miss rate for StoreCondReq accesses | 1955system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4939 # number of LoadLockedReq MSHR misses 1956system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4939 # number of LoadLockedReq MSHR misses 1957system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23403 # number of StoreCondReq MSHR misses 1958system.cpu1.dcache.StoreCondReq_mshr_misses::total 23403 # number of StoreCondReq MSHR misses 1959system.cpu1.dcache.demand_mshr_misses::cpu1.data 231660 # number of demand (read+write) MSHR misses 1960system.cpu1.dcache.demand_mshr_misses::total 231660 # number of demand (read+write) MSHR misses 1961system.cpu1.dcache.overall_mshr_misses::cpu1.data 260288 # number of overall MSHR misses 1962system.cpu1.dcache.overall_mshr_misses::total 260288 # number of overall MSHR misses 1963system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827288064 # number of ReadReq MSHR miss cycles 1964system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827288064 # number of ReadReq MSHR miss cycles 1965system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2196971984 # number of WriteReq MSHR miss cycles 1966system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2196971984 # number of WriteReq MSHR miss cycles 1967system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494563997 # number of SoftPFReq MSHR miss cycles 1968system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494563997 # number of SoftPFReq MSHR miss cycles 1969system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87258999 # number of LoadLockedReq MSHR miss cycles 1970system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87258999 # number of LoadLockedReq MSHR miss cycles 1971system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494349701 # number of StoreCondReq MSHR miss cycles 1972system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494349701 # number of StoreCondReq MSHR miss cycles 1973system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 489000 # number of StoreCondFailReq MSHR miss cycles 1974system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 489000 # number of StoreCondFailReq MSHR miss cycles 1975system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024260048 # number of demand (read+write) MSHR miss cycles 1976system.cpu1.dcache.demand_mshr_miss_latency::total 4024260048 # number of demand (read+write) MSHR miss cycles 1977system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518824045 # number of overall MSHR miss cycles 1978system.cpu1.dcache.overall_mshr_miss_latency::total 4518824045 # number of overall MSHR miss cycles 1979system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298813494 # number of ReadReq MSHR uncacheable cycles 1980system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298813494 # number of ReadReq MSHR uncacheable cycles 1981system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826635494 # number of WriteReq MSHR uncacheable cycles 1982system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826635494 # number of WriteReq MSHR uncacheable cycles 1983system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125448988 # number of overall MSHR uncacheable cycles 1984system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125448988 # number of overall MSHR uncacheable cycles 1985system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses 1986system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses 1987system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014553 # mshr miss rate for WriteReq accesses 1988system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014553 # mshr miss rate for WriteReq accesses 1989system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359355 # mshr miss rate for SoftPFReq accesses 1990system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359355 # mshr miss rate for SoftPFReq accesses 1991system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050774 # mshr miss rate for LoadLockedReq accesses 1992system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050774 # mshr miss rate for LoadLockedReq accesses 1993system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247903 # mshr miss rate for StoreCondReq accesses 1994system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247903 # mshr miss rate for StoreCondReq accesses |
| 1985system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014386 # mshr miss rate for demand accesses 1986system.cpu1.dcache.demand_mshr_miss_rate::total 0.014386 # mshr miss rate for demand accesses | 1995system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014386 # mshr miss rate for demand accesses 1996system.cpu1.dcache.demand_mshr_miss_rate::total 0.014386 # mshr miss rate for demand accesses |
| 1987system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016085 # mshr miss rate for overall accesses 1988system.cpu1.dcache.overall_mshr_miss_rate::total 0.016085 # mshr miss rate for overall accesses 1989system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13080.175107 # average ReadReq mshr miss latency 1990system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13080.175107 # average ReadReq mshr miss latency 1991system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23912.267545 # average WriteReq mshr miss latency 1992system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23912.267545 # average WriteReq mshr miss latency 1993system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17235.442364 # average SoftPFReq mshr miss latency 1994system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17235.442364 # average SoftPFReq mshr miss latency 1995system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17661.785570 # average LoadLockedReq mshr miss latency 1996system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17661.785570 # average LoadLockedReq mshr miss latency 1997system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21147.887664 # average StoreCondReq mshr miss latency 1998system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21147.887664 # average StoreCondReq mshr miss latency | 1997system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016084 # mshr miss rate for overall accesses 1998system.cpu1.dcache.overall_mshr_miss_rate::total 0.016084 # mshr miss rate for overall accesses 1999system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13066.710983 # average ReadReq mshr miss latency 2000system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13066.710983 # average ReadReq mshr miss latency 2001system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23927.725628 # average WriteReq mshr miss latency 2002system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23927.725628 # average WriteReq mshr miss latency 2003system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17275.534337 # average SoftPFReq mshr miss latency 2004system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17275.534337 # average SoftPFReq mshr miss latency 2005system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17667.341365 # average LoadLockedReq mshr miss latency 2006system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17667.341365 # average LoadLockedReq mshr miss latency 2007system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21123.347477 # average StoreCondReq mshr miss latency 2008system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21123.347477 # average StoreCondReq mshr miss latency |
| 1999system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2000system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2009system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2010system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2001system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17372.809403 # average overall mshr miss latency 2002system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17372.809403 # average overall mshr miss latency 2003system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17357.701087 # average overall mshr miss latency 2004system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17357.701087 # average overall mshr miss latency | 2011system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17371.406579 # average overall mshr miss latency 2012system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17371.406579 # average overall mshr miss latency 2013system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17360.861987 # average overall mshr miss latency 2014system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17360.861987 # average overall mshr miss latency |
| 2005system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2006system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2007system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2008system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2009system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2010system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2011system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2015system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2016system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2017system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2018system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2019system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2020system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2021system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2012system.cpu1.icache.tags.replacements 607164 # number of replacements 2013system.cpu1.icache.tags.tagsinuse 499.524787 # Cycle average of tags in use 2014system.cpu1.icache.tags.total_refs 43017402 # Total number of references to valid blocks. 2015system.cpu1.icache.tags.sampled_refs 607676 # Sample count of references to valid blocks. 2016system.cpu1.icache.tags.avg_refs 70.790030 # Average number of references to valid blocks. | 2022system.cpu1.icache.tags.replacements 607210 # number of replacements 2023system.cpu1.icache.tags.tagsinuse 499.525690 # Cycle average of tags in use 2024system.cpu1.icache.tags.total_refs 43016771 # Total number of references to valid blocks. 2025system.cpu1.icache.tags.sampled_refs 607722 # Sample count of references to valid blocks. 2026system.cpu1.icache.tags.avg_refs 70.783633 # Average number of references to valid blocks. |
| 2017system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit. | 2027system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit. |
| 2018system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524787 # Average occupied blocks per requestor 2019system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy 2020system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy | 2028system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.525690 # Average occupied blocks per requestor 2029system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975636 # Average percentage of cache occupancy 2030system.cpu1.icache.tags.occ_percent::total 0.975636 # Average percentage of cache occupancy |
| 2021system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2022system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2023system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2024system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2031system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2032system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2033system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2034system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2025system.cpu1.icache.tags.tag_accesses 87891037 # Number of tag accesses 2026system.cpu1.icache.tags.data_accesses 87891037 # Number of data accesses 2027system.cpu1.icache.ReadReq_hits::cpu1.inst 43017402 # number of ReadReq hits 2028system.cpu1.icache.ReadReq_hits::total 43017402 # number of ReadReq hits 2029system.cpu1.icache.demand_hits::cpu1.inst 43017402 # number of demand (read+write) hits 2030system.cpu1.icache.demand_hits::total 43017402 # number of demand (read+write) hits 2031system.cpu1.icache.overall_hits::cpu1.inst 43017402 # number of overall hits 2032system.cpu1.icache.overall_hits::total 43017402 # number of overall hits 2033system.cpu1.icache.ReadReq_misses::cpu1.inst 624277 # number of ReadReq misses 2034system.cpu1.icache.ReadReq_misses::total 624277 # number of ReadReq misses 2035system.cpu1.icache.demand_misses::cpu1.inst 624277 # number of demand (read+write) misses 2036system.cpu1.icache.demand_misses::total 624277 # number of demand (read+write) misses 2037system.cpu1.icache.overall_misses::cpu1.inst 624277 # number of overall misses 2038system.cpu1.icache.overall_misses::total 624277 # number of overall misses 2039system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095487535 # number of ReadReq miss cycles 2040system.cpu1.icache.ReadReq_miss_latency::total 5095487535 # number of ReadReq miss cycles 2041system.cpu1.icache.demand_miss_latency::cpu1.inst 5095487535 # number of demand (read+write) miss cycles 2042system.cpu1.icache.demand_miss_latency::total 5095487535 # number of demand (read+write) miss cycles 2043system.cpu1.icache.overall_miss_latency::cpu1.inst 5095487535 # number of overall miss cycles 2044system.cpu1.icache.overall_miss_latency::total 5095487535 # number of overall miss cycles 2045system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641679 # number of ReadReq accesses(hits+misses) 2046system.cpu1.icache.ReadReq_accesses::total 43641679 # number of ReadReq accesses(hits+misses) 2047system.cpu1.icache.demand_accesses::cpu1.inst 43641679 # number of demand (read+write) accesses 2048system.cpu1.icache.demand_accesses::total 43641679 # number of demand (read+write) accesses 2049system.cpu1.icache.overall_accesses::cpu1.inst 43641679 # number of overall (read+write) accesses 2050system.cpu1.icache.overall_accesses::total 43641679 # number of overall (read+write) accesses 2051system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014305 # miss rate for ReadReq accesses 2052system.cpu1.icache.ReadReq_miss_rate::total 0.014305 # miss rate for ReadReq accesses 2053system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014305 # miss rate for demand accesses 2054system.cpu1.icache.demand_miss_rate::total 0.014305 # miss rate for demand accesses 2055system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014305 # miss rate for overall accesses 2056system.cpu1.icache.overall_miss_rate::total 0.014305 # miss rate for overall accesses 2057system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8162.222115 # average ReadReq miss latency 2058system.cpu1.icache.ReadReq_avg_miss_latency::total 8162.222115 # average ReadReq miss latency 2059system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8162.222115 # average overall miss latency 2060system.cpu1.icache.demand_avg_miss_latency::total 8162.222115 # average overall miss latency 2061system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8162.222115 # average overall miss latency 2062system.cpu1.icache.overall_avg_miss_latency::total 8162.222115 # average overall miss latency 2063system.cpu1.icache.blocked_cycles::no_mshrs 276500 # number of cycles access was blocked | 2035system.cpu1.icache.tags.tag_accesses 87889967 # Number of tag accesses 2036system.cpu1.icache.tags.data_accesses 87889967 # Number of data accesses 2037system.cpu1.icache.ReadReq_hits::cpu1.inst 43016771 # number of ReadReq hits 2038system.cpu1.icache.ReadReq_hits::total 43016771 # number of ReadReq hits 2039system.cpu1.icache.demand_hits::cpu1.inst 43016771 # number of demand (read+write) hits 2040system.cpu1.icache.demand_hits::total 43016771 # number of demand (read+write) hits 2041system.cpu1.icache.overall_hits::cpu1.inst 43016771 # number of overall hits 2042system.cpu1.icache.overall_hits::total 43016771 # number of overall hits 2043system.cpu1.icache.ReadReq_misses::cpu1.inst 624350 # number of ReadReq misses 2044system.cpu1.icache.ReadReq_misses::total 624350 # number of ReadReq misses 2045system.cpu1.icache.demand_misses::cpu1.inst 624350 # number of demand (read+write) misses 2046system.cpu1.icache.demand_misses::total 624350 # number of demand (read+write) misses 2047system.cpu1.icache.overall_misses::cpu1.inst 624350 # number of overall misses 2048system.cpu1.icache.overall_misses::total 624350 # number of overall misses 2049system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095278041 # number of ReadReq miss cycles 2050system.cpu1.icache.ReadReq_miss_latency::total 5095278041 # number of ReadReq miss cycles 2051system.cpu1.icache.demand_miss_latency::cpu1.inst 5095278041 # number of demand (read+write) miss cycles 2052system.cpu1.icache.demand_miss_latency::total 5095278041 # number of demand (read+write) miss cycles 2053system.cpu1.icache.overall_miss_latency::cpu1.inst 5095278041 # number of overall miss cycles 2054system.cpu1.icache.overall_miss_latency::total 5095278041 # number of overall miss cycles 2055system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641121 # number of ReadReq accesses(hits+misses) 2056system.cpu1.icache.ReadReq_accesses::total 43641121 # number of ReadReq accesses(hits+misses) 2057system.cpu1.icache.demand_accesses::cpu1.inst 43641121 # number of demand (read+write) accesses 2058system.cpu1.icache.demand_accesses::total 43641121 # number of demand (read+write) accesses 2059system.cpu1.icache.overall_accesses::cpu1.inst 43641121 # number of overall (read+write) accesses 2060system.cpu1.icache.overall_accesses::total 43641121 # number of overall (read+write) accesses 2061system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses 2062system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses 2063system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses 2064system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses 2065system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses 2066system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses 2067system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8160.932235 # average ReadReq miss latency 2068system.cpu1.icache.ReadReq_avg_miss_latency::total 8160.932235 # average ReadReq miss latency 2069system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8160.932235 # average overall miss latency 2070system.cpu1.icache.demand_avg_miss_latency::total 8160.932235 # average overall miss latency 2071system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8160.932235 # average overall miss latency 2072system.cpu1.icache.overall_avg_miss_latency::total 8160.932235 # average overall miss latency 2073system.cpu1.icache.blocked_cycles::no_mshrs 275120 # number of cycles access was blocked |
| 2064system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2074system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2065system.cpu1.icache.blocked::no_mshrs 36143 # number of cycles access was blocked | 2075system.cpu1.icache.blocked::no_mshrs 36110 # number of cycles access was blocked |
| 2066system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 2076system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 2067system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.650167 # average number of cycles each access was blocked | 2077system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.618942 # average number of cycles each access was blocked |
| 2068system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2069system.cpu1.icache.fast_writes 0 # number of fast writes performed 2070system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2078system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2079system.cpu1.icache.fast_writes 0 # number of fast writes performed 2080system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2071system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16598 # number of ReadReq MSHR hits 2072system.cpu1.icache.ReadReq_mshr_hits::total 16598 # number of ReadReq MSHR hits 2073system.cpu1.icache.demand_mshr_hits::cpu1.inst 16598 # number of demand (read+write) MSHR hits 2074system.cpu1.icache.demand_mshr_hits::total 16598 # number of demand (read+write) MSHR hits 2075system.cpu1.icache.overall_mshr_hits::cpu1.inst 16598 # number of overall MSHR hits 2076system.cpu1.icache.overall_mshr_hits::total 16598 # number of overall MSHR hits 2077system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607679 # number of ReadReq MSHR misses 2078system.cpu1.icache.ReadReq_mshr_misses::total 607679 # number of ReadReq MSHR misses 2079system.cpu1.icache.demand_mshr_misses::cpu1.inst 607679 # number of demand (read+write) MSHR misses 2080system.cpu1.icache.demand_mshr_misses::total 607679 # number of demand (read+write) MSHR misses 2081system.cpu1.icache.overall_mshr_misses::cpu1.inst 607679 # number of overall MSHR misses 2082system.cpu1.icache.overall_mshr_misses::total 607679 # number of overall MSHR misses 2083system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4104857215 # number of ReadReq MSHR miss cycles 2084system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104857215 # number of ReadReq MSHR miss cycles 2085system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104857215 # number of demand (read+write) MSHR miss cycles 2086system.cpu1.icache.demand_mshr_miss_latency::total 4104857215 # number of demand (read+write) MSHR miss cycles 2087system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104857215 # number of overall MSHR miss cycles 2088system.cpu1.icache.overall_mshr_miss_latency::total 4104857215 # number of overall MSHR miss cycles | 2081system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16625 # number of ReadReq MSHR hits 2082system.cpu1.icache.ReadReq_mshr_hits::total 16625 # number of ReadReq MSHR hits 2083system.cpu1.icache.demand_mshr_hits::cpu1.inst 16625 # number of demand (read+write) MSHR hits 2084system.cpu1.icache.demand_mshr_hits::total 16625 # number of demand (read+write) MSHR hits 2085system.cpu1.icache.overall_mshr_hits::cpu1.inst 16625 # number of overall MSHR hits 2086system.cpu1.icache.overall_mshr_hits::total 16625 # number of overall MSHR hits 2087system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607725 # number of ReadReq MSHR misses 2088system.cpu1.icache.ReadReq_mshr_misses::total 607725 # number of ReadReq MSHR misses 2089system.cpu1.icache.demand_mshr_misses::cpu1.inst 607725 # number of demand (read+write) MSHR misses 2090system.cpu1.icache.demand_mshr_misses::total 607725 # number of demand (read+write) MSHR misses 2091system.cpu1.icache.overall_mshr_misses::cpu1.inst 607725 # number of overall MSHR misses 2092system.cpu1.icache.overall_mshr_misses::total 607725 # number of overall MSHR misses 2093system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4103508232 # number of ReadReq MSHR miss cycles 2094system.cpu1.icache.ReadReq_mshr_miss_latency::total 4103508232 # number of ReadReq MSHR miss cycles 2095system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4103508232 # number of demand (read+write) MSHR miss cycles 2096system.cpu1.icache.demand_mshr_miss_latency::total 4103508232 # number of demand (read+write) MSHR miss cycles 2097system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4103508232 # number of overall MSHR miss cycles 2098system.cpu1.icache.overall_mshr_miss_latency::total 4103508232 # number of overall MSHR miss cycles |
| 2089system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles 2090system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles 2091system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles 2092system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles | 2099system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles 2100system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles 2101system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles 2102system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles |
| 2093system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for ReadReq accesses 2094system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013924 # mshr miss rate for ReadReq accesses 2095system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for demand accesses 2096system.cpu1.icache.demand_mshr_miss_rate::total 0.013924 # mshr miss rate for demand accesses 2097system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for overall accesses 2098system.cpu1.icache.overall_mshr_miss_rate::total 0.013924 # mshr miss rate for overall accesses 2099system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average ReadReq mshr miss latency 2100system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.976254 # average ReadReq mshr miss latency 2101system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average overall mshr miss latency 2102system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.976254 # average overall mshr miss latency 2103system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average overall mshr miss latency 2104system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.976254 # average overall mshr miss latency | 2103system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses 2104system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 2105system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses 2106system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 2107system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses 2108system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses 2109system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6752.245229 # average ReadReq mshr miss latency 2110system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6752.245229 # average ReadReq mshr miss latency 2111system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6752.245229 # average overall mshr miss latency 2112system.cpu1.icache.demand_avg_mshr_miss_latency::total 6752.245229 # average overall mshr miss latency 2113system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6752.245229 # average overall mshr miss latency 2114system.cpu1.icache.overall_avg_mshr_miss_latency::total 6752.245229 # average overall mshr miss latency |
| 2105system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2106system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2107system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2108system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2109system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2115system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2116system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2117system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2118system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2119system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2110system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841342 # number of hwpf identified 2111system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43201 # number of hwpf that were already in mshr 2112system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639993 # number of hwpf that were already in the cache 2113system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42894 # number of hwpf that were already in the prefetch queue | 2120system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841883 # number of hwpf identified 2121system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43038 # number of hwpf that were already in mshr 2122system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4641023 # number of hwpf that were already in the cache 2123system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42756 # number of hwpf that were already in the prefetch queue |
| 2114system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 2124system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 2115system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 5995 # number of hwpf removed because MSHR allocated 2116system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109259 # number of hwpf issued 2117system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564002 # number of hwpf spanning a virtual page | 2125system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 5990 # number of hwpf removed because MSHR allocated 2126system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109076 # number of hwpf issued 2127system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564189 # number of hwpf spanning a virtual page |
| 2118system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 2128system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 2119system.cpu1.l2cache.tags.replacements 85775 # number of replacements 2120system.cpu1.l2cache.tags.tagsinuse 15600.933964 # Cycle average of tags in use 2121system.cpu1.l2cache.tags.total_refs 846435 # Total number of references to valid blocks. 2122system.cpu1.l2cache.tags.sampled_refs 100895 # Sample count of references to valid blocks. 2123system.cpu1.l2cache.tags.avg_refs 8.389266 # Average number of references to valid blocks. | 2129system.cpu1.l2cache.tags.replacements 85682 # number of replacements 2130system.cpu1.l2cache.tags.tagsinuse 15604.887972 # Cycle average of tags in use 2131system.cpu1.l2cache.tags.total_refs 847212 # Total number of references to valid blocks. 2132system.cpu1.l2cache.tags.sampled_refs 100795 # Sample count of references to valid blocks. 2133system.cpu1.l2cache.tags.avg_refs 8.405298 # Average number of references to valid blocks. |
| 2124system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2134system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2125system.cpu1.l2cache.tags.occ_blocks::writebacks 5997.093337 # Average occupied blocks per requestor 2126system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.379548 # Average occupied blocks per requestor 2127system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.187782 # Average occupied blocks per requestor 2128system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 717.531946 # Average occupied blocks per requestor 2129system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1990.637648 # Average occupied blocks per requestor 2130system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.103702 # Average occupied blocks per requestor 2131system.cpu1.l2cache.tags.occ_percent::writebacks 0.366034 # Average percentage of cache occupancy 2132system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000634 # Average percentage of cache occupancy 2133system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000072 # Average percentage of cache occupancy 2134system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.043795 # Average percentage of cache occupancy 2135system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.121499 # Average percentage of cache occupancy 2136system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.420172 # Average percentage of cache occupancy 2137system.cpu1.l2cache.tags.occ_percent::total 0.952205 # Average percentage of cache occupancy | 2135system.cpu1.l2cache.tags.occ_blocks::writebacks 6001.492372 # Average occupied blocks per requestor 2136system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 7.158596 # Average occupied blocks per requestor 2137system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.882758 # Average occupied blocks per requestor 2138system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 688.413448 # Average occupied blocks per requestor 2139system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1964.460870 # Average occupied blocks per requestor 2140system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6940.479928 # Average occupied blocks per requestor 2141system.cpu1.l2cache.tags.occ_percent::writebacks 0.366302 # Average percentage of cache occupancy 2142system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000437 # Average percentage of cache occupancy 2143system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000176 # Average percentage of cache occupancy 2144system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.042017 # Average percentage of cache occupancy 2145system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.119901 # Average percentage of cache occupancy 2146system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.423613 # Average percentage of cache occupancy 2147system.cpu1.l2cache.tags.occ_percent::total 0.952447 # Average percentage of cache occupancy |
| 2138system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9541 # Occupied blocks per task id | 2148system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9541 # Occupied blocks per task id |
| 2139system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id 2140system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5554 # Occupied blocks per task id 2141system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 314 # Occupied blocks per task id 2142system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8089 # Occupied blocks per task id 2143system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1138 # Occupied blocks per task id | 2149system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id 2150system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5548 # Occupied blocks per task id 2151system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 308 # Occupied blocks per task id 2152system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8077 # Occupied blocks per task id 2153system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1156 # Occupied blocks per task id |
| 2144system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id | 2154system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id |
| 2145system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2146system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 2147system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id 2148system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4157 # Occupied blocks per task id 2149system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 969 # Occupied blocks per task id | 2155system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id 2156system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 2157system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id 2158system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4190 # Occupied blocks per task id 2159system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 941 # Occupied blocks per task id |
| 2150system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.582336 # Percentage of cache occupancy per task id | 2160system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.582336 # Percentage of cache occupancy per task id |
| 2151system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id 2152system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.338989 # Percentage of cache occupancy per task id 2153system.cpu1.l2cache.tags.tag_accesses 16876081 # Number of tag accesses 2154system.cpu1.l2cache.tags.data_accesses 16876081 # Number of data accesses 2155system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16270 # number of ReadReq hits 2156system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7392 # number of ReadReq hits 2157system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601743 # number of ReadReq hits 2158system.cpu1.l2cache.ReadReq_hits::cpu1.data 101269 # number of ReadReq hits 2159system.cpu1.l2cache.ReadReq_hits::total 726674 # number of ReadReq hits 2160system.cpu1.l2cache.Writeback_hits::writebacks 117472 # number of Writeback hits 2161system.cpu1.l2cache.Writeback_hits::total 117472 # number of Writeback hits 2162system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits 2163system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits 2164system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 802 # number of SCUpgradeReq hits 2165system.cpu1.l2cache.SCUpgradeReq_hits::total 802 # number of SCUpgradeReq hits 2166system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28891 # number of ReadExReq hits 2167system.cpu1.l2cache.ReadExReq_hits::total 28891 # number of ReadExReq hits 2168system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16270 # number of demand (read+write) hits 2169system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7392 # number of demand (read+write) hits 2170system.cpu1.l2cache.demand_hits::cpu1.inst 601743 # number of demand (read+write) hits 2171system.cpu1.l2cache.demand_hits::cpu1.data 130160 # number of demand (read+write) hits 2172system.cpu1.l2cache.demand_hits::total 755565 # number of demand (read+write) hits 2173system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16270 # number of overall hits 2174system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7392 # number of overall hits 2175system.cpu1.l2cache.overall_hits::cpu1.inst 601743 # number of overall hits 2176system.cpu1.l2cache.overall_hits::cpu1.data 130160 # number of overall hits 2177system.cpu1.l2cache.overall_hits::total 755565 # number of overall hits | 2161system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id 2162system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.338623 # Percentage of cache occupancy per task id 2163system.cpu1.l2cache.tags.tag_accesses 16881821 # Number of tag accesses 2164system.cpu1.l2cache.tags.data_accesses 16881821 # Number of data accesses 2165system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16379 # number of ReadReq hits 2166system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7476 # number of ReadReq hits 2167system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601754 # number of ReadReq hits 2168system.cpu1.l2cache.ReadReq_hits::cpu1.data 101261 # number of ReadReq hits 2169system.cpu1.l2cache.ReadReq_hits::total 726870 # number of ReadReq hits 2170system.cpu1.l2cache.Writeback_hits::writebacks 117580 # number of Writeback hits 2171system.cpu1.l2cache.Writeback_hits::total 117580 # number of Writeback hits 2172system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2286 # number of UpgradeReq hits 2173system.cpu1.l2cache.UpgradeReq_hits::total 2286 # number of UpgradeReq hits 2174system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 847 # number of SCUpgradeReq hits 2175system.cpu1.l2cache.SCUpgradeReq_hits::total 847 # number of SCUpgradeReq hits 2176system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28888 # number of ReadExReq hits 2177system.cpu1.l2cache.ReadExReq_hits::total 28888 # number of ReadExReq hits 2178system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16379 # number of demand (read+write) hits 2179system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7476 # number of demand (read+write) hits 2180system.cpu1.l2cache.demand_hits::cpu1.inst 601754 # number of demand (read+write) hits 2181system.cpu1.l2cache.demand_hits::cpu1.data 130149 # number of demand (read+write) hits 2182system.cpu1.l2cache.demand_hits::total 755758 # number of demand (read+write) hits 2183system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16379 # number of overall hits 2184system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7476 # number of overall hits 2185system.cpu1.l2cache.overall_hits::cpu1.inst 601754 # number of overall hits 2186system.cpu1.l2cache.overall_hits::cpu1.data 130149 # number of overall hits 2187system.cpu1.l2cache.overall_hits::total 755758 # number of overall hits |
| 2178system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 463 # number of ReadReq misses 2179system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses | 2188system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 463 # number of ReadReq misses 2189system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses |
| 2180system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5933 # number of ReadReq misses 2181system.cpu1.l2cache.ReadReq_misses::cpu1.data 72130 # number of ReadReq misses 2182system.cpu1.l2cache.ReadReq_misses::total 78803 # number of ReadReq misses 2183system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28401 # number of UpgradeReq misses 2184system.cpu1.l2cache.UpgradeReq_misses::total 28401 # number of UpgradeReq misses 2185system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22590 # number of SCUpgradeReq misses 2186system.cpu1.l2cache.SCUpgradeReq_misses::total 22590 # number of SCUpgradeReq misses 2187system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2188system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 2189system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32934 # number of ReadExReq misses 2190system.cpu1.l2cache.ReadExReq_misses::total 32934 # number of ReadExReq misses | 2190system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5968 # number of ReadReq misses 2191system.cpu1.l2cache.ReadReq_misses::cpu1.data 72129 # number of ReadReq misses 2192system.cpu1.l2cache.ReadReq_misses::total 78837 # number of ReadReq misses 2193system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28394 # number of UpgradeReq misses 2194system.cpu1.l2cache.UpgradeReq_misses::total 28394 # number of UpgradeReq misses 2195system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22555 # number of SCUpgradeReq misses 2196system.cpu1.l2cache.SCUpgradeReq_misses::total 22555 # number of SCUpgradeReq misses 2197system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 2198system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 2199system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32933 # number of ReadExReq misses 2200system.cpu1.l2cache.ReadExReq_misses::total 32933 # number of ReadExReq misses |
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| 2193system.cpu1.l2cache.demand_misses::cpu1.inst 5933 # number of demand (read+write) misses 2194system.cpu1.l2cache.demand_misses::cpu1.data 105064 # number of demand (read+write) misses 2195system.cpu1.l2cache.demand_misses::total 111737 # number of demand (read+write) misses | 2203system.cpu1.l2cache.demand_misses::cpu1.inst 5968 # number of demand (read+write) misses 2204system.cpu1.l2cache.demand_misses::cpu1.data 105062 # number of demand (read+write) misses 2205system.cpu1.l2cache.demand_misses::total 111770 # number of demand (read+write) misses |
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| 2198system.cpu1.l2cache.overall_misses::cpu1.inst 5933 # number of overall misses 2199system.cpu1.l2cache.overall_misses::cpu1.data 105064 # number of overall misses 2200system.cpu1.l2cache.overall_misses::total 111737 # number of overall misses 2201system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10189999 # number of ReadReq miss cycles 2202system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5582499 # number of ReadReq miss cycles 2203system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 184105701 # number of ReadReq miss cycles 2204system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612613119 # number of ReadReq miss cycles 2205system.cpu1.l2cache.ReadReq_miss_latency::total 1812491318 # number of ReadReq miss cycles 2206system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537520391 # number of UpgradeReq miss cycles 2207system.cpu1.l2cache.UpgradeReq_miss_latency::total 537520391 # number of UpgradeReq miss cycles 2208system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 443077527 # number of SCUpgradeReq miss cycles 2209system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443077527 # number of SCUpgradeReq miss cycles 2210system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 471499 # number of SCUpgradeFailReq miss cycles 2211system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 471499 # number of SCUpgradeFailReq miss cycles 2212system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1278985047 # number of ReadExReq miss cycles 2213system.cpu1.l2cache.ReadExReq_miss_latency::total 1278985047 # number of ReadExReq miss cycles 2214system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10189999 # number of demand (read+write) miss cycles 2215system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5582499 # number of demand (read+write) miss cycles 2216system.cpu1.l2cache.demand_miss_latency::cpu1.inst 184105701 # number of demand (read+write) miss cycles 2217system.cpu1.l2cache.demand_miss_latency::cpu1.data 2891598166 # number of demand (read+write) miss cycles 2218system.cpu1.l2cache.demand_miss_latency::total 3091476365 # number of demand (read+write) miss cycles 2219system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10189999 # number of overall miss cycles 2220system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5582499 # number of overall miss cycles 2221system.cpu1.l2cache.overall_miss_latency::cpu1.inst 184105701 # number of overall miss cycles 2222system.cpu1.l2cache.overall_miss_latency::cpu1.data 2891598166 # number of overall miss cycles 2223system.cpu1.l2cache.overall_miss_latency::total 3091476365 # number of overall miss cycles 2224system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16733 # number of ReadReq accesses(hits+misses) 2225system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7669 # number of ReadReq accesses(hits+misses) 2226system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607676 # number of ReadReq accesses(hits+misses) 2227system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173399 # number of ReadReq accesses(hits+misses) 2228system.cpu1.l2cache.ReadReq_accesses::total 805477 # number of ReadReq accesses(hits+misses) 2229system.cpu1.l2cache.Writeback_accesses::writebacks 117472 # number of Writeback accesses(hits+misses) 2230system.cpu1.l2cache.Writeback_accesses::total 117472 # number of Writeback accesses(hits+misses) 2231system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30662 # number of UpgradeReq accesses(hits+misses) 2232system.cpu1.l2cache.UpgradeReq_accesses::total 30662 # number of UpgradeReq accesses(hits+misses) 2233system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23392 # number of SCUpgradeReq accesses(hits+misses) 2234system.cpu1.l2cache.SCUpgradeReq_accesses::total 23392 # number of SCUpgradeReq accesses(hits+misses) 2235system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2236system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 2237system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61825 # number of ReadExReq accesses(hits+misses) 2238system.cpu1.l2cache.ReadExReq_accesses::total 61825 # number of ReadExReq accesses(hits+misses) 2239system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16733 # number of demand (read+write) accesses 2240system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7669 # number of demand (read+write) accesses 2241system.cpu1.l2cache.demand_accesses::cpu1.inst 607676 # number of demand (read+write) accesses 2242system.cpu1.l2cache.demand_accesses::cpu1.data 235224 # number of demand (read+write) accesses 2243system.cpu1.l2cache.demand_accesses::total 867302 # number of demand (read+write) accesses 2244system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16733 # number of overall (read+write) accesses 2245system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7669 # number of overall (read+write) accesses 2246system.cpu1.l2cache.overall_accesses::cpu1.inst 607676 # number of overall (read+write) accesses 2247system.cpu1.l2cache.overall_accesses::cpu1.data 235224 # number of overall (read+write) accesses 2248system.cpu1.l2cache.overall_accesses::total 867302 # number of overall (read+write) accesses 2249system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.027670 # miss rate for ReadReq accesses 2250system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036119 # miss rate for ReadReq accesses 2251system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009763 # miss rate for ReadReq accesses 2252system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415977 # miss rate for ReadReq accesses 2253system.cpu1.l2cache.ReadReq_miss_rate::total 0.097834 # miss rate for ReadReq accesses 2254system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926261 # miss rate for UpgradeReq accesses 2255system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926261 # miss rate for UpgradeReq accesses 2256system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.965715 # miss rate for SCUpgradeReq accesses 2257system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.965715 # miss rate for SCUpgradeReq accesses | 2208system.cpu1.l2cache.overall_misses::cpu1.inst 5968 # number of overall misses 2209system.cpu1.l2cache.overall_misses::cpu1.data 105062 # number of overall misses 2210system.cpu1.l2cache.overall_misses::total 111770 # number of overall misses 2211system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10162748 # number of ReadReq miss cycles 2212system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5804000 # number of ReadReq miss cycles 2213system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 182703951 # number of ReadReq miss cycles 2214system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1611916890 # number of ReadReq miss cycles 2215system.cpu1.l2cache.ReadReq_miss_latency::total 1810587589 # number of ReadReq miss cycles 2216system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537388904 # number of UpgradeReq miss cycles 2217system.cpu1.l2cache.UpgradeReq_miss_latency::total 537388904 # number of UpgradeReq miss cycles 2218system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442240538 # number of SCUpgradeReq miss cycles 2219system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442240538 # number of SCUpgradeReq miss cycles 2220system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 477999 # number of SCUpgradeFailReq miss cycles 2221system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 477999 # number of SCUpgradeFailReq miss cycles 2222system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1281441808 # number of ReadExReq miss cycles 2223system.cpu1.l2cache.ReadExReq_miss_latency::total 1281441808 # number of ReadExReq miss cycles 2224system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10162748 # number of demand (read+write) miss cycles 2225system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5804000 # number of demand (read+write) miss cycles 2226system.cpu1.l2cache.demand_miss_latency::cpu1.inst 182703951 # number of demand (read+write) miss cycles 2227system.cpu1.l2cache.demand_miss_latency::cpu1.data 2893358698 # number of demand (read+write) miss cycles 2228system.cpu1.l2cache.demand_miss_latency::total 3092029397 # number of demand (read+write) miss cycles 2229system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10162748 # number of overall miss cycles 2230system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5804000 # number of overall miss cycles 2231system.cpu1.l2cache.overall_miss_latency::cpu1.inst 182703951 # number of overall miss cycles 2232system.cpu1.l2cache.overall_miss_latency::cpu1.data 2893358698 # number of overall miss cycles 2233system.cpu1.l2cache.overall_miss_latency::total 3092029397 # number of overall miss cycles 2234system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16842 # number of ReadReq accesses(hits+misses) 2235system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7753 # number of ReadReq accesses(hits+misses) 2236system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607722 # number of ReadReq accesses(hits+misses) 2237system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173390 # number of ReadReq accesses(hits+misses) 2238system.cpu1.l2cache.ReadReq_accesses::total 805707 # number of ReadReq accesses(hits+misses) 2239system.cpu1.l2cache.Writeback_accesses::writebacks 117580 # number of Writeback accesses(hits+misses) 2240system.cpu1.l2cache.Writeback_accesses::total 117580 # number of Writeback accesses(hits+misses) 2241system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30680 # number of UpgradeReq accesses(hits+misses) 2242system.cpu1.l2cache.UpgradeReq_accesses::total 30680 # number of UpgradeReq accesses(hits+misses) 2243system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23402 # number of SCUpgradeReq accesses(hits+misses) 2244system.cpu1.l2cache.SCUpgradeReq_accesses::total 23402 # number of SCUpgradeReq accesses(hits+misses) 2245system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2246system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2247system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61821 # number of ReadExReq accesses(hits+misses) 2248system.cpu1.l2cache.ReadExReq_accesses::total 61821 # number of ReadExReq accesses(hits+misses) 2249system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16842 # number of demand (read+write) accesses 2250system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7753 # number of demand (read+write) accesses 2251system.cpu1.l2cache.demand_accesses::cpu1.inst 607722 # number of demand (read+write) accesses 2252system.cpu1.l2cache.demand_accesses::cpu1.data 235211 # number of demand (read+write) accesses 2253system.cpu1.l2cache.demand_accesses::total 867528 # number of demand (read+write) accesses 2254system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16842 # number of overall (read+write) accesses 2255system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7753 # number of overall (read+write) accesses 2256system.cpu1.l2cache.overall_accesses::cpu1.inst 607722 # number of overall (read+write) accesses 2257system.cpu1.l2cache.overall_accesses::cpu1.data 235211 # number of overall (read+write) accesses 2258system.cpu1.l2cache.overall_accesses::total 867528 # number of overall (read+write) accesses 2259system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.027491 # miss rate for ReadReq accesses 2260system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035728 # miss rate for ReadReq accesses 2261system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009820 # miss rate for ReadReq accesses 2262system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415993 # miss rate for ReadReq accesses 2263system.cpu1.l2cache.ReadReq_miss_rate::total 0.097848 # miss rate for ReadReq accesses 2264system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.925489 # miss rate for UpgradeReq accesses 2265system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.925489 # miss rate for UpgradeReq accesses 2266system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.963807 # miss rate for SCUpgradeReq accesses 2267system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.963807 # miss rate for SCUpgradeReq accesses |
| 2258system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2259system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2268system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2269system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2260system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532697 # miss rate for ReadExReq accesses 2261system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532697 # miss rate for ReadExReq accesses 2262system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.027670 # miss rate for demand accesses 2263system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036119 # miss rate for demand accesses 2264system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009763 # miss rate for demand accesses 2265system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446655 # miss rate for demand accesses 2266system.cpu1.l2cache.demand_miss_rate::total 0.128833 # miss rate for demand accesses 2267system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.027670 # miss rate for overall accesses 2268system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036119 # miss rate for overall accesses 2269system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009763 # miss rate for overall accesses 2270system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446655 # miss rate for overall accesses 2271system.cpu1.l2cache.overall_miss_rate::total 0.128833 # miss rate for overall accesses 2272system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22008.637149 # average ReadReq miss latency 2273system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20153.425993 # average ReadReq miss latency 2274system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31030.794033 # average ReadReq miss latency 2275system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22357.037557 # average ReadReq miss latency 2276system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23000.283213 # average ReadReq miss latency 2277system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18926.107919 # average UpgradeReq miss latency 2278system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18926.107919 # average UpgradeReq miss latency 2279system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19613.879017 # average SCUpgradeReq miss latency 2280system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19613.879017 # average SCUpgradeReq miss latency 2281system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 235749.500000 # average SCUpgradeFailReq miss latency 2282system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 235749.500000 # average SCUpgradeFailReq miss latency 2283system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38834.792221 # average ReadExReq miss latency 2284system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38834.792221 # average ReadExReq miss latency 2285system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.637149 # average overall miss latency 2286system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20153.425993 # average overall miss latency 2287system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31030.794033 # average overall miss latency 2288system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27522.254683 # average overall miss latency 2289system.cpu1.l2cache.demand_avg_miss_latency::total 27667.436615 # average overall miss latency 2290system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22008.637149 # average overall miss latency 2291system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20153.425993 # average overall miss latency 2292system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31030.794033 # average overall miss latency 2293system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27522.254683 # average overall miss latency 2294system.cpu1.l2cache.overall_avg_miss_latency::total 27667.436615 # average overall miss latency 2295system.cpu1.l2cache.blocked_cycles::no_mshrs 22985 # number of cycles access was blocked | 2270system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532715 # miss rate for ReadExReq accesses 2271system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532715 # miss rate for ReadExReq accesses 2272system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.027491 # miss rate for demand accesses 2273system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035728 # miss rate for demand accesses 2274system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009820 # miss rate for demand accesses 2275system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446671 # miss rate for demand accesses 2276system.cpu1.l2cache.demand_miss_rate::total 0.128837 # miss rate for demand accesses 2277system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.027491 # miss rate for overall accesses 2278system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035728 # miss rate for overall accesses 2279system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009820 # miss rate for overall accesses 2280system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446671 # miss rate for overall accesses 2281system.cpu1.l2cache.overall_miss_rate::total 0.128837 # miss rate for overall accesses 2282system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21949.779698 # average ReadReq miss latency 2283system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20953.068592 # average ReadReq miss latency 2284system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30613.932808 # average ReadReq miss latency 2285system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22347.694963 # average ReadReq miss latency 2286system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22966.216231 # average ReadReq miss latency 2287system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18926.142988 # average UpgradeReq miss latency 2288system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18926.142988 # average UpgradeReq miss latency 2289system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19607.206296 # average SCUpgradeReq miss latency 2290system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19607.206296 # average SCUpgradeReq miss latency 2291system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 477999 # average SCUpgradeFailReq miss latency 2292system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 477999 # average SCUpgradeFailReq miss latency 2293system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38910.570188 # average ReadExReq miss latency 2294system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38910.570188 # average ReadExReq miss latency 2295system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21949.779698 # average overall miss latency 2296system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20953.068592 # average overall miss latency 2297system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30613.932808 # average overall miss latency 2298system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27539.535684 # average overall miss latency 2299system.cpu1.l2cache.demand_avg_miss_latency::total 27664.215773 # average overall miss latency 2300system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21949.779698 # average overall miss latency 2301system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20953.068592 # average overall miss latency 2302system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30613.932808 # average overall miss latency 2303system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27539.535684 # average overall miss latency 2304system.cpu1.l2cache.overall_avg_miss_latency::total 27664.215773 # average overall miss latency 2305system.cpu1.l2cache.blocked_cycles::no_mshrs 21207 # number of cycles access was blocked |
| 2296system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2306system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2297system.cpu1.l2cache.blocked::no_mshrs 493 # number of cycles access was blocked | 2307system.cpu1.l2cache.blocked::no_mshrs 485 # number of cycles access was blocked |
| 2298system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2308system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2299system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.622718 # average number of cycles each access was blocked | 2309system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 43.725773 # average number of cycles each access was blocked |
| 2300system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2301system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2302system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2310system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2311system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2312system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2303system.cpu1.l2cache.writebacks::writebacks 40759 # number of writebacks 2304system.cpu1.l2cache.writebacks::total 40759 # number of writebacks 2305system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits 2306system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1321 # number of ReadReq MSHR hits 2307system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 73 # number of ReadReq MSHR hits 2308system.cpu1.l2cache.ReadReq_mshr_hits::total 1407 # number of ReadReq MSHR hits 2309system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1252 # number of ReadExReq MSHR hits 2310system.cpu1.l2cache.ReadExReq_mshr_hits::total 1252 # number of ReadExReq MSHR hits 2311system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits 2312system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1321 # number of demand (read+write) MSHR hits 2313system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1325 # number of demand (read+write) MSHR hits 2314system.cpu1.l2cache.demand_mshr_hits::total 2659 # number of demand (read+write) MSHR hits 2315system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits 2316system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1321 # number of overall MSHR hits 2317system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1325 # number of overall MSHR hits 2318system.cpu1.l2cache.overall_mshr_hits::total 2659 # number of overall MSHR hits | 2313system.cpu1.l2cache.writebacks::writebacks 40787 # number of writebacks 2314system.cpu1.l2cache.writebacks::total 40787 # number of writebacks 2315system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits 2316system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1333 # number of ReadReq MSHR hits 2317system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 75 # number of ReadReq MSHR hits 2318system.cpu1.l2cache.ReadReq_mshr_hits::total 1422 # number of ReadReq MSHR hits 2319system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1248 # number of ReadExReq MSHR hits 2320system.cpu1.l2cache.ReadExReq_mshr_hits::total 1248 # number of ReadExReq MSHR hits 2321system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits 2322system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1333 # number of demand (read+write) MSHR hits 2323system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1323 # number of demand (read+write) MSHR hits 2324system.cpu1.l2cache.demand_mshr_hits::total 2670 # number of demand (read+write) MSHR hits 2325system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits 2326system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1333 # number of overall MSHR hits 2327system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1323 # number of overall MSHR hits 2328system.cpu1.l2cache.overall_mshr_hits::total 2670 # number of overall MSHR hits |
| 2319system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 463 # number of ReadReq MSHR misses | 2329system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 463 # number of ReadReq MSHR misses |
| 2320system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 264 # number of ReadReq MSHR misses 2321system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4612 # number of ReadReq MSHR misses 2322system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72057 # number of ReadReq MSHR misses 2323system.cpu1.l2cache.ReadReq_mshr_misses::total 77396 # number of ReadReq MSHR misses 2324system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109257 # number of HardPFReq MSHR misses 2325system.cpu1.l2cache.HardPFReq_mshr_misses::total 109257 # number of HardPFReq MSHR misses 2326system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28401 # number of UpgradeReq MSHR misses 2327system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28401 # number of UpgradeReq MSHR misses 2328system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22590 # number of SCUpgradeReq MSHR misses 2329system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22590 # number of SCUpgradeReq MSHR misses 2330system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2331system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2332system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31682 # number of ReadExReq MSHR misses 2333system.cpu1.l2cache.ReadExReq_mshr_misses::total 31682 # number of ReadExReq MSHR misses | 2330system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 263 # number of ReadReq MSHR misses 2331system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4635 # number of ReadReq MSHR misses 2332system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72054 # number of ReadReq MSHR misses 2333system.cpu1.l2cache.ReadReq_mshr_misses::total 77415 # number of ReadReq MSHR misses 2334system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109072 # number of HardPFReq MSHR misses 2335system.cpu1.l2cache.HardPFReq_mshr_misses::total 109072 # number of HardPFReq MSHR misses 2336system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28394 # number of UpgradeReq MSHR misses 2337system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28394 # number of UpgradeReq MSHR misses 2338system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22555 # number of SCUpgradeReq MSHR misses 2339system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22555 # number of SCUpgradeReq MSHR misses 2340system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2341system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2342system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31685 # number of ReadExReq MSHR misses 2343system.cpu1.l2cache.ReadExReq_mshr_misses::total 31685 # number of ReadExReq MSHR misses |
| 2334system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 463 # number of demand (read+write) MSHR misses | 2344system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 463 # number of demand (read+write) MSHR misses |
| 2335system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 264 # number of demand (read+write) MSHR misses 2336system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4612 # number of demand (read+write) MSHR misses | 2345system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 263 # number of demand (read+write) MSHR misses 2346system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4635 # number of demand (read+write) MSHR misses |
| 2337system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103739 # number of demand (read+write) MSHR misses | 2347system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103739 # number of demand (read+write) MSHR misses |
| 2338system.cpu1.l2cache.demand_mshr_misses::total 109078 # number of demand (read+write) MSHR misses | 2348system.cpu1.l2cache.demand_mshr_misses::total 109100 # number of demand (read+write) MSHR misses |
| 2339system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 463 # number of overall MSHR misses | 2349system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 463 # number of overall MSHR misses |
| 2340system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 264 # number of overall MSHR misses 2341system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4612 # number of overall MSHR misses | 2350system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 263 # number of overall MSHR misses 2351system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4635 # number of overall MSHR misses |
| 2342system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103739 # number of overall MSHR misses | 2352system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103739 # number of overall MSHR misses |
| 2343system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109257 # number of overall MSHR misses 2344system.cpu1.l2cache.overall_mshr_misses::total 218335 # number of overall MSHR misses 2345system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6946001 # number of ReadReq MSHR miss cycles 2346system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3570001 # number of ReadReq MSHR miss cycles 2347system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 126408787 # number of ReadReq MSHR miss cycles 2348system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1106793437 # number of ReadReq MSHR miss cycles 2349system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1243718226 # number of ReadReq MSHR miss cycles 2350system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3470833266 # number of HardPFReq MSHR miss cycles 2351system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3470833266 # number of HardPFReq MSHR miss cycles 2352system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417527555 # number of UpgradeReq MSHR miss cycles 2353system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417527555 # number of UpgradeReq MSHR miss cycles 2354system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308789786 # number of SCUpgradeReq MSHR miss cycles 2355system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308789786 # number of SCUpgradeReq MSHR miss cycles 2356system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 394499 # number of SCUpgradeFailReq MSHR miss cycles 2357system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 394499 # number of SCUpgradeFailReq MSHR miss cycles 2358system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 943695401 # number of ReadExReq MSHR miss cycles 2359system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 943695401 # number of ReadExReq MSHR miss cycles 2360system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6946001 # number of demand (read+write) MSHR miss cycles 2361system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3570001 # number of demand (read+write) MSHR miss cycles 2362system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 126408787 # number of demand (read+write) MSHR miss cycles 2363system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2050488838 # number of demand (read+write) MSHR miss cycles 2364system.cpu1.l2cache.demand_mshr_miss_latency::total 2187413627 # number of demand (read+write) MSHR miss cycles 2365system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6946001 # number of overall MSHR miss cycles 2366system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3570001 # number of overall MSHR miss cycles 2367system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 126408787 # number of overall MSHR miss cycles 2368system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2050488838 # number of overall MSHR miss cycles 2369system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3470833266 # number of overall MSHR miss cycles 2370system.cpu1.l2cache.overall_mshr_miss_latency::total 5658246893 # number of overall MSHR miss cycles | 2353system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109072 # number of overall MSHR misses 2354system.cpu1.l2cache.overall_mshr_misses::total 218172 # number of overall MSHR misses 2355system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6919250 # number of ReadReq MSHR miss cycles 2356system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3788000 # number of ReadReq MSHR miss cycles 2357system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 124690282 # number of ReadReq MSHR miss cycles 2358system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1106071688 # number of ReadReq MSHR miss cycles 2359system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1241469220 # number of ReadReq MSHR miss cycles 2360system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3463800362 # number of HardPFReq MSHR miss cycles 2361system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3463800362 # number of HardPFReq MSHR miss cycles 2362system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417384045 # number of UpgradeReq MSHR miss cycles 2363system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417384045 # number of UpgradeReq MSHR miss cycles 2364system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308383273 # number of SCUpgradeReq MSHR miss cycles 2365system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308383273 # number of SCUpgradeReq MSHR miss cycles 2366system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 400999 # number of SCUpgradeFailReq MSHR miss cycles 2367system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 400999 # number of SCUpgradeFailReq MSHR miss cycles 2368system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 945118400 # number of ReadExReq MSHR miss cycles 2369system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 945118400 # number of ReadExReq MSHR miss cycles 2370system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6919250 # number of demand (read+write) MSHR miss cycles 2371system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3788000 # number of demand (read+write) MSHR miss cycles 2372system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 124690282 # number of demand (read+write) MSHR miss cycles 2373system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2051190088 # number of demand (read+write) MSHR miss cycles 2374system.cpu1.l2cache.demand_mshr_miss_latency::total 2186587620 # number of demand (read+write) MSHR miss cycles 2375system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6919250 # number of overall MSHR miss cycles 2376system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3788000 # number of overall MSHR miss cycles 2377system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 124690282 # number of overall MSHR miss cycles 2378system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2051190088 # number of overall MSHR miss cycles 2379system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3463800362 # number of overall MSHR miss cycles 2380system.cpu1.l2cache.overall_mshr_miss_latency::total 5650387982 # number of overall MSHR miss cycles |
| 2371system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles | 2381system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles |
| 2372system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182197007 # number of ReadReq MSHR uncacheable cycles 2373system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189537757 # number of ReadReq MSHR uncacheable cycles 2374system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737457999 # number of WriteReq MSHR uncacheable cycles 2375system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737457999 # number of WriteReq MSHR uncacheable cycles | 2382system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182174505 # number of ReadReq MSHR uncacheable cycles 2383system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189515255 # number of ReadReq MSHR uncacheable cycles 2384system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737462500 # number of WriteReq MSHR uncacheable cycles 2385system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737462500 # number of WriteReq MSHR uncacheable cycles |
| 2376system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles | 2386system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles |
| 2377system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919655006 # number of overall MSHR uncacheable cycles 2378system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926995756 # number of overall MSHR uncacheable cycles 2379system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for ReadReq accesses 2380system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for ReadReq accesses 2381system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for ReadReq accesses 2382system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415556 # mshr miss rate for ReadReq accesses 2383system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096087 # mshr miss rate for ReadReq accesses | 2387system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919637005 # number of overall MSHR uncacheable cycles 2388system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926977755 # number of overall MSHR uncacheable cycles 2389system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027491 # mshr miss rate for ReadReq accesses 2390system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.033922 # mshr miss rate for ReadReq accesses 2391system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007627 # mshr miss rate for ReadReq accesses 2392system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415560 # mshr miss rate for ReadReq accesses 2393system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096083 # mshr miss rate for ReadReq accesses |
| 2384system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2385system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2394system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2395system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2386system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926261 # mshr miss rate for UpgradeReq accesses 2387system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926261 # mshr miss rate for UpgradeReq accesses 2388system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.965715 # mshr miss rate for SCUpgradeReq accesses 2389system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.965715 # mshr miss rate for SCUpgradeReq accesses | 2396system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.925489 # mshr miss rate for UpgradeReq accesses 2397system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.925489 # mshr miss rate for UpgradeReq accesses 2398system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.963807 # mshr miss rate for SCUpgradeReq accesses 2399system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.963807 # mshr miss rate for SCUpgradeReq accesses |
| 2390system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2391system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2400system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2401system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2392system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512446 # mshr miss rate for ReadExReq accesses 2393system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512446 # mshr miss rate for ReadExReq accesses 2394system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for demand accesses 2395system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for demand accesses 2396system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for demand accesses 2397system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.441022 # mshr miss rate for demand accesses 2398system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125767 # mshr miss rate for demand accesses 2399system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for overall accesses 2400system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for overall accesses 2401system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for overall accesses 2402system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.441022 # mshr miss rate for overall accesses | 2402system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512528 # mshr miss rate for ReadExReq accesses 2403system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512528 # mshr miss rate for ReadExReq accesses 2404system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027491 # mshr miss rate for demand accesses 2405system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.033922 # mshr miss rate for demand accesses 2406system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007627 # mshr miss rate for demand accesses 2407system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.441047 # mshr miss rate for demand accesses 2408system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125760 # mshr miss rate for demand accesses 2409system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027491 # mshr miss rate for overall accesses 2410system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033922 # mshr miss rate for overall accesses 2411system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007627 # mshr miss rate for overall accesses 2412system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.441047 # mshr miss rate for overall accesses |
| 2403system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2413system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2404system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251740 # mshr miss rate for overall accesses 2405system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average ReadReq mshr miss latency 2406system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average ReadReq mshr miss latency 2407system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average ReadReq mshr miss latency 2408system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15359.971092 # average ReadReq mshr miss latency 2409system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16069.541397 # average ReadReq mshr miss latency 2410system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average HardPFReq mshr miss latency 2411system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31767.605426 # average HardPFReq mshr miss latency 2412system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14701.156825 # average UpgradeReq mshr miss latency 2413system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14701.156825 # average UpgradeReq mshr miss latency 2414system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.313236 # average SCUpgradeReq mshr miss latency 2415system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.313236 # average SCUpgradeReq mshr miss latency 2416system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 197249.500000 # average SCUpgradeFailReq mshr miss latency 2417system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 197249.500000 # average SCUpgradeFailReq mshr miss latency 2418system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29786.484471 # average ReadExReq mshr miss latency 2419system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29786.484471 # average ReadExReq mshr miss latency 2420system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency 2421system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency 2422system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency 2423system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency 2424system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20053.664598 # average overall mshr miss latency 2425system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency 2426system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency 2427system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency 2428system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency 2429system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average overall mshr miss latency 2430system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25915.436797 # average overall mshr miss latency | 2414system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251487 # mshr miss rate for overall accesses 2415system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average ReadReq mshr miss latency 2416system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average ReadReq mshr miss latency 2417system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average ReadReq mshr miss latency 2418system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.593832 # average ReadReq mshr miss latency 2419system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.546147 # average ReadReq mshr miss latency 2420system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866 # average HardPFReq mshr miss latency 2421system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31757.007866 # average HardPFReq mshr miss latency 2422system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14699.726879 # average UpgradeReq mshr miss latency 2423system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14699.726879 # average UpgradeReq mshr miss latency 2424system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13672.501574 # average SCUpgradeReq mshr miss latency 2425system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13672.501574 # average SCUpgradeReq mshr miss latency 2426system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 400999 # average SCUpgradeFailReq mshr miss latency 2427system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999 # average SCUpgradeFailReq mshr miss latency 2428system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29828.575036 # average ReadExReq mshr miss latency 2429system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29828.575036 # average ReadExReq mshr miss latency 2430system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average overall mshr miss latency 2431system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average overall mshr miss latency 2432system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average overall mshr miss latency 2433system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19772.603245 # average overall mshr miss latency 2434system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20042.049679 # average overall mshr miss latency 2435system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average overall mshr miss latency 2436system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average overall mshr miss latency 2437system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average overall mshr miss latency 2438system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19772.603245 # average overall mshr miss latency 2439system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866 # average overall mshr miss latency 2440system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25898.777029 # average overall mshr miss latency |
| 2431system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2432system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2433system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2434system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2435system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2436system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2437system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2438system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2439system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2441system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2442system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2443system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2444system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2445system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2446system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2447system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2448system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2449system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2440system.cpu1.toL2Bus.trans_dist::ReadReq 1294408 # Transaction distribution 2441system.cpu1.toL2Bus.trans_dist::ReadResp 865128 # Transaction distribution | 2450system.cpu1.toL2Bus.trans_dist::ReadReq 1294463 # Transaction distribution 2451system.cpu1.toL2Bus.trans_dist::ReadResp 865156 # Transaction distribution |
| 2442system.cpu1.toL2Bus.trans_dist::WriteReq 11871 # Transaction distribution 2443system.cpu1.toL2Bus.trans_dist::WriteResp 11871 # Transaction distribution | 2452system.cpu1.toL2Bus.trans_dist::WriteReq 11871 # Transaction distribution 2453system.cpu1.toL2Bus.trans_dist::WriteResp 11871 # Transaction distribution |
| 2444system.cpu1.toL2Bus.trans_dist::Writeback 117472 # Transaction distribution 2445system.cpu1.toL2Bus.trans_dist::HardPFReq 157468 # Transaction distribution 2446system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution 2447system.cpu1.toL2Bus.trans_dist::UpgradeReq 84838 # Transaction distribution 2448system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41861 # Transaction distribution 2449system.cpu1.toL2Bus.trans_dist::UpgradeResp 87109 # Transaction distribution | 2454system.cpu1.toL2Bus.trans_dist::Writeback 117580 # Transaction distribution 2455system.cpu1.toL2Bus.trans_dist::HardPFReq 157134 # Transaction distribution 2456system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2457system.cpu1.toL2Bus.trans_dist::UpgradeReq 84893 # Transaction distribution 2458system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41888 # Transaction distribution 2459system.cpu1.toL2Bus.trans_dist::UpgradeResp 87131 # Transaction distribution |
| 2450system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution | 2460system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution |
| 2451system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 2452system.cpu1.toL2Bus.trans_dist::ReadExReq 79574 # Transaction distribution 2453system.cpu1.toL2Bus.trans_dist::ReadExResp 66376 # Transaction distribution 2454system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215557 # Packet count per connected master and slave (bytes) 2455system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825064 # Packet count per connected master and slave (bytes) 2456system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17352 # Packet count per connected master and slave (bytes) 2457system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37871 # Packet count per connected master and slave (bytes) 2458system.cpu1.toL2Bus.pkt_count::total 2095844 # Packet count per connected master and slave (bytes) 2459system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38892880 # Cumulative packet size per connected master and slave (bytes) 2460system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25436874 # Cumulative packet size per connected master and slave (bytes) 2461system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes) 2462system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66932 # Cumulative packet size per connected master and slave (bytes) 2463system.cpu1.toL2Bus.pkt_size::total 64427362 # Cumulative packet size per connected master and slave (bytes) 2464system.cpu1.toL2Bus.snoops 834611 # Total snoops (count) 2465system.cpu1.toL2Bus.snoop_fanout::samples 1797339 # Request fanout histogram 2466system.cpu1.toL2Bus.snoop_fanout::mean 5.418381 # Request fanout histogram 2467system.cpu1.toL2Bus.snoop_fanout::stdev 0.493294 # Request fanout histogram | 2461system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution 2462system.cpu1.toL2Bus.trans_dist::ReadExReq 79541 # Transaction distribution 2463system.cpu1.toL2Bus.trans_dist::ReadExResp 66364 # Transaction distribution 2464system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215649 # Packet count per connected master and slave (bytes) 2465system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825187 # Packet count per connected master and slave (bytes) 2466system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17442 # Packet count per connected master and slave (bytes) 2467system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37966 # Packet count per connected master and slave (bytes) 2468system.cpu1.toL2Bus.pkt_count::total 2096244 # Packet count per connected master and slave (bytes) 2469system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38895824 # Cumulative packet size per connected master and slave (bytes) 2470system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25442442 # Cumulative packet size per connected master and slave (bytes) 2471system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31012 # Cumulative packet size per connected master and slave (bytes) 2472system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67368 # Cumulative packet size per connected master and slave (bytes) 2473system.cpu1.toL2Bus.pkt_size::total 64436646 # Cumulative packet size per connected master and slave (bytes) 2474system.cpu1.toL2Bus.snoops 834109 # Total snoops (count) 2475system.cpu1.toL2Bus.snoop_fanout::samples 1797203 # Request fanout histogram 2476system.cpu1.toL2Bus.snoop_fanout::mean 5.418253 # Request fanout histogram 2477system.cpu1.toL2Bus.snoop_fanout::stdev 0.493272 # Request fanout histogram |
| 2468system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2469system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2470system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2471system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2472system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2473system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 2478system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2479system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2480system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2481system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2482system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2483system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 2474system.cpu1.toL2Bus.snoop_fanout::5 1045366 58.16% 58.16% # Request fanout histogram 2475system.cpu1.toL2Bus.snoop_fanout::6 751973 41.84% 100.00% # Request fanout histogram | 2484system.cpu1.toL2Bus.snoop_fanout::5 1045518 58.17% 58.17% # Request fanout histogram 2485system.cpu1.toL2Bus.snoop_fanout::6 751685 41.83% 100.00% # Request fanout histogram |
| 2476system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2477system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2478system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 2486system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2487system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2488system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 2479system.cpu1.toL2Bus.snoop_fanout::total 1797339 # Request fanout histogram 2480system.cpu1.toL2Bus.reqLayer0.occupancy 659657903 # Layer occupancy (ticks) | 2489system.cpu1.toL2Bus.snoop_fanout::total 1797203 # Request fanout histogram 2490system.cpu1.toL2Bus.reqLayer0.occupancy 659823435 # Layer occupancy (ticks) |
| 2481system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2491system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2482system.cpu1.toL2Bus.snoopLayer0.occupancy 81258998 # Layer occupancy (ticks) | 2492system.cpu1.toL2Bus.snoopLayer0.occupancy 81245999 # Layer occupancy (ticks) |
| 2483system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2493system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2484system.cpu1.toL2Bus.respLayer0.occupancy 912908354 # Layer occupancy (ticks) | 2494system.cpu1.toL2Bus.respLayer0.occupancy 912982594 # Layer occupancy (ticks) |
| 2485system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2495system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2486system.cpu1.toL2Bus.respLayer1.occupancy 403842529 # Layer occupancy (ticks) | 2496system.cpu1.toL2Bus.respLayer1.occupancy 403842731 # Layer occupancy (ticks) |
| 2487system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2497system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2488system.cpu1.toL2Bus.respLayer2.occupancy 9825216 # Layer occupancy (ticks) | 2498system.cpu1.toL2Bus.respLayer2.occupancy 9829718 # Layer occupancy (ticks) |
| 2489system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2499system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2490system.cpu1.toL2Bus.respLayer3.occupancy 21209360 # Layer occupancy (ticks) | 2500system.cpu1.toL2Bus.respLayer3.occupancy 21193613 # Layer occupancy (ticks) |
| 2491system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2492system.iobus.trans_dist::ReadReq 31016 # Transaction distribution 2493system.iobus.trans_dist::ReadResp 31016 # Transaction distribution | 2501system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2502system.iobus.trans_dist::ReadReq 31016 # Transaction distribution 2503system.iobus.trans_dist::ReadResp 31016 # Transaction distribution |
| 2494system.iobus.trans_dist::WriteReq 59408 # Transaction distribution 2495system.iobus.trans_dist::WriteResp 59439 # Transaction distribution 2496system.iobus.trans_dist::WriteInvalidateReq 31 # Transaction distribution | 2504system.iobus.trans_dist::WriteReq 59439 # Transaction distribution 2505system.iobus.trans_dist::WriteResp 23215 # Transaction distribution 2506system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2497system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) 2498system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2499system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2500system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2501system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2502system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2503system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2504system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 2579system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2580system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2581system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2582system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2583system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2584system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2585system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2586system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2507system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) 2508system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2509system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2510system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2511system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2512system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2513system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2514system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 2589system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2590system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2591system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2592system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2593system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2594system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2595system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2596system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2587system.iobus.reqLayer27.occupancy 326664315 # Layer occupancy (ticks) | 2597system.iobus.reqLayer27.occupancy 347117122 # Layer occupancy (ticks) |
| 2588system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2589system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2590system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2591system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) 2592system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2598system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2599system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2600system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2601system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) 2602system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2593system.iobus.respLayer3.occupancy 36832361 # Layer occupancy (ticks) | 2603system.iobus.respLayer3.occupancy 36830633 # Layer occupancy (ticks) |
| 2594system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2595system.iocache.tags.replacements 36453 # number of replacements | 2604system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2605system.iocache.tags.replacements 36453 # number of replacements |
| 2596system.iocache.tags.tagsinuse 14.560247 # Cycle average of tags in use | 2606system.iocache.tags.tagsinuse 14.560350 # Cycle average of tags in use |
| 2597system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2598system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. 2599system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2607system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2608system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. 2609system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2600system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit. 2601system.iocache.tags.occ_blocks::realview.ide 14.560247 # Average occupied blocks per requestor 2602system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy 2603system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy | 2610system.iocache.tags.warmup_cycle 254140746000 # Cycle when the warmup percentage was hit. 2611system.iocache.tags.occ_blocks::realview.ide 14.560350 # Average occupied blocks per requestor 2612system.iocache.tags.occ_percent::realview.ide 0.910022 # Average percentage of cache occupancy 2613system.iocache.tags.occ_percent::total 0.910022 # Average percentage of cache occupancy |
| 2604system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2605system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2606system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2614system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2615system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2616system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2607system.iocache.tags.tag_accesses 328487 # Number of tag accesses 2608system.iocache.tags.data_accesses 328487 # Number of data accesses 2609system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2610system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits | 2617system.iocache.tags.tag_accesses 328239 # Number of tag accesses 2618system.iocache.tags.data_accesses 328239 # Number of data accesses |
| 2611system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses 2612system.iocache.ReadReq_misses::total 247 # number of ReadReq misses | 2619system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses 2620system.iocache.ReadReq_misses::total 247 # number of ReadReq misses |
| 2613system.iocache.WriteInvalidateReq_misses::realview.ide 31 # number of WriteInvalidateReq misses 2614system.iocache.WriteInvalidateReq_misses::total 31 # number of WriteInvalidateReq misses | 2621system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2622system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
| 2615system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses 2616system.iocache.demand_misses::total 247 # number of demand (read+write) misses 2617system.iocache.overall_misses::realview.ide 247 # number of overall misses 2618system.iocache.overall_misses::total 247 # number of overall misses | 2623system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses 2624system.iocache.demand_misses::total 247 # number of demand (read+write) misses 2625system.iocache.overall_misses::realview.ide 247 # number of overall misses 2626system.iocache.overall_misses::total 247 # number of overall misses |
| 2619system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles 2620system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles 2621system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles 2622system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles 2623system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles 2624system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles | 2627system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles 2628system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles 2629system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9649955112 # number of WriteInvalidateReq miss cycles 2630system.iocache.WriteInvalidateReq_miss_latency::total 9649955112 # number of WriteInvalidateReq miss cycles 2631system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles 2632system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles 2633system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles 2634system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles |
| 2625system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) 2626system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) | 2635system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) 2636system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) |
| 2627system.iocache.WriteInvalidateReq_accesses::realview.ide 36255 # number of WriteInvalidateReq accesses(hits+misses) 2628system.iocache.WriteInvalidateReq_accesses::total 36255 # number of WriteInvalidateReq accesses(hits+misses) | 2637system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2638system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) |
| 2629system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses 2630system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses 2631system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses 2632system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses 2633system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2634system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 2639system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses 2640system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses 2641system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses 2642system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses 2643system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2644system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 2635system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000855 # miss rate for WriteInvalidateReq accesses 2636system.iocache.WriteInvalidateReq_miss_rate::total 0.000855 # miss rate for WriteInvalidateReq accesses | 2645system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2646system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
| 2637system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2638system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2639system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2640system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2647system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2648system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2649system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2650system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2641system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency 2642system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency 2643system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency 2644system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency 2645system.iocache.overall_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency 2646system.iocache.overall_avg_miss_latency::total 124827.437247 # average overall miss latency 2647system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 2651system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency 2652system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency 2653system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266396.729019 # average WriteInvalidateReq miss latency 2654system.iocache.WriteInvalidateReq_avg_miss_latency::total 266396.729019 # average WriteInvalidateReq miss latency 2655system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency 2656system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency 2657system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency 2658system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency 2659system.iocache.blocked_cycles::no_mshrs 57106 # number of cycles access was blocked |
| 2648system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2660system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2649system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 2661system.iocache.blocked::no_mshrs 7195 # number of cycles access was blocked |
| 2650system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2662system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2651system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 2663system.iocache.avg_blocked_cycles::no_mshrs 7.936901 # average number of cycles each access was blocked |
| 2652system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2664system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2653system.iocache.fast_writes 36224 # number of fast writes performed | 2665system.iocache.fast_writes 0 # number of fast writes performed |
| 2654system.iocache.cache_copies 0 # number of cache copies performed | 2666system.iocache.cache_copies 0 # number of cache copies performed |
| 2667system.iocache.writebacks::writebacks 36206 # number of writebacks 2668system.iocache.writebacks::total 36206 # number of writebacks |
|
| 2655system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses 2656system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses | 2669system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses 2670system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses |
| 2671system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2672system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses |
|
| 2657system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses 2658system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses 2659system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses 2660system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses | 2673system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses 2674system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses 2675system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses 2676system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses |
| 2661system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles 2662system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles 2663system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2253111299 # number of WriteInvalidateReq MSHR miss cycles 2664system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2253111299 # number of WriteInvalidateReq MSHR miss cycles 2665system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles 2666system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles 2667system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles 2668system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles | 2677system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles 2678system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles 2679system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7766041378 # number of WriteInvalidateReq MSHR miss cycles 2680system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7766041378 # number of WriteInvalidateReq MSHR miss cycles 2681system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles 2682system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles 2683system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles 2684system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles |
| 2669system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2670system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 2685system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2686system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 2687system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2688system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
|
| 2671system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2672system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2673system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2674system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2689system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2690system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2691system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2692system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2675system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency 2676system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency 2677system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2678system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2679system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 2680system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency 2681system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 2682system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency | 2693system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency 2694system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency 2695system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214389.393165 # average WriteInvalidateReq mshr miss latency 2696system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214389.393165 # average WriteInvalidateReq mshr miss latency 2697system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency 2698system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency 2699system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency 2700system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency |
| 2683system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2701system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2684system.l2c.tags.replacements 153470 # number of replacements 2685system.l2c.tags.tagsinuse 64454.116988 # Cycle average of tags in use 2686system.l2c.tags.total_refs 519887 # Total number of references to valid blocks. 2687system.l2c.tags.sampled_refs 218097 # Sample count of references to valid blocks. 2688system.l2c.tags.avg_refs 2.383742 # Average number of references to valid blocks. | 2702system.l2c.tags.replacements 153362 # number of replacements 2703system.l2c.tags.tagsinuse 64452.240621 # Cycle average of tags in use 2704system.l2c.tags.total_refs 520061 # Total number of references to valid blocks. 2705system.l2c.tags.sampled_refs 218026 # Sample count of references to valid blocks. 2706system.l2c.tags.avg_refs 2.385316 # Average number of references to valid blocks. |
| 2689system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2707system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2690system.l2c.tags.occ_blocks::writebacks 14115.348135 # Average occupied blocks per requestor 2691system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.484821 # Average occupied blocks per requestor 2692system.l2c.tags.occ_blocks::cpu0.itb.walker 2.876495 # Average occupied blocks per requestor 2693system.l2c.tags.occ_blocks::cpu0.inst 1418.724430 # Average occupied blocks per requestor 2694system.l2c.tags.occ_blocks::cpu0.data 2146.622945 # Average occupied blocks per requestor 2695system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39266.214752 # Average occupied blocks per requestor 2696system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.503287 # Average occupied blocks per requestor 2697system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002749 # Average occupied blocks per requestor 2698system.l2c.tags.occ_blocks::cpu1.inst 292.346121 # Average occupied blocks per requestor 2699system.l2c.tags.occ_blocks::cpu1.data 885.503464 # Average occupied blocks per requestor 2700system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6306.489787 # Average occupied blocks per requestor 2701system.l2c.tags.occ_percent::writebacks 0.215383 # Average percentage of cache occupancy 2702system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy | 2708system.l2c.tags.occ_blocks::writebacks 14085.588040 # Average occupied blocks per requestor 2709system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.542715 # Average occupied blocks per requestor 2710system.l2c.tags.occ_blocks::cpu0.itb.walker 2.877015 # Average occupied blocks per requestor 2711system.l2c.tags.occ_blocks::cpu0.inst 1413.412167 # Average occupied blocks per requestor 2712system.l2c.tags.occ_blocks::cpu0.data 2156.075780 # Average occupied blocks per requestor 2713system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39299.191861 # Average occupied blocks per requestor 2714system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.498933 # Average occupied blocks per requestor 2715system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000005 # Average occupied blocks per requestor 2716system.l2c.tags.occ_blocks::cpu1.inst 294.129683 # Average occupied blocks per requestor 2717system.l2c.tags.occ_blocks::cpu1.data 883.808465 # Average occupied blocks per requestor 2718system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6297.115959 # Average occupied blocks per requestor 2719system.l2c.tags.occ_percent::writebacks 0.214929 # Average percentage of cache occupancy 2720system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy |
| 2703system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy | 2721system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy |
| 2704system.l2c.tags.occ_percent::cpu0.inst 0.021648 # Average percentage of cache occupancy 2705system.l2c.tags.occ_percent::cpu0.data 0.032755 # Average percentage of cache occupancy 2706system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599155 # Average percentage of cache occupancy | 2722system.l2c.tags.occ_percent::cpu0.inst 0.021567 # Average percentage of cache occupancy 2723system.l2c.tags.occ_percent::cpu0.data 0.032899 # Average percentage of cache occupancy 2724system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599658 # Average percentage of cache occupancy |
| 2707system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy 2708system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy | 2725system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy 2726system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy |
| 2709system.l2c.tags.occ_percent::cpu1.inst 0.004461 # Average percentage of cache occupancy 2710system.l2c.tags.occ_percent::cpu1.data 0.013512 # Average percentage of cache occupancy 2711system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096229 # Average percentage of cache occupancy 2712system.l2c.tags.occ_percent::total 0.983492 # Average percentage of cache occupancy 2713system.l2c.tags.occ_task_id_blocks::1022 44297 # Occupied blocks per task id 2714system.l2c.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2715system.l2c.tags.occ_task_id_blocks::1024 20314 # Occupied blocks per task id | 2727system.l2c.tags.occ_percent::cpu1.inst 0.004488 # Average percentage of cache occupancy 2728system.l2c.tags.occ_percent::cpu1.data 0.013486 # Average percentage of cache occupancy 2729system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096086 # Average percentage of cache occupancy 2730system.l2c.tags.occ_percent::total 0.983463 # Average percentage of cache occupancy 2731system.l2c.tags.occ_task_id_blocks::1022 44393 # Occupied blocks per task id 2732system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 2733system.l2c.tags.occ_task_id_blocks::1024 20252 # Occupied blocks per task id |
| 2716system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id | 2734system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id |
| 2717system.l2c.tags.age_task_id_blocks_1022::3 7726 # Occupied blocks per task id 2718system.l2c.tags.age_task_id_blocks_1022::4 36160 # Occupied blocks per task id | 2735system.l2c.tags.age_task_id_blocks_1022::3 7759 # Occupied blocks per task id 2736system.l2c.tags.age_task_id_blocks_1022::4 36223 # Occupied blocks per task id |
| 2719system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id | 2737system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id |
| 2720system.l2c.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 2721system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 2722system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 2723system.l2c.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id 2724system.l2c.tags.age_task_id_blocks_1024::3 4599 # Occupied blocks per task id 2725system.l2c.tags.age_task_id_blocks_1024::4 15358 # Occupied blocks per task id 2726system.l2c.tags.occ_task_id_percent::1022 0.675919 # Percentage of cache occupancy per task id 2727system.l2c.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 2728system.l2c.tags.occ_task_id_percent::1024 0.309967 # Percentage of cache occupancy per task id 2729system.l2c.tags.tag_accesses 6595063 # Number of tag accesses 2730system.l2c.tags.data_accesses 6595063 # Number of data accesses 2731system.l2c.ReadReq_hits::cpu0.dtb.walker 272 # number of ReadReq hits 2732system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits 2733system.l2c.ReadReq_hits::cpu0.inst 12554 # number of ReadReq hits 2734system.l2c.ReadReq_hits::cpu0.data 38932 # number of ReadReq hits 2735system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 181919 # number of ReadReq hits 2736system.l2c.ReadReq_hits::cpu1.dtb.walker 84 # number of ReadReq hits 2737system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits 2738system.l2c.ReadReq_hits::cpu1.inst 4143 # number of ReadReq hits 2739system.l2c.ReadReq_hits::cpu1.data 11543 # number of ReadReq hits 2740system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44205 # number of ReadReq hits 2741system.l2c.ReadReq_hits::total 293833 # number of ReadReq hits 2742system.l2c.Writeback_hits::writebacks 252624 # number of Writeback hits 2743system.l2c.Writeback_hits::total 252624 # number of Writeback hits 2744system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits 2745system.l2c.UpgradeReq_hits::cpu1.data 720 # number of UpgradeReq hits 2746system.l2c.UpgradeReq_hits::total 12425 # number of UpgradeReq hits 2747system.l2c.SCUpgradeReq_hits::cpu0.data 181 # number of SCUpgradeReq hits 2748system.l2c.SCUpgradeReq_hits::cpu1.data 174 # number of SCUpgradeReq hits 2749system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits 2750system.l2c.ReadExReq_hits::cpu0.data 3713 # number of ReadExReq hits 2751system.l2c.ReadExReq_hits::cpu1.data 1233 # number of ReadExReq hits 2752system.l2c.ReadExReq_hits::total 4946 # number of ReadExReq hits 2753system.l2c.demand_hits::cpu0.dtb.walker 272 # number of demand (read+write) hits 2754system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits 2755system.l2c.demand_hits::cpu0.inst 12554 # number of demand (read+write) hits 2756system.l2c.demand_hits::cpu0.data 42645 # number of demand (read+write) hits 2757system.l2c.demand_hits::cpu0.l2cache.prefetcher 181919 # number of demand (read+write) hits 2758system.l2c.demand_hits::cpu1.dtb.walker 84 # number of demand (read+write) hits 2759system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits 2760system.l2c.demand_hits::cpu1.inst 4143 # number of demand (read+write) hits 2761system.l2c.demand_hits::cpu1.data 12776 # number of demand (read+write) hits 2762system.l2c.demand_hits::cpu1.l2cache.prefetcher 44205 # number of demand (read+write) hits 2763system.l2c.demand_hits::total 298779 # number of demand (read+write) hits 2764system.l2c.overall_hits::cpu0.dtb.walker 272 # number of overall hits 2765system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits 2766system.l2c.overall_hits::cpu0.inst 12554 # number of overall hits 2767system.l2c.overall_hits::cpu0.data 42645 # number of overall hits 2768system.l2c.overall_hits::cpu0.l2cache.prefetcher 181919 # number of overall hits 2769system.l2c.overall_hits::cpu1.dtb.walker 84 # number of overall hits 2770system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits 2771system.l2c.overall_hits::cpu1.inst 4143 # number of overall hits 2772system.l2c.overall_hits::cpu1.data 12776 # number of overall hits 2773system.l2c.overall_hits::cpu1.l2cache.prefetcher 44205 # number of overall hits 2774system.l2c.overall_hits::total 298779 # number of overall hits | 2738system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 2739system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 2740system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 2741system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id 2742system.l2c.tags.age_task_id_blocks_1024::3 4616 # Occupied blocks per task id 2743system.l2c.tags.age_task_id_blocks_1024::4 15266 # Occupied blocks per task id 2744system.l2c.tags.occ_task_id_percent::1022 0.677383 # Percentage of cache occupancy per task id 2745system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id 2746system.l2c.tags.occ_task_id_percent::1024 0.309021 # Percentage of cache occupancy per task id 2747system.l2c.tags.tag_accesses 6595512 # Number of tag accesses 2748system.l2c.tags.data_accesses 6595512 # Number of data accesses 2749system.l2c.ReadReq_hits::cpu0.dtb.walker 297 # number of ReadReq hits 2750system.l2c.ReadReq_hits::cpu0.itb.walker 126 # number of ReadReq hits 2751system.l2c.ReadReq_hits::cpu0.inst 12544 # number of ReadReq hits 2752system.l2c.ReadReq_hits::cpu0.data 38879 # number of ReadReq hits 2753system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182049 # number of ReadReq hits 2754system.l2c.ReadReq_hits::cpu1.dtb.walker 77 # number of ReadReq hits 2755system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits 2756system.l2c.ReadReq_hits::cpu1.inst 4168 # number of ReadReq hits 2757system.l2c.ReadReq_hits::cpu1.data 11674 # number of ReadReq hits 2758system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44095 # number of ReadReq hits 2759system.l2c.ReadReq_hits::total 293955 # number of ReadReq hits 2760system.l2c.Writeback_hits::writebacks 252625 # number of Writeback hits 2761system.l2c.Writeback_hits::total 252625 # number of Writeback hits 2762system.l2c.UpgradeReq_hits::cpu0.data 11700 # number of UpgradeReq hits 2763system.l2c.UpgradeReq_hits::cpu1.data 714 # number of UpgradeReq hits 2764system.l2c.UpgradeReq_hits::total 12414 # number of UpgradeReq hits 2765system.l2c.SCUpgradeReq_hits::cpu0.data 188 # number of SCUpgradeReq hits 2766system.l2c.SCUpgradeReq_hits::cpu1.data 168 # number of SCUpgradeReq hits 2767system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits 2768system.l2c.ReadExReq_hits::cpu0.data 3696 # number of ReadExReq hits 2769system.l2c.ReadExReq_hits::cpu1.data 1226 # number of ReadExReq hits 2770system.l2c.ReadExReq_hits::total 4922 # number of ReadExReq hits 2771system.l2c.demand_hits::cpu0.dtb.walker 297 # number of demand (read+write) hits 2772system.l2c.demand_hits::cpu0.itb.walker 126 # number of demand (read+write) hits 2773system.l2c.demand_hits::cpu0.inst 12544 # number of demand (read+write) hits 2774system.l2c.demand_hits::cpu0.data 42575 # number of demand (read+write) hits 2775system.l2c.demand_hits::cpu0.l2cache.prefetcher 182049 # number of demand (read+write) hits 2776system.l2c.demand_hits::cpu1.dtb.walker 77 # number of demand (read+write) hits 2777system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits 2778system.l2c.demand_hits::cpu1.inst 4168 # number of demand (read+write) hits 2779system.l2c.demand_hits::cpu1.data 12900 # number of demand (read+write) hits 2780system.l2c.demand_hits::cpu1.l2cache.prefetcher 44095 # number of demand (read+write) hits 2781system.l2c.demand_hits::total 298877 # number of demand (read+write) hits 2782system.l2c.overall_hits::cpu0.dtb.walker 297 # number of overall hits 2783system.l2c.overall_hits::cpu0.itb.walker 126 # number of overall hits 2784system.l2c.overall_hits::cpu0.inst 12544 # number of overall hits 2785system.l2c.overall_hits::cpu0.data 42575 # number of overall hits 2786system.l2c.overall_hits::cpu0.l2cache.prefetcher 182049 # number of overall hits 2787system.l2c.overall_hits::cpu1.dtb.walker 77 # number of overall hits 2788system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits 2789system.l2c.overall_hits::cpu1.inst 4168 # number of overall hits 2790system.l2c.overall_hits::cpu1.data 12900 # number of overall hits 2791system.l2c.overall_hits::cpu1.l2cache.prefetcher 44095 # number of overall hits 2792system.l2c.overall_hits::total 298877 # number of overall hits |
| 2775system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses | 2793system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses |
| 2776system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses 2777system.l2c.ReadReq_misses::cpu0.inst 3728 # number of ReadReq misses 2778system.l2c.ReadReq_misses::cpu0.data 8660 # number of ReadReq misses 2779system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164285 # number of ReadReq misses | 2794system.l2c.ReadReq_misses::cpu0.itb.walker 6 # number of ReadReq misses 2795system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses 2796system.l2c.ReadReq_misses::cpu0.data 8650 # number of ReadReq misses 2797system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164264 # number of ReadReq misses |
| 2780system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses 2781system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses | 2798system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses 2799system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses |
| 2782system.l2c.ReadReq_misses::cpu1.inst 483 # number of ReadReq misses 2783system.l2c.ReadReq_misses::cpu1.data 1392 # number of ReadReq misses 2784system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21015 # number of ReadReq misses 2785system.l2c.ReadReq_misses::total 199613 # number of ReadReq misses 2786system.l2c.UpgradeReq_misses::cpu0.data 8842 # number of UpgradeReq misses 2787system.l2c.UpgradeReq_misses::cpu1.data 2853 # number of UpgradeReq misses 2788system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses 2789system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses 2790system.l2c.SCUpgradeReq_misses::cpu1.data 1205 # number of SCUpgradeReq misses 2791system.l2c.SCUpgradeReq_misses::total 1954 # number of SCUpgradeReq misses 2792system.l2c.ReadExReq_misses::cpu0.data 7764 # number of ReadExReq misses 2793system.l2c.ReadExReq_misses::cpu1.data 7212 # number of ReadExReq misses 2794system.l2c.ReadExReq_misses::total 14976 # number of ReadExReq misses | 2800system.l2c.ReadReq_misses::cpu1.inst 479 # number of ReadReq misses 2801system.l2c.ReadReq_misses::cpu1.data 1382 # number of ReadReq misses 2802system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21001 # number of ReadReq misses 2803system.l2c.ReadReq_misses::total 199560 # number of ReadReq misses 2804system.l2c.UpgradeReq_misses::cpu0.data 8869 # number of UpgradeReq misses 2805system.l2c.UpgradeReq_misses::cpu1.data 2860 # number of UpgradeReq misses 2806system.l2c.UpgradeReq_misses::total 11729 # number of UpgradeReq misses 2807system.l2c.SCUpgradeReq_misses::cpu0.data 753 # number of SCUpgradeReq misses 2808system.l2c.SCUpgradeReq_misses::cpu1.data 1212 # number of SCUpgradeReq misses 2809system.l2c.SCUpgradeReq_misses::total 1965 # number of SCUpgradeReq misses 2810system.l2c.ReadExReq_misses::cpu0.data 7749 # number of ReadExReq misses 2811system.l2c.ReadExReq_misses::cpu1.data 7210 # number of ReadExReq misses 2812system.l2c.ReadExReq_misses::total 14959 # number of ReadExReq misses |
| 2795system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses | 2813system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses |
| 2796system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses 2797system.l2c.demand_misses::cpu0.inst 3728 # number of demand (read+write) misses 2798system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses 2799system.l2c.demand_misses::cpu0.l2cache.prefetcher 164285 # number of demand (read+write) misses | 2814system.l2c.demand_misses::cpu0.itb.walker 6 # number of demand (read+write) misses 2815system.l2c.demand_misses::cpu0.inst 3733 # number of demand (read+write) misses 2816system.l2c.demand_misses::cpu0.data 16399 # number of demand (read+write) misses 2817system.l2c.demand_misses::cpu0.l2cache.prefetcher 164264 # number of demand (read+write) misses |
| 2800system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 2801system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses | 2818system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 2819system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses |
| 2802system.l2c.demand_misses::cpu1.inst 483 # number of demand (read+write) misses 2803system.l2c.demand_misses::cpu1.data 8604 # number of demand (read+write) misses 2804system.l2c.demand_misses::cpu1.l2cache.prefetcher 21015 # number of demand (read+write) misses 2805system.l2c.demand_misses::total 214589 # number of demand (read+write) misses | 2820system.l2c.demand_misses::cpu1.inst 479 # number of demand (read+write) misses 2821system.l2c.demand_misses::cpu1.data 8592 # number of demand (read+write) misses 2822system.l2c.demand_misses::cpu1.l2cache.prefetcher 21001 # number of demand (read+write) misses 2823system.l2c.demand_misses::total 214519 # number of demand (read+write) misses |
| 2806system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses | 2824system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses |
| 2807system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses 2808system.l2c.overall_misses::cpu0.inst 3728 # number of overall misses 2809system.l2c.overall_misses::cpu0.data 16424 # number of overall misses 2810system.l2c.overall_misses::cpu0.l2cache.prefetcher 164285 # number of overall misses | 2825system.l2c.overall_misses::cpu0.itb.walker 6 # number of overall misses 2826system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses 2827system.l2c.overall_misses::cpu0.data 16399 # number of overall misses 2828system.l2c.overall_misses::cpu0.l2cache.prefetcher 164264 # number of overall misses |
| 2811system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 2812system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses | 2829system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 2830system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses |
| 2813system.l2c.overall_misses::cpu1.inst 483 # number of overall misses 2814system.l2c.overall_misses::cpu1.data 8604 # number of overall misses 2815system.l2c.overall_misses::cpu1.l2cache.prefetcher 21015 # number of overall misses 2816system.l2c.overall_misses::total 214589 # number of overall misses 2817system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2728250 # number of ReadReq miss cycles 2818system.l2c.ReadReq_miss_latency::cpu0.itb.walker 375000 # number of ReadReq miss cycles 2819system.l2c.ReadReq_miss_latency::cpu0.inst 350452746 # number of ReadReq miss cycles 2820system.l2c.ReadReq_miss_latency::cpu0.data 764076744 # number of ReadReq miss cycles 2821system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of ReadReq miss cycles 2822system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 769500 # number of ReadReq miss cycles 2823system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 2824system.l2c.ReadReq_miss_latency::cpu1.inst 49625500 # number of ReadReq miss cycles 2825system.l2c.ReadReq_miss_latency::cpu1.data 122837500 # number of ReadReq miss cycles 2826system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of ReadReq miss cycles 2827system.l2c.ReadReq_miss_latency::total 22837051971 # number of ReadReq miss cycles 2828system.l2c.UpgradeReq_miss_latency::cpu0.data 6562735 # number of UpgradeReq miss cycles 2829system.l2c.UpgradeReq_miss_latency::cpu1.data 2836384 # number of UpgradeReq miss cycles 2830system.l2c.UpgradeReq_miss_latency::total 9399119 # number of UpgradeReq miss cycles 2831system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1040457 # number of SCUpgradeReq miss cycles 2832system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1019459 # number of SCUpgradeReq miss cycles 2833system.l2c.SCUpgradeReq_miss_latency::total 2059916 # number of SCUpgradeReq miss cycles 2834system.l2c.ReadExReq_miss_latency::cpu0.data 712108661 # number of ReadExReq miss cycles 2835system.l2c.ReadExReq_miss_latency::cpu1.data 561982732 # number of ReadExReq miss cycles 2836system.l2c.ReadExReq_miss_latency::total 1274091393 # number of ReadExReq miss cycles 2837system.l2c.demand_miss_latency::cpu0.dtb.walker 2728250 # number of demand (read+write) miss cycles 2838system.l2c.demand_miss_latency::cpu0.itb.walker 375000 # number of demand (read+write) miss cycles 2839system.l2c.demand_miss_latency::cpu0.inst 350452746 # number of demand (read+write) miss cycles 2840system.l2c.demand_miss_latency::cpu0.data 1476185405 # number of demand (read+write) miss cycles 2841system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of demand (read+write) miss cycles 2842system.l2c.demand_miss_latency::cpu1.dtb.walker 769500 # number of demand (read+write) miss cycles 2843system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles 2844system.l2c.demand_miss_latency::cpu1.inst 49625500 # number of demand (read+write) miss cycles 2845system.l2c.demand_miss_latency::cpu1.data 684820232 # number of demand (read+write) miss cycles 2846system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of demand (read+write) miss cycles 2847system.l2c.demand_miss_latency::total 24111143364 # number of demand (read+write) miss cycles 2848system.l2c.overall_miss_latency::cpu0.dtb.walker 2728250 # number of overall miss cycles 2849system.l2c.overall_miss_latency::cpu0.itb.walker 375000 # number of overall miss cycles 2850system.l2c.overall_miss_latency::cpu0.inst 350452746 # number of overall miss cycles 2851system.l2c.overall_miss_latency::cpu0.data 1476185405 # number of overall miss cycles 2852system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of overall miss cycles 2853system.l2c.overall_miss_latency::cpu1.dtb.walker 769500 # number of overall miss cycles 2854system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles 2855system.l2c.overall_miss_latency::cpu1.inst 49625500 # number of overall miss cycles 2856system.l2c.overall_miss_latency::cpu1.data 684820232 # number of overall miss cycles 2857system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of overall miss cycles 2858system.l2c.overall_miss_latency::total 24111143364 # number of overall miss cycles 2859system.l2c.ReadReq_accesses::cpu0.dtb.walker 306 # number of ReadReq accesses(hits+misses) 2860system.l2c.ReadReq_accesses::cpu0.itb.walker 138 # number of ReadReq accesses(hits+misses) 2861system.l2c.ReadReq_accesses::cpu0.inst 16282 # number of ReadReq accesses(hits+misses) 2862system.l2c.ReadReq_accesses::cpu0.data 47592 # number of ReadReq accesses(hits+misses) 2863system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346204 # number of ReadReq accesses(hits+misses) 2864system.l2c.ReadReq_accesses::cpu1.dtb.walker 94 # number of ReadReq accesses(hits+misses) 2865system.l2c.ReadReq_accesses::cpu1.itb.walker 49 # number of ReadReq accesses(hits+misses) 2866system.l2c.ReadReq_accesses::cpu1.inst 4626 # number of ReadReq accesses(hits+misses) 2867system.l2c.ReadReq_accesses::cpu1.data 12935 # number of ReadReq accesses(hits+misses) 2868system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65220 # number of ReadReq accesses(hits+misses) 2869system.l2c.ReadReq_accesses::total 493446 # number of ReadReq accesses(hits+misses) 2870system.l2c.Writeback_accesses::writebacks 252624 # number of Writeback accesses(hits+misses) 2871system.l2c.Writeback_accesses::total 252624 # number of Writeback accesses(hits+misses) 2872system.l2c.UpgradeReq_accesses::cpu0.data 20547 # number of UpgradeReq accesses(hits+misses) 2873system.l2c.UpgradeReq_accesses::cpu1.data 3573 # number of UpgradeReq accesses(hits+misses) 2874system.l2c.UpgradeReq_accesses::total 24120 # number of UpgradeReq accesses(hits+misses) 2875system.l2c.SCUpgradeReq_accesses::cpu0.data 930 # number of SCUpgradeReq accesses(hits+misses) 2876system.l2c.SCUpgradeReq_accesses::cpu1.data 1379 # number of SCUpgradeReq accesses(hits+misses) 2877system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) 2878system.l2c.ReadExReq_accesses::cpu0.data 11477 # number of ReadExReq accesses(hits+misses) 2879system.l2c.ReadExReq_accesses::cpu1.data 8445 # number of ReadExReq accesses(hits+misses) 2880system.l2c.ReadExReq_accesses::total 19922 # number of ReadExReq accesses(hits+misses) 2881system.l2c.demand_accesses::cpu0.dtb.walker 306 # number of demand (read+write) accesses 2882system.l2c.demand_accesses::cpu0.itb.walker 138 # number of demand (read+write) accesses 2883system.l2c.demand_accesses::cpu0.inst 16282 # number of demand (read+write) accesses 2884system.l2c.demand_accesses::cpu0.data 59069 # number of demand (read+write) accesses 2885system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346204 # number of demand (read+write) accesses 2886system.l2c.demand_accesses::cpu1.dtb.walker 94 # number of demand (read+write) accesses 2887system.l2c.demand_accesses::cpu1.itb.walker 49 # number of demand (read+write) accesses 2888system.l2c.demand_accesses::cpu1.inst 4626 # number of demand (read+write) accesses 2889system.l2c.demand_accesses::cpu1.data 21380 # number of demand (read+write) accesses 2890system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65220 # number of demand (read+write) accesses 2891system.l2c.demand_accesses::total 513368 # number of demand (read+write) accesses 2892system.l2c.overall_accesses::cpu0.dtb.walker 306 # number of overall (read+write) accesses 2893system.l2c.overall_accesses::cpu0.itb.walker 138 # number of overall (read+write) accesses 2894system.l2c.overall_accesses::cpu0.inst 16282 # number of overall (read+write) accesses 2895system.l2c.overall_accesses::cpu0.data 59069 # number of overall (read+write) accesses 2896system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346204 # number of overall (read+write) accesses 2897system.l2c.overall_accesses::cpu1.dtb.walker 94 # number of overall (read+write) accesses 2898system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses 2899system.l2c.overall_accesses::cpu1.inst 4626 # number of overall (read+write) accesses 2900system.l2c.overall_accesses::cpu1.data 21380 # number of overall (read+write) accesses 2901system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65220 # number of overall (read+write) accesses 2902system.l2c.overall_accesses::total 513368 # number of overall (read+write) accesses 2903system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for ReadReq accesses 2904system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.036232 # miss rate for ReadReq accesses 2905system.l2c.ReadReq_miss_rate::cpu0.inst 0.228965 # miss rate for ReadReq accesses 2906system.l2c.ReadReq_miss_rate::cpu0.data 0.181963 # miss rate for ReadReq accesses 2907system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474532 # miss rate for ReadReq accesses 2908system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.106383 # miss rate for ReadReq accesses 2909system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses 2910system.l2c.ReadReq_miss_rate::cpu1.inst 0.104410 # miss rate for ReadReq accesses 2911system.l2c.ReadReq_miss_rate::cpu1.data 0.107615 # miss rate for ReadReq accesses 2912system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.322217 # miss rate for ReadReq accesses 2913system.l2c.ReadReq_miss_rate::total 0.404529 # miss rate for ReadReq accesses 2914system.l2c.UpgradeReq_miss_rate::cpu0.data 0.430330 # miss rate for UpgradeReq accesses 2915system.l2c.UpgradeReq_miss_rate::cpu1.data 0.798489 # miss rate for UpgradeReq accesses 2916system.l2c.UpgradeReq_miss_rate::total 0.484867 # miss rate for UpgradeReq accesses 2917system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.805376 # miss rate for SCUpgradeReq accesses 2918system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.873822 # miss rate for SCUpgradeReq accesses 2919system.l2c.SCUpgradeReq_miss_rate::total 0.846254 # miss rate for SCUpgradeReq accesses 2920system.l2c.ReadExReq_miss_rate::cpu0.data 0.676483 # miss rate for ReadExReq accesses 2921system.l2c.ReadExReq_miss_rate::cpu1.data 0.853996 # miss rate for ReadExReq accesses 2922system.l2c.ReadExReq_miss_rate::total 0.751732 # miss rate for ReadExReq accesses 2923system.l2c.demand_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for demand accesses 2924system.l2c.demand_miss_rate::cpu0.itb.walker 0.036232 # miss rate for demand accesses 2925system.l2c.demand_miss_rate::cpu0.inst 0.228965 # miss rate for demand accesses 2926system.l2c.demand_miss_rate::cpu0.data 0.278048 # miss rate for demand accesses 2927system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474532 # miss rate for demand accesses 2928system.l2c.demand_miss_rate::cpu1.dtb.walker 0.106383 # miss rate for demand accesses 2929system.l2c.demand_miss_rate::cpu1.itb.walker 0.020408 # miss rate for demand accesses 2930system.l2c.demand_miss_rate::cpu1.inst 0.104410 # miss rate for demand accesses 2931system.l2c.demand_miss_rate::cpu1.data 0.402432 # miss rate for demand accesses 2932system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.322217 # miss rate for demand accesses 2933system.l2c.demand_miss_rate::total 0.418002 # miss rate for demand accesses 2934system.l2c.overall_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for overall accesses 2935system.l2c.overall_miss_rate::cpu0.itb.walker 0.036232 # miss rate for overall accesses 2936system.l2c.overall_miss_rate::cpu0.inst 0.228965 # miss rate for overall accesses 2937system.l2c.overall_miss_rate::cpu0.data 0.278048 # miss rate for overall accesses 2938system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474532 # miss rate for overall accesses 2939system.l2c.overall_miss_rate::cpu1.dtb.walker 0.106383 # miss rate for overall accesses 2940system.l2c.overall_miss_rate::cpu1.itb.walker 0.020408 # miss rate for overall accesses 2941system.l2c.overall_miss_rate::cpu1.inst 0.104410 # miss rate for overall accesses 2942system.l2c.overall_miss_rate::cpu1.data 0.402432 # miss rate for overall accesses 2943system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.322217 # miss rate for overall accesses 2944system.l2c.overall_miss_rate::total 0.418002 # miss rate for overall accesses 2945system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80242.647059 # average ReadReq miss latency | 2831system.l2c.overall_misses::cpu1.inst 479 # number of overall misses 2832system.l2c.overall_misses::cpu1.data 8592 # number of overall misses 2833system.l2c.overall_misses::cpu1.l2cache.prefetcher 21001 # number of overall misses 2834system.l2c.overall_misses::total 214519 # number of overall misses 2835system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2746500 # number of ReadReq miss cycles 2836system.l2c.ReadReq_miss_latency::cpu0.itb.walker 450000 # number of ReadReq miss cycles 2837system.l2c.ReadReq_miss_latency::cpu0.inst 351602993 # number of ReadReq miss cycles 2838system.l2c.ReadReq_miss_latency::cpu0.data 773076495 # number of ReadReq miss cycles 2839system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 19011653853 # number of ReadReq miss cycles 2840system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 762250 # number of ReadReq miss cycles 2841system.l2c.ReadReq_miss_latency::cpu1.itb.walker 318000 # number of ReadReq miss cycles 2842system.l2c.ReadReq_miss_latency::cpu1.inst 47746000 # number of ReadReq miss cycles 2843system.l2c.ReadReq_miss_latency::cpu1.data 122164750 # number of ReadReq miss cycles 2844system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2528718655 # number of ReadReq miss cycles 2845system.l2c.ReadReq_miss_latency::total 22839239496 # number of ReadReq miss cycles 2846system.l2c.UpgradeReq_miss_latency::cpu0.data 7000718 # number of UpgradeReq miss cycles 2847system.l2c.UpgradeReq_miss_latency::cpu1.data 3239366 # number of UpgradeReq miss cycles 2848system.l2c.UpgradeReq_miss_latency::total 10240084 # number of UpgradeReq miss cycles 2849system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1399947 # number of SCUpgradeReq miss cycles 2850system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1250448 # number of SCUpgradeReq miss cycles 2851system.l2c.SCUpgradeReq_miss_latency::total 2650395 # number of SCUpgradeReq miss cycles 2852system.l2c.ReadExReq_miss_latency::cpu0.data 713784680 # number of ReadExReq miss cycles 2853system.l2c.ReadExReq_miss_latency::cpu1.data 563377983 # number of ReadExReq miss cycles 2854system.l2c.ReadExReq_miss_latency::total 1277162663 # number of ReadExReq miss cycles 2855system.l2c.demand_miss_latency::cpu0.dtb.walker 2746500 # number of demand (read+write) miss cycles 2856system.l2c.demand_miss_latency::cpu0.itb.walker 450000 # number of demand (read+write) miss cycles 2857system.l2c.demand_miss_latency::cpu0.inst 351602993 # number of demand (read+write) miss cycles 2858system.l2c.demand_miss_latency::cpu0.data 1486861175 # number of demand (read+write) miss cycles 2859system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19011653853 # number of demand (read+write) miss cycles 2860system.l2c.demand_miss_latency::cpu1.dtb.walker 762250 # number of demand (read+write) miss cycles 2861system.l2c.demand_miss_latency::cpu1.itb.walker 318000 # number of demand (read+write) miss cycles 2862system.l2c.demand_miss_latency::cpu1.inst 47746000 # number of demand (read+write) miss cycles 2863system.l2c.demand_miss_latency::cpu1.data 685542733 # number of demand (read+write) miss cycles 2864system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2528718655 # number of demand (read+write) miss cycles 2865system.l2c.demand_miss_latency::total 24116402159 # number of demand (read+write) miss cycles 2866system.l2c.overall_miss_latency::cpu0.dtb.walker 2746500 # number of overall miss cycles 2867system.l2c.overall_miss_latency::cpu0.itb.walker 450000 # number of overall miss cycles 2868system.l2c.overall_miss_latency::cpu0.inst 351602993 # number of overall miss cycles 2869system.l2c.overall_miss_latency::cpu0.data 1486861175 # number of overall miss cycles 2870system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19011653853 # number of overall miss cycles 2871system.l2c.overall_miss_latency::cpu1.dtb.walker 762250 # number of overall miss cycles 2872system.l2c.overall_miss_latency::cpu1.itb.walker 318000 # number of overall miss cycles 2873system.l2c.overall_miss_latency::cpu1.inst 47746000 # number of overall miss cycles 2874system.l2c.overall_miss_latency::cpu1.data 685542733 # number of overall miss cycles 2875system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2528718655 # number of overall miss cycles 2876system.l2c.overall_miss_latency::total 24116402159 # number of overall miss cycles 2877system.l2c.ReadReq_accesses::cpu0.dtb.walker 331 # number of ReadReq accesses(hits+misses) 2878system.l2c.ReadReq_accesses::cpu0.itb.walker 132 # number of ReadReq accesses(hits+misses) 2879system.l2c.ReadReq_accesses::cpu0.inst 16277 # number of ReadReq accesses(hits+misses) 2880system.l2c.ReadReq_accesses::cpu0.data 47529 # number of ReadReq accesses(hits+misses) 2881system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346313 # number of ReadReq accesses(hits+misses) 2882system.l2c.ReadReq_accesses::cpu1.dtb.walker 87 # number of ReadReq accesses(hits+misses) 2883system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) 2884system.l2c.ReadReq_accesses::cpu1.inst 4647 # number of ReadReq accesses(hits+misses) 2885system.l2c.ReadReq_accesses::cpu1.data 13056 # number of ReadReq accesses(hits+misses) 2886system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65096 # number of ReadReq accesses(hits+misses) 2887system.l2c.ReadReq_accesses::total 493515 # number of ReadReq accesses(hits+misses) 2888system.l2c.Writeback_accesses::writebacks 252625 # number of Writeback accesses(hits+misses) 2889system.l2c.Writeback_accesses::total 252625 # number of Writeback accesses(hits+misses) 2890system.l2c.UpgradeReq_accesses::cpu0.data 20569 # number of UpgradeReq accesses(hits+misses) 2891system.l2c.UpgradeReq_accesses::cpu1.data 3574 # number of UpgradeReq accesses(hits+misses) 2892system.l2c.UpgradeReq_accesses::total 24143 # number of UpgradeReq accesses(hits+misses) 2893system.l2c.SCUpgradeReq_accesses::cpu0.data 941 # number of SCUpgradeReq accesses(hits+misses) 2894system.l2c.SCUpgradeReq_accesses::cpu1.data 1380 # number of SCUpgradeReq accesses(hits+misses) 2895system.l2c.SCUpgradeReq_accesses::total 2321 # number of SCUpgradeReq accesses(hits+misses) 2896system.l2c.ReadExReq_accesses::cpu0.data 11445 # number of ReadExReq accesses(hits+misses) 2897system.l2c.ReadExReq_accesses::cpu1.data 8436 # number of ReadExReq accesses(hits+misses) 2898system.l2c.ReadExReq_accesses::total 19881 # number of ReadExReq accesses(hits+misses) 2899system.l2c.demand_accesses::cpu0.dtb.walker 331 # number of demand (read+write) accesses 2900system.l2c.demand_accesses::cpu0.itb.walker 132 # number of demand (read+write) accesses 2901system.l2c.demand_accesses::cpu0.inst 16277 # number of demand (read+write) accesses 2902system.l2c.demand_accesses::cpu0.data 58974 # number of demand (read+write) accesses 2903system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346313 # number of demand (read+write) accesses 2904system.l2c.demand_accesses::cpu1.dtb.walker 87 # number of demand (read+write) accesses 2905system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses 2906system.l2c.demand_accesses::cpu1.inst 4647 # number of demand (read+write) accesses 2907system.l2c.demand_accesses::cpu1.data 21492 # number of demand (read+write) accesses 2908system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65096 # number of demand (read+write) accesses 2909system.l2c.demand_accesses::total 513396 # number of demand (read+write) accesses 2910system.l2c.overall_accesses::cpu0.dtb.walker 331 # number of overall (read+write) accesses 2911system.l2c.overall_accesses::cpu0.itb.walker 132 # number of overall (read+write) accesses 2912system.l2c.overall_accesses::cpu0.inst 16277 # number of overall (read+write) accesses 2913system.l2c.overall_accesses::cpu0.data 58974 # number of overall (read+write) accesses 2914system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346313 # number of overall (read+write) accesses 2915system.l2c.overall_accesses::cpu1.dtb.walker 87 # number of overall (read+write) accesses 2916system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses 2917system.l2c.overall_accesses::cpu1.inst 4647 # number of overall (read+write) accesses 2918system.l2c.overall_accesses::cpu1.data 21492 # number of overall (read+write) accesses 2919system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65096 # number of overall (read+write) accesses 2920system.l2c.overall_accesses::total 513396 # number of overall (read+write) accesses 2921system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.102719 # miss rate for ReadReq accesses 2922system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.045455 # miss rate for ReadReq accesses 2923system.l2c.ReadReq_miss_rate::cpu0.inst 0.229342 # miss rate for ReadReq accesses 2924system.l2c.ReadReq_miss_rate::cpu0.data 0.181994 # miss rate for ReadReq accesses 2925system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474322 # miss rate for ReadReq accesses 2926system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.114943 # miss rate for ReadReq accesses 2927system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021277 # miss rate for ReadReq accesses 2928system.l2c.ReadReq_miss_rate::cpu1.inst 0.103077 # miss rate for ReadReq accesses 2929system.l2c.ReadReq_miss_rate::cpu1.data 0.105852 # miss rate for ReadReq accesses 2930system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.322616 # miss rate for ReadReq accesses 2931system.l2c.ReadReq_miss_rate::total 0.404365 # miss rate for ReadReq accesses 2932system.l2c.UpgradeReq_miss_rate::cpu0.data 0.431183 # miss rate for UpgradeReq accesses 2933system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800224 # miss rate for UpgradeReq accesses 2934system.l2c.UpgradeReq_miss_rate::total 0.485814 # miss rate for UpgradeReq accesses 2935system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.800213 # miss rate for SCUpgradeReq accesses 2936system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.878261 # miss rate for SCUpgradeReq accesses 2937system.l2c.SCUpgradeReq_miss_rate::total 0.846618 # miss rate for SCUpgradeReq accesses 2938system.l2c.ReadExReq_miss_rate::cpu0.data 0.677064 # miss rate for ReadExReq accesses 2939system.l2c.ReadExReq_miss_rate::cpu1.data 0.854670 # miss rate for ReadExReq accesses 2940system.l2c.ReadExReq_miss_rate::total 0.752427 # miss rate for ReadExReq accesses 2941system.l2c.demand_miss_rate::cpu0.dtb.walker 0.102719 # miss rate for demand accesses 2942system.l2c.demand_miss_rate::cpu0.itb.walker 0.045455 # miss rate for demand accesses 2943system.l2c.demand_miss_rate::cpu0.inst 0.229342 # miss rate for demand accesses 2944system.l2c.demand_miss_rate::cpu0.data 0.278072 # miss rate for demand accesses 2945system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474322 # miss rate for demand accesses 2946system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114943 # miss rate for demand accesses 2947system.l2c.demand_miss_rate::cpu1.itb.walker 0.021277 # miss rate for demand accesses 2948system.l2c.demand_miss_rate::cpu1.inst 0.103077 # miss rate for demand accesses 2949system.l2c.demand_miss_rate::cpu1.data 0.399777 # miss rate for demand accesses 2950system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.322616 # miss rate for demand accesses 2951system.l2c.demand_miss_rate::total 0.417843 # miss rate for demand accesses 2952system.l2c.overall_miss_rate::cpu0.dtb.walker 0.102719 # miss rate for overall accesses 2953system.l2c.overall_miss_rate::cpu0.itb.walker 0.045455 # miss rate for overall accesses 2954system.l2c.overall_miss_rate::cpu0.inst 0.229342 # miss rate for overall accesses 2955system.l2c.overall_miss_rate::cpu0.data 0.278072 # miss rate for overall accesses 2956system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474322 # miss rate for overall accesses 2957system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114943 # miss rate for overall accesses 2958system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses 2959system.l2c.overall_miss_rate::cpu1.inst 0.103077 # miss rate for overall accesses 2960system.l2c.overall_miss_rate::cpu1.data 0.399777 # miss rate for overall accesses 2961system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.322616 # miss rate for overall accesses 2962system.l2c.overall_miss_rate::total 0.417843 # miss rate for overall accesses 2963system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80779.411765 # average ReadReq miss latency |
| 2946system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency | 2964system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency |
| 2947system.l2c.ReadReq_avg_miss_latency::cpu0.inst 94005.564914 # average ReadReq miss latency 2948system.l2c.ReadReq_avg_miss_latency::cpu0.data 88230.570901 # average ReadReq miss latency 2949system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210 # average ReadReq miss latency 2950system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76950 # average ReadReq miss latency 2951system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 2952system.l2c.ReadReq_avg_miss_latency::cpu1.inst 102744.306418 # average ReadReq miss latency 2953system.l2c.ReadReq_avg_miss_latency::cpu1.data 88245.330460 # average ReadReq miss latency 2954system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041 # average ReadReq miss latency 2955system.l2c.ReadReq_avg_miss_latency::total 114406.636697 # average ReadReq miss latency 2956system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 742.222913 # average UpgradeReq miss latency 2957system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 994.175955 # average UpgradeReq miss latency 2958system.l2c.UpgradeReq_avg_miss_latency::total 803.686960 # average UpgradeReq miss latency 2959system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1389.128171 # average SCUpgradeReq miss latency 2960system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 846.024066 # average SCUpgradeReq miss latency 2961system.l2c.SCUpgradeReq_avg_miss_latency::total 1054.204708 # average SCUpgradeReq miss latency 2962system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91719.302035 # average ReadExReq miss latency 2963system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77923.285080 # average ReadExReq miss latency 2964system.l2c.ReadExReq_avg_miss_latency::total 85075.547075 # average ReadExReq miss latency 2965system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80242.647059 # average overall miss latency | 2965system.l2c.ReadReq_avg_miss_latency::cpu0.inst 94187.782748 # average ReadReq miss latency 2966system.l2c.ReadReq_avg_miss_latency::cpu0.data 89373.005202 # average ReadReq miss latency 2967system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115738.408008 # average ReadReq miss latency 2968system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76225 # average ReadReq miss latency 2969system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 318000 # average ReadReq miss latency 2970system.l2c.ReadReq_avg_miss_latency::cpu1.inst 99678.496868 # average ReadReq miss latency 2971system.l2c.ReadReq_avg_miss_latency::cpu1.data 88397.069465 # average ReadReq miss latency 2972system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265 # average ReadReq miss latency 2973system.l2c.ReadReq_avg_miss_latency::total 114447.983043 # average ReadReq miss latency 2974system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 789.346939 # average UpgradeReq miss latency 2975system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1132.645455 # average UpgradeReq miss latency 2976system.l2c.UpgradeReq_avg_miss_latency::total 873.056868 # average UpgradeReq miss latency 2977system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1859.159363 # average SCUpgradeReq miss latency 2978system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1031.722772 # average SCUpgradeReq miss latency 2979system.l2c.SCUpgradeReq_avg_miss_latency::total 1348.801527 # average SCUpgradeReq miss latency 2980system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92113.134598 # average ReadExReq miss latency 2981system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78138.416505 # average ReadExReq miss latency 2982system.l2c.ReadExReq_avg_miss_latency::total 85377.542817 # average ReadExReq miss latency 2983system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80779.411765 # average overall miss latency |
| 2966system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2984system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2967system.l2c.demand_avg_miss_latency::cpu0.inst 94005.564914 # average overall miss latency 2968system.l2c.demand_avg_miss_latency::cpu0.data 89879.773807 # average overall miss latency 2969system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210 # average overall miss latency 2970system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76950 # average overall miss latency 2971system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 2972system.l2c.demand_avg_miss_latency::cpu1.inst 102744.306418 # average overall miss latency 2973system.l2c.demand_avg_miss_latency::cpu1.data 79593.239424 # average overall miss latency 2974system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041 # average overall miss latency 2975system.l2c.demand_avg_miss_latency::total 112359.642684 # average overall miss latency 2976system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80242.647059 # average overall miss latency | 2985system.l2c.demand_avg_miss_latency::cpu0.inst 94187.782748 # average overall miss latency 2986system.l2c.demand_avg_miss_latency::cpu0.data 90667.795292 # average overall miss latency 2987system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115738.408008 # average overall miss latency 2988system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76225 # average overall miss latency 2989system.l2c.demand_avg_miss_latency::cpu1.itb.walker 318000 # average overall miss latency 2990system.l2c.demand_avg_miss_latency::cpu1.inst 99678.496868 # average overall miss latency 2991system.l2c.demand_avg_miss_latency::cpu1.data 79788.493133 # average overall miss latency 2992system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265 # average overall miss latency 2993system.l2c.demand_avg_miss_latency::total 112420.821275 # average overall miss latency 2994system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80779.411765 # average overall miss latency |
| 2977system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2995system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2978system.l2c.overall_avg_miss_latency::cpu0.inst 94005.564914 # average overall miss latency 2979system.l2c.overall_avg_miss_latency::cpu0.data 89879.773807 # average overall miss latency 2980system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210 # average overall miss latency 2981system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76950 # average overall miss latency 2982system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 2983system.l2c.overall_avg_miss_latency::cpu1.inst 102744.306418 # average overall miss latency 2984system.l2c.overall_avg_miss_latency::cpu1.data 79593.239424 # average overall miss latency 2985system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041 # average overall miss latency 2986system.l2c.overall_avg_miss_latency::total 112359.642684 # average overall miss latency 2987system.l2c.blocked_cycles::no_mshrs 853 # number of cycles access was blocked | 2996system.l2c.overall_avg_miss_latency::cpu0.inst 94187.782748 # average overall miss latency 2997system.l2c.overall_avg_miss_latency::cpu0.data 90667.795292 # average overall miss latency 2998system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115738.408008 # average overall miss latency 2999system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76225 # average overall miss latency 3000system.l2c.overall_avg_miss_latency::cpu1.itb.walker 318000 # average overall miss latency 3001system.l2c.overall_avg_miss_latency::cpu1.inst 99678.496868 # average overall miss latency 3002system.l2c.overall_avg_miss_latency::cpu1.data 79788.493133 # average overall miss latency 3003system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265 # average overall miss latency 3004system.l2c.overall_avg_miss_latency::total 112420.821275 # average overall miss latency 3005system.l2c.blocked_cycles::no_mshrs 117 # number of cycles access was blocked |
| 2988system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3006system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2989system.l2c.blocked::no_mshrs 17 # number of cycles access was blocked | 3007system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked |
| 2990system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 3008system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2991system.l2c.avg_blocked_cycles::no_mshrs 50.176471 # average number of cycles each access was blocked | 3009system.l2c.avg_blocked_cycles::no_mshrs 19.500000 # average number of cycles each access was blocked |
| 2992system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2993system.l2c.fast_writes 0 # number of fast writes performed 2994system.l2c.cache_copies 0 # number of cache copies performed | 3010system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3011system.l2c.fast_writes 0 # number of fast writes performed 3012system.l2c.cache_copies 0 # number of cache copies performed |
| 2995system.l2c.writebacks::writebacks 113437 # number of writebacks 2996system.l2c.writebacks::total 113437 # number of writebacks | 3013system.l2c.writebacks::writebacks 113392 # number of writebacks 3014system.l2c.writebacks::total 113392 # number of writebacks |
| 2997system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits 2998system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits 2999system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 3000system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 18 # number of ReadReq MSHR hits 3001system.l2c.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits 3002system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 3003system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits 3004system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 3005system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 18 # number of demand (read+write) MSHR hits 3006system.l2c.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 3007system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 3008system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits 3009system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 3010system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 18 # number of overall MSHR hits 3011system.l2c.overall_mshr_hits::total 24 # number of overall MSHR hits 3012system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 34 # number of ReadReq MSHR misses | 3015system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits 3016system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits 3017system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 3018system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 18 # number of ReadReq MSHR hits 3019system.l2c.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits 3020system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 3021system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits 3022system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 3023system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 18 # number of demand (read+write) MSHR hits 3024system.l2c.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 3025system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 3026system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits 3027system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 3028system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 18 # number of overall MSHR hits 3029system.l2c.overall_mshr_hits::total 24 # number of overall MSHR hits 3030system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 34 # number of ReadReq MSHR misses |
| 3013system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses 3014system.l2c.ReadReq_mshr_misses::cpu0.inst 3728 # number of ReadReq MSHR misses 3015system.l2c.ReadReq_mshr_misses::cpu0.data 8659 # number of ReadReq MSHR misses 3016system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164282 # number of ReadReq MSHR misses | 3031system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6 # number of ReadReq MSHR misses 3032system.l2c.ReadReq_mshr_misses::cpu0.inst 3733 # number of ReadReq MSHR misses 3033system.l2c.ReadReq_mshr_misses::cpu0.data 8649 # number of ReadReq MSHR misses 3034system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164261 # number of ReadReq MSHR misses |
| 3017system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses 3018system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses | 3035system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses 3036system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses |
| 3019system.l2c.ReadReq_mshr_misses::cpu1.inst 481 # number of ReadReq MSHR misses 3020system.l2c.ReadReq_mshr_misses::cpu1.data 1392 # number of ReadReq MSHR misses 3021system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20997 # number of ReadReq MSHR misses 3022system.l2c.ReadReq_mshr_misses::total 199589 # number of ReadReq MSHR misses 3023system.l2c.UpgradeReq_mshr_misses::cpu0.data 8842 # number of UpgradeReq MSHR misses 3024system.l2c.UpgradeReq_mshr_misses::cpu1.data 2853 # number of UpgradeReq MSHR misses 3025system.l2c.UpgradeReq_mshr_misses::total 11695 # number of UpgradeReq MSHR misses 3026system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 749 # number of SCUpgradeReq MSHR misses 3027system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1205 # number of SCUpgradeReq MSHR misses 3028system.l2c.SCUpgradeReq_mshr_misses::total 1954 # number of SCUpgradeReq MSHR misses 3029system.l2c.ReadExReq_mshr_misses::cpu0.data 7764 # number of ReadExReq MSHR misses 3030system.l2c.ReadExReq_mshr_misses::cpu1.data 7212 # number of ReadExReq MSHR misses 3031system.l2c.ReadExReq_mshr_misses::total 14976 # number of ReadExReq MSHR misses | 3037system.l2c.ReadReq_mshr_misses::cpu1.inst 477 # number of ReadReq MSHR misses 3038system.l2c.ReadReq_mshr_misses::cpu1.data 1382 # number of ReadReq MSHR misses 3039system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20983 # number of ReadReq MSHR misses 3040system.l2c.ReadReq_mshr_misses::total 199536 # number of ReadReq MSHR misses 3041system.l2c.UpgradeReq_mshr_misses::cpu0.data 8869 # number of UpgradeReq MSHR misses 3042system.l2c.UpgradeReq_mshr_misses::cpu1.data 2860 # number of UpgradeReq MSHR misses 3043system.l2c.UpgradeReq_mshr_misses::total 11729 # number of UpgradeReq MSHR misses 3044system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 753 # number of SCUpgradeReq MSHR misses 3045system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1212 # number of SCUpgradeReq MSHR misses 3046system.l2c.SCUpgradeReq_mshr_misses::total 1965 # number of SCUpgradeReq MSHR misses 3047system.l2c.ReadExReq_mshr_misses::cpu0.data 7749 # number of ReadExReq MSHR misses 3048system.l2c.ReadExReq_mshr_misses::cpu1.data 7210 # number of ReadExReq MSHR misses 3049system.l2c.ReadExReq_mshr_misses::total 14959 # number of ReadExReq MSHR misses |
| 3032system.l2c.demand_mshr_misses::cpu0.dtb.walker 34 # number of demand (read+write) MSHR misses | 3050system.l2c.demand_mshr_misses::cpu0.dtb.walker 34 # number of demand (read+write) MSHR misses |
| 3033system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses 3034system.l2c.demand_mshr_misses::cpu0.inst 3728 # number of demand (read+write) MSHR misses 3035system.l2c.demand_mshr_misses::cpu0.data 16423 # number of demand (read+write) MSHR misses 3036system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164282 # number of demand (read+write) MSHR misses | 3051system.l2c.demand_mshr_misses::cpu0.itb.walker 6 # number of demand (read+write) MSHR misses 3052system.l2c.demand_mshr_misses::cpu0.inst 3733 # number of demand (read+write) MSHR misses 3053system.l2c.demand_mshr_misses::cpu0.data 16398 # number of demand (read+write) MSHR misses 3054system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164261 # number of demand (read+write) MSHR misses |
| 3037system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses 3038system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses | 3055system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses 3056system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses |
| 3039system.l2c.demand_mshr_misses::cpu1.inst 481 # number of demand (read+write) MSHR misses 3040system.l2c.demand_mshr_misses::cpu1.data 8604 # number of demand (read+write) MSHR misses 3041system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20997 # number of demand (read+write) MSHR misses 3042system.l2c.demand_mshr_misses::total 214565 # number of demand (read+write) MSHR misses | 3057system.l2c.demand_mshr_misses::cpu1.inst 477 # number of demand (read+write) MSHR misses 3058system.l2c.demand_mshr_misses::cpu1.data 8592 # number of demand (read+write) MSHR misses 3059system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20983 # number of demand (read+write) MSHR misses 3060system.l2c.demand_mshr_misses::total 214495 # number of demand (read+write) MSHR misses |
| 3043system.l2c.overall_mshr_misses::cpu0.dtb.walker 34 # number of overall MSHR misses | 3061system.l2c.overall_mshr_misses::cpu0.dtb.walker 34 # number of overall MSHR misses |
| 3044system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses 3045system.l2c.overall_mshr_misses::cpu0.inst 3728 # number of overall MSHR misses 3046system.l2c.overall_mshr_misses::cpu0.data 16423 # number of overall MSHR misses 3047system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164282 # number of overall MSHR misses | 3062system.l2c.overall_mshr_misses::cpu0.itb.walker 6 # number of overall MSHR misses 3063system.l2c.overall_mshr_misses::cpu0.inst 3733 # number of overall MSHR misses 3064system.l2c.overall_mshr_misses::cpu0.data 16398 # number of overall MSHR misses 3065system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164261 # number of overall MSHR misses |
| 3048system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses 3049system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses | 3066system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses 3067system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses |
| 3050system.l2c.overall_mshr_misses::cpu1.inst 481 # number of overall MSHR misses 3051system.l2c.overall_mshr_misses::cpu1.data 8604 # number of overall MSHR misses 3052system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 20997 # number of overall MSHR misses 3053system.l2c.overall_mshr_misses::total 214565 # number of overall MSHR misses 3054system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of ReadReq MSHR miss cycles 3055system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 312500 # number of ReadReq MSHR miss cycles 3056system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 304401246 # number of ReadReq MSHR miss cycles 3057system.l2c.ReadReq_mshr_miss_latency::cpu0.data 656530744 # number of ReadReq MSHR miss cycles 3058system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16993327084 # number of ReadReq MSHR miss cycles 3059system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 644500 # number of ReadReq MSHR miss cycles 3060system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 3061system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 43489500 # number of ReadReq MSHR miss cycles 3062system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105535000 # number of ReadReq MSHR miss cycles 3063system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2275742147 # number of ReadReq MSHR miss cycles 3064system.l2c.ReadReq_mshr_miss_latency::total 20382351471 # number of ReadReq MSHR miss cycles 3065system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 89515758 # number of UpgradeReq MSHR miss cycles 3066system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28874331 # number of UpgradeReq MSHR miss cycles 3067system.l2c.UpgradeReq_mshr_miss_latency::total 118390089 # number of UpgradeReq MSHR miss cycles 3068system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7686202 # number of SCUpgradeReq MSHR miss cycles 3069system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12118693 # number of SCUpgradeReq MSHR miss cycles 3070system.l2c.SCUpgradeReq_mshr_miss_latency::total 19804895 # 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number of demand (read+write) MSHR miss cycles 3081system.l2c.demand_mshr_miss_latency::cpu1.inst 43489500 # number of demand (read+write) MSHR miss cycles 3082system.l2c.demand_mshr_miss_latency::cpu1.data 576524766 # number of demand (read+write) MSHR miss cycles 3083system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2275742147 # number of demand (read+write) MSHR miss cycles 3084system.l2c.demand_mshr_miss_latency::total 21469345572 # number of demand (read+write) MSHR miss cycles 3085system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles 3086system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 312500 # number of overall MSHR miss cycles 3087system.l2c.overall_mshr_miss_latency::cpu0.inst 304401246 # number of overall MSHR miss cycles 3088system.l2c.overall_mshr_miss_latency::cpu0.data 1272535079 # number of overall MSHR miss cycles 3089system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16993327084 # number of overall MSHR miss cycles 3090system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 644500 # 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number of demand (read+write) MSHR miss cycles 3094system.l2c.demand_mshr_miss_latency::cpu0.inst 305475493 # number of demand (read+write) MSHR miss cycles 3095system.l2c.demand_mshr_miss_latency::cpu0.data 1283616313 # number of demand (read+write) MSHR miss cycles 3096system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16992433103 # number of demand (read+write) MSHR miss cycles 3097system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 638750 # number of demand (read+write) MSHR miss cycles 3098system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 305500 # number of demand (read+write) MSHR miss cycles 3099system.l2c.demand_mshr_miss_latency::cpu1.inst 41657500 # number of demand (read+write) MSHR miss cycles 3100system.l2c.demand_mshr_miss_latency::cpu1.data 577402763 # number of demand (read+write) MSHR miss cycles 3101system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2271307905 # number of demand (read+write) MSHR miss cycles 3102system.l2c.demand_mshr_miss_latency::total 21475537827 # number of demand (read+write) MSHR miss cycles 3103system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2325500 # number of overall MSHR miss cycles 3104system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 375000 # number of overall MSHR miss cycles 3105system.l2c.overall_mshr_miss_latency::cpu0.inst 305475493 # number of overall MSHR miss cycles 3106system.l2c.overall_mshr_miss_latency::cpu0.data 1283616313 # number of overall MSHR miss cycles 3107system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16992433103 # number of overall MSHR miss cycles 3108system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 638750 # number of overall MSHR miss cycles 3109system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 305500 # number of overall MSHR miss cycles 3110system.l2c.overall_mshr_miss_latency::cpu1.inst 41657500 # number of overall MSHR miss cycles 3111system.l2c.overall_mshr_miss_latency::cpu1.data 577402763 # number of overall MSHR miss cycles 3112system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2271307905 # number of overall MSHR miss cycles 3113system.l2c.overall_mshr_miss_latency::total 21475537827 # number of overall MSHR miss cycles |
| 3096system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles | 3114system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles |
| 3097system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686344747 # number of ReadReq MSHR uncacheable cycles | 3115system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686294748 # number of ReadReq MSHR uncacheable cycles |
| 3098system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles | 3116system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles |
| 3099system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919845500 # number of ReadReq MSHR uncacheable cycles 3100system.l2c.ReadReq_mshr_uncacheable_latency::total 5770622747 # number of ReadReq MSHR uncacheable cycles 3101system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713919500 # number of WriteReq MSHR uncacheable cycles 3102system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535238000 # number of WriteReq MSHR uncacheable cycles 3103system.l2c.WriteReq_mshr_uncacheable_latency::total 4249157500 # number of WriteReq MSHR uncacheable cycles | 3117system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919867500 # number of ReadReq MSHR uncacheable cycles 3118system.l2c.ReadReq_mshr_uncacheable_latency::total 5770594748 # number of ReadReq MSHR uncacheable cycles 3119system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713847001 # number of WriteReq MSHR uncacheable cycles 3120system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535209500 # number of WriteReq MSHR uncacheable cycles 3121system.l2c.WriteReq_mshr_uncacheable_latency::total 4249056501 # number of WriteReq MSHR uncacheable cycles |
| 3104system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles | 3122system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles |
| 3105system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400264247 # number of overall MSHR uncacheable cycles | 3123system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400141749 # number of overall MSHR uncacheable cycles |
| 3106system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles | 3124system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles |
| 3107system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455083500 # number of overall MSHR uncacheable cycles 3108system.l2c.overall_mshr_uncacheable_latency::total 10019780247 # number of overall MSHR uncacheable cycles 3109system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.111111 # mshr miss rate for ReadReq accesses 3110system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.036232 # mshr miss rate for ReadReq accesses 3111system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.228965 # mshr miss rate for ReadReq accesses 3112system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181942 # mshr miss rate for ReadReq accesses 3113system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for ReadReq accesses 3114system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for ReadReq accesses 3115system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses 3116system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for ReadReq accesses 3117system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.107615 # mshr miss rate for ReadReq accesses 3118system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for ReadReq accesses 3119system.l2c.ReadReq_mshr_miss_rate::total 0.404480 # mshr miss rate for ReadReq accesses 3120system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430330 # mshr miss rate for UpgradeReq accesses 3121system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.798489 # mshr miss rate for UpgradeReq accesses 3122system.l2c.UpgradeReq_mshr_miss_rate::total 0.484867 # mshr miss rate for UpgradeReq accesses 3123system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.805376 # mshr miss rate for SCUpgradeReq accesses 3124system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.873822 # mshr miss rate for SCUpgradeReq accesses 3125system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.846254 # mshr miss rate for SCUpgradeReq accesses 3126system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.676483 # mshr miss rate for ReadExReq accesses 3127system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853996 # mshr miss rate for ReadExReq accesses 3128system.l2c.ReadExReq_mshr_miss_rate::total 0.751732 # mshr miss rate for ReadExReq accesses 3129system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.111111 # mshr miss rate for demand accesses 3130system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036232 # mshr miss rate for demand accesses 3131system.l2c.demand_mshr_miss_rate::cpu0.inst 0.228965 # mshr miss rate for demand accesses 3132system.l2c.demand_mshr_miss_rate::cpu0.data 0.278031 # mshr miss rate for demand accesses 3133system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for demand accesses 3134system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for demand accesses 3135system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses 3136system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for demand accesses 3137system.l2c.demand_mshr_miss_rate::cpu1.data 0.402432 # mshr miss rate for demand accesses 3138system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for demand accesses 3139system.l2c.demand_mshr_miss_rate::total 0.417956 # mshr miss rate for demand accesses 3140system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.111111 # mshr miss rate for overall accesses 3141system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036232 # mshr miss rate for overall accesses 3142system.l2c.overall_mshr_miss_rate::cpu0.inst 0.228965 # mshr miss rate for overall accesses 3143system.l2c.overall_mshr_miss_rate::cpu0.data 0.278031 # mshr miss rate for overall accesses 3144system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for overall accesses 3145system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for overall accesses 3146system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses 3147system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for overall accesses 3148system.l2c.overall_mshr_miss_rate::cpu1.data 0.402432 # mshr miss rate for overall accesses 3149system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for overall accesses 3150system.l2c.overall_mshr_miss_rate::total 0.417956 # mshr miss rate for overall accesses 3151system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency | 3125system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455077000 # number of overall MSHR uncacheable cycles 3126system.l2c.overall_mshr_uncacheable_latency::total 10019651249 # number of overall MSHR uncacheable cycles 3127system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.102719 # mshr miss rate for ReadReq accesses 3128system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for ReadReq accesses 3129system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229342 # mshr miss rate for ReadReq accesses 3130system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181973 # mshr miss rate for ReadReq accesses 3131system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474314 # mshr miss rate for ReadReq accesses 3132system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.114943 # mshr miss rate for ReadReq accesses 3133system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for ReadReq accesses 3134system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.102647 # mshr miss rate for ReadReq accesses 3135system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.105852 # mshr miss rate for ReadReq accesses 3136system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.322339 # mshr miss rate for ReadReq accesses 3137system.l2c.ReadReq_mshr_miss_rate::total 0.404316 # mshr miss rate for ReadReq accesses 3138system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.431183 # mshr miss rate for UpgradeReq accesses 3139system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.800224 # mshr miss rate for UpgradeReq accesses 3140system.l2c.UpgradeReq_mshr_miss_rate::total 0.485814 # mshr miss rate for UpgradeReq accesses 3141system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.800213 # mshr miss rate for SCUpgradeReq accesses 3142system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.878261 # mshr miss rate for SCUpgradeReq accesses 3143system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.846618 # mshr miss rate for SCUpgradeReq accesses 3144system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.677064 # mshr miss rate for ReadExReq accesses 3145system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854670 # mshr miss rate for ReadExReq accesses 3146system.l2c.ReadExReq_mshr_miss_rate::total 0.752427 # mshr miss rate for ReadExReq accesses 3147system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.102719 # mshr miss rate for demand accesses 3148system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for demand accesses 3149system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229342 # mshr miss rate for demand accesses 3150system.l2c.demand_mshr_miss_rate::cpu0.data 0.278055 # mshr miss rate for demand accesses 3151system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474314 # mshr miss rate for demand accesses 3152system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114943 # mshr miss rate for demand accesses 3153system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses 3154system.l2c.demand_mshr_miss_rate::cpu1.inst 0.102647 # mshr miss rate for demand accesses 3155system.l2c.demand_mshr_miss_rate::cpu1.data 0.399777 # mshr miss rate for demand accesses 3156system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.322339 # mshr miss rate for demand accesses 3157system.l2c.demand_mshr_miss_rate::total 0.417796 # mshr miss rate for demand accesses 3158system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.102719 # mshr miss rate for overall accesses 3159system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for overall accesses 3160system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229342 # mshr miss rate for overall accesses 3161system.l2c.overall_mshr_miss_rate::cpu0.data 0.278055 # mshr miss rate for overall accesses 3162system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474314 # mshr miss rate for overall accesses 3163system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114943 # mshr miss rate for overall accesses 3164system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for overall accesses 3165system.l2c.overall_mshr_miss_rate::cpu1.inst 0.102647 # mshr miss rate for overall accesses 3166system.l2c.overall_mshr_miss_rate::cpu1.data 0.399777 # mshr miss rate for overall accesses 3167system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.322339 # mshr miss rate for overall accesses 3168system.l2c.overall_mshr_miss_rate::total 0.417796 # mshr miss rate for overall accesses 3169system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824 # average ReadReq mshr miss latency |
| 3152system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 3170system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 3153system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average ReadReq mshr miss latency 3154system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75820.619471 # average ReadReq mshr miss latency 3155system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average ReadReq mshr miss latency 3156system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average ReadReq mshr miss latency 3157system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 3158system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average ReadReq mshr miss latency 3159system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75815.373563 # average ReadReq mshr miss latency 3160system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average ReadReq mshr miss latency 3161system.l2c.ReadReq_avg_mshr_miss_latency::total 102121.617279 # average ReadReq mshr miss latency 3162system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10123.926487 # average UpgradeReq mshr miss latency 3163system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10120.690852 # average UpgradeReq mshr miss latency 3164system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10123.137153 # average UpgradeReq mshr miss latency 3165system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10261.951936 # average SCUpgradeReq mshr miss latency 3166system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.006639 # average SCUpgradeReq mshr miss latency 3167system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10135.565507 # average SCUpgradeReq mshr miss latency 3168system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79341.104456 # average ReadExReq mshr miss latency 3169system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65306.401276 # average ReadExReq mshr miss latency 3170system.l2c.ReadExReq_avg_mshr_miss_latency::total 72582.405248 # average ReadExReq mshr miss latency 3171system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency | 3171system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81831.099116 # average ReadReq mshr miss latency 3172system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76970.747485 # average ReadReq mshr miss latency 3173system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638 # average ReadReq mshr miss latency 3174system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63875 # average ReadReq mshr miss latency 3175system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 305500 # average ReadReq mshr miss latency 3176system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 87332.285115 # average ReadReq mshr miss latency 3177system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75969.428365 # average ReadReq mshr miss latency 3178system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309 # average ReadReq mshr miss latency 3179system.l2c.ReadReq_avg_mshr_miss_latency::total 102163.161014 # average ReadReq mshr miss latency 3180system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.617657 # average UpgradeReq mshr miss latency 3181system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10125.469580 # average UpgradeReq mshr miss latency 3182system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10150.534828 # average UpgradeReq mshr miss latency 3183system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10408.637450 # average SCUpgradeReq mshr miss latency 3184system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.822607 # average SCUpgradeReq mshr miss latency 3185system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10198.424936 # average SCUpgradeReq mshr miss latency 3186system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79738.846045 # average ReadExReq mshr miss latency 3187system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65521.915811 # average ReadExReq mshr miss latency 3188system.l2c.ReadExReq_avg_mshr_miss_latency::total 72886.511866 # average ReadExReq mshr miss latency 3189system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824 # average overall mshr miss latency |
| 3172system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 3190system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 3173system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency 3174system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency 3175system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency 3176system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency 3177system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 3178system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency 3179system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency 3180system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency 3181system.l2c.demand_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency 3182system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency | 3191system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81831.099116 # average overall mshr miss latency 3192system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78278.833577 # average overall mshr miss latency 3193system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638 # average overall mshr miss latency 3194system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63875 # average overall mshr miss latency 3195system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 305500 # average overall mshr miss latency 3196system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 87332.285115 # average overall mshr miss latency 3197system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67202.369995 # average overall mshr miss latency 3198system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309 # average overall mshr miss latency 3199system.l2c.demand_avg_mshr_miss_latency::total 100121.391300 # average overall mshr miss latency 3200system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824 # average overall mshr miss latency |
| 3183system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 3201system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 3184system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency 3185system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency 3186system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency 3187system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency 3188system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 3189system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency 3190system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency 3191system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency 3192system.l2c.overall_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency | 3202system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81831.099116 # average overall mshr miss latency 3203system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78278.833577 # average overall mshr miss latency 3204system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638 # average overall mshr miss latency 3205system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63875 # average overall mshr miss latency 3206system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 305500 # average overall mshr miss latency 3207system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 87332.285115 # average overall mshr miss latency 3208system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67202.369995 # average overall mshr miss latency 3209system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309 # average overall mshr miss latency 3210system.l2c.overall_avg_mshr_miss_latency::total 100121.391300 # average overall mshr miss latency |
| 3193system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3194system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3195system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3196system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3197system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3198system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3199system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3200system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3201system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3202system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3203system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3204system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3205system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3206system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 3211system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3212system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3213system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3214system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3215system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3216system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3217system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3218system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3219system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3220system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3221system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3222system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3223system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3224system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 3207system.membus.trans_dist::ReadReq 237839 # Transaction distribution 3208system.membus.trans_dist::ReadResp 237839 # Transaction distribution 3209system.membus.trans_dist::WriteReq 30978 # Transaction distribution 3210system.membus.trans_dist::WriteResp 30978 # Transaction distribution 3211system.membus.trans_dist::Writeback 113437 # Transaction distribution | 3225system.membus.trans_dist::ReadReq 237783 # Transaction distribution 3226system.membus.trans_dist::ReadResp 237783 # Transaction distribution 3227system.membus.trans_dist::WriteReq 30976 # Transaction distribution 3228system.membus.trans_dist::WriteResp 30976 # Transaction distribution 3229system.membus.trans_dist::Writeback 149598 # Transaction distribution |
| 3212system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 3213system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 3230system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 3231system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 3214system.membus.trans_dist::UpgradeReq 79519 # Transaction distribution 3215system.membus.trans_dist::SCUpgradeReq 40695 # Transaction distribution 3216system.membus.trans_dist::UpgradeResp 13753 # Transaction distribution 3217system.membus.trans_dist::ReadExReq 31200 # Transaction distribution 3218system.membus.trans_dist::ReadExResp 14872 # Transaction distribution | 3232system.membus.trans_dist::UpgradeReq 79558 # Transaction distribution 3233system.membus.trans_dist::SCUpgradeReq 40675 # Transaction distribution 3234system.membus.trans_dist::UpgradeResp 13780 # Transaction distribution 3235system.membus.trans_dist::ReadExReq 31194 # Transaction distribution 3236system.membus.trans_dist::ReadExResp 14873 # Transaction distribution |
| 3219system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) 3220system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) | 3237system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) 3238system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) |
| 3221system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) 3222system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708866 # Packet count per connected master and slave (bytes) 3223system.membus.pkt_count_system.l2c.mem_side::total 830616 # Packet count per connected master and slave (bytes) 3224system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) 3225system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) 3226system.membus.pkt_count::total 903326 # Packet count per connected master and slave (bytes) | 3239system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13732 # Packet count per connected master and slave (bytes) 3240system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708374 # Packet count per connected master and slave (bytes) 3241system.membus.pkt_count_system.l2c.mem_side::total 830114 # Packet count per connected master and slave (bytes) 3242system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108916 # Packet count per connected master and slave (bytes) 3243system.membus.pkt_count_system.iocache.mem_side::total 108916 # Packet count per connected master and slave (bytes) 3244system.membus.pkt_count::total 939030 # Packet count per connected master and slave (bytes) |
| 3227system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) 3228system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) | 3245system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) 3246system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) |
| 3229system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) 3230system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21055004 # Cumulative packet size per connected master and slave (bytes) 3231system.membus.pkt_size_system.l2c.mem_side::total 21245656 # Cumulative packet size per connected master and slave (bytes) 3232system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 3233system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 3234system.membus.pkt_size::total 23564952 # Cumulative packet size per connected master and slave (bytes) 3235system.membus.snoops 123021 # Total snoops (count) 3236system.membus.snoop_fanout::samples 500917 # Request fanout histogram | 3247system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27464 # Cumulative packet size per connected master and slave (bytes) 3248system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21024476 # Cumulative packet size per connected master and slave (bytes) 3249system.membus.pkt_size_system.l2c.mem_side::total 21215108 # Cumulative packet size per connected master and slave (bytes) 3250system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) 3251system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) 3252system.membus.pkt_size::total 25851588 # Cumulative packet size per connected master and slave (bytes) 3253system.membus.snoops 123388 # Total snoops (count) 3254system.membus.snoop_fanout::samples 537032 # Request fanout histogram |
| 3237system.membus.snoop_fanout::mean 1 # Request fanout histogram 3238system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3239system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3240system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 3255system.membus.snoop_fanout::mean 1 # Request fanout histogram 3256system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3257system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3258system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 3241system.membus.snoop_fanout::1 500917 100.00% 100.00% # Request fanout histogram | 3259system.membus.snoop_fanout::1 537032 100.00% 100.00% # Request fanout histogram |
| 3242system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3243system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3244system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3245system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3260system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3261system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3262system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3263system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3246system.membus.snoop_fanout::total 500917 # Request fanout histogram 3247system.membus.reqLayer0.occupancy 81243492 # Layer occupancy (ticks) | 3264system.membus.snoop_fanout::total 537032 # Request fanout histogram 3265system.membus.reqLayer0.occupancy 81237991 # Layer occupancy (ticks) |
| 3248system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3249system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) 3250system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3266system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3267system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) 3268system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3251system.membus.reqLayer2.occupancy 11638997 # Layer occupancy (ticks) | 3269system.membus.reqLayer2.occupancy 11614997 # Layer occupancy (ticks) |
| 3252system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3270system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3253system.membus.reqLayer5.occupancy 1642210248 # Layer occupancy (ticks) | 3271system.membus.reqLayer5.occupancy 1967612498 # Layer occupancy (ticks) |
| 3254system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) | 3272system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) |
| 3255system.membus.respLayer2.occupancy 2114152611 # Layer occupancy (ticks) | 3273system.membus.respLayer2.occupancy 2113693587 # Layer occupancy (ticks) |
| 3256system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 3274system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 3257system.membus.respLayer3.occupancy 38560639 # Layer occupancy (ticks) | 3275system.membus.respLayer3.occupancy 38580367 # Layer occupancy (ticks) |
| 3258system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3259system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3260system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3261system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3262system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3263system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3264system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3265system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 3282system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3283system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3284system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3285system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3286system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3287system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3288system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3289system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3276system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3277system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3278system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3279system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3280system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3281system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3282system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3283system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 3300system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3301system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3302system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3303system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3304system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3305system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3306system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3307system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3290system.toL2Bus.trans_dist::ReadReq 659694 # Transaction distribution 3291system.toL2Bus.trans_dist::ReadResp 659679 # Transaction distribution 3292system.toL2Bus.trans_dist::WriteReq 30978 # Transaction distribution 3293system.toL2Bus.trans_dist::WriteResp 30978 # Transaction distribution 3294system.toL2Bus.trans_dist::Writeback 252624 # Transaction distribution 3295system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution 3296system.toL2Bus.trans_dist::UpgradeReq 91840 # Transaction distribution 3297system.toL2Bus.trans_dist::SCUpgradeReq 41050 # Transaction distribution 3298system.toL2Bus.trans_dist::UpgradeResp 132890 # Transaction distribution 3299system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution 3300system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 3301system.toL2Bus.trans_dist::ReadExReq 40171 # Transaction distribution 3302system.toL2Bus.trans_dist::ReadExResp 40171 # Transaction distribution 3303system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1298541 # Packet count per connected master and slave (bytes) 3304system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426600 # Packet count per connected master and slave (bytes) 3305system.toL2Bus.pkt_count::total 1725141 # Packet count per connected master and slave (bytes) 3306system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40737982 # Cumulative packet size per connected master and slave (bytes) 3307system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8560538 # Cumulative packet size per connected master and slave (bytes) 3308system.toL2Bus.pkt_size::total 49298520 # Cumulative packet size per connected master and slave (bytes) 3309system.toL2Bus.snoops 291438 # Total snoops (count) 3310system.toL2Bus.snoop_fanout::samples 1083643 # Request fanout histogram 3311system.toL2Bus.snoop_fanout::mean 1.033661 # Request fanout histogram 3312system.toL2Bus.snoop_fanout::stdev 0.180356 # Request fanout histogram | 3308system.toL2Bus.trans_dist::ReadReq 659684 # Transaction distribution 3309system.toL2Bus.trans_dist::ReadResp 659669 # Transaction distribution 3310system.toL2Bus.trans_dist::WriteReq 30976 # Transaction distribution 3311system.toL2Bus.trans_dist::WriteResp 30976 # Transaction distribution 3312system.toL2Bus.trans_dist::Writeback 252625 # Transaction distribution 3313system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 3314system.toL2Bus.trans_dist::UpgradeReq 91886 # Transaction distribution 3315system.toL2Bus.trans_dist::SCUpgradeReq 41031 # Transaction distribution 3316system.toL2Bus.trans_dist::UpgradeResp 132917 # Transaction distribution 3317system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution 3318system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution 3319system.toL2Bus.trans_dist::ReadExReq 40129 # Transaction distribution 3320system.toL2Bus.trans_dist::ReadExResp 40129 # Transaction distribution 3321system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1298615 # Packet count per connected master and slave (bytes) 3322system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426559 # Packet count per connected master and slave (bytes) 3323system.toL2Bus.pkt_count::total 1725174 # Packet count per connected master and slave (bytes) 3324system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40738026 # Cumulative packet size per connected master and slave (bytes) 3325system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8562330 # Cumulative packet size per connected master and slave (bytes) 3326system.toL2Bus.pkt_size::total 49300356 # Cumulative packet size per connected master and slave (bytes) 3327system.toL2Bus.snoops 291348 # Total snoops (count) 3328system.toL2Bus.snoop_fanout::samples 1083611 # Request fanout histogram 3329system.toL2Bus.snoop_fanout::mean 1.033657 # Request fanout histogram 3330system.toL2Bus.snoop_fanout::stdev 0.180345 # Request fanout histogram |
| 3313system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3314system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 3331system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3332system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 3315system.toL2Bus.snoop_fanout::1 1047166 96.63% 96.63% # Request fanout histogram 3316system.toL2Bus.snoop_fanout::2 36477 3.37% 100.00% # Request fanout histogram | 3333system.toL2Bus.snoop_fanout::1 1047140 96.63% 96.63% # Request fanout histogram 3334system.toL2Bus.snoop_fanout::2 36471 3.37% 100.00% # Request fanout histogram |
| 3317system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3318system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3319system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3335system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3336system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3337system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3320system.toL2Bus.snoop_fanout::total 1083643 # Request fanout histogram 3321system.toL2Bus.reqLayer0.occupancy 1586607093 # Layer occupancy (ticks) | 3338system.toL2Bus.snoop_fanout::total 1083611 # Request fanout histogram 3339system.toL2Bus.reqLayer0.occupancy 1586551162 # Layer occupancy (ticks) |
| 3322system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 3323system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) 3324system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3340system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 3341system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) 3342system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3325system.toL2Bus.respLayer0.occupancy 2272505602 # Layer occupancy (ticks) | 3343system.toL2Bus.respLayer0.occupancy 2272414912 # Layer occupancy (ticks) |
| 3326system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 3344system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 3327system.toL2Bus.respLayer1.occupancy 846502909 # Layer occupancy (ticks) | 3345system.toL2Bus.respLayer1.occupancy 846278221 # Layer occupancy (ticks) |
| 3328system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3329system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 3346system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3347system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 3330system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed | 3348system.cpu0.kern.inst.quiesce 1853 # number of quiesce instructions executed |
| 3331system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3349system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 3332system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed | 3350system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed |
| 3333 3334---------- End Simulation Statistics ---------- | 3351 3352---------- End Simulation Statistics ---------- |