| stats.txt (10517:ba51f8572571) | stats.txt (10535:4ccec5baf82c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.824341 # Number of seconds simulated 4sim_ticks 2824340874000 # Number of ticks simulated 5final_tick 2824340874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.824366 # Number of seconds simulated 4sim_ticks 2824365837500 # Number of ticks simulated 5final_tick 2824365837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 96866 # Simulator instruction rate (inst/s) 8host_op_rate 117519 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2277239721 # Simulator tick rate (ticks/s) 10host_mem_usage 609056 # Number of bytes of host memory used 11host_seconds 1240.25 # Real time elapsed on the host 12sim_insts 120137719 # Number of instructions simulated 13sim_ops 145752951 # Number of ops (including micro ops) simulated | 7host_inst_rate 90810 # Simulator instruction rate (inst/s) 8host_op_rate 110172 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2134851185 # Simulator tick rate (ticks/s) 10host_mem_usage 669748 # Number of bytes of host memory used 11host_seconds 1322.98 # Real time elapsed on the host 12sim_insts 120140086 # Number of instructions simulated 13sim_ops 145755972 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | |
| 17system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 286816 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1046908 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 10513536 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 286496 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1047804 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10514048 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 549344 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 1344384 # Number of bytes read from this memory 27system.physmem.bytes_read::total 13777356 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 286816 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 318768 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 7262336 # Number of bytes written to this memory 32system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory | 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 32208 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 549728 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 1343808 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 13778252 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 286496 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 32208 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 318704 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 7259968 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 35system.physmem.bytes_written::total 9598416 # Number of bytes written to this memory 36system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 34system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 35system.physmem.bytes_written::total 9596048 # Number of bytes written to this memory |
| 37system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.inst 6727 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.data 16883 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu0.l2cache.prefetcher 164274 # Number of read requests responded to by this memory | 37system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 6722 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 16897 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 164282 # Number of read requests responded to by this memory |
| 42system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory | 41system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.data 8607 # Number of read requests responded to by this memory 46system.physmem.num_reads::cpu1.l2cache.prefetcher 21006 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 218132 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 113474 # Number of write requests responded to by this memory 49system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory | 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 570 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 20997 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 218146 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 113437 # Number of write requests responded to by this memory |
| 50system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 51system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 49system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 52system.physmem.num_writes::total 154134 # Number of write requests responded to by this memory 53system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 52system.physmem.num_writes::total 154097 # Number of write requests responded to by this memory |
| 54system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) |
| 55system.physmem.bw_read::cpu0.itb.walker 181 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.inst 101551 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.data 370673 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu0.l2cache.prefetcher 3722474 # Total read bandwidth from this memory (bytes/s) | 54system.physmem.bw_read::cpu0.itb.walker 113 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.inst 101437 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.data 370987 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.l2cache.prefetcher 3722623 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) |
| 60system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.inst 11313 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.data 194503 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu1.l2cache.prefetcher 475999 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 4878078 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 101551 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 11313 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 112865 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2571338 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::realview.ide 820841 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.inst 11404 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.data 194638 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.l2cache.prefetcher 475791 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 4878352 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 101437 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 11404 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 112841 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2570477 # Write bandwidth from this memory (bytes/s) |
| 70system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 69system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 72system.physmem.bw_write::total 3398462 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2571338 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 821181 # Total bandwidth to/from this memory (bytes/s) | 71system.physmem.bw_write::realview.ide 820834 # Write bandwidth from this memory (bytes/s) 72system.physmem.bw_write::total 3397594 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2570477 # Total bandwidth to/from this memory (bytes/s) |
| 75system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) | 74system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) |
| 76system.physmem.bw_total::cpu0.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.inst 101551 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.data 376942 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.l2cache.prefetcher 3722474 # Total bandwidth to/from this memory (bytes/s) | 75system.physmem.bw_total::cpu0.itb.walker 113 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.inst 101437 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.data 377256 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.l2cache.prefetcher 3722623 # Total bandwidth to/from this memory (bytes/s) |
| 80system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) | 79system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) |
| 81system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.inst 11313 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.data 194518 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.l2cache.prefetcher 475999 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 8276541 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 218132 # Number of read requests accepted 87system.physmem.writeReqs 154134 # Number of write requests accepted 88system.physmem.readBursts 218132 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 154134 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13944832 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue 92system.physmem.bytesWritten 9612032 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 13777356 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 9598416 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue | 80system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.inst 11404 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.data 194652 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.l2cache.prefetcher 475791 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::realview.ide 821174 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 8275946 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 218146 # Number of read requests accepted 87system.physmem.writeReqs 154097 # Number of write requests accepted 88system.physmem.readBursts 218146 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 154097 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13946112 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 15232 # Total number of bytes read from write queue 92system.physmem.bytesWritten 9610368 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 13778252 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 9596048 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 238 # Number of DRAM read bursts serviced by the write queue |
| 96system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one | 96system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one |
| 97system.physmem.neitherReadNorWriteReqs 13729 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 13731 # Per bank write bursts | 97system.physmem.neitherReadNorWriteReqs 13753 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 13737 # Per bank write bursts |
| 99system.physmem.perBankRdBursts::1 13637 # Per bank write bursts | 99system.physmem.perBankRdBursts::1 13637 # Per bank write bursts |
| 100system.physmem.perBankRdBursts::2 14382 # Per bank write bursts 101system.physmem.perBankRdBursts::3 14282 # Per bank write bursts 102system.physmem.perBankRdBursts::4 15946 # Per bank write bursts 103system.physmem.perBankRdBursts::5 13017 # Per bank write bursts 104system.physmem.perBankRdBursts::6 13909 # Per bank write bursts 105system.physmem.perBankRdBursts::7 13917 # Per bank write bursts 106system.physmem.perBankRdBursts::8 13612 # Per bank write bursts 107system.physmem.perBankRdBursts::9 13371 # Per bank write bursts 108system.physmem.perBankRdBursts::10 12787 # Per bank write bursts 109system.physmem.perBankRdBursts::11 11726 # Per bank write bursts 110system.physmem.perBankRdBursts::12 13349 # Per bank write bursts 111system.physmem.perBankRdBursts::13 14174 # Per bank write bursts 112system.physmem.perBankRdBursts::14 13344 # Per bank write bursts 113system.physmem.perBankRdBursts::15 12704 # Per bank write bursts 114system.physmem.perBankWrBursts::0 9692 # Per bank write bursts 115system.physmem.perBankWrBursts::1 9790 # Per bank write bursts 116system.physmem.perBankWrBursts::2 10299 # Per bank write bursts 117system.physmem.perBankWrBursts::3 9942 # Per bank write bursts 118system.physmem.perBankWrBursts::4 9060 # Per bank write bursts 119system.physmem.perBankWrBursts::5 9040 # Per bank write bursts 120system.physmem.perBankWrBursts::6 9465 # Per bank write bursts 121system.physmem.perBankWrBursts::7 9428 # Per bank write bursts | 100system.physmem.perBankRdBursts::2 14389 # Per bank write bursts 101system.physmem.perBankRdBursts::3 14286 # Per bank write bursts 102system.physmem.perBankRdBursts::4 15951 # Per bank write bursts 103system.physmem.perBankRdBursts::5 13008 # Per bank write bursts 104system.physmem.perBankRdBursts::6 13922 # Per bank write bursts 105system.physmem.perBankRdBursts::7 13905 # Per bank write bursts 106system.physmem.perBankRdBursts::8 13614 # Per bank write bursts 107system.physmem.perBankRdBursts::9 13369 # Per bank write bursts 108system.physmem.perBankRdBursts::10 12796 # Per bank write bursts 109system.physmem.perBankRdBursts::11 11719 # Per bank write bursts 110system.physmem.perBankRdBursts::12 13344 # Per bank write bursts 111system.physmem.perBankRdBursts::13 14168 # Per bank write bursts 112system.physmem.perBankRdBursts::14 13355 # Per bank write bursts 113system.physmem.perBankRdBursts::15 12708 # Per bank write bursts 114system.physmem.perBankWrBursts::0 9678 # Per bank write bursts 115system.physmem.perBankWrBursts::1 9778 # Per bank write bursts 116system.physmem.perBankWrBursts::2 10288 # Per bank write bursts 117system.physmem.perBankWrBursts::3 9945 # Per bank write bursts 118system.physmem.perBankWrBursts::4 9066 # Per bank write bursts 119system.physmem.perBankWrBursts::5 9050 # Per bank write bursts 120system.physmem.perBankWrBursts::6 9464 # Per bank write bursts 121system.physmem.perBankWrBursts::7 9420 # Per bank write bursts |
| 122system.physmem.perBankWrBursts::8 9418 # Per bank write bursts | 122system.physmem.perBankWrBursts::8 9418 # Per bank write bursts |
| 123system.physmem.perBankWrBursts::9 9301 # Per bank write bursts 124system.physmem.perBankWrBursts::10 9150 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8663 # Per bank write bursts 126system.physmem.perBankWrBursts::12 9463 # Per bank write bursts 127system.physmem.perBankWrBursts::13 9594 # Per bank write bursts 128system.physmem.perBankWrBursts::14 9165 # Per bank write bursts 129system.physmem.perBankWrBursts::15 8718 # Per bank write bursts | 123system.physmem.perBankWrBursts::9 9295 # Per bank write bursts 124system.physmem.perBankWrBursts::10 9149 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8660 # Per bank write bursts 126system.physmem.perBankWrBursts::12 9452 # Per bank write bursts 127system.physmem.perBankWrBursts::13 9588 # Per bank write bursts 128system.physmem.perBankWrBursts::14 9180 # Per bank write bursts 129system.physmem.perBankWrBursts::15 8731 # Per bank write bursts |
| 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 131system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 132system.physmem.totGap 2824339295000 # Total gap between requests | 131system.physmem.numWrRetry 6 # Number of times write queue was full causing retry 132system.physmem.totGap 2824364779500 # Total gap between requests |
| 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 559 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 3083 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) | 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 559 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 3083 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 139system.physmem.readPktSize::6 214462 # Read request sizes (log2) | 139system.physmem.readPktSize::6 214476 # Read request sizes (log2) |
| 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) | 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 146system.physmem.writePktSize::6 149698 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 53523 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 76682 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 20695 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 15255 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 11067 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 9733 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 8849 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 8196 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 7196 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 2474 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 1465 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 1103 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 647 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 481 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 305 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 208 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see | 146system.physmem.writePktSize::6 149661 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 53531 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 76693 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 20729 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 15217 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 11073 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 9725 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 8854 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 8206 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 7203 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 2475 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 1454 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 1095 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 641 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 479 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 300 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 216 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see |
| 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 194system.physmem.wrQLenPdf::15 2920 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3538 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4134 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 5600 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 6932 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7778 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8822 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9717 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10984 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 10866 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 10869 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 10841 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 11416 # What write queue length does an incoming req see | 194system.physmem.wrQLenPdf::15 2958 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3567 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4160 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 4854 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 5584 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 6912 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7776 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8777 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9674 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10921 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 10781 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 10780 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 10773 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 11406 # What write queue length does an incoming req see |
| 208system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see | 208system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see |
| 209system.physmem.wrQLenPdf::30 9280 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 9219 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 8573 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 815 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 368 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 234 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see | 209system.physmem.wrQLenPdf::30 9277 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 9241 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 8653 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 876 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 584 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 425 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 224 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 188 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see |
| 220system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see | 220system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see |
| 221system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 92801 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 253.842782 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 143.815283 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 308.388546 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 46919 50.56% 50.56% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 18870 20.33% 70.89% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6768 7.29% 78.19% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3705 3.99% 82.18% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3168 3.41% 85.59% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 2103 2.27% 87.86% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1242 1.34% 89.20% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1089 1.17% 90.37% # Bytes accessed per row activation | 221system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 147 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 88 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 79 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 23 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 92847 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 253.712882 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 143.703009 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 308.429657 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 46968 50.59% 50.59% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 18903 20.36% 70.95% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6762 7.28% 78.23% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3669 3.95% 82.18% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3165 3.41% 85.59% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 2101 2.26% 87.85% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1261 1.36% 89.21% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1081 1.16% 90.37% # Bytes accessed per row activation |
| 255system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation | 255system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation |
| 256system.physmem.bytesPerActivate::total 92801 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 7531 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 28.931483 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 528.461754 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 7530 99.99% 99.99% # Reads before turning the bus around for writes | 256system.physmem.bytesPerActivate::total 92847 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 7530 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 28.938645 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 528.498472 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 7529 99.99% 99.99% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes | 261system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 262system.physmem.rdPerTurnAround::total 7531 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 7531 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 19.942637 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.618581 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 11.035986 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 6139 81.52% 81.52% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 568 7.54% 89.06% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 91 1.21% 90.27% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 228 3.03% 93.29% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 184 2.44% 95.74% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 18 0.24% 95.98% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 26 0.35% 96.32% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 11 0.15% 96.47% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 33 0.44% 96.91% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 5 0.07% 96.97% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 10 0.13% 97.11% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 1 0.01% 97.12% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 156 2.07% 99.19% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 9 0.12% 99.31% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 1 0.01% 99.38% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 13 0.17% 99.55% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::88-91 3 0.04% 99.60% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 4 0.05% 99.65% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 1 0.01% 99.67% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 2 0.03% 99.73% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 4 0.05% 99.79% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 4 0.05% 99.84% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 6 0.08% 99.95% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::136-139 2 0.03% 99.97% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 7531 # Writes before turning the bus around for reads 299system.physmem.totQLat 8907181250 # Total ticks spent queuing 300system.physmem.totMemAccLat 12992581250 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 1089440000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 40879.63 # Average queueing delay per DRAM burst | 262system.physmem.rdPerTurnAround::total 7530 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 7530 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 19.941833 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.646034 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 10.689402 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 6119 81.26% 81.26% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 568 7.54% 88.80% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 91 1.21% 90.01% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 218 2.90% 92.91% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 217 2.88% 95.79% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 12 0.16% 95.95% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 20 0.27% 96.22% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 25 0.33% 96.55% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 26 0.35% 96.89% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 6 0.08% 97.08% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 5 0.07% 97.14% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 157 2.08% 99.23% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 8 0.11% 99.43% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 4 0.05% 99.48% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 13 0.17% 99.65% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.01% 99.67% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 1 0.01% 99.68% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 6 0.08% 99.76% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 2 0.03% 99.79% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::108-111 2 0.03% 99.81% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 7 0.09% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 7530 # Writes before turning the bus around for reads 295system.physmem.totQLat 8946488000 # Total ticks spent queuing 296system.physmem.totMemAccLat 13032263000 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 1089540000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 41056.26 # Average queueing delay per DRAM burst |
| 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 304system.physmem.avgMemAccLat 59629.63 # Average memory access latency per DRAM burst | 300system.physmem.avgMemAccLat 59806.26 # Average memory access latency per DRAM burst |
| 305system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.07 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 301system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.07 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 313system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 21.20 # Average write queue length when enqueuing 315system.physmem.readRowHits 185267 # Number of row buffer hits during reads 316system.physmem.writeRowHits 90008 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 85.03 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 59.92 # Row buffer hit rate for writes 319system.physmem.avgGap 7586884.90 # Average gap between requests 320system.physmem.pageHitRate 74.78 # Row buffer hit rate, read and write combined 321system.physmem.memoryStateTime::IDLE 2697410352000 # Time in different power states 322system.physmem.memoryStateTime::REF 94310840000 # Time in different power states | 309system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 23.08 # Average write queue length when enqueuing 311system.physmem.readRowHits 185273 # Number of row buffer hits during reads 312system.physmem.writeRowHits 89950 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 85.02 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 59.89 # Row buffer hit rate for writes 315system.physmem.avgGap 7587422.14 # Average gap between requests 316system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined 317system.physmem.memoryStateTime::IDLE 2697372741500 # Time in different power states 318system.physmem.memoryStateTime::REF 94311620000 # Time in different power states |
| 323system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 319system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 324system.physmem.memoryStateTime::ACT 32616675500 # Time in different power states | 320system.physmem.memoryStateTime::ACT 32676864750 # Time in different power states |
| 325system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 321system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 326system.physmem.actEnergy::0 364754880 # Energy for activate commands per rank (pJ) 327system.physmem.actEnergy::1 336820680 # Energy for activate commands per rank (pJ) 328system.physmem.preEnergy::0 199023000 # Energy for precharge commands per rank (pJ) 329system.physmem.preEnergy::1 183781125 # Energy for precharge commands per rank (pJ) 330system.physmem.readEnergy::0 880003800 # Energy for read commands per rank (pJ) 331system.physmem.readEnergy::1 819522600 # Energy for read commands per rank (pJ) 332system.physmem.writeEnergy::0 497119680 # Energy for write commands per rank (pJ) 333system.physmem.writeEnergy::1 476098560 # Energy for write commands per rank (pJ) 334system.physmem.refreshEnergy::0 184472003040 # Energy for refresh commands per rank (pJ) 335system.physmem.refreshEnergy::1 184472003040 # Energy for refresh commands per rank (pJ) 336system.physmem.actBackEnergy::0 78880301865 # Energy for active background per rank (pJ) 337system.physmem.actBackEnergy::1 78435436815 # Energy for active background per rank (pJ) 338system.physmem.preBackEnergy::0 1625409465000 # Energy for precharge background per rank (pJ) 339system.physmem.preBackEnergy::1 1625799697500 # Energy for precharge background per rank (pJ) 340system.physmem.totalEnergy::0 1890702671265 # Total energy per rank (pJ) 341system.physmem.totalEnergy::1 1890523360320 # Total energy per rank (pJ) 342system.physmem.averagePower::0 669.432189 # Core power per rank (mW) 343system.physmem.averagePower::1 669.368701 # Core power per rank (mW) | 322system.physmem.actEnergy::0 364906080 # Energy for activate commands per rank (pJ) 323system.physmem.actEnergy::1 337017240 # Energy for activate commands per rank (pJ) 324system.physmem.preEnergy::0 199105500 # Energy for precharge commands per rank (pJ) 325system.physmem.preEnergy::1 183888375 # Energy for precharge commands per rank (pJ) 326system.physmem.readEnergy::0 880113000 # Energy for read commands per rank (pJ) 327system.physmem.readEnergy::1 819569400 # Energy for read commands per rank (pJ) 328system.physmem.writeEnergy::0 496944720 # Energy for write commands per rank (pJ) 329system.physmem.writeEnergy::1 476105040 # Energy for write commands per rank (pJ) 330system.physmem.refreshEnergy::0 184473528720 # Energy for refresh commands per rank (pJ) 331system.physmem.refreshEnergy::1 184473528720 # Energy for refresh commands per rank (pJ) 332system.physmem.actBackEnergy::0 78935898240 # Energy for active background per rank (pJ) 333system.physmem.actBackEnergy::1 78466357035 # Energy for active background per rank (pJ) 334system.physmem.preBackEnergy::0 1625374711500 # Energy for precharge background per rank (pJ) 335system.physmem.preBackEnergy::1 1625786589750 # Energy for precharge background per rank (pJ) 336system.physmem.totalEnergy::0 1890725207760 # Total energy per rank (pJ) 337system.physmem.totalEnergy::1 1890543055560 # Total energy per rank (pJ) 338system.physmem.averagePower::0 669.434632 # Core power per rank (mW) 339system.physmem.averagePower::1 669.370138 # Core power per rank (mW) |
| 344system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 350system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 351system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 353system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) | 340system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 346system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 347system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 349system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) |
| 362system.membus.trans_dist::ReadReq 237823 # Transaction distribution 363system.membus.trans_dist::ReadResp 237823 # Transaction distribution 364system.membus.trans_dist::WriteReq 30977 # Transaction distribution 365system.membus.trans_dist::WriteResp 30977 # Transaction distribution 366system.membus.trans_dist::Writeback 113474 # Transaction distribution 367system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 368system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 369system.membus.trans_dist::UpgradeReq 79489 # Transaction distribution 370system.membus.trans_dist::SCUpgradeReq 40661 # Transaction distribution 371system.membus.trans_dist::UpgradeResp 13729 # Transaction distribution 372system.membus.trans_dist::ReadExReq 31194 # Transaction distribution 373system.membus.trans_dist::ReadExResp 14874 # Transaction distribution 374system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) 375system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 376system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13738 # Packet count per connected master and slave (bytes) 377system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708779 # Packet count per connected master and slave (bytes) 378system.membus.pkt_count_system.l2c.mem_side::total 830527 # Packet count per connected master and slave (bytes) 379system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) 380system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) 381system.membus.pkt_count::total 903237 # Packet count per connected master and slave (bytes) 382system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) 383system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 384system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27476 # Cumulative packet size per connected master and slave (bytes) 385system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21056476 # Cumulative packet size per connected master and slave (bytes) 386system.membus.pkt_size_system.l2c.mem_side::total 21247122 # Cumulative packet size per connected master and slave (bytes) 387system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 388system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 389system.membus.pkt_size::total 23566418 # Cumulative packet size per connected master and slave (bytes) 390system.membus.snoops 122973 # Total snoops (count) 391system.membus.snoop_fanout::samples 500866 # Request fanout histogram 392system.membus.snoop_fanout::mean 1 # Request fanout histogram 393system.membus.snoop_fanout::stdev 0 # Request fanout histogram 394system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 395system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 396system.membus.snoop_fanout::1 500866 100.00% 100.00% # Request fanout histogram 397system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 398system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 399system.membus.snoop_fanout::min_value 1 # Request fanout histogram 400system.membus.snoop_fanout::max_value 1 # Request fanout histogram 401system.membus.snoop_fanout::total 500866 # Request fanout histogram 402system.membus.reqLayer0.occupancy 81235490 # Layer occupancy (ticks) 403system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 404system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) 405system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 406system.membus.reqLayer2.occupancy 11626497 # Layer occupancy (ticks) 407system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 408system.membus.reqLayer5.occupancy 1642596998 # Layer occupancy (ticks) 409system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 410system.membus.respLayer2.occupancy 2113984385 # Layer occupancy (ticks) 411system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 412system.membus.respLayer3.occupancy 38546403 # Layer occupancy (ticks) 413system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 414system.cpu_clk_domain.clock 500 # Clock period in ticks 415system.l2c.tags.replacements 153419 # number of replacements 416system.l2c.tags.tagsinuse 64440.075057 # Cycle average of tags in use 417system.l2c.tags.total_refs 521049 # Total number of references to valid blocks. 418system.l2c.tags.sampled_refs 218085 # Sample count of references to valid blocks. 419system.l2c.tags.avg_refs 2.389201 # Average number of references to valid blocks. 420system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 421system.l2c.tags.occ_blocks::writebacks 14106.989110 # Average occupied blocks per requestor 422system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.481706 # Average occupied blocks per requestor 423system.l2c.tags.occ_blocks::cpu0.itb.walker 2.879098 # Average occupied blocks per requestor 424system.l2c.tags.occ_blocks::cpu0.inst 1413.448081 # Average occupied blocks per requestor 425system.l2c.tags.occ_blocks::cpu0.data 2144.570039 # Average occupied blocks per requestor 426system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39278.457251 # Average occupied blocks per requestor 427system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.502209 # Average occupied blocks per requestor 428system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002709 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu1.inst 292.869735 # Average occupied blocks per requestor 430system.l2c.tags.occ_blocks::cpu1.data 885.757521 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6295.117598 # Average occupied blocks per requestor 432system.l2c.tags.occ_percent::writebacks 0.215256 # Average percentage of cache occupancy 433system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy 434system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy 435system.l2c.tags.occ_percent::cpu0.inst 0.021568 # Average percentage of cache occupancy 436system.l2c.tags.occ_percent::cpu0.data 0.032724 # Average percentage of cache occupancy 437system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599342 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy 439system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 440system.l2c.tags.occ_percent::cpu1.inst 0.004469 # Average percentage of cache occupancy 441system.l2c.tags.occ_percent::cpu1.data 0.013516 # Average percentage of cache occupancy 442system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096056 # Average percentage of cache occupancy 443system.l2c.tags.occ_percent::total 0.983278 # Average percentage of cache occupancy 444system.l2c.tags.occ_task_id_blocks::1022 44367 # Occupied blocks per task id 445system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 446system.l2c.tags.occ_task_id_blocks::1024 20280 # Occupied blocks per task id 447system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id 448system.l2c.tags.age_task_id_blocks_1022::3 7792 # Occupied blocks per task id 449system.l2c.tags.age_task_id_blocks_1022::4 36164 # Occupied blocks per task id 450system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 451system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 452system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 453system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 454system.l2c.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id 455system.l2c.tags.age_task_id_blocks_1024::3 4621 # Occupied blocks per task id 456system.l2c.tags.age_task_id_blocks_1024::4 15296 # Occupied blocks per task id 457system.l2c.tags.occ_task_id_percent::1022 0.676987 # Percentage of cache occupancy per task id 458system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id 459system.l2c.tags.occ_task_id_percent::1024 0.309448 # Percentage of cache occupancy per task id 460system.l2c.tags.tag_accesses 6602520 # Number of tag accesses 461system.l2c.tags.data_accesses 6602520 # Number of data accesses 462system.l2c.ReadReq_hits::cpu0.dtb.walker 282 # number of ReadReq hits 463system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits 464system.l2c.ReadReq_hits::cpu0.inst 12559 # number of ReadReq hits 465system.l2c.ReadReq_hits::cpu0.data 39006 # number of ReadReq hits 466system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182592 # number of ReadReq hits 467system.l2c.ReadReq_hits::cpu1.dtb.walker 97 # number of ReadReq hits 468system.l2c.ReadReq_hits::cpu1.itb.walker 55 # number of ReadReq hits 469system.l2c.ReadReq_hits::cpu1.inst 4109 # number of ReadReq hits 470system.l2c.ReadReq_hits::cpu1.data 11553 # number of ReadReq hits 471system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44326 # number of ReadReq hits 472system.l2c.ReadReq_hits::total 294701 # number of ReadReq hits 473system.l2c.Writeback_hits::writebacks 252802 # number of Writeback hits 474system.l2c.Writeback_hits::total 252802 # number of Writeback hits 475system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits 476system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits 477system.l2c.UpgradeReq_hits::total 12432 # number of UpgradeReq hits 478system.l2c.SCUpgradeReq_hits::cpu0.data 184 # number of SCUpgradeReq hits 479system.l2c.SCUpgradeReq_hits::cpu1.data 173 # number of SCUpgradeReq hits 480system.l2c.SCUpgradeReq_hits::total 357 # number of SCUpgradeReq hits 481system.l2c.ReadExReq_hits::cpu0.data 3642 # number of ReadExReq hits 482system.l2c.ReadExReq_hits::cpu1.data 1229 # number of ReadExReq hits 483system.l2c.ReadExReq_hits::total 4871 # number of ReadExReq hits 484system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits 485system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits 486system.l2c.demand_hits::cpu0.inst 12559 # number of demand (read+write) hits 487system.l2c.demand_hits::cpu0.data 42648 # number of demand (read+write) hits 488system.l2c.demand_hits::cpu0.l2cache.prefetcher 182592 # number of demand (read+write) hits 489system.l2c.demand_hits::cpu1.dtb.walker 97 # number of demand (read+write) hits 490system.l2c.demand_hits::cpu1.itb.walker 55 # number of demand (read+write) hits 491system.l2c.demand_hits::cpu1.inst 4109 # number of demand (read+write) hits 492system.l2c.demand_hits::cpu1.data 12782 # number of demand (read+write) hits 493system.l2c.demand_hits::cpu1.l2cache.prefetcher 44326 # number of demand (read+write) hits 494system.l2c.demand_hits::total 299572 # number of demand (read+write) hits 495system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits 496system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits 497system.l2c.overall_hits::cpu0.inst 12559 # number of overall hits 498system.l2c.overall_hits::cpu0.data 42648 # number of overall hits 499system.l2c.overall_hits::cpu0.l2cache.prefetcher 182592 # number of overall hits 500system.l2c.overall_hits::cpu1.dtb.walker 97 # number of overall hits 501system.l2c.overall_hits::cpu1.itb.walker 55 # number of overall hits 502system.l2c.overall_hits::cpu1.inst 4109 # number of overall hits 503system.l2c.overall_hits::cpu1.data 12782 # number of overall hits 504system.l2c.overall_hits::cpu1.l2cache.prefetcher 44326 # number of overall hits 505system.l2c.overall_hits::total 299572 # number of overall hits 506system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses 507system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses 508system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses 509system.l2c.ReadReq_misses::cpu0.data 8647 # number of ReadReq misses 510system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164277 # number of ReadReq misses 511system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses 512system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses 513system.l2c.ReadReq_misses::cpu1.inst 479 # number of ReadReq misses 514system.l2c.ReadReq_misses::cpu1.data 1383 # number of ReadReq misses 515system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21024 # number of ReadReq misses 516system.l2c.ReadReq_misses::total 199597 # number of ReadReq misses 517system.l2c.UpgradeReq_misses::cpu0.data 8851 # number of UpgradeReq misses 518system.l2c.UpgradeReq_misses::cpu1.data 2828 # number of UpgradeReq misses 519system.l2c.UpgradeReq_misses::total 11679 # number of UpgradeReq misses 520system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses 521system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses 522system.l2c.SCUpgradeReq_misses::total 1952 # number of SCUpgradeReq misses 523system.l2c.ReadExReq_misses::cpu0.data 7757 # number of ReadExReq misses 524system.l2c.ReadExReq_misses::cpu1.data 7215 # number of ReadExReq misses 525system.l2c.ReadExReq_misses::total 14972 # number of ReadExReq misses 526system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses 527system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses 528system.l2c.demand_misses::cpu0.inst 3733 # number of demand (read+write) misses 529system.l2c.demand_misses::cpu0.data 16404 # number of demand (read+write) misses 530system.l2c.demand_misses::cpu0.l2cache.prefetcher 164277 # number of demand (read+write) misses 531system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 532system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses 533system.l2c.demand_misses::cpu1.inst 479 # number of demand (read+write) misses 534system.l2c.demand_misses::cpu1.data 8598 # number of demand (read+write) misses 535system.l2c.demand_misses::cpu1.l2cache.prefetcher 21024 # number of demand (read+write) misses 536system.l2c.demand_misses::total 214569 # number of demand (read+write) misses 537system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses 538system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses 539system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses 540system.l2c.overall_misses::cpu0.data 16404 # number of overall misses 541system.l2c.overall_misses::cpu0.l2cache.prefetcher 164277 # number of overall misses 542system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 543system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses 544system.l2c.overall_misses::cpu1.inst 479 # number of overall misses 545system.l2c.overall_misses::cpu1.data 8598 # number of overall misses 546system.l2c.overall_misses::cpu1.l2cache.prefetcher 21024 # number of overall misses 547system.l2c.overall_misses::total 214569 # number of overall misses 548system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2727250 # number of ReadReq miss cycles 549system.l2c.ReadReq_miss_latency::cpu0.itb.walker 613750 # number of ReadReq miss cycles 550system.l2c.ReadReq_miss_latency::cpu0.inst 350075996 # number of ReadReq miss cycles 551system.l2c.ReadReq_miss_latency::cpu0.data 761569744 # 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number of ReadReq accesses(hits+misses) 596system.l2c.ReadReq_accesses::cpu1.itb.walker 57 # number of ReadReq accesses(hits+misses) 597system.l2c.ReadReq_accesses::cpu1.inst 4588 # number of ReadReq accesses(hits+misses) 598system.l2c.ReadReq_accesses::cpu1.data 12936 # number of ReadReq accesses(hits+misses) 599system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65350 # number of ReadReq accesses(hits+misses) 600system.l2c.ReadReq_accesses::total 494298 # number of ReadReq accesses(hits+misses) 601system.l2c.Writeback_accesses::writebacks 252802 # number of Writeback accesses(hits+misses) 602system.l2c.Writeback_accesses::total 252802 # number of Writeback accesses(hits+misses) 603system.l2c.UpgradeReq_accesses::cpu0.data 20556 # number of UpgradeReq accesses(hits+misses) 604system.l2c.UpgradeReq_accesses::cpu1.data 3555 # number of UpgradeReq accesses(hits+misses) 605system.l2c.UpgradeReq_accesses::total 24111 # number of UpgradeReq accesses(hits+misses) 606system.l2c.SCUpgradeReq_accesses::cpu0.data 933 # number of SCUpgradeReq accesses(hits+misses) 607system.l2c.SCUpgradeReq_accesses::cpu1.data 1376 # number of SCUpgradeReq accesses(hits+misses) 608system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) 609system.l2c.ReadExReq_accesses::cpu0.data 11399 # number of ReadExReq accesses(hits+misses) 610system.l2c.ReadExReq_accesses::cpu1.data 8444 # number of ReadExReq accesses(hits+misses) 611system.l2c.ReadExReq_accesses::total 19843 # number of ReadExReq accesses(hits+misses) 612system.l2c.demand_accesses::cpu0.dtb.walker 316 # number of demand (read+write) accesses 613system.l2c.demand_accesses::cpu0.itb.walker 130 # number of demand (read+write) accesses 614system.l2c.demand_accesses::cpu0.inst 16292 # number of demand (read+write) accesses 615system.l2c.demand_accesses::cpu0.data 59052 # number of demand (read+write) accesses 616system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346869 # number of demand (read+write) accesses 617system.l2c.demand_accesses::cpu1.dtb.walker 107 # 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number of overall (read+write) accesses 629system.l2c.overall_accesses::cpu1.itb.walker 57 # number of overall (read+write) accesses 630system.l2c.overall_accesses::cpu1.inst 4588 # number of overall (read+write) accesses 631system.l2c.overall_accesses::cpu1.data 21380 # number of overall (read+write) accesses 632system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65350 # number of overall (read+write) accesses 633system.l2c.overall_accesses::total 514141 # number of overall (read+write) accesses 634system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for ReadReq accesses 635system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.061538 # miss rate for ReadReq accesses 636system.l2c.ReadReq_miss_rate::cpu0.inst 0.229131 # miss rate for ReadReq accesses 637system.l2c.ReadReq_miss_rate::cpu0.data 0.181458 # miss rate for ReadReq accesses 638system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for ReadReq accesses 639system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.093458 # 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miss rate for demand accesses 664system.l2c.demand_miss_rate::total 0.417335 # miss rate for demand accesses 665system.l2c.overall_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for overall accesses 666system.l2c.overall_miss_rate::cpu0.itb.walker 0.061538 # miss rate for overall accesses 667system.l2c.overall_miss_rate::cpu0.inst 0.229131 # miss rate for overall accesses 668system.l2c.overall_miss_rate::cpu0.data 0.277789 # miss rate for overall accesses 669system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for overall accesses 670system.l2c.overall_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for overall accesses 671system.l2c.overall_miss_rate::cpu1.itb.walker 0.035088 # miss rate for overall accesses 672system.l2c.overall_miss_rate::cpu1.inst 0.104403 # miss rate for overall accesses 673system.l2c.overall_miss_rate::cpu1.data 0.402152 # miss rate for overall accesses 674system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for overall accesses 675system.l2c.overall_miss_rate::total 0.417335 # miss rate for overall accesses 676system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average ReadReq miss latency 677system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 76718.750000 # average ReadReq miss latency 678system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93778.729172 # average ReadReq miss latency 679system.l2c.ReadReq_avg_miss_latency::cpu0.data 88073.290621 # average ReadReq miss latency 680system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average ReadReq miss latency 681system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76825 # average ReadReq miss latency 682system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency 683system.l2c.ReadReq_avg_miss_latency::cpu1.inst 99243.736952 # average ReadReq miss latency 684system.l2c.ReadReq_avg_miss_latency::cpu1.data 88453.904555 # average ReadReq miss latency 685system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average ReadReq miss latency 686system.l2c.ReadReq_avg_miss_latency::total 114219.308061 # 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average overall miss latency 709system.l2c.overall_avg_miss_latency::cpu0.inst 93778.729172 # average overall miss latency 710system.l2c.overall_avg_miss_latency::cpu0.data 89782.014326 # average overall miss latency 711system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average overall miss latency 712system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76825 # average overall miss latency 713system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency 714system.l2c.overall_avg_miss_latency::cpu1.inst 99243.736952 # average overall miss latency 715system.l2c.overall_avg_miss_latency::cpu1.data 79702.341475 # average overall miss latency 716system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average overall miss latency 717system.l2c.overall_avg_miss_latency::total 112187.662859 # average overall miss latency 718system.l2c.blocked_cycles::no_mshrs 168 # number of cycles access was blocked 719system.l2c.blocked_cycles::no_targets 0 # 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number of SCUpgradeReq MSHR miss cycles 800system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12103692 # number of SCUpgradeReq MSHR miss cycles 801system.l2c.SCUpgradeReq_mshr_miss_latency::total 19777895 # number of SCUpgradeReq MSHR miss cycles 802system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 615195579 # number of ReadExReq MSHR miss cycles 803system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 471924516 # number of ReadExReq MSHR miss cycles 804system.l2c.ReadExReq_mshr_miss_latency::total 1087120095 # number of ReadExReq MSHR miss cycles 805system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of demand (read+write) MSHR miss cycles 806system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 513750 # number of demand (read+write) MSHR miss cycles 807system.l2c.demand_mshr_miss_latency::cpu0.inst 303960496 # number of demand (read+write) MSHR miss cycles 808system.l2c.demand_mshr_miss_latency::cpu0.data 1269353323 # number of demand (read+write) MSHR miss cycles 809system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of demand (read+write) MSHR miss cycles 810system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 643750 # number of demand (read+write) MSHR miss cycles 811system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 812system.l2c.demand_mshr_miss_latency::cpu1.inst 41455250 # number of demand (read+write) MSHR miss cycles 813system.l2c.demand_mshr_miss_latency::cpu1.data 577058766 # number of demand (read+write) MSHR miss cycles 814system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of demand (read+write) MSHR miss cycles 815system.l2c.demand_mshr_miss_latency::total 21430411326 # number of demand (read+write) MSHR miss cycles 816system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles 817system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 513750 # number of overall MSHR miss cycles 818system.l2c.overall_mshr_miss_latency::cpu0.inst 303960496 # number of overall MSHR miss cycles 819system.l2c.overall_mshr_miss_latency::cpu0.data 1269353323 # number of overall MSHR miss cycles 820system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of overall MSHR miss cycles 821system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 643750 # number of overall MSHR miss cycles 822system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 125000 # number of overall MSHR miss cycles 823system.l2c.overall_mshr_miss_latency::cpu1.inst 41455250 # number of overall MSHR miss cycles 824system.l2c.overall_mshr_miss_latency::cpu1.data 577058766 # number of overall MSHR miss cycles 825system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of overall MSHR miss cycles 826system.l2c.overall_mshr_miss_latency::total 21430411326 # number of overall MSHR miss cycles 827system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles 828system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686341747 # number of ReadReq MSHR uncacheable cycles 829system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles 830system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919844500 # number of ReadReq MSHR uncacheable cycles 831system.l2c.ReadReq_mshr_uncacheable_latency::total 5770618747 # number of ReadReq MSHR uncacheable cycles 832system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713885499 # number of WriteReq MSHR uncacheable cycles 833system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535420500 # number of WriteReq MSHR uncacheable cycles 834system.l2c.WriteReq_mshr_uncacheable_latency::total 4249305999 # number of WriteReq MSHR uncacheable cycles 835system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles 836system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400227246 # number of overall MSHR uncacheable cycles 837system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles 838system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455265000 # number of overall MSHR uncacheable cycles 839system.l2c.overall_mshr_uncacheable_latency::total 10019924746 # number of overall MSHR uncacheable cycles 840system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for ReadReq accesses 841system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for ReadReq accesses 842system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for ReadReq accesses 843system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181437 # mshr miss rate for ReadReq accesses 844system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for ReadReq accesses 845system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for ReadReq accesses 846system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for ReadReq accesses 847system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for ReadReq accesses 848system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.106911 # mshr miss rate for ReadReq accesses 849system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for ReadReq accesses 850system.l2c.ReadReq_mshr_miss_rate::total 0.403750 # mshr miss rate for ReadReq accesses 851system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430580 # mshr miss rate for UpgradeReq accesses 852system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795499 # mshr miss rate for UpgradeReq accesses 853system.l2c.UpgradeReq_mshr_miss_rate::total 0.484385 # mshr miss rate for UpgradeReq accesses 854system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.802787 # mshr miss rate for SCUpgradeReq accesses 855system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.874273 # mshr miss rate for SCUpgradeReq accesses 856system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845388 # mshr miss rate for SCUpgradeReq accesses 857system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.680498 # mshr miss rate for ReadExReq accesses 858system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854453 # mshr miss rate for ReadExReq accesses 859system.l2c.ReadExReq_mshr_miss_rate::total 0.754523 # mshr miss rate for ReadExReq accesses 860system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for demand accesses 861system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for demand accesses 862system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for demand accesses 863system.l2c.demand_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for demand accesses 864system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for demand accesses 865system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for demand accesses 866system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for demand accesses 867system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for demand accesses 868system.l2c.demand_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for demand accesses 869system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for demand accesses 870system.l2c.demand_mshr_miss_rate::total 0.417288 # mshr miss rate for demand accesses 871system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for overall accesses 872system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for overall accesses 873system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for overall accesses 874system.l2c.overall_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for overall accesses 875system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for overall accesses 876system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for overall accesses 877system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for overall accesses 878system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for overall accesses 879system.l2c.overall_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for overall accesses 880system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for overall accesses 881system.l2c.overall_mshr_miss_rate::total 0.417288 # mshr miss rate for overall accesses 882system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency 883system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average ReadReq mshr miss latency 884system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average ReadReq mshr miss latency 885system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75660.160074 # average ReadReq mshr miss latency 886system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average ReadReq mshr miss latency 887system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average ReadReq mshr miss latency 888system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 889system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average ReadReq mshr miss latency 890system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76018.980477 # average ReadReq mshr miss latency 891system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average ReadReq mshr miss latency 892system.l2c.ReadReq_avg_mshr_miss_latency::total 101934.085427 # average ReadReq mshr miss latency 893system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10125.044176 # average UpgradeReq mshr miss latency 894system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.776521 # average UpgradeReq mshr miss latency 895system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.136484 # average UpgradeReq mshr miss latency 896system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10245.931909 # average SCUpgradeReq mshr miss latency 897system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10061.256858 # average SCUpgradeReq mshr miss latency 898system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10132.118340 # average SCUpgradeReq mshr miss latency 899system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79308.441279 # average ReadExReq mshr miss latency 900system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65408.803326 # average ReadExReq mshr miss latency 901system.l2c.ReadExReq_avg_mshr_miss_latency::total 72610.212063 # average ReadExReq mshr miss latency 902system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency 903system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency 904system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency 905system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency 906system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency 907system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency 908system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 909system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency 910system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency 911system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency 912system.l2c.demand_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency 913system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency 914system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency 915system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency 916system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency 917system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency 918system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency 919system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 920system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency 921system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency 922system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency 923system.l2c.overall_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency 924system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 925system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 926system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 927system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 928system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 929system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 930system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 931system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 933system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 934system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 935system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 936system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 937system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 938system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 939system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 940system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 941system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 942system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 943system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 944system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 945system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 946system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 947system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 948system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 949system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 950system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 951system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 952system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 953system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 954system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 955system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 956system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 957system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 958system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 959system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 960system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 961system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 962system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 963system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 964system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 965system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 966system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 967system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 968system.realview.ethernet.droppedPackets 0 # number of packets dropped | |
| 969system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 970system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 971system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 972system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 973system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 974system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 358system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 359system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 360system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 361system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 362system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 363system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 975system.toL2Bus.trans_dist::ReadReq 660487 # Transaction distribution 976system.toL2Bus.trans_dist::ReadResp 660472 # Transaction distribution 977system.toL2Bus.trans_dist::WriteReq 30977 # Transaction distribution 978system.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution 979system.toL2Bus.trans_dist::Writeback 252802 # Transaction distribution 980system.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution 981system.toL2Bus.trans_dist::UpgradeReq 91823 # Transaction distribution 982system.toL2Bus.trans_dist::SCUpgradeReq 41018 # Transaction distribution 983system.toL2Bus.trans_dist::UpgradeResp 132841 # Transaction distribution 984system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution 985system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 986system.toL2Bus.trans_dist::ReadExReq 40090 # Transaction distribution 987system.toL2Bus.trans_dist::ReadExResp 40090 # Transaction distribution 988system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1299997 # Packet count per connected master and slave (bytes) 989system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426747 # Packet count per connected master and slave (bytes) 990system.toL2Bus.pkt_count::total 1726744 # Packet count per connected master and slave (bytes) 991system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40789878 # Cumulative packet size per connected master and slave (bytes) 992system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8569500 # Cumulative packet size per connected master and slave (bytes) 993system.toL2Bus.pkt_size::total 49359378 # Cumulative packet size per connected master and slave (bytes) 994system.toL2Bus.snoops 291335 # Total snoops (count) 995system.toL2Bus.snoop_fanout::samples 1084475 # Request fanout histogram 996system.toL2Bus.snoop_fanout::mean 1.033634 # Request fanout histogram 997system.toL2Bus.snoop_fanout::stdev 0.180285 # Request fanout histogram 998system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 999system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1000system.toL2Bus.snoop_fanout::1 1048000 96.64% 96.64% # Request fanout histogram 1001system.toL2Bus.snoop_fanout::2 36475 3.36% 100.00% # Request fanout histogram 1002system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1003system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1004system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1005system.toL2Bus.snoop_fanout::total 1084475 # Request fanout histogram 1006system.toL2Bus.reqLayer0.occupancy 1587731325 # Layer occupancy (ticks) 1007system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1008system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) 1009system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1010system.toL2Bus.respLayer0.occupancy 2275347621 # Layer occupancy (ticks) 1011system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1012system.toL2Bus.respLayer1.occupancy 846816900 # Layer occupancy (ticks) 1013system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1014system.iobus.trans_dist::ReadReq 31016 # Transaction distribution 1015system.iobus.trans_dist::ReadResp 31016 # Transaction distribution 1016system.iobus.trans_dist::WriteReq 59425 # Transaction distribution 1017system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1018system.iobus.trans_dist::WriteInvalidateReq 15 # Transaction distribution 1019system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1020system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1021system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1022system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1024system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1025system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1026system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1027system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1028system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1029system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1030system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1031system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1032system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1033system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1034system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1035system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1036system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1037system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1038system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1039system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1040system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) 1041system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) 1042system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) 1043system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes) 1044system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 1045system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1052system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1053system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1054system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1055system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1056system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1057system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1058system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1059system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1060system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1061system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1062system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1063system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1064system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1065system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) 1066system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) 1067system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) 1068system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes) 1069system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 1070system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1071system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1072system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1073system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1074system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1075system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1076system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1077system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1078system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1079system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1080system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1081system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1082system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1083system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1084system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1085system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1086system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1087system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1088system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1090system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1092system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1093system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1094system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1096system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1097system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1098system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1099system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1100system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1101system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1102system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1103system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1104system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1105system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1106system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1107system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1108system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1109system.iobus.reqLayer27.occupancy 326640327 # Layer occupancy (ticks) 1110system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1111system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1112system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1113system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 1114system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1115system.iobus.respLayer3.occupancy 36831597 # Layer occupancy (ticks) 1116system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1117system.cpu0.branchPred.lookups 24028098 # Number of BP lookups 1118system.cpu0.branchPred.condPredicted 15717962 # Number of conditional branches predicted 1119system.cpu0.branchPred.condIncorrect 977131 # Number of conditional branches incorrect 1120system.cpu0.branchPred.BTBLookups 14655901 # Number of BTB lookups 1121system.cpu0.branchPred.BTBHits 10773369 # Number of BTB hits | 364system.cpu0.branchPred.lookups 24027931 # Number of BP lookups 365system.cpu0.branchPred.condPredicted 15718166 # Number of conditional branches predicted 366system.cpu0.branchPred.condIncorrect 977317 # Number of conditional branches incorrect 367system.cpu0.branchPred.BTBLookups 14657289 # Number of BTB lookups 368system.cpu0.branchPred.BTBHits 10772949 # Number of BTB hits |
| 1122system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 369system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1123system.cpu0.branchPred.BTBHitPct 73.508746 # BTB Hit Percentage 1124system.cpu0.branchPred.usedRAS 3877913 # Number of times the RAS was used to get a target. 1125system.cpu0.branchPred.RASInCorrect 32441 # Number of incorrect RAS predictions. | 370system.cpu0.branchPred.BTBHitPct 73.498919 # BTB Hit Percentage 371system.cpu0.branchPred.usedRAS 3877670 # Number of times the RAS was used to get a target. 372system.cpu0.branchPred.RASInCorrect 32392 # Number of incorrect RAS predictions. 373system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 1126system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1127system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1128system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1129system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1130system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1131system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1132system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1133system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1141system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1142system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1143system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1144system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1145system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1146system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1147system.cpu0.dtb.inst_hits 0 # ITB inst hits 1148system.cpu0.dtb.inst_misses 0 # ITB inst misses | 374system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 375system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 376system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 377system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 378system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 379system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 380system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 381system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 389system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 395system.cpu0.dtb.inst_hits 0 # ITB inst hits 396system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1149system.cpu0.dtb.read_hits 17721911 # DTB read hits 1150system.cpu0.dtb.read_misses 56434 # DTB read misses 1151system.cpu0.dtb.write_hits 14647364 # DTB write hits 1152system.cpu0.dtb.write_misses 8710 # DTB write misses | 397system.cpu0.dtb.read_hits 17722563 # DTB read hits 398system.cpu0.dtb.read_misses 56347 # DTB read misses 399system.cpu0.dtb.write_hits 14648246 # DTB write hits 400system.cpu0.dtb.write_misses 8736 # DTB write misses |
| 1153system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1154system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1155system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1156system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 401system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 402system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 403system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 404system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1157system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB 1158system.cpu0.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions 1159system.cpu0.dtb.prefetch_faults 2358 # Number of TLB faults due to prefetch | 405system.cpu0.dtb.flush_entries 3529 # Number of entries that have been flushed from TLB 406system.cpu0.dtb.align_faults 316 # Number of TLB faults due to alignment restrictions 407system.cpu0.dtb.prefetch_faults 2360 # Number of TLB faults due to prefetch |
| 1160system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 408system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1161system.cpu0.dtb.perms_faults 855 # Number of TLB faults due to permissions restrictions 1162system.cpu0.dtb.read_accesses 17778345 # DTB read accesses 1163system.cpu0.dtb.write_accesses 14656074 # DTB write accesses | 409system.cpu0.dtb.perms_faults 858 # Number of TLB faults due to permissions restrictions 410system.cpu0.dtb.read_accesses 17778910 # DTB read accesses 411system.cpu0.dtb.write_accesses 14656982 # DTB write accesses |
| 1164system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 412system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1165system.cpu0.dtb.hits 32369275 # DTB hits 1166system.cpu0.dtb.misses 65144 # DTB misses 1167system.cpu0.dtb.accesses 32434419 # DTB accesses | 413system.cpu0.dtb.hits 32370809 # DTB hits 414system.cpu0.dtb.misses 65083 # DTB misses 415system.cpu0.dtb.accesses 32435892 # DTB accesses |
| 1168system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1169system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1170system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1171system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1172system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1173system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1174system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1175system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1181system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1182system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1183system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1184system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1185system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1186system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1187system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1188system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 416system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 417system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 418system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 419system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 420system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 421system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 422system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 423system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 429system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 430system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 431system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 432system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 433system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 434system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 435system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 436system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1189system.cpu0.itb.inst_hits 37749203 # ITB inst hits 1190system.cpu0.itb.inst_misses 10291 # ITB inst misses | 437system.cpu0.itb.inst_hits 37749898 # ITB inst hits 438system.cpu0.itb.inst_misses 10270 # ITB inst misses |
| 1191system.cpu0.itb.read_hits 0 # DTB read hits 1192system.cpu0.itb.read_misses 0 # DTB read misses 1193system.cpu0.itb.write_hits 0 # DTB write hits 1194system.cpu0.itb.write_misses 0 # DTB write misses 1195system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1196system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1197system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1198system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 439system.cpu0.itb.read_hits 0 # DTB read hits 440system.cpu0.itb.read_misses 0 # DTB read misses 441system.cpu0.itb.write_hits 0 # DTB write hits 442system.cpu0.itb.write_misses 0 # DTB write misses 443system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 444system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1199system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB | 447system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB |
| 1200system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1201system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1202system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 448system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 449system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 450system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1203system.cpu0.itb.perms_faults 1952 # Number of TLB faults due to permissions restrictions | 451system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions |
| 1204system.cpu0.itb.read_accesses 0 # DTB read accesses 1205system.cpu0.itb.write_accesses 0 # DTB write accesses | 452system.cpu0.itb.read_accesses 0 # DTB read accesses 453system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1206system.cpu0.itb.inst_accesses 37759494 # ITB inst accesses 1207system.cpu0.itb.hits 37749203 # DTB hits 1208system.cpu0.itb.misses 10291 # DTB misses 1209system.cpu0.itb.accesses 37759494 # DTB accesses 1210system.cpu0.numCycles 126930318 # number of cpu cycles simulated | 454system.cpu0.itb.inst_accesses 37760168 # ITB inst accesses 455system.cpu0.itb.hits 37749898 # DTB hits 456system.cpu0.itb.misses 10270 # DTB misses 457system.cpu0.itb.accesses 37760168 # DTB accesses 458system.cpu0.numCycles 126937172 # number of cpu cycles simulated |
| 1211system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1212system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 459system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 460system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1213system.cpu0.fetch.icacheStallCycles 18136746 # Number of cycles fetch is stalled on an Icache miss 1214system.cpu0.fetch.Insts 112711782 # Number of instructions fetch has processed 1215system.cpu0.fetch.Branches 24028098 # Number of branches that fetch encountered 1216system.cpu0.fetch.predictedBranches 14651282 # Number of branches that fetch has predicted taken 1217system.cpu0.fetch.Cycles 104771989 # Number of cycles fetch has run and was not squashing or blocked 1218system.cpu0.fetch.SquashCycles 2822564 # Number of cycles fetch has spent squashing 1219system.cpu0.fetch.TlbCycles 133376 # Number of cycles fetch has spent waiting for tlb 1220system.cpu0.fetch.MiscStallCycles 38789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1221system.cpu0.fetch.PendingTrapStallCycles 365072 # Number of stall cycles due to pending traps 1222system.cpu0.fetch.PendingQuiesceStallCycles 429907 # Number of stall cycles due to pending quiesce instructions 1223system.cpu0.fetch.IcacheWaitRetryStallCycles 37570 # Number of stall cycles due to full MSHR 1224system.cpu0.fetch.CacheLines 37749815 # Number of cache lines fetched 1225system.cpu0.fetch.IcacheSquashes 265004 # Number of outstanding Icache misses that were squashed 1226system.cpu0.fetch.ItlbSquashes 3918 # Number of outstanding ITLB misses that were squashed 1227system.cpu0.fetch.rateDist::samples 125324731 # Number of instructions fetched each cycle (Total) 1228system.cpu0.fetch.rateDist::mean 1.084977 # Number of instructions fetched each cycle (Total) 1229system.cpu0.fetch.rateDist::stdev 1.263079 # Number of instructions fetched each cycle (Total) | 461system.cpu0.fetch.icacheStallCycles 18140410 # Number of cycles fetch is stalled on an Icache miss 462system.cpu0.fetch.Insts 112713647 # Number of instructions fetch has processed 463system.cpu0.fetch.Branches 24027931 # Number of branches that fetch encountered 464system.cpu0.fetch.predictedBranches 14650619 # Number of branches that fetch has predicted taken 465system.cpu0.fetch.Cycles 104775763 # Number of cycles fetch has run and was not squashing or blocked 466system.cpu0.fetch.SquashCycles 2822832 # Number of cycles fetch has spent squashing 467system.cpu0.fetch.TlbCycles 131776 # Number of cycles fetch has spent waiting for tlb 468system.cpu0.fetch.MiscStallCycles 38634 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 469system.cpu0.fetch.PendingTrapStallCycles 364177 # Number of stall cycles due to pending traps 470system.cpu0.fetch.PendingQuiesceStallCycles 430173 # Number of stall cycles due to pending quiesce instructions 471system.cpu0.fetch.IcacheWaitRetryStallCycles 37568 # Number of stall cycles due to full MSHR 472system.cpu0.fetch.CacheLines 37750515 # Number of cache lines fetched 473system.cpu0.fetch.IcacheSquashes 265085 # Number of outstanding Icache misses that were squashed 474system.cpu0.fetch.ItlbSquashes 3932 # Number of outstanding ITLB misses that were squashed 475system.cpu0.fetch.rateDist::samples 125329917 # Number of instructions fetched each cycle (Total) 476system.cpu0.fetch.rateDist::mean 1.084963 # Number of instructions fetched each cycle (Total) 477system.cpu0.fetch.rateDist::stdev 1.263075 # Number of instructions fetched each cycle (Total) |
| 1230system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 478system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1231system.cpu0.fetch.rateDist::0 62770441 50.09% 50.09% # Number of instructions fetched each cycle (Total) 1232system.cpu0.fetch.rateDist::1 21460959 17.12% 67.21% # Number of instructions fetched each cycle (Total) 1233system.cpu0.fetch.rateDist::2 8766539 7.00% 74.21% # Number of instructions fetched each cycle (Total) 1234system.cpu0.fetch.rateDist::3 32326792 25.79% 100.00% # Number of instructions fetched each cycle (Total) | 479system.cpu0.fetch.rateDist::0 62773644 50.09% 50.09% # Number of instructions fetched each cycle (Total) 480system.cpu0.fetch.rateDist::1 21461872 17.12% 67.21% # Number of instructions fetched each cycle (Total) 481system.cpu0.fetch.rateDist::2 8766803 6.99% 74.21% # Number of instructions fetched each cycle (Total) 482system.cpu0.fetch.rateDist::3 32327598 25.79% 100.00% # Number of instructions fetched each cycle (Total) |
| 1235system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1236system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1237system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 483system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 484system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 485system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1238system.cpu0.fetch.rateDist::total 125324731 # Number of instructions fetched each cycle (Total) 1239system.cpu0.fetch.branchRate 0.189301 # Number of branch fetches per cycle 1240system.cpu0.fetch.rate 0.887982 # Number of inst fetches per cycle 1241system.cpu0.decode.IdleCycles 19209269 # Number of cycles decode is idle 1242system.cpu0.decode.BlockedCycles 58676701 # Number of cycles decode is blocked 1243system.cpu0.decode.RunCycles 41413260 # Number of cycles decode is running 1244system.cpu0.decode.UnblockCycles 4958284 # Number of cycles decode is unblocking 1245system.cpu0.decode.SquashCycles 1067217 # Number of cycles decode is squashing 1246system.cpu0.decode.BranchResolved 3055385 # Number of times decode resolved a branch 1247system.cpu0.decode.BranchMispred 348256 # Number of times decode detected a branch misprediction 1248system.cpu0.decode.DecodedInsts 110724808 # Number of instructions handled by decode 1249system.cpu0.decode.SquashedInsts 3997323 # Number of squashed instructions handled by decode 1250system.cpu0.rename.SquashCycles 1067217 # Number of cycles rename is squashing 1251system.cpu0.rename.IdleCycles 24959463 # Number of cycles rename is idle 1252system.cpu0.rename.BlockCycles 12008700 # Number of cycles rename is blocking 1253system.cpu0.rename.serializeStallCycles 36549302 # count of cycles rename stalled for serializing inst 1254system.cpu0.rename.RunCycles 40482992 # Number of cycles rename is running 1255system.cpu0.rename.UnblockCycles 10257057 # Number of cycles rename is unblocking 1256system.cpu0.rename.RenamedInsts 105644030 # Number of instructions processed by rename 1257system.cpu0.rename.SquashedInsts 1060860 # Number of squashed instructions processed by rename 1258system.cpu0.rename.ROBFullEvents 1434602 # Number of times rename has blocked due to ROB full 1259system.cpu0.rename.IQFullEvents 161076 # Number of times rename has blocked due to IQ full 1260system.cpu0.rename.LQFullEvents 61450 # Number of times rename has blocked due to LQ full 1261system.cpu0.rename.SQFullEvents 6058216 # Number of times rename has blocked due to SQ full 1262system.cpu0.rename.RenamedOperands 109726611 # Number of destination operands rename has renamed 1263system.cpu0.rename.RenameLookups 482367040 # Number of register rename lookups that rename has made 1264system.cpu0.rename.int_rename_lookups 120917485 # Number of integer rename lookups | 486system.cpu0.fetch.rateDist::total 125329917 # Number of instructions fetched each cycle (Total) 487system.cpu0.fetch.branchRate 0.189290 # Number of branch fetches per cycle 488system.cpu0.fetch.rate 0.887948 # Number of inst fetches per cycle 489system.cpu0.decode.IdleCycles 19211260 # Number of cycles decode is idle 490system.cpu0.decode.BlockedCycles 58677383 # Number of cycles decode is blocked 491system.cpu0.decode.RunCycles 41416135 # Number of cycles decode is running 492system.cpu0.decode.UnblockCycles 4957927 # Number of cycles decode is unblocking 493system.cpu0.decode.SquashCycles 1067212 # Number of cycles decode is squashing 494system.cpu0.decode.BranchResolved 3055574 # Number of times decode resolved a branch 495system.cpu0.decode.BranchMispred 348409 # Number of times decode detected a branch misprediction 496system.cpu0.decode.DecodedInsts 110727822 # Number of instructions handled by decode 497system.cpu0.decode.SquashedInsts 3998029 # Number of squashed instructions handled by decode 498system.cpu0.rename.SquashCycles 1067212 # Number of cycles rename is squashing 499system.cpu0.rename.IdleCycles 24961632 # Number of cycles rename is idle 500system.cpu0.rename.BlockCycles 12004838 # Number of cycles rename is blocking 501system.cpu0.rename.serializeStallCycles 36556596 # count of cycles rename stalled for serializing inst 502system.cpu0.rename.RunCycles 40485229 # Number of cycles rename is running 503system.cpu0.rename.UnblockCycles 10254410 # Number of cycles rename is unblocking 504system.cpu0.rename.RenamedInsts 105647594 # Number of instructions processed by rename 505system.cpu0.rename.SquashedInsts 1060765 # Number of squashed instructions processed by rename 506system.cpu0.rename.ROBFullEvents 1435224 # Number of times rename has blocked due to ROB full 507system.cpu0.rename.IQFullEvents 161199 # Number of times rename has blocked due to IQ full 508system.cpu0.rename.LQFullEvents 61281 # Number of times rename has blocked due to LQ full 509system.cpu0.rename.SQFullEvents 6055537 # Number of times rename has blocked due to SQ full 510system.cpu0.rename.RenamedOperands 109729609 # Number of destination operands rename has renamed 511system.cpu0.rename.RenameLookups 482383818 # Number of register rename lookups that rename has made 512system.cpu0.rename.int_rename_lookups 120922156 # Number of integer rename lookups |
| 1265system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups | 513system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups |
| 1266system.cpu0.rename.CommittedMaps 98135067 # Number of HB maps that are committed 1267system.cpu0.rename.UndoneMaps 11591541 # Number of HB maps that are undone due to squashing 1268system.cpu0.rename.serializingInsts 1228775 # count of serializing insts renamed 1269system.cpu0.rename.tempSerializingInsts 1087468 # count of temporary serializing insts renamed 1270system.cpu0.rename.skidInsts 12318365 # count of insts added to the skid buffer 1271system.cpu0.memDep0.insertedLoads 18735262 # Number of loads inserted to the mem dependence unit. 1272system.cpu0.memDep0.insertedStores 16202067 # Number of stores inserted to the mem dependence unit. 1273system.cpu0.memDep0.conflictingLoads 1700806 # Number of conflicting loads. 1274system.cpu0.memDep0.conflictingStores 2287265 # Number of conflicting stores. 1275system.cpu0.iq.iqInstsAdded 102683814 # Number of instructions added to the IQ (excludes non-spec) 1276system.cpu0.iq.iqNonSpecInstsAdded 1694438 # Number of non-speculative instructions added to the IQ 1277system.cpu0.iq.iqInstsIssued 100667981 # Number of instructions issued 1278system.cpu0.iq.iqSquashedInstsIssued 483835 # Number of squashed instructions issued 1279system.cpu0.iq.iqSquashedInstsExamined 9019913 # Number of squashed instructions iterated over during squash; mainly for profiling 1280system.cpu0.iq.iqSquashedOperandsExamined 22488132 # Number of squashed operands that are examined and possibly removed from graph 1281system.cpu0.iq.iqSquashedNonSpecRemoved 122848 # Number of squashed non-spec instructions that were removed 1282system.cpu0.iq.issued_per_cycle::samples 125324731 # Number of insts issued each cycle 1283system.cpu0.iq.issued_per_cycle::mean 0.803257 # Number of insts issued each cycle 1284system.cpu0.iq.issued_per_cycle::stdev 1.034844 # Number of insts issued each cycle | 514system.cpu0.rename.CommittedMaps 98138163 # Number of HB maps that are committed 515system.cpu0.rename.UndoneMaps 11591443 # Number of HB maps that are undone due to squashing 516system.cpu0.rename.serializingInsts 1228785 # count of serializing insts renamed 517system.cpu0.rename.tempSerializingInsts 1087461 # count of temporary serializing insts renamed 518system.cpu0.rename.skidInsts 12318010 # count of insts added to the skid buffer 519system.cpu0.memDep0.insertedLoads 18735902 # Number of loads inserted to the mem dependence unit. 520system.cpu0.memDep0.insertedStores 16202980 # Number of stores inserted to the mem dependence unit. 521system.cpu0.memDep0.conflictingLoads 1699572 # Number of conflicting loads. 522system.cpu0.memDep0.conflictingStores 2289990 # Number of conflicting stores. 523system.cpu0.iq.iqInstsAdded 102687216 # Number of instructions added to the IQ (excludes non-spec) 524system.cpu0.iq.iqNonSpecInstsAdded 1694558 # Number of non-speculative instructions added to the IQ 525system.cpu0.iq.iqInstsIssued 100671408 # Number of instructions issued 526system.cpu0.iq.iqSquashedInstsIssued 483936 # Number of squashed instructions issued 527system.cpu0.iq.iqSquashedInstsExamined 9020941 # Number of squashed instructions iterated over during squash; mainly for profiling 528system.cpu0.iq.iqSquashedOperandsExamined 22487287 # Number of squashed operands that are examined and possibly removed from graph 529system.cpu0.iq.iqSquashedNonSpecRemoved 122833 # Number of squashed non-spec instructions that were removed 530system.cpu0.iq.issued_per_cycle::samples 125329917 # Number of insts issued each cycle 531system.cpu0.iq.issued_per_cycle::mean 0.803251 # Number of insts issued each cycle 532system.cpu0.iq.issued_per_cycle::stdev 1.034851 # Number of insts issued each cycle |
| 1285system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 533system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1286system.cpu0.iq.issued_per_cycle::0 69182553 55.20% 55.20% # Number of insts issued each cycle 1287system.cpu0.iq.issued_per_cycle::1 23178514 18.49% 73.70% # Number of insts issued each cycle 1288system.cpu0.iq.issued_per_cycle::2 22516011 17.97% 91.66% # Number of insts issued each cycle 1289system.cpu0.iq.issued_per_cycle::3 9333204 7.45% 99.11% # Number of insts issued each cycle 1290system.cpu0.iq.issued_per_cycle::4 1114412 0.89% 100.00% # Number of insts issued each cycle 1291system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle | 534system.cpu0.iq.issued_per_cycle::0 69186063 55.20% 55.20% # Number of insts issued each cycle 535system.cpu0.iq.issued_per_cycle::1 23179586 18.49% 73.70% # Number of insts issued each cycle 536system.cpu0.iq.issued_per_cycle::2 22515563 17.97% 91.66% # Number of insts issued each cycle 537system.cpu0.iq.issued_per_cycle::3 9334163 7.45% 99.11% # Number of insts issued each cycle 538system.cpu0.iq.issued_per_cycle::4 1114503 0.89% 100.00% # Number of insts issued each cycle 539system.cpu0.iq.issued_per_cycle::5 39 0.00% 100.00% # Number of insts issued each cycle |
| 1292system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1293system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1294system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1295system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1296system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1297system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 540system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 541system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 542system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 543system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 544system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 545system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1298system.cpu0.iq.issued_per_cycle::total 125324731 # Number of insts issued each cycle | 546system.cpu0.iq.issued_per_cycle::total 125329917 # Number of insts issued each cycle |
| 1299system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 547system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1300system.cpu0.iq.fu_full::IntAlu 9379454 40.76% 40.76% # attempts to use FU when none available 1301system.cpu0.iq.fu_full::IntMult 82 0.00% 40.76% # attempts to use FU when none available 1302system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available 1303system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available 1304system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available 1305system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available 1306system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available 1307system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available 1308system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available 1309system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available 1310system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available 1311system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available 1312system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available 1313system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available 1314system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available 1315system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available 1316system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available 1317system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available 1318system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available 1319system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available 1320system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available 1321system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available 1322system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available 1323system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available 1324system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available 1325system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available 1326system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available 1327system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available 1328system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available 1329system.cpu0.iq.fu_full::MemRead 5581640 24.26% 65.02% # attempts to use FU when none available 1330system.cpu0.iq.fu_full::MemWrite 8050330 34.98% 100.00% # attempts to use FU when none available | 548system.cpu0.iq.fu_full::IntAlu 9379139 40.75% 40.75% # attempts to use FU when none available 549system.cpu0.iq.fu_full::IntMult 80 0.00% 40.75% # attempts to use FU when none available 550system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available 551system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available 552system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available 553system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available 554system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available 555system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available 556system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available 557system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available 558system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available 559system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available 560system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available 561system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available 562system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available 563system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available 564system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available 565system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available 566system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available 567system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available 568system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available 569system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available 570system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available 571system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available 572system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available 573system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available 574system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available 575system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available 576system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available 577system.cpu0.iq.fu_full::MemRead 5583986 24.26% 65.02% # attempts to use FU when none available 578system.cpu0.iq.fu_full::MemWrite 8051096 34.98% 100.00% # attempts to use FU when none available |
| 1331system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1332system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1333system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued | 579system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 580system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 581system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued |
| 1334system.cpu0.iq.FU_type_0::IntAlu 66408183 65.97% 65.97% # Type of FU issued 1335system.cpu0.iq.FU_type_0::IntMult 93140 0.09% 66.06% # Type of FU issued | 582system.cpu0.iq.FU_type_0::IntAlu 66410061 65.97% 65.97% # Type of FU issued 583system.cpu0.iq.FU_type_0::IntMult 93146 0.09% 66.06% # Type of FU issued |
| 1336system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued 1337system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued 1338system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 1339system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 1340system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 1341system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 1342system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 1343system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 1351system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 1352system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 1353system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 1354system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 1355system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 1356system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 1357system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 1358system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued | 584system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued 585system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued 586system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 587system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 588system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 589system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 590system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 591system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 599system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 600system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 601system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 602system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 603system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 604system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 605system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 606system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued |
| 1359system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued | 607system.cpu0.iq.FU_type_0::SimdFloatMisc 8111 0.01% 66.07% # Type of FU issued |
| 1360system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued 1361system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued 1362system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued | 608system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued 609system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued 610system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued |
| 1363system.cpu0.iq.FU_type_0::MemRead 18430252 18.31% 84.38% # Type of FU issued 1364system.cpu0.iq.FU_type_0::MemWrite 15726021 15.62% 100.00% # Type of FU issued | 611system.cpu0.iq.FU_type_0::MemRead 18430824 18.31% 84.38% # Type of FU issued 612system.cpu0.iq.FU_type_0::MemWrite 15726990 15.62% 100.00% # Type of FU issued |
| 1365system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1366system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 613system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 614system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1367system.cpu0.iq.FU_type_0::total 100667981 # Type of FU issued 1368system.cpu0.iq.rate 0.793096 # Inst issue rate 1369system.cpu0.iq.fu_busy_cnt 23011506 # FU busy when requested 1370system.cpu0.iq.fu_busy_rate 0.228588 # FU busy rate (busy events/executed inst) 1371system.cpu0.iq.int_inst_queue_reads 350124170 # Number of integer instruction queue reads 1372system.cpu0.iq.int_inst_queue_writes 113406012 # Number of integer instruction queue writes 1373system.cpu0.iq.int_inst_queue_wakeup_accesses 98579580 # Number of integer instruction queue wakeup accesses 1374system.cpu0.iq.fp_inst_queue_reads 31864 # Number of floating instruction queue reads | 615system.cpu0.iq.FU_type_0::total 100671408 # Type of FU issued 616system.cpu0.iq.rate 0.793081 # Inst issue rate 617system.cpu0.iq.fu_busy_cnt 23014301 # FU busy when requested 618system.cpu0.iq.fu_busy_rate 0.228608 # FU busy rate (busy events/executed inst) 619system.cpu0.iq.int_inst_queue_reads 350139117 # Number of integer instruction queue reads 620system.cpu0.iq.int_inst_queue_writes 113410576 # Number of integer instruction queue writes 621system.cpu0.iq.int_inst_queue_wakeup_accesses 98583429 # Number of integer instruction queue wakeup accesses 622system.cpu0.iq.fp_inst_queue_reads 31853 # Number of floating instruction queue reads |
| 1375system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes 1376system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses | 623system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes 624system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses |
| 1377system.cpu0.iq.int_alu_accesses 123656622 # Number of integer alu accesses 1378system.cpu0.iq.fp_alu_accesses 20592 # Number of floating point alu accesses 1379system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores | 625system.cpu0.iq.int_alu_accesses 123662855 # Number of integer alu accesses 626system.cpu0.iq.fp_alu_accesses 20581 # Number of floating point alu accesses 627system.cpu0.iew.lsq.thread0.forwLoads 365420 # Number of loads that had data forwarded from stores |
| 1380system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 628system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1381system.cpu0.iew.lsq.thread0.squashedLoads 2006492 # Number of loads squashed 1382system.cpu0.iew.lsq.thread0.ignoredResponses 2605 # Number of memory responses ignored because the instruction is squashed 1383system.cpu0.iew.lsq.thread0.memOrderViolation 19209 # Number of memory ordering violations 1384system.cpu0.iew.lsq.thread0.squashedStores 1022192 # Number of stores squashed | 629system.cpu0.iew.lsq.thread0.squashedLoads 2006460 # Number of loads squashed 630system.cpu0.iew.lsq.thread0.ignoredResponses 2583 # Number of memory responses ignored because the instruction is squashed 631system.cpu0.iew.lsq.thread0.memOrderViolation 19225 # Number of memory ordering violations 632system.cpu0.iew.lsq.thread0.squashedStores 1022371 # Number of stores squashed |
| 1385system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1386system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 633system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 634system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1387system.cpu0.iew.lsq.thread0.rescheduledLoads 106472 # Number of loads that were rescheduled 1388system.cpu0.iew.lsq.thread0.cacheBlocked 336634 # Number of times an access to memory failed due to the cache being blocked | 635system.cpu0.iew.lsq.thread0.rescheduledLoads 106487 # Number of loads that were rescheduled 636system.cpu0.iew.lsq.thread0.cacheBlocked 336614 # Number of times an access to memory failed due to the cache being blocked |
| 1389system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 637system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1390system.cpu0.iew.iewSquashCycles 1067217 # Number of cycles IEW is squashing 1391system.cpu0.iew.iewBlockCycles 1619268 # Number of cycles IEW is blocking 1392system.cpu0.iew.iewUnblockCycles 191305 # Number of cycles IEW is unblocking 1393system.cpu0.iew.iewDispatchedInsts 104552982 # Number of instructions dispatched to IQ | 638system.cpu0.iew.iewSquashCycles 1067212 # Number of cycles IEW is squashing 639system.cpu0.iew.iewBlockCycles 1617559 # Number of cycles IEW is blocking 640system.cpu0.iew.iewUnblockCycles 190582 # Number of cycles IEW is unblocking 641system.cpu0.iew.iewDispatchedInsts 104556500 # Number of instructions dispatched to IQ |
| 1394system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 642system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 1395system.cpu0.iew.iewDispLoadInsts 18735262 # Number of dispatched load instructions 1396system.cpu0.iew.iewDispStoreInsts 16202067 # Number of dispatched store instructions 1397system.cpu0.iew.iewDispNonSpecInsts 876141 # Number of dispatched non-speculative instructions 1398system.cpu0.iew.iewIQFullEvents 27204 # Number of times the IQ has become full, causing a stall 1399system.cpu0.iew.iewLSQFullEvents 140421 # Number of times the LSQ has become full, causing a stall 1400system.cpu0.iew.memOrderViolationEvents 19209 # Number of memory order violations 1401system.cpu0.iew.predictedTakenIncorrect 291739 # Number of branches that were predicted taken incorrectly 1402system.cpu0.iew.predictedNotTakenIncorrect 400527 # Number of branches that were predicted not taken incorrectly 1403system.cpu0.iew.branchMispredicts 692266 # Number of branch mispredicts detected at execute 1404system.cpu0.iew.iewExecutedInsts 99570429 # Number of executed instructions 1405system.cpu0.iew.iewExecLoadInsts 17973451 # Number of load instructions executed 1406system.cpu0.iew.iewExecSquashedInsts 1032544 # Number of squashed instructions skipped in execute | 643system.cpu0.iew.iewDispLoadInsts 18735902 # Number of dispatched load instructions 644system.cpu0.iew.iewDispStoreInsts 16202980 # Number of dispatched store instructions 645system.cpu0.iew.iewDispNonSpecInsts 876211 # Number of dispatched non-speculative instructions 646system.cpu0.iew.iewIQFullEvents 27258 # Number of times the IQ has become full, causing a stall 647system.cpu0.iew.iewLSQFullEvents 139659 # Number of times the LSQ has become full, causing a stall 648system.cpu0.iew.memOrderViolationEvents 19225 # Number of memory order violations 649system.cpu0.iew.predictedTakenIncorrect 291750 # Number of branches that were predicted taken incorrectly 650system.cpu0.iew.predictedNotTakenIncorrect 400567 # Number of branches that were predicted not taken incorrectly 651system.cpu0.iew.branchMispredicts 692317 # Number of branch mispredicts detected at execute 652system.cpu0.iew.iewExecutedInsts 99574081 # Number of executed instructions 653system.cpu0.iew.iewExecLoadInsts 17974103 # Number of load instructions executed 654system.cpu0.iew.iewExecSquashedInsts 1032379 # Number of squashed instructions skipped in execute |
| 1407system.cpu0.iew.exec_swp 0 # number of swp insts executed | 655system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 1408system.cpu0.iew.exec_nop 174730 # number of nop insts executed 1409system.cpu0.iew.exec_refs 33508210 # number of memory reference insts executed 1410system.cpu0.iew.exec_branches 16843179 # Number of branches executed 1411system.cpu0.iew.exec_stores 15534759 # Number of stores executed 1412system.cpu0.iew.exec_rate 0.784450 # Inst execution rate 1413system.cpu0.iew.wb_sent 99039643 # cumulative count of insts sent to commit 1414system.cpu0.iew.wb_count 98589303 # cumulative count of insts written-back 1415system.cpu0.iew.wb_producers 51320532 # num instructions producing a value 1416system.cpu0.iew.wb_consumers 84799978 # num instructions consuming a value | 656system.cpu0.iew.exec_nop 174726 # number of nop insts executed 657system.cpu0.iew.exec_refs 33509859 # number of memory reference insts executed 658system.cpu0.iew.exec_branches 16843488 # Number of branches executed 659system.cpu0.iew.exec_stores 15535756 # Number of stores executed 660system.cpu0.iew.exec_rate 0.784436 # Inst execution rate 661system.cpu0.iew.wb_sent 99043344 # cumulative count of insts sent to commit 662system.cpu0.iew.wb_count 98593152 # cumulative count of insts written-back 663system.cpu0.iew.wb_producers 51321674 # num instructions producing a value 664system.cpu0.iew.wb_consumers 84801576 # num instructions consuming a value |
| 1417system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 665system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1418system.cpu0.iew.wb_rate 0.776720 # insts written-back per cycle 1419system.cpu0.iew.wb_fanout 0.605195 # average fanout of values written-back | 666system.cpu0.iew.wb_rate 0.776708 # insts written-back per cycle 667system.cpu0.iew.wb_fanout 0.605197 # average fanout of values written-back |
| 1420system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 668system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1421system.cpu0.commit.commitSquashedInsts 8525678 # The number of squashed insts skipped by commit 1422system.cpu0.commit.commitNonSpecStalls 1571590 # The number of times commit has been forced to stall to communicate backwards 1423system.cpu0.commit.branchMispredicts 633066 # The number of times a branch was mispredicted 1424system.cpu0.commit.committed_per_cycle::samples 123570875 # Number of insts commited each cycle 1425system.cpu0.commit.committed_per_cycle::mean 0.768216 # Number of insts commited each cycle 1426system.cpu0.commit.committed_per_cycle::stdev 1.481246 # Number of insts commited each cycle | 669system.cpu0.commit.commitSquashedInsts 8525747 # The number of squashed insts skipped by commit 670system.cpu0.commit.commitNonSpecStalls 1571725 # The number of times commit has been forced to stall to communicate backwards 671system.cpu0.commit.branchMispredicts 633113 # The number of times a branch was mispredicted 672system.cpu0.commit.committed_per_cycle::samples 123576047 # Number of insts commited each cycle 673system.cpu0.commit.committed_per_cycle::mean 0.768210 # Number of insts commited each cycle 674system.cpu0.commit.committed_per_cycle::stdev 1.481297 # Number of insts commited each cycle |
| 1427system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 675system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1428system.cpu0.commit.committed_per_cycle::0 79246760 64.13% 64.13% # Number of insts commited each cycle 1429system.cpu0.commit.committed_per_cycle::1 24711613 20.00% 84.13% # Number of insts commited each cycle 1430system.cpu0.commit.committed_per_cycle::2 8248135 6.67% 90.80% # Number of insts commited each cycle 1431system.cpu0.commit.committed_per_cycle::3 3213746 2.60% 93.40% # Number of insts commited each cycle 1432system.cpu0.commit.committed_per_cycle::4 3439781 2.78% 96.19% # Number of insts commited each cycle 1433system.cpu0.commit.committed_per_cycle::5 1516341 1.23% 97.41% # Number of insts commited each cycle 1434system.cpu0.commit.committed_per_cycle::6 1141391 0.92% 98.34% # Number of insts commited each cycle 1435system.cpu0.commit.committed_per_cycle::7 534018 0.43% 98.77% # Number of insts commited each cycle 1436system.cpu0.commit.committed_per_cycle::8 1519090 1.23% 100.00% # Number of insts commited each cycle | 676system.cpu0.commit.committed_per_cycle::0 79251877 64.13% 64.13% # Number of insts commited each cycle 677system.cpu0.commit.committed_per_cycle::1 24711108 20.00% 84.13% # Number of insts commited each cycle 678system.cpu0.commit.committed_per_cycle::2 8248464 6.67% 90.80% # Number of insts commited each cycle 679system.cpu0.commit.committed_per_cycle::3 3214478 2.60% 93.40% # Number of insts commited each cycle 680system.cpu0.commit.committed_per_cycle::4 3439388 2.78% 96.19% # Number of insts commited each cycle 681system.cpu0.commit.committed_per_cycle::5 1513562 1.22% 97.41% # Number of insts commited each cycle 682system.cpu0.commit.committed_per_cycle::6 1143910 0.93% 98.34% # Number of insts commited each cycle 683system.cpu0.commit.committed_per_cycle::7 534023 0.43% 98.77% # Number of insts commited each cycle 684system.cpu0.commit.committed_per_cycle::8 1519237 1.23% 100.00% # Number of insts commited each cycle |
| 1437system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1438system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1439system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 685system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 686system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 687system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1440system.cpu0.commit.committed_per_cycle::total 123570875 # Number of insts commited each cycle 1441system.cpu0.commit.committedInsts 78899754 # Number of instructions committed 1442system.cpu0.commit.committedOps 94929142 # Number of ops (including micro ops) committed | 688system.cpu0.commit.committed_per_cycle::total 123576047 # Number of insts commited each cycle 689system.cpu0.commit.committedInsts 78902307 # Number of instructions committed 690system.cpu0.commit.committedOps 94932349 # Number of ops (including micro ops) committed |
| 1443system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 691system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 1444system.cpu0.commit.refs 31908645 # Number of memory references committed 1445system.cpu0.commit.loads 16728770 # Number of loads committed 1446system.cpu0.commit.membars 647107 # Number of memory barriers committed 1447system.cpu0.commit.branches 16205360 # Number of branches committed | 692system.cpu0.commit.refs 31910051 # Number of memory references committed 693system.cpu0.commit.loads 16729442 # Number of loads committed 694system.cpu0.commit.membars 647161 # Number of memory barriers committed 695system.cpu0.commit.branches 16205593 # Number of branches committed |
| 1448system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. | 696system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. |
| 1449system.cpu0.commit.int_insts 81878721 # Number of committed integer instructions. 1450system.cpu0.commit.function_calls 1929507 # Number of function calls committed. | 697system.cpu0.commit.int_insts 81881586 # Number of committed integer instructions. 698system.cpu0.commit.function_calls 1929479 # Number of function calls committed. |
| 1451system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 699system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 1452system.cpu0.commit.op_class_0::IntAlu 62921673 66.28% 66.28% # Class of committed instruction 1453system.cpu0.commit.op_class_0::IntMult 90715 0.10% 66.38% # Class of committed instruction | 700system.cpu0.commit.op_class_0::IntAlu 62923469 66.28% 66.28% # Class of committed instruction 701system.cpu0.commit.op_class_0::IntMult 90718 0.10% 66.38% # Class of committed instruction |
| 1454system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 1455system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 1456system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 1457system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 1458system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 1459system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 1460system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 1461system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 1469system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 1470system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 1471system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 1472system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 1473system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 1474system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 1475system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 1476system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction | 702system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 703system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 704system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 705system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 706system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 707system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 708system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 709system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 717system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 718system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 719system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 720system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 721system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 722system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 723system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 724system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction |
| 1477system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction | 725system.cpu0.commit.op_class_0::SimdFloatMisc 8111 0.01% 66.39% # Class of committed instruction |
| 1478system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction 1479system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction 1480system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction | 726system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction 727system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction 728system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction |
| 1481system.cpu0.commit.op_class_0::MemRead 16728770 17.62% 84.01% # Class of committed instruction 1482system.cpu0.commit.op_class_0::MemWrite 15179875 15.99% 100.00% # Class of committed instruction | 729system.cpu0.commit.op_class_0::MemRead 16729442 17.62% 84.01% # Class of committed instruction 730system.cpu0.commit.op_class_0::MemWrite 15180609 15.99% 100.00% # Class of committed instruction |
| 1483system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1484system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 731system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 732system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1485system.cpu0.commit.op_class_0::total 94929142 # Class of committed instruction 1486system.cpu0.commit.bw_lim_events 1519090 # number cycles where commit BW limit reached | 733system.cpu0.commit.op_class_0::total 94932349 # Class of committed instruction 734system.cpu0.commit.bw_lim_events 1519237 # number cycles where commit BW limit reached |
| 1487system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 735system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1488system.cpu0.rob.rob_reads 221323955 # The number of ROB reads 1489system.cpu0.rob.rob_writes 208662740 # The number of ROB writes 1490system.cpu0.timesIdled 109422 # Number of times that the entire CPU went into an idle state and unscheduled itself 1491system.cpu0.idleCycles 1605587 # Total number of cycles that the CPU has spent unscheduled due to idling 1492system.cpu0.quiesceCycles 5521751456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1493system.cpu0.committedInsts 78777703 # Number of Instructions Simulated 1494system.cpu0.committedOps 94807091 # Number of Ops (including micro ops) Simulated 1495system.cpu0.cpi 1.611247 # CPI: Cycles Per Instruction 1496system.cpu0.cpi_total 1.611247 # CPI: Total CPI of All Threads 1497system.cpu0.ipc 0.620637 # IPC: Instructions Per Cycle 1498system.cpu0.ipc_total 0.620637 # IPC: Total IPC of All Threads 1499system.cpu0.int_regfile_reads 110612001 # number of integer regfile reads 1500system.cpu0.int_regfile_writes 59736021 # number of integer regfile writes | 736system.cpu0.rob.rob_reads 221333052 # The number of ROB reads 737system.cpu0.rob.rob_writes 208669303 # The number of ROB writes 738system.cpu0.timesIdled 109478 # Number of times that the entire CPU went into an idle state and unscheduled itself 739system.cpu0.idleCycles 1607255 # Total number of cycles that the CPU has spent unscheduled due to idling 740system.cpu0.quiesceCycles 5521794529 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 741system.cpu0.committedInsts 78780256 # Number of Instructions Simulated 742system.cpu0.committedOps 94810298 # Number of Ops (including micro ops) Simulated 743system.cpu0.cpi 1.611282 # CPI: Cycles Per Instruction 744system.cpu0.cpi_total 1.611282 # CPI: Total CPI of All Threads 745system.cpu0.ipc 0.620624 # IPC: Instructions Per Cycle 746system.cpu0.ipc_total 0.620624 # IPC: Total IPC of All Threads 747system.cpu0.int_regfile_reads 110616528 # number of integer regfile reads 748system.cpu0.int_regfile_writes 59738270 # number of integer regfile writes |
| 1501system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads 1502system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes | 749system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads 750system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes |
| 1503system.cpu0.cc_regfile_reads 350763374 # number of cc regfile reads 1504system.cpu0.cc_regfile_writes 41072426 # number of cc regfile writes 1505system.cpu0.misc_regfile_reads 246706358 # number of misc regfile reads 1506system.cpu0.misc_regfile_writes 1224463 # number of misc regfile writes 1507system.cpu0.toL2Bus.trans_dist::ReadReq 2021709 # Transaction distribution 1508system.cpu0.toL2Bus.trans_dist::ReadResp 1920443 # Transaction distribution 1509system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution 1510system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution 1511system.cpu0.toL2Bus.trans_dist::Writeback 512971 # Transaction distribution 1512system.cpu0.toL2Bus.trans_dist::HardPFReq 647722 # Transaction distribution 1513system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution 1514system.cpu0.toL2Bus.trans_dist::UpgradeReq 80908 # Transaction distribution 1515system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43157 # Transaction distribution 1516system.cpu0.toL2Bus.trans_dist::UpgradeResp 104918 # Transaction distribution 1517system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 1518system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 1519system.cpu0.toL2Bus.trans_dist::ReadExReq 291878 # Transaction distribution 1520system.cpu0.toL2Bus.trans_dist::ReadExResp 281134 # Transaction distribution 1521system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2533809 # Packet count per connected master and slave (bytes) 1522system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360432 # Packet count per connected master and slave (bytes) 1523system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28914 # Packet count per connected master and slave (bytes) 1524system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120703 # Packet count per connected master and slave (bytes) 1525system.cpu0.toL2Bus.pkt_count::total 5043858 # Packet count per connected master and slave (bytes) 1526system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80936864 # Cumulative packet size per connected master and slave (bytes) 1527system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86195670 # Cumulative packet size per connected master and slave (bytes) 1528system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50328 # Cumulative packet size per connected master and slave (bytes) 1529system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 219428 # Cumulative packet size per connected master and slave (bytes) 1530system.cpu0.toL2Bus.pkt_size::total 167402290 # Cumulative packet size per connected master and slave (bytes) 1531system.cpu0.toL2Bus.snoops 1041040 # Total snoops (count) 1532system.cpu0.toL2Bus.snoop_fanout::samples 3611543 # Request fanout histogram 1533system.cpu0.toL2Bus.snoop_fanout::mean 5.254928 # Request fanout histogram 1534system.cpu0.toL2Bus.snoop_fanout::stdev 0.435821 # Request fanout histogram 1535system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1536system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1537system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1538system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1539system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1540system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1541system.cpu0.toL2Bus.snoop_fanout::5 2690859 74.51% 74.51% # Request fanout histogram 1542system.cpu0.toL2Bus.snoop_fanout::6 920684 25.49% 100.00% # Request fanout histogram 1543system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1544system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1545system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1546system.cpu0.toL2Bus.snoop_fanout::total 3611543 # Request fanout histogram 1547system.cpu0.toL2Bus.reqLayer0.occupancy 1890112247 # Layer occupancy (ticks) 1548system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1549system.cpu0.toL2Bus.snoopLayer0.occupancy 117326747 # Layer occupancy (ticks) 1550system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1551system.cpu0.toL2Bus.respLayer0.occupancy 1900909092 # Layer occupancy (ticks) 1552system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1553system.cpu0.toL2Bus.respLayer1.occupancy 1220029643 # Layer occupancy (ticks) 1554system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1555system.cpu0.toL2Bus.respLayer2.occupancy 16342731 # Layer occupancy (ticks) 1556system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1557system.cpu0.toL2Bus.respLayer3.occupancy 65878690 # Layer occupancy (ticks) 1558system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1559system.cpu0.icache.tags.replacements 1263367 # number of replacements 1560system.cpu0.icache.tags.tagsinuse 511.774258 # Cycle average of tags in use 1561system.cpu0.icache.tags.total_refs 36446077 # Total number of references to valid blocks. 1562system.cpu0.icache.tags.sampled_refs 1263879 # Sample count of references to valid blocks. 1563system.cpu0.icache.tags.avg_refs 28.836682 # Average number of references to valid blocks. | 751system.cpu0.cc_regfile_reads 350776322 # number of cc regfile reads 752system.cpu0.cc_regfile_writes 41073406 # number of cc regfile writes 753system.cpu0.misc_regfile_reads 245816593 # number of misc regfile reads 754system.cpu0.misc_regfile_writes 1224552 # number of misc regfile writes 755system.cpu0.dcache.tags.replacements 712837 # number of replacements 756system.cpu0.dcache.tags.tagsinuse 493.082878 # Cycle average of tags in use 757system.cpu0.dcache.tags.total_refs 28842463 # Total number of references to valid blocks. 758system.cpu0.dcache.tags.sampled_refs 713349 # Sample count of references to valid blocks. 759system.cpu0.dcache.tags.avg_refs 40.432471 # Average number of references to valid blocks. 760system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. 761system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082878 # Average occupied blocks per requestor 762system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy 763system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy 764system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 765system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id 766system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 767system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 768system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 769system.cpu0.dcache.tags.tag_accesses 63484078 # Number of tag accesses 770system.cpu0.dcache.tags.data_accesses 63484078 # Number of data accesses 771system.cpu0.dcache.ReadReq_hits::cpu0.data 15589241 # number of ReadReq hits 772system.cpu0.dcache.ReadReq_hits::total 15589241 # number of ReadReq hits 773system.cpu0.dcache.WriteReq_hits::cpu0.data 12071944 # number of WriteReq hits 774system.cpu0.dcache.WriteReq_hits::total 12071944 # number of WriteReq hits 775system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310964 # number of SoftPFReq hits 776system.cpu0.dcache.SoftPFReq_hits::total 310964 # number of SoftPFReq hits 777system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363200 # number of LoadLockedReq hits 778system.cpu0.dcache.LoadLockedReq_hits::total 363200 # number of LoadLockedReq hits 779system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360654 # number of StoreCondReq hits 780system.cpu0.dcache.StoreCondReq_hits::total 360654 # number of StoreCondReq hits 781system.cpu0.dcache.demand_hits::cpu0.data 27661185 # number of demand (read+write) hits 782system.cpu0.dcache.demand_hits::total 27661185 # number of demand (read+write) hits 783system.cpu0.dcache.overall_hits::cpu0.data 27972149 # number of overall hits 784system.cpu0.dcache.overall_hits::total 27972149 # number of overall hits 785system.cpu0.dcache.ReadReq_misses::cpu0.data 638343 # number of ReadReq misses 786system.cpu0.dcache.ReadReq_misses::total 638343 # number of ReadReq misses 787system.cpu0.dcache.WriteReq_misses::cpu0.data 1832165 # number of WriteReq misses 788system.cpu0.dcache.WriteReq_misses::total 1832165 # number of WriteReq misses 789system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146120 # number of SoftPFReq misses 790system.cpu0.dcache.SoftPFReq_misses::total 146120 # number of SoftPFReq misses 791system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses 792system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses 793system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20612 # number of StoreCondReq misses 794system.cpu0.dcache.StoreCondReq_misses::total 20612 # number of StoreCondReq misses 795system.cpu0.dcache.demand_misses::cpu0.data 2470508 # number of demand (read+write) misses 796system.cpu0.dcache.demand_misses::total 2470508 # number of demand (read+write) misses 797system.cpu0.dcache.overall_misses::cpu0.data 2616628 # number of overall misses 798system.cpu0.dcache.overall_misses::total 2616628 # number of overall misses 799system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8099233830 # number of ReadReq miss cycles 800system.cpu0.dcache.ReadReq_miss_latency::total 8099233830 # number of ReadReq miss cycles 801system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24956974532 # number of WriteReq miss cycles 802system.cpu0.dcache.WriteReq_miss_latency::total 24956974532 # number of WriteReq miss cycles 803system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395327755 # number of LoadLockedReq miss cycles 804system.cpu0.dcache.LoadLockedReq_miss_latency::total 395327755 # number of LoadLockedReq miss cycles 805system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453888287 # number of StoreCondReq miss cycles 806system.cpu0.dcache.StoreCondReq_miss_latency::total 453888287 # number of StoreCondReq miss cycles 807system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 344500 # number of StoreCondFailReq miss cycles 808system.cpu0.dcache.StoreCondFailReq_miss_latency::total 344500 # number of StoreCondFailReq miss cycles 809system.cpu0.dcache.demand_miss_latency::cpu0.data 33056208362 # number of demand (read+write) miss cycles 810system.cpu0.dcache.demand_miss_latency::total 33056208362 # number of demand (read+write) miss cycles 811system.cpu0.dcache.overall_miss_latency::cpu0.data 33056208362 # number of overall miss cycles 812system.cpu0.dcache.overall_miss_latency::total 33056208362 # number of overall miss cycles 813system.cpu0.dcache.ReadReq_accesses::cpu0.data 16227584 # number of ReadReq accesses(hits+misses) 814system.cpu0.dcache.ReadReq_accesses::total 16227584 # number of ReadReq accesses(hits+misses) 815system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904109 # number of WriteReq accesses(hits+misses) 816system.cpu0.dcache.WriteReq_accesses::total 13904109 # number of WriteReq accesses(hits+misses) 817system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457084 # number of SoftPFReq accesses(hits+misses) 818system.cpu0.dcache.SoftPFReq_accesses::total 457084 # number of SoftPFReq accesses(hits+misses) 819system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388176 # number of LoadLockedReq accesses(hits+misses) 820system.cpu0.dcache.LoadLockedReq_accesses::total 388176 # number of LoadLockedReq accesses(hits+misses) 821system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381266 # number of StoreCondReq accesses(hits+misses) 822system.cpu0.dcache.StoreCondReq_accesses::total 381266 # number of StoreCondReq accesses(hits+misses) 823system.cpu0.dcache.demand_accesses::cpu0.data 30131693 # number of demand (read+write) accesses 824system.cpu0.dcache.demand_accesses::total 30131693 # number of demand (read+write) accesses 825system.cpu0.dcache.overall_accesses::cpu0.data 30588777 # number of overall (read+write) accesses 826system.cpu0.dcache.overall_accesses::total 30588777 # number of overall (read+write) accesses 827system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039337 # miss rate for ReadReq accesses 828system.cpu0.dcache.ReadReq_miss_rate::total 0.039337 # miss rate for ReadReq accesses 829system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131771 # miss rate for WriteReq accesses 830system.cpu0.dcache.WriteReq_miss_rate::total 0.131771 # miss rate for WriteReq accesses 831system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319679 # miss rate for SoftPFReq accesses 832system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319679 # miss rate for SoftPFReq accesses 833system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses 834system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses 835system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054062 # miss rate for StoreCondReq accesses 836system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054062 # miss rate for StoreCondReq accesses 837system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081990 # miss rate for demand accesses 838system.cpu0.dcache.demand_miss_rate::total 0.081990 # miss rate for demand accesses 839system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085542 # miss rate for overall accesses 840system.cpu0.dcache.overall_miss_rate::total 0.085542 # miss rate for overall accesses 841system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12687.902632 # average ReadReq miss latency 842system.cpu0.dcache.ReadReq_avg_miss_latency::total 12687.902632 # average ReadReq miss latency 843system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13621.575858 # average WriteReq miss latency 844system.cpu0.dcache.WriteReq_avg_miss_latency::total 13621.575858 # average WriteReq miss latency 845system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15828.305373 # average LoadLockedReq miss latency 846system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15828.305373 # average LoadLockedReq miss latency 847system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22020.584465 # average StoreCondReq miss latency 848system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22020.584465 # average StoreCondReq miss latency 849system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 850system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 851system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13380.328403 # average overall miss latency 852system.cpu0.dcache.demand_avg_miss_latency::total 13380.328403 # average overall miss latency 853system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12633.132552 # average overall miss latency 854system.cpu0.dcache.overall_avg_miss_latency::total 12633.132552 # average overall miss latency 855system.cpu0.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked 856system.cpu0.dcache.blocked_cycles::no_targets 3366874 # number of cycles access was blocked 857system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked 858system.cpu0.dcache.blocked::no_targets 191323 # number of cycles access was blocked 859system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.357143 # average number of cycles each access was blocked 860system.cpu0.dcache.avg_blocked_cycles::no_targets 17.597853 # average number of cycles each access was blocked 861system.cpu0.dcache.fast_writes 0 # number of fast writes performed 862system.cpu0.dcache.cache_copies 0 # number of cache copies performed 863system.cpu0.dcache.writebacks::writebacks 513073 # number of writebacks 864system.cpu0.dcache.writebacks::total 513073 # number of writebacks 865system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248142 # number of ReadReq MSHR hits 866system.cpu0.dcache.ReadReq_mshr_hits::total 248142 # number of ReadReq MSHR hits 867system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519584 # number of WriteReq MSHR hits 868system.cpu0.dcache.WriteReq_mshr_hits::total 1519584 # number of WriteReq MSHR hits 869system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18421 # number of LoadLockedReq MSHR hits 870system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18421 # number of LoadLockedReq MSHR hits 871system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767726 # number of demand (read+write) MSHR hits 872system.cpu0.dcache.demand_mshr_hits::total 1767726 # number of demand (read+write) MSHR hits 873system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767726 # number of overall MSHR hits 874system.cpu0.dcache.overall_mshr_hits::total 1767726 # number of overall MSHR hits 875system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390201 # number of ReadReq MSHR misses 876system.cpu0.dcache.ReadReq_mshr_misses::total 390201 # number of ReadReq MSHR misses 877system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312581 # number of WriteReq MSHR misses 878system.cpu0.dcache.WriteReq_mshr_misses::total 312581 # number of WriteReq MSHR misses 879system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101511 # number of SoftPFReq MSHR misses 880system.cpu0.dcache.SoftPFReq_mshr_misses::total 101511 # number of SoftPFReq MSHR misses 881system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6555 # number of LoadLockedReq MSHR misses 882system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6555 # number of LoadLockedReq MSHR misses 883system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20612 # number of StoreCondReq MSHR misses 884system.cpu0.dcache.StoreCondReq_mshr_misses::total 20612 # number of StoreCondReq MSHR misses 885system.cpu0.dcache.demand_mshr_misses::cpu0.data 702782 # number of demand (read+write) MSHR misses 886system.cpu0.dcache.demand_mshr_misses::total 702782 # number of demand (read+write) MSHR misses 887system.cpu0.dcache.overall_mshr_misses::cpu0.data 804293 # number of overall MSHR misses 888system.cpu0.dcache.overall_mshr_misses::total 804293 # number of overall MSHR misses 889system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170777489 # number of ReadReq MSHR miss cycles 890system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170777489 # number of ReadReq MSHR miss cycles 891system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4999843092 # number of WriteReq MSHR miss cycles 892system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4999843092 # number of WriteReq MSHR miss cycles 893system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1415062493 # number of SoftPFReq MSHR miss cycles 894system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1415062493 # number of SoftPFReq MSHR miss cycles 895system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97847997 # number of LoadLockedReq MSHR miss cycles 896system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97847997 # number of LoadLockedReq MSHR miss cycles 897system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411963713 # number of StoreCondReq MSHR miss cycles 898system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411963713 # number of StoreCondReq MSHR miss cycles 899system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 324500 # number of StoreCondFailReq MSHR miss cycles 900system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 324500 # number of StoreCondFailReq MSHR miss cycles 901system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9170620581 # number of demand (read+write) MSHR miss cycles 902system.cpu0.dcache.demand_mshr_miss_latency::total 9170620581 # number of demand (read+write) MSHR miss cycles 903system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10585683074 # number of overall MSHR miss cycles 904system.cpu0.dcache.overall_mshr_miss_latency::total 10585683074 # number of overall MSHR miss cycles 905system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217063246 # number of ReadReq MSHR uncacheable cycles 906system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217063246 # number of ReadReq MSHR uncacheable cycles 907system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187063995 # number of WriteReq MSHR uncacheable cycles 908system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187063995 # number of WriteReq MSHR uncacheable cycles 909system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404127241 # number of overall MSHR uncacheable cycles 910system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404127241 # number of overall MSHR uncacheable cycles 911system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses 912system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses 913system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022481 # mshr miss rate for WriteReq accesses 914system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022481 # mshr miss rate for WriteReq accesses 915system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222084 # mshr miss rate for SoftPFReq accesses 916system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222084 # mshr miss rate for SoftPFReq accesses 917system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016887 # mshr miss rate for LoadLockedReq accesses 918system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016887 # mshr miss rate for LoadLockedReq accesses 919system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054062 # mshr miss rate for StoreCondReq accesses 920system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054062 # mshr miss rate for StoreCondReq accesses 921system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023324 # mshr miss rate for demand accesses 922system.cpu0.dcache.demand_mshr_miss_rate::total 0.023324 # mshr miss rate for demand accesses 923system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026294 # mshr miss rate for overall accesses 924system.cpu0.dcache.overall_mshr_miss_rate::total 0.026294 # mshr miss rate for overall accesses 925system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10688.792415 # average ReadReq mshr miss latency 926system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10688.792415 # average ReadReq mshr miss latency 927system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15995.351899 # average WriteReq mshr miss latency 928system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15995.351899 # average WriteReq mshr miss latency 929system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13939.991656 # average SoftPFReq mshr miss latency 930system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13939.991656 # average SoftPFReq mshr miss latency 931system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14927.230664 # average LoadLockedReq mshr miss latency 932system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14927.230664 # average LoadLockedReq mshr miss latency 933system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19986.595818 # average StoreCondReq mshr miss latency 934system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19986.595818 # average StoreCondReq mshr miss latency 935system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 936system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 937system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13049.025987 # average overall mshr miss latency 938system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13049.025987 # average overall mshr miss latency 939system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13161.476072 # average overall mshr miss latency 940system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13161.476072 # average overall mshr miss latency 941system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 942system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 943system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 944system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 945system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 946system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 947system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 948system.cpu0.icache.tags.replacements 1263629 # number of replacements 949system.cpu0.icache.tags.tagsinuse 511.774279 # Cycle average of tags in use 950system.cpu0.icache.tags.total_refs 36446507 # Total number of references to valid blocks. 951system.cpu0.icache.tags.sampled_refs 1264141 # Sample count of references to valid blocks. 952system.cpu0.icache.tags.avg_refs 28.831046 # Average number of references to valid blocks. |
| 1564system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. | 953system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. |
| 1565system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774258 # Average occupied blocks per requestor | 954system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774279 # Average occupied blocks per requestor |
| 1566system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy 1567system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy 1568system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1569system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id | 955system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy 956system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy 957system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 958system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id |
| 1570system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 1571system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id | 959system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id 960system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id |
| 1572system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 961system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1573system.cpu0.icache.tags.tag_accesses 76757150 # Number of tag accesses 1574system.cpu0.icache.tags.data_accesses 76757150 # Number of data accesses 1575system.cpu0.icache.ReadReq_hits::cpu0.inst 36446077 # number of ReadReq hits 1576system.cpu0.icache.ReadReq_hits::total 36446077 # number of ReadReq hits 1577system.cpu0.icache.demand_hits::cpu0.inst 36446077 # number of demand (read+write) hits 1578system.cpu0.icache.demand_hits::total 36446077 # number of demand (read+write) hits 1579system.cpu0.icache.overall_hits::cpu0.inst 36446077 # number of overall hits 1580system.cpu0.icache.overall_hits::total 36446077 # number of overall hits 1581system.cpu0.icache.ReadReq_misses::cpu0.inst 1300540 # number of ReadReq misses 1582system.cpu0.icache.ReadReq_misses::total 1300540 # number of ReadReq misses 1583system.cpu0.icache.demand_misses::cpu0.inst 1300540 # number of demand (read+write) misses 1584system.cpu0.icache.demand_misses::total 1300540 # number of demand (read+write) misses 1585system.cpu0.icache.overall_misses::cpu0.inst 1300540 # number of overall misses 1586system.cpu0.icache.overall_misses::total 1300540 # number of overall misses 1587system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11011983856 # number of ReadReq miss cycles 1588system.cpu0.icache.ReadReq_miss_latency::total 11011983856 # number of ReadReq miss cycles 1589system.cpu0.icache.demand_miss_latency::cpu0.inst 11011983856 # number of demand (read+write) miss cycles 1590system.cpu0.icache.demand_miss_latency::total 11011983856 # number of demand (read+write) miss cycles 1591system.cpu0.icache.overall_miss_latency::cpu0.inst 11011983856 # number of overall miss cycles 1592system.cpu0.icache.overall_miss_latency::total 11011983856 # number of overall miss cycles 1593system.cpu0.icache.ReadReq_accesses::cpu0.inst 37746617 # number of ReadReq accesses(hits+misses) 1594system.cpu0.icache.ReadReq_accesses::total 37746617 # number of ReadReq accesses(hits+misses) 1595system.cpu0.icache.demand_accesses::cpu0.inst 37746617 # number of demand (read+write) accesses 1596system.cpu0.icache.demand_accesses::total 37746617 # number of demand (read+write) accesses 1597system.cpu0.icache.overall_accesses::cpu0.inst 37746617 # number of overall (read+write) accesses 1598system.cpu0.icache.overall_accesses::total 37746617 # number of overall (read+write) accesses 1599system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034454 # miss rate for ReadReq accesses 1600system.cpu0.icache.ReadReq_miss_rate::total 0.034454 # miss rate for ReadReq accesses 1601system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034454 # miss rate for demand accesses 1602system.cpu0.icache.demand_miss_rate::total 0.034454 # miss rate for demand accesses 1603system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034454 # miss rate for overall accesses 1604system.cpu0.icache.overall_miss_rate::total 0.034454 # miss rate for overall accesses 1605system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8467.239651 # average ReadReq miss latency 1606system.cpu0.icache.ReadReq_avg_miss_latency::total 8467.239651 # average ReadReq miss latency 1607system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency 1608system.cpu0.icache.demand_avg_miss_latency::total 8467.239651 # average overall miss latency 1609system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency 1610system.cpu0.icache.overall_avg_miss_latency::total 8467.239651 # average overall miss latency 1611system.cpu0.icache.blocked_cycles::no_mshrs 724812 # number of cycles access was blocked | 962system.cpu0.icache.tags.tag_accesses 76758780 # Number of tag accesses 963system.cpu0.icache.tags.data_accesses 76758780 # Number of data accesses 964system.cpu0.icache.ReadReq_hits::cpu0.inst 36446507 # number of ReadReq hits 965system.cpu0.icache.ReadReq_hits::total 36446507 # number of ReadReq hits 966system.cpu0.icache.demand_hits::cpu0.inst 36446507 # number of demand (read+write) hits 967system.cpu0.icache.demand_hits::total 36446507 # number of demand (read+write) hits 968system.cpu0.icache.overall_hits::cpu0.inst 36446507 # number of overall hits 969system.cpu0.icache.overall_hits::total 36446507 # number of overall hits 970system.cpu0.icache.ReadReq_misses::cpu0.inst 1300794 # number of ReadReq misses 971system.cpu0.icache.ReadReq_misses::total 1300794 # number of ReadReq misses 972system.cpu0.icache.demand_misses::cpu0.inst 1300794 # number of demand (read+write) misses 973system.cpu0.icache.demand_misses::total 1300794 # number of demand (read+write) misses 974system.cpu0.icache.overall_misses::cpu0.inst 1300794 # number of overall misses 975system.cpu0.icache.overall_misses::total 1300794 # number of overall misses 976system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11016728605 # number of ReadReq miss cycles 977system.cpu0.icache.ReadReq_miss_latency::total 11016728605 # number of ReadReq miss cycles 978system.cpu0.icache.demand_miss_latency::cpu0.inst 11016728605 # number of demand (read+write) miss cycles 979system.cpu0.icache.demand_miss_latency::total 11016728605 # number of demand (read+write) miss cycles 980system.cpu0.icache.overall_miss_latency::cpu0.inst 11016728605 # number of overall miss cycles 981system.cpu0.icache.overall_miss_latency::total 11016728605 # number of overall miss cycles 982system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747301 # number of ReadReq accesses(hits+misses) 983system.cpu0.icache.ReadReq_accesses::total 37747301 # number of ReadReq accesses(hits+misses) 984system.cpu0.icache.demand_accesses::cpu0.inst 37747301 # number of demand (read+write) accesses 985system.cpu0.icache.demand_accesses::total 37747301 # number of demand (read+write) accesses 986system.cpu0.icache.overall_accesses::cpu0.inst 37747301 # number of overall (read+write) accesses 987system.cpu0.icache.overall_accesses::total 37747301 # number of overall (read+write) accesses 988system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034461 # miss rate for ReadReq accesses 989system.cpu0.icache.ReadReq_miss_rate::total 0.034461 # miss rate for ReadReq accesses 990system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034461 # miss rate for demand accesses 991system.cpu0.icache.demand_miss_rate::total 0.034461 # miss rate for demand accesses 992system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034461 # miss rate for overall accesses 993system.cpu0.icache.overall_miss_rate::total 0.034461 # miss rate for overall accesses 994system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8469.233872 # average ReadReq miss latency 995system.cpu0.icache.ReadReq_avg_miss_latency::total 8469.233872 # average ReadReq miss latency 996system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency 997system.cpu0.icache.demand_avg_miss_latency::total 8469.233872 # average overall miss latency 998system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency 999system.cpu0.icache.overall_avg_miss_latency::total 8469.233872 # average overall miss latency 1000system.cpu0.icache.blocked_cycles::no_mshrs 724171 # number of cycles access was blocked |
| 1612system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked | 1001system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked |
| 1613system.cpu0.icache.blocked::no_mshrs 96016 # number of cycles access was blocked | 1002system.cpu0.icache.blocked::no_mshrs 96135 # number of cycles access was blocked |
| 1614system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked | 1003system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked |
| 1615system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.548867 # average number of cycles each access was blocked | 1004system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.532855 # average number of cycles each access was blocked |
| 1616system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked 1617system.cpu0.icache.fast_writes 0 # number of fast writes performed 1618system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1005system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked 1006system.cpu0.icache.fast_writes 0 # number of fast writes performed 1007system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1619system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36623 # number of ReadReq MSHR hits 1620system.cpu0.icache.ReadReq_mshr_hits::total 36623 # number of ReadReq MSHR hits 1621system.cpu0.icache.demand_mshr_hits::cpu0.inst 36623 # number of demand (read+write) MSHR hits 1622system.cpu0.icache.demand_mshr_hits::total 36623 # number of demand (read+write) MSHR hits 1623system.cpu0.icache.overall_mshr_hits::cpu0.inst 36623 # number of overall MSHR hits 1624system.cpu0.icache.overall_mshr_hits::total 36623 # number of overall MSHR hits 1625system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1263917 # number of ReadReq MSHR misses 1626system.cpu0.icache.ReadReq_mshr_misses::total 1263917 # number of ReadReq MSHR misses 1627system.cpu0.icache.demand_mshr_misses::cpu0.inst 1263917 # number of demand (read+write) MSHR misses 1628system.cpu0.icache.demand_mshr_misses::total 1263917 # number of demand (read+write) MSHR misses 1629system.cpu0.icache.overall_mshr_misses::cpu0.inst 1263917 # number of overall MSHR misses 1630system.cpu0.icache.overall_mshr_misses::total 1263917 # number of overall MSHR misses 1631system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8916921322 # number of ReadReq MSHR miss cycles 1632system.cpu0.icache.ReadReq_mshr_miss_latency::total 8916921322 # number of ReadReq MSHR miss cycles 1633system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8916921322 # number of demand (read+write) MSHR miss cycles 1634system.cpu0.icache.demand_mshr_miss_latency::total 8916921322 # number of demand (read+write) MSHR miss cycles 1635system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8916921322 # number of overall MSHR miss cycles 1636system.cpu0.icache.overall_mshr_miss_latency::total 8916921322 # number of overall MSHR miss cycles | 1008system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36615 # number of ReadReq MSHR hits 1009system.cpu0.icache.ReadReq_mshr_hits::total 36615 # number of ReadReq MSHR hits 1010system.cpu0.icache.demand_mshr_hits::cpu0.inst 36615 # number of demand (read+write) MSHR hits 1011system.cpu0.icache.demand_mshr_hits::total 36615 # number of demand (read+write) MSHR hits 1012system.cpu0.icache.overall_mshr_hits::cpu0.inst 36615 # number of overall MSHR hits 1013system.cpu0.icache.overall_mshr_hits::total 36615 # number of overall MSHR hits 1014system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264179 # number of ReadReq MSHR misses 1015system.cpu0.icache.ReadReq_mshr_misses::total 1264179 # number of ReadReq MSHR misses 1016system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264179 # number of demand (read+write) MSHR misses 1017system.cpu0.icache.demand_mshr_misses::total 1264179 # number of demand (read+write) MSHR misses 1018system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264179 # number of overall MSHR misses 1019system.cpu0.icache.overall_mshr_misses::total 1264179 # number of overall MSHR misses 1020system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8918143809 # number of ReadReq MSHR miss cycles 1021system.cpu0.icache.ReadReq_mshr_miss_latency::total 8918143809 # number of ReadReq MSHR miss cycles 1022system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8918143809 # number of demand (read+write) MSHR miss cycles 1023system.cpu0.icache.demand_mshr_miss_latency::total 8918143809 # number of demand (read+write) MSHR miss cycles 1024system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8918143809 # number of overall MSHR miss cycles 1025system.cpu0.icache.overall_mshr_miss_latency::total 8918143809 # number of overall MSHR miss cycles |
| 1637system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles 1638system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles 1639system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles 1640system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles | 1026system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles 1027system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles 1028system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles 1029system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles |
| 1641system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for ReadReq accesses 1642system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033484 # mshr miss rate for ReadReq accesses 1643system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for demand accesses 1644system.cpu0.icache.demand_mshr_miss_rate::total 0.033484 # mshr miss rate for demand accesses 1645system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for overall accesses 1646system.cpu0.icache.overall_mshr_miss_rate::total 0.033484 # mshr miss rate for overall accesses 1647system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average ReadReq mshr miss latency 1648system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.989625 # average ReadReq mshr miss latency 1649system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency 1650system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency 1651system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency 1652system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency | 1030system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for ReadReq accesses 1031system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033491 # mshr miss rate for ReadReq accesses 1032system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for demand accesses 1033system.cpu0.icache.demand_mshr_miss_rate::total 0.033491 # mshr miss rate for demand accesses 1034system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for overall accesses 1035system.cpu0.icache.overall_mshr_miss_rate::total 0.033491 # mshr miss rate for overall accesses 1036system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average ReadReq mshr miss latency 1037system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.494505 # average ReadReq mshr miss latency 1038system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency 1039system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency 1040system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency 1041system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency |
| 1653system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1654system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1655system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1656system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1657system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1042system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1043system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1044system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1045system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1046system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1658system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11566475 # number of hwpf identified 1659system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 526266 # number of hwpf that were already in mshr 1660system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10413579 # number of hwpf that were already in the cache 1661system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118534 # number of hwpf that were already in the prefetch queue | 1047system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11567606 # number of hwpf identified 1048system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525705 # number of hwpf that were already in mshr 1049system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10416149 # number of hwpf that were already in the cache 1050system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118627 # number of hwpf that were already in the prefetch queue |
| 1662system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1051system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1663system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25521 # number of hwpf removed because MSHR allocated 1664system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 482570 # number of hwpf issued 1665system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881997 # number of hwpf spanning a virtual page | 1052system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25546 # number of hwpf removed because MSHR allocated 1053system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 481574 # number of hwpf issued 1054system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 882370 # number of hwpf spanning a virtual page |
| 1666system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1055system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1667system.cpu0.l2cache.tags.replacements 397205 # number of replacements 1668system.cpu0.l2cache.tags.tagsinuse 16210.584505 # Cycle average of tags in use 1669system.cpu0.l2cache.tags.total_refs 2245016 # Total number of references to valid blocks. 1670system.cpu0.l2cache.tags.sampled_refs 413453 # Sample count of references to valid blocks. 1671system.cpu0.l2cache.tags.avg_refs 5.429918 # Average number of references to valid blocks. 1672system.cpu0.l2cache.tags.warmup_cycle 2809067534500 # Cycle when the warmup percentage was hit. 1673system.cpu0.l2cache.tags.occ_blocks::writebacks 4582.280464 # Average occupied blocks per requestor 1674system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 7.704235 # Average occupied blocks per requestor 1675system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.810288 # Average occupied blocks per requestor 1676system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 954.063900 # Average occupied blocks per requestor 1677system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1415.763715 # Average occupied blocks per requestor 1678system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9248.961904 # Average occupied blocks per requestor 1679system.cpu0.l2cache.tags.occ_percent::writebacks 0.279680 # Average percentage of cache occupancy 1680system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000470 # Average percentage of cache occupancy 1681system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy 1682system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.058231 # Average percentage of cache occupancy 1683system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086411 # Average percentage of cache occupancy 1684system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.564512 # Average percentage of cache occupancy 1685system.cpu0.l2cache.tags.occ_percent::total 0.989416 # Average percentage of cache occupancy 1686system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8114 # Occupied blocks per task id 1687system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 1688system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8126 # Occupied blocks per task id | 1056system.cpu0.l2cache.tags.replacements 396542 # number of replacements 1057system.cpu0.l2cache.tags.tagsinuse 16205.769061 # Cycle average of tags in use 1058system.cpu0.l2cache.tags.total_refs 2244815 # Total number of references to valid blocks. 1059system.cpu0.l2cache.tags.sampled_refs 412792 # Sample count of references to valid blocks. 1060system.cpu0.l2cache.tags.avg_refs 5.438126 # Average number of references to valid blocks. 1061system.cpu0.l2cache.tags.warmup_cycle 2809084521500 # Cycle when the warmup percentage was hit. 1062system.cpu0.l2cache.tags.occ_blocks::writebacks 4618.987809 # Average occupied blocks per requestor 1063system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.979975 # Average occupied blocks per requestor 1064system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 2.443926 # Average occupied blocks per requestor 1065system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 942.112111 # Average occupied blocks per requestor 1066system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.719068 # Average occupied blocks per requestor 1067system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9222.526172 # Average occupied blocks per requestor 1068system.cpu0.l2cache.tags.occ_percent::writebacks 0.281921 # Average percentage of cache occupancy 1069system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000548 # Average percentage of cache occupancy 1070system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000149 # Average percentage of cache occupancy 1071system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057502 # Average percentage of cache occupancy 1072system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086103 # Average percentage of cache occupancy 1073system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.562898 # Average percentage of cache occupancy 1074system.cpu0.l2cache.tags.occ_percent::total 0.989122 # Average percentage of cache occupancy 1075system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8075 # Occupied blocks per task id 1076system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 1077system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8170 # Occupied blocks per task id |
| 1689system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id | 1078system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id |
| 1690system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 255 # Occupied blocks per task id 1691system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3376 # Occupied blocks per task id 1692system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3995 # Occupied blocks per task id 1693system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id 1694system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 1695system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 1696system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 500 # Occupied blocks per task id 1697system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id 1698system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3570 # Occupied blocks per task id 1699system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 262 # Occupied blocks per task id 1700system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.495239 # Percentage of cache occupancy per task id 1701system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 1702system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.495972 # Percentage of cache occupancy per task id 1703system.cpu0.l2cache.tags.tag_accesses 43582923 # Number of tag accesses 1704system.cpu0.l2cache.tags.data_accesses 43582923 # Number of data accesses 1705system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54301 # number of ReadReq hits 1706system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12378 # number of ReadReq hits 1707system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242064 # number of ReadReq hits 1708system.cpu0.l2cache.ReadReq_hits::cpu0.data 407333 # number of ReadReq hits 1709system.cpu0.l2cache.ReadReq_hits::total 1716076 # number of ReadReq hits 1710system.cpu0.l2cache.Writeback_hits::writebacks 512970 # number of Writeback hits 1711system.cpu0.l2cache.Writeback_hits::total 512970 # number of Writeback hits 1712system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15323 # number of UpgradeReq hits 1713system.cpu0.l2cache.UpgradeReq_hits::total 15323 # number of UpgradeReq hits 1714system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2128 # number of SCUpgradeReq hits 1715system.cpu0.l2cache.SCUpgradeReq_hits::total 2128 # number of SCUpgradeReq hits 1716system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216744 # number of ReadExReq hits 1717system.cpu0.l2cache.ReadExReq_hits::total 216744 # number of ReadExReq hits 1718system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54301 # number of demand (read+write) hits 1719system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12378 # number of demand (read+write) hits 1720system.cpu0.l2cache.demand_hits::cpu0.inst 1242064 # number of demand (read+write) hits 1721system.cpu0.l2cache.demand_hits::cpu0.data 624077 # number of demand (read+write) hits 1722system.cpu0.l2cache.demand_hits::total 1932820 # number of demand (read+write) hits 1723system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54301 # number of overall hits 1724system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12378 # number of overall hits 1725system.cpu0.l2cache.overall_hits::cpu0.inst 1242064 # number of overall hits 1726system.cpu0.l2cache.overall_hits::cpu0.data 624077 # number of overall hits 1727system.cpu0.l2cache.overall_hits::total 1932820 # number of overall hits 1728system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 556 # number of ReadReq misses 1729system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 204 # number of ReadReq misses 1730system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21825 # number of ReadReq misses 1731system.cpu0.l2cache.ReadReq_misses::cpu0.data 90809 # number of ReadReq misses 1732system.cpu0.l2cache.ReadReq_misses::total 113394 # number of ReadReq misses | 1079system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 189 # Occupied blocks per task id 1080system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3306 # Occupied blocks per task id 1081system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4046 # Occupied blocks per task id 1082system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 488 # Occupied blocks per task id 1083system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1084system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1085system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1086system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 491 # Occupied blocks per task id 1087system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3813 # Occupied blocks per task id 1088system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id 1089system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id 1090system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.492859 # Percentage of cache occupancy per task id 1091system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id 1092system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.498657 # Percentage of cache occupancy per task id 1093system.cpu0.l2cache.tags.tag_accesses 43582688 # Number of tag accesses 1094system.cpu0.l2cache.tags.data_accesses 43582688 # Number of data accesses 1095system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54105 # number of ReadReq hits 1096system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12184 # number of ReadReq hits 1097system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242379 # number of ReadReq hits 1098system.cpu0.l2cache.ReadReq_hits::cpu0.data 407374 # number of ReadReq hits 1099system.cpu0.l2cache.ReadReq_hits::total 1716042 # number of ReadReq hits 1100system.cpu0.l2cache.Writeback_hits::writebacks 513072 # number of Writeback hits 1101system.cpu0.l2cache.Writeback_hits::total 513072 # number of Writeback hits 1102system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15340 # number of UpgradeReq hits 1103system.cpu0.l2cache.UpgradeReq_hits::total 15340 # number of UpgradeReq hits 1104system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2133 # number of SCUpgradeReq hits 1105system.cpu0.l2cache.SCUpgradeReq_hits::total 2133 # number of SCUpgradeReq hits 1106system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216716 # number of ReadExReq hits 1107system.cpu0.l2cache.ReadExReq_hits::total 216716 # number of ReadExReq hits 1108system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54105 # number of demand (read+write) hits 1109system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12184 # number of demand (read+write) hits 1110system.cpu0.l2cache.demand_hits::cpu0.inst 1242379 # number of demand (read+write) hits 1111system.cpu0.l2cache.demand_hits::cpu0.data 624090 # number of demand (read+write) hits 1112system.cpu0.l2cache.demand_hits::total 1932758 # number of demand (read+write) hits 1113system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54105 # number of overall hits 1114system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12184 # number of overall hits 1115system.cpu0.l2cache.overall_hits::cpu0.inst 1242379 # number of overall hits 1116system.cpu0.l2cache.overall_hits::cpu0.data 624090 # number of overall hits 1117system.cpu0.l2cache.overall_hits::total 1932758 # number of overall hits 1118system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 529 # number of ReadReq misses 1119system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 208 # number of ReadReq misses 1120system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21771 # number of ReadReq misses 1121system.cpu0.l2cache.ReadReq_misses::cpu0.data 90784 # number of ReadReq misses 1122system.cpu0.l2cache.ReadReq_misses::total 113292 # number of ReadReq misses |
| 1733system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1734system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses | 1123system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1124system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses |
| 1735system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27941 # number of UpgradeReq misses 1736system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses | 1125system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27958 # number of UpgradeReq misses 1126system.cpu0.l2cache.UpgradeReq_misses::total 27958 # number of UpgradeReq misses |
| 1737system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses 1738system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses | 1127system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses 1128system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses |
| 1739system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52711 # number of ReadExReq misses 1740system.cpu0.l2cache.ReadExReq_misses::total 52711 # number of ReadExReq misses 1741system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 556 # number of demand (read+write) misses 1742system.cpu0.l2cache.demand_misses::cpu0.itb.walker 204 # number of demand (read+write) misses 1743system.cpu0.l2cache.demand_misses::cpu0.inst 21825 # number of demand (read+write) misses 1744system.cpu0.l2cache.demand_misses::cpu0.data 143520 # number of demand (read+write) misses 1745system.cpu0.l2cache.demand_misses::total 166105 # number of demand (read+write) misses 1746system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 556 # number of overall misses 1747system.cpu0.l2cache.overall_misses::cpu0.itb.walker 204 # number of overall misses 1748system.cpu0.l2cache.overall_misses::cpu0.inst 21825 # number of overall misses 1749system.cpu0.l2cache.overall_misses::cpu0.data 143520 # number of overall misses 1750system.cpu0.l2cache.overall_misses::total 166105 # number of overall misses 1751system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14566249 # number of ReadReq miss cycles 1752system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5056249 # number of ReadReq miss cycles 1753system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 811526688 # number of ReadReq miss cycles 1754system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694555362 # number of ReadReq miss cycles 1755system.cpu0.l2cache.ReadReq_miss_latency::total 3525704548 # number of ReadReq miss cycles 1756system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501364439 # number of UpgradeReq miss cycles 1757system.cpu0.l2cache.UpgradeReq_miss_latency::total 501364439 # number of UpgradeReq miss cycles 1758system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362083288 # number of SCUpgradeReq miss cycles 1759system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362083288 # number of SCUpgradeReq miss cycles 1760system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 361000 # number of SCUpgradeFailReq miss cycles 1761system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 361000 # number of SCUpgradeFailReq miss cycles 1762system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2596231534 # number of ReadExReq miss cycles 1763system.cpu0.l2cache.ReadExReq_miss_latency::total 2596231534 # number of ReadExReq miss cycles 1764system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14566249 # number of demand (read+write) miss cycles 1765system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5056249 # number of demand (read+write) miss cycles 1766system.cpu0.l2cache.demand_miss_latency::cpu0.inst 811526688 # number of demand (read+write) miss cycles 1767system.cpu0.l2cache.demand_miss_latency::cpu0.data 5290786896 # number of demand (read+write) miss cycles 1768system.cpu0.l2cache.demand_miss_latency::total 6121936082 # number of demand (read+write) miss cycles 1769system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14566249 # number of overall miss cycles 1770system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5056249 # number of overall miss cycles 1771system.cpu0.l2cache.overall_miss_latency::cpu0.inst 811526688 # number of overall miss cycles 1772system.cpu0.l2cache.overall_miss_latency::cpu0.data 5290786896 # number of overall miss cycles 1773system.cpu0.l2cache.overall_miss_latency::total 6121936082 # number of overall miss cycles 1774system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54857 # number of ReadReq accesses(hits+misses) 1775system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12582 # number of ReadReq accesses(hits+misses) 1776system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1263889 # number of ReadReq accesses(hits+misses) 1777system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498142 # number of ReadReq accesses(hits+misses) 1778system.cpu0.l2cache.ReadReq_accesses::total 1829470 # number of ReadReq accesses(hits+misses) 1779system.cpu0.l2cache.Writeback_accesses::writebacks 512971 # number of Writeback accesses(hits+misses) 1780system.cpu0.l2cache.Writeback_accesses::total 512971 # number of Writeback accesses(hits+misses) 1781system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43264 # number of UpgradeReq accesses(hits+misses) 1782system.cpu0.l2cache.UpgradeReq_accesses::total 43264 # number of UpgradeReq accesses(hits+misses) 1783system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20607 # number of SCUpgradeReq accesses(hits+misses) 1784system.cpu0.l2cache.SCUpgradeReq_accesses::total 20607 # number of SCUpgradeReq accesses(hits+misses) 1785system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269455 # number of ReadExReq accesses(hits+misses) 1786system.cpu0.l2cache.ReadExReq_accesses::total 269455 # number of ReadExReq accesses(hits+misses) 1787system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54857 # number of demand (read+write) accesses 1788system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12582 # number of demand (read+write) accesses 1789system.cpu0.l2cache.demand_accesses::cpu0.inst 1263889 # number of demand (read+write) accesses 1790system.cpu0.l2cache.demand_accesses::cpu0.data 767597 # number of demand (read+write) accesses 1791system.cpu0.l2cache.demand_accesses::total 2098925 # number of demand (read+write) accesses 1792system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54857 # number of overall (read+write) accesses 1793system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12582 # number of overall (read+write) accesses 1794system.cpu0.l2cache.overall_accesses::cpu0.inst 1263889 # number of overall (read+write) accesses 1795system.cpu0.l2cache.overall_accesses::cpu0.data 767597 # number of overall (read+write) accesses 1796system.cpu0.l2cache.overall_accesses::total 2098925 # number of overall (read+write) accesses 1797system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for ReadReq accesses 1798system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016214 # miss rate for ReadReq accesses 1799system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017268 # miss rate for ReadReq accesses 1800system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182295 # miss rate for ReadReq accesses 1801system.cpu0.l2cache.ReadReq_miss_rate::total 0.061982 # miss rate for ReadReq accesses | 1129system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52756 # number of ReadExReq misses 1130system.cpu0.l2cache.ReadExReq_misses::total 52756 # number of ReadExReq misses 1131system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 529 # number of demand (read+write) misses 1132system.cpu0.l2cache.demand_misses::cpu0.itb.walker 208 # number of demand (read+write) misses 1133system.cpu0.l2cache.demand_misses::cpu0.inst 21771 # number of demand (read+write) misses 1134system.cpu0.l2cache.demand_misses::cpu0.data 143540 # number of demand (read+write) misses 1135system.cpu0.l2cache.demand_misses::total 166048 # number of demand (read+write) misses 1136system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 529 # number of overall misses 1137system.cpu0.l2cache.overall_misses::cpu0.itb.walker 208 # number of overall misses 1138system.cpu0.l2cache.overall_misses::cpu0.inst 21771 # number of overall misses 1139system.cpu0.l2cache.overall_misses::cpu0.data 143540 # number of overall misses 1140system.cpu0.l2cache.overall_misses::total 166048 # number of overall misses 1141system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 13920749 # number of ReadReq miss cycles 1142system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4946000 # number of ReadReq miss cycles 1143system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 810765185 # number of ReadReq miss cycles 1144system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694797858 # number of ReadReq miss cycles 1145system.cpu0.l2cache.ReadReq_miss_latency::total 3524429792 # number of ReadReq miss cycles 1146system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501186435 # number of UpgradeReq miss cycles 1147system.cpu0.l2cache.UpgradeReq_miss_latency::total 501186435 # number of UpgradeReq miss cycles 1148system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362145290 # number of SCUpgradeReq miss cycles 1149system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362145290 # number of SCUpgradeReq miss cycles 1150system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 314500 # number of SCUpgradeFailReq miss cycles 1151system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 314500 # number of SCUpgradeFailReq miss cycles 1152system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2597613271 # number of ReadExReq miss cycles 1153system.cpu0.l2cache.ReadExReq_miss_latency::total 2597613271 # number of ReadExReq miss cycles 1154system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 13920749 # number of demand (read+write) miss cycles 1155system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4946000 # number of demand (read+write) miss cycles 1156system.cpu0.l2cache.demand_miss_latency::cpu0.inst 810765185 # number of demand (read+write) miss cycles 1157system.cpu0.l2cache.demand_miss_latency::cpu0.data 5292411129 # number of demand (read+write) miss cycles 1158system.cpu0.l2cache.demand_miss_latency::total 6122043063 # number of demand (read+write) miss cycles 1159system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 13920749 # number of overall miss cycles 1160system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4946000 # number of overall miss cycles 1161system.cpu0.l2cache.overall_miss_latency::cpu0.inst 810765185 # number of overall miss cycles 1162system.cpu0.l2cache.overall_miss_latency::cpu0.data 5292411129 # number of overall miss cycles 1163system.cpu0.l2cache.overall_miss_latency::total 6122043063 # number of overall miss cycles 1164system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54634 # number of ReadReq accesses(hits+misses) 1165system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12392 # number of ReadReq accesses(hits+misses) 1166system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264150 # number of ReadReq accesses(hits+misses) 1167system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498158 # number of ReadReq accesses(hits+misses) 1168system.cpu0.l2cache.ReadReq_accesses::total 1829334 # number of ReadReq accesses(hits+misses) 1169system.cpu0.l2cache.Writeback_accesses::writebacks 513073 # number of Writeback accesses(hits+misses) 1170system.cpu0.l2cache.Writeback_accesses::total 513073 # number of Writeback accesses(hits+misses) 1171system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43298 # number of UpgradeReq accesses(hits+misses) 1172system.cpu0.l2cache.UpgradeReq_accesses::total 43298 # number of UpgradeReq accesses(hits+misses) 1173system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20612 # number of SCUpgradeReq accesses(hits+misses) 1174system.cpu0.l2cache.SCUpgradeReq_accesses::total 20612 # number of SCUpgradeReq accesses(hits+misses) 1175system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269472 # number of ReadExReq accesses(hits+misses) 1176system.cpu0.l2cache.ReadExReq_accesses::total 269472 # number of ReadExReq accesses(hits+misses) 1177system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54634 # number of demand (read+write) accesses 1178system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12392 # number of demand (read+write) accesses 1179system.cpu0.l2cache.demand_accesses::cpu0.inst 1264150 # number of demand (read+write) accesses 1180system.cpu0.l2cache.demand_accesses::cpu0.data 767630 # number of demand (read+write) accesses 1181system.cpu0.l2cache.demand_accesses::total 2098806 # number of demand (read+write) accesses 1182system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54634 # number of overall (read+write) accesses 1183system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12392 # number of overall (read+write) accesses 1184system.cpu0.l2cache.overall_accesses::cpu0.inst 1264150 # number of overall (read+write) accesses 1185system.cpu0.l2cache.overall_accesses::cpu0.data 767630 # number of overall (read+write) accesses 1186system.cpu0.l2cache.overall_accesses::total 2098806 # number of overall (read+write) accesses 1187system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009683 # miss rate for ReadReq accesses 1188system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016785 # miss rate for ReadReq accesses 1189system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017222 # miss rate for ReadReq accesses 1190system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182239 # miss rate for ReadReq accesses 1191system.cpu0.l2cache.ReadReq_miss_rate::total 0.061931 # miss rate for ReadReq accesses |
| 1802system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses 1803system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses | 1192system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses 1193system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses |
| 1804system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645826 # miss rate for UpgradeReq accesses 1805system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645826 # miss rate for UpgradeReq accesses 1806system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.896734 # miss rate for SCUpgradeReq accesses 1807system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.896734 # miss rate for SCUpgradeReq accesses 1808system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195621 # miss rate for ReadExReq accesses 1809system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195621 # miss rate for ReadExReq accesses 1810system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for demand accesses 1811system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016214 # miss rate for demand accesses 1812system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017268 # miss rate for demand accesses 1813system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186973 # miss rate for demand accesses 1814system.cpu0.l2cache.demand_miss_rate::total 0.079138 # miss rate for demand accesses 1815system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for overall accesses 1816system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016214 # miss rate for overall accesses 1817system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017268 # miss rate for overall accesses 1818system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186973 # miss rate for overall accesses 1819system.cpu0.l2cache.overall_miss_rate::total 0.079138 # miss rate for overall accesses 1820system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average ReadReq miss latency 1821system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24785.534314 # average ReadReq miss latency 1822system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.353402 # average ReadReq miss latency 1823system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29672.778711 # average ReadReq miss latency 1824system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31092.514137 # average ReadReq miss latency 1825system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17943.682724 # average UpgradeReq miss latency 1826system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17943.682724 # average UpgradeReq miss latency 1827system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19594.311813 # average SCUpgradeReq miss latency 1828system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19594.311813 # average SCUpgradeReq miss latency | 1194system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645711 # miss rate for UpgradeReq accesses 1195system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645711 # miss rate for UpgradeReq accesses 1196system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.896517 # miss rate for SCUpgradeReq accesses 1197system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.896517 # miss rate for SCUpgradeReq accesses 1198system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195775 # miss rate for ReadExReq accesses 1199system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195775 # miss rate for ReadExReq accesses 1200system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009683 # miss rate for demand accesses 1201system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016785 # miss rate for demand accesses 1202system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017222 # miss rate for demand accesses 1203system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186991 # miss rate for demand accesses 1204system.cpu0.l2cache.demand_miss_rate::total 0.079115 # miss rate for demand accesses 1205system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009683 # miss rate for overall accesses 1206system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016785 # miss rate for overall accesses 1207system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017222 # miss rate for overall accesses 1208system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186991 # miss rate for overall accesses 1209system.cpu0.l2cache.overall_miss_rate::total 0.079115 # miss rate for overall accesses 1210system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26315.215501 # average ReadReq miss latency 1211system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23778.846154 # average ReadReq miss latency 1212system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37240.603785 # average ReadReq miss latency 1213system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29683.621101 # average ReadReq miss latency 1214system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.255658 # average ReadReq miss latency 1215system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17926.405143 # average UpgradeReq miss latency 1216system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17926.405143 # average UpgradeReq miss latency 1217system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19597.667082 # average SCUpgradeReq miss latency 1218system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19597.667082 # average SCUpgradeReq miss latency |
| 1829system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1830system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 1219system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1220system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 1831system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49254.074747 # average ReadExReq miss latency 1832system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49254.074747 # average ReadExReq miss latency 1833system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency 1834system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency 1835system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency 1836system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency 1837system.cpu0.l2cache.demand_avg_miss_latency::total 36855.820607 # average overall miss latency 1838system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency 1839system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency 1840system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency 1841system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency 1842system.cpu0.l2cache.overall_avg_miss_latency::total 36855.820607 # average overall miss latency 1843system.cpu0.l2cache.blocked_cycles::no_mshrs 65022 # number of cycles access was blocked | 1221system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49238.252919 # average ReadExReq miss latency 1222system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49238.252919 # average ReadExReq miss latency 1223system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26315.215501 # average overall miss latency 1224system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23778.846154 # average overall miss latency 1225system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37240.603785 # average overall miss latency 1226system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36870.636262 # average overall miss latency 1227system.cpu0.l2cache.demand_avg_miss_latency::total 36869.116539 # average overall miss latency 1228system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26315.215501 # average overall miss latency 1229system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23778.846154 # average overall miss latency 1230system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37240.603785 # average overall miss latency 1231system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36870.636262 # average overall miss latency 1232system.cpu0.l2cache.overall_avg_miss_latency::total 36869.116539 # average overall miss latency 1233system.cpu0.l2cache.blocked_cycles::no_mshrs 65149 # number of cycles access was blocked |
| 1844system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1234system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1845system.cpu0.l2cache.blocked::no_mshrs 1467 # number of cycles access was blocked | 1235system.cpu0.l2cache.blocked::no_mshrs 1474 # number of cycles access was blocked |
| 1846system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1236system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1847system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.323108 # average number of cycles each access was blocked | 1237system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.198779 # average number of cycles each access was blocked |
| 1848system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1849system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1850system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1238system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1239system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1240system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1851system.cpu0.l2cache.writebacks::writebacks 212015 # number of writebacks 1852system.cpu0.l2cache.writebacks::total 212015 # number of writebacks | 1241system.cpu0.l2cache.writebacks::writebacks 211864 # number of writebacks 1242system.cpu0.l2cache.writebacks::total 211864 # number of writebacks |
| 1853system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits | 1243system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits |
| 1854system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5576 # number of ReadReq MSHR hits 1855system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3180 # number of ReadReq MSHR hits 1856system.cpu0.l2cache.ReadReq_mshr_hits::total 8757 # number of ReadReq MSHR hits 1857system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8826 # number of ReadExReq MSHR hits 1858system.cpu0.l2cache.ReadExReq_mshr_hits::total 8826 # number of ReadExReq MSHR hits | 1244system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5535 # number of ReadReq MSHR hits 1245system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3178 # number of ReadReq MSHR hits 1246system.cpu0.l2cache.ReadReq_mshr_hits::total 8714 # number of ReadReq MSHR hits 1247system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8807 # number of ReadExReq MSHR hits 1248system.cpu0.l2cache.ReadExReq_mshr_hits::total 8807 # number of ReadExReq MSHR hits |
| 1859system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits | 1249system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits |
| 1860system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5576 # number of demand (read+write) MSHR hits 1861system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12006 # number of demand (read+write) MSHR hits 1862system.cpu0.l2cache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits | 1250system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5535 # number of demand (read+write) MSHR hits 1251system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11985 # number of demand (read+write) MSHR hits 1252system.cpu0.l2cache.demand_mshr_hits::total 17521 # number of demand (read+write) MSHR hits |
| 1863system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits | 1253system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits |
| 1864system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5576 # number of overall MSHR hits 1865system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12006 # number of overall MSHR hits 1866system.cpu0.l2cache.overall_mshr_hits::total 17583 # number of overall MSHR hits 1867system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 556 # number of ReadReq MSHR misses 1868system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 203 # number of ReadReq MSHR misses 1869system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16249 # number of ReadReq MSHR misses 1870system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87629 # number of ReadReq MSHR misses 1871system.cpu0.l2cache.ReadReq_mshr_misses::total 104637 # number of ReadReq MSHR misses | 1254system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5535 # number of overall MSHR hits 1255system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11985 # number of overall MSHR hits 1256system.cpu0.l2cache.overall_mshr_hits::total 17521 # number of overall MSHR hits 1257system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 529 # number of ReadReq MSHR misses 1258system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 207 # number of ReadReq MSHR misses 1259system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16236 # number of ReadReq MSHR misses 1260system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87606 # number of ReadReq MSHR misses 1261system.cpu0.l2cache.ReadReq_mshr_misses::total 104578 # number of ReadReq MSHR misses |
| 1872system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1873system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses | 1262system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1263system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses |
| 1874system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of HardPFReq MSHR misses 1875system.cpu0.l2cache.HardPFReq_mshr_misses::total 482567 # number of HardPFReq MSHR misses 1876system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27941 # number of UpgradeReq MSHR misses 1877system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses | 1264system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 481571 # number of HardPFReq MSHR misses 1265system.cpu0.l2cache.HardPFReq_mshr_misses::total 481571 # number of HardPFReq MSHR misses 1266system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27958 # number of UpgradeReq MSHR misses 1267system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27958 # number of UpgradeReq MSHR misses |
| 1878system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18479 # number of SCUpgradeReq MSHR misses 1879system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18479 # number of SCUpgradeReq MSHR misses | 1268system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18479 # number of SCUpgradeReq MSHR misses 1269system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18479 # number of SCUpgradeReq MSHR misses |
| 1880system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43885 # number of ReadExReq MSHR misses 1881system.cpu0.l2cache.ReadExReq_mshr_misses::total 43885 # number of ReadExReq MSHR misses 1882system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 556 # number of demand (read+write) MSHR misses 1883system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 203 # number of demand (read+write) MSHR misses 1884system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16249 # number of demand (read+write) MSHR misses 1885system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131514 # number of demand (read+write) MSHR misses 1886system.cpu0.l2cache.demand_mshr_misses::total 148522 # number of demand (read+write) MSHR misses 1887system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 556 # number of overall MSHR misses 1888system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 203 # number of overall MSHR misses 1889system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16249 # number of overall MSHR misses 1890system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131514 # number of overall MSHR misses 1891system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of overall MSHR misses 1892system.cpu0.l2cache.overall_mshr_misses::total 631089 # number of overall MSHR misses 1893system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of ReadReq MSHR miss cycles 1894system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3620751 # number of ReadReq MSHR miss cycles 1895system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 587001511 # number of ReadReq MSHR miss cycles 1896system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2007365947 # number of ReadReq MSHR miss cycles 1897system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2608656960 # number of ReadReq MSHR miss cycles 1898system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of HardPFReq MSHR miss cycles 1899system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21948496416 # number of HardPFReq MSHR miss cycles 1900system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 481784375 # number of UpgradeReq MSHR miss cycles 1901system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481784375 # number of UpgradeReq MSHR miss cycles 1902system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249254743 # number of SCUpgradeReq MSHR miss cycles 1903system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249254743 # number of SCUpgradeReq MSHR miss cycles 1904system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 284000 # number of SCUpgradeFailReq MSHR miss cycles 1905system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 284000 # number of SCUpgradeFailReq MSHR miss cycles 1906system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315803854 # number of ReadExReq MSHR miss cycles 1907system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315803854 # number of ReadExReq MSHR miss cycles 1908system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of demand (read+write) MSHR miss cycles 1909system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3620751 # number of demand (read+write) MSHR miss cycles 1910system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 587001511 # number of demand (read+write) MSHR miss cycles 1911system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3323169801 # number of demand (read+write) MSHR miss cycles 1912system.cpu0.l2cache.demand_mshr_miss_latency::total 3924460814 # number of demand (read+write) MSHR miss cycles 1913system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of overall MSHR miss cycles 1914system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3620751 # number of overall MSHR miss cycles 1915system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 587001511 # number of overall MSHR miss cycles 1916system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3323169801 # number of overall MSHR miss cycles 1917system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of overall MSHR miss cycles 1918system.cpu0.l2cache.overall_mshr_miss_latency::total 25872957230 # number of overall MSHR miss cycles | 1270system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43949 # number of ReadExReq MSHR misses 1271system.cpu0.l2cache.ReadExReq_mshr_misses::total 43949 # number of ReadExReq MSHR misses 1272system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 529 # number of demand (read+write) MSHR misses 1273system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 207 # number of demand (read+write) MSHR misses 1274system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16236 # number of demand (read+write) MSHR misses 1275system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131555 # number of demand (read+write) MSHR misses 1276system.cpu0.l2cache.demand_mshr_misses::total 148527 # number of demand (read+write) MSHR misses 1277system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 529 # number of overall MSHR misses 1278system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 207 # number of overall MSHR misses 1279system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16236 # number of overall MSHR misses 1280system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131555 # number of overall MSHR misses 1281system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 481571 # number of overall MSHR misses 1282system.cpu0.l2cache.overall_mshr_misses::total 630098 # number of overall MSHR misses 1283system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10212251 # number of ReadReq MSHR miss cycles 1284system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3484000 # number of ReadReq MSHR miss cycles 1285system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 587444763 # number of ReadReq MSHR miss cycles 1286system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2008905945 # number of ReadReq MSHR miss cycles 1287system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2610046959 # number of ReadReq MSHR miss cycles 1288system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21960966186 # number of HardPFReq MSHR miss cycles 1289system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21960966186 # number of HardPFReq MSHR miss cycles 1290system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 481827867 # number of UpgradeReq MSHR miss cycles 1291system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481827867 # number of UpgradeReq MSHR miss cycles 1292system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249217743 # number of SCUpgradeReq MSHR miss cycles 1293system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249217743 # number of SCUpgradeReq MSHR miss cycles 1294system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 244500 # number of SCUpgradeFailReq MSHR miss cycles 1295system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 244500 # number of SCUpgradeFailReq MSHR miss cycles 1296system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1317766861 # number of ReadExReq MSHR miss cycles 1297system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1317766861 # number of ReadExReq MSHR miss cycles 1298system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10212251 # number of demand (read+write) MSHR miss cycles 1299system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3484000 # number of demand (read+write) MSHR miss cycles 1300system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 587444763 # number of demand (read+write) MSHR miss cycles 1301system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3326672806 # number of demand (read+write) MSHR miss cycles 1302system.cpu0.l2cache.demand_mshr_miss_latency::total 3927813820 # number of demand (read+write) MSHR miss cycles 1303system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10212251 # number of overall MSHR miss cycles 1304system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3484000 # number of overall MSHR miss cycles 1305system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 587444763 # number of overall MSHR miss cycles 1306system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3326672806 # number of overall MSHR miss cycles 1307system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21960966186 # number of overall MSHR miss cycles 1308system.cpu0.l2cache.overall_mshr_miss_latency::total 25888780006 # number of overall MSHR miss cycles |
| 1919system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles | 1309system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles |
| 1920system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053946738 # number of ReadReq MSHR uncacheable cycles 1921system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272660488 # number of ReadReq MSHR uncacheable cycles 1922system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040262957 # number of WriteReq MSHR uncacheable cycles 1923system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040262957 # number of WriteReq MSHR uncacheable cycles | 1310system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053860233 # number of ReadReq MSHR uncacheable cycles 1311system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272573983 # number of ReadReq MSHR uncacheable cycles 1312system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040265950 # number of WriteReq MSHR uncacheable cycles 1313system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040265950 # number of WriteReq MSHR uncacheable cycles |
| 1924system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles | 1314system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles |
| 1925system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7094209695 # number of overall MSHR uncacheable cycles 1926system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312923445 # number of overall MSHR uncacheable cycles 1927system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for ReadReq accesses 1928system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for ReadReq accesses 1929system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for ReadReq accesses 1930system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175912 # mshr miss rate for ReadReq accesses 1931system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057195 # mshr miss rate for ReadReq accesses | 1315system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7094126183 # number of overall MSHR uncacheable cycles 1316system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312839933 # number of overall MSHR uncacheable cycles 1317system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for ReadReq accesses 1318system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for ReadReq accesses 1319system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for ReadReq accesses 1320system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175860 # mshr miss rate for ReadReq accesses 1321system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057167 # mshr miss rate for ReadReq accesses |
| 1932system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses 1933system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses 1934system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1935system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1322system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses 1323system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses 1324system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1325system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1936system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645826 # mshr miss rate for UpgradeReq accesses 1937system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645826 # mshr miss rate for UpgradeReq accesses 1938system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896734 # mshr miss rate for SCUpgradeReq accesses 1939system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896734 # mshr miss rate for SCUpgradeReq accesses 1940system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162866 # mshr miss rate for ReadExReq accesses 1941system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162866 # mshr miss rate for ReadExReq accesses 1942system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for demand accesses 1943system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for demand accesses 1944system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for demand accesses 1945system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for demand accesses 1946system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070761 # mshr miss rate for demand accesses 1947system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for overall accesses 1948system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for overall accesses 1949system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for overall accesses 1950system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for overall accesses | 1326system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645711 # mshr miss rate for UpgradeReq accesses 1327system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645711 # mshr miss rate for UpgradeReq accesses 1328system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896517 # mshr miss rate for SCUpgradeReq accesses 1329system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896517 # mshr miss rate for SCUpgradeReq accesses 1330system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163093 # mshr miss rate for ReadExReq accesses 1331system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163093 # mshr miss rate for ReadExReq accesses 1332system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for demand accesses 1333system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for demand accesses 1334system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for demand accesses 1335system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171378 # mshr miss rate for demand accesses 1336system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070767 # mshr miss rate for demand accesses 1337system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009683 # mshr miss rate for overall accesses 1338system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016704 # mshr miss rate for overall accesses 1339system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for overall accesses 1340system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171378 # mshr miss rate for overall accesses |
| 1951system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1341system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1952system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300672 # mshr miss rate for overall accesses 1953system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average ReadReq mshr miss latency 1954system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average ReadReq mshr miss latency 1955system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average ReadReq mshr miss latency 1956system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22907.552831 # average ReadReq mshr miss latency 1957system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24930.540440 # average ReadReq mshr miss latency 1958system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average HardPFReq mshr miss latency 1959system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45482.795997 # average HardPFReq mshr miss latency 1960system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17242.918113 # average UpgradeReq mshr miss latency 1961system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17242.918113 # average UpgradeReq mshr miss latency 1962system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13488.540668 # average SCUpgradeReq mshr miss latency 1963system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13488.540668 # average SCUpgradeReq mshr miss latency | 1342system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300217 # mshr miss rate for overall accesses 1343system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average ReadReq mshr miss latency 1344system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average ReadReq mshr miss latency 1345system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average ReadReq mshr miss latency 1346system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22931.145641 # average ReadReq mshr miss latency 1347system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24957.897062 # average ReadReq mshr miss latency 1348system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858 # average HardPFReq mshr miss latency 1349system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45602.758858 # average HardPFReq mshr miss latency 1350system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17233.989091 # average UpgradeReq mshr miss latency 1351system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17233.989091 # average UpgradeReq mshr miss latency 1352system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13486.538395 # average SCUpgradeReq mshr miss latency 1353system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13486.538395 # average SCUpgradeReq mshr miss latency |
| 1964system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1965system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 1354system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1355system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 1966system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29982.997699 # average ReadExReq mshr miss latency 1967system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29982.997699 # average ReadExReq mshr miss latency 1968system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency 1969system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency 1970system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency 1971system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency 1972system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26423.430966 # average overall mshr miss latency 1973system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency 1974system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency 1975system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency 1976system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency 1977system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average overall mshr miss latency 1978system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40997.319285 # average overall mshr miss latency | 1356system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29984.001024 # average ReadExReq mshr miss latency 1357system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29984.001024 # average ReadExReq mshr miss latency 1358system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average overall mshr miss latency 1359system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average overall mshr miss latency 1360system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average overall mshr miss latency 1361system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25287.315617 # average overall mshr miss latency 1362system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26445.116511 # average overall mshr miss latency 1363system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306 # average overall mshr miss latency 1364system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874 # average overall mshr miss latency 1365system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36181.618810 # average overall mshr miss latency 1366system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25287.315617 # average overall mshr miss latency 1367system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858 # average overall mshr miss latency 1368system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41086.910300 # average overall mshr miss latency |
| 1979system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1980system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1981system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1982system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1983system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1984system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1985system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1986system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1987system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1369system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1370system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1371system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1372system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1373system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1374system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1375system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1376system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1377system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1988system.cpu0.dcache.tags.replacements 712829 # number of replacements 1989system.cpu0.dcache.tags.tagsinuse 493.082766 # Cycle average of tags in use 1990system.cpu0.dcache.tags.total_refs 28841671 # Total number of references to valid blocks. 1991system.cpu0.dcache.tags.sampled_refs 713341 # Sample count of references to valid blocks. 1992system.cpu0.dcache.tags.avg_refs 40.431815 # Average number of references to valid blocks. 1993system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. 1994system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082766 # Average occupied blocks per requestor 1995system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy 1996system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy 1997system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1998system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id 1999system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 2000system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 2001system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2002system.cpu0.dcache.tags.tag_accesses 63481444 # Number of tag accesses 2003system.cpu0.dcache.tags.data_accesses 63481444 # Number of data accesses 2004system.cpu0.dcache.ReadReq_hits::cpu0.data 15588806 # number of ReadReq hits 2005system.cpu0.dcache.ReadReq_hits::total 15588806 # number of ReadReq hits 2006system.cpu0.dcache.WriteReq_hits::cpu0.data 12071580 # number of WriteReq hits 2007system.cpu0.dcache.WriteReq_hits::total 12071580 # number of WriteReq hits 2008system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311031 # number of SoftPFReq hits 2009system.cpu0.dcache.SoftPFReq_hits::total 311031 # number of SoftPFReq hits 2010system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363190 # number of LoadLockedReq hits 2011system.cpu0.dcache.LoadLockedReq_hits::total 363190 # number of LoadLockedReq hits 2012system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360636 # number of StoreCondReq hits 2013system.cpu0.dcache.StoreCondReq_hits::total 360636 # number of StoreCondReq hits 2014system.cpu0.dcache.demand_hits::cpu0.data 27660386 # number of demand (read+write) hits 2015system.cpu0.dcache.demand_hits::total 27660386 # number of demand (read+write) hits 2016system.cpu0.dcache.overall_hits::cpu0.data 27971417 # number of overall hits 2017system.cpu0.dcache.overall_hits::total 27971417 # number of overall hits 2018system.cpu0.dcache.ReadReq_misses::cpu0.data 638107 # number of ReadReq misses 2019system.cpu0.dcache.ReadReq_misses::total 638107 # number of ReadReq misses 2020system.cpu0.dcache.WriteReq_misses::cpu0.data 1831928 # number of WriteReq misses 2021system.cpu0.dcache.WriteReq_misses::total 1831928 # number of WriteReq misses 2022system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146057 # number of SoftPFReq misses 2023system.cpu0.dcache.SoftPFReq_misses::total 146057 # number of SoftPFReq misses 2024system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses 2025system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses 2026system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20607 # number of StoreCondReq misses 2027system.cpu0.dcache.StoreCondReq_misses::total 20607 # number of StoreCondReq misses 2028system.cpu0.dcache.demand_misses::cpu0.data 2470035 # number of demand (read+write) misses 2029system.cpu0.dcache.demand_misses::total 2470035 # number of demand (read+write) misses 2030system.cpu0.dcache.overall_misses::cpu0.data 2616092 # number of overall misses 2031system.cpu0.dcache.overall_misses::total 2616092 # number of overall misses 2032system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8089240805 # number of ReadReq miss cycles 2033system.cpu0.dcache.ReadReq_miss_latency::total 8089240805 # number of ReadReq miss cycles 2034system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24966494558 # number of WriteReq miss cycles 2035system.cpu0.dcache.WriteReq_miss_latency::total 24966494558 # number of WriteReq miss cycles 2036system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395038253 # number of LoadLockedReq miss cycles 2037system.cpu0.dcache.LoadLockedReq_miss_latency::total 395038253 # number of LoadLockedReq miss cycles 2038system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453870788 # number of StoreCondReq miss cycles 2039system.cpu0.dcache.StoreCondReq_miss_latency::total 453870788 # number of StoreCondReq miss cycles 2040system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 394000 # number of StoreCondFailReq miss cycles 2041system.cpu0.dcache.StoreCondFailReq_miss_latency::total 394000 # number of StoreCondFailReq miss cycles 2042system.cpu0.dcache.demand_miss_latency::cpu0.data 33055735363 # number of demand (read+write) miss cycles 2043system.cpu0.dcache.demand_miss_latency::total 33055735363 # number of demand (read+write) miss cycles 2044system.cpu0.dcache.overall_miss_latency::cpu0.data 33055735363 # number of overall miss cycles 2045system.cpu0.dcache.overall_miss_latency::total 33055735363 # number of overall miss cycles 2046system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226913 # number of ReadReq accesses(hits+misses) 2047system.cpu0.dcache.ReadReq_accesses::total 16226913 # number of ReadReq accesses(hits+misses) 2048system.cpu0.dcache.WriteReq_accesses::cpu0.data 13903508 # number of WriteReq accesses(hits+misses) 2049system.cpu0.dcache.WriteReq_accesses::total 13903508 # number of WriteReq accesses(hits+misses) 2050system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457088 # number of SoftPFReq accesses(hits+misses) 2051system.cpu0.dcache.SoftPFReq_accesses::total 457088 # number of SoftPFReq accesses(hits+misses) 2052system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388166 # number of LoadLockedReq accesses(hits+misses) 2053system.cpu0.dcache.LoadLockedReq_accesses::total 388166 # number of LoadLockedReq accesses(hits+misses) 2054system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381243 # number of StoreCondReq accesses(hits+misses) 2055system.cpu0.dcache.StoreCondReq_accesses::total 381243 # number of StoreCondReq accesses(hits+misses) 2056system.cpu0.dcache.demand_accesses::cpu0.data 30130421 # number of demand (read+write) accesses 2057system.cpu0.dcache.demand_accesses::total 30130421 # number of demand (read+write) accesses 2058system.cpu0.dcache.overall_accesses::cpu0.data 30587509 # number of overall (read+write) accesses 2059system.cpu0.dcache.overall_accesses::total 30587509 # number of overall (read+write) accesses 2060system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039324 # miss rate for ReadReq accesses 2061system.cpu0.dcache.ReadReq_miss_rate::total 0.039324 # miss rate for ReadReq accesses 2062system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131760 # miss rate for WriteReq accesses 2063system.cpu0.dcache.WriteReq_miss_rate::total 0.131760 # miss rate for WriteReq accesses 2064system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319538 # miss rate for SoftPFReq accesses 2065system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319538 # miss rate for SoftPFReq accesses 2066system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064344 # miss rate for LoadLockedReq accesses 2067system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064344 # miss rate for LoadLockedReq accesses 2068system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054052 # miss rate for StoreCondReq accesses 2069system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054052 # miss rate for StoreCondReq accesses 2070system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081978 # miss rate for demand accesses 2071system.cpu0.dcache.demand_miss_rate::total 0.081978 # miss rate for demand accesses 2072system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085528 # miss rate for overall accesses 2073system.cpu0.dcache.overall_miss_rate::total 0.085528 # miss rate for overall accesses 2074system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12676.934754 # average ReadReq miss latency 2075system.cpu0.dcache.ReadReq_avg_miss_latency::total 12676.934754 # average ReadReq miss latency 2076system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13628.534832 # average WriteReq miss latency 2077system.cpu0.dcache.WriteReq_avg_miss_latency::total 13628.534832 # average WriteReq miss latency 2078system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.714166 # average LoadLockedReq miss latency 2079system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.714166 # average LoadLockedReq miss latency 2080system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22025.078274 # average StoreCondReq miss latency 2081system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22025.078274 # average StoreCondReq miss latency 2082system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 2083system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2084system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13382.699178 # average overall miss latency 2085system.cpu0.dcache.demand_avg_miss_latency::total 13382.699178 # average overall miss latency 2086system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12635.540097 # average overall miss latency 2087system.cpu0.dcache.overall_avg_miss_latency::total 12635.540097 # average overall miss latency 2088system.cpu0.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked 2089system.cpu0.dcache.blocked_cycles::no_targets 3370028 # number of cycles access was blocked 2090system.cpu0.dcache.blocked::no_mshrs 68 # number of cycles access was blocked 2091system.cpu0.dcache.blocked::no_targets 191306 # number of cycles access was blocked 2092system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.602941 # average number of cycles each access was blocked 2093system.cpu0.dcache.avg_blocked_cycles::no_targets 17.615903 # average number of cycles each access was blocked 2094system.cpu0.dcache.fast_writes 0 # number of fast writes performed 2095system.cpu0.dcache.cache_copies 0 # number of cache copies performed 2096system.cpu0.dcache.writebacks::writebacks 512971 # number of writebacks 2097system.cpu0.dcache.writebacks::total 512971 # number of writebacks 2098system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 247929 # number of ReadReq MSHR hits 2099system.cpu0.dcache.ReadReq_mshr_hits::total 247929 # number of ReadReq MSHR hits 2100system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519381 # number of WriteReq MSHR hits 2101system.cpu0.dcache.WriteReq_mshr_hits::total 1519381 # number of WriteReq MSHR hits 2102system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18420 # number of LoadLockedReq MSHR hits 2103system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18420 # number of LoadLockedReq MSHR hits 2104system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767310 # number of demand (read+write) MSHR hits 2105system.cpu0.dcache.demand_mshr_hits::total 1767310 # number of demand (read+write) MSHR hits 2106system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767310 # number of overall MSHR hits 2107system.cpu0.dcache.overall_mshr_hits::total 1767310 # number of overall MSHR hits 2108system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390178 # number of ReadReq MSHR misses 2109system.cpu0.dcache.ReadReq_mshr_misses::total 390178 # number of ReadReq MSHR misses 2110system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312547 # number of WriteReq MSHR misses 2111system.cpu0.dcache.WriteReq_mshr_misses::total 312547 # number of WriteReq MSHR misses 2112system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101517 # number of SoftPFReq MSHR misses 2113system.cpu0.dcache.SoftPFReq_mshr_misses::total 101517 # number of SoftPFReq MSHR misses 2114system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses 2115system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses 2116system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20607 # number of StoreCondReq MSHR misses 2117system.cpu0.dcache.StoreCondReq_mshr_misses::total 20607 # number of StoreCondReq MSHR misses 2118system.cpu0.dcache.demand_mshr_misses::cpu0.data 702725 # number of demand (read+write) MSHR misses 2119system.cpu0.dcache.demand_mshr_misses::total 702725 # number of demand (read+write) MSHR misses 2120system.cpu0.dcache.overall_mshr_misses::cpu0.data 804242 # number of overall MSHR misses 2121system.cpu0.dcache.overall_mshr_misses::total 804242 # number of overall MSHR misses 2122system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170870238 # number of ReadReq MSHR miss cycles 2123system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170870238 # number of ReadReq MSHR miss cycles 2124system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4998082086 # number of WriteReq MSHR miss cycles 2125system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4998082086 # number of WriteReq MSHR miss cycles 2126system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1413907491 # number of SoftPFReq MSHR miss cycles 2127system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1413907491 # number of SoftPFReq MSHR miss cycles 2128system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97710498 # number of LoadLockedReq MSHR miss cycles 2129system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97710498 # number of LoadLockedReq MSHR miss cycles 2130system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411958212 # number of StoreCondReq MSHR miss cycles 2131system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411958212 # number of StoreCondReq MSHR miss cycles 2132system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 372000 # number of StoreCondFailReq MSHR miss cycles 2133system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 372000 # number of StoreCondFailReq MSHR miss cycles 2134system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9168952324 # number of demand (read+write) MSHR miss cycles 2135system.cpu0.dcache.demand_mshr_miss_latency::total 9168952324 # number of demand (read+write) MSHR miss cycles 2136system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10582859815 # number of overall MSHR miss cycles 2137system.cpu0.dcache.overall_mshr_miss_latency::total 10582859815 # number of overall MSHR miss cycles 2138system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217153741 # number of ReadReq MSHR uncacheable cycles 2139system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217153741 # number of ReadReq MSHR uncacheable cycles 2140system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187052487 # number of WriteReq MSHR uncacheable cycles 2141system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187052487 # number of WriteReq MSHR uncacheable cycles 2142system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404206228 # number of overall MSHR uncacheable cycles 2143system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404206228 # number of overall MSHR uncacheable cycles 2144system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses 2145system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses 2146system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022480 # mshr miss rate for WriteReq accesses 2147system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022480 # mshr miss rate for WriteReq accesses 2148system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222095 # mshr miss rate for SoftPFReq accesses 2149system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222095 # mshr miss rate for SoftPFReq accesses 2150system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016890 # mshr miss rate for LoadLockedReq accesses 2151system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016890 # mshr miss rate for LoadLockedReq accesses 2152system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054052 # mshr miss rate for StoreCondReq accesses 2153system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054052 # mshr miss rate for StoreCondReq accesses 2154system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023323 # mshr miss rate for demand accesses 2155system.cpu0.dcache.demand_mshr_miss_rate::total 0.023323 # mshr miss rate for demand accesses 2156system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026293 # mshr miss rate for overall accesses 2157system.cpu0.dcache.overall_mshr_miss_rate::total 0.026293 # mshr miss rate for overall accesses 2158system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10689.660201 # average ReadReq mshr miss latency 2159system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10689.660201 # average ReadReq mshr miss latency 2160system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15991.457560 # average WriteReq mshr miss latency 2161system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15991.457560 # average WriteReq mshr miss latency 2162system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13927.790331 # average SoftPFReq mshr miss latency 2163system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13927.790331 # average SoftPFReq mshr miss latency 2164system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14903.980781 # average LoadLockedReq mshr miss latency 2165system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14903.980781 # average LoadLockedReq mshr miss latency 2166system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19991.178337 # average StoreCondReq mshr miss latency 2167system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19991.178337 # average StoreCondReq mshr miss latency 2168system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2169system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2170system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13047.710447 # average overall mshr miss latency 2171system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13047.710447 # average overall mshr miss latency 2172system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13158.800231 # average overall mshr miss latency 2173system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13158.800231 # average overall mshr miss latency 2174system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2175system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2176system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2177system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2178system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2179system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2180system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2181system.cpu1.branchPred.lookups 33910931 # Number of BP lookups 2182system.cpu1.branchPred.condPredicted 11562938 # Number of conditional branches predicted 2183system.cpu1.branchPred.condIncorrect 305104 # Number of conditional branches incorrect 2184system.cpu1.branchPred.BTBLookups 18756149 # Number of BTB lookups 2185system.cpu1.branchPred.BTBHits 14959197 # Number of BTB hits | 1378system.cpu0.toL2Bus.trans_dist::ReadReq 2021884 # Transaction distribution 1379system.cpu0.toL2Bus.trans_dist::ReadResp 1920690 # Transaction distribution 1380system.cpu0.toL2Bus.trans_dist::WriteReq 19107 # Transaction distribution 1381system.cpu0.toL2Bus.trans_dist::WriteResp 19107 # Transaction distribution 1382system.cpu0.toL2Bus.trans_dist::Writeback 513073 # Transaction distribution 1383system.cpu0.toL2Bus.trans_dist::HardPFReq 646583 # Transaction distribution 1384system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution 1385system.cpu0.toL2Bus.trans_dist::UpgradeReq 80962 # Transaction distribution 1386system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43193 # Transaction distribution 1387system.cpu0.toL2Bus.trans_dist::UpgradeResp 104964 # Transaction distribution 1388system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution 1389system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 1390system.cpu0.toL2Bus.trans_dist::ReadExReq 291894 # Transaction distribution 1391system.cpu0.toL2Bus.trans_dist::ReadExResp 281156 # Transaction distribution 1392system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534332 # Packet count per connected master and slave (bytes) 1393system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360691 # Packet count per connected master and slave (bytes) 1394system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28712 # Packet count per connected master and slave (bytes) 1395system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120464 # Packet count per connected master and slave (bytes) 1396system.cpu0.toL2Bus.pkt_count::total 5044199 # Packet count per connected master and slave (bytes) 1397system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953568 # Cumulative packet size per connected master and slave (bytes) 1398system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86204446 # Cumulative packet size per connected master and slave (bytes) 1399system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49568 # Cumulative packet size per connected master and slave (bytes) 1400system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218536 # Cumulative packet size per connected master and slave (bytes) 1401system.cpu0.toL2Bus.pkt_size::total 167426118 # Cumulative packet size per connected master and slave (bytes) 1402system.cpu0.toL2Bus.snoops 1040274 # Total snoops (count) 1403system.cpu0.toL2Bus.snoop_fanout::samples 3610797 # Request fanout histogram 1404system.cpu0.toL2Bus.snoop_fanout::mean 5.254659 # Request fanout histogram 1405system.cpu0.toL2Bus.snoop_fanout::stdev 0.435670 # Request fanout histogram 1406system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1407system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1408system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1409system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1410system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1411system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1412system.cpu0.toL2Bus.snoop_fanout::5 2691274 74.53% 74.53% # Request fanout histogram 1413system.cpu0.toL2Bus.snoop_fanout::6 919523 25.47% 100.00% # Request fanout histogram 1414system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1415system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1416system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1417system.cpu0.toL2Bus.snoop_fanout::total 3610797 # Request fanout histogram 1418system.cpu0.toL2Bus.reqLayer0.occupancy 1890423984 # Layer occupancy (ticks) 1419system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1420system.cpu0.toL2Bus.snoopLayer0.occupancy 117333499 # Layer occupancy (ticks) 1421system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1422system.cpu0.toL2Bus.respLayer0.occupancy 1901305348 # Layer occupancy (ticks) 1423system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1424system.cpu0.toL2Bus.respLayer1.occupancy 1220101128 # Layer occupancy (ticks) 1425system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1426system.cpu0.toL2Bus.respLayer2.occupancy 16329482 # Layer occupancy (ticks) 1427system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1428system.cpu0.toL2Bus.respLayer3.occupancy 65866183 # Layer occupancy (ticks) 1429system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1430system.cpu1.branchPred.lookups 33911271 # Number of BP lookups 1431system.cpu1.branchPred.condPredicted 11563003 # Number of conditional branches predicted 1432system.cpu1.branchPred.condIncorrect 305102 # Number of conditional branches incorrect 1433system.cpu1.branchPred.BTBLookups 18755199 # Number of BTB lookups 1434system.cpu1.branchPred.BTBHits 14959397 # Number of BTB hits |
| 2186system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1435system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 2187system.cpu1.branchPred.BTBHitPct 79.756228 # BTB Hit Percentage 2188system.cpu1.branchPred.usedRAS 12490116 # Number of times the RAS was used to get a target. 2189system.cpu1.branchPred.RASInCorrect 7241 # Number of incorrect RAS predictions. | 1436system.cpu1.branchPred.BTBHitPct 79.761334 # BTB Hit Percentage 1437system.cpu1.branchPred.usedRAS 12490268 # Number of times the RAS was used to get a target. 1438system.cpu1.branchPred.RASInCorrect 7230 # Number of incorrect RAS predictions. |
| 2190system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2191system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2192system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2193system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2194system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2195system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2196system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2197system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 2205system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2206system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2207system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2208system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2209system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2210system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2211system.cpu1.dtb.inst_hits 0 # ITB inst hits 2212system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1439system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1440system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1441system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1442system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1443system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1444system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1445system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1446system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1454system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1455system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1456system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1457system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1458system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1459system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1460system.cpu1.dtb.inst_hits 0 # ITB inst hits 1461system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 2213system.cpu1.dtb.read_hits 10163466 # DTB read hits 2214system.cpu1.dtb.read_misses 18799 # DTB read misses 2215system.cpu1.dtb.write_hits 6542146 # DTB write hits 2216system.cpu1.dtb.write_misses 2834 # DTB write misses | 1462system.cpu1.dtb.read_hits 10163694 # DTB read hits 1463system.cpu1.dtb.read_misses 18763 # DTB read misses 1464system.cpu1.dtb.write_hits 6542250 # DTB write hits 1465system.cpu1.dtb.write_misses 2833 # DTB write misses |
| 2217system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 2218system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 2219system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2220system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1466system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1467system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1468system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1469system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 2221system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB | 1470system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB |
| 2222system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions 2223system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch 2224system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1471system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions 1472system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch 1473system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 2225system.cpu1.dtb.perms_faults 406 # Number of TLB faults due to permissions restrictions 2226system.cpu1.dtb.read_accesses 10182265 # DTB read accesses 2227system.cpu1.dtb.write_accesses 6544980 # DTB write accesses | 1474system.cpu1.dtb.perms_faults 411 # Number of TLB faults due to permissions restrictions 1475system.cpu1.dtb.read_accesses 10182457 # DTB read accesses 1476system.cpu1.dtb.write_accesses 6545083 # DTB write accesses |
| 2228system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1477system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 2229system.cpu1.dtb.hits 16705612 # DTB hits 2230system.cpu1.dtb.misses 21633 # DTB misses 2231system.cpu1.dtb.accesses 16727245 # DTB accesses | 1478system.cpu1.dtb.hits 16705944 # DTB hits 1479system.cpu1.dtb.misses 21596 # DTB misses 1480system.cpu1.dtb.accesses 16727540 # DTB accesses |
| 2232system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2233system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2234system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2235system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2236system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2237system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2238system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2239system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 2245system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2246system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2247system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2248system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2249system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2250system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2251system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2252system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1481system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1482system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1483system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1484system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1485system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1486system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1487system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1488system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1494system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1495system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1496system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1497system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1498system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1499system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1500system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1501system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 2253system.cpu1.itb.inst_hits 43642051 # ITB inst hits 2254system.cpu1.itb.inst_misses 6989 # ITB inst misses | 1502system.cpu1.itb.inst_hits 43642438 # ITB inst hits 1503system.cpu1.itb.inst_misses 7000 # ITB inst misses |
| 2255system.cpu1.itb.read_hits 0 # DTB read hits 2256system.cpu1.itb.read_misses 0 # DTB read misses 2257system.cpu1.itb.write_hits 0 # DTB write hits 2258system.cpu1.itb.write_misses 0 # DTB write misses 2259system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 2260system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 2261system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2262system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1504system.cpu1.itb.read_hits 0 # DTB read hits 1505system.cpu1.itb.read_misses 0 # DTB read misses 1506system.cpu1.itb.write_hits 0 # DTB write hits 1507system.cpu1.itb.write_misses 0 # DTB write misses 1508system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1509system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1510system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1511system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 2263system.cpu1.itb.flush_entries 1203 # Number of entries that have been flushed from TLB | 1512system.cpu1.itb.flush_entries 1205 # Number of entries that have been flushed from TLB |
| 2264system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2265system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2266system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1513system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1514system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1515system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 2267system.cpu1.itb.perms_faults 541 # Number of TLB faults due to permissions restrictions | 1516system.cpu1.itb.perms_faults 538 # Number of TLB faults due to permissions restrictions |
| 2268system.cpu1.itb.read_accesses 0 # DTB read accesses 2269system.cpu1.itb.write_accesses 0 # DTB write accesses | 1517system.cpu1.itb.read_accesses 0 # DTB read accesses 1518system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 2270system.cpu1.itb.inst_accesses 43649040 # ITB inst accesses 2271system.cpu1.itb.hits 43642051 # DTB hits 2272system.cpu1.itb.misses 6989 # DTB misses 2273system.cpu1.itb.accesses 43649040 # DTB accesses 2274system.cpu1.numCycles 104614253 # number of cpu cycles simulated | 1519system.cpu1.itb.inst_accesses 43649438 # ITB inst accesses 1520system.cpu1.itb.hits 43642438 # DTB hits 1521system.cpu1.itb.misses 7000 # DTB misses 1522system.cpu1.itb.accesses 43649438 # DTB accesses 1523system.cpu1.numCycles 104622324 # number of cpu cycles simulated |
| 2275system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2276system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1524system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1525system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2277system.cpu1.fetch.icacheStallCycles 9984991 # Number of cycles fetch is stalled on an Icache miss 2278system.cpu1.fetch.Insts 109167147 # Number of instructions fetch has processed 2279system.cpu1.fetch.Branches 33910931 # Number of branches that fetch encountered 2280system.cpu1.fetch.predictedBranches 27449313 # Number of branches that fetch has predicted taken 2281system.cpu1.fetch.Cycles 91788694 # Number of cycles fetch has run and was not squashing or blocked 2282system.cpu1.fetch.SquashCycles 3775566 # Number of cycles fetch has spent squashing 2283system.cpu1.fetch.TlbCycles 78493 # Number of cycles fetch has spent waiting for tlb 2284system.cpu1.fetch.MiscStallCycles 31389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2285system.cpu1.fetch.PendingTrapStallCycles 199715 # Number of stall cycles due to pending traps 2286system.cpu1.fetch.PendingQuiesceStallCycles 294230 # Number of stall cycles due to pending quiesce instructions 2287system.cpu1.fetch.IcacheWaitRetryStallCycles 7403 # Number of stall cycles due to full MSHR 2288system.cpu1.fetch.CacheLines 43641443 # Number of cache lines fetched 2289system.cpu1.fetch.IcacheSquashes 116254 # Number of outstanding Icache misses that were squashed 2290system.cpu1.fetch.ItlbSquashes 2254 # Number of outstanding ITLB misses that were squashed 2291system.cpu1.fetch.rateDist::samples 104272698 # Number of instructions fetched each cycle (Total) 2292system.cpu1.fetch.rateDist::mean 1.296959 # Number of instructions fetched each cycle (Total) 2293system.cpu1.fetch.rateDist::stdev 1.339784 # Number of instructions fetched each cycle (Total) | 1526system.cpu1.fetch.icacheStallCycles 9983715 # Number of cycles fetch is stalled on an Icache miss 1527system.cpu1.fetch.Insts 109168018 # Number of instructions fetch has processed 1528system.cpu1.fetch.Branches 33911271 # Number of branches that fetch encountered 1529system.cpu1.fetch.predictedBranches 27449665 # Number of branches that fetch has predicted taken 1530system.cpu1.fetch.Cycles 91793931 # Number of cycles fetch has run and was not squashing or blocked 1531system.cpu1.fetch.SquashCycles 3775602 # Number of cycles fetch has spent squashing 1532system.cpu1.fetch.TlbCycles 78298 # Number of cycles fetch has spent waiting for tlb 1533system.cpu1.fetch.MiscStallCycles 31640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1534system.cpu1.fetch.PendingTrapStallCycles 200637 # Number of stall cycles due to pending traps 1535system.cpu1.fetch.PendingQuiesceStallCycles 294928 # Number of stall cycles due to pending quiesce instructions 1536system.cpu1.fetch.IcacheWaitRetryStallCycles 7575 # Number of stall cycles due to full MSHR 1537system.cpu1.fetch.CacheLines 43641835 # Number of cache lines fetched 1538system.cpu1.fetch.IcacheSquashes 116209 # Number of outstanding Icache misses that were squashed 1539system.cpu1.fetch.ItlbSquashes 2258 # Number of outstanding ITLB misses that were squashed 1540system.cpu1.fetch.rateDist::samples 104278525 # Number of instructions fetched each cycle (Total) 1541system.cpu1.fetch.rateDist::mean 1.296897 # Number of instructions fetched each cycle (Total) 1542system.cpu1.fetch.rateDist::stdev 1.339782 # Number of instructions fetched each cycle (Total) |
| 2294system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1543system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 2295system.cpu1.fetch.rateDist::0 47324573 45.39% 45.39% # Number of instructions fetched each cycle (Total) 2296system.cpu1.fetch.rateDist::1 14035291 13.46% 58.85% # Number of instructions fetched each cycle (Total) 2297system.cpu1.fetch.rateDist::2 7536357 7.23% 66.07% # Number of instructions fetched each cycle (Total) 2298system.cpu1.fetch.rateDist::3 35376477 33.93% 100.00% # Number of instructions fetched each cycle (Total) | 1544system.cpu1.fetch.rateDist::0 47329971 45.39% 45.39% # Number of instructions fetched each cycle (Total) 1545system.cpu1.fetch.rateDist::1 14035379 13.46% 58.85% # Number of instructions fetched each cycle (Total) 1546system.cpu1.fetch.rateDist::2 7536372 7.23% 66.07% # Number of instructions fetched each cycle (Total) 1547system.cpu1.fetch.rateDist::3 35376803 33.93% 100.00% # Number of instructions fetched each cycle (Total) |
| 2299system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2300system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2301system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1548system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1549system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1550system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 2302system.cpu1.fetch.rateDist::total 104272698 # Number of instructions fetched each cycle (Total) 2303system.cpu1.fetch.branchRate 0.324152 # Number of branch fetches per cycle 2304system.cpu1.fetch.rate 1.043521 # Number of inst fetches per cycle 2305system.cpu1.decode.IdleCycles 13017206 # Number of cycles decode is idle 2306system.cpu1.decode.BlockedCycles 61665780 # Number of cycles decode is blocked 2307system.cpu1.decode.RunCycles 26725185 # Number of cycles decode is running 2308system.cpu1.decode.UnblockCycles 1111466 # Number of cycles decode is unblocking 2309system.cpu1.decode.SquashCycles 1753061 # Number of cycles decode is squashing 2310system.cpu1.decode.BranchResolved 754244 # Number of times decode resolved a branch 2311system.cpu1.decode.BranchMispred 137628 # Number of times decode detected a branch misprediction 2312system.cpu1.decode.DecodedInsts 68061507 # Number of instructions handled by decode 2313system.cpu1.decode.SquashedInsts 1169291 # Number of squashed instructions handled by decode 2314system.cpu1.rename.SquashCycles 1753061 # Number of cycles rename is squashing 2315system.cpu1.rename.IdleCycles 17449719 # Number of cycles rename is idle 2316system.cpu1.rename.BlockCycles 2249370 # Number of cycles rename is blocking 2317system.cpu1.rename.serializeStallCycles 56981821 # count of cycles rename stalled for serializing inst 2318system.cpu1.rename.RunCycles 23380432 # Number of cycles rename is running 2319system.cpu1.rename.UnblockCycles 2458295 # Number of cycles rename is unblocking 2320system.cpu1.rename.RenamedInsts 55156803 # Number of instructions processed by rename 2321system.cpu1.rename.SquashedInsts 230618 # Number of squashed instructions processed by rename 2322system.cpu1.rename.ROBFullEvents 263094 # Number of times rename has blocked due to ROB full 2323system.cpu1.rename.IQFullEvents 35438 # Number of times rename has blocked due to IQ full 2324system.cpu1.rename.LQFullEvents 18102 # Number of times rename has blocked due to LQ full 2325system.cpu1.rename.SQFullEvents 1431236 # Number of times rename has blocked due to SQ full 2326system.cpu1.rename.RenamedOperands 55002903 # Number of destination operands rename has renamed 2327system.cpu1.rename.RenameLookups 260522537 # Number of register rename lookups that rename has made 2328system.cpu1.rename.int_rename_lookups 58680311 # Number of integer rename lookups | 1551system.cpu1.fetch.rateDist::total 104278525 # Number of instructions fetched each cycle (Total) 1552system.cpu1.fetch.branchRate 0.324130 # Number of branch fetches per cycle 1553system.cpu1.fetch.rate 1.043449 # Number of inst fetches per cycle 1554system.cpu1.decode.IdleCycles 13017622 # Number of cycles decode is idle 1555system.cpu1.decode.BlockedCycles 61671390 # Number of cycles decode is blocked 1556system.cpu1.decode.RunCycles 26724772 # Number of cycles decode is running 1557system.cpu1.decode.UnblockCycles 1111637 # Number of cycles decode is unblocking 1558system.cpu1.decode.SquashCycles 1753104 # Number of cycles decode is squashing 1559system.cpu1.decode.BranchResolved 754173 # Number of times decode resolved a branch 1560system.cpu1.decode.BranchMispred 137598 # Number of times decode detected a branch misprediction 1561system.cpu1.decode.DecodedInsts 68061604 # Number of instructions handled by decode 1562system.cpu1.decode.SquashedInsts 1168958 # Number of squashed instructions handled by decode 1563system.cpu1.rename.SquashCycles 1753104 # Number of cycles rename is squashing 1564system.cpu1.rename.IdleCycles 17450100 # Number of cycles rename is idle 1565system.cpu1.rename.BlockCycles 2254257 # Number of cycles rename is blocking 1566system.cpu1.rename.serializeStallCycles 56981217 # count of cycles rename stalled for serializing inst 1567system.cpu1.rename.RunCycles 23380222 # Number of cycles rename is running 1568system.cpu1.rename.UnblockCycles 2459625 # Number of cycles rename is unblocking 1569system.cpu1.rename.RenamedInsts 55156752 # Number of instructions processed by rename 1570system.cpu1.rename.SquashedInsts 230613 # Number of squashed instructions processed by rename 1571system.cpu1.rename.ROBFullEvents 263389 # Number of times rename has blocked due to ROB full 1572system.cpu1.rename.IQFullEvents 35416 # Number of times rename has blocked due to IQ full 1573system.cpu1.rename.LQFullEvents 18082 # Number of times rename has blocked due to LQ full 1574system.cpu1.rename.SQFullEvents 1432431 # Number of times rename has blocked due to SQ full 1575system.cpu1.rename.RenamedOperands 55002738 # Number of destination operands rename has renamed 1576system.cpu1.rename.RenameLookups 260522478 # Number of register rename lookups that rename has made 1577system.cpu1.rename.int_rename_lookups 58680214 # Number of integer rename lookups |
| 2329system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups | 1578system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups |
| 2330system.cpu1.rename.CommittedMaps 52222762 # Number of HB maps that are committed 2331system.cpu1.rename.UndoneMaps 2780141 # Number of HB maps that are undone due to squashing 2332system.cpu1.rename.serializingInsts 1878015 # count of serializing insts renamed | 1579system.cpu1.rename.CommittedMaps 52222609 # Number of HB maps that are committed 1580system.cpu1.rename.UndoneMaps 2780129 # Number of HB maps that are undone due to squashing 1581system.cpu1.rename.serializingInsts 1878054 # count of serializing insts renamed |
| 2333system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed | 1582system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed |
| 2334system.cpu1.rename.skidInsts 13100914 # count of insts added to the skid buffer 2335system.cpu1.memDep0.insertedLoads 10457203 # Number of loads inserted to the mem dependence unit. 2336system.cpu1.memDep0.insertedStores 6914095 # Number of stores inserted to the mem dependence unit. 2337system.cpu1.memDep0.conflictingLoads 629486 # Number of conflicting loads. 2338system.cpu1.memDep0.conflictingStores 832023 # Number of conflicting stores. 2339system.cpu1.iq.iqInstsAdded 54264845 # Number of instructions added to the IQ (excludes non-spec) 2340system.cpu1.iq.iqNonSpecInstsAdded 589076 # Number of non-speculative instructions added to the IQ 2341system.cpu1.iq.iqInstsIssued 53908335 # Number of instructions issued 2342system.cpu1.iq.iqSquashedInstsIssued 111707 # Number of squashed instructions issued 2343system.cpu1.iq.iqSquashedInstsExamined 2293120 # Number of squashed instructions iterated over during squash; mainly for profiling 2344system.cpu1.iq.iqSquashedOperandsExamined 5811368 # Number of squashed operands that are examined and possibly removed from graph 2345system.cpu1.iq.iqSquashedNonSpecRemoved 48776 # Number of squashed non-spec instructions that were removed 2346system.cpu1.iq.issued_per_cycle::samples 104272698 # Number of insts issued each cycle 2347system.cpu1.iq.issued_per_cycle::mean 0.516994 # Number of insts issued each cycle 2348system.cpu1.iq.issued_per_cycle::stdev 0.852584 # Number of insts issued each cycle | 1583system.cpu1.rename.skidInsts 13101359 # count of insts added to the skid buffer 1584system.cpu1.memDep0.insertedLoads 10457131 # Number of loads inserted to the mem dependence unit. 1585system.cpu1.memDep0.insertedStores 6914141 # Number of stores inserted to the mem dependence unit. 1586system.cpu1.memDep0.conflictingLoads 629237 # Number of conflicting loads. 1587system.cpu1.memDep0.conflictingStores 831086 # Number of conflicting stores. 1588system.cpu1.iq.iqInstsAdded 54264809 # Number of instructions added to the IQ (excludes non-spec) 1589system.cpu1.iq.iqNonSpecInstsAdded 589071 # Number of non-speculative instructions added to the IQ 1590system.cpu1.iq.iqInstsIssued 53908897 # Number of instructions issued 1591system.cpu1.iq.iqSquashedInstsIssued 111732 # Number of squashed instructions issued 1592system.cpu1.iq.iqSquashedInstsExamined 2292977 # Number of squashed instructions iterated over during squash; mainly for profiling 1593system.cpu1.iq.iqSquashedOperandsExamined 5809537 # Number of squashed operands that are examined and possibly removed from graph 1594system.cpu1.iq.iqSquashedNonSpecRemoved 48790 # Number of squashed non-spec instructions that were removed 1595system.cpu1.iq.issued_per_cycle::samples 104278525 # Number of insts issued each cycle 1596system.cpu1.iq.issued_per_cycle::mean 0.516970 # Number of insts issued each cycle 1597system.cpu1.iq.issued_per_cycle::stdev 0.852578 # Number of insts issued each cycle |
| 2349system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1598system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 2350system.cpu1.iq.issued_per_cycle::0 71021448 68.11% 68.11% # Number of insts issued each cycle 2351system.cpu1.iq.issued_per_cycle::1 16528398 15.85% 83.96% # Number of insts issued each cycle 2352system.cpu1.iq.issued_per_cycle::2 13076148 12.54% 96.50% # Number of insts issued each cycle 2353system.cpu1.iq.issued_per_cycle::3 3359187 3.22% 99.72% # Number of insts issued each cycle 2354system.cpu1.iq.issued_per_cycle::4 287505 0.28% 100.00% # Number of insts issued each cycle | 1599system.cpu1.iq.issued_per_cycle::0 71027306 68.11% 68.11% # Number of insts issued each cycle 1600system.cpu1.iq.issued_per_cycle::1 16528003 15.85% 83.96% # Number of insts issued each cycle 1601system.cpu1.iq.issued_per_cycle::2 13076309 12.54% 96.50% # Number of insts issued each cycle 1602system.cpu1.iq.issued_per_cycle::3 3359364 3.22% 99.72% # Number of insts issued each cycle 1603system.cpu1.iq.issued_per_cycle::4 287531 0.28% 100.00% # Number of insts issued each cycle |
| 2355system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle 2356system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2357system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2358system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2359system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2360system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2361system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1604system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle 1605system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1606system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1607system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1608system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1609system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1610system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 2362system.cpu1.iq.issued_per_cycle::total 104272698 # Number of insts issued each cycle | 1611system.cpu1.iq.issued_per_cycle::total 104278525 # Number of insts issued each cycle |
| 2363system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1612system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 2364system.cpu1.iq.fu_full::IntAlu 2925111 45.11% 45.11% # attempts to use FU when none available 2365system.cpu1.iq.fu_full::IntMult 678 0.01% 45.12% # attempts to use FU when none available 2366system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.12% # attempts to use FU when none available 2367system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.12% # attempts to use FU when none available 2368system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.12% # attempts to use FU when none available 2369system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.12% # attempts to use FU when none available 2370system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.12% # attempts to use FU when none available 2371system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.12% # attempts to use FU when none available 2372system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.12% # attempts to use FU when none available 2373system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.12% # attempts to use FU when none available 2374system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.12% # attempts to use FU when none available 2375system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.12% # attempts to use FU when none available 2376system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.12% # attempts to use FU when none available 2377system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.12% # attempts to use FU when none available 2378system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.12% # attempts to use FU when none available 2379system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.12% # attempts to use FU when none available 2380system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.12% # attempts to use FU when none available 2381system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.12% # attempts to use FU when none available 2382system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.12% # attempts to use FU when none available 2383system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.12% # attempts to use FU when none available 2384system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.12% # attempts to use FU when none available 2385system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.12% # attempts to use FU when none available 2386system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.12% # attempts to use FU when none available 2387system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.12% # attempts to use FU when none available 2388system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.12% # attempts to use FU when none available 2389system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.12% # attempts to use FU when none available 2390system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.12% # attempts to use FU when none available 2391system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.12% # attempts to use FU when none available 2392system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.12% # attempts to use FU when none available 2393system.cpu1.iq.fu_full::MemRead 1673253 25.80% 70.93% # attempts to use FU when none available 2394system.cpu1.iq.fu_full::MemWrite 1885198 29.07% 100.00% # attempts to use FU when none available | 1613system.cpu1.iq.fu_full::IntAlu 2925381 45.12% 45.12% # attempts to use FU when none available 1614system.cpu1.iq.fu_full::IntMult 677 0.01% 45.13% # attempts to use FU when none available 1615system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.13% # attempts to use FU when none available 1616system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.13% # attempts to use FU when none available 1617system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.13% # attempts to use FU when none available 1618system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.13% # attempts to use FU when none available 1619system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.13% # attempts to use FU when none available 1620system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.13% # attempts to use FU when none available 1621system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.13% # attempts to use FU when none available 1622system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.13% # attempts to use FU when none available 1623system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.13% # attempts to use FU when none available 1624system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.13% # attempts to use FU when none available 1625system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.13% # attempts to use FU when none available 1626system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.13% # attempts to use FU when none available 1627system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.13% # attempts to use FU when none available 1628system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.13% # attempts to use FU when none available 1629system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.13% # attempts to use FU when none available 1630system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.13% # attempts to use FU when none available 1631system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.13% # attempts to use FU when none available 1632system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.13% # attempts to use FU when none available 1633system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.13% # attempts to use FU when none available 1634system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.13% # attempts to use FU when none available 1635system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.13% # attempts to use FU when none available 1636system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.13% # attempts to use FU when none available 1637system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.13% # attempts to use FU when none available 1638system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.13% # attempts to use FU when none available 1639system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.13% # attempts to use FU when none available 1640system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.13% # attempts to use FU when none available 1641system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.13% # attempts to use FU when none available 1642system.cpu1.iq.fu_full::MemRead 1673591 25.81% 70.94% # attempts to use FU when none available 1643system.cpu1.iq.fu_full::MemWrite 1884116 29.06% 100.00% # attempts to use FU when none available |
| 2395system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2396system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2397system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued | 1644system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1645system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1646system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued |
| 2398system.cpu1.iq.FU_type_0::IntAlu 36727070 68.13% 68.13% # Type of FU issued 2399system.cpu1.iq.FU_type_0::IntMult 46542 0.09% 68.22% # Type of FU issued 2400system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued 2401system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued 2402system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued 2403system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued 2404system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued 2405system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued 2406system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued 2407system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued 2408system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued 2409system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued 2410system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued 2411system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued 2412system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.22% # Type of FU issued 2413system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued 2414system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued 2415system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.22% # Type of FU issued 2416system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued 2417system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued 2418system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued 2419system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued 2420system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued 2421system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued 2422system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued | 1647system.cpu1.iq.FU_type_0::IntAlu 36727260 68.13% 68.13% # Type of FU issued 1648system.cpu1.iq.FU_type_0::IntMult 46535 0.09% 68.21% # Type of FU issued 1649system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued 1650system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued 1651system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued 1652system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued 1653system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued 1654system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued 1655system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued 1656system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued 1657system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued 1658system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued 1659system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued 1660system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued 1661system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued 1662system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued 1663system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued 1664system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued 1665system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued 1666system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued 1667system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued 1668system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued 1669system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued 1670system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued 1671system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued |
| 2423system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued 2424system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 2425system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 2426system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued | 1672system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued 1673system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 1674system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 1675system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued |
| 2427system.cpu1.iq.FU_type_0::MemRead 10379930 19.25% 87.48% # Type of FU issued 2428system.cpu1.iq.FU_type_0::MemWrite 6751385 12.52% 100.00% # Type of FU issued | 1676system.cpu1.iq.FU_type_0::MemRead 10380151 19.25% 87.48% # Type of FU issued 1677system.cpu1.iq.FU_type_0::MemWrite 6751543 12.52% 100.00% # Type of FU issued |
| 2429system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2430system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1678system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1679system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2431system.cpu1.iq.FU_type_0::total 53908335 # Type of FU issued 2432system.cpu1.iq.rate 0.515306 # Inst issue rate 2433system.cpu1.iq.fu_busy_cnt 6484240 # FU busy when requested 2434system.cpu1.iq.fu_busy_rate 0.120283 # FU busy rate (busy events/executed inst) 2435system.cpu1.iq.int_inst_queue_reads 218679535 # Number of integer instruction queue reads 2436system.cpu1.iq.int_inst_queue_writes 57155155 # Number of integer instruction queue writes 2437system.cpu1.iq.int_inst_queue_wakeup_accesses 51920155 # Number of integer instruction queue wakeup accesses 2438system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads | 1680system.cpu1.iq.FU_type_0::total 53908897 # Type of FU issued 1681system.cpu1.iq.rate 0.515271 # Inst issue rate 1682system.cpu1.iq.fu_busy_cnt 6483765 # FU busy when requested 1683system.cpu1.iq.fu_busy_rate 0.120273 # FU busy rate (busy events/executed inst) 1684system.cpu1.iq.int_inst_queue_reads 218686026 # Number of integer instruction queue reads 1685system.cpu1.iq.int_inst_queue_writes 57154966 # Number of integer instruction queue writes 1686system.cpu1.iq.int_inst_queue_wakeup_accesses 51920427 # Number of integer instruction queue wakeup accesses 1687system.cpu1.iq.fp_inst_queue_reads 5790 # Number of floating instruction queue reads |
| 2439system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes 2440system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses | 1688system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes 1689system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses |
| 2441system.cpu1.iq.int_alu_accesses 60388817 # Number of integer alu accesses 2442system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses 2443system.cpu1.iew.lsq.thread0.forwLoads 91403 # Number of loads that had data forwarded from stores | 1690system.cpu1.iq.int_alu_accesses 60388895 # Number of integer alu accesses 1691system.cpu1.iq.fp_alu_accesses 3701 # Number of floating point alu accesses 1692system.cpu1.iew.lsq.thread0.forwLoads 91393 # Number of loads that had data forwarded from stores |
| 2444system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1693system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2445system.cpu1.iew.lsq.thread0.squashedLoads 490692 # Number of loads squashed | 1694system.cpu1.iew.lsq.thread0.squashedLoads 490676 # Number of loads squashed |
| 2446system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed | 1695system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed |
| 2447system.cpu1.iew.lsq.thread0.memOrderViolation 10198 # Number of memory ordering violations 2448system.cpu1.iew.lsq.thread0.squashedStores 355978 # Number of stores squashed | 1696system.cpu1.iew.lsq.thread0.memOrderViolation 10193 # Number of memory ordering violations 1697system.cpu1.iew.lsq.thread0.squashedStores 356081 # Number of stores squashed |
| 2449system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2450system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1698system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1699system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2451system.cpu1.iew.lsq.thread0.rescheduledLoads 51963 # Number of loads that were rescheduled 2452system.cpu1.iew.lsq.thread0.cacheBlocked 70332 # Number of times an access to memory failed due to the cache being blocked | 1700system.cpu1.iew.lsq.thread0.rescheduledLoads 51970 # Number of loads that were rescheduled 1701system.cpu1.iew.lsq.thread0.cacheBlocked 70495 # Number of times an access to memory failed due to the cache being blocked |
| 2453system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1702system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2454system.cpu1.iew.iewSquashCycles 1753061 # Number of cycles IEW is squashing 2455system.cpu1.iew.iewBlockCycles 546569 # Number of cycles IEW is blocking 2456system.cpu1.iew.iewUnblockCycles 114085 # Number of cycles IEW is unblocking 2457system.cpu1.iew.iewDispatchedInsts 54906076 # Number of instructions dispatched to IQ | 1703system.cpu1.iew.iewSquashCycles 1753104 # Number of cycles IEW is squashing 1704system.cpu1.iew.iewBlockCycles 548003 # Number of cycles IEW is blocking 1705system.cpu1.iew.iewUnblockCycles 114295 # Number of cycles IEW is unblocking 1706system.cpu1.iew.iewDispatchedInsts 54906042 # Number of instructions dispatched to IQ |
| 2458system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 1707system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 2459system.cpu1.iew.iewDispLoadInsts 10457203 # Number of dispatched load instructions 2460system.cpu1.iew.iewDispStoreInsts 6914095 # Number of dispatched store instructions 2461system.cpu1.iew.iewDispNonSpecInsts 301562 # Number of dispatched non-speculative instructions 2462system.cpu1.iew.iewIQFullEvents 9838 # Number of times the IQ has become full, causing a stall 2463system.cpu1.iew.iewLSQFullEvents 96727 # Number of times the LSQ has become full, causing a stall 2464system.cpu1.iew.memOrderViolationEvents 10198 # Number of memory order violations 2465system.cpu1.iew.predictedTakenIncorrect 54956 # Number of branches that were predicted taken incorrectly 2466system.cpu1.iew.predictedNotTakenIncorrect 127310 # Number of branches that were predicted not taken incorrectly 2467system.cpu1.iew.branchMispredicts 182266 # Number of branch mispredicts detected at execute 2468system.cpu1.iew.iewExecutedInsts 53638370 # Number of executed instructions 2469system.cpu1.iew.iewExecLoadInsts 10277968 # Number of load instructions executed 2470system.cpu1.iew.iewExecSquashedInsts 248350 # Number of squashed instructions skipped in execute | 1708system.cpu1.iew.iewDispLoadInsts 10457131 # Number of dispatched load instructions 1709system.cpu1.iew.iewDispStoreInsts 6914141 # Number of dispatched store instructions 1710system.cpu1.iew.iewDispNonSpecInsts 301584 # Number of dispatched non-speculative instructions 1711system.cpu1.iew.iewIQFullEvents 9824 # Number of times the IQ has become full, causing a stall 1712system.cpu1.iew.iewLSQFullEvents 96972 # Number of times the LSQ has become full, causing a stall 1713system.cpu1.iew.memOrderViolationEvents 10193 # Number of memory order violations 1714system.cpu1.iew.predictedTakenIncorrect 54960 # Number of branches that were predicted taken incorrectly 1715system.cpu1.iew.predictedNotTakenIncorrect 127313 # Number of branches that were predicted not taken incorrectly 1716system.cpu1.iew.branchMispredicts 182273 # Number of branch mispredicts detected at execute 1717system.cpu1.iew.iewExecutedInsts 53638837 # Number of executed instructions 1718system.cpu1.iew.iewExecLoadInsts 10278190 # Number of load instructions executed 1719system.cpu1.iew.iewExecSquashedInsts 248481 # Number of squashed instructions skipped in execute |
| 2471system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1720system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2472system.cpu1.iew.exec_nop 52155 # number of nop insts executed 2473system.cpu1.iew.exec_refs 16965083 # number of memory reference insts executed 2474system.cpu1.iew.exec_branches 11807834 # Number of branches executed 2475system.cpu1.iew.exec_stores 6687115 # Number of stores executed 2476system.cpu1.iew.exec_rate 0.512725 # Inst execution rate 2477system.cpu1.iew.wb_sent 53497576 # cumulative count of insts sent to commit 2478system.cpu1.iew.wb_count 51921941 # cumulative count of insts written-back 2479system.cpu1.iew.wb_producers 25229731 # num instructions producing a value 2480system.cpu1.iew.wb_consumers 38490253 # num instructions consuming a value | 1721system.cpu1.iew.exec_nop 52162 # number of nop insts executed 1722system.cpu1.iew.exec_refs 16965416 # number of memory reference insts executed 1723system.cpu1.iew.exec_branches 11807917 # Number of branches executed 1724system.cpu1.iew.exec_stores 6687226 # Number of stores executed 1725system.cpu1.iew.exec_rate 0.512690 # Inst execution rate 1726system.cpu1.iew.wb_sent 53497875 # cumulative count of insts sent to commit 1727system.cpu1.iew.wb_count 51922213 # cumulative count of insts written-back 1728system.cpu1.iew.wb_producers 25229776 # num instructions producing a value 1729system.cpu1.iew.wb_consumers 38490454 # num instructions consuming a value |
| 2481system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1730system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2482system.cpu1.iew.wb_rate 0.496318 # insts written-back per cycle 2483system.cpu1.iew.wb_fanout 0.655484 # average fanout of values written-back | 1731system.cpu1.iew.wb_rate 0.496282 # insts written-back per cycle 1732system.cpu1.iew.wb_fanout 0.655481 # average fanout of values written-back |
| 2484system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1733system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2485system.cpu1.commit.commitSquashedInsts 3658728 # The number of squashed insts skipped by commit 2486system.cpu1.commit.commitNonSpecStalls 540300 # The number of times commit has been forced to stall to communicate backwards 2487system.cpu1.commit.branchMispredicts 170382 # The number of times a branch was mispredicted 2488system.cpu1.commit.committed_per_cycle::samples 102340769 # Number of insts commited each cycle 2489system.cpu1.commit.committed_per_cycle::mean 0.498127 # Number of insts commited each cycle 2490system.cpu1.commit.committed_per_cycle::stdev 1.159192 # Number of insts commited each cycle | 1734system.cpu1.commit.commitSquashedInsts 3658692 # The number of squashed insts skipped by commit 1735system.cpu1.commit.commitNonSpecStalls 540281 # The number of times commit has been forced to stall to communicate backwards 1736system.cpu1.commit.branchMispredicts 170405 # The number of times a branch was mispredicted 1737system.cpu1.commit.committed_per_cycle::samples 102346479 # Number of insts commited each cycle 1738system.cpu1.commit.committed_per_cycle::mean 0.498098 # Number of insts commited each cycle 1739system.cpu1.commit.committed_per_cycle::stdev 1.159114 # Number of insts commited each cycle |
| 2491system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1740system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2492system.cpu1.commit.committed_per_cycle::0 76762339 75.01% 75.01% # Number of insts commited each cycle 2493system.cpu1.commit.committed_per_cycle::1 14287767 13.96% 88.97% # Number of insts commited each cycle 2494system.cpu1.commit.committed_per_cycle::2 6080575 5.94% 94.91% # Number of insts commited each cycle 2495system.cpu1.commit.committed_per_cycle::3 703802 0.69% 95.60% # Number of insts commited each cycle 2496system.cpu1.commit.committed_per_cycle::4 1980023 1.93% 97.53% # Number of insts commited each cycle 2497system.cpu1.commit.committed_per_cycle::5 1565125 1.53% 99.06% # Number of insts commited each cycle 2498system.cpu1.commit.committed_per_cycle::6 446359 0.44% 99.50% # Number of insts commited each cycle 2499system.cpu1.commit.committed_per_cycle::7 123712 0.12% 99.62% # Number of insts commited each cycle 2500system.cpu1.commit.committed_per_cycle::8 391067 0.38% 100.00% # Number of insts commited each cycle | 1741system.cpu1.commit.committed_per_cycle::0 76767559 75.01% 75.01% # Number of insts commited each cycle 1742system.cpu1.commit.committed_per_cycle::1 14288132 13.96% 88.97% # Number of insts commited each cycle 1743system.cpu1.commit.committed_per_cycle::2 6080244 5.94% 94.91% # Number of insts commited each cycle 1744system.cpu1.commit.committed_per_cycle::3 703970 0.69% 95.60% # Number of insts commited each cycle 1745system.cpu1.commit.committed_per_cycle::4 1980102 1.93% 97.53% # Number of insts commited each cycle 1746system.cpu1.commit.committed_per_cycle::5 1566998 1.53% 99.06% # Number of insts commited each cycle 1747system.cpu1.commit.committed_per_cycle::6 444730 0.43% 99.50% # Number of insts commited each cycle 1748system.cpu1.commit.committed_per_cycle::7 123732 0.12% 99.62% # Number of insts commited each cycle 1749system.cpu1.commit.committed_per_cycle::8 391012 0.38% 100.00% # Number of insts commited each cycle |
| 2501system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2502system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2503system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1750system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1751system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1752system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2504system.cpu1.commit.committed_per_cycle::total 102340769 # Number of insts commited each cycle 2505system.cpu1.commit.committedInsts 41392870 # Number of instructions committed 2506system.cpu1.commit.committedOps 50978714 # Number of ops (including micro ops) committed | 1753system.cpu1.commit.committed_per_cycle::total 102346479 # Number of insts commited each cycle 1754system.cpu1.commit.committedInsts 41392684 # Number of instructions committed 1755system.cpu1.commit.committedOps 50978528 # Number of ops (including micro ops) committed |
| 2507system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1756system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2508system.cpu1.commit.refs 16524628 # Number of memory references committed 2509system.cpu1.commit.loads 9966511 # Number of loads committed 2510system.cpu1.commit.membars 209715 # Number of memory barriers committed 2511system.cpu1.commit.branches 11639820 # Number of branches committed | 1757system.cpu1.commit.refs 16524515 # Number of memory references committed 1758system.cpu1.commit.loads 9966455 # Number of loads committed 1759system.cpu1.commit.membars 209698 # Number of memory barriers committed 1760system.cpu1.commit.branches 11639872 # Number of branches committed |
| 2512system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. | 1761system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. |
| 2513system.cpu1.commit.int_insts 45828641 # Number of committed integer instructions. 2514system.cpu1.commit.function_calls 3366594 # Number of function calls committed. | 1762system.cpu1.commit.int_insts 45828467 # Number of committed integer instructions. 1763system.cpu1.commit.function_calls 3366626 # Number of function calls committed. |
| 2515system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 1764system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 2516system.cpu1.commit.op_class_0::IntAlu 34405110 67.49% 67.49% # Class of committed instruction 2517system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction | 1765system.cpu1.commit.op_class_0::IntAlu 34405041 67.49% 67.49% # Class of committed instruction 1766system.cpu1.commit.op_class_0::IntMult 45633 0.09% 67.58% # Class of committed instruction |
| 2518system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction 2519system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction 2520system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction 2521system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction 2522system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction 2523system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction 2524system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction 2525system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 2537system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction 2538system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction 2539system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction 2540system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction 2541system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction 2542system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction 2543system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction 2544system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction | 1767system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction 1768system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction 1769system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction 1770system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction 1771system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction 1772system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction 1773system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction 1774system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 1786system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction 1787system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction 1788system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction 1789system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction 1790system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction 1791system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction 1792system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction 1793system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction |
| 2545system.cpu1.commit.op_class_0::MemRead 9966511 19.55% 87.14% # Class of committed instruction 2546system.cpu1.commit.op_class_0::MemWrite 6558117 12.86% 100.00% # Class of committed instruction | 1794system.cpu1.commit.op_class_0::MemRead 9966455 19.55% 87.14% # Class of committed instruction 1795system.cpu1.commit.op_class_0::MemWrite 6558060 12.86% 100.00% # Class of committed instruction |
| 2547system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2548system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1796system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1797system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2549system.cpu1.commit.op_class_0::total 50978714 # Class of committed instruction 2550system.cpu1.commit.bw_lim_events 391067 # number cycles where commit BW limit reached | 1798system.cpu1.commit.op_class_0::total 50978528 # Class of committed instruction 1799system.cpu1.commit.bw_lim_events 391012 # number cycles where commit BW limit reached |
| 2551system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1800system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2552system.cpu1.rob.rob_reads 136550879 # The number of ROB reads 2553system.cpu1.rob.rob_writes 111203214 # The number of ROB writes 2554system.cpu1.timesIdled 53373 # Number of times that the entire CPU went into an idle state and unscheduled itself 2555system.cpu1.idleCycles 341555 # Total number of cycles that the CPU has spent unscheduled due to idling 2556system.cpu1.quiesceCycles 5543525682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2557system.cpu1.committedInsts 41360016 # Number of Instructions Simulated 2558system.cpu1.committedOps 50945860 # Number of Ops (including micro ops) Simulated 2559system.cpu1.cpi 2.529357 # CPI: Cycles Per Instruction 2560system.cpu1.cpi_total 2.529357 # CPI: Total CPI of All Threads 2561system.cpu1.ipc 0.395357 # IPC: Instructions Per Cycle 2562system.cpu1.ipc_total 0.395357 # IPC: Total IPC of All Threads 2563system.cpu1.int_regfile_reads 56284604 # number of integer regfile reads 2564system.cpu1.int_regfile_writes 35740768 # number of integer regfile writes | 1801system.cpu1.rob.rob_reads 136555973 # The number of ROB reads 1802system.cpu1.rob.rob_writes 111202855 # The number of ROB writes 1803system.cpu1.timesIdled 53415 # Number of times that the entire CPU went into an idle state and unscheduled itself 1804system.cpu1.idleCycles 343799 # Total number of cycles that the CPU has spent unscheduled due to idling 1805system.cpu1.quiesceCycles 5543567058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1806system.cpu1.committedInsts 41359830 # Number of Instructions Simulated 1807system.cpu1.committedOps 50945674 # Number of Ops (including micro ops) Simulated 1808system.cpu1.cpi 2.529564 # CPI: Cycles Per Instruction 1809system.cpu1.cpi_total 2.529564 # CPI: Total CPI of All Threads 1810system.cpu1.ipc 0.395325 # IPC: Instructions Per Cycle 1811system.cpu1.ipc_total 0.395325 # IPC: Total IPC of All Threads 1812system.cpu1.int_regfile_reads 56285102 # number of integer regfile reads 1813system.cpu1.int_regfile_writes 35740910 # number of integer regfile writes |
| 2565system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads 2566system.cpu1.fp_regfile_writes 520 # number of floating regfile writes | 1814system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads 1815system.cpu1.fp_regfile_writes 520 # number of floating regfile writes |
| 2567system.cpu1.cc_regfile_reads 191160889 # number of cc regfile reads 2568system.cpu1.cc_regfile_writes 15560745 # number of cc regfile writes 2569system.cpu1.misc_regfile_reads 205861724 # number of misc regfile reads 2570system.cpu1.misc_regfile_writes 388836 # number of misc regfile writes 2571system.cpu1.toL2Bus.trans_dist::ReadReq 1295167 # Transaction distribution 2572system.cpu1.toL2Bus.trans_dist::ReadResp 865146 # Transaction distribution 2573system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution 2574system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution 2575system.cpu1.toL2Bus.trans_dist::Writeback 117435 # Transaction distribution 2576system.cpu1.toL2Bus.trans_dist::HardPFReq 157667 # Transaction distribution 2577system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution 2578system.cpu1.toL2Bus.trans_dist::UpgradeReq 84819 # Transaction distribution 2579system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41863 # Transaction distribution 2580system.cpu1.toL2Bus.trans_dist::UpgradeResp 87089 # Transaction distribution 2581system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2582system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 2583system.cpu1.toL2Bus.trans_dist::ReadExReq 79490 # Transaction distribution 2584system.cpu1.toL2Bus.trans_dist::ReadExResp 66369 # Transaction distribution 2585system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215695 # Packet count per connected master and slave (bytes) 2586system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 824924 # Packet count per connected master and slave (bytes) 2587system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17344 # Packet count per connected master and slave (bytes) 2588system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37959 # Packet count per connected master and slave (bytes) 2589system.cpu1.toL2Bus.pkt_count::total 2095922 # Packet count per connected master and slave (bytes) 2590system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897296 # Cumulative packet size per connected master and slave (bytes) 2591system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25431436 # Cumulative packet size per connected master and slave (bytes) 2592system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30740 # Cumulative packet size per connected master and slave (bytes) 2593system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67228 # Cumulative packet size per connected master and slave (bytes) 2594system.cpu1.toL2Bus.pkt_size::total 64426700 # Cumulative packet size per connected master and slave (bytes) 2595system.cpu1.toL2Bus.snoops 835314 # Total snoops (count) 2596system.cpu1.toL2Bus.snoop_fanout::samples 1798151 # Request fanout histogram 2597system.cpu1.toL2Bus.snoop_fanout::mean 5.418656 # Request fanout histogram 2598system.cpu1.toL2Bus.snoop_fanout::stdev 0.493339 # Request fanout histogram 2599system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2600system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2601system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2602system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2603system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2604system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2605system.cpu1.toL2Bus.snoop_fanout::5 1045344 58.13% 58.13% # Request fanout histogram 2606system.cpu1.toL2Bus.snoop_fanout::6 752807 41.87% 100.00% # Request fanout histogram 2607system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2608system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2609system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2610system.cpu1.toL2Bus.snoop_fanout::total 1798151 # Request fanout histogram 2611system.cpu1.toL2Bus.reqLayer0.occupancy 659597923 # Layer occupancy (ticks) 2612system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2613system.cpu1.toL2Bus.snoopLayer0.occupancy 81215248 # Layer occupancy (ticks) 2614system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2615system.cpu1.toL2Bus.respLayer0.occupancy 913005612 # Layer occupancy (ticks) 2616system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2617system.cpu1.toL2Bus.respLayer1.occupancy 403790804 # Layer occupancy (ticks) 2618system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2619system.cpu1.toL2Bus.respLayer2.occupancy 9801715 # Layer occupancy (ticks) 2620system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2621system.cpu1.toL2Bus.respLayer3.occupancy 21218619 # Layer occupancy (ticks) 2622system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2623system.cpu1.icache.tags.replacements 607233 # number of replacements 2624system.cpu1.icache.tags.tagsinuse 499.524677 # Cycle average of tags in use 2625system.cpu1.icache.tags.total_refs 43016935 # Total number of references to valid blocks. 2626system.cpu1.icache.tags.sampled_refs 607745 # Sample count of references to valid blocks. 2627system.cpu1.icache.tags.avg_refs 70.781224 # Average number of references to valid blocks. | 1816system.cpu1.cc_regfile_reads 191162273 # number of cc regfile reads 1817system.cpu1.cc_regfile_writes 15560809 # number of cc regfile writes 1818system.cpu1.misc_regfile_reads 205875636 # number of misc regfile reads 1819system.cpu1.misc_regfile_writes 388862 # number of misc regfile writes 1820system.cpu1.dcache.tags.replacements 191071 # number of replacements 1821system.cpu1.dcache.tags.tagsinuse 472.558495 # Cycle average of tags in use 1822system.cpu1.dcache.tags.total_refs 15741437 # Total number of references to valid blocks. 1823system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. 1824system.cpu1.dcache.tags.avg_refs 82.245811 # Average number of references to valid blocks. 1825system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. 1826system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558495 # Average occupied blocks per requestor 1827system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy 1828system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy 1829system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id 1830system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 1831system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1832system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id 1833system.cpu1.dcache.tags.tag_accesses 32983767 # Number of tag accesses 1834system.cpu1.dcache.tags.data_accesses 32983767 # Number of data accesses 1835system.cpu1.dcache.ReadReq_hits::cpu1.data 9574609 # number of ReadReq hits 1836system.cpu1.dcache.ReadReq_hits::total 9574609 # number of ReadReq hits 1837system.cpu1.dcache.WriteReq_hits::cpu1.data 5910607 # number of WriteReq hits 1838system.cpu1.dcache.WriteReq_hits::total 5910607 # number of WriteReq hits 1839system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49573 # number of SoftPFReq hits 1840system.cpu1.dcache.SoftPFReq_hits::total 49573 # number of SoftPFReq hits 1841system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79145 # number of LoadLockedReq hits 1842system.cpu1.dcache.LoadLockedReq_hits::total 79145 # number of LoadLockedReq hits 1843system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71001 # number of StoreCondReq hits 1844system.cpu1.dcache.StoreCondReq_hits::total 71001 # number of StoreCondReq hits 1845system.cpu1.dcache.demand_hits::cpu1.data 15485216 # number of demand (read+write) hits 1846system.cpu1.dcache.demand_hits::total 15485216 # number of demand (read+write) hits 1847system.cpu1.dcache.overall_hits::cpu1.data 15534789 # number of overall hits 1848system.cpu1.dcache.overall_hits::total 15534789 # number of overall hits 1849system.cpu1.dcache.ReadReq_misses::cpu1.data 219415 # number of ReadReq misses 1850system.cpu1.dcache.ReadReq_misses::total 219415 # number of ReadReq misses 1851system.cpu1.dcache.WriteReq_misses::cpu1.data 398307 # number of WriteReq misses 1852system.cpu1.dcache.WriteReq_misses::total 398307 # number of WriteReq misses 1853system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30093 # number of SoftPFReq misses 1854system.cpu1.dcache.SoftPFReq_misses::total 30093 # number of SoftPFReq misses 1855system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18121 # number of LoadLockedReq misses 1856system.cpu1.dcache.LoadLockedReq_misses::total 18121 # number of LoadLockedReq misses 1857system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23394 # number of StoreCondReq misses 1858system.cpu1.dcache.StoreCondReq_misses::total 23394 # number of StoreCondReq misses 1859system.cpu1.dcache.demand_misses::cpu1.data 617722 # number of demand (read+write) misses 1860system.cpu1.dcache.demand_misses::total 617722 # number of demand (read+write) misses 1861system.cpu1.dcache.overall_misses::cpu1.data 647815 # number of overall misses 1862system.cpu1.dcache.overall_misses::total 647815 # number of overall misses 1863system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3455998019 # number of ReadReq miss cycles 1864system.cpu1.dcache.ReadReq_miss_latency::total 3455998019 # number of ReadReq miss cycles 1865system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8728631208 # number of WriteReq miss cycles 1866system.cpu1.dcache.WriteReq_miss_latency::total 8728631208 # number of WriteReq miss cycles 1867system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363006249 # number of LoadLockedReq miss cycles 1868system.cpu1.dcache.LoadLockedReq_miss_latency::total 363006249 # number of LoadLockedReq miss cycles 1869system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542688316 # number of StoreCondReq miss cycles 1870system.cpu1.dcache.StoreCondReq_miss_latency::total 542688316 # number of StoreCondReq miss cycles 1871system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 504500 # number of StoreCondFailReq miss cycles 1872system.cpu1.dcache.StoreCondFailReq_miss_latency::total 504500 # number of StoreCondFailReq miss cycles 1873system.cpu1.dcache.demand_miss_latency::cpu1.data 12184629227 # number of demand (read+write) miss cycles 1874system.cpu1.dcache.demand_miss_latency::total 12184629227 # number of demand (read+write) miss cycles 1875system.cpu1.dcache.overall_miss_latency::cpu1.data 12184629227 # number of overall miss cycles 1876system.cpu1.dcache.overall_miss_latency::total 12184629227 # number of overall miss cycles 1877system.cpu1.dcache.ReadReq_accesses::cpu1.data 9794024 # number of ReadReq accesses(hits+misses) 1878system.cpu1.dcache.ReadReq_accesses::total 9794024 # number of ReadReq accesses(hits+misses) 1879system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308914 # number of WriteReq accesses(hits+misses) 1880system.cpu1.dcache.WriteReq_accesses::total 6308914 # number of WriteReq accesses(hits+misses) 1881system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79666 # number of SoftPFReq accesses(hits+misses) 1882system.cpu1.dcache.SoftPFReq_accesses::total 79666 # number of SoftPFReq accesses(hits+misses) 1883system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97266 # number of LoadLockedReq accesses(hits+misses) 1884system.cpu1.dcache.LoadLockedReq_accesses::total 97266 # number of LoadLockedReq accesses(hits+misses) 1885system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94395 # number of StoreCondReq accesses(hits+misses) 1886system.cpu1.dcache.StoreCondReq_accesses::total 94395 # number of StoreCondReq accesses(hits+misses) 1887system.cpu1.dcache.demand_accesses::cpu1.data 16102938 # number of demand (read+write) accesses 1888system.cpu1.dcache.demand_accesses::total 16102938 # number of demand (read+write) accesses 1889system.cpu1.dcache.overall_accesses::cpu1.data 16182604 # number of overall (read+write) accesses 1890system.cpu1.dcache.overall_accesses::total 16182604 # number of overall (read+write) accesses 1891system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022403 # miss rate for ReadReq accesses 1892system.cpu1.dcache.ReadReq_miss_rate::total 0.022403 # miss rate for ReadReq accesses 1893system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063134 # miss rate for WriteReq accesses 1894system.cpu1.dcache.WriteReq_miss_rate::total 0.063134 # miss rate for WriteReq accesses 1895system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377740 # miss rate for SoftPFReq accesses 1896system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377740 # miss rate for SoftPFReq accesses 1897system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186304 # miss rate for LoadLockedReq accesses 1898system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186304 # miss rate for LoadLockedReq accesses 1899system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247831 # miss rate for StoreCondReq accesses 1900system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247831 # miss rate for StoreCondReq accesses 1901system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038361 # miss rate for demand accesses 1902system.cpu1.dcache.demand_miss_rate::total 0.038361 # miss rate for demand accesses 1903system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040032 # miss rate for overall accesses 1904system.cpu1.dcache.overall_miss_rate::total 0.040032 # miss rate for overall accesses 1905system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15750.965153 # average ReadReq miss latency 1906system.cpu1.dcache.ReadReq_avg_miss_latency::total 15750.965153 # average ReadReq miss latency 1907system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21914.330424 # average WriteReq miss latency 1908system.cpu1.dcache.WriteReq_avg_miss_latency::total 21914.330424 # average WriteReq miss latency 1909system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20032.351912 # average LoadLockedReq miss latency 1910system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20032.351912 # average LoadLockedReq miss latency 1911system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23197.756519 # average StoreCondReq miss latency 1912system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23197.756519 # average StoreCondReq miss latency 1913system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1914system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1915system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19725.101627 # average overall miss latency 1916system.cpu1.dcache.demand_avg_miss_latency::total 19725.101627 # average overall miss latency 1917system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18808.809964 # average overall miss latency 1918system.cpu1.dcache.overall_avg_miss_latency::total 18808.809964 # average overall miss latency 1919system.cpu1.dcache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked 1920system.cpu1.dcache.blocked_cycles::no_targets 1112453 # number of cycles access was blocked 1921system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked 1922system.cpu1.dcache.blocked::no_targets 39616 # number of cycles access was blocked 1923system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.648649 # average number of cycles each access was blocked 1924system.cpu1.dcache.avg_blocked_cycles::no_targets 28.080902 # average number of cycles each access was blocked 1925system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1926system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1927system.cpu1.dcache.writebacks::writebacks 117473 # number of writebacks 1928system.cpu1.dcache.writebacks::total 117473 # number of writebacks 1929system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79558 # number of ReadReq MSHR hits 1930system.cpu1.dcache.ReadReq_mshr_hits::total 79558 # number of ReadReq MSHR hits 1931system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306502 # number of WriteReq MSHR hits 1932system.cpu1.dcache.WriteReq_mshr_hits::total 306502 # number of WriteReq MSHR hits 1933system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits 1934system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits 1935system.cpu1.dcache.demand_mshr_hits::cpu1.data 386060 # number of demand (read+write) MSHR hits 1936system.cpu1.dcache.demand_mshr_hits::total 386060 # number of demand (read+write) MSHR hits 1937system.cpu1.dcache.overall_mshr_hits::cpu1.data 386060 # number of overall MSHR hits 1938system.cpu1.dcache.overall_mshr_hits::total 386060 # number of overall MSHR hits 1939system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139857 # number of ReadReq MSHR misses 1940system.cpu1.dcache.ReadReq_mshr_misses::total 139857 # number of ReadReq MSHR misses 1941system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91805 # number of WriteReq MSHR misses 1942system.cpu1.dcache.WriteReq_mshr_misses::total 91805 # number of WriteReq MSHR misses 1943system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28628 # number of SoftPFReq MSHR misses 1944system.cpu1.dcache.SoftPFReq_mshr_misses::total 28628 # number of SoftPFReq MSHR misses 1945system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4934 # number of LoadLockedReq MSHR misses 1946system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4934 # number of LoadLockedReq MSHR misses 1947system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23394 # number of StoreCondReq MSHR misses 1948system.cpu1.dcache.StoreCondReq_mshr_misses::total 23394 # number of StoreCondReq MSHR misses 1949system.cpu1.dcache.demand_mshr_misses::cpu1.data 231662 # number of demand (read+write) MSHR misses 1950system.cpu1.dcache.demand_mshr_misses::total 231662 # number of demand (read+write) MSHR misses 1951system.cpu1.dcache.overall_mshr_misses::cpu1.data 260290 # number of overall MSHR misses 1952system.cpu1.dcache.overall_mshr_misses::total 260290 # number of overall MSHR misses 1953system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829354050 # number of ReadReq MSHR miss cycles 1954system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829354050 # number of ReadReq MSHR miss cycles 1955system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2195265722 # number of WriteReq MSHR miss cycles 1956system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2195265722 # number of WriteReq MSHR miss cycles 1957system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493416244 # number of SoftPFReq MSHR miss cycles 1958system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493416244 # number of SoftPFReq MSHR miss cycles 1959system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87143250 # number of LoadLockedReq MSHR miss cycles 1960system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87143250 # number of LoadLockedReq MSHR miss cycles 1961system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494733684 # number of StoreCondReq MSHR miss cycles 1962system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494733684 # number of StoreCondReq MSHR miss cycles 1963system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 482500 # number of StoreCondFailReq MSHR miss cycles 1964system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 482500 # number of StoreCondFailReq MSHR miss cycles 1965system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024619772 # number of demand (read+write) MSHR miss cycles 1966system.cpu1.dcache.demand_mshr_miss_latency::total 4024619772 # number of demand (read+write) MSHR miss cycles 1967system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518036016 # number of overall MSHR miss cycles 1968system.cpu1.dcache.overall_mshr_miss_latency::total 4518036016 # number of overall MSHR miss cycles 1969system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298838492 # number of ReadReq MSHR uncacheable cycles 1970system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298838492 # number of ReadReq MSHR uncacheable cycles 1971system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826630495 # number of WriteReq MSHR uncacheable cycles 1972system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826630495 # number of WriteReq MSHR uncacheable cycles 1973system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125468987 # number of overall MSHR uncacheable cycles 1974system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125468987 # number of overall MSHR uncacheable cycles 1975system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014280 # mshr miss rate for ReadReq accesses 1976system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014280 # mshr miss rate for ReadReq accesses 1977system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014552 # mshr miss rate for WriteReq accesses 1978system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014552 # mshr miss rate for WriteReq accesses 1979system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359350 # mshr miss rate for SoftPFReq accesses 1980system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359350 # mshr miss rate for SoftPFReq accesses 1981system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050727 # mshr miss rate for LoadLockedReq accesses 1982system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050727 # mshr miss rate for LoadLockedReq accesses 1983system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247831 # mshr miss rate for StoreCondReq accesses 1984system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247831 # mshr miss rate for StoreCondReq accesses 1985system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014386 # mshr miss rate for demand accesses 1986system.cpu1.dcache.demand_mshr_miss_rate::total 0.014386 # mshr miss rate for demand accesses 1987system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016085 # mshr miss rate for overall accesses 1988system.cpu1.dcache.overall_mshr_miss_rate::total 0.016085 # mshr miss rate for overall accesses 1989system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13080.175107 # average ReadReq mshr miss latency 1990system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13080.175107 # average ReadReq mshr miss latency 1991system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23912.267545 # average WriteReq mshr miss latency 1992system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23912.267545 # average WriteReq mshr miss latency 1993system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17235.442364 # average SoftPFReq mshr miss latency 1994system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17235.442364 # average SoftPFReq mshr miss latency 1995system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17661.785570 # average LoadLockedReq mshr miss latency 1996system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17661.785570 # average LoadLockedReq mshr miss latency 1997system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21147.887664 # average StoreCondReq mshr miss latency 1998system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21147.887664 # average StoreCondReq mshr miss latency 1999system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2000system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2001system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17372.809403 # average overall mshr miss latency 2002system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17372.809403 # average overall mshr miss latency 2003system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17357.701087 # average overall mshr miss latency 2004system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17357.701087 # average overall mshr miss latency 2005system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2006system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2007system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2008system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2009system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2010system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2011system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2012system.cpu1.icache.tags.replacements 607164 # number of replacements 2013system.cpu1.icache.tags.tagsinuse 499.524787 # Cycle average of tags in use 2014system.cpu1.icache.tags.total_refs 43017402 # Total number of references to valid blocks. 2015system.cpu1.icache.tags.sampled_refs 607676 # Sample count of references to valid blocks. 2016system.cpu1.icache.tags.avg_refs 70.790030 # Average number of references to valid blocks. |
| 2628system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit. | 2017system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit. |
| 2629system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524677 # Average occupied blocks per requestor | 2018system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524787 # Average occupied blocks per requestor |
| 2630system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy 2631system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy 2632system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2633system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2634system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2635system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2019system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy 2020system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy 2021system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2022system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2023system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2024system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2636system.cpu1.icache.tags.tag_accesses 87890334 # Number of tag accesses 2637system.cpu1.icache.tags.data_accesses 87890334 # Number of data accesses 2638system.cpu1.icache.ReadReq_hits::cpu1.inst 43016935 # number of ReadReq hits 2639system.cpu1.icache.ReadReq_hits::total 43016935 # number of ReadReq hits 2640system.cpu1.icache.demand_hits::cpu1.inst 43016935 # number of demand (read+write) hits 2641system.cpu1.icache.demand_hits::total 43016935 # number of demand (read+write) hits 2642system.cpu1.icache.overall_hits::cpu1.inst 43016935 # number of overall hits 2643system.cpu1.icache.overall_hits::total 43016935 # number of overall hits 2644system.cpu1.icache.ReadReq_misses::cpu1.inst 624358 # number of ReadReq misses 2645system.cpu1.icache.ReadReq_misses::total 624358 # number of ReadReq misses 2646system.cpu1.icache.demand_misses::cpu1.inst 624358 # number of demand (read+write) misses 2647system.cpu1.icache.demand_misses::total 624358 # number of demand (read+write) misses 2648system.cpu1.icache.overall_misses::cpu1.inst 624358 # number of overall misses 2649system.cpu1.icache.overall_misses::total 624358 # number of overall misses 2650system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5094140300 # number of ReadReq miss cycles 2651system.cpu1.icache.ReadReq_miss_latency::total 5094140300 # number of ReadReq miss cycles 2652system.cpu1.icache.demand_miss_latency::cpu1.inst 5094140300 # number of demand (read+write) miss cycles 2653system.cpu1.icache.demand_miss_latency::total 5094140300 # number of demand (read+write) miss cycles 2654system.cpu1.icache.overall_miss_latency::cpu1.inst 5094140300 # number of overall miss cycles 2655system.cpu1.icache.overall_miss_latency::total 5094140300 # number of overall miss cycles 2656system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641293 # number of ReadReq accesses(hits+misses) 2657system.cpu1.icache.ReadReq_accesses::total 43641293 # number of ReadReq accesses(hits+misses) 2658system.cpu1.icache.demand_accesses::cpu1.inst 43641293 # number of demand (read+write) accesses 2659system.cpu1.icache.demand_accesses::total 43641293 # number of demand (read+write) accesses 2660system.cpu1.icache.overall_accesses::cpu1.inst 43641293 # number of overall (read+write) accesses 2661system.cpu1.icache.overall_accesses::total 43641293 # number of overall (read+write) accesses 2662system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014307 # miss rate for ReadReq accesses 2663system.cpu1.icache.ReadReq_miss_rate::total 0.014307 # miss rate for ReadReq accesses 2664system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014307 # miss rate for demand accesses 2665system.cpu1.icache.demand_miss_rate::total 0.014307 # miss rate for demand accesses 2666system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014307 # miss rate for overall accesses 2667system.cpu1.icache.overall_miss_rate::total 0.014307 # miss rate for overall accesses 2668system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8159.005410 # average ReadReq miss latency 2669system.cpu1.icache.ReadReq_avg_miss_latency::total 8159.005410 # average ReadReq miss latency 2670system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency 2671system.cpu1.icache.demand_avg_miss_latency::total 8159.005410 # average overall miss latency 2672system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency 2673system.cpu1.icache.overall_avg_miss_latency::total 8159.005410 # average overall miss latency 2674system.cpu1.icache.blocked_cycles::no_mshrs 274240 # number of cycles access was blocked | 2025system.cpu1.icache.tags.tag_accesses 87891037 # Number of tag accesses 2026system.cpu1.icache.tags.data_accesses 87891037 # Number of data accesses 2027system.cpu1.icache.ReadReq_hits::cpu1.inst 43017402 # number of ReadReq hits 2028system.cpu1.icache.ReadReq_hits::total 43017402 # number of ReadReq hits 2029system.cpu1.icache.demand_hits::cpu1.inst 43017402 # number of demand (read+write) hits 2030system.cpu1.icache.demand_hits::total 43017402 # number of demand (read+write) hits 2031system.cpu1.icache.overall_hits::cpu1.inst 43017402 # number of overall hits 2032system.cpu1.icache.overall_hits::total 43017402 # number of overall hits 2033system.cpu1.icache.ReadReq_misses::cpu1.inst 624277 # number of ReadReq misses 2034system.cpu1.icache.ReadReq_misses::total 624277 # number of ReadReq misses 2035system.cpu1.icache.demand_misses::cpu1.inst 624277 # number of demand (read+write) misses 2036system.cpu1.icache.demand_misses::total 624277 # number of demand (read+write) misses 2037system.cpu1.icache.overall_misses::cpu1.inst 624277 # number of overall misses 2038system.cpu1.icache.overall_misses::total 624277 # number of overall misses 2039system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095487535 # number of ReadReq miss cycles 2040system.cpu1.icache.ReadReq_miss_latency::total 5095487535 # number of ReadReq miss cycles 2041system.cpu1.icache.demand_miss_latency::cpu1.inst 5095487535 # number of demand (read+write) miss cycles 2042system.cpu1.icache.demand_miss_latency::total 5095487535 # number of demand (read+write) miss cycles 2043system.cpu1.icache.overall_miss_latency::cpu1.inst 5095487535 # number of overall miss cycles 2044system.cpu1.icache.overall_miss_latency::total 5095487535 # number of overall miss cycles 2045system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641679 # number of ReadReq accesses(hits+misses) 2046system.cpu1.icache.ReadReq_accesses::total 43641679 # number of ReadReq accesses(hits+misses) 2047system.cpu1.icache.demand_accesses::cpu1.inst 43641679 # number of demand (read+write) accesses 2048system.cpu1.icache.demand_accesses::total 43641679 # number of demand (read+write) accesses 2049system.cpu1.icache.overall_accesses::cpu1.inst 43641679 # number of overall (read+write) accesses 2050system.cpu1.icache.overall_accesses::total 43641679 # number of overall (read+write) accesses 2051system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014305 # miss rate for ReadReq accesses 2052system.cpu1.icache.ReadReq_miss_rate::total 0.014305 # miss rate for ReadReq accesses 2053system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014305 # miss rate for demand accesses 2054system.cpu1.icache.demand_miss_rate::total 0.014305 # miss rate for demand accesses 2055system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014305 # miss rate for overall accesses 2056system.cpu1.icache.overall_miss_rate::total 0.014305 # miss rate for overall accesses 2057system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8162.222115 # average ReadReq miss latency 2058system.cpu1.icache.ReadReq_avg_miss_latency::total 8162.222115 # average ReadReq miss latency 2059system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8162.222115 # average overall miss latency 2060system.cpu1.icache.demand_avg_miss_latency::total 8162.222115 # average overall miss latency 2061system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8162.222115 # average overall miss latency 2062system.cpu1.icache.overall_avg_miss_latency::total 8162.222115 # average overall miss latency 2063system.cpu1.icache.blocked_cycles::no_mshrs 276500 # number of cycles access was blocked |
| 2675system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2064system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2676system.cpu1.icache.blocked::no_mshrs 36121 # number of cycles access was blocked | 2065system.cpu1.icache.blocked::no_mshrs 36143 # number of cycles access was blocked |
| 2677system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 2066system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 2678system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.592259 # average number of cycles each access was blocked | 2067system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.650167 # average number of cycles each access was blocked |
| 2679system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2680system.cpu1.icache.fast_writes 0 # number of fast writes performed 2681system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2068system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2069system.cpu1.icache.fast_writes 0 # number of fast writes performed 2070system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2682system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16610 # number of ReadReq MSHR hits 2683system.cpu1.icache.ReadReq_mshr_hits::total 16610 # number of ReadReq MSHR hits 2684system.cpu1.icache.demand_mshr_hits::cpu1.inst 16610 # number of demand (read+write) MSHR hits 2685system.cpu1.icache.demand_mshr_hits::total 16610 # number of demand (read+write) MSHR hits 2686system.cpu1.icache.overall_mshr_hits::cpu1.inst 16610 # number of overall MSHR hits 2687system.cpu1.icache.overall_mshr_hits::total 16610 # number of overall MSHR hits 2688system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607748 # number of ReadReq MSHR misses 2689system.cpu1.icache.ReadReq_mshr_misses::total 607748 # number of ReadReq MSHR misses 2690system.cpu1.icache.demand_mshr_misses::cpu1.inst 607748 # number of demand (read+write) MSHR misses 2691system.cpu1.icache.demand_mshr_misses::total 607748 # number of demand (read+write) MSHR misses 2692system.cpu1.icache.overall_mshr_misses::cpu1.inst 607748 # number of overall MSHR misses 2693system.cpu1.icache.overall_mshr_misses::total 607748 # number of overall MSHR misses 2694system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4102836710 # number of ReadReq MSHR miss cycles 2695system.cpu1.icache.ReadReq_mshr_miss_latency::total 4102836710 # number of ReadReq MSHR miss cycles 2696system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4102836710 # number of demand (read+write) MSHR miss cycles 2697system.cpu1.icache.demand_mshr_miss_latency::total 4102836710 # number of demand (read+write) MSHR miss cycles 2698system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4102836710 # number of overall MSHR miss cycles 2699system.cpu1.icache.overall_mshr_miss_latency::total 4102836710 # number of overall MSHR miss cycles | 2071system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16598 # number of ReadReq MSHR hits 2072system.cpu1.icache.ReadReq_mshr_hits::total 16598 # number of ReadReq MSHR hits 2073system.cpu1.icache.demand_mshr_hits::cpu1.inst 16598 # number of demand (read+write) MSHR hits 2074system.cpu1.icache.demand_mshr_hits::total 16598 # number of demand (read+write) MSHR hits 2075system.cpu1.icache.overall_mshr_hits::cpu1.inst 16598 # number of overall MSHR hits 2076system.cpu1.icache.overall_mshr_hits::total 16598 # number of overall MSHR hits 2077system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607679 # number of ReadReq MSHR misses 2078system.cpu1.icache.ReadReq_mshr_misses::total 607679 # number of ReadReq MSHR misses 2079system.cpu1.icache.demand_mshr_misses::cpu1.inst 607679 # number of demand (read+write) MSHR misses 2080system.cpu1.icache.demand_mshr_misses::total 607679 # number of demand (read+write) MSHR misses 2081system.cpu1.icache.overall_mshr_misses::cpu1.inst 607679 # number of overall MSHR misses 2082system.cpu1.icache.overall_mshr_misses::total 607679 # number of overall MSHR misses 2083system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4104857215 # number of ReadReq MSHR miss cycles 2084system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104857215 # number of ReadReq MSHR miss cycles 2085system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104857215 # number of demand (read+write) MSHR miss cycles 2086system.cpu1.icache.demand_mshr_miss_latency::total 4104857215 # number of demand (read+write) MSHR miss cycles 2087system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104857215 # number of overall MSHR miss cycles 2088system.cpu1.icache.overall_mshr_miss_latency::total 4104857215 # number of overall MSHR miss cycles |
| 2700system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles 2701system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles 2702system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles 2703system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles | 2089system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles 2090system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles 2091system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles 2092system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles |
| 2704system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses 2705system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 2706system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses 2707system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 2708system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses 2709system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses 2710system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average ReadReq mshr miss latency 2711system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6750.884758 # average ReadReq mshr miss latency 2712system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency 2713system.cpu1.icache.demand_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency 2714system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency 2715system.cpu1.icache.overall_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency | 2093system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for ReadReq accesses 2094system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013924 # mshr miss rate for ReadReq accesses 2095system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for demand accesses 2096system.cpu1.icache.demand_mshr_miss_rate::total 0.013924 # mshr miss rate for demand accesses 2097system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for overall accesses 2098system.cpu1.icache.overall_mshr_miss_rate::total 0.013924 # mshr miss rate for overall accesses 2099system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average ReadReq mshr miss latency 2100system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.976254 # average ReadReq mshr miss latency 2101system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average overall mshr miss latency 2102system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.976254 # average overall mshr miss latency 2103system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average overall mshr miss latency 2104system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.976254 # average overall mshr miss latency |
| 2716system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2717system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2718system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2719system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2720system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2105system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2106system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2107system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2108system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2109system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2721system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841881 # number of hwpf identified 2722system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43251 # number of hwpf that were already in mshr 2723system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4640074 # number of hwpf that were already in the cache 2724system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42977 # number of hwpf that were already in the prefetch queue | 2110system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841342 # number of hwpf identified 2111system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43201 # number of hwpf that were already in mshr 2112system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639993 # number of hwpf that were already in the cache 2113system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42894 # number of hwpf that were already in the prefetch queue |
| 2725system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 2114system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 2726system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6024 # number of hwpf removed because MSHR allocated 2727system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109555 # number of hwpf issued 2728system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564023 # number of hwpf spanning a virtual page | 2115system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 5995 # number of hwpf removed because MSHR allocated 2116system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109259 # number of hwpf issued 2117system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564002 # number of hwpf spanning a virtual page |
| 2729system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 2118system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 2730system.cpu1.l2cache.tags.replacements 85866 # number of replacements 2731system.cpu1.l2cache.tags.tagsinuse 15600.635673 # Cycle average of tags in use 2732system.cpu1.l2cache.tags.total_refs 846675 # Total number of references to valid blocks. 2733system.cpu1.l2cache.tags.sampled_refs 100980 # Sample count of references to valid blocks. 2734system.cpu1.l2cache.tags.avg_refs 8.384581 # Average number of references to valid blocks. | 2119system.cpu1.l2cache.tags.replacements 85775 # number of replacements 2120system.cpu1.l2cache.tags.tagsinuse 15600.933964 # Cycle average of tags in use 2121system.cpu1.l2cache.tags.total_refs 846435 # Total number of references to valid blocks. 2122system.cpu1.l2cache.tags.sampled_refs 100895 # Sample count of references to valid blocks. 2123system.cpu1.l2cache.tags.avg_refs 8.389266 # Average number of references to valid blocks. |
| 2735system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2124system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2736system.cpu1.l2cache.tags.occ_blocks::writebacks 6012.739780 # Average occupied blocks per requestor 2737system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.101116 # Average occupied blocks per requestor 2738system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.182282 # Average occupied blocks per requestor 2739system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 726.495477 # Average occupied blocks per requestor 2740system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1966.711133 # Average occupied blocks per requestor 2741system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.405886 # Average occupied blocks per requestor 2742system.cpu1.l2cache.tags.occ_percent::writebacks 0.366989 # Average percentage of cache occupancy 2743system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000555 # Average percentage of cache occupancy | 2125system.cpu1.l2cache.tags.occ_blocks::writebacks 5997.093337 # Average occupied blocks per requestor 2126system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.379548 # Average occupied blocks per requestor 2127system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.187782 # Average occupied blocks per requestor 2128system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 717.531946 # Average occupied blocks per requestor 2129system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1990.637648 # Average occupied blocks per requestor 2130system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.103702 # Average occupied blocks per requestor 2131system.cpu1.l2cache.tags.occ_percent::writebacks 0.366034 # Average percentage of cache occupancy 2132system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000634 # Average percentage of cache occupancy |
| 2744system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000072 # Average percentage of cache occupancy | 2133system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000072 # Average percentage of cache occupancy |
| 2745system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.044342 # Average percentage of cache occupancy 2746system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.120039 # Average percentage of cache occupancy 2747system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.420191 # Average percentage of cache occupancy 2748system.cpu1.l2cache.tags.occ_percent::total 0.952187 # Average percentage of cache occupancy 2749system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9526 # Occupied blocks per task id | 2134system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.043795 # Average percentage of cache occupancy 2135system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.121499 # Average percentage of cache occupancy 2136system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.420172 # Average percentage of cache occupancy 2137system.cpu1.l2cache.tags.occ_percent::total 0.952205 # Average percentage of cache occupancy 2138system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9541 # Occupied blocks per task id |
| 2750system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id | 2139system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id |
| 2751system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5563 # Occupied blocks per task id 2752system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id 2753system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8131 # Occupied blocks per task id 2754system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1089 # Occupied blocks per task id | 2140system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5554 # Occupied blocks per task id 2141system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 314 # Occupied blocks per task id 2142system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8089 # Occupied blocks per task id 2143system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1138 # Occupied blocks per task id |
| 2755system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id | 2144system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id |
| 2756system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 2757system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 2758system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 415 # Occupied blocks per task id 2759system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4194 # Occupied blocks per task id 2760system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 954 # Occupied blocks per task id 2761system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.581421 # Percentage of cache occupancy per task id | 2145system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2146system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 2147system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id 2148system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4157 # Occupied blocks per task id 2149system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 969 # Occupied blocks per task id 2150system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.582336 # Percentage of cache occupancy per task id |
| 2762system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id | 2151system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id |
| 2763system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.339539 # Percentage of cache occupancy per task id 2764system.cpu1.l2cache.tags.tag_accesses 16877479 # Number of tag accesses 2765system.cpu1.l2cache.tags.data_accesses 16877479 # Number of data accesses 2766system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16335 # number of ReadReq hits 2767system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7409 # number of ReadReq hits 2768system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601802 # number of ReadReq hits 2769system.cpu1.l2cache.ReadReq_hits::cpu1.data 101305 # number of ReadReq hits 2770system.cpu1.l2cache.ReadReq_hits::total 726851 # number of ReadReq hits 2771system.cpu1.l2cache.Writeback_hits::writebacks 117435 # number of Writeback hits 2772system.cpu1.l2cache.Writeback_hits::total 117435 # number of Writeback hits 2773system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2252 # number of UpgradeReq hits 2774system.cpu1.l2cache.UpgradeReq_hits::total 2252 # number of UpgradeReq hits 2775system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 837 # number of SCUpgradeReq hits 2776system.cpu1.l2cache.SCUpgradeReq_hits::total 837 # number of SCUpgradeReq hits 2777system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28910 # number of ReadExReq hits 2778system.cpu1.l2cache.ReadExReq_hits::total 28910 # number of ReadExReq hits 2779system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16335 # number of demand (read+write) hits 2780system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7409 # number of demand (read+write) hits 2781system.cpu1.l2cache.demand_hits::cpu1.inst 601802 # number of demand (read+write) hits 2782system.cpu1.l2cache.demand_hits::cpu1.data 130215 # number of demand (read+write) hits 2783system.cpu1.l2cache.demand_hits::total 755761 # number of demand (read+write) hits 2784system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16335 # number of overall hits 2785system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7409 # number of overall hits 2786system.cpu1.l2cache.overall_hits::cpu1.inst 601802 # number of overall hits 2787system.cpu1.l2cache.overall_hits::cpu1.data 130215 # number of overall hits 2788system.cpu1.l2cache.overall_hits::total 755761 # number of overall hits 2789system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses 2790system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses 2791system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5943 # number of ReadReq misses 2792system.cpu1.l2cache.ReadReq_misses::cpu1.data 72078 # number of ReadReq misses 2793system.cpu1.l2cache.ReadReq_misses::total 78769 # number of ReadReq misses 2794system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28388 # number of UpgradeReq misses 2795system.cpu1.l2cache.UpgradeReq_misses::total 28388 # number of UpgradeReq misses 2796system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22558 # number of SCUpgradeReq misses 2797system.cpu1.l2cache.SCUpgradeReq_misses::total 22558 # number of SCUpgradeReq misses | 2152system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.338989 # Percentage of cache occupancy per task id 2153system.cpu1.l2cache.tags.tag_accesses 16876081 # Number of tag accesses 2154system.cpu1.l2cache.tags.data_accesses 16876081 # Number of data accesses 2155system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16270 # number of ReadReq hits 2156system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7392 # number of ReadReq hits 2157system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601743 # number of ReadReq hits 2158system.cpu1.l2cache.ReadReq_hits::cpu1.data 101269 # number of ReadReq hits 2159system.cpu1.l2cache.ReadReq_hits::total 726674 # number of ReadReq hits 2160system.cpu1.l2cache.Writeback_hits::writebacks 117472 # number of Writeback hits 2161system.cpu1.l2cache.Writeback_hits::total 117472 # number of Writeback hits 2162system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits 2163system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits 2164system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 802 # number of SCUpgradeReq hits 2165system.cpu1.l2cache.SCUpgradeReq_hits::total 802 # number of SCUpgradeReq hits 2166system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28891 # number of ReadExReq hits 2167system.cpu1.l2cache.ReadExReq_hits::total 28891 # number of ReadExReq hits 2168system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16270 # number of demand (read+write) hits 2169system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7392 # number of demand (read+write) hits 2170system.cpu1.l2cache.demand_hits::cpu1.inst 601743 # number of demand (read+write) hits 2171system.cpu1.l2cache.demand_hits::cpu1.data 130160 # number of demand (read+write) hits 2172system.cpu1.l2cache.demand_hits::total 755565 # number of demand (read+write) hits 2173system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16270 # number of overall hits 2174system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7392 # number of overall hits 2175system.cpu1.l2cache.overall_hits::cpu1.inst 601743 # number of overall hits 2176system.cpu1.l2cache.overall_hits::cpu1.data 130160 # number of overall hits 2177system.cpu1.l2cache.overall_hits::total 755565 # number of overall hits 2178system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 463 # number of ReadReq misses 2179system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses 2180system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5933 # number of ReadReq misses 2181system.cpu1.l2cache.ReadReq_misses::cpu1.data 72130 # number of ReadReq misses 2182system.cpu1.l2cache.ReadReq_misses::total 78803 # number of ReadReq misses 2183system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28401 # number of UpgradeReq misses 2184system.cpu1.l2cache.UpgradeReq_misses::total 28401 # number of UpgradeReq misses 2185system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22590 # number of SCUpgradeReq misses 2186system.cpu1.l2cache.SCUpgradeReq_misses::total 22590 # number of SCUpgradeReq misses |
| 2798system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2799system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses | 2187system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2188system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses |
| 2800system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32913 # number of ReadExReq misses 2801system.cpu1.l2cache.ReadExReq_misses::total 32913 # number of ReadExReq misses 2802system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses 2803system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses 2804system.cpu1.l2cache.demand_misses::cpu1.inst 5943 # number of demand (read+write) misses 2805system.cpu1.l2cache.demand_misses::cpu1.data 104991 # number of demand (read+write) misses 2806system.cpu1.l2cache.demand_misses::total 111682 # number of demand (read+write) misses 2807system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses 2808system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses 2809system.cpu1.l2cache.overall_misses::cpu1.inst 5943 # number of overall misses 2810system.cpu1.l2cache.overall_misses::cpu1.data 104991 # number of overall misses 2811system.cpu1.l2cache.overall_misses::total 111682 # number of overall misses 2812system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10433249 # number of ReadReq miss cycles 2813system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5666498 # number of ReadReq miss cycles 2814system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 181785702 # number of ReadReq miss cycles 2815system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1611031625 # number of ReadReq miss cycles 2816system.cpu1.l2cache.ReadReq_miss_latency::total 1808917074 # number of ReadReq miss cycles 2817system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536972883 # number of UpgradeReq miss cycles 2818system.cpu1.l2cache.UpgradeReq_miss_latency::total 536972883 # number of UpgradeReq miss cycles 2819system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442531028 # number of SCUpgradeReq miss cycles 2820system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442531028 # number of SCUpgradeReq miss cycles 2821system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 437999 # number of SCUpgradeFailReq miss cycles 2822system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 437999 # number of SCUpgradeFailReq miss cycles 2823system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1278690285 # number of ReadExReq miss cycles 2824system.cpu1.l2cache.ReadExReq_miss_latency::total 1278690285 # number of ReadExReq miss cycles 2825system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10433249 # number of demand (read+write) miss cycles 2826system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5666498 # number of demand (read+write) miss cycles 2827system.cpu1.l2cache.demand_miss_latency::cpu1.inst 181785702 # number of demand (read+write) miss cycles 2828system.cpu1.l2cache.demand_miss_latency::cpu1.data 2889721910 # number of demand (read+write) miss cycles 2829system.cpu1.l2cache.demand_miss_latency::total 3087607359 # number of demand (read+write) miss cycles 2830system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10433249 # number of overall miss cycles 2831system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5666498 # number of overall miss cycles 2832system.cpu1.l2cache.overall_miss_latency::cpu1.inst 181785702 # number of overall miss cycles 2833system.cpu1.l2cache.overall_miss_latency::cpu1.data 2889721910 # number of overall miss cycles 2834system.cpu1.l2cache.overall_miss_latency::total 3087607359 # number of overall miss cycles 2835system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16807 # number of ReadReq accesses(hits+misses) 2836system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7685 # number of ReadReq accesses(hits+misses) 2837system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607745 # number of ReadReq accesses(hits+misses) 2838system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173383 # number of ReadReq accesses(hits+misses) 2839system.cpu1.l2cache.ReadReq_accesses::total 805620 # number of ReadReq accesses(hits+misses) 2840system.cpu1.l2cache.Writeback_accesses::writebacks 117435 # number of Writeback accesses(hits+misses) 2841system.cpu1.l2cache.Writeback_accesses::total 117435 # number of Writeback accesses(hits+misses) 2842system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30640 # number of UpgradeReq accesses(hits+misses) 2843system.cpu1.l2cache.UpgradeReq_accesses::total 30640 # number of UpgradeReq accesses(hits+misses) 2844system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23395 # number of SCUpgradeReq accesses(hits+misses) 2845system.cpu1.l2cache.SCUpgradeReq_accesses::total 23395 # number of SCUpgradeReq accesses(hits+misses) | 2189system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32934 # number of ReadExReq misses 2190system.cpu1.l2cache.ReadExReq_misses::total 32934 # number of ReadExReq misses 2191system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 463 # number of demand (read+write) misses 2192system.cpu1.l2cache.demand_misses::cpu1.itb.walker 277 # number of demand (read+write) misses 2193system.cpu1.l2cache.demand_misses::cpu1.inst 5933 # number of demand (read+write) misses 2194system.cpu1.l2cache.demand_misses::cpu1.data 105064 # number of demand (read+write) misses 2195system.cpu1.l2cache.demand_misses::total 111737 # number of demand (read+write) misses 2196system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 463 # number of overall misses 2197system.cpu1.l2cache.overall_misses::cpu1.itb.walker 277 # number of overall misses 2198system.cpu1.l2cache.overall_misses::cpu1.inst 5933 # number of overall misses 2199system.cpu1.l2cache.overall_misses::cpu1.data 105064 # number of overall misses 2200system.cpu1.l2cache.overall_misses::total 111737 # number of overall misses 2201system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10189999 # number of ReadReq miss cycles 2202system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5582499 # number of ReadReq miss cycles 2203system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 184105701 # number of ReadReq miss cycles 2204system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612613119 # number of ReadReq miss cycles 2205system.cpu1.l2cache.ReadReq_miss_latency::total 1812491318 # number of ReadReq miss cycles 2206system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537520391 # number of UpgradeReq miss cycles 2207system.cpu1.l2cache.UpgradeReq_miss_latency::total 537520391 # number of UpgradeReq miss cycles 2208system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 443077527 # number of SCUpgradeReq miss cycles 2209system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443077527 # number of SCUpgradeReq miss cycles 2210system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 471499 # number of SCUpgradeFailReq miss cycles 2211system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 471499 # number of SCUpgradeFailReq miss cycles 2212system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1278985047 # number of ReadExReq miss cycles 2213system.cpu1.l2cache.ReadExReq_miss_latency::total 1278985047 # number of ReadExReq miss cycles 2214system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10189999 # number of demand (read+write) miss cycles 2215system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5582499 # number of demand (read+write) miss cycles 2216system.cpu1.l2cache.demand_miss_latency::cpu1.inst 184105701 # number of demand (read+write) miss cycles 2217system.cpu1.l2cache.demand_miss_latency::cpu1.data 2891598166 # number of demand (read+write) miss cycles 2218system.cpu1.l2cache.demand_miss_latency::total 3091476365 # number of demand (read+write) miss cycles 2219system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10189999 # number of overall miss cycles 2220system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5582499 # number of overall miss cycles 2221system.cpu1.l2cache.overall_miss_latency::cpu1.inst 184105701 # number of overall miss cycles 2222system.cpu1.l2cache.overall_miss_latency::cpu1.data 2891598166 # number of overall miss cycles 2223system.cpu1.l2cache.overall_miss_latency::total 3091476365 # number of overall miss cycles 2224system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16733 # number of ReadReq accesses(hits+misses) 2225system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7669 # number of ReadReq accesses(hits+misses) 2226system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607676 # number of ReadReq accesses(hits+misses) 2227system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173399 # number of ReadReq accesses(hits+misses) 2228system.cpu1.l2cache.ReadReq_accesses::total 805477 # number of ReadReq accesses(hits+misses) 2229system.cpu1.l2cache.Writeback_accesses::writebacks 117472 # number of Writeback accesses(hits+misses) 2230system.cpu1.l2cache.Writeback_accesses::total 117472 # number of Writeback accesses(hits+misses) 2231system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30662 # number of UpgradeReq accesses(hits+misses) 2232system.cpu1.l2cache.UpgradeReq_accesses::total 30662 # number of UpgradeReq accesses(hits+misses) 2233system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23392 # number of SCUpgradeReq accesses(hits+misses) 2234system.cpu1.l2cache.SCUpgradeReq_accesses::total 23392 # number of SCUpgradeReq accesses(hits+misses) |
| 2846system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2847system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) | 2235system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2236system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) |
| 2848system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61823 # number of ReadExReq accesses(hits+misses) 2849system.cpu1.l2cache.ReadExReq_accesses::total 61823 # number of ReadExReq accesses(hits+misses) 2850system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16807 # number of demand (read+write) accesses 2851system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7685 # number of demand (read+write) accesses 2852system.cpu1.l2cache.demand_accesses::cpu1.inst 607745 # number of demand (read+write) accesses 2853system.cpu1.l2cache.demand_accesses::cpu1.data 235206 # number of demand (read+write) accesses 2854system.cpu1.l2cache.demand_accesses::total 867443 # number of demand (read+write) accesses 2855system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16807 # number of overall (read+write) accesses 2856system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7685 # number of overall (read+write) accesses 2857system.cpu1.l2cache.overall_accesses::cpu1.inst 607745 # number of overall (read+write) accesses 2858system.cpu1.l2cache.overall_accesses::cpu1.data 235206 # number of overall (read+write) accesses 2859system.cpu1.l2cache.overall_accesses::total 867443 # number of overall (read+write) accesses 2860system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for ReadReq accesses 2861system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035914 # miss rate for ReadReq accesses 2862system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009779 # miss rate for ReadReq accesses 2863system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415715 # miss rate for ReadReq accesses 2864system.cpu1.l2cache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses 2865system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926501 # miss rate for UpgradeReq accesses 2866system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926501 # miss rate for UpgradeReq accesses 2867system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964223 # miss rate for SCUpgradeReq accesses 2868system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964223 # miss rate for SCUpgradeReq accesses | 2237system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61825 # number of ReadExReq accesses(hits+misses) 2238system.cpu1.l2cache.ReadExReq_accesses::total 61825 # number of ReadExReq accesses(hits+misses) 2239system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16733 # number of demand (read+write) accesses 2240system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7669 # number of demand (read+write) accesses 2241system.cpu1.l2cache.demand_accesses::cpu1.inst 607676 # number of demand (read+write) accesses 2242system.cpu1.l2cache.demand_accesses::cpu1.data 235224 # number of demand (read+write) accesses 2243system.cpu1.l2cache.demand_accesses::total 867302 # number of demand (read+write) accesses 2244system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16733 # number of overall (read+write) accesses 2245system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7669 # number of overall (read+write) accesses 2246system.cpu1.l2cache.overall_accesses::cpu1.inst 607676 # number of overall (read+write) accesses 2247system.cpu1.l2cache.overall_accesses::cpu1.data 235224 # number of overall (read+write) accesses 2248system.cpu1.l2cache.overall_accesses::total 867302 # number of overall (read+write) accesses 2249system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.027670 # miss rate for ReadReq accesses 2250system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036119 # miss rate for ReadReq accesses 2251system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009763 # miss rate for ReadReq accesses 2252system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415977 # miss rate for ReadReq accesses 2253system.cpu1.l2cache.ReadReq_miss_rate::total 0.097834 # miss rate for ReadReq accesses 2254system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926261 # miss rate for UpgradeReq accesses 2255system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926261 # miss rate for UpgradeReq accesses 2256system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.965715 # miss rate for SCUpgradeReq accesses 2257system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.965715 # miss rate for SCUpgradeReq accesses |
| 2869system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2870system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2258system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2259system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2871system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532375 # miss rate for ReadExReq accesses 2872system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532375 # miss rate for ReadExReq accesses 2873system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for demand accesses 2874system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035914 # miss rate for demand accesses 2875system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009779 # miss rate for demand accesses 2876system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446379 # miss rate for demand accesses 2877system.cpu1.l2cache.demand_miss_rate::total 0.128749 # miss rate for demand accesses 2878system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for overall accesses 2879system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035914 # miss rate for overall accesses 2880system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009779 # miss rate for overall accesses 2881system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446379 # miss rate for overall accesses 2882system.cpu1.l2cache.overall_miss_rate::total 0.128749 # miss rate for overall accesses 2883system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average ReadReq miss latency 2884system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20530.789855 # average ReadReq miss latency 2885system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30588.204947 # average ReadReq miss latency 2886system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22351.225409 # average ReadReq miss latency 2887system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22964.834821 # average ReadReq miss latency 2888system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18915.488340 # average UpgradeReq miss latency 2889system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18915.488340 # average UpgradeReq miss latency 2890system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19617.476195 # average SCUpgradeReq miss latency 2891system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.476195 # average SCUpgradeReq miss latency 2892system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 218999.500000 # average SCUpgradeFailReq miss latency 2893system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 218999.500000 # average SCUpgradeFailReq miss latency 2894system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38850.614803 # average ReadExReq miss latency 2895system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38850.614803 # average ReadExReq miss latency 2896system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency 2897system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency 2898system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency 2899system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency 2900system.cpu1.l2cache.demand_avg_miss_latency::total 27646.418931 # average overall miss latency 2901system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency 2902system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency 2903system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency 2904system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency 2905system.cpu1.l2cache.overall_avg_miss_latency::total 27646.418931 # average overall miss latency 2906system.cpu1.l2cache.blocked_cycles::no_mshrs 22060 # number of cycles access was blocked | 2260system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532697 # miss rate for ReadExReq accesses 2261system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532697 # miss rate for ReadExReq accesses 2262system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.027670 # miss rate for demand accesses 2263system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036119 # miss rate for demand accesses 2264system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009763 # miss rate for demand accesses 2265system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446655 # miss rate for demand accesses 2266system.cpu1.l2cache.demand_miss_rate::total 0.128833 # miss rate for demand accesses 2267system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.027670 # miss rate for overall accesses 2268system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036119 # miss rate for overall accesses 2269system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009763 # miss rate for overall accesses 2270system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446655 # miss rate for overall accesses 2271system.cpu1.l2cache.overall_miss_rate::total 0.128833 # miss rate for overall accesses 2272system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22008.637149 # average ReadReq miss latency 2273system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20153.425993 # average ReadReq miss latency 2274system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31030.794033 # average ReadReq miss latency 2275system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22357.037557 # average ReadReq miss latency 2276system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23000.283213 # average ReadReq miss latency 2277system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18926.107919 # average UpgradeReq miss latency 2278system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18926.107919 # average UpgradeReq miss latency 2279system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19613.879017 # average SCUpgradeReq miss latency 2280system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19613.879017 # average SCUpgradeReq miss latency 2281system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 235749.500000 # average SCUpgradeFailReq miss latency 2282system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 235749.500000 # average SCUpgradeFailReq miss latency 2283system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38834.792221 # average ReadExReq miss latency 2284system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38834.792221 # average ReadExReq miss latency 2285system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.637149 # average overall miss latency 2286system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20153.425993 # average overall miss latency 2287system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31030.794033 # average overall miss latency 2288system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27522.254683 # average overall miss latency 2289system.cpu1.l2cache.demand_avg_miss_latency::total 27667.436615 # average overall miss latency 2290system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22008.637149 # average overall miss latency 2291system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20153.425993 # average overall miss latency 2292system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31030.794033 # average overall miss latency 2293system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27522.254683 # average overall miss latency 2294system.cpu1.l2cache.overall_avg_miss_latency::total 27667.436615 # average overall miss latency 2295system.cpu1.l2cache.blocked_cycles::no_mshrs 22985 # number of cycles access was blocked |
| 2907system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2296system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2908system.cpu1.l2cache.blocked::no_mshrs 480 # number of cycles access was blocked | 2297system.cpu1.l2cache.blocked::no_mshrs 493 # number of cycles access was blocked |
| 2909system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2298system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2910system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.958333 # average number of cycles each access was blocked | 2299system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.622718 # average number of cycles each access was blocked |
| 2911system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2912system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2913system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2300system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2301system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2302system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2914system.cpu1.l2cache.writebacks::writebacks 40786 # number of writebacks 2915system.cpu1.l2cache.writebacks::total 40786 # number of writebacks 2916system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits 2917system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1367 # number of ReadReq MSHR hits 2918system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 84 # number of ReadReq MSHR hits 2919system.cpu1.l2cache.ReadReq_mshr_hits::total 1465 # number of ReadReq MSHR hits 2920system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1237 # number of ReadExReq MSHR hits 2921system.cpu1.l2cache.ReadExReq_mshr_hits::total 1237 # number of ReadExReq MSHR hits 2922system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits 2923system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1367 # number of demand (read+write) MSHR hits 2924system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1321 # number of demand (read+write) MSHR hits 2925system.cpu1.l2cache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits 2926system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits 2927system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1367 # number of overall MSHR hits 2928system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1321 # number of overall MSHR hits 2929system.cpu1.l2cache.overall_mshr_hits::total 2702 # number of overall MSHR hits 2930system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 472 # number of ReadReq MSHR misses 2931system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses 2932system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4576 # number of ReadReq MSHR misses 2933system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71994 # number of ReadReq MSHR misses 2934system.cpu1.l2cache.ReadReq_mshr_misses::total 77304 # number of ReadReq MSHR misses 2935system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of HardPFReq MSHR misses 2936system.cpu1.l2cache.HardPFReq_mshr_misses::total 109552 # number of HardPFReq MSHR misses 2937system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28388 # number of UpgradeReq MSHR misses 2938system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28388 # number of UpgradeReq MSHR misses 2939system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22558 # number of SCUpgradeReq MSHR misses 2940system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22558 # number of SCUpgradeReq MSHR misses | 2303system.cpu1.l2cache.writebacks::writebacks 40759 # number of writebacks 2304system.cpu1.l2cache.writebacks::total 40759 # number of writebacks 2305system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits 2306system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1321 # number of ReadReq MSHR hits 2307system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 73 # number of ReadReq MSHR hits 2308system.cpu1.l2cache.ReadReq_mshr_hits::total 1407 # number of ReadReq MSHR hits 2309system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1252 # number of ReadExReq MSHR hits 2310system.cpu1.l2cache.ReadExReq_mshr_hits::total 1252 # number of ReadExReq MSHR hits 2311system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits 2312system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1321 # number of demand (read+write) MSHR hits 2313system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1325 # number of demand (read+write) MSHR hits 2314system.cpu1.l2cache.demand_mshr_hits::total 2659 # number of demand (read+write) MSHR hits 2315system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits 2316system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1321 # number of overall MSHR hits 2317system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1325 # number of overall MSHR hits 2318system.cpu1.l2cache.overall_mshr_hits::total 2659 # number of overall MSHR hits 2319system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 463 # number of ReadReq MSHR misses 2320system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 264 # number of ReadReq MSHR misses 2321system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4612 # number of ReadReq MSHR misses 2322system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72057 # number of ReadReq MSHR misses 2323system.cpu1.l2cache.ReadReq_mshr_misses::total 77396 # number of ReadReq MSHR misses 2324system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109257 # number of HardPFReq MSHR misses 2325system.cpu1.l2cache.HardPFReq_mshr_misses::total 109257 # number of HardPFReq MSHR misses 2326system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28401 # number of UpgradeReq MSHR misses 2327system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28401 # number of UpgradeReq MSHR misses 2328system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22590 # number of SCUpgradeReq MSHR misses 2329system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22590 # number of SCUpgradeReq MSHR misses |
| 2941system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2942system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses | 2330system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2331system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses |
| 2943system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31676 # number of ReadExReq MSHR misses 2944system.cpu1.l2cache.ReadExReq_mshr_misses::total 31676 # number of ReadExReq MSHR misses 2945system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 472 # number of demand (read+write) MSHR misses 2946system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses 2947system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4576 # number of demand (read+write) MSHR misses 2948system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103670 # number of demand (read+write) MSHR misses 2949system.cpu1.l2cache.demand_mshr_misses::total 108980 # number of demand (read+write) MSHR misses 2950system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 472 # number of overall MSHR misses 2951system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses 2952system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4576 # number of overall MSHR misses 2953system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103670 # number of overall MSHR misses 2954system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of overall MSHR misses 2955system.cpu1.l2cache.overall_mshr_misses::total 218532 # number of overall MSHR misses 2956system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of ReadReq MSHR miss cycles 2957system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3660000 # number of ReadReq MSHR miss cycles 2958system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 123437534 # number of ReadReq MSHR miss cycles 2959system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105460943 # number of ReadReq MSHR miss cycles 2960system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1239685228 # number of ReadReq MSHR miss cycles 2961system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of HardPFReq MSHR miss cycles 2962system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3461172800 # number of HardPFReq MSHR miss cycles 2963system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 416881074 # number of UpgradeReq MSHR miss cycles 2964system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 416881074 # number of UpgradeReq MSHR miss cycles 2965system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308366284 # number of SCUpgradeReq MSHR miss cycles 2966system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308366284 # number of SCUpgradeReq MSHR miss cycles 2967system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 367999 # number of SCUpgradeFailReq MSHR miss cycles 2968system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 367999 # number of SCUpgradeFailReq MSHR miss cycles 2969system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944446910 # number of ReadExReq MSHR miss cycles 2970system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944446910 # number of ReadExReq MSHR miss cycles 2971system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of demand (read+write) MSHR miss cycles 2972system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3660000 # number of demand (read+write) MSHR miss cycles 2973system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 123437534 # number of demand (read+write) MSHR miss cycles 2974system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2049907853 # number of demand (read+write) MSHR miss cycles 2975system.cpu1.l2cache.demand_mshr_miss_latency::total 2184132138 # number of demand (read+write) MSHR miss cycles 2976system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of overall MSHR miss cycles 2977system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3660000 # number of overall MSHR miss cycles 2978system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 123437534 # number of overall MSHR miss cycles 2979system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2049907853 # number of overall MSHR miss cycles 2980system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of overall MSHR miss cycles 2981system.cpu1.l2cache.overall_mshr_miss_latency::total 5645304938 # number of overall MSHR miss cycles | 2332system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31682 # number of ReadExReq MSHR misses 2333system.cpu1.l2cache.ReadExReq_mshr_misses::total 31682 # number of ReadExReq MSHR misses 2334system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 463 # number of demand (read+write) MSHR misses 2335system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 264 # number of demand (read+write) MSHR misses 2336system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4612 # number of demand (read+write) MSHR misses 2337system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103739 # number of demand (read+write) MSHR misses 2338system.cpu1.l2cache.demand_mshr_misses::total 109078 # number of demand (read+write) MSHR misses 2339system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 463 # number of overall MSHR misses 2340system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 264 # number of overall MSHR misses 2341system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4612 # number of overall MSHR misses 2342system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103739 # number of overall MSHR misses 2343system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109257 # number of overall MSHR misses 2344system.cpu1.l2cache.overall_mshr_misses::total 218335 # number of overall MSHR misses 2345system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6946001 # number of ReadReq MSHR miss cycles 2346system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3570001 # number of ReadReq MSHR miss cycles 2347system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 126408787 # number of ReadReq MSHR miss cycles 2348system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1106793437 # number of ReadReq MSHR miss cycles 2349system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1243718226 # number of ReadReq MSHR miss cycles 2350system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3470833266 # number of HardPFReq MSHR miss cycles 2351system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3470833266 # number of HardPFReq MSHR miss cycles 2352system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417527555 # number of UpgradeReq MSHR miss cycles 2353system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417527555 # number of UpgradeReq MSHR miss cycles 2354system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308789786 # number of SCUpgradeReq MSHR miss cycles 2355system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308789786 # number of SCUpgradeReq MSHR miss cycles 2356system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 394499 # number of SCUpgradeFailReq MSHR miss cycles 2357system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 394499 # number of SCUpgradeFailReq MSHR miss cycles 2358system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 943695401 # number of ReadExReq MSHR miss cycles 2359system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 943695401 # number of ReadExReq MSHR miss cycles 2360system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6946001 # number of demand (read+write) MSHR miss cycles 2361system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3570001 # number of demand (read+write) MSHR miss cycles 2362system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 126408787 # number of demand (read+write) MSHR miss cycles 2363system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2050488838 # number of demand (read+write) MSHR miss cycles 2364system.cpu1.l2cache.demand_mshr_miss_latency::total 2187413627 # number of demand (read+write) MSHR miss cycles 2365system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6946001 # number of overall MSHR miss cycles 2366system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3570001 # number of overall MSHR miss cycles 2367system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 126408787 # number of overall MSHR miss cycles 2368system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2050488838 # number of overall MSHR miss cycles 2369system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3470833266 # number of overall MSHR miss cycles 2370system.cpu1.l2cache.overall_mshr_miss_latency::total 5658246893 # number of overall MSHR miss cycles |
| 2982system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles | 2371system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles |
| 2983system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182190507 # number of ReadReq MSHR uncacheable cycles 2984system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189531257 # number of ReadReq MSHR uncacheable cycles 2985system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737661499 # number of WriteReq MSHR uncacheable cycles 2986system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737661499 # number of WriteReq MSHR uncacheable cycles | 2372system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182197007 # number of ReadReq MSHR uncacheable cycles 2373system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189537757 # number of ReadReq MSHR uncacheable cycles 2374system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737457999 # number of WriteReq MSHR uncacheable cycles 2375system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737457999 # number of WriteReq MSHR uncacheable cycles |
| 2987system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles | 2376system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles |
| 2988system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919852006 # number of overall MSHR uncacheable cycles 2989system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927192756 # number of overall MSHR uncacheable cycles 2990system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for ReadReq accesses 2991system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for ReadReq accesses 2992system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for ReadReq accesses 2993system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415231 # mshr miss rate for ReadReq accesses 2994system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.095956 # mshr miss rate for ReadReq accesses | 2377system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919655006 # number of overall MSHR uncacheable cycles 2378system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926995756 # number of overall MSHR uncacheable cycles 2379system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for ReadReq accesses 2380system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for ReadReq accesses 2381system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for ReadReq accesses 2382system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415556 # mshr miss rate for ReadReq accesses 2383system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096087 # mshr miss rate for ReadReq accesses |
| 2995system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2996system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2384system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2385system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2997system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926501 # mshr miss rate for UpgradeReq accesses 2998system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926501 # mshr miss rate for UpgradeReq accesses 2999system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964223 # mshr miss rate for SCUpgradeReq accesses 3000system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964223 # mshr miss rate for SCUpgradeReq accesses | 2386system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926261 # mshr miss rate for UpgradeReq accesses 2387system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926261 # mshr miss rate for UpgradeReq accesses 2388system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.965715 # mshr miss rate for SCUpgradeReq accesses 2389system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.965715 # mshr miss rate for SCUpgradeReq accesses |
| 3001system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 3002system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2390system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2391system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 3003system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512366 # mshr miss rate for ReadExReq accesses 3004system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512366 # mshr miss rate for ReadExReq accesses 3005system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for demand accesses 3006system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for demand accesses 3007system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for demand accesses 3008system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for demand accesses 3009system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125634 # mshr miss rate for demand accesses 3010system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for overall accesses 3011system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for overall accesses 3012system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for overall accesses 3013system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for overall accesses | 2392system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512446 # mshr miss rate for ReadExReq accesses 2393system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512446 # mshr miss rate for ReadExReq accesses 2394system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for demand accesses 2395system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for demand accesses 2396system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for demand accesses 2397system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.441022 # mshr miss rate for demand accesses 2398system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125767 # mshr miss rate for demand accesses 2399system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for overall accesses 2400system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for overall accesses 2401system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for overall accesses 2402system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.441022 # mshr miss rate for overall accesses |
| 3014system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2403system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 3015system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251927 # mshr miss rate for overall accesses 3016system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average ReadReq mshr miss latency 3017system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average ReadReq mshr miss latency 3018system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average ReadReq mshr miss latency 3019system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15354.903784 # average ReadReq mshr miss latency 3020system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.495240 # average ReadReq mshr miss latency 3021system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average HardPFReq mshr miss latency 3022system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31593.880532 # average HardPFReq mshr miss latency 3023system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14685.116035 # average UpgradeReq mshr miss latency 3024system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14685.116035 # average UpgradeReq mshr miss latency 3025system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.930136 # average SCUpgradeReq mshr miss latency 3026system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.930136 # average SCUpgradeReq mshr miss latency 3027system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183999.500000 # average SCUpgradeFailReq mshr miss latency 3028system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183999.500000 # average SCUpgradeFailReq mshr miss latency 3029system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29815.851433 # average ReadExReq mshr miss latency 3030system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29815.851433 # average ReadExReq mshr miss latency 3031system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency 3032system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency 3033system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency 3034system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency 3035system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20041.586878 # average overall mshr miss latency 3036system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency 3037system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency 3038system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency 3039system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency 3040system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average overall mshr miss latency 3041system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25832.852571 # average overall mshr miss latency | 2404system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251740 # mshr miss rate for overall accesses 2405system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average ReadReq mshr miss latency 2406system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average ReadReq mshr miss latency 2407system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average ReadReq mshr miss latency 2408system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15359.971092 # average ReadReq mshr miss latency 2409system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16069.541397 # average ReadReq mshr miss latency 2410system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average HardPFReq mshr miss latency 2411system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31767.605426 # average HardPFReq mshr miss latency 2412system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14701.156825 # average UpgradeReq mshr miss latency 2413system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14701.156825 # average UpgradeReq mshr miss latency 2414system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.313236 # average SCUpgradeReq mshr miss latency 2415system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.313236 # average SCUpgradeReq mshr miss latency 2416system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 197249.500000 # average SCUpgradeFailReq mshr miss latency 2417system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 197249.500000 # average SCUpgradeFailReq mshr miss latency 2418system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29786.484471 # average ReadExReq mshr miss latency 2419system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29786.484471 # average ReadExReq mshr miss latency 2420system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency 2421system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency 2422system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency 2423system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency 2424system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20053.664598 # average overall mshr miss latency 2425system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency 2426system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency 2427system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency 2428system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency 2429system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average overall mshr miss latency 2430system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25915.436797 # average overall mshr miss latency |
| 3042system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3043system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3044system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3045system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3046system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3047system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3048system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3049system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3050system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2431system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2432system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2433system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2434system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2435system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2436system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2437system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2438system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2439system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 3051system.cpu1.dcache.tags.replacements 191071 # number of replacements 3052system.cpu1.dcache.tags.tagsinuse 472.558673 # Cycle average of tags in use 3053system.cpu1.dcache.tags.total_refs 15741841 # Total number of references to valid blocks. 3054system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. 3055system.cpu1.dcache.tags.avg_refs 82.247922 # Average number of references to valid blocks. 3056system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. 3057system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558673 # Average occupied blocks per requestor 3058system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy 3059system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy 3060system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id 3061system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 3062system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 3063system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id 3064system.cpu1.dcache.tags.tag_accesses 32983753 # Number of tag accesses 3065system.cpu1.dcache.tags.data_accesses 32983753 # Number of data accesses 3066system.cpu1.dcache.ReadReq_hits::cpu1.data 9574420 # number of ReadReq hits 3067system.cpu1.dcache.ReadReq_hits::total 9574420 # number of ReadReq hits 3068system.cpu1.dcache.WriteReq_hits::cpu1.data 5910665 # number of WriteReq hits 3069system.cpu1.dcache.WriteReq_hits::total 5910665 # number of WriteReq hits 3070system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49536 # number of SoftPFReq hits 3071system.cpu1.dcache.SoftPFReq_hits::total 49536 # number of SoftPFReq hits 3072system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79144 # number of LoadLockedReq hits 3073system.cpu1.dcache.LoadLockedReq_hits::total 79144 # number of LoadLockedReq hits 3074system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71002 # number of StoreCondReq hits 3075system.cpu1.dcache.StoreCondReq_hits::total 71002 # number of StoreCondReq hits 3076system.cpu1.dcache.demand_hits::cpu1.data 15485085 # number of demand (read+write) hits 3077system.cpu1.dcache.demand_hits::total 15485085 # number of demand (read+write) hits 3078system.cpu1.dcache.overall_hits::cpu1.data 15534621 # number of overall hits 3079system.cpu1.dcache.overall_hits::total 15534621 # number of overall hits 3080system.cpu1.dcache.ReadReq_misses::cpu1.data 219558 # number of ReadReq misses 3081system.cpu1.dcache.ReadReq_misses::total 219558 # number of ReadReq misses 3082system.cpu1.dcache.WriteReq_misses::cpu1.data 398300 # number of WriteReq misses 3083system.cpu1.dcache.WriteReq_misses::total 398300 # number of WriteReq misses 3084system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30127 # number of SoftPFReq misses 3085system.cpu1.dcache.SoftPFReq_misses::total 30127 # number of SoftPFReq misses 3086system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18119 # number of LoadLockedReq misses 3087system.cpu1.dcache.LoadLockedReq_misses::total 18119 # number of LoadLockedReq misses 3088system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23397 # number of StoreCondReq misses 3089system.cpu1.dcache.StoreCondReq_misses::total 23397 # number of StoreCondReq misses 3090system.cpu1.dcache.demand_misses::cpu1.data 617858 # number of demand (read+write) misses 3091system.cpu1.dcache.demand_misses::total 617858 # number of demand (read+write) misses 3092system.cpu1.dcache.overall_misses::cpu1.data 647985 # number of overall misses 3093system.cpu1.dcache.overall_misses::total 647985 # number of overall misses 3094system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453411003 # number of ReadReq miss cycles 3095system.cpu1.dcache.ReadReq_miss_latency::total 3453411003 # number of ReadReq miss cycles 3096system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8719629262 # number of WriteReq miss cycles 3097system.cpu1.dcache.WriteReq_miss_latency::total 8719629262 # number of WriteReq miss cycles 3098system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362936751 # number of LoadLockedReq miss cycles 3099system.cpu1.dcache.LoadLockedReq_miss_latency::total 362936751 # number of LoadLockedReq miss cycles 3100system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542268315 # number of StoreCondReq miss cycles 3101system.cpu1.dcache.StoreCondReq_miss_latency::total 542268315 # number of StoreCondReq miss cycles 3102system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 468000 # number of StoreCondFailReq miss cycles 3103system.cpu1.dcache.StoreCondFailReq_miss_latency::total 468000 # number of StoreCondFailReq miss cycles 3104system.cpu1.dcache.demand_miss_latency::cpu1.data 12173040265 # number of demand (read+write) miss cycles 3105system.cpu1.dcache.demand_miss_latency::total 12173040265 # number of demand (read+write) miss cycles 3106system.cpu1.dcache.overall_miss_latency::cpu1.data 12173040265 # number of overall miss cycles 3107system.cpu1.dcache.overall_miss_latency::total 12173040265 # number of overall miss cycles 3108system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793978 # number of ReadReq accesses(hits+misses) 3109system.cpu1.dcache.ReadReq_accesses::total 9793978 # number of ReadReq accesses(hits+misses) 3110system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308965 # number of WriteReq accesses(hits+misses) 3111system.cpu1.dcache.WriteReq_accesses::total 6308965 # number of WriteReq accesses(hits+misses) 3112system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79663 # number of SoftPFReq accesses(hits+misses) 3113system.cpu1.dcache.SoftPFReq_accesses::total 79663 # number of SoftPFReq accesses(hits+misses) 3114system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97263 # number of LoadLockedReq accesses(hits+misses) 3115system.cpu1.dcache.LoadLockedReq_accesses::total 97263 # number of LoadLockedReq accesses(hits+misses) 3116system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94399 # number of StoreCondReq accesses(hits+misses) 3117system.cpu1.dcache.StoreCondReq_accesses::total 94399 # number of StoreCondReq accesses(hits+misses) 3118system.cpu1.dcache.demand_accesses::cpu1.data 16102943 # number of demand (read+write) accesses 3119system.cpu1.dcache.demand_accesses::total 16102943 # number of demand (read+write) accesses 3120system.cpu1.dcache.overall_accesses::cpu1.data 16182606 # number of overall (read+write) accesses 3121system.cpu1.dcache.overall_accesses::total 16182606 # number of overall (read+write) accesses 3122system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022418 # miss rate for ReadReq accesses 3123system.cpu1.dcache.ReadReq_miss_rate::total 0.022418 # miss rate for ReadReq accesses 3124system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063132 # miss rate for WriteReq accesses 3125system.cpu1.dcache.WriteReq_miss_rate::total 0.063132 # miss rate for WriteReq accesses 3126system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378181 # miss rate for SoftPFReq accesses 3127system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378181 # miss rate for SoftPFReq accesses 3128system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186289 # miss rate for LoadLockedReq accesses 3129system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186289 # miss rate for LoadLockedReq accesses 3130system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247852 # miss rate for StoreCondReq accesses 3131system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247852 # miss rate for StoreCondReq accesses 3132system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038369 # miss rate for demand accesses 3133system.cpu1.dcache.demand_miss_rate::total 0.038369 # miss rate for demand accesses 3134system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040042 # miss rate for overall accesses 3135system.cpu1.dcache.overall_miss_rate::total 0.040042 # miss rate for overall accesses 3136system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15728.923578 # average ReadReq miss latency 3137system.cpu1.dcache.ReadReq_avg_miss_latency::total 15728.923578 # average ReadReq miss latency 3138system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21892.114642 # average WriteReq miss latency 3139system.cpu1.dcache.WriteReq_avg_miss_latency::total 21892.114642 # average WriteReq miss latency 3140system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.727468 # average LoadLockedReq miss latency 3141system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.727468 # average LoadLockedReq miss latency 3142system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23176.831004 # average StoreCondReq miss latency 3143system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23176.831004 # average StoreCondReq miss latency 3144system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 3145system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 3146system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19702.003154 # average overall miss latency 3147system.cpu1.dcache.demand_avg_miss_latency::total 19702.003154 # average overall miss latency 3148system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18785.990825 # average overall miss latency 3149system.cpu1.dcache.overall_avg_miss_latency::total 18785.990825 # average overall miss latency 3150system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked 3151system.cpu1.dcache.blocked_cycles::no_targets 1110000 # number of cycles access was blocked 3152system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked 3153system.cpu1.dcache.blocked::no_targets 39631 # number of cycles access was blocked 3154system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked 3155system.cpu1.dcache.avg_blocked_cycles::no_targets 28.008377 # average number of cycles each access was blocked 3156system.cpu1.dcache.fast_writes 0 # number of fast writes performed 3157system.cpu1.dcache.cache_copies 0 # number of cache copies performed 3158system.cpu1.dcache.writebacks::writebacks 117436 # number of writebacks 3159system.cpu1.dcache.writebacks::total 117436 # number of writebacks 3160system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79714 # number of ReadReq MSHR hits 3161system.cpu1.dcache.ReadReq_mshr_hits::total 79714 # number of ReadReq MSHR hits 3162system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306518 # number of WriteReq MSHR hits 3163system.cpu1.dcache.WriteReq_mshr_hits::total 306518 # number of WriteReq MSHR hits 3164system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits 3165system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits 3166system.cpu1.dcache.demand_mshr_hits::cpu1.data 386232 # number of demand (read+write) MSHR hits 3167system.cpu1.dcache.demand_mshr_hits::total 386232 # number of demand (read+write) MSHR hits 3168system.cpu1.dcache.overall_mshr_hits::cpu1.data 386232 # number of overall MSHR hits 3169system.cpu1.dcache.overall_mshr_hits::total 386232 # number of overall MSHR hits 3170system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139844 # number of ReadReq MSHR misses 3171system.cpu1.dcache.ReadReq_mshr_misses::total 139844 # number of ReadReq MSHR misses 3172system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91782 # number of WriteReq MSHR misses 3173system.cpu1.dcache.WriteReq_mshr_misses::total 91782 # number of WriteReq MSHR misses 3174system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28626 # number of SoftPFReq MSHR misses 3175system.cpu1.dcache.SoftPFReq_mshr_misses::total 28626 # number of SoftPFReq MSHR misses 3176system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4932 # number of LoadLockedReq MSHR misses 3177system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4932 # number of LoadLockedReq MSHR misses 3178system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23397 # number of StoreCondReq MSHR misses 3179system.cpu1.dcache.StoreCondReq_mshr_misses::total 23397 # number of StoreCondReq MSHR misses 3180system.cpu1.dcache.demand_mshr_misses::cpu1.data 231626 # number of demand (read+write) MSHR misses 3181system.cpu1.dcache.demand_mshr_misses::total 231626 # number of demand (read+write) MSHR misses 3182system.cpu1.dcache.overall_mshr_misses::cpu1.data 260252 # number of overall MSHR misses 3183system.cpu1.dcache.overall_mshr_misses::total 260252 # number of overall MSHR misses 3184system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827153559 # number of ReadReq MSHR miss cycles 3185system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827153559 # number of ReadReq MSHR miss cycles 3186system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2193887187 # number of WriteReq MSHR miss cycles 3187system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2193887187 # number of WriteReq MSHR miss cycles 3188system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494621242 # number of SoftPFReq MSHR miss cycles 3189system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494621242 # number of SoftPFReq MSHR miss cycles 3190system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939750 # number of LoadLockedReq MSHR miss cycles 3191system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939750 # number of LoadLockedReq MSHR miss cycles 3192system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494306685 # number of StoreCondReq MSHR miss cycles 3193system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494306685 # number of StoreCondReq MSHR miss cycles 3194system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 448000 # number of StoreCondFailReq MSHR miss cycles 3195system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 448000 # number of StoreCondFailReq MSHR miss cycles 3196system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4021040746 # number of demand (read+write) MSHR miss cycles 3197system.cpu1.dcache.demand_mshr_miss_latency::total 4021040746 # number of demand (read+write) MSHR miss cycles 3198system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4515661988 # number of overall MSHR miss cycles 3199system.cpu1.dcache.overall_mshr_miss_latency::total 4515661988 # number of overall MSHR miss cycles 3200system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298831492 # number of ReadReq MSHR uncacheable cycles 3201system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298831492 # number of ReadReq MSHR uncacheable cycles 3202system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826840995 # number of WriteReq MSHR uncacheable cycles 3203system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826840995 # number of WriteReq MSHR uncacheable cycles 3204system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125672487 # number of overall MSHR uncacheable cycles 3205system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125672487 # number of overall MSHR uncacheable cycles 3206system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses 3207system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses 3208system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014548 # mshr miss rate for WriteReq accesses 3209system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014548 # mshr miss rate for WriteReq accesses 3210system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359339 # mshr miss rate for SoftPFReq accesses 3211system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359339 # mshr miss rate for SoftPFReq accesses 3212system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050708 # mshr miss rate for LoadLockedReq accesses 3213system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050708 # mshr miss rate for LoadLockedReq accesses 3214system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247852 # mshr miss rate for StoreCondReq accesses 3215system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247852 # mshr miss rate for StoreCondReq accesses 3216system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014384 # mshr miss rate for demand accesses 3217system.cpu1.dcache.demand_mshr_miss_rate::total 0.014384 # mshr miss rate for demand accesses 3218system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016082 # mshr miss rate for overall accesses 3219system.cpu1.dcache.overall_mshr_miss_rate::total 0.016082 # mshr miss rate for overall accesses 3220system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13065.655724 # average ReadReq mshr miss latency 3221system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13065.655724 # average ReadReq mshr miss latency 3222system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23903.240145 # average WriteReq mshr miss latency 3223system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23903.240145 # average WriteReq mshr miss latency 3224system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17278.741075 # average SoftPFReq mshr miss latency 3225system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17278.741075 # average SoftPFReq mshr miss latency 3226system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17627.686537 # average LoadLockedReq mshr miss latency 3227system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17627.686537 # average LoadLockedReq mshr miss latency 3228system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21126.925888 # average StoreCondReq mshr miss latency 3229system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21126.925888 # average StoreCondReq mshr miss latency 3230system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 3231system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 3232system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17360.057791 # average overall mshr miss latency 3233system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17360.057791 # average overall mshr miss latency 3234system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17351.113490 # average overall mshr miss latency 3235system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17351.113490 # average overall mshr miss latency 3236system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3237system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3238system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3239system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3240system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3241system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3242system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2440system.cpu1.toL2Bus.trans_dist::ReadReq 1294408 # Transaction distribution 2441system.cpu1.toL2Bus.trans_dist::ReadResp 865128 # Transaction distribution 2442system.cpu1.toL2Bus.trans_dist::WriteReq 11871 # Transaction distribution 2443system.cpu1.toL2Bus.trans_dist::WriteResp 11871 # Transaction distribution 2444system.cpu1.toL2Bus.trans_dist::Writeback 117472 # Transaction distribution 2445system.cpu1.toL2Bus.trans_dist::HardPFReq 157468 # Transaction distribution 2446system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution 2447system.cpu1.toL2Bus.trans_dist::UpgradeReq 84838 # Transaction distribution 2448system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41861 # Transaction distribution 2449system.cpu1.toL2Bus.trans_dist::UpgradeResp 87109 # Transaction distribution 2450system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2451system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 2452system.cpu1.toL2Bus.trans_dist::ReadExReq 79574 # Transaction distribution 2453system.cpu1.toL2Bus.trans_dist::ReadExResp 66376 # Transaction distribution 2454system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215557 # Packet count per connected master and slave (bytes) 2455system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825064 # Packet count per connected master and slave (bytes) 2456system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17352 # Packet count per connected master and slave (bytes) 2457system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37871 # Packet count per connected master and slave (bytes) 2458system.cpu1.toL2Bus.pkt_count::total 2095844 # Packet count per connected master and slave (bytes) 2459system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38892880 # Cumulative packet size per connected master and slave (bytes) 2460system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25436874 # Cumulative packet size per connected master and slave (bytes) 2461system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes) 2462system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66932 # Cumulative packet size per connected master and slave (bytes) 2463system.cpu1.toL2Bus.pkt_size::total 64427362 # Cumulative packet size per connected master and slave (bytes) 2464system.cpu1.toL2Bus.snoops 834611 # Total snoops (count) 2465system.cpu1.toL2Bus.snoop_fanout::samples 1797339 # Request fanout histogram 2466system.cpu1.toL2Bus.snoop_fanout::mean 5.418381 # Request fanout histogram 2467system.cpu1.toL2Bus.snoop_fanout::stdev 0.493294 # Request fanout histogram 2468system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2469system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2470system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2471system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2472system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2473system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2474system.cpu1.toL2Bus.snoop_fanout::5 1045366 58.16% 58.16% # Request fanout histogram 2475system.cpu1.toL2Bus.snoop_fanout::6 751973 41.84% 100.00% # Request fanout histogram 2476system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2477system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2478system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2479system.cpu1.toL2Bus.snoop_fanout::total 1797339 # Request fanout histogram 2480system.cpu1.toL2Bus.reqLayer0.occupancy 659657903 # Layer occupancy (ticks) 2481system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2482system.cpu1.toL2Bus.snoopLayer0.occupancy 81258998 # Layer occupancy (ticks) 2483system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2484system.cpu1.toL2Bus.respLayer0.occupancy 912908354 # Layer occupancy (ticks) 2485system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2486system.cpu1.toL2Bus.respLayer1.occupancy 403842529 # Layer occupancy (ticks) 2487system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2488system.cpu1.toL2Bus.respLayer2.occupancy 9825216 # Layer occupancy (ticks) 2489system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2490system.cpu1.toL2Bus.respLayer3.occupancy 21209360 # Layer occupancy (ticks) 2491system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2492system.iobus.trans_dist::ReadReq 31016 # Transaction distribution 2493system.iobus.trans_dist::ReadResp 31016 # Transaction distribution 2494system.iobus.trans_dist::WriteReq 59408 # Transaction distribution 2495system.iobus.trans_dist::WriteResp 59439 # Transaction distribution 2496system.iobus.trans_dist::WriteInvalidateReq 31 # Transaction distribution 2497system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) 2498system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2499system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2500system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2501system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2502system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2503system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2504system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2505system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2506system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2507system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2508system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2509system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2510system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2511system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2512system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2513system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2514system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2515system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2516system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2517system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2518system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes) 2519system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) 2520system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) 2521system.iobus.pkt_count::total 180910 # Packet count per connected master and slave (bytes) 2522system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes) 2523system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2524system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2525system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2526system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2527system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2528system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2529system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2530system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2531system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2532system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2533system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2534system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2535system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2536system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2537system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2538system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2539system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2540system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2541system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2542system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2543system.iobus.pkt_size_system.bridge.master::total 162848 # Cumulative packet size per connected master and slave (bytes) 2544system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) 2545system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) 2546system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 2547system.iobus.reqLayer0.occupancy 40134000 # Layer occupancy (ticks) 2548system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2549system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2550system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2551system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2552system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2553system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2554system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2555system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2556system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2557system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 2558system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2559system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2560system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2561system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2562system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2563system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2564system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2565system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2566system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2567system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2568system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2569system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2570system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2571system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2572system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2573system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2574system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2575system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2576system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2577system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2578system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2579system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2580system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2581system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2582system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2583system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2584system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2585system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2586system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2587system.iobus.reqLayer27.occupancy 326664315 # Layer occupancy (ticks) 2588system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2589system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2590system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2591system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) 2592system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2593system.iobus.respLayer3.occupancy 36832361 # Layer occupancy (ticks) 2594system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3243system.iocache.tags.replacements 36453 # number of replacements | 2595system.iocache.tags.replacements 36453 # number of replacements |
| 3244system.iocache.tags.tagsinuse 14.560234 # Cycle average of tags in use | 2596system.iocache.tags.tagsinuse 14.560247 # Cycle average of tags in use |
| 3245system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3246system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. 3247system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 3248system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit. | 2597system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2598system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. 2599system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2600system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit. |
| 3249system.iocache.tags.occ_blocks::realview.ide 14.560234 # Average occupied blocks per requestor | 2601system.iocache.tags.occ_blocks::realview.ide 14.560247 # Average occupied blocks per requestor |
| 3250system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy 3251system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy 3252system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3253system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3254system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2602system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy 2603system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy 2604system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2605system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2606system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 3255system.iocache.tags.tag_accesses 328359 # Number of tag accesses 3256system.iocache.tags.data_accesses 328359 # Number of data accesses | 2607system.iocache.tags.tag_accesses 328487 # Number of tag accesses 2608system.iocache.tags.data_accesses 328487 # Number of data accesses |
| 3257system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 3258system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 3259system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses 3260system.iocache.ReadReq_misses::total 247 # number of ReadReq misses | 2609system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2610system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 2611system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses 2612system.iocache.ReadReq_misses::total 247 # number of ReadReq misses |
| 3261system.iocache.WriteInvalidateReq_misses::realview.ide 15 # number of WriteInvalidateReq misses 3262system.iocache.WriteInvalidateReq_misses::total 15 # number of WriteInvalidateReq misses | 2613system.iocache.WriteInvalidateReq_misses::realview.ide 31 # number of WriteInvalidateReq misses 2614system.iocache.WriteInvalidateReq_misses::total 31 # number of WriteInvalidateReq misses |
| 3263system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses 3264system.iocache.demand_misses::total 247 # number of demand (read+write) misses 3265system.iocache.overall_misses::realview.ide 247 # number of overall misses 3266system.iocache.overall_misses::total 247 # number of overall misses 3267system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles 3268system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles 3269system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles 3270system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles 3271system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles 3272system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles 3273system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) 3274system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) | 2615system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses 2616system.iocache.demand_misses::total 247 # number of demand (read+write) misses 2617system.iocache.overall_misses::realview.ide 247 # number of overall misses 2618system.iocache.overall_misses::total 247 # number of overall misses 2619system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles 2620system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles 2621system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles 2622system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles 2623system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles 2624system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles 2625system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) 2626system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) |
| 3275system.iocache.WriteInvalidateReq_accesses::realview.ide 36239 # number of WriteInvalidateReq accesses(hits+misses) 3276system.iocache.WriteInvalidateReq_accesses::total 36239 # number of WriteInvalidateReq accesses(hits+misses) | 2627system.iocache.WriteInvalidateReq_accesses::realview.ide 36255 # number of WriteInvalidateReq accesses(hits+misses) 2628system.iocache.WriteInvalidateReq_accesses::total 36255 # number of WriteInvalidateReq accesses(hits+misses) |
| 3277system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses 3278system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses 3279system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses 3280system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses 3281system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3282system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 2629system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses 2630system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses 2631system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses 2632system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses 2633system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2634system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 3283system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000414 # miss rate for WriteInvalidateReq accesses 3284system.iocache.WriteInvalidateReq_miss_rate::total 0.000414 # miss rate for WriteInvalidateReq accesses | 2635system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000855 # miss rate for WriteInvalidateReq accesses 2636system.iocache.WriteInvalidateReq_miss_rate::total 0.000855 # miss rate for WriteInvalidateReq accesses |
| 3285system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3286system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3287system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3288system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3289system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency 3290system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency 3291system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency 3292system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency --- 10 unchanged lines hidden (view full) --- 3303system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses 3304system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses 3305system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses 3306system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses 3307system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses 3308system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses 3309system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles 3310system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles | 2637system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2638system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2639system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2640system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2641system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency 2642system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency 2643system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency 2644system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency --- 10 unchanged lines hidden (view full) --- 2655system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses 2656system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses 2657system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses 2658system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses 2659system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses 2660system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses 2661system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles 2662system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles |
| 3311system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2254879547 # number of WriteInvalidateReq MSHR miss cycles 3312system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2254879547 # number of WriteInvalidateReq MSHR miss cycles | 2663system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2253111299 # number of WriteInvalidateReq MSHR miss cycles 2664system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2253111299 # number of WriteInvalidateReq MSHR miss cycles |
| 3313system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles 3314system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles 3315system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles 3316system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles 3317system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3318system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3319system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3320system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3321system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3322system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3323system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency 3324system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency 3325system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 3326system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 3327system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 3328system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency 3329system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 3330system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency 3331system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2665system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles 2666system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles 2667system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles 2668system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles 2669system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2670system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2671system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2672system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2673system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2674system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2675system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency 2676system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency 2677system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2678system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2679system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 2680system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency 2681system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 2682system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency 2683system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2684system.l2c.tags.replacements 153470 # number of replacements 2685system.l2c.tags.tagsinuse 64454.116988 # Cycle average of tags in use 2686system.l2c.tags.total_refs 519887 # Total number of references to valid blocks. 2687system.l2c.tags.sampled_refs 218097 # Sample count of references to valid blocks. 2688system.l2c.tags.avg_refs 2.383742 # Average number of references to valid blocks. 2689system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2690system.l2c.tags.occ_blocks::writebacks 14115.348135 # Average occupied blocks per requestor 2691system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.484821 # Average occupied blocks per requestor 2692system.l2c.tags.occ_blocks::cpu0.itb.walker 2.876495 # Average occupied blocks per requestor 2693system.l2c.tags.occ_blocks::cpu0.inst 1418.724430 # Average occupied blocks per requestor 2694system.l2c.tags.occ_blocks::cpu0.data 2146.622945 # Average occupied blocks per requestor 2695system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39266.214752 # Average occupied blocks per requestor 2696system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.503287 # Average occupied blocks per requestor 2697system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002749 # Average occupied blocks per requestor 2698system.l2c.tags.occ_blocks::cpu1.inst 292.346121 # Average occupied blocks per requestor 2699system.l2c.tags.occ_blocks::cpu1.data 885.503464 # Average occupied blocks per requestor 2700system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6306.489787 # Average occupied blocks per requestor 2701system.l2c.tags.occ_percent::writebacks 0.215383 # Average percentage of cache occupancy 2702system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy 2703system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy 2704system.l2c.tags.occ_percent::cpu0.inst 0.021648 # Average percentage of cache occupancy 2705system.l2c.tags.occ_percent::cpu0.data 0.032755 # Average percentage of cache occupancy 2706system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599155 # Average percentage of cache occupancy 2707system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy 2708system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 2709system.l2c.tags.occ_percent::cpu1.inst 0.004461 # Average percentage of cache occupancy 2710system.l2c.tags.occ_percent::cpu1.data 0.013512 # Average percentage of cache occupancy 2711system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096229 # Average percentage of cache occupancy 2712system.l2c.tags.occ_percent::total 0.983492 # Average percentage of cache occupancy 2713system.l2c.tags.occ_task_id_blocks::1022 44297 # Occupied blocks per task id 2714system.l2c.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2715system.l2c.tags.occ_task_id_blocks::1024 20314 # Occupied blocks per task id 2716system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id 2717system.l2c.tags.age_task_id_blocks_1022::3 7726 # Occupied blocks per task id 2718system.l2c.tags.age_task_id_blocks_1022::4 36160 # Occupied blocks per task id 2719system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 2720system.l2c.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 2721system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 2722system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 2723system.l2c.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id 2724system.l2c.tags.age_task_id_blocks_1024::3 4599 # Occupied blocks per task id 2725system.l2c.tags.age_task_id_blocks_1024::4 15358 # Occupied blocks per task id 2726system.l2c.tags.occ_task_id_percent::1022 0.675919 # Percentage of cache occupancy per task id 2727system.l2c.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 2728system.l2c.tags.occ_task_id_percent::1024 0.309967 # Percentage of cache occupancy per task id 2729system.l2c.tags.tag_accesses 6595063 # Number of tag accesses 2730system.l2c.tags.data_accesses 6595063 # Number of data accesses 2731system.l2c.ReadReq_hits::cpu0.dtb.walker 272 # number of ReadReq hits 2732system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits 2733system.l2c.ReadReq_hits::cpu0.inst 12554 # number of ReadReq hits 2734system.l2c.ReadReq_hits::cpu0.data 38932 # number of ReadReq hits 2735system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 181919 # number of ReadReq hits 2736system.l2c.ReadReq_hits::cpu1.dtb.walker 84 # number of ReadReq hits 2737system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits 2738system.l2c.ReadReq_hits::cpu1.inst 4143 # number of ReadReq hits 2739system.l2c.ReadReq_hits::cpu1.data 11543 # number of ReadReq hits 2740system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44205 # number of ReadReq hits 2741system.l2c.ReadReq_hits::total 293833 # number of ReadReq hits 2742system.l2c.Writeback_hits::writebacks 252624 # number of Writeback hits 2743system.l2c.Writeback_hits::total 252624 # number of Writeback hits 2744system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits 2745system.l2c.UpgradeReq_hits::cpu1.data 720 # number of UpgradeReq hits 2746system.l2c.UpgradeReq_hits::total 12425 # number of UpgradeReq hits 2747system.l2c.SCUpgradeReq_hits::cpu0.data 181 # number of SCUpgradeReq hits 2748system.l2c.SCUpgradeReq_hits::cpu1.data 174 # number of SCUpgradeReq hits 2749system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits 2750system.l2c.ReadExReq_hits::cpu0.data 3713 # number of ReadExReq hits 2751system.l2c.ReadExReq_hits::cpu1.data 1233 # number of ReadExReq hits 2752system.l2c.ReadExReq_hits::total 4946 # number of ReadExReq hits 2753system.l2c.demand_hits::cpu0.dtb.walker 272 # number of demand (read+write) hits 2754system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits 2755system.l2c.demand_hits::cpu0.inst 12554 # number of demand (read+write) hits 2756system.l2c.demand_hits::cpu0.data 42645 # number of demand (read+write) hits 2757system.l2c.demand_hits::cpu0.l2cache.prefetcher 181919 # number of demand (read+write) hits 2758system.l2c.demand_hits::cpu1.dtb.walker 84 # number of demand (read+write) hits 2759system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits 2760system.l2c.demand_hits::cpu1.inst 4143 # number of demand (read+write) hits 2761system.l2c.demand_hits::cpu1.data 12776 # number of demand (read+write) hits 2762system.l2c.demand_hits::cpu1.l2cache.prefetcher 44205 # number of demand (read+write) hits 2763system.l2c.demand_hits::total 298779 # number of demand (read+write) hits 2764system.l2c.overall_hits::cpu0.dtb.walker 272 # number of overall hits 2765system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits 2766system.l2c.overall_hits::cpu0.inst 12554 # number of overall hits 2767system.l2c.overall_hits::cpu0.data 42645 # number of overall hits 2768system.l2c.overall_hits::cpu0.l2cache.prefetcher 181919 # number of overall hits 2769system.l2c.overall_hits::cpu1.dtb.walker 84 # number of overall hits 2770system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits 2771system.l2c.overall_hits::cpu1.inst 4143 # number of overall hits 2772system.l2c.overall_hits::cpu1.data 12776 # number of overall hits 2773system.l2c.overall_hits::cpu1.l2cache.prefetcher 44205 # number of overall hits 2774system.l2c.overall_hits::total 298779 # number of overall hits 2775system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses 2776system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses 2777system.l2c.ReadReq_misses::cpu0.inst 3728 # number of ReadReq misses 2778system.l2c.ReadReq_misses::cpu0.data 8660 # number of ReadReq misses 2779system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164285 # number of ReadReq misses 2780system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses 2781system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 2782system.l2c.ReadReq_misses::cpu1.inst 483 # number of ReadReq misses 2783system.l2c.ReadReq_misses::cpu1.data 1392 # number of ReadReq misses 2784system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21015 # number of ReadReq misses 2785system.l2c.ReadReq_misses::total 199613 # number of ReadReq misses 2786system.l2c.UpgradeReq_misses::cpu0.data 8842 # number of UpgradeReq misses 2787system.l2c.UpgradeReq_misses::cpu1.data 2853 # number of UpgradeReq misses 2788system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses 2789system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses 2790system.l2c.SCUpgradeReq_misses::cpu1.data 1205 # number of SCUpgradeReq misses 2791system.l2c.SCUpgradeReq_misses::total 1954 # number of SCUpgradeReq misses 2792system.l2c.ReadExReq_misses::cpu0.data 7764 # number of ReadExReq misses 2793system.l2c.ReadExReq_misses::cpu1.data 7212 # number of ReadExReq misses 2794system.l2c.ReadExReq_misses::total 14976 # number of ReadExReq misses 2795system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses 2796system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses 2797system.l2c.demand_misses::cpu0.inst 3728 # number of demand (read+write) misses 2798system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses 2799system.l2c.demand_misses::cpu0.l2cache.prefetcher 164285 # number of demand (read+write) misses 2800system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 2801system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 2802system.l2c.demand_misses::cpu1.inst 483 # number of demand (read+write) misses 2803system.l2c.demand_misses::cpu1.data 8604 # number of demand (read+write) misses 2804system.l2c.demand_misses::cpu1.l2cache.prefetcher 21015 # number of demand (read+write) misses 2805system.l2c.demand_misses::total 214589 # number of demand (read+write) misses 2806system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses 2807system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses 2808system.l2c.overall_misses::cpu0.inst 3728 # number of overall misses 2809system.l2c.overall_misses::cpu0.data 16424 # number of overall misses 2810system.l2c.overall_misses::cpu0.l2cache.prefetcher 164285 # number of overall misses 2811system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 2812system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 2813system.l2c.overall_misses::cpu1.inst 483 # number of overall misses 2814system.l2c.overall_misses::cpu1.data 8604 # number of overall misses 2815system.l2c.overall_misses::cpu1.l2cache.prefetcher 21015 # number of overall misses 2816system.l2c.overall_misses::total 214589 # number of overall misses 2817system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2728250 # number of ReadReq miss cycles 2818system.l2c.ReadReq_miss_latency::cpu0.itb.walker 375000 # number of ReadReq miss cycles 2819system.l2c.ReadReq_miss_latency::cpu0.inst 350452746 # number of ReadReq miss cycles 2820system.l2c.ReadReq_miss_latency::cpu0.data 764076744 # number of ReadReq miss cycles 2821system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of ReadReq miss cycles 2822system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 769500 # number of ReadReq miss cycles 2823system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 2824system.l2c.ReadReq_miss_latency::cpu1.inst 49625500 # number of ReadReq miss cycles 2825system.l2c.ReadReq_miss_latency::cpu1.data 122837500 # number of ReadReq miss cycles 2826system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of ReadReq miss cycles 2827system.l2c.ReadReq_miss_latency::total 22837051971 # number of ReadReq miss cycles 2828system.l2c.UpgradeReq_miss_latency::cpu0.data 6562735 # number of UpgradeReq miss cycles 2829system.l2c.UpgradeReq_miss_latency::cpu1.data 2836384 # number of UpgradeReq miss cycles 2830system.l2c.UpgradeReq_miss_latency::total 9399119 # number of UpgradeReq miss cycles 2831system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1040457 # number of SCUpgradeReq miss cycles 2832system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1019459 # number of SCUpgradeReq miss cycles 2833system.l2c.SCUpgradeReq_miss_latency::total 2059916 # number of SCUpgradeReq miss cycles 2834system.l2c.ReadExReq_miss_latency::cpu0.data 712108661 # number of ReadExReq miss cycles 2835system.l2c.ReadExReq_miss_latency::cpu1.data 561982732 # number of ReadExReq miss cycles 2836system.l2c.ReadExReq_miss_latency::total 1274091393 # number of ReadExReq miss cycles 2837system.l2c.demand_miss_latency::cpu0.dtb.walker 2728250 # number of demand (read+write) miss cycles 2838system.l2c.demand_miss_latency::cpu0.itb.walker 375000 # number of demand (read+write) miss cycles 2839system.l2c.demand_miss_latency::cpu0.inst 350452746 # number of demand (read+write) miss cycles 2840system.l2c.demand_miss_latency::cpu0.data 1476185405 # number of demand (read+write) miss cycles 2841system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of demand (read+write) miss cycles 2842system.l2c.demand_miss_latency::cpu1.dtb.walker 769500 # number of demand (read+write) miss cycles 2843system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles 2844system.l2c.demand_miss_latency::cpu1.inst 49625500 # number of demand (read+write) miss cycles 2845system.l2c.demand_miss_latency::cpu1.data 684820232 # number of demand (read+write) miss cycles 2846system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of demand (read+write) miss cycles 2847system.l2c.demand_miss_latency::total 24111143364 # number of demand (read+write) miss cycles 2848system.l2c.overall_miss_latency::cpu0.dtb.walker 2728250 # number of overall miss cycles 2849system.l2c.overall_miss_latency::cpu0.itb.walker 375000 # number of overall miss cycles 2850system.l2c.overall_miss_latency::cpu0.inst 350452746 # number of overall miss cycles 2851system.l2c.overall_miss_latency::cpu0.data 1476185405 # number of overall miss cycles 2852system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of overall miss cycles 2853system.l2c.overall_miss_latency::cpu1.dtb.walker 769500 # number of overall miss cycles 2854system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles 2855system.l2c.overall_miss_latency::cpu1.inst 49625500 # number of overall miss cycles 2856system.l2c.overall_miss_latency::cpu1.data 684820232 # number of overall miss cycles 2857system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of overall miss cycles 2858system.l2c.overall_miss_latency::total 24111143364 # number of overall miss cycles 2859system.l2c.ReadReq_accesses::cpu0.dtb.walker 306 # number of ReadReq accesses(hits+misses) 2860system.l2c.ReadReq_accesses::cpu0.itb.walker 138 # number of ReadReq accesses(hits+misses) 2861system.l2c.ReadReq_accesses::cpu0.inst 16282 # number of ReadReq accesses(hits+misses) 2862system.l2c.ReadReq_accesses::cpu0.data 47592 # number of ReadReq accesses(hits+misses) 2863system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346204 # number of ReadReq accesses(hits+misses) 2864system.l2c.ReadReq_accesses::cpu1.dtb.walker 94 # number of ReadReq accesses(hits+misses) 2865system.l2c.ReadReq_accesses::cpu1.itb.walker 49 # number of ReadReq accesses(hits+misses) 2866system.l2c.ReadReq_accesses::cpu1.inst 4626 # number of ReadReq accesses(hits+misses) 2867system.l2c.ReadReq_accesses::cpu1.data 12935 # number of ReadReq accesses(hits+misses) 2868system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65220 # number of ReadReq accesses(hits+misses) 2869system.l2c.ReadReq_accesses::total 493446 # number of ReadReq accesses(hits+misses) 2870system.l2c.Writeback_accesses::writebacks 252624 # number of Writeback accesses(hits+misses) 2871system.l2c.Writeback_accesses::total 252624 # number of Writeback accesses(hits+misses) 2872system.l2c.UpgradeReq_accesses::cpu0.data 20547 # number of UpgradeReq accesses(hits+misses) 2873system.l2c.UpgradeReq_accesses::cpu1.data 3573 # number of UpgradeReq accesses(hits+misses) 2874system.l2c.UpgradeReq_accesses::total 24120 # number of UpgradeReq accesses(hits+misses) 2875system.l2c.SCUpgradeReq_accesses::cpu0.data 930 # number of SCUpgradeReq accesses(hits+misses) 2876system.l2c.SCUpgradeReq_accesses::cpu1.data 1379 # number of SCUpgradeReq accesses(hits+misses) 2877system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) 2878system.l2c.ReadExReq_accesses::cpu0.data 11477 # number of ReadExReq accesses(hits+misses) 2879system.l2c.ReadExReq_accesses::cpu1.data 8445 # number of ReadExReq accesses(hits+misses) 2880system.l2c.ReadExReq_accesses::total 19922 # number of ReadExReq accesses(hits+misses) 2881system.l2c.demand_accesses::cpu0.dtb.walker 306 # number of demand (read+write) accesses 2882system.l2c.demand_accesses::cpu0.itb.walker 138 # number of demand (read+write) accesses 2883system.l2c.demand_accesses::cpu0.inst 16282 # number of demand (read+write) accesses 2884system.l2c.demand_accesses::cpu0.data 59069 # number of demand (read+write) accesses 2885system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346204 # number of demand (read+write) accesses 2886system.l2c.demand_accesses::cpu1.dtb.walker 94 # number of demand (read+write) accesses 2887system.l2c.demand_accesses::cpu1.itb.walker 49 # number of demand (read+write) accesses 2888system.l2c.demand_accesses::cpu1.inst 4626 # number of demand (read+write) accesses 2889system.l2c.demand_accesses::cpu1.data 21380 # number of demand (read+write) accesses 2890system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65220 # number of demand (read+write) accesses 2891system.l2c.demand_accesses::total 513368 # number of demand (read+write) accesses 2892system.l2c.overall_accesses::cpu0.dtb.walker 306 # number of overall (read+write) accesses 2893system.l2c.overall_accesses::cpu0.itb.walker 138 # number of overall (read+write) accesses 2894system.l2c.overall_accesses::cpu0.inst 16282 # number of overall (read+write) accesses 2895system.l2c.overall_accesses::cpu0.data 59069 # number of overall (read+write) accesses 2896system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346204 # number of overall (read+write) accesses 2897system.l2c.overall_accesses::cpu1.dtb.walker 94 # number of overall (read+write) accesses 2898system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses 2899system.l2c.overall_accesses::cpu1.inst 4626 # number of overall (read+write) accesses 2900system.l2c.overall_accesses::cpu1.data 21380 # number of overall (read+write) accesses 2901system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65220 # number of overall (read+write) accesses 2902system.l2c.overall_accesses::total 513368 # number of overall (read+write) accesses 2903system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for ReadReq accesses 2904system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.036232 # miss rate for ReadReq accesses 2905system.l2c.ReadReq_miss_rate::cpu0.inst 0.228965 # miss rate for ReadReq accesses 2906system.l2c.ReadReq_miss_rate::cpu0.data 0.181963 # miss rate for ReadReq accesses 2907system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474532 # miss rate for ReadReq accesses 2908system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.106383 # miss rate for ReadReq accesses 2909system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses 2910system.l2c.ReadReq_miss_rate::cpu1.inst 0.104410 # miss rate for ReadReq accesses 2911system.l2c.ReadReq_miss_rate::cpu1.data 0.107615 # miss rate for ReadReq accesses 2912system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.322217 # miss rate for ReadReq accesses 2913system.l2c.ReadReq_miss_rate::total 0.404529 # miss rate for ReadReq accesses 2914system.l2c.UpgradeReq_miss_rate::cpu0.data 0.430330 # miss rate for UpgradeReq accesses 2915system.l2c.UpgradeReq_miss_rate::cpu1.data 0.798489 # miss rate for UpgradeReq accesses 2916system.l2c.UpgradeReq_miss_rate::total 0.484867 # miss rate for UpgradeReq accesses 2917system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.805376 # miss rate for SCUpgradeReq accesses 2918system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.873822 # miss rate for SCUpgradeReq accesses 2919system.l2c.SCUpgradeReq_miss_rate::total 0.846254 # miss rate for SCUpgradeReq accesses 2920system.l2c.ReadExReq_miss_rate::cpu0.data 0.676483 # miss rate for ReadExReq accesses 2921system.l2c.ReadExReq_miss_rate::cpu1.data 0.853996 # miss rate for ReadExReq accesses 2922system.l2c.ReadExReq_miss_rate::total 0.751732 # miss rate for ReadExReq accesses 2923system.l2c.demand_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for demand accesses 2924system.l2c.demand_miss_rate::cpu0.itb.walker 0.036232 # miss rate for demand accesses 2925system.l2c.demand_miss_rate::cpu0.inst 0.228965 # miss rate for demand accesses 2926system.l2c.demand_miss_rate::cpu0.data 0.278048 # miss rate for demand accesses 2927system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474532 # miss rate for demand accesses 2928system.l2c.demand_miss_rate::cpu1.dtb.walker 0.106383 # miss rate for demand accesses 2929system.l2c.demand_miss_rate::cpu1.itb.walker 0.020408 # miss rate for demand accesses 2930system.l2c.demand_miss_rate::cpu1.inst 0.104410 # miss rate for demand accesses 2931system.l2c.demand_miss_rate::cpu1.data 0.402432 # miss rate for demand accesses 2932system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.322217 # miss rate for demand accesses 2933system.l2c.demand_miss_rate::total 0.418002 # miss rate for demand accesses 2934system.l2c.overall_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for overall accesses 2935system.l2c.overall_miss_rate::cpu0.itb.walker 0.036232 # miss rate for overall accesses 2936system.l2c.overall_miss_rate::cpu0.inst 0.228965 # miss rate for overall accesses 2937system.l2c.overall_miss_rate::cpu0.data 0.278048 # miss rate for overall accesses 2938system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474532 # miss rate for overall accesses 2939system.l2c.overall_miss_rate::cpu1.dtb.walker 0.106383 # miss rate for overall accesses 2940system.l2c.overall_miss_rate::cpu1.itb.walker 0.020408 # miss rate for overall accesses 2941system.l2c.overall_miss_rate::cpu1.inst 0.104410 # miss rate for overall accesses 2942system.l2c.overall_miss_rate::cpu1.data 0.402432 # miss rate for overall accesses 2943system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.322217 # miss rate for overall accesses 2944system.l2c.overall_miss_rate::total 0.418002 # miss rate for overall accesses 2945system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80242.647059 # average ReadReq miss latency 2946system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 2947system.l2c.ReadReq_avg_miss_latency::cpu0.inst 94005.564914 # average ReadReq miss latency 2948system.l2c.ReadReq_avg_miss_latency::cpu0.data 88230.570901 # average ReadReq miss latency 2949system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210 # average ReadReq miss latency 2950system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76950 # average ReadReq miss latency 2951system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 2952system.l2c.ReadReq_avg_miss_latency::cpu1.inst 102744.306418 # average ReadReq miss latency 2953system.l2c.ReadReq_avg_miss_latency::cpu1.data 88245.330460 # average ReadReq miss latency 2954system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041 # average ReadReq miss latency 2955system.l2c.ReadReq_avg_miss_latency::total 114406.636697 # average ReadReq miss latency 2956system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 742.222913 # average UpgradeReq miss latency 2957system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 994.175955 # average UpgradeReq miss latency 2958system.l2c.UpgradeReq_avg_miss_latency::total 803.686960 # average UpgradeReq miss latency 2959system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1389.128171 # average SCUpgradeReq miss latency 2960system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 846.024066 # average SCUpgradeReq miss latency 2961system.l2c.SCUpgradeReq_avg_miss_latency::total 1054.204708 # average SCUpgradeReq miss latency 2962system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91719.302035 # average ReadExReq miss latency 2963system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77923.285080 # average ReadExReq miss latency 2964system.l2c.ReadExReq_avg_miss_latency::total 85075.547075 # average ReadExReq miss latency 2965system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80242.647059 # average overall miss latency 2966system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2967system.l2c.demand_avg_miss_latency::cpu0.inst 94005.564914 # average overall miss latency 2968system.l2c.demand_avg_miss_latency::cpu0.data 89879.773807 # average overall miss latency 2969system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210 # average overall miss latency 2970system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76950 # average overall miss latency 2971system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 2972system.l2c.demand_avg_miss_latency::cpu1.inst 102744.306418 # average overall miss latency 2973system.l2c.demand_avg_miss_latency::cpu1.data 79593.239424 # average overall miss latency 2974system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041 # average overall miss latency 2975system.l2c.demand_avg_miss_latency::total 112359.642684 # average overall miss latency 2976system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80242.647059 # average overall miss latency 2977system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2978system.l2c.overall_avg_miss_latency::cpu0.inst 94005.564914 # average overall miss latency 2979system.l2c.overall_avg_miss_latency::cpu0.data 89879.773807 # average overall miss latency 2980system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115730.735210 # average overall miss latency 2981system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76950 # average overall miss latency 2982system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 2983system.l2c.overall_avg_miss_latency::cpu1.inst 102744.306418 # average overall miss latency 2984system.l2c.overall_avg_miss_latency::cpu1.data 79593.239424 # average overall miss latency 2985system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041 # average overall miss latency 2986system.l2c.overall_avg_miss_latency::total 112359.642684 # average overall miss latency 2987system.l2c.blocked_cycles::no_mshrs 853 # number of cycles access was blocked 2988system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2989system.l2c.blocked::no_mshrs 17 # number of cycles access was blocked 2990system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2991system.l2c.avg_blocked_cycles::no_mshrs 50.176471 # average number of cycles each access was blocked 2992system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2993system.l2c.fast_writes 0 # number of fast writes performed 2994system.l2c.cache_copies 0 # number of cache copies performed 2995system.l2c.writebacks::writebacks 113437 # number of writebacks 2996system.l2c.writebacks::total 113437 # number of writebacks 2997system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits 2998system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits 2999system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 3000system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 18 # number of ReadReq MSHR hits 3001system.l2c.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits 3002system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 3003system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits 3004system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 3005system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 18 # number of demand (read+write) MSHR hits 3006system.l2c.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 3007system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 3008system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits 3009system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 3010system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 18 # number of overall MSHR hits 3011system.l2c.overall_mshr_hits::total 24 # number of overall MSHR hits 3012system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 34 # number of ReadReq MSHR misses 3013system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses 3014system.l2c.ReadReq_mshr_misses::cpu0.inst 3728 # number of ReadReq MSHR misses 3015system.l2c.ReadReq_mshr_misses::cpu0.data 8659 # number of ReadReq MSHR misses 3016system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164282 # number of ReadReq MSHR misses 3017system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses 3018system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 3019system.l2c.ReadReq_mshr_misses::cpu1.inst 481 # number of ReadReq MSHR misses 3020system.l2c.ReadReq_mshr_misses::cpu1.data 1392 # number of ReadReq MSHR misses 3021system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20997 # number of ReadReq MSHR misses 3022system.l2c.ReadReq_mshr_misses::total 199589 # number of ReadReq MSHR misses 3023system.l2c.UpgradeReq_mshr_misses::cpu0.data 8842 # number of UpgradeReq MSHR misses 3024system.l2c.UpgradeReq_mshr_misses::cpu1.data 2853 # number of UpgradeReq MSHR misses 3025system.l2c.UpgradeReq_mshr_misses::total 11695 # number of UpgradeReq MSHR misses 3026system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 749 # number of SCUpgradeReq MSHR misses 3027system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1205 # number of SCUpgradeReq MSHR misses 3028system.l2c.SCUpgradeReq_mshr_misses::total 1954 # number of SCUpgradeReq MSHR misses 3029system.l2c.ReadExReq_mshr_misses::cpu0.data 7764 # number of ReadExReq MSHR misses 3030system.l2c.ReadExReq_mshr_misses::cpu1.data 7212 # number of ReadExReq MSHR misses 3031system.l2c.ReadExReq_mshr_misses::total 14976 # number of ReadExReq MSHR misses 3032system.l2c.demand_mshr_misses::cpu0.dtb.walker 34 # number of demand (read+write) MSHR misses 3033system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses 3034system.l2c.demand_mshr_misses::cpu0.inst 3728 # number of demand (read+write) MSHR misses 3035system.l2c.demand_mshr_misses::cpu0.data 16423 # number of demand (read+write) MSHR misses 3036system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164282 # number of demand (read+write) MSHR misses 3037system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses 3038system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3039system.l2c.demand_mshr_misses::cpu1.inst 481 # number of demand (read+write) MSHR misses 3040system.l2c.demand_mshr_misses::cpu1.data 8604 # number of demand (read+write) MSHR misses 3041system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20997 # number of demand (read+write) MSHR misses 3042system.l2c.demand_mshr_misses::total 214565 # number of demand (read+write) MSHR misses 3043system.l2c.overall_mshr_misses::cpu0.dtb.walker 34 # number of overall MSHR misses 3044system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses 3045system.l2c.overall_mshr_misses::cpu0.inst 3728 # number of overall MSHR misses 3046system.l2c.overall_mshr_misses::cpu0.data 16423 # number of overall MSHR misses 3047system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164282 # number of overall MSHR misses 3048system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses 3049system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3050system.l2c.overall_mshr_misses::cpu1.inst 481 # number of overall MSHR misses 3051system.l2c.overall_mshr_misses::cpu1.data 8604 # number of overall MSHR misses 3052system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 20997 # number of overall MSHR misses 3053system.l2c.overall_mshr_misses::total 214565 # number of overall MSHR misses 3054system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of ReadReq MSHR miss cycles 3055system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 312500 # number of ReadReq MSHR miss cycles 3056system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 304401246 # number of ReadReq MSHR miss cycles 3057system.l2c.ReadReq_mshr_miss_latency::cpu0.data 656530744 # number of ReadReq MSHR miss cycles 3058system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16993327084 # number of ReadReq MSHR miss cycles 3059system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 644500 # number of ReadReq MSHR miss cycles 3060system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 3061system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 43489500 # number of ReadReq MSHR miss cycles 3062system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105535000 # number of ReadReq MSHR miss cycles 3063system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2275742147 # number of ReadReq MSHR miss cycles 3064system.l2c.ReadReq_mshr_miss_latency::total 20382351471 # number of ReadReq MSHR miss cycles 3065system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 89515758 # number of UpgradeReq MSHR miss cycles 3066system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28874331 # number of UpgradeReq MSHR miss cycles 3067system.l2c.UpgradeReq_mshr_miss_latency::total 118390089 # number of UpgradeReq MSHR miss cycles 3068system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7686202 # number of SCUpgradeReq MSHR miss cycles 3069system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12118693 # number of SCUpgradeReq MSHR miss cycles 3070system.l2c.SCUpgradeReq_mshr_miss_latency::total 19804895 # number of SCUpgradeReq MSHR miss cycles 3071system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 616004335 # number of ReadExReq MSHR miss cycles 3072system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 470989766 # number of ReadExReq MSHR miss cycles 3073system.l2c.ReadExReq_mshr_miss_latency::total 1086994101 # number of ReadExReq MSHR miss cycles 3074system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of demand (read+write) MSHR miss cycles 3075system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 312500 # number of demand (read+write) MSHR miss cycles 3076system.l2c.demand_mshr_miss_latency::cpu0.inst 304401246 # number of demand (read+write) MSHR miss cycles 3077system.l2c.demand_mshr_miss_latency::cpu0.data 1272535079 # number of demand (read+write) MSHR miss cycles 3078system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16993327084 # number of demand (read+write) MSHR miss cycles 3079system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 644500 # number of demand (read+write) MSHR miss cycles 3080system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 3081system.l2c.demand_mshr_miss_latency::cpu1.inst 43489500 # number of demand (read+write) MSHR miss cycles 3082system.l2c.demand_mshr_miss_latency::cpu1.data 576524766 # number of demand (read+write) MSHR miss cycles 3083system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2275742147 # number of demand (read+write) MSHR miss cycles 3084system.l2c.demand_mshr_miss_latency::total 21469345572 # number of demand (read+write) MSHR miss cycles 3085system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles 3086system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 312500 # number of overall MSHR miss cycles 3087system.l2c.overall_mshr_miss_latency::cpu0.inst 304401246 # number of overall MSHR miss cycles 3088system.l2c.overall_mshr_miss_latency::cpu0.data 1272535079 # number of overall MSHR miss cycles 3089system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16993327084 # number of overall MSHR miss cycles 3090system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 644500 # number of overall MSHR miss cycles 3091system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles 3092system.l2c.overall_mshr_miss_latency::cpu1.inst 43489500 # number of overall MSHR miss cycles 3093system.l2c.overall_mshr_miss_latency::cpu1.data 576524766 # number of overall MSHR miss cycles 3094system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2275742147 # number of overall MSHR miss cycles 3095system.l2c.overall_mshr_miss_latency::total 21469345572 # number of overall MSHR miss cycles 3096system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles 3097system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686344747 # number of ReadReq MSHR uncacheable cycles 3098system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles 3099system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919845500 # number of ReadReq MSHR uncacheable cycles 3100system.l2c.ReadReq_mshr_uncacheable_latency::total 5770622747 # number of ReadReq MSHR uncacheable cycles 3101system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713919500 # number of WriteReq MSHR uncacheable cycles 3102system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535238000 # number of WriteReq MSHR uncacheable cycles 3103system.l2c.WriteReq_mshr_uncacheable_latency::total 4249157500 # number of WriteReq MSHR uncacheable cycles 3104system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles 3105system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400264247 # number of overall MSHR uncacheable cycles 3106system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles 3107system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455083500 # number of overall MSHR uncacheable cycles 3108system.l2c.overall_mshr_uncacheable_latency::total 10019780247 # number of overall MSHR uncacheable cycles 3109system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.111111 # mshr miss rate for ReadReq accesses 3110system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.036232 # mshr miss rate for ReadReq accesses 3111system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.228965 # mshr miss rate for ReadReq accesses 3112system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181942 # mshr miss rate for ReadReq accesses 3113system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for ReadReq accesses 3114system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for ReadReq accesses 3115system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses 3116system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for ReadReq accesses 3117system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.107615 # mshr miss rate for ReadReq accesses 3118system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for ReadReq accesses 3119system.l2c.ReadReq_mshr_miss_rate::total 0.404480 # mshr miss rate for ReadReq accesses 3120system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430330 # mshr miss rate for UpgradeReq accesses 3121system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.798489 # mshr miss rate for UpgradeReq accesses 3122system.l2c.UpgradeReq_mshr_miss_rate::total 0.484867 # mshr miss rate for UpgradeReq accesses 3123system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.805376 # mshr miss rate for SCUpgradeReq accesses 3124system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.873822 # mshr miss rate for SCUpgradeReq accesses 3125system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.846254 # mshr miss rate for SCUpgradeReq accesses 3126system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.676483 # mshr miss rate for ReadExReq accesses 3127system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853996 # mshr miss rate for ReadExReq accesses 3128system.l2c.ReadExReq_mshr_miss_rate::total 0.751732 # mshr miss rate for ReadExReq accesses 3129system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.111111 # mshr miss rate for demand accesses 3130system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036232 # mshr miss rate for demand accesses 3131system.l2c.demand_mshr_miss_rate::cpu0.inst 0.228965 # mshr miss rate for demand accesses 3132system.l2c.demand_mshr_miss_rate::cpu0.data 0.278031 # mshr miss rate for demand accesses 3133system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for demand accesses 3134system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for demand accesses 3135system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses 3136system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for demand accesses 3137system.l2c.demand_mshr_miss_rate::cpu1.data 0.402432 # mshr miss rate for demand accesses 3138system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for demand accesses 3139system.l2c.demand_mshr_miss_rate::total 0.417956 # mshr miss rate for demand accesses 3140system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.111111 # mshr miss rate for overall accesses 3141system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036232 # mshr miss rate for overall accesses 3142system.l2c.overall_mshr_miss_rate::cpu0.inst 0.228965 # mshr miss rate for overall accesses 3143system.l2c.overall_mshr_miss_rate::cpu0.data 0.278031 # mshr miss rate for overall accesses 3144system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for overall accesses 3145system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for overall accesses 3146system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses 3147system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for overall accesses 3148system.l2c.overall_mshr_miss_rate::cpu1.data 0.402432 # mshr miss rate for overall accesses 3149system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for overall accesses 3150system.l2c.overall_mshr_miss_rate::total 0.417956 # mshr miss rate for overall accesses 3151system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency 3152system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 3153system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average ReadReq mshr miss latency 3154system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75820.619471 # average ReadReq mshr miss latency 3155system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average ReadReq mshr miss latency 3156system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average ReadReq mshr miss latency 3157system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 3158system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average ReadReq mshr miss latency 3159system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75815.373563 # average ReadReq mshr miss latency 3160system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average ReadReq mshr miss latency 3161system.l2c.ReadReq_avg_mshr_miss_latency::total 102121.617279 # average ReadReq mshr miss latency 3162system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10123.926487 # average UpgradeReq mshr miss latency 3163system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10120.690852 # average UpgradeReq mshr miss latency 3164system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10123.137153 # average UpgradeReq mshr miss latency 3165system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10261.951936 # average SCUpgradeReq mshr miss latency 3166system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.006639 # average SCUpgradeReq mshr miss latency 3167system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10135.565507 # average SCUpgradeReq mshr miss latency 3168system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79341.104456 # average ReadExReq mshr miss latency 3169system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65306.401276 # average ReadExReq mshr miss latency 3170system.l2c.ReadExReq_avg_mshr_miss_latency::total 72582.405248 # average ReadExReq mshr miss latency 3171system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency 3172system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 3173system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency 3174system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency 3175system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency 3176system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency 3177system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 3178system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency 3179system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency 3180system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency 3181system.l2c.demand_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency 3182system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency 3183system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 3184system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency 3185system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency 3186system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency 3187system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency 3188system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 3189system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency 3190system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency 3191system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency 3192system.l2c.overall_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency 3193system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3194system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3195system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3196system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3197system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3198system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3199system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3200system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3201system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3202system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3203system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3204system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3205system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3206system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3207system.membus.trans_dist::ReadReq 237839 # Transaction distribution 3208system.membus.trans_dist::ReadResp 237839 # Transaction distribution 3209system.membus.trans_dist::WriteReq 30978 # Transaction distribution 3210system.membus.trans_dist::WriteResp 30978 # Transaction distribution 3211system.membus.trans_dist::Writeback 113437 # Transaction distribution 3212system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 3213system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 3214system.membus.trans_dist::UpgradeReq 79519 # Transaction distribution 3215system.membus.trans_dist::SCUpgradeReq 40695 # Transaction distribution 3216system.membus.trans_dist::UpgradeResp 13753 # Transaction distribution 3217system.membus.trans_dist::ReadExReq 31200 # Transaction distribution 3218system.membus.trans_dist::ReadExResp 14872 # Transaction distribution 3219system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) 3220system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 3221system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) 3222system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708866 # Packet count per connected master and slave (bytes) 3223system.membus.pkt_count_system.l2c.mem_side::total 830616 # Packet count per connected master and slave (bytes) 3224system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) 3225system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) 3226system.membus.pkt_count::total 903326 # Packet count per connected master and slave (bytes) 3227system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) 3228system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 3229system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) 3230system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21055004 # Cumulative packet size per connected master and slave (bytes) 3231system.membus.pkt_size_system.l2c.mem_side::total 21245656 # Cumulative packet size per connected master and slave (bytes) 3232system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 3233system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 3234system.membus.pkt_size::total 23564952 # Cumulative packet size per connected master and slave (bytes) 3235system.membus.snoops 123021 # Total snoops (count) 3236system.membus.snoop_fanout::samples 500917 # Request fanout histogram 3237system.membus.snoop_fanout::mean 1 # Request fanout histogram 3238system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3239system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3240system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3241system.membus.snoop_fanout::1 500917 100.00% 100.00% # Request fanout histogram 3242system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3243system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3244system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3245system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3246system.membus.snoop_fanout::total 500917 # Request fanout histogram 3247system.membus.reqLayer0.occupancy 81243492 # Layer occupancy (ticks) 3248system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3249system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) 3250system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3251system.membus.reqLayer2.occupancy 11638997 # Layer occupancy (ticks) 3252system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3253system.membus.reqLayer5.occupancy 1642210248 # Layer occupancy (ticks) 3254system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 3255system.membus.respLayer2.occupancy 2114152611 # Layer occupancy (ticks) 3256system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 3257system.membus.respLayer3.occupancy 38560639 # Layer occupancy (ticks) 3258system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3259system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3260system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3261system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3262system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3263system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3264system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3265system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3266system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3267system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3268system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3269system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3270system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3271system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3272system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3273system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3274system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3275system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3276system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3277system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3278system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3279system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3280system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3281system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3282system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3283system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3284system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3285system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3286system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3287system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3288system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3289system.realview.ethernet.droppedPackets 0 # number of packets dropped 3290system.toL2Bus.trans_dist::ReadReq 659694 # Transaction distribution 3291system.toL2Bus.trans_dist::ReadResp 659679 # Transaction distribution 3292system.toL2Bus.trans_dist::WriteReq 30978 # Transaction distribution 3293system.toL2Bus.trans_dist::WriteResp 30978 # Transaction distribution 3294system.toL2Bus.trans_dist::Writeback 252624 # Transaction distribution 3295system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution 3296system.toL2Bus.trans_dist::UpgradeReq 91840 # Transaction distribution 3297system.toL2Bus.trans_dist::SCUpgradeReq 41050 # Transaction distribution 3298system.toL2Bus.trans_dist::UpgradeResp 132890 # Transaction distribution 3299system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution 3300system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 3301system.toL2Bus.trans_dist::ReadExReq 40171 # Transaction distribution 3302system.toL2Bus.trans_dist::ReadExResp 40171 # Transaction distribution 3303system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1298541 # Packet count per connected master and slave (bytes) 3304system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426600 # Packet count per connected master and slave (bytes) 3305system.toL2Bus.pkt_count::total 1725141 # Packet count per connected master and slave (bytes) 3306system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40737982 # Cumulative packet size per connected master and slave (bytes) 3307system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8560538 # Cumulative packet size per connected master and slave (bytes) 3308system.toL2Bus.pkt_size::total 49298520 # Cumulative packet size per connected master and slave (bytes) 3309system.toL2Bus.snoops 291438 # Total snoops (count) 3310system.toL2Bus.snoop_fanout::samples 1083643 # Request fanout histogram 3311system.toL2Bus.snoop_fanout::mean 1.033661 # Request fanout histogram 3312system.toL2Bus.snoop_fanout::stdev 0.180356 # Request fanout histogram 3313system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3314system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3315system.toL2Bus.snoop_fanout::1 1047166 96.63% 96.63% # Request fanout histogram 3316system.toL2Bus.snoop_fanout::2 36477 3.37% 100.00% # Request fanout histogram 3317system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3318system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3319system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3320system.toL2Bus.snoop_fanout::total 1083643 # Request fanout histogram 3321system.toL2Bus.reqLayer0.occupancy 1586607093 # Layer occupancy (ticks) 3322system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 3323system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) 3324system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3325system.toL2Bus.respLayer0.occupancy 2272505602 # Layer occupancy (ticks) 3326system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 3327system.toL2Bus.respLayer1.occupancy 846502909 # Layer occupancy (ticks) 3328system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
|
| 3332system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 3329system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 3333system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed | 3330system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed |
| 3334system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3331system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 3335system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed | 3332system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed |
| 3336 3337---------- End Simulation Statistics ---------- | 3333 3334---------- End Simulation Statistics ---------- |