| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.607932 # Number of seconds simulated 4sim_ticks 2607931908500 # Number of ticks simulated 5final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.824356 # Number of seconds simulated 4sim_ticks 2824356167500 # Number of ticks simulated 5final_tick 2824356167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 52184 # Simulator instruction rate (inst/s) 8host_op_rate 62850 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2168410643 # Simulator tick rate (ticks/s) 10host_mem_usage 492092 # Number of bytes of host memory used 11host_seconds 1202.69 # Real time elapsed on the host 12sim_insts 62761278 # Number of instructions simulated 13sim_ops 75589768 # Number of ops (including micro ops) simulated | 7host_inst_rate 95847 # Simulator instruction rate (inst/s) 8host_op_rate 116283 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2253286315 # Simulator tick rate (ticks/s) 10host_mem_usage 605880 # Number of bytes of host memory used 11host_seconds 1253.44 # Real time elapsed on the host 12sim_insts 120137953 # Number of instructions simulated 13sim_ops 145753814 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory | 16system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 208 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 336 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 208 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 336 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 74 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 119 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 74 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 119 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 74 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 119 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory |
| 36system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory | 36system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory |
| 37system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory 43system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory 44system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory 45system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory 46system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory 47system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory 48system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory 49system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 50system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 51system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory 52system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory | 37system.physmem.bytes_read::cpu0.inst 286048 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 1048060 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu0.l2cache.prefetcher 10518784 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.inst 32848 # Number of bytes read from this memory 43system.physmem.bytes_read::cpu1.data 551328 # Number of bytes read from this memory 44system.physmem.bytes_read::cpu1.l2cache.prefetcher 1337024 # Number of bytes read from this memory 45system.physmem.bytes_read::total 13777996 # Number of bytes read from this memory 46system.physmem.bytes_inst_read::cpu0.inst 286048 # Number of instructions bytes read from this memory 47system.physmem.bytes_inst_read::cpu1.inst 32848 # Number of instructions bytes read from this memory 48system.physmem.bytes_inst_read::total 318896 # Number of instructions bytes read from this memory 49system.physmem.bytes_written::writebacks 7262976 # Number of bytes written to this memory 50system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 51system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 52system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 53system.physmem.bytes_written::total 9599056 # Number of bytes written to this memory 54system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory |
| 54system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory | 56system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory |
| 55system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory 60system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory 61system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory 62system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory 63system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory 64system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 65system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 66system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory 67system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s) 76system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s) 77system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s) 78system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s) 79system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s) 80system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s) 81system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) 83system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s) 84system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s) 85system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s) 94system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s) 95system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s) 96system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s) 97system.physmem.readReqs 15317443 # Number of read requests accepted 98system.physmem.writeReqs 825902 # Number of write requests accepted 99system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue 100system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue 101system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM 102system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue 103system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM 104system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side 105system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side 106system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue 107system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one 108system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write 109system.physmem.perBankRdBursts::0 957415 # Per bank write bursts 110system.physmem.perBankRdBursts::1 954356 # Per bank write bursts 111system.physmem.perBankRdBursts::2 951532 # Per bank write bursts 112system.physmem.perBankRdBursts::3 951095 # Per bank write bursts 113system.physmem.perBankRdBursts::4 960453 # Per bank write bursts 114system.physmem.perBankRdBursts::5 954333 # Per bank write bursts 115system.physmem.perBankRdBursts::6 950562 # Per bank write bursts 116system.physmem.perBankRdBursts::7 950350 # Per bank write bursts 117system.physmem.perBankRdBursts::8 957423 # Per bank write bursts 118system.physmem.perBankRdBursts::9 955252 # Per bank write bursts 119system.physmem.perBankRdBursts::10 950399 # Per bank write bursts 120system.physmem.perBankRdBursts::11 949996 # Per bank write bursts 121system.physmem.perBankRdBursts::12 957025 # Per bank write bursts 122system.physmem.perBankRdBursts::13 954231 # Per bank write bursts 123system.physmem.perBankRdBursts::14 950565 # Per bank write bursts 124system.physmem.perBankRdBursts::15 950154 # Per bank write bursts 125system.physmem.perBankWrBursts::0 7537 # Per bank write bursts 126system.physmem.perBankWrBursts::1 7271 # Per bank write bursts 127system.physmem.perBankWrBursts::2 7519 # Per bank write bursts 128system.physmem.perBankWrBursts::3 7339 # Per bank write bursts 129system.physmem.perBankWrBursts::4 7525 # Per bank write bursts 130system.physmem.perBankWrBursts::5 7506 # Per bank write bursts 131system.physmem.perBankWrBursts::6 7304 # Per bank write bursts 132system.physmem.perBankWrBursts::7 7173 # Per bank write bursts 133system.physmem.perBankWrBursts::8 7520 # Per bank write bursts 134system.physmem.perBankWrBursts::9 7613 # Per bank write bursts 135system.physmem.perBankWrBursts::10 6934 # Per bank write bursts 136system.physmem.perBankWrBursts::11 6533 # Per bank write bursts 137system.physmem.perBankWrBursts::12 7225 # Per bank write bursts 138system.physmem.perBankWrBursts::13 7011 # Per bank write bursts 139system.physmem.perBankWrBursts::14 7249 # Per bank write bursts 140system.physmem.perBankWrBursts::15 7053 # Per bank write bursts | 57system.physmem.num_reads::cpu0.inst 6715 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu0.data 16901 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu0.l2cache.prefetcher 164356 # Number of read requests responded to by this memory 60system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory 61system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 62system.physmem.num_reads::cpu1.inst 580 # Number of read requests responded to by this memory 63system.physmem.num_reads::cpu1.data 8638 # Number of read requests responded to by this memory 64system.physmem.num_reads::cpu1.l2cache.prefetcher 20891 # Number of read requests responded to by this memory 65system.physmem.num_reads::total 218142 # Number of read requests responded to by this memory 66system.physmem.num_writes::writebacks 113484 # Number of write requests responded to by this memory 67system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 68system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 69system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 70system.physmem.num_writes::total 154144 # Number of write requests responded to by this memory 71system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu0.dtb.walker 702 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_read::cpu0.inst 101279 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_read::cpu0.data 371079 # Total read bandwidth from this memory (bytes/s) 76system.physmem.bw_read::cpu0.l2cache.prefetcher 3724312 # Total read bandwidth from this memory (bytes/s) 77system.physmem.bw_read::cpu1.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) 78system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 79system.physmem.bw_read::cpu1.inst 11630 # Total read bandwidth from this memory (bytes/s) 80system.physmem.bw_read::cpu1.data 195205 # Total read bandwidth from this memory (bytes/s) 81system.physmem.bw_read::cpu1.l2cache.prefetcher 473391 # Total read bandwidth from this memory (bytes/s) 82system.physmem.bw_read::total 4878279 # Total read bandwidth from this memory (bytes/s) 83system.physmem.bw_inst_read::cpu0.inst 101279 # Instruction read bandwidth from this memory (bytes/s) 84system.physmem.bw_inst_read::cpu1.inst 11630 # Instruction read bandwidth from this memory (bytes/s) 85system.physmem.bw_inst_read::total 112909 # Instruction read bandwidth from this memory (bytes/s) 86system.physmem.bw_write::writebacks 2571551 # Write bandwidth from this memory (bytes/s) 87system.physmem.bw_write::realview.ide 820837 # Write bandwidth from this memory (bytes/s) 88system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) 89system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 90system.physmem.bw_write::total 3398671 # Write bandwidth from this memory (bytes/s) 91system.physmem.bw_total::writebacks 2571551 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::realview.ide 821177 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.bw_total::cpu0.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s) 94system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 95system.physmem.bw_total::cpu0.inst 101279 # Total bandwidth to/from this memory (bytes/s) 96system.physmem.bw_total::cpu0.data 377348 # Total bandwidth to/from this memory (bytes/s) 97system.physmem.bw_total::cpu0.l2cache.prefetcher 3724312 # Total bandwidth to/from this memory (bytes/s) 98system.physmem.bw_total::cpu1.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) 99system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 100system.physmem.bw_total::cpu1.inst 11630 # Total bandwidth to/from this memory (bytes/s) 101system.physmem.bw_total::cpu1.data 195219 # Total bandwidth to/from this memory (bytes/s) 102system.physmem.bw_total::cpu1.l2cache.prefetcher 473391 # Total bandwidth to/from this memory (bytes/s) 103system.physmem.bw_total::total 8276949 # Total bandwidth to/from this memory (bytes/s) 104system.physmem.readReqs 218142 # Number of read requests accepted 105system.physmem.writeReqs 154144 # Number of write requests accepted 106system.physmem.readBursts 218142 # Number of DRAM read bursts, including those serviced by the write queue 107system.physmem.writeBursts 154144 # Number of DRAM write bursts, including those merged in the write queue 108system.physmem.bytesReadDRAM 13946624 # Total number of bytes read from DRAM 109system.physmem.bytesReadWrQ 14464 # Total number of bytes read from write queue 110system.physmem.bytesWritten 9613440 # Total number of bytes written to DRAM 111system.physmem.bytesReadSys 13777996 # Total read bytes from the system interface side 112system.physmem.bytesWrittenSys 9599056 # Total written bytes from the system interface side 113system.physmem.servicedByWrQ 226 # Number of DRAM read bursts serviced by the write queue 114system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one 115system.physmem.neitherReadNorWriteReqs 13812 # Number of requests that are neither read nor write 116system.physmem.perBankRdBursts::0 13742 # Per bank write bursts 117system.physmem.perBankRdBursts::1 13629 # Per bank write bursts 118system.physmem.perBankRdBursts::2 14383 # Per bank write bursts 119system.physmem.perBankRdBursts::3 14277 # Per bank write bursts 120system.physmem.perBankRdBursts::4 15951 # Per bank write bursts 121system.physmem.perBankRdBursts::5 13005 # Per bank write bursts 122system.physmem.perBankRdBursts::6 13913 # Per bank write bursts 123system.physmem.perBankRdBursts::7 13901 # Per bank write bursts 124system.physmem.perBankRdBursts::8 13634 # Per bank write bursts 125system.physmem.perBankRdBursts::9 13374 # Per bank write bursts 126system.physmem.perBankRdBursts::10 12813 # Per bank write bursts 127system.physmem.perBankRdBursts::11 11699 # Per bank write bursts 128system.physmem.perBankRdBursts::12 13387 # Per bank write bursts 129system.physmem.perBankRdBursts::13 14173 # Per bank write bursts 130system.physmem.perBankRdBursts::14 13330 # Per bank write bursts 131system.physmem.perBankRdBursts::15 12705 # Per bank write bursts 132system.physmem.perBankWrBursts::0 9697 # Per bank write bursts 133system.physmem.perBankWrBursts::1 9775 # Per bank write bursts 134system.physmem.perBankWrBursts::2 10292 # Per bank write bursts 135system.physmem.perBankWrBursts::3 9920 # Per bank write bursts 136system.physmem.perBankWrBursts::4 9082 # Per bank write bursts 137system.physmem.perBankWrBursts::5 9049 # Per bank write bursts 138system.physmem.perBankWrBursts::6 9470 # Per bank write bursts 139system.physmem.perBankWrBursts::7 9454 # Per bank write bursts 140system.physmem.perBankWrBursts::8 9424 # Per bank write bursts 141system.physmem.perBankWrBursts::9 9315 # Per bank write bursts 142system.physmem.perBankWrBursts::10 9173 # Per bank write bursts 143system.physmem.perBankWrBursts::11 8636 # Per bank write bursts 144system.physmem.perBankWrBursts::12 9486 # Per bank write bursts 145system.physmem.perBankWrBursts::13 9567 # Per bank write bursts 146system.physmem.perBankWrBursts::14 9156 # Per bank write bursts 147system.physmem.perBankWrBursts::15 8714 # Per bank write bursts |
| 141system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 148system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 142system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 143system.physmem.totGap 2607930021000 # Total gap between requests | 149system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 150system.physmem.totGap 2824354558500 # Total gap between requests |
| 144system.physmem.readPktSize::0 0 # Read request sizes (log2) 145system.physmem.readPktSize::1 0 # Read request sizes (log2) | 151system.physmem.readPktSize::0 0 # Read request sizes (log2) 152system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 146system.physmem.readPktSize::2 59 # Read request sizes (log2) 147system.physmem.readPktSize::3 15138841 # Read request sizes (log2) 148system.physmem.readPktSize::4 3437 # Read request sizes (log2) | 153system.physmem.readPktSize::2 559 # Read request sizes (log2) 154system.physmem.readPktSize::3 28 # Read request sizes (log2) 155system.physmem.readPktSize::4 3083 # Read request sizes (log2) |
| 149system.physmem.readPktSize::5 0 # Read request sizes (log2) | 156system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 150system.physmem.readPktSize::6 175106 # Read request sizes (log2) | 157system.physmem.readPktSize::6 214472 # Read request sizes (log2) |
| 151system.physmem.writePktSize::0 0 # Write request sizes (log2) 152system.physmem.writePktSize::1 0 # Write request sizes (log2) | 158system.physmem.writePktSize::0 0 # Write request sizes (log2) 159system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| 153system.physmem.writePktSize::2 757284 # Write request sizes (log2) | 160system.physmem.writePktSize::2 4436 # Write request sizes (log2) |
| 154system.physmem.writePktSize::3 0 # Write request sizes (log2) 155system.physmem.writePktSize::4 0 # Write request sizes (log2) 156system.physmem.writePktSize::5 0 # Write request sizes (log2) | 161system.physmem.writePktSize::3 0 # Write request sizes (log2) 162system.physmem.writePktSize::4 0 # Write request sizes (log2) 163system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 157system.physmem.writePktSize::6 68618 # Write request sizes (log2) 158system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see 187system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see | 164system.physmem.writePktSize::6 149708 # Write request sizes (log2) 165system.physmem.rdQLenPdf::0 53602 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::1 76817 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::2 20742 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::3 15242 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::4 11051 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::5 9710 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::6 8839 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::7 8210 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::8 7163 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::9 2472 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::10 1433 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::12 621 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::13 437 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::14 277 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::15 206 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 187system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 190system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 191system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 192system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 193system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 194system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 195system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 196system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 190system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 197system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 205system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 246system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 247system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 248system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 249system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 250system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 251system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 252system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 253system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 254system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation 255system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation 256system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation 257system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation 258system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation 268system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes 269system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes 270system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes 271system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes 272system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes 273system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes 274system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes 275system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes 276system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes 277system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes 278system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads 298system.physmem.totQLat 400005056750 # Total ticks spent queuing 299system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst | 212system.physmem.wrQLenPdf::15 2929 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::17 4158 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::19 5623 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::20 6990 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::21 7782 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::22 8751 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::23 9680 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::24 10891 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::25 10789 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::26 10809 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::27 10760 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::28 11318 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::29 9435 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::30 9260 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::31 9292 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::32 8709 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::33 893 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::34 622 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::35 394 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::38 198 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::42 167 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see 246system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see 247system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see 248system.physmem.wrQLenPdf::51 46 # What write queue length does an incoming req see 249system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see 250system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see 251system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see 252system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see 253system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see 254system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see 255system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see 256system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see 257system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see 258system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 259system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see 260system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see 261system.physmem.bytesPerActivate::samples 92866 # Bytes accessed per row activation 262system.physmem.bytesPerActivate::mean 253.699567 # Bytes accessed per row activation 263system.physmem.bytesPerActivate::gmean 143.705803 # Bytes accessed per row activation 264system.physmem.bytesPerActivate::stdev 308.390709 # Bytes accessed per row activation 265system.physmem.bytesPerActivate::0-127 46941 50.55% 50.55% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::128-255 18915 20.37% 70.92% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::256-383 6813 7.34% 78.25% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::384-511 3565 3.84% 82.09% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::512-639 3222 3.47% 85.56% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::640-767 2153 2.32% 87.88% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::768-895 1230 1.32% 89.20% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::896-1023 1078 1.16% 90.36% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::1024-1151 8949 9.64% 100.00% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::total 92866 # Bytes accessed per row activation 275system.physmem.rdPerTurnAround::samples 7533 # Reads before turning the bus around for writes 276system.physmem.rdPerTurnAround::mean 28.928183 # Reads before turning the bus around for writes 277system.physmem.rdPerTurnAround::stdev 527.934330 # Reads before turning the bus around for writes 278system.physmem.rdPerTurnAround::0-2047 7532 99.99% 99.99% # Reads before turning the bus around for writes 279system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 280system.physmem.rdPerTurnAround::total 7533 # Reads before turning the bus around for writes 281system.physmem.wrPerTurnAround::samples 7533 # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::mean 19.940263 # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::gmean 18.639504 # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::stdev 10.756386 # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::16-19 6124 81.30% 81.30% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::20-23 560 7.43% 88.73% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::24-27 110 1.46% 90.19% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::28-31 221 2.93% 93.12% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::32-35 195 2.59% 95.71% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::36-39 21 0.28% 95.99% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::40-43 17 0.23% 96.22% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::44-47 21 0.28% 96.50% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::48-51 30 0.40% 96.89% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::56-59 3 0.04% 97.04% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::60-63 3 0.04% 97.08% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::64-67 162 2.15% 99.23% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::72-75 6 0.08% 99.40% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::76-79 5 0.07% 99.47% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::80-83 13 0.17% 99.64% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::88-91 1 0.01% 99.65% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::96-99 7 0.09% 99.76% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::100-103 2 0.03% 99.79% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::104-107 1 0.01% 99.80% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::108-111 1 0.01% 99.81% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::124-127 1 0.01% 99.89% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::128-131 3 0.04% 99.93% # Writes before turning the bus around for reads 312system.physmem.wrPerTurnAround::140-143 3 0.04% 99.97% # Writes before turning the bus around for reads 313system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads 314system.physmem.wrPerTurnAround::total 7533 # Writes before turning the bus around for reads 315system.physmem.totQLat 8921648500 # Total ticks spent queuing 316system.physmem.totMemAccLat 13007573500 # Total ticks spent from burst creation until serviced by the DRAM 317system.physmem.totBusLat 1089580000 # Total ticks spent in databus transfers 318system.physmem.avgQLat 40940.77 # Average queueing delay per DRAM burst |
| 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 319system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 303system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s | 320system.physmem.avgMemAccLat 59690.77 # Average memory access latency per DRAM burst 321system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s 322system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s 323system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s 324system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s |
| 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 325system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 309system.physmem.busUtil 2.95 # Data bus utilization in percentage 310system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads 311system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 312system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing 314system.physmem.readRowHits 14262971 # Number of row buffer hits during reads 315system.physmem.writeRowHits 87526 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes 318system.physmem.avgGap 161548.30 # Average gap between requests 319system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined 320system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states 321system.physmem.memoryStateTime::REF 87084400000 # Time in different power states | 326system.physmem.busUtil 0.07 # Data bus utilization in percentage 327system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 328system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 329system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing 330system.physmem.avgWrQLen 22.17 # Average write queue length when enqueuing 331system.physmem.readRowHits 185257 # Number of row buffer hits during reads 332system.physmem.writeRowHits 90003 # Number of row buffer hits during writes 333system.physmem.readRowHitRate 85.01 # Row buffer hit rate for reads 334system.physmem.writeRowHitRate 59.91 # Row buffer hit rate for writes 335system.physmem.avgGap 7586518.32 # Average gap between requests 336system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined 337system.physmem.memoryStateTime::IDLE 2697281054000 # Time in different power states 338system.physmem.memoryStateTime::REF 94311360000 # Time in different power states |
| 322system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 339system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 323system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states | 340system.physmem.memoryStateTime::ACT 32761026000 # Time in different power states |
| 324system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 341system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 325system.physmem.actEnergy::0 3862736640 # Energy for activate commands per rank (pJ) 326system.physmem.actEnergy::1 3855690720 # Energy for activate commands per rank (pJ) 327system.physmem.preEnergy::0 2107644000 # Energy for precharge commands per rank (pJ) 328system.physmem.preEnergy::1 2103799500 # Energy for precharge commands per rank (pJ) 329system.physmem.readEnergy::0 59514748800 # Energy for read commands per rank (pJ) 330system.physmem.readEnergy::1 59475351000 # Energy for read commands per rank (pJ) 331system.physmem.writeEnergy::0 383447520 # Energy for write commands per rank (pJ) 332system.physmem.writeEnergy::1 370254240 # Energy for write commands per rank (pJ) 333system.physmem.refreshEnergy::0 170337086400 # Energy for refresh commands per rank (pJ) 334system.physmem.refreshEnergy::1 170337086400 # Energy for refresh commands per rank (pJ) 335system.physmem.actBackEnergy::0 141921165285 # Energy for active background per rank (pJ) 336system.physmem.actBackEnergy::1 140687744850 # Energy for active background per rank (pJ) 337system.physmem.preBackEnergy::0 1440263842500 # Energy for precharge background per rank (pJ) 338system.physmem.preBackEnergy::1 1441345790250 # Energy for precharge background per rank (pJ) 339system.physmem.totalEnergy::0 1818390671145 # Total energy per rank (pJ) 340system.physmem.totalEnergy::1 1818175716960 # Total energy per rank (pJ) 341system.physmem.averagePower::0 697.255251 # Core power per rank (mW) 342system.physmem.averagePower::1 697.172828 # Core power per rank (mW) 343system.membus.trans_dist::ReadReq 16496763 # Transaction distribution 344system.membus.trans_dist::ReadResp 16496763 # Transaction distribution 345system.membus.trans_dist::WriteReq 769202 # Transaction distribution 346system.membus.trans_dist::WriteResp 769202 # Transaction distribution 347system.membus.trans_dist::Writeback 68618 # Transaction distribution 348system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution 349system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution 350system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution 351system.membus.trans_dist::ReadExReq 15703 # Transaction distribution 352system.membus.trans_dist::ReadExResp 8933 # Transaction distribution 353system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes) 354system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) 355system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes) 356system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 357system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) 358system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes) 359system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes) 360system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 361system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 362system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes) 363system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) 364system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) 365system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes) 366system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 367system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) 368system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes) 369system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes) 370system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 371system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 372system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes) 373system.membus.snoops 72850 # Total snoops (count) 374system.membus.snoop_fanout::samples 332577 # Request fanout histogram | 342system.physmem.actEnergy::0 364739760 # Energy for activate commands per rank (pJ) 343system.physmem.actEnergy::1 337327200 # Energy for activate commands per rank (pJ) 344system.physmem.preEnergy::0 199014750 # Energy for precharge commands per rank (pJ) 345system.physmem.preEnergy::1 184057500 # Energy for precharge commands per rank (pJ) 346system.physmem.readEnergy::0 879847800 # Energy for read commands per rank (pJ) 347system.physmem.readEnergy::1 819897000 # Energy for read commands per rank (pJ) 348system.physmem.writeEnergy::0 497268720 # Energy for write commands per rank (pJ) 349system.physmem.writeEnergy::1 476092080 # Energy for write commands per rank (pJ) 350system.physmem.refreshEnergy::0 184473020160 # Energy for refresh commands per rank (pJ) 351system.physmem.refreshEnergy::1 184473020160 # Energy for refresh commands per rank (pJ) 352system.physmem.actBackEnergy::0 78882264090 # Energy for active background per rank (pJ) 353system.physmem.actBackEnergy::1 78474830085 # Energy for active background per rank (pJ) 354system.physmem.preBackEnergy::0 1625417087250 # Energy for precharge background per rank (pJ) 355system.physmem.preBackEnergy::1 1625774485500 # Energy for precharge background per rank (pJ) 356system.physmem.totalEnergy::0 1890713242530 # Total energy per rank (pJ) 357system.physmem.totalEnergy::1 1890539709525 # Total energy per rank (pJ) 358system.physmem.averagePower::0 669.432241 # Core power per rank (mW) 359system.physmem.averagePower::1 669.370799 # Core power per rank (mW) 360system.membus.trans_dist::ReadReq 237803 # Transaction distribution 361system.membus.trans_dist::ReadResp 237803 # Transaction distribution 362system.membus.trans_dist::WriteReq 30981 # Transaction distribution 363system.membus.trans_dist::WriteResp 30981 # Transaction distribution 364system.membus.trans_dist::Writeback 113484 # Transaction distribution 365system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 366system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 367system.membus.trans_dist::UpgradeReq 79622 # Transaction distribution 368system.membus.trans_dist::SCUpgradeReq 40753 # Transaction distribution 369system.membus.trans_dist::UpgradeResp 13812 # Transaction distribution 370system.membus.trans_dist::ReadExReq 31225 # Transaction distribution 371system.membus.trans_dist::ReadExResp 14907 # Transaction distribution 372system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) 373system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 374system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13750 # Packet count per connected master and slave (bytes) 375system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 709115 # Packet count per connected master and slave (bytes) 376system.membus.pkt_count_system.l2c.mem_side::total 830877 # Packet count per connected master and slave (bytes) 377system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) 378system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) 379system.membus.pkt_count::total 903587 # Packet count per connected master and slave (bytes) 380system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) 381system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 336 # Cumulative packet size per connected master and slave (bytes) 382system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27500 # Cumulative packet size per connected master and slave (bytes) 383system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21057756 # Cumulative packet size per connected master and slave (bytes) 384system.membus.pkt_size_system.l2c.mem_side::total 21248442 # Cumulative packet size per connected master and slave (bytes) 385system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 386system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 387system.membus.pkt_size::total 23567738 # Cumulative packet size per connected master and slave (bytes) 388system.membus.snoops 123113 # Total snoops (count) 389system.membus.snoop_fanout::samples 501114 # Request fanout histogram |
| 375system.membus.snoop_fanout::mean 1 # Request fanout histogram 376system.membus.snoop_fanout::stdev 0 # Request fanout histogram 377system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 378system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 390system.membus.snoop_fanout::mean 1 # Request fanout histogram 391system.membus.snoop_fanout::stdev 0 # Request fanout histogram 392system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 393system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 379system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram | 394system.membus.snoop_fanout::1 501114 100.00% 100.00% # Request fanout histogram |
| 380system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 381system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 382system.membus.snoop_fanout::min_value 1 # Request fanout histogram 383system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 395system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 396system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 397system.membus.snoop_fanout::min_value 1 # Request fanout histogram 398system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 384system.membus.snoop_fanout::total 332577 # Request fanout histogram 385system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks) 386system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 387system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) | 399system.membus.snoop_fanout::total 501114 # Request fanout histogram 400system.membus.reqLayer0.occupancy 81319989 # Layer occupancy (ticks) 401system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 402system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) |
| 388system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 403system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 389system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks) | 404system.membus.reqLayer2.occupancy 11512493 # Layer occupancy (ticks) |
| 390system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 405system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 391system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 392system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 393system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks) 394system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 395system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks) 396system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 397system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks) 398system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 399system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks) 400system.membus.respLayer2.utilization 1.4 # Layer utilization (%) | 406system.membus.reqLayer5.occupancy 1643090249 # Layer occupancy (ticks) 407system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 408system.membus.respLayer2.occupancy 2114237552 # Layer occupancy (ticks) 409system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 410system.membus.respLayer3.occupancy 38543657 # Layer occupancy (ticks) 411system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 401system.cpu_clk_domain.clock 500 # Clock period in ticks | 412system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 402system.l2c.tags.replacements 91666 # number of replacements 403system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use 404system.l2c.tags.total_refs 387443 # Total number of references to valid blocks. 405system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks. 406system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks. | 413system.l2c.tags.replacements 153338 # number of replacements 414system.l2c.tags.tagsinuse 64407.351795 # Cycle average of tags in use 415system.l2c.tags.total_refs 520948 # Total number of references to valid blocks. 416system.l2c.tags.sampled_refs 218016 # Sample count of references to valid blocks. 417system.l2c.tags.avg_refs 2.389494 # Average number of references to valid blocks. |
| 407system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 418system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 408system.l2c.tags.occ_blocks::writebacks 7736.589041 # Average occupied blocks per requestor 409system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.331203 # Average occupied blocks per requestor 410system.l2c.tags.occ_blocks::cpu0.itb.walker 1.025467 # Average occupied blocks per requestor 411system.l2c.tags.occ_blocks::cpu0.inst 672.803532 # Average occupied blocks per requestor 412system.l2c.tags.occ_blocks::cpu0.data 1677.780077 # Average occupied blocks per requestor 413system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24285.244228 # Average occupied blocks per requestor 414system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.407687 # Average occupied blocks per requestor 415system.l2c.tags.occ_blocks::cpu1.inst 678.722766 # Average occupied blocks per requestor 416system.l2c.tags.occ_blocks::cpu1.data 3493.963497 # Average occupied blocks per requestor 417system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16278.332216 # Average occupied blocks per requestor 418system.l2c.tags.occ_percent::writebacks 0.118051 # Average percentage of cache occupancy 419system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy | 419system.l2c.tags.occ_blocks::writebacks 14039.109160 # Average occupied blocks per requestor 420system.l2c.tags.occ_blocks::cpu0.dtb.walker 10.926266 # Average occupied blocks per requestor 421system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063683 # Average occupied blocks per requestor 422system.l2c.tags.occ_blocks::cpu0.inst 1406.687456 # Average occupied blocks per requestor 423system.l2c.tags.occ_blocks::cpu0.data 2124.369402 # Average occupied blocks per requestor 424system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39350.084930 # Average occupied blocks per requestor 425system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.463090 # Average occupied blocks per requestor 426system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906491 # Average occupied blocks per requestor 427system.l2c.tags.occ_blocks::cpu1.inst 305.066680 # Average occupied blocks per requestor 428system.l2c.tags.occ_blocks::cpu1.data 911.182744 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6250.491894 # Average occupied blocks per requestor 430system.l2c.tags.occ_percent::writebacks 0.214220 # Average percentage of cache occupancy 431system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000167 # Average percentage of cache occupancy |
| 420system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy | 432system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy |
| 421system.l2c.tags.occ_percent::cpu0.inst 0.010266 # Average percentage of cache occupancy 422system.l2c.tags.occ_percent::cpu0.data 0.025601 # Average percentage of cache occupancy 423system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370563 # Average percentage of cache occupancy 424system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy 425system.l2c.tags.occ_percent::cpu1.inst 0.010356 # Average percentage of cache occupancy 426system.l2c.tags.occ_percent::cpu1.data 0.053314 # Average percentage of cache occupancy 427system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248388 # Average percentage of cache occupancy 428system.l2c.tags.occ_percent::total 0.836658 # Average percentage of cache occupancy 429system.l2c.tags.occ_task_id_blocks::1022 52524 # Occupied blocks per task id 430system.l2c.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 431system.l2c.tags.occ_task_id_blocks::1024 12291 # Occupied blocks per task id 432system.l2c.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id 433system.l2c.tags.age_task_id_blocks_1022::3 5897 # Occupied blocks per task id 434system.l2c.tags.age_task_id_blocks_1022::4 46469 # Occupied blocks per task id 435system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 436system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 437system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 438system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id 439system.l2c.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id 440system.l2c.tags.age_task_id_blocks_1024::3 2272 # Occupied blocks per task id 441system.l2c.tags.age_task_id_blocks_1024::4 9679 # Occupied blocks per task id 442system.l2c.tags.occ_task_id_percent::1022 0.801453 # Percentage of cache occupancy per task id 443system.l2c.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id 444system.l2c.tags.occ_task_id_percent::1024 0.187546 # Percentage of cache occupancy per task id 445system.l2c.tags.tag_accesses 5049935 # Number of tag accesses 446system.l2c.tags.data_accesses 5049935 # Number of data accesses 447system.l2c.ReadReq_hits::cpu0.dtb.walker 116 # number of ReadReq hits 448system.l2c.ReadReq_hits::cpu0.itb.walker 44 # number of ReadReq hits 449system.l2c.ReadReq_hits::cpu0.inst 4746 # number of ReadReq hits 450system.l2c.ReadReq_hits::cpu0.data 14884 # number of ReadReq hits 451system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72204 # number of ReadReq hits 452system.l2c.ReadReq_hits::cpu1.dtb.walker 168 # number of ReadReq hits 453system.l2c.ReadReq_hits::cpu1.itb.walker 72 # number of ReadReq hits 454system.l2c.ReadReq_hits::cpu1.inst 7407 # number of ReadReq hits 455system.l2c.ReadReq_hits::cpu1.data 16636 # number of ReadReq hits 456system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 74707 # number of ReadReq hits 457system.l2c.ReadReq_hits::total 190984 # number of ReadReq hits 458system.l2c.Writeback_hits::writebacks 213987 # number of Writeback hits 459system.l2c.Writeback_hits::total 213987 # number of Writeback hits 460system.l2c.UpgradeReq_hits::cpu0.data 3107 # number of UpgradeReq hits 461system.l2c.UpgradeReq_hits::cpu1.data 2045 # number of UpgradeReq hits 462system.l2c.UpgradeReq_hits::total 5152 # number of UpgradeReq hits 463system.l2c.SCUpgradeReq_hits::cpu0.data 90 # number of SCUpgradeReq hits 464system.l2c.SCUpgradeReq_hits::cpu1.data 245 # number of SCUpgradeReq hits 465system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits 466system.l2c.ReadExReq_hits::cpu0.data 1803 # number of ReadExReq hits 467system.l2c.ReadExReq_hits::cpu1.data 2746 # number of ReadExReq hits 468system.l2c.ReadExReq_hits::total 4549 # number of ReadExReq hits 469system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits 470system.l2c.demand_hits::cpu0.itb.walker 44 # number of demand (read+write) hits 471system.l2c.demand_hits::cpu0.inst 4746 # number of demand (read+write) hits 472system.l2c.demand_hits::cpu0.data 16687 # number of demand (read+write) hits 473system.l2c.demand_hits::cpu0.l2cache.prefetcher 72204 # number of demand (read+write) hits 474system.l2c.demand_hits::cpu1.dtb.walker 168 # number of demand (read+write) hits 475system.l2c.demand_hits::cpu1.itb.walker 72 # number of demand (read+write) hits 476system.l2c.demand_hits::cpu1.inst 7407 # number of demand (read+write) hits 477system.l2c.demand_hits::cpu1.data 19382 # number of demand (read+write) hits 478system.l2c.demand_hits::cpu1.l2cache.prefetcher 74707 # number of demand (read+write) hits 479system.l2c.demand_hits::total 195533 # number of demand (read+write) hits 480system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits 481system.l2c.overall_hits::cpu0.itb.walker 44 # number of overall hits 482system.l2c.overall_hits::cpu0.inst 4746 # number of overall hits 483system.l2c.overall_hits::cpu0.data 16687 # number of overall hits 484system.l2c.overall_hits::cpu0.l2cache.prefetcher 72204 # number of overall hits 485system.l2c.overall_hits::cpu1.dtb.walker 168 # number of overall hits 486system.l2c.overall_hits::cpu1.itb.walker 72 # number of overall hits 487system.l2c.overall_hits::cpu1.inst 7407 # number of overall hits 488system.l2c.overall_hits::cpu1.data 19382 # number of overall hits 489system.l2c.overall_hits::cpu1.l2cache.prefetcher 74707 # number of overall hits 490system.l2c.overall_hits::total 195533 # number of overall hits 491system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses | 433system.l2c.tags.occ_percent::cpu0.inst 0.021464 # Average percentage of cache occupancy 434system.l2c.tags.occ_percent::cpu0.data 0.032415 # Average percentage of cache occupancy 435system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.600435 # Average percentage of cache occupancy 436system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000114 # Average percentage of cache occupancy 437system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::cpu1.inst 0.004655 # Average percentage of cache occupancy 439system.l2c.tags.occ_percent::cpu1.data 0.013904 # Average percentage of cache occupancy 440system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.095375 # Average percentage of cache occupancy 441system.l2c.tags.occ_percent::total 0.982778 # Average percentage of cache occupancy 442system.l2c.tags.occ_task_id_blocks::1022 44311 # Occupied blocks per task id 443system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 444system.l2c.tags.occ_task_id_blocks::1024 20347 # Occupied blocks per task id 445system.l2c.tags.age_task_id_blocks_1022::2 406 # Occupied blocks per task id 446system.l2c.tags.age_task_id_blocks_1022::3 7760 # Occupied blocks per task id 447system.l2c.tags.age_task_id_blocks_1022::4 36145 # Occupied blocks per task id 448system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 449system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id 450system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 451system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 452system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id 453system.l2c.tags.age_task_id_blocks_1024::3 4612 # Occupied blocks per task id 454system.l2c.tags.age_task_id_blocks_1024::4 15362 # Occupied blocks per task id 455system.l2c.tags.occ_task_id_percent::1022 0.676132 # Percentage of cache occupancy per task id 456system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id 457system.l2c.tags.occ_task_id_percent::1024 0.310471 # Percentage of cache occupancy per task id 458system.l2c.tags.tag_accesses 6600636 # Number of tag accesses 459system.l2c.tags.data_accesses 6600636 # Number of data accesses 460system.l2c.ReadReq_hits::cpu0.dtb.walker 292 # number of ReadReq hits 461system.l2c.ReadReq_hits::cpu0.itb.walker 154 # number of ReadReq hits 462system.l2c.ReadReq_hits::cpu0.inst 12492 # number of ReadReq hits 463system.l2c.ReadReq_hits::cpu0.data 39083 # number of ReadReq hits 464system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182457 # number of ReadReq hits 465system.l2c.ReadReq_hits::cpu1.dtb.walker 82 # number of ReadReq hits 466system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits 467system.l2c.ReadReq_hits::cpu1.inst 4094 # number of ReadReq hits 468system.l2c.ReadReq_hits::cpu1.data 11500 # number of ReadReq hits 469system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44186 # number of ReadReq hits 470system.l2c.ReadReq_hits::total 294388 # number of ReadReq hits 471system.l2c.Writeback_hits::writebacks 252842 # number of Writeback hits 472system.l2c.Writeback_hits::total 252842 # number of Writeback hits 473system.l2c.UpgradeReq_hits::cpu0.data 11706 # number of UpgradeReq hits 474system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits 475system.l2c.UpgradeReq_hits::total 12433 # number of UpgradeReq hits 476system.l2c.SCUpgradeReq_hits::cpu0.data 197 # number of SCUpgradeReq hits 477system.l2c.SCUpgradeReq_hits::cpu1.data 154 # number of SCUpgradeReq hits 478system.l2c.SCUpgradeReq_hits::total 351 # number of SCUpgradeReq hits 479system.l2c.ReadExReq_hits::cpu0.data 3674 # number of ReadExReq hits 480system.l2c.ReadExReq_hits::cpu1.data 1157 # number of ReadExReq hits 481system.l2c.ReadExReq_hits::total 4831 # number of ReadExReq hits 482system.l2c.demand_hits::cpu0.dtb.walker 292 # number of demand (read+write) hits 483system.l2c.demand_hits::cpu0.itb.walker 154 # number of demand (read+write) hits 484system.l2c.demand_hits::cpu0.inst 12492 # number of demand (read+write) hits 485system.l2c.demand_hits::cpu0.data 42757 # number of demand (read+write) hits 486system.l2c.demand_hits::cpu0.l2cache.prefetcher 182457 # number of demand (read+write) hits 487system.l2c.demand_hits::cpu1.dtb.walker 82 # number of demand (read+write) hits 488system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits 489system.l2c.demand_hits::cpu1.inst 4094 # number of demand (read+write) hits 490system.l2c.demand_hits::cpu1.data 12657 # number of demand (read+write) hits 491system.l2c.demand_hits::cpu1.l2cache.prefetcher 44186 # number of demand (read+write) hits 492system.l2c.demand_hits::total 299219 # number of demand (read+write) hits 493system.l2c.overall_hits::cpu0.dtb.walker 292 # number of overall hits 494system.l2c.overall_hits::cpu0.itb.walker 154 # number of overall hits 495system.l2c.overall_hits::cpu0.inst 12492 # number of overall hits 496system.l2c.overall_hits::cpu0.data 42757 # number of overall hits 497system.l2c.overall_hits::cpu0.l2cache.prefetcher 182457 # number of overall hits 498system.l2c.overall_hits::cpu1.dtb.walker 82 # number of overall hits 499system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits 500system.l2c.overall_hits::cpu1.inst 4094 # number of overall hits 501system.l2c.overall_hits::cpu1.data 12657 # number of overall hits 502system.l2c.overall_hits::cpu1.l2cache.prefetcher 44186 # number of overall hits 503system.l2c.overall_hits::total 299219 # number of overall hits 504system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses |
| 492system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses | 505system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses |
| 493system.l2c.ReadReq_misses::cpu0.inst 1063 # number of ReadReq misses 494system.l2c.ReadReq_misses::cpu0.data 3259 # number of ReadReq misses 495system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq misses 496system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses 497system.l2c.ReadReq_misses::cpu1.inst 1104 # number of ReadReq misses 498system.l2c.ReadReq_misses::cpu1.data 4621 # number of ReadReq misses 499system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq misses 500system.l2c.ReadReq_misses::total 166173 # number of ReadReq misses 501system.l2c.UpgradeReq_misses::cpu0.data 7830 # number of UpgradeReq misses 502system.l2c.UpgradeReq_misses::cpu1.data 5610 # number of UpgradeReq misses 503system.l2c.UpgradeReq_misses::total 13440 # number of UpgradeReq misses 504system.l2c.SCUpgradeReq_misses::cpu0.data 1272 # number of SCUpgradeReq misses 505system.l2c.SCUpgradeReq_misses::cpu1.data 1187 # number of SCUpgradeReq misses 506system.l2c.SCUpgradeReq_misses::total 2459 # number of SCUpgradeReq misses 507system.l2c.ReadExReq_misses::cpu0.data 3945 # number of ReadExReq misses 508system.l2c.ReadExReq_misses::cpu1.data 5092 # number of ReadExReq misses 509system.l2c.ReadExReq_misses::total 9037 # number of ReadExReq misses 510system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses | 506system.l2c.ReadReq_misses::cpu0.inst 3722 # number of ReadReq misses 507system.l2c.ReadReq_misses::cpu0.data 8649 # number of ReadReq misses 508system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164359 # number of ReadReq misses 509system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses 510system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 511system.l2c.ReadReq_misses::cpu1.inst 492 # number of ReadReq misses 512system.l2c.ReadReq_misses::cpu1.data 1396 # number of ReadReq misses 513system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 20906 # number of ReadReq misses 514system.l2c.ReadReq_misses::total 199570 # number of ReadReq misses 515system.l2c.UpgradeReq_misses::cpu0.data 8911 # number of UpgradeReq misses 516system.l2c.UpgradeReq_misses::cpu1.data 2815 # number of UpgradeReq misses 517system.l2c.UpgradeReq_misses::total 11726 # number of UpgradeReq misses 518system.l2c.SCUpgradeReq_misses::cpu0.data 768 # number of SCUpgradeReq misses 519system.l2c.SCUpgradeReq_misses::cpu1.data 1215 # number of SCUpgradeReq misses 520system.l2c.SCUpgradeReq_misses::total 1983 # number of SCUpgradeReq misses 521system.l2c.ReadExReq_misses::cpu0.data 7775 # number of ReadExReq misses 522system.l2c.ReadExReq_misses::cpu1.data 7235 # number of ReadExReq misses 523system.l2c.ReadExReq_misses::total 15010 # number of ReadExReq misses 524system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses |
| 511system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses | 525system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses |
| 512system.l2c.demand_misses::cpu0.inst 1063 # number of demand (read+write) misses 513system.l2c.demand_misses::cpu0.data 7204 # number of demand (read+write) misses 514system.l2c.demand_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) misses 515system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses 516system.l2c.demand_misses::cpu1.inst 1104 # number of demand (read+write) misses 517system.l2c.demand_misses::cpu1.data 9713 # number of demand (read+write) misses 518system.l2c.demand_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) misses 519system.l2c.demand_misses::total 175210 # number of demand (read+write) misses 520system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses | 526system.l2c.demand_misses::cpu0.inst 3722 # number of demand (read+write) misses 527system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses 528system.l2c.demand_misses::cpu0.l2cache.prefetcher 164359 # number of demand (read+write) misses 529system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses 530system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 531system.l2c.demand_misses::cpu1.inst 492 # number of demand (read+write) misses 532system.l2c.demand_misses::cpu1.data 8631 # number of demand (read+write) misses 533system.l2c.demand_misses::cpu1.l2cache.prefetcher 20906 # number of demand (read+write) misses 534system.l2c.demand_misses::total 214580 # number of demand (read+write) misses 535system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses |
| 521system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses | 536system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses |
| 522system.l2c.overall_misses::cpu0.inst 1063 # number of overall misses 523system.l2c.overall_misses::cpu0.data 7204 # number of overall misses 524system.l2c.overall_misses::cpu0.l2cache.prefetcher 72015 # number of overall misses 525system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses 526system.l2c.overall_misses::cpu1.inst 1104 # number of overall misses 527system.l2c.overall_misses::cpu1.data 9713 # number of overall misses 528system.l2c.overall_misses::cpu1.l2cache.prefetcher 84097 # number of overall misses 529system.l2c.overall_misses::total 175210 # number of overall misses 530system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195250 # number of ReadReq miss cycles 531system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182000 # number of ReadReq miss cycles 532system.l2c.ReadReq_miss_latency::cpu0.inst 88517249 # number of ReadReq miss cycles 533system.l2c.ReadReq_miss_latency::cpu0.data 251848999 # number of ReadReq miss cycles 534system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of ReadReq miss cycles 535system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 744500 # number of ReadReq miss cycles 536system.l2c.ReadReq_miss_latency::cpu1.inst 96486500 # number of ReadReq miss cycles 537system.l2c.ReadReq_miss_latency::cpu1.data 359268498 # number of ReadReq miss cycles 538system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of ReadReq miss cycles 539system.l2c.ReadReq_miss_latency::total 17143743646 # number of ReadReq miss cycles 540system.l2c.UpgradeReq_miss_latency::cpu0.data 12214974 # number of UpgradeReq miss cycles 541system.l2c.UpgradeReq_miss_latency::cpu1.data 6369731 # number of UpgradeReq miss cycles 542system.l2c.UpgradeReq_miss_latency::total 18584705 # number of UpgradeReq miss cycles 543system.l2c.SCUpgradeReq_miss_latency::cpu0.data 508980 # number of SCUpgradeReq miss cycles 544system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4358314 # number of SCUpgradeReq miss cycles 545system.l2c.SCUpgradeReq_miss_latency::total 4867294 # number of SCUpgradeReq miss cycles 546system.l2c.ReadExReq_miss_latency::cpu0.data 294129193 # number of ReadExReq miss cycles 547system.l2c.ReadExReq_miss_latency::cpu1.data 380271953 # number of ReadExReq miss cycles 548system.l2c.ReadExReq_miss_latency::total 674401146 # number of ReadExReq miss cycles 549system.l2c.demand_miss_latency::cpu0.dtb.walker 195250 # number of demand (read+write) miss cycles 550system.l2c.demand_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) miss cycles 551system.l2c.demand_miss_latency::cpu0.inst 88517249 # number of demand (read+write) miss cycles 552system.l2c.demand_miss_latency::cpu0.data 545978192 # number of demand (read+write) miss cycles 553system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of demand (read+write) miss cycles 554system.l2c.demand_miss_latency::cpu1.dtb.walker 744500 # number of demand (read+write) miss cycles 555system.l2c.demand_miss_latency::cpu1.inst 96486500 # number of demand (read+write) miss cycles 556system.l2c.demand_miss_latency::cpu1.data 739540451 # number of demand (read+write) miss cycles 557system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of demand (read+write) miss cycles 558system.l2c.demand_miss_latency::total 17818144792 # number of demand (read+write) miss cycles 559system.l2c.overall_miss_latency::cpu0.dtb.walker 195250 # number of overall miss cycles 560system.l2c.overall_miss_latency::cpu0.itb.walker 182000 # number of overall miss cycles 561system.l2c.overall_miss_latency::cpu0.inst 88517249 # number of overall miss cycles 562system.l2c.overall_miss_latency::cpu0.data 545978192 # number of overall miss cycles 563system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of overall miss cycles 564system.l2c.overall_miss_latency::cpu1.dtb.walker 744500 # number of overall miss cycles 565system.l2c.overall_miss_latency::cpu1.inst 96486500 # number of overall miss cycles 566system.l2c.overall_miss_latency::cpu1.data 739540451 # number of overall miss cycles 567system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of overall miss cycles 568system.l2c.overall_miss_latency::total 17818144792 # number of overall miss cycles 569system.l2c.ReadReq_accesses::cpu0.dtb.walker 119 # number of ReadReq accesses(hits+misses) 570system.l2c.ReadReq_accesses::cpu0.itb.walker 47 # number of ReadReq accesses(hits+misses) 571system.l2c.ReadReq_accesses::cpu0.inst 5809 # number of ReadReq accesses(hits+misses) 572system.l2c.ReadReq_accesses::cpu0.data 18143 # number of ReadReq accesses(hits+misses) 573system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144219 # number of ReadReq accesses(hits+misses) 574system.l2c.ReadReq_accesses::cpu1.dtb.walker 176 # number of ReadReq accesses(hits+misses) 575system.l2c.ReadReq_accesses::cpu1.itb.walker 72 # number of ReadReq accesses(hits+misses) 576system.l2c.ReadReq_accesses::cpu1.inst 8511 # number of ReadReq accesses(hits+misses) 577system.l2c.ReadReq_accesses::cpu1.data 21257 # number of ReadReq accesses(hits+misses) 578system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 158804 # number of ReadReq accesses(hits+misses) 579system.l2c.ReadReq_accesses::total 357157 # number of ReadReq accesses(hits+misses) 580system.l2c.Writeback_accesses::writebacks 213987 # number of Writeback accesses(hits+misses) 581system.l2c.Writeback_accesses::total 213987 # number of Writeback accesses(hits+misses) 582system.l2c.UpgradeReq_accesses::cpu0.data 10937 # number of UpgradeReq accesses(hits+misses) 583system.l2c.UpgradeReq_accesses::cpu1.data 7655 # number of UpgradeReq accesses(hits+misses) 584system.l2c.UpgradeReq_accesses::total 18592 # number of UpgradeReq accesses(hits+misses) 585system.l2c.SCUpgradeReq_accesses::cpu0.data 1362 # number of SCUpgradeReq accesses(hits+misses) 586system.l2c.SCUpgradeReq_accesses::cpu1.data 1432 # number of SCUpgradeReq accesses(hits+misses) 587system.l2c.SCUpgradeReq_accesses::total 2794 # number of SCUpgradeReq accesses(hits+misses) 588system.l2c.ReadExReq_accesses::cpu0.data 5748 # number of ReadExReq accesses(hits+misses) 589system.l2c.ReadExReq_accesses::cpu1.data 7838 # number of ReadExReq accesses(hits+misses) 590system.l2c.ReadExReq_accesses::total 13586 # number of ReadExReq accesses(hits+misses) 591system.l2c.demand_accesses::cpu0.dtb.walker 119 # number of demand (read+write) accesses 592system.l2c.demand_accesses::cpu0.itb.walker 47 # number of demand (read+write) accesses 593system.l2c.demand_accesses::cpu0.inst 5809 # number of demand (read+write) accesses 594system.l2c.demand_accesses::cpu0.data 23891 # number of demand (read+write) accesses 595system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144219 # number of demand (read+write) accesses 596system.l2c.demand_accesses::cpu1.dtb.walker 176 # number of demand (read+write) accesses 597system.l2c.demand_accesses::cpu1.itb.walker 72 # number of demand (read+write) accesses 598system.l2c.demand_accesses::cpu1.inst 8511 # number of demand (read+write) accesses 599system.l2c.demand_accesses::cpu1.data 29095 # number of demand (read+write) accesses 600system.l2c.demand_accesses::cpu1.l2cache.prefetcher 158804 # number of demand (read+write) accesses 601system.l2c.demand_accesses::total 370743 # number of demand (read+write) accesses 602system.l2c.overall_accesses::cpu0.dtb.walker 119 # number of overall (read+write) accesses 603system.l2c.overall_accesses::cpu0.itb.walker 47 # number of overall (read+write) accesses 604system.l2c.overall_accesses::cpu0.inst 5809 # number of overall (read+write) accesses 605system.l2c.overall_accesses::cpu0.data 23891 # number of overall (read+write) accesses 606system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144219 # number of overall (read+write) accesses 607system.l2c.overall_accesses::cpu1.dtb.walker 176 # number of overall (read+write) accesses 608system.l2c.overall_accesses::cpu1.itb.walker 72 # number of overall (read+write) accesses 609system.l2c.overall_accesses::cpu1.inst 8511 # number of overall (read+write) accesses 610system.l2c.overall_accesses::cpu1.data 29095 # number of overall (read+write) accesses 611system.l2c.overall_accesses::cpu1.l2cache.prefetcher 158804 # number of overall (read+write) accesses 612system.l2c.overall_accesses::total 370743 # number of overall (read+write) accesses 613system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for ReadReq accesses 614system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.063830 # miss rate for ReadReq accesses 615system.l2c.ReadReq_miss_rate::cpu0.inst 0.182992 # miss rate for ReadReq accesses 616system.l2c.ReadReq_miss_rate::cpu0.data 0.179629 # miss rate for ReadReq accesses 617system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for ReadReq accesses 618system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses 619system.l2c.ReadReq_miss_rate::cpu1.inst 0.129714 # miss rate for ReadReq accesses 620system.l2c.ReadReq_miss_rate::cpu1.data 0.217387 # miss rate for ReadReq accesses 621system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for ReadReq accesses 622system.l2c.ReadReq_miss_rate::total 0.465266 # miss rate for ReadReq accesses 623system.l2c.UpgradeReq_miss_rate::cpu0.data 0.715918 # miss rate for UpgradeReq accesses 624system.l2c.UpgradeReq_miss_rate::cpu1.data 0.732854 # miss rate for UpgradeReq accesses 625system.l2c.UpgradeReq_miss_rate::total 0.722892 # miss rate for UpgradeReq accesses 626system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.933921 # miss rate for SCUpgradeReq accesses 627system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828911 # miss rate for SCUpgradeReq accesses 628system.l2c.SCUpgradeReq_miss_rate::total 0.880100 # miss rate for SCUpgradeReq accesses 629system.l2c.ReadExReq_miss_rate::cpu0.data 0.686326 # miss rate for ReadExReq accesses 630system.l2c.ReadExReq_miss_rate::cpu1.data 0.649656 # miss rate for ReadExReq accesses 631system.l2c.ReadExReq_miss_rate::total 0.665170 # miss rate for ReadExReq accesses 632system.l2c.demand_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for demand accesses 633system.l2c.demand_miss_rate::cpu0.itb.walker 0.063830 # miss rate for demand accesses 634system.l2c.demand_miss_rate::cpu0.inst 0.182992 # miss rate for demand accesses 635system.l2c.demand_miss_rate::cpu0.data 0.301536 # miss rate for demand accesses 636system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for demand accesses 637system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses 638system.l2c.demand_miss_rate::cpu1.inst 0.129714 # miss rate for demand accesses 639system.l2c.demand_miss_rate::cpu1.data 0.333837 # miss rate for demand accesses 640system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for demand accesses 641system.l2c.demand_miss_rate::total 0.472592 # miss rate for demand accesses 642system.l2c.overall_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for overall accesses 643system.l2c.overall_miss_rate::cpu0.itb.walker 0.063830 # miss rate for overall accesses 644system.l2c.overall_miss_rate::cpu0.inst 0.182992 # miss rate for overall accesses 645system.l2c.overall_miss_rate::cpu0.data 0.301536 # miss rate for overall accesses 646system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for overall accesses 647system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses 648system.l2c.overall_miss_rate::cpu1.inst 0.129714 # miss rate for overall accesses 649system.l2c.overall_miss_rate::cpu1.data 0.333837 # miss rate for overall accesses 650system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for overall accesses 651system.l2c.overall_miss_rate::total 0.472592 # miss rate for overall accesses 652system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average ReadReq miss latency 653system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq miss latency 654system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83271.165569 # average ReadReq miss latency 655system.l2c.ReadReq_avg_miss_latency::cpu0.data 77277.999079 # average ReadReq miss latency 656system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average ReadReq miss latency 657system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average ReadReq miss latency 658system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87397.192029 # average ReadReq miss latency 659system.l2c.ReadReq_avg_miss_latency::cpu1.data 77746.915819 # average ReadReq miss latency 660system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average ReadReq miss latency 661system.l2c.ReadReq_avg_miss_latency::total 103168.045627 # average ReadReq miss latency 662system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1560.022222 # average UpgradeReq miss latency 663system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1135.424421 # average UpgradeReq miss latency 664system.l2c.UpgradeReq_avg_miss_latency::total 1382.790551 # average UpgradeReq miss latency 665system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 400.141509 # average SCUpgradeReq miss latency 666system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3671.705139 # average SCUpgradeReq miss latency 667system.l2c.SCUpgradeReq_avg_miss_latency::total 1979.379423 # average SCUpgradeReq miss latency 668system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74557.463371 # average ReadExReq miss latency 669system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74680.273566 # average ReadExReq miss latency 670system.l2c.ReadExReq_avg_miss_latency::total 74626.662167 # average ReadExReq miss latency 671system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency 672system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency 673system.l2c.demand_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency 674system.l2c.demand_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency 675system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency 676system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency 677system.l2c.demand_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency 678system.l2c.demand_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency 679system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency 680system.l2c.demand_avg_miss_latency::total 101695.935118 # average overall miss latency 681system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency 682system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency 683system.l2c.overall_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency 684system.l2c.overall_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency 685system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency 686system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency 687system.l2c.overall_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency 688system.l2c.overall_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency 689system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency 690system.l2c.overall_avg_miss_latency::total 101695.935118 # average overall miss latency 691system.l2c.blocked_cycles::no_mshrs 369 # number of cycles access was blocked | 537system.l2c.overall_misses::cpu0.inst 3722 # number of overall misses 538system.l2c.overall_misses::cpu0.data 16424 # number of overall misses 539system.l2c.overall_misses::cpu0.l2cache.prefetcher 164359 # number of overall misses 540system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses 541system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 542system.l2c.overall_misses::cpu1.inst 492 # number of overall misses 543system.l2c.overall_misses::cpu1.data 8631 # number of overall misses 544system.l2c.overall_misses::cpu1.l2cache.prefetcher 20906 # number of overall misses 545system.l2c.overall_misses::total 214580 # number of overall misses 546system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2653000 # number of ReadReq miss cycles 547system.l2c.ReadReq_miss_latency::cpu0.itb.walker 225500 # number of ReadReq miss cycles 548system.l2c.ReadReq_miss_latency::cpu0.inst 348764246 # number of ReadReq miss cycles 549system.l2c.ReadReq_miss_latency::cpu0.data 769947990 # number of ReadReq miss cycles 550system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of ReadReq miss cycles 551system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 875000 # number of ReadReq miss cycles 552system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles 553system.l2c.ReadReq_miss_latency::cpu1.inst 50097250 # number of ReadReq miss cycles 554system.l2c.ReadReq_miss_latency::cpu1.data 119367500 # number of ReadReq miss cycles 555system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of ReadReq miss cycles 556system.l2c.ReadReq_miss_latency::total 22807506228 # number of ReadReq miss cycles 557system.l2c.UpgradeReq_miss_latency::cpu0.data 7178208 # number of UpgradeReq miss cycles 558system.l2c.UpgradeReq_miss_latency::cpu1.data 2570892 # number of UpgradeReq miss cycles 559system.l2c.UpgradeReq_miss_latency::total 9749100 # number of UpgradeReq miss cycles 560system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1432440 # number of SCUpgradeReq miss cycles 561system.l2c.SCUpgradeReq_miss_latency::cpu1.data 791466 # number of SCUpgradeReq miss cycles 562system.l2c.SCUpgradeReq_miss_latency::total 2223906 # number of SCUpgradeReq miss cycles 563system.l2c.ReadExReq_miss_latency::cpu0.data 708658416 # number of ReadExReq miss cycles 564system.l2c.ReadExReq_miss_latency::cpu1.data 564088479 # number of ReadExReq miss cycles 565system.l2c.ReadExReq_miss_latency::total 1272746895 # number of ReadExReq miss cycles 566system.l2c.demand_miss_latency::cpu0.dtb.walker 2653000 # number of demand (read+write) miss cycles 567system.l2c.demand_miss_latency::cpu0.itb.walker 225500 # number of demand (read+write) miss cycles 568system.l2c.demand_miss_latency::cpu0.inst 348764246 # number of demand (read+write) miss cycles 569system.l2c.demand_miss_latency::cpu0.data 1478606406 # number of demand (read+write) miss cycles 570system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of demand (read+write) miss cycles 571system.l2c.demand_miss_latency::cpu1.dtb.walker 875000 # number of demand (read+write) miss cycles 572system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles 573system.l2c.demand_miss_latency::cpu1.inst 50097250 # number of demand (read+write) miss cycles 574system.l2c.demand_miss_latency::cpu1.data 683455979 # number of demand (read+write) miss cycles 575system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of demand (read+write) miss cycles 576system.l2c.demand_miss_latency::total 24080253123 # number of demand (read+write) miss cycles 577system.l2c.overall_miss_latency::cpu0.dtb.walker 2653000 # number of overall miss cycles 578system.l2c.overall_miss_latency::cpu0.itb.walker 225500 # number of overall miss cycles 579system.l2c.overall_miss_latency::cpu0.inst 348764246 # number of overall miss cycles 580system.l2c.overall_miss_latency::cpu0.data 1478606406 # number of overall miss cycles 581system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of overall miss cycles 582system.l2c.overall_miss_latency::cpu1.dtb.walker 875000 # number of overall miss cycles 583system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles 584system.l2c.overall_miss_latency::cpu1.inst 50097250 # number of overall miss cycles 585system.l2c.overall_miss_latency::cpu1.data 683455979 # number of overall miss cycles 586system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of overall miss cycles 587system.l2c.overall_miss_latency::total 24080253123 # number of overall miss cycles 588system.l2c.ReadReq_accesses::cpu0.dtb.walker 323 # number of ReadReq accesses(hits+misses) 589system.l2c.ReadReq_accesses::cpu0.itb.walker 157 # number of ReadReq accesses(hits+misses) 590system.l2c.ReadReq_accesses::cpu0.inst 16214 # number of ReadReq accesses(hits+misses) 591system.l2c.ReadReq_accesses::cpu0.data 47732 # number of ReadReq accesses(hits+misses) 592system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346816 # number of ReadReq accesses(hits+misses) 593system.l2c.ReadReq_accesses::cpu1.dtb.walker 93 # number of ReadReq accesses(hits+misses) 594system.l2c.ReadReq_accesses::cpu1.itb.walker 49 # number of ReadReq accesses(hits+misses) 595system.l2c.ReadReq_accesses::cpu1.inst 4586 # number of ReadReq accesses(hits+misses) 596system.l2c.ReadReq_accesses::cpu1.data 12896 # number of ReadReq accesses(hits+misses) 597system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65092 # number of ReadReq accesses(hits+misses) 598system.l2c.ReadReq_accesses::total 493958 # number of ReadReq accesses(hits+misses) 599system.l2c.Writeback_accesses::writebacks 252842 # number of Writeback accesses(hits+misses) 600system.l2c.Writeback_accesses::total 252842 # number of Writeback accesses(hits+misses) 601system.l2c.UpgradeReq_accesses::cpu0.data 20617 # number of UpgradeReq accesses(hits+misses) 602system.l2c.UpgradeReq_accesses::cpu1.data 3542 # number of UpgradeReq accesses(hits+misses) 603system.l2c.UpgradeReq_accesses::total 24159 # number of UpgradeReq accesses(hits+misses) 604system.l2c.SCUpgradeReq_accesses::cpu0.data 965 # number of SCUpgradeReq accesses(hits+misses) 605system.l2c.SCUpgradeReq_accesses::cpu1.data 1369 # number of SCUpgradeReq accesses(hits+misses) 606system.l2c.SCUpgradeReq_accesses::total 2334 # number of SCUpgradeReq accesses(hits+misses) 607system.l2c.ReadExReq_accesses::cpu0.data 11449 # number of ReadExReq accesses(hits+misses) 608system.l2c.ReadExReq_accesses::cpu1.data 8392 # number of ReadExReq accesses(hits+misses) 609system.l2c.ReadExReq_accesses::total 19841 # number of ReadExReq accesses(hits+misses) 610system.l2c.demand_accesses::cpu0.dtb.walker 323 # number of demand (read+write) accesses 611system.l2c.demand_accesses::cpu0.itb.walker 157 # number of demand (read+write) accesses 612system.l2c.demand_accesses::cpu0.inst 16214 # number of demand (read+write) accesses 613system.l2c.demand_accesses::cpu0.data 59181 # number of demand (read+write) accesses 614system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346816 # number of demand (read+write) accesses 615system.l2c.demand_accesses::cpu1.dtb.walker 93 # number of demand (read+write) accesses 616system.l2c.demand_accesses::cpu1.itb.walker 49 # number of demand (read+write) accesses 617system.l2c.demand_accesses::cpu1.inst 4586 # number of demand (read+write) accesses 618system.l2c.demand_accesses::cpu1.data 21288 # number of demand (read+write) accesses 619system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65092 # number of demand (read+write) accesses 620system.l2c.demand_accesses::total 513799 # number of demand (read+write) accesses 621system.l2c.overall_accesses::cpu0.dtb.walker 323 # number of overall (read+write) accesses 622system.l2c.overall_accesses::cpu0.itb.walker 157 # number of overall (read+write) accesses 623system.l2c.overall_accesses::cpu0.inst 16214 # number of overall (read+write) accesses 624system.l2c.overall_accesses::cpu0.data 59181 # number of overall (read+write) accesses 625system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346816 # number of overall (read+write) accesses 626system.l2c.overall_accesses::cpu1.dtb.walker 93 # number of overall (read+write) accesses 627system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses 628system.l2c.overall_accesses::cpu1.inst 4586 # number of overall (read+write) accesses 629system.l2c.overall_accesses::cpu1.data 21288 # number of overall (read+write) accesses 630system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65092 # number of overall (read+write) accesses 631system.l2c.overall_accesses::total 513799 # number of overall (read+write) accesses 632system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for ReadReq accesses 633system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019108 # miss rate for ReadReq accesses 634system.l2c.ReadReq_miss_rate::cpu0.inst 0.229555 # miss rate for ReadReq accesses 635system.l2c.ReadReq_miss_rate::cpu0.data 0.181199 # miss rate for ReadReq accesses 636system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for ReadReq accesses 637system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for ReadReq accesses 638system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses 639system.l2c.ReadReq_miss_rate::cpu1.inst 0.107283 # miss rate for ReadReq accesses 640system.l2c.ReadReq_miss_rate::cpu1.data 0.108251 # miss rate for ReadReq accesses 641system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for ReadReq accesses 642system.l2c.ReadReq_miss_rate::total 0.404022 # miss rate for ReadReq accesses 643system.l2c.UpgradeReq_miss_rate::cpu0.data 0.432216 # miss rate for UpgradeReq accesses 644system.l2c.UpgradeReq_miss_rate::cpu1.data 0.794749 # miss rate for UpgradeReq accesses 645system.l2c.UpgradeReq_miss_rate::total 0.485368 # miss rate for UpgradeReq accesses 646system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795855 # miss rate for SCUpgradeReq accesses 647system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.887509 # miss rate for SCUpgradeReq accesses 648system.l2c.SCUpgradeReq_miss_rate::total 0.849614 # miss rate for SCUpgradeReq accesses 649system.l2c.ReadExReq_miss_rate::cpu0.data 0.679099 # miss rate for ReadExReq accesses 650system.l2c.ReadExReq_miss_rate::cpu1.data 0.862131 # miss rate for ReadExReq accesses 651system.l2c.ReadExReq_miss_rate::total 0.756514 # miss rate for ReadExReq accesses 652system.l2c.demand_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for demand accesses 653system.l2c.demand_miss_rate::cpu0.itb.walker 0.019108 # miss rate for demand accesses 654system.l2c.demand_miss_rate::cpu0.inst 0.229555 # miss rate for demand accesses 655system.l2c.demand_miss_rate::cpu0.data 0.277522 # miss rate for demand accesses 656system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for demand accesses 657system.l2c.demand_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for demand accesses 658system.l2c.demand_miss_rate::cpu1.itb.walker 0.020408 # miss rate for demand accesses 659system.l2c.demand_miss_rate::cpu1.inst 0.107283 # miss rate for demand accesses 660system.l2c.demand_miss_rate::cpu1.data 0.405440 # miss rate for demand accesses 661system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for demand accesses 662system.l2c.demand_miss_rate::total 0.417634 # miss rate for demand accesses 663system.l2c.overall_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for overall accesses 664system.l2c.overall_miss_rate::cpu0.itb.walker 0.019108 # miss rate for overall accesses 665system.l2c.overall_miss_rate::cpu0.inst 0.229555 # miss rate for overall accesses 666system.l2c.overall_miss_rate::cpu0.data 0.277522 # miss rate for overall accesses 667system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for overall accesses 668system.l2c.overall_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for overall accesses 669system.l2c.overall_miss_rate::cpu1.itb.walker 0.020408 # miss rate for overall accesses 670system.l2c.overall_miss_rate::cpu1.inst 0.107283 # miss rate for overall accesses 671system.l2c.overall_miss_rate::cpu1.data 0.405440 # miss rate for overall accesses 672system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for overall accesses 673system.l2c.overall_miss_rate::total 0.417634 # miss rate for overall accesses 674system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average ReadReq miss latency 675system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75166.666667 # average ReadReq miss latency 676system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93703.451370 # average ReadReq miss latency 677system.l2c.ReadReq_avg_miss_latency::cpu0.data 89021.619840 # average ReadReq miss latency 678system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average ReadReq miss latency 679system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average ReadReq miss latency 680system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency 681system.l2c.ReadReq_avg_miss_latency::cpu1.inst 101823.678862 # average ReadReq miss latency 682system.l2c.ReadReq_avg_miss_latency::cpu1.data 85506.805158 # average ReadReq miss latency 683system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average ReadReq miss latency 684system.l2c.ReadReq_avg_miss_latency::total 114283.240106 # average ReadReq miss latency 685system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 805.544608 # average UpgradeReq miss latency 686system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 913.283126 # average UpgradeReq miss latency 687system.l2c.UpgradeReq_avg_miss_latency::total 831.408835 # average UpgradeReq miss latency 688system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1865.156250 # average SCUpgradeReq miss latency 689system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 651.412346 # average SCUpgradeReq miss latency 690system.l2c.SCUpgradeReq_avg_miss_latency::total 1121.485628 # average SCUpgradeReq miss latency 691system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91145.776977 # average ReadExReq miss latency 692system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77966.617692 # average ReadExReq miss latency 693system.l2c.ReadExReq_avg_miss_latency::total 84793.264157 # average ReadExReq miss latency 694system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency 695system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency 696system.l2c.demand_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency 697system.l2c.demand_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency 698system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency 699system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency 700system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency 701system.l2c.demand_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency 702system.l2c.demand_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency 703system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency 704system.l2c.demand_avg_miss_latency::total 112220.398560 # average overall miss latency 705system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency 706system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency 707system.l2c.overall_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency 708system.l2c.overall_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency 709system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency 710system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency 711system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency 712system.l2c.overall_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency 713system.l2c.overall_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency 714system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency 715system.l2c.overall_avg_miss_latency::total 112220.398560 # average overall miss latency 716system.l2c.blocked_cycles::no_mshrs 435 # number of cycles access was blocked |
| 692system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 717system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 693system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked | 718system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked |
| 694system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 719system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 695system.l2c.avg_blocked_cycles::no_mshrs 36.900000 # average number of cycles each access was blocked | 720system.l2c.avg_blocked_cycles::no_mshrs 16.730769 # average number of cycles each access was blocked |
| 696system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 697system.l2c.fast_writes 0 # number of fast writes performed 698system.l2c.cache_copies 0 # number of cache copies performed | 721system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.l2c.fast_writes 0 # number of fast writes performed 723system.l2c.cache_copies 0 # number of cache copies performed |
| 699system.l2c.writebacks::writebacks 68618 # number of writebacks 700system.l2c.writebacks::total 68618 # number of writebacks 701system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses | 724system.l2c.writebacks::writebacks 113484 # number of writebacks 725system.l2c.writebacks::total 113484 # number of writebacks 726system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 727system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits 728system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 729system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadReq MSHR hits 730system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits 731system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 732system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits 733system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 734system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits 735system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 736system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 737system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits 738system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 739system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits 740system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits 741system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 31 # number of ReadReq MSHR misses |
| 702system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses | 742system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses |
| 703system.l2c.ReadReq_mshr_misses::cpu0.inst 1063 # number of ReadReq MSHR misses 704system.l2c.ReadReq_mshr_misses::cpu0.data 3259 # number of ReadReq MSHR misses 705system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq MSHR misses 706system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses 707system.l2c.ReadReq_mshr_misses::cpu1.inst 1104 # number of ReadReq MSHR misses 708system.l2c.ReadReq_mshr_misses::cpu1.data 4621 # number of ReadReq MSHR misses 709system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq MSHR misses 710system.l2c.ReadReq_mshr_misses::total 166173 # number of ReadReq MSHR misses 711system.l2c.UpgradeReq_mshr_misses::cpu0.data 7830 # number of UpgradeReq MSHR misses 712system.l2c.UpgradeReq_mshr_misses::cpu1.data 5610 # number of UpgradeReq MSHR misses 713system.l2c.UpgradeReq_mshr_misses::total 13440 # number of UpgradeReq MSHR misses 714system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1272 # number of SCUpgradeReq MSHR misses 715system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1187 # number of SCUpgradeReq MSHR misses 716system.l2c.SCUpgradeReq_mshr_misses::total 2459 # number of SCUpgradeReq MSHR misses 717system.l2c.ReadExReq_mshr_misses::cpu0.data 3945 # number of ReadExReq MSHR misses 718system.l2c.ReadExReq_mshr_misses::cpu1.data 5092 # number of ReadExReq MSHR misses 719system.l2c.ReadExReq_mshr_misses::total 9037 # number of ReadExReq MSHR misses 720system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses | 743system.l2c.ReadReq_mshr_misses::cpu0.inst 3721 # number of ReadReq MSHR misses 744system.l2c.ReadReq_mshr_misses::cpu0.data 8649 # number of ReadReq MSHR misses 745system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of ReadReq MSHR misses 746system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses 747system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 748system.l2c.ReadReq_mshr_misses::cpu1.inst 491 # number of ReadReq MSHR misses 749system.l2c.ReadReq_mshr_misses::cpu1.data 1396 # number of ReadReq MSHR misses 750system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of ReadReq MSHR misses 751system.l2c.ReadReq_mshr_misses::total 199550 # number of ReadReq MSHR misses 752system.l2c.UpgradeReq_mshr_misses::cpu0.data 8911 # number of UpgradeReq MSHR misses 753system.l2c.UpgradeReq_mshr_misses::cpu1.data 2815 # number of UpgradeReq MSHR misses 754system.l2c.UpgradeReq_mshr_misses::total 11726 # number of UpgradeReq MSHR misses 755system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 768 # number of SCUpgradeReq MSHR misses 756system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1215 # number of SCUpgradeReq MSHR misses 757system.l2c.SCUpgradeReq_mshr_misses::total 1983 # number of SCUpgradeReq MSHR misses 758system.l2c.ReadExReq_mshr_misses::cpu0.data 7775 # number of ReadExReq MSHR misses 759system.l2c.ReadExReq_mshr_misses::cpu1.data 7235 # number of ReadExReq MSHR misses 760system.l2c.ReadExReq_mshr_misses::total 15010 # number of ReadExReq MSHR misses 761system.l2c.demand_mshr_misses::cpu0.dtb.walker 31 # number of demand (read+write) MSHR misses |
| 721system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses | 762system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses |
| 722system.l2c.demand_mshr_misses::cpu0.inst 1063 # number of demand (read+write) MSHR misses 723system.l2c.demand_mshr_misses::cpu0.data 7204 # number of demand (read+write) MSHR misses 724system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) MSHR misses 725system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses 726system.l2c.demand_mshr_misses::cpu1.inst 1104 # number of demand (read+write) MSHR misses 727system.l2c.demand_mshr_misses::cpu1.data 9713 # number of demand (read+write) MSHR misses 728system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) MSHR misses 729system.l2c.demand_mshr_misses::total 175210 # number of demand (read+write) MSHR misses 730system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses | 763system.l2c.demand_mshr_misses::cpu0.inst 3721 # number of demand (read+write) MSHR misses 764system.l2c.demand_mshr_misses::cpu0.data 16424 # number of demand (read+write) MSHR misses 765system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of demand (read+write) MSHR misses 766system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses 767system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 768system.l2c.demand_mshr_misses::cpu1.inst 491 # number of demand (read+write) MSHR misses 769system.l2c.demand_mshr_misses::cpu1.data 8631 # number of demand (read+write) MSHR misses 770system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of demand (read+write) MSHR misses 771system.l2c.demand_mshr_misses::total 214560 # number of demand (read+write) MSHR misses 772system.l2c.overall_mshr_misses::cpu0.dtb.walker 31 # number of overall MSHR misses |
| 731system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses | 773system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses |
| 732system.l2c.overall_mshr_misses::cpu0.inst 1063 # number of overall MSHR misses 733system.l2c.overall_mshr_misses::cpu0.data 7204 # number of overall MSHR misses 734system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of overall MSHR misses 735system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses 736system.l2c.overall_mshr_misses::cpu1.inst 1104 # number of overall MSHR misses 737system.l2c.overall_mshr_misses::cpu1.data 9713 # number of overall MSHR misses 738system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of overall MSHR misses 739system.l2c.overall_mshr_misses::total 175210 # number of overall MSHR misses 740system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158750 # number of ReadReq MSHR miss cycles 741system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 145000 # number of ReadReq MSHR miss cycles 742system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 75361749 # number of ReadReq MSHR miss cycles 743system.l2c.ReadReq_mshr_miss_latency::cpu0.data 211101499 # number of ReadReq MSHR miss cycles 744system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of ReadReq MSHR miss cycles 745system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 645000 # number of ReadReq MSHR miss cycles 746system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 82874000 # number of ReadReq MSHR miss cycles 747system.l2c.ReadReq_mshr_miss_latency::cpu1.data 301675998 # number of ReadReq MSHR miss cycles 748system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of ReadReq MSHR miss cycles 749system.l2c.ReadReq_mshr_miss_latency::total 15091446656 # number of ReadReq MSHR miss cycles 750system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 79003615 # number of UpgradeReq MSHR miss cycles 751system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56662566 # number of UpgradeReq MSHR miss cycles 752system.l2c.UpgradeReq_mshr_miss_latency::total 135666181 # number of UpgradeReq MSHR miss cycles 753system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12832754 # number of SCUpgradeReq MSHR miss cycles 754system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11966179 # number of SCUpgradeReq MSHR miss cycles 755system.l2c.SCUpgradeReq_mshr_miss_latency::total 24798933 # number of SCUpgradeReq MSHR miss cycles 756system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 244772807 # number of ReadExReq MSHR miss cycles 757system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 316260047 # number of ReadExReq MSHR miss cycles 758system.l2c.ReadExReq_mshr_miss_latency::total 561032854 # number of ReadExReq MSHR miss cycles 759system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158750 # number of demand (read+write) MSHR miss cycles 760system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145000 # number of demand (read+write) MSHR miss cycles 761system.l2c.demand_mshr_miss_latency::cpu0.inst 75361749 # number of demand (read+write) MSHR miss cycles 762system.l2c.demand_mshr_miss_latency::cpu0.data 455874306 # number of demand (read+write) MSHR miss cycles 763system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of demand (read+write) MSHR miss cycles 764system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 645000 # number of demand (read+write) MSHR miss cycles 765system.l2c.demand_mshr_miss_latency::cpu1.inst 82874000 # number of demand (read+write) MSHR miss cycles 766system.l2c.demand_mshr_miss_latency::cpu1.data 617936045 # number of demand (read+write) MSHR miss cycles 767system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of demand (read+write) MSHR miss cycles 768system.l2c.demand_mshr_miss_latency::total 15652479510 # number of demand (read+write) MSHR miss cycles 769system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158750 # number of overall MSHR miss cycles 770system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145000 # number of overall MSHR miss cycles 771system.l2c.overall_mshr_miss_latency::cpu0.inst 75361749 # number of overall MSHR miss cycles 772system.l2c.overall_mshr_miss_latency::cpu0.data 455874306 # number of overall MSHR miss cycles 773system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of overall MSHR miss cycles 774system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 645000 # number of overall MSHR miss cycles 775system.l2c.overall_mshr_miss_latency::cpu1.inst 82874000 # number of overall MSHR miss cycles 776system.l2c.overall_mshr_miss_latency::cpu1.data 617936045 # number of overall MSHR miss cycles 777system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of overall MSHR miss cycles 778system.l2c.overall_mshr_miss_latency::total 15652479510 # number of overall MSHR miss cycles 779system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 178129250 # number of ReadReq MSHR uncacheable cycles 780system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343853503 # number of ReadReq MSHR uncacheable cycles 781system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3278250 # number of ReadReq MSHR uncacheable cycles 782system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154953535743 # number of ReadReq MSHR uncacheable cycles 783system.l2c.ReadReq_mshr_uncacheable_latency::total 167478796746 # number of ReadReq MSHR uncacheable cycles 784system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076363997 # number of WriteReq MSHR uncacheable cycles 785system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16025248776 # number of WriteReq MSHR uncacheable cycles 786system.l2c.WriteReq_mshr_uncacheable_latency::total 17101612773 # number of WriteReq MSHR uncacheable cycles 787system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles 788system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles 789system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles 790system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles 791system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles 792system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses 793system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses 794system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses 795system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses 796system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses 797system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses 798system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses 799system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses 800system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses 801system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses 802system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses 803system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses 804system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses 805system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses 806system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses 807system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses 808system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses 809system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses 810system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses 811system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses 812system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses 813system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses 814system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses 815system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses 816system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses 817system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses 818system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses 819system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses 820system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses 821system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses 822system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses 823system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses 824system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses 825system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses 826system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses 827system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses 828system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses 829system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses 830system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses 831system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency 832system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency 833system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency 834system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency 835system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency 836system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency 837system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency 838system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency 839system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency 840system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency 841system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency 842system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency 843system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency 844system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency 845system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency 846system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency 847system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency 848system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency 849system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency 850system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency 851system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency 852system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency 853system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency 854system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency 855system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency 856system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency 857system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency 858system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency 859system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency 860system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency 861system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency 862system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency 863system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency 864system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency 865system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency 866system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency 867system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency 868system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency 869system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency | 774system.l2c.overall_mshr_misses::cpu0.inst 3721 # number of overall MSHR misses 775system.l2c.overall_mshr_misses::cpu0.data 16424 # number of overall MSHR misses 776system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of overall MSHR misses 777system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses 778system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 779system.l2c.overall_mshr_misses::cpu1.inst 491 # number of overall MSHR misses 780system.l2c.overall_mshr_misses::cpu1.data 8631 # number of overall MSHR misses 781system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of overall MSHR misses 782system.l2c.overall_mshr_misses::total 214560 # number of overall MSHR misses 783system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of ReadReq MSHR miss cycles 784system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 187500 # number of ReadReq MSHR miss cycles 785system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 302749246 # number of ReadReq MSHR miss cycles 786system.l2c.ReadReq_mshr_miss_latency::cpu0.data 662570490 # number of ReadReq MSHR miss cycles 787system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of ReadReq MSHR miss cycles 788system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 738500 # number of ReadReq MSHR miss cycles 789system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 790system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 43998750 # number of ReadReq MSHR miss cycles 791system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101980500 # number of ReadReq MSHR miss cycles 792system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of ReadReq MSHR miss cycles 793system.l2c.ReadReq_mshr_miss_latency::total 20353955728 # number of ReadReq MSHR miss cycles 794system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90147824 # number of UpgradeReq MSHR miss cycles 795system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28509296 # number of UpgradeReq MSHR miss cycles 796system.l2c.UpgradeReq_mshr_miss_latency::total 118657120 # number of UpgradeReq MSHR miss cycles 797system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7897727 # number of SCUpgradeReq MSHR miss cycles 798system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12233707 # number of SCUpgradeReq MSHR miss cycles 799system.l2c.SCUpgradeReq_mshr_miss_latency::total 20131434 # number of SCUpgradeReq MSHR miss cycles 800system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 612435582 # number of ReadExReq MSHR miss cycles 801system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 472780517 # number of ReadExReq MSHR miss cycles 802system.l2c.ReadExReq_mshr_miss_latency::total 1085216099 # number of ReadExReq MSHR miss cycles 803system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of demand (read+write) MSHR miss cycles 804system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 187500 # number of demand (read+write) MSHR miss cycles 805system.l2c.demand_mshr_miss_latency::cpu0.inst 302749246 # number of demand (read+write) MSHR miss cycles 806system.l2c.demand_mshr_miss_latency::cpu0.data 1275006072 # number of demand (read+write) MSHR miss cycles 807system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of demand (read+write) MSHR miss cycles 808system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 738500 # number of demand (read+write) MSHR miss cycles 809system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 810system.l2c.demand_mshr_miss_latency::cpu1.inst 43998750 # number of demand (read+write) MSHR miss cycles 811system.l2c.demand_mshr_miss_latency::cpu1.data 574761017 # number of demand (read+write) MSHR miss cycles 812system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of demand (read+write) MSHR miss cycles 813system.l2c.demand_mshr_miss_latency::total 21439171827 # number of demand (read+write) MSHR miss cycles 814system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of overall MSHR miss cycles 815system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 187500 # number of overall MSHR miss cycles 816system.l2c.overall_mshr_miss_latency::cpu0.inst 302749246 # number of overall MSHR miss cycles 817system.l2c.overall_mshr_miss_latency::cpu0.data 1275006072 # number of overall MSHR miss cycles 818system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of overall MSHR miss cycles 819system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 738500 # number of overall MSHR miss cycles 820system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles 821system.l2c.overall_mshr_miss_latency::cpu1.inst 43998750 # number of overall MSHR miss cycles 822system.l2c.overall_mshr_miss_latency::cpu1.data 574761017 # number of overall MSHR miss cycles 823system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of overall MSHR miss cycles 824system.l2c.overall_mshr_miss_latency::total 21439171827 # number of overall MSHR miss cycles 825system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 158715000 # number of ReadReq MSHR uncacheable cycles 826system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685804000 # number of ReadReq MSHR uncacheable cycles 827system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5055250 # number of ReadReq MSHR uncacheable cycles 828system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919801500 # number of ReadReq MSHR uncacheable cycles 829system.l2c.ReadReq_mshr_uncacheable_latency::total 5769375750 # number of ReadReq MSHR uncacheable cycles 830system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713908502 # number of WriteReq MSHR uncacheable cycles 831system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535177501 # number of WriteReq MSHR uncacheable cycles 832system.l2c.WriteReq_mshr_uncacheable_latency::total 4249086003 # number of WriteReq MSHR uncacheable cycles 833system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158715000 # number of overall MSHR uncacheable cycles 834system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6399712502 # number of overall MSHR uncacheable cycles 835system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5055250 # number of overall MSHR uncacheable cycles 836system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3454979001 # number of overall MSHR uncacheable cycles 837system.l2c.overall_mshr_uncacheable_latency::total 10018461753 # number of overall MSHR uncacheable cycles 838system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for ReadReq accesses 839system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for ReadReq accesses 840system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for ReadReq accesses 841system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181199 # mshr miss rate for ReadReq accesses 842system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for ReadReq accesses 843system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for ReadReq accesses 844system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses 845system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for ReadReq accesses 846system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108251 # mshr miss rate for ReadReq accesses 847system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for ReadReq accesses 848system.l2c.ReadReq_mshr_miss_rate::total 0.403982 # mshr miss rate for ReadReq accesses 849system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.432216 # mshr miss rate for UpgradeReq accesses 850system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.794749 # mshr miss rate for UpgradeReq accesses 851system.l2c.UpgradeReq_mshr_miss_rate::total 0.485368 # mshr miss rate for UpgradeReq accesses 852system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795855 # mshr miss rate for SCUpgradeReq accesses 853system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.887509 # mshr miss rate for SCUpgradeReq accesses 854system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.849614 # mshr miss rate for SCUpgradeReq accesses 855system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.679099 # mshr miss rate for ReadExReq accesses 856system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.862131 # mshr miss rate for ReadExReq accesses 857system.l2c.ReadExReq_mshr_miss_rate::total 0.756514 # mshr miss rate for ReadExReq accesses 858system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for demand accesses 859system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for demand accesses 860system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for demand accesses 861system.l2c.demand_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for demand accesses 862system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for demand accesses 863system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for demand accesses 864system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses 865system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for demand accesses 866system.l2c.demand_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for demand accesses 867system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for demand accesses 868system.l2c.demand_mshr_miss_rate::total 0.417595 # mshr miss rate for demand accesses 869system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for overall accesses 870system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for overall accesses 871system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for overall accesses 872system.l2c.overall_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for overall accesses 873system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for overall accesses 874system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for overall accesses 875system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses 876system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for overall accesses 877system.l2c.overall_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for overall accesses 878system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for overall accesses 879system.l2c.overall_mshr_miss_rate::total 0.417595 # mshr miss rate for overall accesses 880system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average ReadReq mshr miss latency 881system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 882system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average ReadReq mshr miss latency 883system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76606.600763 # average ReadReq mshr miss latency 884system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average ReadReq mshr miss latency 885system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average ReadReq mshr miss latency 886system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 887system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average ReadReq mshr miss latency 888system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73051.934097 # average ReadReq mshr miss latency 889system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average ReadReq mshr miss latency 890system.l2c.ReadReq_avg_mshr_miss_latency::total 101999.277013 # average ReadReq mshr miss latency 891system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10116.465492 # average UpgradeReq mshr miss latency 892system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10127.636234 # average UpgradeReq mshr miss latency 893system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.147194 # average UpgradeReq mshr miss latency 894system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10283.498698 # average SCUpgradeReq mshr miss latency 895system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10068.894650 # average SCUpgradeReq mshr miss latency 896system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10152.009077 # average SCUpgradeReq mshr miss latency 897system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78769.849775 # average ReadExReq mshr miss latency 898system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65346.305045 # average ReadExReq mshr miss latency 899system.l2c.ReadExReq_avg_mshr_miss_latency::total 72299.540240 # average ReadExReq mshr miss latency 900system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency 901system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 902system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency 903system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency 904system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency 905system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency 906system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 907system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency 908system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency 909system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency 910system.l2c.demand_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency 911system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency 912system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 913system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency 914system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency 915system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency 916system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency 917system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 918system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency 919system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency 920system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency 921system.l2c.overall_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency |
| 870system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 871system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 872system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 873system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 874system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 875system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 876system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 877system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 878system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 879system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 880system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 881system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 882system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 883system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 922system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 923system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 924system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 925system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 926system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 927system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 928system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 929system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 930system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 931system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 932system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 933system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 934system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 935system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 936system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 937system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 938system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 939system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 940system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 941system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 942system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 943system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 944system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 945system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 946system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 947system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 948system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 949system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 950system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 951system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 952system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 953system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 954system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 955system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 956system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 957system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 958system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 959system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 960system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 961system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 962system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 963system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 964system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 965system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 966system.realview.ethernet.droppedPackets 0 # number of packets dropped |
|
| 884system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). | 967system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| 885system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 886system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 887system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 888system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 889system.cf0.dma_write_txs 0 # Number of DMA write transactions. 890system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution 891system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution 892system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution 893system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution 894system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution 895system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution 896system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution 897system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution 898system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 899system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution 900system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution 901system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution 902system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes) 903system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes) 904system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes) 905system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes) 906system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes) 907system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes) 908system.toL2Bus.snoops 177868 # Total snoops (count) 909system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram 910system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 911system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 968system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 969system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 970system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 971system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 972system.cf0.dma_write_txs 631 # Number of DMA write transactions. 973system.toL2Bus.trans_dist::ReadReq 660507 # Transaction distribution 974system.toL2Bus.trans_dist::ReadResp 660492 # Transaction distribution 975system.toL2Bus.trans_dist::WriteReq 30981 # Transaction distribution 976system.toL2Bus.trans_dist::WriteResp 30981 # Transaction distribution 977system.toL2Bus.trans_dist::Writeback 252842 # Transaction distribution 978system.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution 979system.toL2Bus.trans_dist::UpgradeReq 91952 # Transaction distribution 980system.toL2Bus.trans_dist::SCUpgradeReq 41104 # Transaction distribution 981system.toL2Bus.trans_dist::UpgradeResp 133056 # Transaction distribution 982system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution 983system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution 984system.toL2Bus.trans_dist::ReadExReq 40101 # Transaction distribution 985system.toL2Bus.trans_dist::ReadExResp 40101 # Transaction distribution 986system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1300560 # Packet count per connected master and slave (bytes) 987system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426210 # Packet count per connected master and slave (bytes) 988system.toL2Bus.pkt_count::total 1726770 # Packet count per connected master and slave (bytes) 989system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40798474 # Cumulative packet size per connected master and slave (bytes) 990system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8541616 # Cumulative packet size per connected master and slave (bytes) 991system.toL2Bus.pkt_size::total 49340090 # Cumulative packet size per connected master and slave (bytes) 992system.toL2Bus.snoops 291850 # Total snoops (count) 993system.toL2Bus.snoop_fanout::samples 1084776 # Request fanout histogram 994system.toL2Bus.snoop_fanout::mean 1.033629 # Request fanout histogram 995system.toL2Bus.snoop_fanout::stdev 0.180273 # Request fanout histogram |
| 912system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 913system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 996system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 997system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 914system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram 915system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram | 998system.toL2Bus.snoop_fanout::1 1048296 96.64% 96.64% # Request fanout histogram 999system.toL2Bus.snoop_fanout::2 36480 3.36% 100.00% # Request fanout histogram |
| 916system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 917system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 1000system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1001system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram |
| 918system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 919system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram 920system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks) | 1002system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1003system.toL2Bus.snoop_fanout::total 1084776 # Request fanout histogram 1004system.toL2Bus.reqLayer0.occupancy 1587917075 # Layer occupancy (ticks) |
| 921system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1005system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 922system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks) 923system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 924system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks) 925system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 926system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution 927system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution 928system.iobus.trans_dist::WriteReq 8084 # Transaction distribution 929system.iobus.trans_dist::WriteResp 8084 # Transaction distribution 930system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) 931system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes) | 1006system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) 1007system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1008system.toL2Bus.respLayer0.occupancy 2276216676 # Layer occupancy (ticks) 1009system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1010system.toL2Bus.respLayer1.occupancy 846189675 # Layer occupancy (ticks) 1011system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1012system.iobus.trans_dist::ReadReq 31016 # Transaction distribution 1013system.iobus.trans_dist::ReadResp 31016 # Transaction distribution 1014system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1015system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1016system.iobus.trans_dist::WriteInvalidateReq 21 # Transaction distribution 1017system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1018system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) |
| 932system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) | 1019system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 933system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) 934system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) | 1020system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) |
| 935system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 1021system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 936system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes) 937system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 938system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) | 1022system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) |
| 939system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 940system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 941system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) | 1024system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1025system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1026system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 942system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 943system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) | 1027system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) |
| 944system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 1028system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 945system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 946system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 947system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 948system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 949system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) | |
| 950system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) | 1029system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 1030system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1031system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) |
|
| 951system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) | 1032system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 952system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 953system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes) 954system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 955system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 956system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes) 957system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) 958system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes) | 1033system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1034system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1035system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1036system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1037system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1038system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) 1039system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) 1040system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) 1041system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes) 1042system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 1043system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) |
| 959system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) | 1044system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) |
| 960system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) | 1045system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) |
| 962system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) | 1046system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
| 963system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes) 964system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 965system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1047system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) |
| 966system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 967system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 968system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1049system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 969system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 970system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) | 1052system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) |
| 971system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1053system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 972system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 973system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 974system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 975system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 976system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | |
| 977system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1054system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 1055system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1056system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) |
|
| 978system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1057system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 979system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 980system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) 981system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 982system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 983system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) 984system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) | 1058system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1059system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1060system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1061system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1062system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1063system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) 1064system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) 1065system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) 1066system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes) 1067system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) |
| 985system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1068system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 986system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks) | 1069system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) |
| 987system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1070system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 988system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) | 1071system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) |
| 989system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1072system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 990system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) | 1073system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) |
| 991system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1074system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 992system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 993system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 994system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 995system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 996system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks) | 1075system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) |
| 997system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 1076system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 998system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) | 1077system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) |
| 999system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1078system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1000system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1001system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1002system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) | 1079system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) |
| 1003system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 1080system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 1004system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 1005system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1006system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 1007system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) | |
| 1008system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1009system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 1081system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1082system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 1010system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) | 1083system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) |
| 1011system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1012system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1013system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 1084system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1085system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1086system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 1014system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) | 1087system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) |
| 1015system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1016system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1017system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1018system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1019system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 1088system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1090system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1092system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 1020system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) | 1093system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) |
| 1021system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1022system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1023system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1024system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1025system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1094system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1096system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1097system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1098system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1026system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1027system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1028system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) | 1099system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) |
| 1029system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1100system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1030system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) 1031system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 1032system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks) 1033system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 1034system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks) 1035system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1036system.cpu0.branchPred.lookups 6445077 # Number of BP lookups 1037system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted 1038system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect 1039system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups 1040system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits | 1101system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1102system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1103system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1104system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1105system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1106system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1107system.iobus.reqLayer27.occupancy 326647327 # Layer occupancy (ticks) 1108system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1109system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1110system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1111system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 1112system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1113system.iobus.respLayer3.occupancy 36834343 # Layer occupancy (ticks) 1114system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1115system.cpu0.branchPred.lookups 24027935 # Number of BP lookups 1116system.cpu0.branchPred.condPredicted 15717476 # Number of conditional branches predicted 1117system.cpu0.branchPred.condIncorrect 977431 # Number of conditional branches incorrect 1118system.cpu0.branchPred.BTBLookups 14651046 # Number of BTB lookups 1119system.cpu0.branchPred.BTBHits 10773468 # Number of BTB hits |
| 1041system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1120system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1042system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage 1043system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target. 1044system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions. | 1121system.cpu0.branchPred.BTBHitPct 73.533780 # BTB Hit Percentage 1122system.cpu0.branchPred.usedRAS 3878036 # Number of times the RAS was used to get a target. 1123system.cpu0.branchPred.RASInCorrect 32430 # Number of incorrect RAS predictions. |
| 1045system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1046system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1047system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1048system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1049system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1050system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1051system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1052system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1060system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1061system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1062system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1063system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1064system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1065system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1066system.cpu0.dtb.inst_hits 0 # ITB inst hits 1067system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1124system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1125system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1126system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1127system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1128system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1129system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1130system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1131system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1139system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1140system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1141system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1142system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1143system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1144system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1145system.cpu0.dtb.inst_hits 0 # ITB inst hits 1146system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1068system.cpu0.dtb.read_hits 6738270 # DTB read hits 1069system.cpu0.dtb.read_misses 20792 # DTB read misses 1070system.cpu0.dtb.write_hits 5108254 # DTB write hits 1071system.cpu0.dtb.write_misses 4938 # DTB write misses 1072system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1073system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1074system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1075system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1076system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB 1077system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions 1078system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch | 1147system.cpu0.dtb.read_hits 17722520 # DTB read hits 1148system.cpu0.dtb.read_misses 56371 # DTB read misses 1149system.cpu0.dtb.write_hits 14647463 # DTB write hits 1150system.cpu0.dtb.write_misses 8727 # DTB write misses 1151system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1152system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1153system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1154system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1155system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB 1156system.cpu0.dtb.align_faults 304 # Number of TLB faults due to alignment restrictions 1157system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch |
| 1079system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1158system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1080system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions 1081system.cpu0.dtb.read_accesses 6759062 # DTB read accesses 1082system.cpu0.dtb.write_accesses 5113192 # DTB write accesses | 1159system.cpu0.dtb.perms_faults 853 # Number of TLB faults due to permissions restrictions 1160system.cpu0.dtb.read_accesses 17778891 # DTB read accesses 1161system.cpu0.dtb.write_accesses 14656190 # DTB write accesses |
| 1083system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1162system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1084system.cpu0.dtb.hits 11846524 # DTB hits 1085system.cpu0.dtb.misses 25730 # DTB misses 1086system.cpu0.dtb.accesses 11872254 # DTB accesses | 1163system.cpu0.dtb.hits 32369983 # DTB hits 1164system.cpu0.dtb.misses 65098 # DTB misses 1165system.cpu0.dtb.accesses 32435081 # DTB accesses |
| 1087system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1088system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1089system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1090system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1091system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1092system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1093system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1094system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1100system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1101system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1102system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1103system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1104system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1105system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1106system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1107system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1166system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1167system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1168system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1169system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1170system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1171system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1172system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1173system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1179system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1180system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1181system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1182system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1183system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1184system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1185system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1186system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1108system.cpu0.itb.inst_hits 11251934 # ITB inst hits 1109system.cpu0.itb.inst_misses 5844 # ITB inst misses | 1187system.cpu0.itb.inst_hits 37749886 # ITB inst hits 1188system.cpu0.itb.inst_misses 10298 # ITB inst misses |
| 1110system.cpu0.itb.read_hits 0 # DTB read hits 1111system.cpu0.itb.read_misses 0 # DTB read misses 1112system.cpu0.itb.write_hits 0 # DTB write hits 1113system.cpu0.itb.write_misses 0 # DTB write misses | 1189system.cpu0.itb.read_hits 0 # DTB read hits 1190system.cpu0.itb.read_misses 0 # DTB read misses 1191system.cpu0.itb.write_hits 0 # DTB write hits 1192system.cpu0.itb.write_misses 0 # DTB write misses |
| 1114system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1115system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1116system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1117system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1118system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB | 1193system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1194system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1195system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1196system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1197system.cpu0.itb.flush_entries 2364 # Number of entries that have been flushed from TLB |
| 1119system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1120system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1121system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1198system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1199system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1200system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1122system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions | 1201system.cpu0.itb.perms_faults 1942 # Number of TLB faults due to permissions restrictions |
| 1123system.cpu0.itb.read_accesses 0 # DTB read accesses 1124system.cpu0.itb.write_accesses 0 # DTB write accesses | 1202system.cpu0.itb.read_accesses 0 # DTB read accesses 1203system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1125system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses 1126system.cpu0.itb.hits 11251934 # DTB hits 1127system.cpu0.itb.misses 5844 # DTB misses 1128system.cpu0.itb.accesses 11257778 # DTB accesses 1129system.cpu0.numCycles 70547986 # number of cpu cycles simulated | 1204system.cpu0.itb.inst_accesses 37760184 # ITB inst accesses 1205system.cpu0.itb.hits 37749886 # DTB hits 1206system.cpu0.itb.misses 10298 # DTB misses 1207system.cpu0.itb.accesses 37760184 # DTB accesses 1208system.cpu0.numCycles 126958641 # number of cpu cycles simulated |
| 1130system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1131system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1209system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1210system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1132system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss 1133system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed 1134system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered 1135system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken 1136system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked 1137system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing 1138system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb 1139system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1140system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps 1141system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions 1142system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR 1143system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched 1144system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed 1145system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed 1146system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total) 1147system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total) 1148system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total) | 1211system.cpu0.fetch.icacheStallCycles 18143411 # Number of cycles fetch is stalled on an Icache miss 1212system.cpu0.fetch.Insts 112712815 # Number of instructions fetch has processed 1213system.cpu0.fetch.Branches 24027935 # Number of branches that fetch encountered 1214system.cpu0.fetch.predictedBranches 14651504 # Number of branches that fetch has predicted taken 1215system.cpu0.fetch.Cycles 104787507 # Number of cycles fetch has run and was not squashing or blocked 1216system.cpu0.fetch.SquashCycles 2823240 # Number of cycles fetch has spent squashing 1217system.cpu0.fetch.TlbCycles 133419 # Number of cycles fetch has spent waiting for tlb 1218system.cpu0.fetch.MiscStallCycles 39139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1219system.cpu0.fetch.PendingTrapStallCycles 365906 # Number of stall cycles due to pending traps 1220system.cpu0.fetch.PendingQuiesceStallCycles 432078 # Number of stall cycles due to pending quiesce instructions 1221system.cpu0.fetch.IcacheWaitRetryStallCycles 38034 # Number of stall cycles due to full MSHR 1222system.cpu0.fetch.CacheLines 37750510 # Number of cache lines fetched 1223system.cpu0.fetch.IcacheSquashes 265510 # Number of outstanding Icache misses that were squashed 1224system.cpu0.fetch.ItlbSquashes 3919 # Number of outstanding ITLB misses that were squashed 1225system.cpu0.fetch.rateDist::samples 125351114 # Number of instructions fetched each cycle (Total) 1226system.cpu0.fetch.rateDist::mean 1.084784 # Number of instructions fetched each cycle (Total) 1227system.cpu0.fetch.rateDist::stdev 1.263056 # Number of instructions fetched each cycle (Total) |
| 1149system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1228system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1150system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total) 1151system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total) 1152system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total) 1153system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total) | 1229system.cpu0.fetch.rateDist::0 62795131 50.10% 50.10% # Number of instructions fetched each cycle (Total) 1230system.cpu0.fetch.rateDist::1 21461544 17.12% 67.22% # Number of instructions fetched each cycle (Total) 1231system.cpu0.fetch.rateDist::2 8765998 6.99% 74.21% # Number of instructions fetched each cycle (Total) 1232system.cpu0.fetch.rateDist::3 32328441 25.79% 100.00% # Number of instructions fetched each cycle (Total) |
| 1154system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1155system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1156system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1233system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1234system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1235system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1157system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total) 1158system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle 1159system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle 1160system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle 1161system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked 1162system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running 1163system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking 1164system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing 1165system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch 1166system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction 1167system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode 1168system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode 1169system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing 1170system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle 1171system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking 1172system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst 1173system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running 1174system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking 1175system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename 1176system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename 1177system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full 1178system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full 1179system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full 1180system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full 1181system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed 1182system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made 1183system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups 1184system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups 1185system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed 1186system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing 1187system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed 1188system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed 1189system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer 1190system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit. 1191system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit. 1192system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads. 1193system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores. 1194system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec) 1195system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ 1196system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued 1197system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued 1198system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling 1199system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph 1200system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed 1201system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle 1202system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle 1203system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle | 1236system.cpu0.fetch.rateDist::total 125351114 # Number of instructions fetched each cycle (Total) 1237system.cpu0.fetch.branchRate 0.189258 # Number of branch fetches per cycle 1238system.cpu0.fetch.rate 0.887792 # Number of inst fetches per cycle 1239system.cpu0.decode.IdleCycles 19217150 # Number of cycles decode is idle 1240system.cpu0.decode.BlockedCycles 58693987 # Number of cycles decode is blocked 1241system.cpu0.decode.RunCycles 41414238 # Number of cycles decode is running 1242system.cpu0.decode.UnblockCycles 4958351 # Number of cycles decode is unblocking 1243system.cpu0.decode.SquashCycles 1067388 # Number of cycles decode is squashing 1244system.cpu0.decode.BranchResolved 3055751 # Number of times decode resolved a branch 1245system.cpu0.decode.BranchMispred 348432 # Number of times decode detected a branch misprediction 1246system.cpu0.decode.DecodedInsts 110728193 # Number of instructions handled by decode 1247system.cpu0.decode.SquashedInsts 3997819 # Number of squashed instructions handled by decode 1248system.cpu0.rename.SquashCycles 1067388 # Number of cycles rename is squashing 1249system.cpu0.rename.IdleCycles 24968075 # Number of cycles rename is idle 1250system.cpu0.rename.BlockCycles 11998776 # Number of cycles rename is blocking 1251system.cpu0.rename.serializeStallCycles 36565512 # count of cycles rename stalled for serializing inst 1252system.cpu0.rename.RunCycles 40482982 # Number of cycles rename is running 1253system.cpu0.rename.UnblockCycles 10268381 # Number of cycles rename is unblocking 1254system.cpu0.rename.RenamedInsts 105647193 # Number of instructions processed by rename 1255system.cpu0.rename.SquashedInsts 1060681 # Number of squashed instructions processed by rename 1256system.cpu0.rename.ROBFullEvents 1440352 # Number of times rename has blocked due to ROB full 1257system.cpu0.rename.IQFullEvents 161094 # Number of times rename has blocked due to IQ full 1258system.cpu0.rename.LQFullEvents 60996 # Number of times rename has blocked due to LQ full 1259system.cpu0.rename.SQFullEvents 6068574 # Number of times rename has blocked due to SQ full 1260system.cpu0.rename.RenamedOperands 109731042 # Number of destination operands rename has renamed 1261system.cpu0.rename.RenameLookups 482381977 # Number of register rename lookups that rename has made 1262system.cpu0.rename.int_rename_lookups 120921551 # Number of integer rename lookups 1263system.cpu0.rename.fp_rename_lookups 9385 # Number of floating rename lookups 1264system.cpu0.rename.CommittedMaps 98136808 # Number of HB maps that are committed 1265system.cpu0.rename.UndoneMaps 11594231 # Number of HB maps that are undone due to squashing 1266system.cpu0.rename.serializingInsts 1228692 # count of serializing insts renamed 1267system.cpu0.rename.tempSerializingInsts 1087401 # count of temporary serializing insts renamed 1268system.cpu0.rename.skidInsts 12320869 # count of insts added to the skid buffer 1269system.cpu0.memDep0.insertedLoads 18735521 # Number of loads inserted to the mem dependence unit. 1270system.cpu0.memDep0.insertedStores 16202725 # Number of stores inserted to the mem dependence unit. 1271system.cpu0.memDep0.conflictingLoads 1699910 # Number of conflicting loads. 1272system.cpu0.memDep0.conflictingStores 2282844 # Number of conflicting stores. 1273system.cpu0.iq.iqInstsAdded 102687285 # Number of instructions added to the IQ (excludes non-spec) 1274system.cpu0.iq.iqNonSpecInstsAdded 1694390 # Number of non-speculative instructions added to the IQ 1275system.cpu0.iq.iqInstsIssued 100670059 # Number of instructions issued 1276system.cpu0.iq.iqSquashedInstsIssued 484670 # Number of squashed instructions issued 1277system.cpu0.iq.iqSquashedInstsExamined 9020348 # Number of squashed instructions iterated over during squash; mainly for profiling 1278system.cpu0.iq.iqSquashedOperandsExamined 22495673 # Number of squashed operands that are examined and possibly removed from graph 1279system.cpu0.iq.iqSquashedNonSpecRemoved 122680 # Number of squashed non-spec instructions that were removed 1280system.cpu0.iq.issued_per_cycle::samples 125351114 # Number of insts issued each cycle 1281system.cpu0.iq.issued_per_cycle::mean 0.803105 # Number of insts issued each cycle 1282system.cpu0.iq.issued_per_cycle::stdev 1.034773 # Number of insts issued each cycle |
| 1204system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1283system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1205system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle 1206system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle 1207system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle 1208system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle 1209system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle 1210system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle | 1284system.cpu0.iq.issued_per_cycle::0 69205207 55.21% 55.21% # Number of insts issued each cycle 1285system.cpu0.iq.issued_per_cycle::1 23183333 18.49% 73.70% # Number of insts issued each cycle 1286system.cpu0.iq.issued_per_cycle::2 22514733 17.96% 91.67% # Number of insts issued each cycle 1287system.cpu0.iq.issued_per_cycle::3 9334141 7.45% 99.11% # Number of insts issued each cycle 1288system.cpu0.iq.issued_per_cycle::4 1113663 0.89% 100.00% # Number of insts issued each cycle 1289system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle |
| 1211system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1212system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1213system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1214system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1215system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1216system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1290system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1291system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1292system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1293system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1294system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1295system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1217system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle | 1296system.cpu0.iq.issued_per_cycle::total 125351114 # Number of insts issued each cycle |
| 1218system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1297system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1219system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available 1220system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available 1221system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available 1222system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available 1223system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available 1224system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available 1225system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available 1226system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available 1227system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available 1228system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available 1229system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available 1230system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available 1231system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available 1232system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available 1233system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available 1234system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available 1235system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available 1236system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available 1237system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available 1238system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available 1239system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available 1240system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available 1241system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available 1242system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available 1243system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available 1244system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available 1245system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available 1246system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available 1247system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available 1248system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available 1249system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available | 1298system.cpu0.iq.fu_full::IntAlu 9379501 40.75% 40.75% # attempts to use FU when none available 1299system.cpu0.iq.fu_full::IntMult 82 0.00% 40.75% # attempts to use FU when none available 1300system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available 1301system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available 1302system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available 1303system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available 1304system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available 1305system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available 1306system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available 1307system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available 1308system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available 1309system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available 1310system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available 1311system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available 1312system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available 1313system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available 1314system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available 1315system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available 1316system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available 1317system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available 1318system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available 1319system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available 1320system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available 1321system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available 1322system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available 1323system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available 1324system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available 1325system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available 1326system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available 1327system.cpu0.iq.fu_full::MemRead 5582636 24.26% 65.01% # attempts to use FU when none available 1328system.cpu0.iq.fu_full::MemWrite 8053143 34.99% 100.00% # attempts to use FU when none available |
| 1250system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1251system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1329system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1330system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1252system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued 1253system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued 1254system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued 1255system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued 1256system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued 1257system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued 1258system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued 1259system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued 1260system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued 1261system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued 1262system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued 1263system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued 1264system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued 1265system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued 1266system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued 1267system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued 1268system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued 1269system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued 1270system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued 1271system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued 1272system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued 1273system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued 1274system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued 1275system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued 1276system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued 1277system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued 1278system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued 1279system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued 1280system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued 1281system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued 1282system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued 1283system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued | 1331system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued 1332system.cpu0.iq.FU_type_0::IntAlu 66409608 65.97% 65.97% # Type of FU issued 1333system.cpu0.iq.FU_type_0::IntMult 93111 0.09% 66.06% # Type of FU issued 1334system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued 1335system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued 1336system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 1337system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 1338system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 1339system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 1340system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 1341system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued 1342system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued 1343system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued 1344system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued 1345system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued 1346system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued 1347system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued 1348system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued 1349system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 1350system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 1351system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 1352system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 1353system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 1354system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 1355system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 1356system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued 1357system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued 1358system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued 1359system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued 1360system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued 1361system.cpu0.iq.FU_type_0::MemRead 18430675 18.31% 84.38% # Type of FU issued 1362system.cpu0.iq.FU_type_0::MemWrite 15726281 15.62% 100.00% # Type of FU issued |
| 1284system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1285system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1363system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1364system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1286system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued 1287system.cpu0.iq.rate 0.464855 # Inst issue rate 1288system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested 1289system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst) 1290system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads 1291system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes 1292system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses 1293system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads 1294system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes 1295system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses 1296system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses 1297system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses 1298system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores | 1365system.cpu0.iq.FU_type_0::total 100670059 # Type of FU issued 1366system.cpu0.iq.rate 0.792936 # Inst issue rate 1367system.cpu0.iq.fu_busy_cnt 23015362 # FU busy when requested 1368system.cpu0.iq.fu_busy_rate 0.228622 # FU busy rate (busy events/executed inst) 1369system.cpu0.iq.int_inst_queue_reads 350159403 # Number of integer instruction queue reads 1370system.cpu0.iq.int_inst_queue_writes 113409879 # Number of integer instruction queue writes 1371system.cpu0.iq.int_inst_queue_wakeup_accesses 98581657 # Number of integer instruction queue wakeup accesses 1372system.cpu0.iq.fp_inst_queue_reads 31861 # Number of floating instruction queue reads 1373system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes 1374system.cpu0.iq.fp_inst_queue_wakeup_accesses 9722 # Number of floating instruction queue wakeup accesses 1375system.cpu0.iq.int_alu_accesses 123662544 # Number of integer alu accesses 1376system.cpu0.iq.fp_alu_accesses 20604 # Number of floating point alu accesses 1377system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores |
| 1299system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1378system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1300system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed 1301system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed 1302system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations 1303system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed | 1379system.cpu0.iew.lsq.thread0.squashedLoads 2006423 # Number of loads squashed 1380system.cpu0.iew.lsq.thread0.ignoredResponses 2595 # Number of memory responses ignored because the instruction is squashed 1381system.cpu0.iew.lsq.thread0.memOrderViolation 19219 # Number of memory ordering violations 1382system.cpu0.iew.lsq.thread0.squashedStores 1022338 # Number of stores squashed |
| 1304system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1305system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1383system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1384system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1306system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled 1307system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked | 1385system.cpu0.iew.lsq.thread0.rescheduledLoads 106441 # Number of loads that were rescheduled 1386system.cpu0.iew.lsq.thread0.cacheBlocked 337136 # Number of times an access to memory failed due to the cache being blocked |
| 1308system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1387system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1309system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing 1310system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking 1311system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking 1312system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ | 1388system.cpu0.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing 1389system.cpu0.iew.iewBlockCycles 1615648 # Number of cycles IEW is blocking 1390system.cpu0.iew.iewUnblockCycles 188928 # Number of cycles IEW is unblocking 1391system.cpu0.iew.iewDispatchedInsts 104556414 # Number of instructions dispatched to IQ |
| 1313system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 1392system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 1314system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions 1315system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions 1316system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions 1317system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall 1318system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall 1319system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations 1320system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly 1321system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly 1322system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute 1323system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions 1324system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed 1325system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute | 1393system.cpu0.iew.iewDispLoadInsts 18735521 # Number of dispatched load instructions 1394system.cpu0.iew.iewDispStoreInsts 16202725 # Number of dispatched store instructions 1395system.cpu0.iew.iewDispNonSpecInsts 876047 # Number of dispatched non-speculative instructions 1396system.cpu0.iew.iewIQFullEvents 27263 # Number of times the IQ has become full, causing a stall 1397system.cpu0.iew.iewLSQFullEvents 138025 # Number of times the LSQ has become full, causing a stall 1398system.cpu0.iew.memOrderViolationEvents 19219 # Number of memory order violations 1399system.cpu0.iew.predictedTakenIncorrect 291871 # Number of branches that were predicted taken incorrectly 1400system.cpu0.iew.predictedNotTakenIncorrect 400586 # Number of branches that were predicted not taken incorrectly 1401system.cpu0.iew.branchMispredicts 692457 # Number of branch mispredicts detected at execute 1402system.cpu0.iew.iewExecutedInsts 99572602 # Number of executed instructions 1403system.cpu0.iew.iewExecLoadInsts 17974009 # Number of load instructions executed 1404system.cpu0.iew.iewExecSquashedInsts 1032494 # Number of squashed instructions skipped in execute |
| 1326system.cpu0.iew.exec_swp 0 # number of swp insts executed | 1405system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 1327system.cpu0.iew.exec_nop 102446 # number of nop insts executed 1328system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed 1329system.cpu0.iew.exec_branches 4700114 # Number of branches executed 1330system.cpu0.iew.exec_stores 5379801 # Number of stores executed 1331system.cpu0.iew.exec_rate 0.459648 # Inst execution rate 1332system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit 1333system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back 1334system.cpu0.iew.wb_producers 15739944 # num instructions producing a value 1335system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value | 1406system.cpu0.iew.exec_nop 174739 # number of nop insts executed 1407system.cpu0.iew.exec_refs 33508875 # number of memory reference insts executed 1408system.cpu0.iew.exec_branches 16843329 # Number of branches executed 1409system.cpu0.iew.exec_stores 15534866 # Number of stores executed 1410system.cpu0.iew.exec_rate 0.784292 # Inst execution rate 1411system.cpu0.iew.wb_sent 99041613 # cumulative count of insts sent to commit 1412system.cpu0.iew.wb_count 98591379 # cumulative count of insts written-back 1413system.cpu0.iew.wb_producers 51320038 # num instructions producing a value 1414system.cpu0.iew.wb_consumers 84796920 # num instructions consuming a value |
| 1336system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1415system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1337system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle 1338system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back | 1416system.cpu0.iew.wb_rate 0.776563 # insts written-back per cycle 1417system.cpu0.iew.wb_fanout 0.605211 # average fanout of values written-back |
| 1339system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1418system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1340system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit 1341system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards 1342system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted 1343system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle 1344system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle 1345system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle | 1419system.cpu0.commit.commitSquashedInsts 8526320 # The number of squashed insts skipped by commit 1420system.cpu0.commit.commitNonSpecStalls 1571710 # The number of times commit has been forced to stall to communicate backwards 1421system.cpu0.commit.branchMispredicts 633199 # The number of times a branch was mispredicted 1422system.cpu0.commit.committed_per_cycle::samples 123596989 # Number of insts commited each cycle 1423system.cpu0.commit.committed_per_cycle::mean 0.768069 # Number of insts commited each cycle 1424system.cpu0.commit.committed_per_cycle::stdev 1.480980 # Number of insts commited each cycle |
| 1346system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1425system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1347system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle 1348system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle 1349system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle 1350system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle 1351system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle 1352system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle 1353system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle 1354system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle 1355system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle | 1426system.cpu0.commit.committed_per_cycle::0 79268840 64.13% 64.13% # Number of insts commited each cycle 1427system.cpu0.commit.committed_per_cycle::1 24713999 20.00% 84.13% # Number of insts commited each cycle 1428system.cpu0.commit.committed_per_cycle::2 8247824 6.67% 90.80% # Number of insts commited each cycle 1429system.cpu0.commit.committed_per_cycle::3 3215855 2.60% 93.41% # Number of insts commited each cycle 1430system.cpu0.commit.committed_per_cycle::4 3439875 2.78% 96.19% # Number of insts commited each cycle 1431system.cpu0.commit.committed_per_cycle::5 1518279 1.23% 97.42% # Number of insts commited each cycle 1432system.cpu0.commit.committed_per_cycle::6 1140929 0.92% 98.34% # Number of insts commited each cycle 1433system.cpu0.commit.committed_per_cycle::7 533748 0.43% 98.77% # Number of insts commited each cycle 1434system.cpu0.commit.committed_per_cycle::8 1517640 1.23% 100.00% # Number of insts commited each cycle |
| 1356system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1357system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1358system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1435system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1436system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1437system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1359system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle 1360system.cpu0.commit.committedInsts 24068410 # Number of instructions committed 1361system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed | 1438system.cpu0.commit.committed_per_cycle::total 123596989 # Number of insts commited each cycle 1439system.cpu0.commit.committedInsts 78900966 # Number of instructions committed 1440system.cpu0.commit.committedOps 94931037 # Number of ops (including micro ops) committed |
| 1362system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 1441system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 1363system.cpu0.commit.refs 10570507 # Number of memory references committed 1364system.cpu0.commit.loads 5342633 # Number of loads committed 1365system.cpu0.commit.membars 231974 # Number of memory barriers committed 1366system.cpu0.commit.branches 4351471 # Number of branches committed 1367system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 1368system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions. 1369system.cpu0.commit.function_calls 499778 # Number of function calls committed. | 1442system.cpu0.commit.refs 31909485 # Number of memory references committed 1443system.cpu0.commit.loads 16729098 # Number of loads committed 1444system.cpu0.commit.membars 647159 # Number of memory barriers committed 1445system.cpu0.commit.branches 16205509 # Number of branches committed 1446system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. 1447system.cpu0.commit.int_insts 81880566 # Number of committed integer instructions. 1448system.cpu0.commit.function_calls 1929583 # Number of function calls committed. |
| 1370system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 1449system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 1371system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction 1372system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction 1373system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction 1374system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction 1375system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction 1376system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction 1377system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction 1378system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction 1379system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction 1380system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction 1381system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction 1382system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction 1383system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction 1384system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction 1385system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction 1386system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction 1387system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction 1388system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction 1389system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction 1390system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction 1391system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction 1392system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction 1393system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction 1394system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction 1395system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction 1396system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction 1397system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction 1398system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction 1399system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction 1400system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction 1401system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction | 1450system.cpu0.commit.op_class_0::IntAlu 62922752 66.28% 66.28% # Class of committed instruction 1451system.cpu0.commit.op_class_0::IntMult 90691 0.10% 66.38% # Class of committed instruction 1452system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 1453system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 1454system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 1455system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 1456system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 1457system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 1458system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 1459system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction 1460system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction 1461system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction 1462system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction 1463system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction 1464system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction 1465system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction 1466system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction 1467system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 1468system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 1469system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 1470system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 1471system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 1472system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 1473system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 1474system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction 1475system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction 1476system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction 1477system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction 1478system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction 1479system.cpu0.commit.op_class_0::MemRead 16729098 17.62% 84.01% # Class of committed instruction 1480system.cpu0.commit.op_class_0::MemWrite 15180387 15.99% 100.00% # Class of committed instruction |
| 1402system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1403system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1481system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1482system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1404system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction 1405system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached | 1483system.cpu0.commit.op_class_0::total 94931037 # Class of committed instruction 1484system.cpu0.commit.bw_lim_events 1517640 # number cycles where commit BW limit reached |
| 1406system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 1485system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1407system.cpu0.rob.rob_reads 99997744 # The number of ROB reads 1408system.cpu0.rob.rob_writes 65895627 # The number of ROB writes 1409system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself 1410system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling 1411system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1412system.cpu0.committedInsts 23987668 # Number of Instructions Simulated 1413system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated 1414system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction 1415system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads 1416system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle 1417system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads 1418system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads 1419system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes 1420system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads 1421system.cpu0.fp_regfile_writes 840 # number of floating regfile writes 1422system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads 1423system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes 1424system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads 1425system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes 1426system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution 1427system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution 1428system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution 1429system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution 1430system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution 1431system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution 1432system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution 1433system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution 1434system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution 1435system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution 1436system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution 1437system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution 1438system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution 1439system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes) 1440system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes) 1441system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes) 1442system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes) 1443system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes) 1444system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes) 1445system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes) 1446system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes) 1447system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes) 1448system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes) 1449system.cpu0.toL2Bus.snoops 640729 # Total snoops (count) 1450system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram 1451system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram 1452system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram | 1486system.cpu0.rob.rob_reads 221353668 # The number of ROB reads 1487system.cpu0.rob.rob_writes 208668086 # The number of ROB writes 1488system.cpu0.timesIdled 109562 # Number of times that the entire CPU went into an idle state and unscheduled itself 1489system.cpu0.idleCycles 1607527 # Total number of cycles that the CPU has spent unscheduled due to idling 1490system.cpu0.quiesceCycles 5521753720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1491system.cpu0.committedInsts 78778915 # Number of Instructions Simulated 1492system.cpu0.committedOps 94808986 # Number of Ops (including micro ops) Simulated 1493system.cpu0.cpi 1.611581 # CPI: Cycles Per Instruction 1494system.cpu0.cpi_total 1.611581 # CPI: Total CPI of All Threads 1495system.cpu0.ipc 0.620508 # IPC: Instructions Per Cycle 1496system.cpu0.ipc_total 0.620508 # IPC: Total IPC of All Threads 1497system.cpu0.int_regfile_reads 110614815 # number of integer regfile reads 1498system.cpu0.int_regfile_writes 59737885 # number of integer regfile writes 1499system.cpu0.fp_regfile_reads 8165 # number of floating regfile reads 1500system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes 1501system.cpu0.cc_regfile_reads 350771001 # number of cc regfile reads 1502system.cpu0.cc_regfile_writes 41073809 # number of cc regfile writes 1503system.cpu0.misc_regfile_reads 245697526 # number of misc regfile reads 1504system.cpu0.misc_regfile_writes 1224542 # number of misc regfile writes 1505system.cpu0.toL2Bus.trans_dist::ReadReq 2022292 # Transaction distribution 1506system.cpu0.toL2Bus.trans_dist::ReadResp 1921231 # Transaction distribution 1507system.cpu0.toL2Bus.trans_dist::WriteReq 19109 # Transaction distribution 1508system.cpu0.toL2Bus.trans_dist::WriteResp 19109 # Transaction distribution 1509system.cpu0.toL2Bus.trans_dist::Writeback 512497 # Transaction distribution 1510system.cpu0.toL2Bus.trans_dist::HardPFReq 635775 # Transaction distribution 1511system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution 1512system.cpu0.toL2Bus.trans_dist::UpgradeReq 81120 # Transaction distribution 1513system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43298 # Transaction distribution 1514system.cpu0.toL2Bus.trans_dist::UpgradeResp 105236 # Transaction distribution 1515system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 1516system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution 1517system.cpu0.toL2Bus.trans_dist::ReadExReq 291864 # Transaction distribution 1518system.cpu0.toL2Bus.trans_dist::ReadExResp 281152 # Transaction distribution 1519system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2535030 # Packet count per connected master and slave (bytes) 1520system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2361050 # Packet count per connected master and slave (bytes) 1521system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28910 # Packet count per connected master and slave (bytes) 1522system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120430 # Packet count per connected master and slave (bytes) 1523system.cpu0.toL2Bus.pkt_count::total 5045420 # Packet count per connected master and slave (bytes) 1524system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80976096 # Cumulative packet size per connected master and slave (bytes) 1525system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86183658 # Cumulative packet size per connected master and slave (bytes) 1526system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50232 # Cumulative packet size per connected master and slave (bytes) 1527system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218780 # Cumulative packet size per connected master and slave (bytes) 1528system.cpu0.toL2Bus.pkt_size::total 167428766 # Cumulative packet size per connected master and slave (bytes) 1529system.cpu0.toL2Bus.snoops 1029243 # Total snoops (count) 1530system.cpu0.toL2Bus.snoop_fanout::samples 3600041 # Request fanout histogram 1531system.cpu0.toL2Bus.snoop_fanout::mean 5.252406 # Request fanout histogram 1532system.cpu0.toL2Bus.snoop_fanout::stdev 0.434393 # Request fanout histogram |
| 1453system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1454system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1455system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1456system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1457system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1458system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1533system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1534system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1535system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1536system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1537system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1538system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1459system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram 1460system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram | 1539system.cpu0.toL2Bus.snoop_fanout::5 2691370 74.76% 74.76% # Request fanout histogram 1540system.cpu0.toL2Bus.snoop_fanout::6 908671 25.24% 100.00% # Request fanout histogram |
| 1461system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1462system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1463system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1541system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1542system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1543system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1464system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram 1465system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks) 1466system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1467system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks) | 1544system.cpu0.toL2Bus.snoop_fanout::total 3600041 # Request fanout histogram 1545system.cpu0.toL2Bus.reqLayer0.occupancy 1889888022 # Layer occupancy (ticks) 1546system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1547system.cpu0.toL2Bus.snoopLayer0.occupancy 117489749 # Layer occupancy (ticks) |
| 1468system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1548system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1469system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks) 1470system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1471system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks) | 1549system.cpu0.toL2Bus.respLayer0.occupancy 1901826585 # Layer occupancy (ticks) 1550system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1551system.cpu0.toL2Bus.respLayer1.occupancy 1220473591 # Layer occupancy (ticks) |
| 1472system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1552system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1473system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks) | 1553system.cpu0.toL2Bus.respLayer2.occupancy 16363478 # Layer occupancy (ticks) |
| 1474system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1554system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1475system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks) | 1555system.cpu0.toL2Bus.respLayer3.occupancy 65772430 # Layer occupancy (ticks) |
| 1476system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1556system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1477system.cpu0.icache.tags.replacements 322116 # number of replacements 1478system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use 1479system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks. 1480system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks. 1481system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks. 1482system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit. 1483system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor 1484system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy 1485system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy | 1557system.cpu0.icache.tags.replacements 1263981 # number of replacements 1558system.cpu0.icache.tags.tagsinuse 511.774384 # Cycle average of tags in use 1559system.cpu0.icache.tags.total_refs 36445999 # Total number of references to valid blocks. 1560system.cpu0.icache.tags.sampled_refs 1264493 # Sample count of references to valid blocks. 1561system.cpu0.icache.tags.avg_refs 28.822618 # Average number of references to valid blocks. 1562system.cpu0.icache.tags.warmup_cycle 6310719000 # Cycle when the warmup percentage was hit. 1563system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774384 # Average occupied blocks per requestor 1564system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy 1565system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy |
| 1486system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1566system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1487system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 1488system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 1489system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 1490system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 1567system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 1568system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id 1569system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id |
| 1491system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1570system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1492system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses 1493system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses 1494system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits 1495system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits 1496system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits 1497system.cpu0.icache.demand_hits::total 10915164 # number of demand (read+write) hits 1498system.cpu0.icache.overall_hits::cpu0.inst 10915164 # number of overall hits 1499system.cpu0.icache.overall_hits::total 10915164 # number of overall hits 1500system.cpu0.icache.ReadReq_misses::cpu0.inst 334091 # number of ReadReq misses 1501system.cpu0.icache.ReadReq_misses::total 334091 # number of ReadReq misses 1502system.cpu0.icache.demand_misses::cpu0.inst 334091 # number of demand (read+write) misses 1503system.cpu0.icache.demand_misses::total 334091 # number of demand (read+write) misses 1504system.cpu0.icache.overall_misses::cpu0.inst 334091 # number of overall misses 1505system.cpu0.icache.overall_misses::total 334091 # number of overall misses 1506system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863305358 # number of ReadReq miss cycles 1507system.cpu0.icache.ReadReq_miss_latency::total 2863305358 # number of ReadReq miss cycles 1508system.cpu0.icache.demand_miss_latency::cpu0.inst 2863305358 # number of demand (read+write) miss cycles 1509system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles 1510system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles 1511system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles 1512system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses) 1513system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses) 1514system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses 1515system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses 1516system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses 1517system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses 1518system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses 1519system.cpu0.icache.ReadReq_miss_rate::total 0.029699 # miss rate for ReadReq accesses 1520system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029699 # miss rate for demand accesses 1521system.cpu0.icache.demand_miss_rate::total 0.029699 # miss rate for demand accesses 1522system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029699 # miss rate for overall accesses 1523system.cpu0.icache.overall_miss_rate::total 0.029699 # miss rate for overall accesses 1524system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8570.435474 # average ReadReq miss latency 1525system.cpu0.icache.ReadReq_avg_miss_latency::total 8570.435474 # average ReadReq miss latency 1526system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency 1527system.cpu0.icache.demand_avg_miss_latency::total 8570.435474 # average overall miss latency 1528system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency 1529system.cpu0.icache.overall_avg_miss_latency::total 8570.435474 # average overall miss latency 1530system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked 1531system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked 1532system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked 1533system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked 1534system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked 1535system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked | 1571system.cpu0.icache.tags.tag_accesses 76759130 # Number of tag accesses 1572system.cpu0.icache.tags.data_accesses 76759130 # Number of data accesses 1573system.cpu0.icache.ReadReq_hits::cpu0.inst 36445999 # number of ReadReq hits 1574system.cpu0.icache.ReadReq_hits::total 36445999 # number of ReadReq hits 1575system.cpu0.icache.demand_hits::cpu0.inst 36445999 # number of demand (read+write) hits 1576system.cpu0.icache.demand_hits::total 36445999 # number of demand (read+write) hits 1577system.cpu0.icache.overall_hits::cpu0.inst 36445999 # number of overall hits 1578system.cpu0.icache.overall_hits::total 36445999 # number of overall hits 1579system.cpu0.icache.ReadReq_misses::cpu0.inst 1301304 # number of ReadReq misses 1580system.cpu0.icache.ReadReq_misses::total 1301304 # number of ReadReq misses 1581system.cpu0.icache.demand_misses::cpu0.inst 1301304 # number of demand (read+write) misses 1582system.cpu0.icache.demand_misses::total 1301304 # number of demand (read+write) misses 1583system.cpu0.icache.overall_misses::cpu0.inst 1301304 # number of overall misses 1584system.cpu0.icache.overall_misses::total 1301304 # number of overall misses 1585system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11020664802 # number of ReadReq miss cycles 1586system.cpu0.icache.ReadReq_miss_latency::total 11020664802 # number of ReadReq miss cycles 1587system.cpu0.icache.demand_miss_latency::cpu0.inst 11020664802 # number of demand (read+write) miss cycles 1588system.cpu0.icache.demand_miss_latency::total 11020664802 # number of demand (read+write) miss cycles 1589system.cpu0.icache.overall_miss_latency::cpu0.inst 11020664802 # number of overall miss cycles 1590system.cpu0.icache.overall_miss_latency::total 11020664802 # number of overall miss cycles 1591system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747303 # number of ReadReq accesses(hits+misses) 1592system.cpu0.icache.ReadReq_accesses::total 37747303 # number of ReadReq accesses(hits+misses) 1593system.cpu0.icache.demand_accesses::cpu0.inst 37747303 # number of demand (read+write) accesses 1594system.cpu0.icache.demand_accesses::total 37747303 # number of demand (read+write) accesses 1595system.cpu0.icache.overall_accesses::cpu0.inst 37747303 # number of overall (read+write) accesses 1596system.cpu0.icache.overall_accesses::total 37747303 # number of overall (read+write) accesses 1597system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034474 # miss rate for ReadReq accesses 1598system.cpu0.icache.ReadReq_miss_rate::total 0.034474 # miss rate for ReadReq accesses 1599system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034474 # miss rate for demand accesses 1600system.cpu0.icache.demand_miss_rate::total 0.034474 # miss rate for demand accesses 1601system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034474 # miss rate for overall accesses 1602system.cpu0.icache.overall_miss_rate::total 0.034474 # miss rate for overall accesses 1603system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.939465 # average ReadReq miss latency 1604system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.939465 # average ReadReq miss latency 1605system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency 1606system.cpu0.icache.demand_avg_miss_latency::total 8468.939465 # average overall miss latency 1607system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency 1608system.cpu0.icache.overall_avg_miss_latency::total 8468.939465 # average overall miss latency 1609system.cpu0.icache.blocked_cycles::no_mshrs 725662 # number of cycles access was blocked 1610system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked 1611system.cpu0.icache.blocked::no_mshrs 96193 # number of cycles access was blocked 1612system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked 1613system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.543813 # average number of cycles each access was blocked 1614system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked |
| 1536system.cpu0.icache.fast_writes 0 # number of fast writes performed 1537system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1615system.cpu0.icache.fast_writes 0 # number of fast writes performed 1616system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1538system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits 1539system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits 1540system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits 1541system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits 1542system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits 1543system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits 1544system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses 1545system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses 1546system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses 1547system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses 1548system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses 1549system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses 1550system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles 1551system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles 1552system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles 1553system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles 1554system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles 1555system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles 1556system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles 1557system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 272886999 # number of ReadReq MSHR uncacheable cycles 1558system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 272886999 # number of overall MSHR uncacheable cycles 1559system.cpu0.icache.overall_mshr_uncacheable_latency::total 272886999 # number of overall MSHR uncacheable cycles 1560system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for ReadReq accesses 1561system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028681 # mshr miss rate for ReadReq accesses 1562system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for demand accesses 1563system.cpu0.icache.demand_mshr_miss_rate::total 0.028681 # mshr miss rate for demand accesses 1564system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for overall accesses 1565system.cpu0.icache.overall_mshr_miss_rate::total 0.028681 # mshr miss rate for overall accesses 1566system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average ReadReq mshr miss latency 1567system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency 1568system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency 1569system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency 1570system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency 1571system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency | 1617system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36779 # number of ReadReq MSHR hits 1618system.cpu0.icache.ReadReq_mshr_hits::total 36779 # number of ReadReq MSHR hits 1619system.cpu0.icache.demand_mshr_hits::cpu0.inst 36779 # number of demand (read+write) MSHR hits 1620system.cpu0.icache.demand_mshr_hits::total 36779 # number of demand (read+write) MSHR hits 1621system.cpu0.icache.overall_mshr_hits::cpu0.inst 36779 # number of overall MSHR hits 1622system.cpu0.icache.overall_mshr_hits::total 36779 # number of overall MSHR hits 1623system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264525 # number of ReadReq MSHR misses 1624system.cpu0.icache.ReadReq_mshr_misses::total 1264525 # number of ReadReq MSHR misses 1625system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264525 # number of demand (read+write) MSHR misses 1626system.cpu0.icache.demand_mshr_misses::total 1264525 # number of demand (read+write) MSHR misses 1627system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264525 # number of overall MSHR misses 1628system.cpu0.icache.overall_mshr_misses::total 1264525 # number of overall MSHR misses 1629system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8921757516 # number of ReadReq MSHR miss cycles 1630system.cpu0.icache.ReadReq_mshr_miss_latency::total 8921757516 # number of ReadReq MSHR miss cycles 1631system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8921757516 # number of demand (read+write) MSHR miss cycles 1632system.cpu0.icache.demand_mshr_miss_latency::total 8921757516 # number of demand (read+write) MSHR miss cycles 1633system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8921757516 # number of overall MSHR miss cycles 1634system.cpu0.icache.overall_mshr_miss_latency::total 8921757516 # number of overall MSHR miss cycles 1635system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243776998 # number of ReadReq MSHR uncacheable cycles 1636system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243776998 # number of ReadReq MSHR uncacheable cycles 1637system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243776998 # number of overall MSHR uncacheable cycles 1638system.cpu0.icache.overall_mshr_uncacheable_latency::total 243776998 # number of overall MSHR uncacheable cycles 1639system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for ReadReq accesses 1640system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033500 # mshr miss rate for ReadReq accesses 1641system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for demand accesses 1642system.cpu0.icache.demand_mshr_miss_rate::total 0.033500 # mshr miss rate for demand accesses 1643system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for overall accesses 1644system.cpu0.icache.overall_mshr_miss_rate::total 0.033500 # mshr miss rate for overall accesses 1645system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average ReadReq mshr miss latency 1646system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7055.422009 # average ReadReq mshr miss latency 1647system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency 1648system.cpu0.icache.demand_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency 1649system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency 1650system.cpu0.icache.overall_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency |
| 1572system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1573system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1574system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1575system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1576system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1651system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1652system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1653system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1654system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1655system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1577system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified 1578system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr 1579system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache 1580system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue | 1656system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11570902 # number of hwpf identified 1657system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525454 # number of hwpf that were already in mshr 1658system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10431616 # number of hwpf that were already in the cache 1659system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 117790 # number of hwpf that were already in the prefetch queue |
| 1581system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1660system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1582system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated 1583system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued 1584system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page | 1661system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25307 # number of hwpf removed because MSHR allocated 1662system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 470730 # number of hwpf issued 1663system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881250 # number of hwpf spanning a virtual page |
| 1585system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1664system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1586system.cpu0.l2cache.tags.replacements 165160 # number of replacements 1587system.cpu0.l2cache.tags.tagsinuse 15951.411231 # Cycle average of tags in use 1588system.cpu0.l2cache.tags.total_refs 747099 # Total number of references to valid blocks. 1589system.cpu0.l2cache.tags.sampled_refs 181321 # Sample count of references to valid blocks. 1590system.cpu0.l2cache.tags.avg_refs 4.120311 # Average number of references to valid blocks. 1591system.cpu0.l2cache.tags.warmup_cycle 4999805500 # Cycle when the warmup percentage was hit. 1592system.cpu0.l2cache.tags.occ_blocks::writebacks 4772.372752 # Average occupied blocks per requestor 1593system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.637155 # Average occupied blocks per requestor 1594system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.084033 # Average occupied blocks per requestor 1595system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor 1596system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor 1597system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor 1598system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy 1599system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy 1600system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy 1601system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy 1602system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy 1603system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy 1604system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy 1605system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id 1606system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id 1607system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8811 # Occupied blocks per task id 1608system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id 1609system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id 1610system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1027 # Occupied blocks per task id 1611system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id 1612system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 943 # Occupied blocks per task id 1613system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1614system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1615system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 1616system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1617system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id 1618system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id 1619system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6017 # Occupied blocks per task id 1620system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id 1621system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.447876 # Percentage of cache occupancy per task id 1622system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 1623system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.537781 # Percentage of cache occupancy per task id 1624system.cpu0.l2cache.tags.tag_accesses 15517001 # Number of tag accesses 1625system.cpu0.l2cache.tags.data_accesses 15517001 # Number of data accesses 1626system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 19658 # number of ReadReq hits 1627system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6554 # number of ReadReq hits 1628system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314769 # number of ReadReq hits 1629system.cpu0.l2cache.ReadReq_hits::cpu0.data 162769 # number of ReadReq hits 1630system.cpu0.l2cache.ReadReq_hits::total 503750 # number of ReadReq hits 1631system.cpu0.l2cache.Writeback_hits::writebacks 228045 # number of Writeback hits 1632system.cpu0.l2cache.Writeback_hits::total 228045 # number of Writeback hits 1633system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6593 # number of UpgradeReq hits 1634system.cpu0.l2cache.UpgradeReq_hits::total 6593 # number of UpgradeReq hits 1635system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 622 # number of SCUpgradeReq hits 1636system.cpu0.l2cache.SCUpgradeReq_hits::total 622 # number of SCUpgradeReq hits 1637system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95529 # number of ReadExReq hits 1638system.cpu0.l2cache.ReadExReq_hits::total 95529 # number of ReadExReq hits 1639system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 19658 # number of demand (read+write) hits 1640system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6554 # number of demand (read+write) hits 1641system.cpu0.l2cache.demand_hits::cpu0.inst 314769 # number of demand (read+write) hits 1642system.cpu0.l2cache.demand_hits::cpu0.data 258298 # number of demand (read+write) hits 1643system.cpu0.l2cache.demand_hits::total 599279 # number of demand (read+write) hits 1644system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 19658 # number of overall hits 1645system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6554 # number of overall hits 1646system.cpu0.l2cache.overall_hits::cpu0.inst 314769 # number of overall hits 1647system.cpu0.l2cache.overall_hits::cpu0.data 258298 # number of overall hits 1648system.cpu0.l2cache.overall_hits::total 599279 # number of overall hits 1649system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 345 # number of ReadReq misses 1650system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses 1651system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7801 # number of ReadReq misses 1652system.cpu0.l2cache.ReadReq_misses::cpu0.data 50805 # number of ReadReq misses 1653system.cpu0.l2cache.ReadReq_misses::total 59122 # number of ReadReq misses 1654system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses 1655system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses 1656system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19680 # number of UpgradeReq misses 1657system.cpu0.l2cache.UpgradeReq_misses::total 19680 # number of UpgradeReq misses 1658system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10856 # number of SCUpgradeReq misses 1659system.cpu0.l2cache.SCUpgradeReq_misses::total 10856 # number of SCUpgradeReq misses 1660system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1661system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1662system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23597 # number of ReadExReq misses 1663system.cpu0.l2cache.ReadExReq_misses::total 23597 # number of ReadExReq misses 1664system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 345 # number of demand (read+write) misses 1665system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses 1666system.cpu0.l2cache.demand_misses::cpu0.inst 7801 # number of demand (read+write) misses 1667system.cpu0.l2cache.demand_misses::cpu0.data 74402 # number of demand (read+write) misses 1668system.cpu0.l2cache.demand_misses::total 82719 # number of demand (read+write) misses 1669system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 345 # number of overall misses 1670system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses 1671system.cpu0.l2cache.overall_misses::cpu0.inst 7801 # number of overall misses 1672system.cpu0.l2cache.overall_misses::cpu0.data 74402 # number of overall misses 1673system.cpu0.l2cache.overall_misses::total 82719 # number of overall misses 1674system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7498249 # number of ReadReq miss cycles 1675system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3753000 # number of ReadReq miss cycles 1676system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 255179729 # number of ReadReq miss cycles 1677system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1303745054 # number of ReadReq miss cycles 1678system.cpu0.l2cache.ReadReq_miss_latency::total 1570176032 # number of ReadReq miss cycles 1679system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 310997961 # number of UpgradeReq miss cycles 1680system.cpu0.l2cache.UpgradeReq_miss_latency::total 310997961 # number of UpgradeReq miss cycles 1681system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 212766148 # number of SCUpgradeReq miss cycles 1682system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 212766148 # number of SCUpgradeReq miss cycles 1683system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 609000 # number of SCUpgradeFailReq miss cycles 1684system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 609000 # number of SCUpgradeFailReq miss cycles 1685system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 893661798 # number of ReadExReq miss cycles 1686system.cpu0.l2cache.ReadExReq_miss_latency::total 893661798 # number of ReadExReq miss cycles 1687system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7498249 # number of demand (read+write) miss cycles 1688system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3753000 # number of demand (read+write) miss cycles 1689system.cpu0.l2cache.demand_miss_latency::cpu0.inst 255179729 # number of demand (read+write) miss cycles 1690system.cpu0.l2cache.demand_miss_latency::cpu0.data 2197406852 # number of demand (read+write) miss cycles 1691system.cpu0.l2cache.demand_miss_latency::total 2463837830 # number of demand (read+write) miss cycles 1692system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7498249 # number of overall miss cycles 1693system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3753000 # number of overall miss cycles 1694system.cpu0.l2cache.overall_miss_latency::cpu0.inst 255179729 # number of overall miss cycles 1695system.cpu0.l2cache.overall_miss_latency::cpu0.data 2197406852 # number of overall miss cycles 1696system.cpu0.l2cache.overall_miss_latency::total 2463837830 # number of overall miss cycles 1697system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20003 # number of ReadReq accesses(hits+misses) 1698system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6725 # number of ReadReq accesses(hits+misses) 1699system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322570 # number of ReadReq accesses(hits+misses) 1700system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213574 # number of ReadReq accesses(hits+misses) 1701system.cpu0.l2cache.ReadReq_accesses::total 562872 # number of ReadReq accesses(hits+misses) 1702system.cpu0.l2cache.Writeback_accesses::writebacks 228050 # number of Writeback accesses(hits+misses) 1703system.cpu0.l2cache.Writeback_accesses::total 228050 # number of Writeback accesses(hits+misses) 1704system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) 1705system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) 1706system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11478 # number of SCUpgradeReq accesses(hits+misses) 1707system.cpu0.l2cache.SCUpgradeReq_accesses::total 11478 # number of SCUpgradeReq accesses(hits+misses) 1708system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1709system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1710system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119126 # number of ReadExReq accesses(hits+misses) 1711system.cpu0.l2cache.ReadExReq_accesses::total 119126 # number of ReadExReq accesses(hits+misses) 1712system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20003 # number of demand (read+write) accesses 1713system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6725 # number of demand (read+write) accesses 1714system.cpu0.l2cache.demand_accesses::cpu0.inst 322570 # number of demand (read+write) accesses 1715system.cpu0.l2cache.demand_accesses::cpu0.data 332700 # number of demand (read+write) accesses 1716system.cpu0.l2cache.demand_accesses::total 681998 # number of demand (read+write) accesses 1717system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20003 # number of overall (read+write) accesses 1718system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6725 # number of overall (read+write) accesses 1719system.cpu0.l2cache.overall_accesses::cpu0.inst 322570 # number of overall (read+write) accesses 1720system.cpu0.l2cache.overall_accesses::cpu0.data 332700 # number of overall (read+write) accesses 1721system.cpu0.l2cache.overall_accesses::total 681998 # number of overall (read+write) accesses 1722system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for ReadReq accesses 1723system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025428 # miss rate for ReadReq accesses 1724system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024184 # miss rate for ReadReq accesses 1725system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.237880 # miss rate for ReadReq accesses 1726system.cpu0.l2cache.ReadReq_miss_rate::total 0.105036 # miss rate for ReadReq accesses 1727system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000022 # miss rate for Writeback accesses 1728system.cpu0.l2cache.Writeback_miss_rate::total 0.000022 # miss rate for Writeback accesses 1729system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.749058 # miss rate for UpgradeReq accesses 1730system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses 1731system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.945809 # miss rate for SCUpgradeReq accesses 1732system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.945809 # miss rate for SCUpgradeReq accesses 1733system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1734system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1735system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198084 # miss rate for ReadExReq accesses 1736system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198084 # miss rate for ReadExReq accesses 1737system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for demand accesses 1738system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025428 # miss rate for demand accesses 1739system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024184 # miss rate for demand accesses 1740system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223631 # miss rate for demand accesses 1741system.cpu0.l2cache.demand_miss_rate::total 0.121289 # miss rate for demand accesses 1742system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for overall accesses 1743system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025428 # miss rate for overall accesses 1744system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024184 # miss rate for overall accesses 1745system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223631 # miss rate for overall accesses 1746system.cpu0.l2cache.overall_miss_rate::total 0.121289 # miss rate for overall accesses 1747system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average ReadReq miss latency 1748system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21947.368421 # average ReadReq miss latency 1749system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32711.156134 # average ReadReq miss latency 1750system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency 1751system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26558.236054 # average ReadReq miss latency 1752system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15802.741921 # average UpgradeReq miss latency 1753system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency 1754system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19598.945099 # average SCUpgradeReq miss latency 1755system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency 1756system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 609000 # average SCUpgradeFailReq miss latency 1757system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 609000 # average SCUpgradeFailReq miss latency 1758system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37871.839556 # average ReadExReq miss latency 1759system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37871.839556 # average ReadExReq miss latency 1760system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency 1761system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency 1762system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency 1763system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency 1764system.cpu0.l2cache.demand_avg_miss_latency::total 29785.633651 # average overall miss latency 1765system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency 1766system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency 1767system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency 1768system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency 1769system.cpu0.l2cache.overall_avg_miss_latency::total 29785.633651 # average overall miss latency 1770system.cpu0.l2cache.blocked_cycles::no_mshrs 4781 # number of cycles access was blocked | 1665system.cpu0.l2cache.tags.replacements 397283 # number of replacements 1666system.cpu0.l2cache.tags.tagsinuse 16205.229139 # Cycle average of tags in use 1667system.cpu0.l2cache.tags.total_refs 2244912 # Total number of references to valid blocks. 1668system.cpu0.l2cache.tags.sampled_refs 413530 # Sample count of references to valid blocks. 1669system.cpu0.l2cache.tags.avg_refs 5.428656 # Average number of references to valid blocks. 1670system.cpu0.l2cache.tags.warmup_cycle 2809069613500 # Cycle when the warmup percentage was hit. 1671system.cpu0.l2cache.tags.occ_blocks::writebacks 4639.805304 # Average occupied blocks per requestor 1672system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.151524 # Average occupied blocks per requestor 1673system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.649414 # Average occupied blocks per requestor 1674system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 948.692737 # Average occupied blocks per requestor 1675system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.057987 # Average occupied blocks per requestor 1676system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9191.872173 # Average occupied blocks per requestor 1677system.cpu0.l2cache.tags.occ_percent::writebacks 0.283191 # Average percentage of cache occupancy 1678system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000803 # Average percentage of cache occupancy 1679system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy 1680system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057904 # Average percentage of cache occupancy 1681system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086063 # Average percentage of cache occupancy 1682system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.561027 # Average percentage of cache occupancy 1683system.cpu0.l2cache.tags.occ_percent::total 0.989089 # Average percentage of cache occupancy 1684system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8152 # Occupied blocks per task id 1685system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 1686system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8085 # Occupied blocks per task id 1687system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id 1688system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 237 # Occupied blocks per task id 1689system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3322 # Occupied blocks per task id 1690system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4084 # Occupied blocks per task id 1691system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id 1692system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1693system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1694system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1695system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1696system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 501 # Occupied blocks per task id 1697system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3682 # Occupied blocks per task id 1698system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3594 # Occupied blocks per task id 1699system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 245 # Occupied blocks per task id 1700system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.497559 # Percentage of cache occupancy per task id 1701system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 1702system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.493469 # Percentage of cache occupancy per task id 1703system.cpu0.l2cache.tags.tag_accesses 43590224 # Number of tag accesses 1704system.cpu0.l2cache.tags.data_accesses 43590224 # Number of data accesses 1705system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54156 # number of ReadReq hits 1706system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12330 # number of ReadReq hits 1707system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242747 # number of ReadReq hits 1708system.cpu0.l2cache.ReadReq_hits::cpu0.data 407291 # number of ReadReq hits 1709system.cpu0.l2cache.ReadReq_hits::total 1716524 # number of ReadReq hits 1710system.cpu0.l2cache.Writeback_hits::writebacks 512497 # number of Writeback hits 1711system.cpu0.l2cache.Writeback_hits::total 512497 # number of Writeback hits 1712system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15462 # number of UpgradeReq hits 1713system.cpu0.l2cache.UpgradeReq_hits::total 15462 # number of UpgradeReq hits 1714system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2188 # number of SCUpgradeReq hits 1715system.cpu0.l2cache.SCUpgradeReq_hits::total 2188 # number of SCUpgradeReq hits 1716system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216542 # number of ReadExReq hits 1717system.cpu0.l2cache.ReadExReq_hits::total 216542 # number of ReadExReq hits 1718system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54156 # number of demand (read+write) hits 1719system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12330 # number of demand (read+write) hits 1720system.cpu0.l2cache.demand_hits::cpu0.inst 1242747 # number of demand (read+write) hits 1721system.cpu0.l2cache.demand_hits::cpu0.data 623833 # number of demand (read+write) hits 1722system.cpu0.l2cache.demand_hits::total 1933066 # number of demand (read+write) hits 1723system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54156 # number of overall hits 1724system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12330 # number of overall hits 1725system.cpu0.l2cache.overall_hits::cpu0.inst 1242747 # number of overall hits 1726system.cpu0.l2cache.overall_hits::cpu0.data 623833 # number of overall hits 1727system.cpu0.l2cache.overall_hits::total 1933066 # number of overall hits 1728system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 539 # number of ReadReq misses 1729system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 228 # number of ReadReq misses 1730system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21755 # number of ReadReq misses 1731system.cpu0.l2cache.ReadReq_misses::cpu0.data 91027 # number of ReadReq misses 1732system.cpu0.l2cache.ReadReq_misses::total 113549 # number of ReadReq misses 1733system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27999 # number of UpgradeReq misses 1734system.cpu0.l2cache.UpgradeReq_misses::total 27999 # number of UpgradeReq misses 1735system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18512 # number of SCUpgradeReq misses 1736system.cpu0.l2cache.SCUpgradeReq_misses::total 18512 # number of SCUpgradeReq misses 1737system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52925 # number of ReadExReq misses 1738system.cpu0.l2cache.ReadExReq_misses::total 52925 # number of ReadExReq misses 1739system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 539 # number of demand (read+write) misses 1740system.cpu0.l2cache.demand_misses::cpu0.itb.walker 228 # number of demand (read+write) misses 1741system.cpu0.l2cache.demand_misses::cpu0.inst 21755 # number of demand (read+write) misses 1742system.cpu0.l2cache.demand_misses::cpu0.data 143952 # number of demand (read+write) misses 1743system.cpu0.l2cache.demand_misses::total 166474 # number of demand (read+write) misses 1744system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 539 # number of overall misses 1745system.cpu0.l2cache.overall_misses::cpu0.itb.walker 228 # number of overall misses 1746system.cpu0.l2cache.overall_misses::cpu0.inst 21755 # number of overall misses 1747system.cpu0.l2cache.overall_misses::cpu0.data 143952 # number of overall misses 1748system.cpu0.l2cache.overall_misses::total 166474 # number of overall misses 1749system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14141500 # number of ReadReq miss cycles 1750system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5255000 # number of ReadReq miss cycles 1751system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 812129434 # number of ReadReq miss cycles 1752system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2705700107 # number of ReadReq miss cycles 1753system.cpu0.l2cache.ReadReq_miss_latency::total 3537226041 # number of ReadReq miss cycles 1754system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502587457 # number of UpgradeReq miss cycles 1755system.cpu0.l2cache.UpgradeReq_miss_latency::total 502587457 # number of UpgradeReq miss cycles 1756system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362338282 # number of SCUpgradeReq miss cycles 1757system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362338282 # number of SCUpgradeReq miss cycles 1758system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 217500 # number of SCUpgradeFailReq miss cycles 1759system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 217500 # number of SCUpgradeFailReq miss cycles 1760system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2594310029 # number of ReadExReq miss cycles 1761system.cpu0.l2cache.ReadExReq_miss_latency::total 2594310029 # number of ReadExReq miss cycles 1762system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14141500 # number of demand (read+write) miss cycles 1763system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5255000 # number of demand (read+write) miss cycles 1764system.cpu0.l2cache.demand_miss_latency::cpu0.inst 812129434 # number of demand (read+write) miss cycles 1765system.cpu0.l2cache.demand_miss_latency::cpu0.data 5300010136 # number of demand (read+write) miss cycles 1766system.cpu0.l2cache.demand_miss_latency::total 6131536070 # number of demand (read+write) miss cycles 1767system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14141500 # number of overall miss cycles 1768system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5255000 # number of overall miss cycles 1769system.cpu0.l2cache.overall_miss_latency::cpu0.inst 812129434 # number of overall miss cycles 1770system.cpu0.l2cache.overall_miss_latency::cpu0.data 5300010136 # number of overall miss cycles 1771system.cpu0.l2cache.overall_miss_latency::total 6131536070 # number of overall miss cycles 1772system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54695 # number of ReadReq accesses(hits+misses) 1773system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12558 # number of ReadReq accesses(hits+misses) 1774system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264502 # number of ReadReq accesses(hits+misses) 1775system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498318 # number of ReadReq accesses(hits+misses) 1776system.cpu0.l2cache.ReadReq_accesses::total 1830073 # number of ReadReq accesses(hits+misses) 1777system.cpu0.l2cache.Writeback_accesses::writebacks 512497 # number of Writeback accesses(hits+misses) 1778system.cpu0.l2cache.Writeback_accesses::total 512497 # number of Writeback accesses(hits+misses) 1779system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43461 # number of UpgradeReq accesses(hits+misses) 1780system.cpu0.l2cache.UpgradeReq_accesses::total 43461 # number of UpgradeReq accesses(hits+misses) 1781system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20700 # number of SCUpgradeReq accesses(hits+misses) 1782system.cpu0.l2cache.SCUpgradeReq_accesses::total 20700 # number of SCUpgradeReq accesses(hits+misses) 1783system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269467 # number of ReadExReq accesses(hits+misses) 1784system.cpu0.l2cache.ReadExReq_accesses::total 269467 # number of ReadExReq accesses(hits+misses) 1785system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54695 # number of demand (read+write) accesses 1786system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12558 # number of demand (read+write) accesses 1787system.cpu0.l2cache.demand_accesses::cpu0.inst 1264502 # number of demand (read+write) accesses 1788system.cpu0.l2cache.demand_accesses::cpu0.data 767785 # number of demand (read+write) accesses 1789system.cpu0.l2cache.demand_accesses::total 2099540 # number of demand (read+write) accesses 1790system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54695 # number of overall (read+write) accesses 1791system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12558 # number of overall (read+write) accesses 1792system.cpu0.l2cache.overall_accesses::cpu0.inst 1264502 # number of overall (read+write) accesses 1793system.cpu0.l2cache.overall_accesses::cpu0.data 767785 # number of overall (read+write) accesses 1794system.cpu0.l2cache.overall_accesses::total 2099540 # number of overall (read+write) accesses 1795system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for ReadReq accesses 1796system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.018156 # miss rate for ReadReq accesses 1797system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017204 # miss rate for ReadReq accesses 1798system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182668 # miss rate for ReadReq accesses 1799system.cpu0.l2cache.ReadReq_miss_rate::total 0.062046 # miss rate for ReadReq accesses 1800system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.644233 # miss rate for UpgradeReq accesses 1801system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.644233 # miss rate for UpgradeReq accesses 1802system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.894300 # miss rate for SCUpgradeReq accesses 1803system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.894300 # miss rate for SCUpgradeReq accesses 1804system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.196406 # miss rate for ReadExReq accesses 1805system.cpu0.l2cache.ReadExReq_miss_rate::total 0.196406 # miss rate for ReadExReq accesses 1806system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for demand accesses 1807system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.018156 # miss rate for demand accesses 1808system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017204 # miss rate for demand accesses 1809system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.187490 # miss rate for demand accesses 1810system.cpu0.l2cache.demand_miss_rate::total 0.079291 # miss rate for demand accesses 1811system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for overall accesses 1812system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.018156 # miss rate for overall accesses 1813system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017204 # miss rate for overall accesses 1814system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.187490 # miss rate for overall accesses 1815system.cpu0.l2cache.overall_miss_rate::total 0.079291 # miss rate for overall accesses 1816system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average ReadReq miss latency 1817system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23048.245614 # average ReadReq miss latency 1818system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37330.702551 # average ReadReq miss latency 1819system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29724.148956 # average ReadReq miss latency 1820system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31151.538464 # average ReadReq miss latency 1821system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17950.193114 # average UpgradeReq miss latency 1822system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17950.193114 # average UpgradeReq miss latency 1823system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19573.156979 # average SCUpgradeReq miss latency 1824system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19573.156979 # average SCUpgradeReq miss latency 1825system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1826system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1827system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49018.611790 # average ReadExReq miss latency 1828system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49018.611790 # average ReadExReq miss latency 1829system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency 1830system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency 1831system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency 1832system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency 1833system.cpu0.l2cache.demand_avg_miss_latency::total 36831.793974 # average overall miss latency 1834system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency 1835system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency 1836system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency 1837system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency 1838system.cpu0.l2cache.overall_avg_miss_latency::total 36831.793974 # average overall miss latency 1839system.cpu0.l2cache.blocked_cycles::no_mshrs 59871 # number of cycles access was blocked |
| 1771system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1840system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1772system.cpu0.l2cache.blocked::no_mshrs 266 # number of cycles access was blocked | 1841system.cpu0.l2cache.blocked::no_mshrs 1464 # number of cycles access was blocked |
| 1773system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1842system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1774system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 17.973684 # average number of cycles each access was blocked | 1843system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 40.895492 # average number of cycles each access was blocked |
| 1775system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1776system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1777system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1844system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1845system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1846system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1778system.cpu0.l2cache.writebacks::writebacks 105131 # number of writebacks 1779system.cpu0.l2cache.writebacks::total 105131 # number of writebacks | 1847system.cpu0.l2cache.writebacks::writebacks 212118 # number of writebacks 1848system.cpu0.l2cache.writebacks::total 212118 # number of writebacks |
| 1780system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1781system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits | 1849system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1850system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits |
| 1782system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1845 # number of ReadReq MSHR hits 1783system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 997 # number of ReadReq MSHR hits 1784system.cpu0.l2cache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits 1785system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 936 # number of ReadExReq MSHR hits 1786system.cpu0.l2cache.ReadExReq_mshr_hits::total 936 # number of ReadExReq MSHR hits | 1851system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5582 # number of ReadReq MSHR hits 1852system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3121 # number of ReadReq MSHR hits 1853system.cpu0.l2cache.ReadReq_mshr_hits::total 8705 # number of ReadReq MSHR hits 1854system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8957 # number of ReadExReq MSHR hits 1855system.cpu0.l2cache.ReadExReq_mshr_hits::total 8957 # number of ReadExReq MSHR hits |
| 1787system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1788system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits | 1856system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1857system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits |
| 1789system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1845 # number of demand (read+write) MSHR hits 1790system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1933 # number of demand (read+write) MSHR hits 1791system.cpu0.l2cache.demand_mshr_hits::total 3780 # number of demand (read+write) MSHR hits | 1858system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5582 # number of demand (read+write) MSHR hits 1859system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12078 # number of demand (read+write) MSHR hits 1860system.cpu0.l2cache.demand_mshr_hits::total 17662 # number of demand (read+write) MSHR hits |
| 1792system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1793system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits | 1861system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1862system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits |
| 1794system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1845 # number of overall MSHR hits 1795system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1933 # number of overall MSHR hits 1796system.cpu0.l2cache.overall_mshr_hits::total 3780 # number of overall MSHR hits 1797system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses 1798system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 170 # number of ReadReq MSHR misses 1799system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5956 # number of ReadReq MSHR misses 1800system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49808 # number of ReadReq MSHR misses 1801system.cpu0.l2cache.ReadReq_mshr_misses::total 56278 # number of ReadReq MSHR misses 1802system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses 1803system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses 1804system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of HardPFReq MSHR misses 1805system.cpu0.l2cache.HardPFReq_mshr_misses::total 198779 # number of HardPFReq MSHR misses 1806system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19680 # number of UpgradeReq MSHR misses 1807system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19680 # number of UpgradeReq MSHR misses 1808system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10856 # number of SCUpgradeReq MSHR misses 1809system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10856 # number of SCUpgradeReq MSHR misses 1810system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1811system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1812system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22661 # number of ReadExReq MSHR misses 1813system.cpu0.l2cache.ReadExReq_mshr_misses::total 22661 # number of ReadExReq MSHR misses 1814system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 344 # number of demand (read+write) MSHR misses 1815system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 170 # number of demand (read+write) MSHR misses 1816system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5956 # number of demand (read+write) MSHR misses 1817system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72469 # number of demand (read+write) MSHR misses 1818system.cpu0.l2cache.demand_mshr_misses::total 78939 # number of demand (read+write) MSHR misses 1819system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 344 # number of overall MSHR misses 1820system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 170 # number of overall MSHR misses 1821system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5956 # number of overall MSHR misses 1822system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72469 # number of overall MSHR misses 1823system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of overall MSHR misses 1824system.cpu0.l2cache.overall_mshr_misses::total 277718 # number of overall MSHR misses 1825system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of ReadReq MSHR miss cycles 1826system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2550500 # number of ReadReq MSHR miss cycles 1827system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 181100759 # number of ReadReq MSHR miss cycles 1828system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 940424592 # number of ReadReq MSHR miss cycles 1829system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1129080602 # number of ReadReq MSHR miss cycles 1830system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of HardPFReq MSHR miss cycles 1831system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8151036272 # number of HardPFReq MSHR miss cycles 1832system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 354005766 # number of UpgradeReq MSHR miss cycles 1833system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles 1834system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158485722 # number of SCUpgradeReq MSHR miss cycles 1835system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles 1836system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles 1837system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles 1838system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # number of ReadExReq MSHR miss cycles 1839system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 601346170 # number of ReadExReq MSHR miss cycles 1840system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of demand (read+write) MSHR miss cycles 1841system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2550500 # number of demand (read+write) MSHR miss cycles 1842system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 181100759 # number of demand (read+write) MSHR miss cycles 1843system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541770762 # number of demand (read+write) MSHR miss cycles 1844system.cpu0.l2cache.demand_mshr_miss_latency::total 1730426772 # number of demand (read+write) MSHR miss cycles 1845system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of overall MSHR miss cycles 1846system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2550500 # number of overall MSHR miss cycles 1847system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles 1848system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles 1849system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles 1850system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles 1851system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles 1852system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles 1853system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles 1854system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles 1855system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles 1856system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles 1857system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles 1858system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles 1859system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses 1860system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses 1861system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses 1862system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses 1863system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses 1864system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses 1865system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses | 1863system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5582 # number of overall MSHR hits 1864system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12078 # number of overall MSHR hits 1865system.cpu0.l2cache.overall_mshr_hits::total 17662 # number of overall MSHR hits 1866system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 538 # number of ReadReq MSHR misses 1867system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 227 # number of ReadReq MSHR misses 1868system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16173 # number of ReadReq MSHR misses 1869system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87906 # number of ReadReq MSHR misses 1870system.cpu0.l2cache.ReadReq_mshr_misses::total 104844 # number of ReadReq MSHR misses 1871system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of HardPFReq MSHR misses 1872system.cpu0.l2cache.HardPFReq_mshr_misses::total 470726 # number of HardPFReq MSHR misses 1873system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27999 # number of UpgradeReq MSHR misses 1874system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27999 # number of UpgradeReq MSHR misses 1875system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18512 # number of SCUpgradeReq MSHR misses 1876system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18512 # number of SCUpgradeReq MSHR misses 1877system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43968 # number of ReadExReq MSHR misses 1878system.cpu0.l2cache.ReadExReq_mshr_misses::total 43968 # number of ReadExReq MSHR misses 1879system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 538 # number of demand (read+write) MSHR misses 1880system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 227 # number of demand (read+write) MSHR misses 1881system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16173 # number of demand (read+write) MSHR misses 1882system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131874 # number of demand (read+write) MSHR misses 1883system.cpu0.l2cache.demand_mshr_misses::total 148812 # number of demand (read+write) MSHR misses 1884system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 538 # number of overall MSHR misses 1885system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 227 # number of overall MSHR misses 1886system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16173 # number of overall MSHR misses 1887system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131874 # number of overall MSHR misses 1888system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of overall MSHR misses 1889system.cpu0.l2cache.overall_mshr_misses::total 619538 # number of overall MSHR misses 1890system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of ReadReq MSHR miss cycles 1891system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3653000 # number of ReadReq MSHR miss cycles 1892system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 584863774 # number of ReadReq MSHR miss cycles 1893system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2018675176 # number of ReadReq MSHR miss cycles 1894system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2617551450 # number of ReadReq MSHR miss cycles 1895system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of HardPFReq MSHR miss cycles 1896system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21918972757 # number of HardPFReq MSHR miss cycles 1897system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 483477329 # number of UpgradeReq MSHR miss cycles 1898system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 483477329 # number of UpgradeReq MSHR miss cycles 1899system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 250147229 # number of SCUpgradeReq MSHR miss cycles 1900system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 250147229 # number of SCUpgradeReq MSHR miss cycles 1901system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 175500 # number of SCUpgradeFailReq MSHR miss cycles 1902system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 175500 # number of SCUpgradeFailReq MSHR miss cycles 1903system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315007380 # number of ReadExReq MSHR miss cycles 1904system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315007380 # number of ReadExReq MSHR miss cycles 1905system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of demand (read+write) MSHR miss cycles 1906system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3653000 # number of demand (read+write) MSHR miss cycles 1907system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 584863774 # number of demand (read+write) MSHR miss cycles 1908system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3333682556 # number of demand (read+write) MSHR miss cycles 1909system.cpu0.l2cache.demand_mshr_miss_latency::total 3932558830 # number of demand (read+write) MSHR miss cycles 1910system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of overall MSHR miss cycles 1911system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3653000 # number of overall MSHR miss cycles 1912system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 584863774 # number of overall MSHR miss cycles 1913system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3333682556 # number of overall MSHR miss cycles 1914system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of overall MSHR miss cycles 1915system.cpu0.l2cache.overall_mshr_miss_latency::total 25851531587 # number of overall MSHR miss cycles 1916system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218357500 # number of ReadReq MSHR uncacheable cycles 1917system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053329974 # number of ReadReq MSHR uncacheable cycles 1918system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4271687474 # number of ReadReq MSHR uncacheable cycles 1919system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040369451 # number of WriteReq MSHR uncacheable cycles 1920system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040369451 # number of WriteReq MSHR uncacheable cycles 1921system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218357500 # number of overall MSHR uncacheable cycles 1922system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7093699425 # number of overall MSHR uncacheable cycles 1923system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312056925 # number of overall MSHR uncacheable cycles 1924system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for ReadReq accesses 1925system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for ReadReq accesses 1926system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for ReadReq accesses 1927system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176405 # mshr miss rate for ReadReq accesses 1928system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057290 # mshr miss rate for ReadReq accesses |
| 1866system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1867system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1929system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1930system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1868system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses 1869system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses 1870system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses 1871system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses 1872system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1873system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1874system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses 1875system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses 1876system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses 1877system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses 1878system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses 1879system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses 1880system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses 1881system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses 1882system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses 1883system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses 1884system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses | 1931system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.644233 # mshr miss rate for UpgradeReq accesses 1932system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.644233 # mshr miss rate for UpgradeReq accesses 1933system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.894300 # mshr miss rate for SCUpgradeReq accesses 1934system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.894300 # mshr miss rate for SCUpgradeReq accesses 1935system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163167 # mshr miss rate for ReadExReq accesses 1936system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163167 # mshr miss rate for ReadExReq accesses 1937system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for demand accesses 1938system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for demand accesses 1939system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for demand accesses 1940system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for demand accesses 1941system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070878 # mshr miss rate for demand accesses 1942system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for overall accesses 1943system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for overall accesses 1944system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for overall accesses 1945system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for overall accesses |
| 1885system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1946system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1886system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses 1887system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency 1888system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency 1889system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency 1890system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency 1891system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency 1892system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency 1893system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency 1894system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency 1895system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency 1896system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency 1897system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency 1898system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency 1899system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency 1900system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency 1901system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency 1902system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency 1903system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency 1904system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency 1905system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency 1906system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency 1907system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency 1908system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency 1909system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency 1910system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency 1911system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency 1912system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency | 1947system.cpu0.l2cache.overall_mshr_miss_rate::total 0.295083 # mshr miss rate for overall accesses 1948system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average ReadReq mshr miss latency 1949system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average ReadReq mshr miss latency 1950system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average ReadReq mshr miss latency 1951system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22964.020385 # average ReadReq mshr miss latency 1952system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24966.154000 # average ReadReq mshr miss latency 1953system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average HardPFReq mshr miss latency 1954system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46564.185443 # average HardPFReq mshr miss latency 1955system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17267.664167 # average UpgradeReq mshr miss latency 1956system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17267.664167 # average UpgradeReq mshr miss latency 1957system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13512.706839 # average SCUpgradeReq mshr miss latency 1958system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13512.706839 # average SCUpgradeReq mshr miss latency 1959system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1960system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1961system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29908.282842 # average ReadExReq mshr miss latency 1962system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29908.282842 # average ReadExReq mshr miss latency 1963system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency 1964system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency 1965system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency 1966system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency 1967system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26426.355603 # average overall mshr miss latency 1968system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency 1969system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency 1970system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency 1971system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency 1972system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average overall mshr miss latency 1973system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41727.112117 # average overall mshr miss latency |
| 1913system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1914system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1915system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1916system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1917system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1918system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1919system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1920system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1921system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1974system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1975system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1976system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1977system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1978system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1979system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1980system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1981system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1982system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1922system.cpu0.dcache.tags.replacements 297335 # number of replacements 1923system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use 1924system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks. 1925system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks. 1926system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks. 1927system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. 1928system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor 1929system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy 1930system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy | 1983system.cpu0.dcache.tags.replacements 712949 # number of replacements 1984system.cpu0.dcache.tags.tagsinuse 494.466444 # Cycle average of tags in use 1985system.cpu0.dcache.tags.total_refs 28841621 # Total number of references to valid blocks. 1986system.cpu0.dcache.tags.sampled_refs 713461 # Sample count of references to valid blocks. 1987system.cpu0.dcache.tags.avg_refs 40.424944 # Average number of references to valid blocks. 1988system.cpu0.dcache.tags.warmup_cycle 256469000 # Cycle when the warmup percentage was hit. 1989system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.466444 # Average occupied blocks per requestor 1990system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965755 # Average percentage of cache occupancy 1991system.cpu0.dcache.tags.occ_percent::total 0.965755 # Average percentage of cache occupancy |
| 1931system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1992system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1932system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 1933system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id 1934system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id | 1993system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id 1994system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 1995system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id |
| 1935system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1996system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1936system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses 1937system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses 1938system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits 1939system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits 1940system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits 1941system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits 1942system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits 1943system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits 1944system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits 1945system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits 1946system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits 1947system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits 1948system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits 1949system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits 1950system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits 1951system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits 1952system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses 1953system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses 1954system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses 1955system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses 1956system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses 1957system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses 1958system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses 1959system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses 1960system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses 1961system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses 1962system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses 1963system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses 1964system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses 1965system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses 1966system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles 1967system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles 1968system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles 1969system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles 1970system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles 1971system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles 1972system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273467244 # number of StoreCondReq miss cycles 1973system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles 1974system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles 1975system.cpu0.dcache.StoreCondFailReq_miss_latency::total 660000 # number of StoreCondFailReq miss cycles 1976system.cpu0.dcache.demand_miss_latency::cpu0.data 16742760911 # number of demand (read+write) miss cycles 1977system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles 1978system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles 1979system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles 1980system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses) 1981system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses) 1982system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses) 1983system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses) 1984system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses) 1985system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses) 1986system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses) 1987system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses) 1988system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses) 1989system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses) 1990system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses 1991system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses 1992system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses 1993system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses 1994system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses 1995system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses 1996system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses 1997system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses 1998system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses 1999system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses 2000system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses 2001system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses 2002system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses 2003system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses 2004system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses 2005system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses 2006system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses 2007system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses 2008system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency 2009system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency 2010system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency 2011system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency 2012system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency 2013system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency 2014system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency 2015system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency | 1997system.cpu0.dcache.tags.tag_accesses 63482821 # Number of tag accesses 1998system.cpu0.dcache.tags.data_accesses 63482821 # Number of data accesses 1999system.cpu0.dcache.ReadReq_hits::cpu0.data 15588564 # number of ReadReq hits 2000system.cpu0.dcache.ReadReq_hits::total 15588564 # number of ReadReq hits 2001system.cpu0.dcache.WriteReq_hits::cpu0.data 12071351 # number of WriteReq hits 2002system.cpu0.dcache.WriteReq_hits::total 12071351 # number of WriteReq hits 2003system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311001 # number of SoftPFReq hits 2004system.cpu0.dcache.SoftPFReq_hits::total 311001 # number of SoftPFReq hits 2005system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363214 # number of LoadLockedReq hits 2006system.cpu0.dcache.LoadLockedReq_hits::total 363214 # number of LoadLockedReq hits 2007system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360561 # number of StoreCondReq hits 2008system.cpu0.dcache.StoreCondReq_hits::total 360561 # number of StoreCondReq hits 2009system.cpu0.dcache.demand_hits::cpu0.data 27659915 # number of demand (read+write) hits 2010system.cpu0.dcache.demand_hits::total 27659915 # number of demand (read+write) hits 2011system.cpu0.dcache.overall_hits::cpu0.data 27970916 # number of overall hits 2012system.cpu0.dcache.overall_hits::total 27970916 # number of overall hits 2013system.cpu0.dcache.ReadReq_misses::cpu0.data 638335 # number of ReadReq misses 2014system.cpu0.dcache.ReadReq_misses::total 638335 # number of ReadReq misses 2015system.cpu0.dcache.WriteReq_misses::cpu0.data 1832649 # number of WriteReq misses 2016system.cpu0.dcache.WriteReq_misses::total 1832649 # number of WriteReq misses 2017system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146162 # number of SoftPFReq misses 2018system.cpu0.dcache.SoftPFReq_misses::total 146162 # number of SoftPFReq misses 2019system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24977 # number of LoadLockedReq misses 2020system.cpu0.dcache.LoadLockedReq_misses::total 24977 # number of LoadLockedReq misses 2021system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20700 # number of StoreCondReq misses 2022system.cpu0.dcache.StoreCondReq_misses::total 20700 # number of StoreCondReq misses 2023system.cpu0.dcache.demand_misses::cpu0.data 2470984 # number of demand (read+write) misses 2024system.cpu0.dcache.demand_misses::total 2470984 # number of demand (read+write) misses 2025system.cpu0.dcache.overall_misses::cpu0.data 2617146 # number of overall misses 2026system.cpu0.dcache.overall_misses::total 2617146 # number of overall misses 2027system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8102181310 # number of ReadReq miss cycles 2028system.cpu0.dcache.ReadReq_miss_latency::total 8102181310 # number of ReadReq miss cycles 2029system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25003432618 # number of WriteReq miss cycles 2030system.cpu0.dcache.WriteReq_miss_latency::total 25003432618 # number of WriteReq miss cycles 2031system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 396859499 # number of LoadLockedReq miss cycles 2032system.cpu0.dcache.LoadLockedReq_miss_latency::total 396859499 # number of LoadLockedReq miss cycles 2033system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 455692776 # number of StoreCondReq miss cycles 2034system.cpu0.dcache.StoreCondReq_miss_latency::total 455692776 # number of StoreCondReq miss cycles 2035system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 235500 # number of StoreCondFailReq miss cycles 2036system.cpu0.dcache.StoreCondFailReq_miss_latency::total 235500 # number of StoreCondFailReq miss cycles 2037system.cpu0.dcache.demand_miss_latency::cpu0.data 33105613928 # number of demand (read+write) miss cycles 2038system.cpu0.dcache.demand_miss_latency::total 33105613928 # number of demand (read+write) miss cycles 2039system.cpu0.dcache.overall_miss_latency::cpu0.data 33105613928 # number of overall miss cycles 2040system.cpu0.dcache.overall_miss_latency::total 33105613928 # number of overall miss cycles 2041system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226899 # number of ReadReq accesses(hits+misses) 2042system.cpu0.dcache.ReadReq_accesses::total 16226899 # number of ReadReq accesses(hits+misses) 2043system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904000 # number of WriteReq accesses(hits+misses) 2044system.cpu0.dcache.WriteReq_accesses::total 13904000 # number of WriteReq accesses(hits+misses) 2045system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457163 # number of SoftPFReq accesses(hits+misses) 2046system.cpu0.dcache.SoftPFReq_accesses::total 457163 # number of SoftPFReq accesses(hits+misses) 2047system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388191 # number of LoadLockedReq accesses(hits+misses) 2048system.cpu0.dcache.LoadLockedReq_accesses::total 388191 # number of LoadLockedReq accesses(hits+misses) 2049system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381261 # number of StoreCondReq accesses(hits+misses) 2050system.cpu0.dcache.StoreCondReq_accesses::total 381261 # number of StoreCondReq accesses(hits+misses) 2051system.cpu0.dcache.demand_accesses::cpu0.data 30130899 # number of demand (read+write) accesses 2052system.cpu0.dcache.demand_accesses::total 30130899 # number of demand (read+write) accesses 2053system.cpu0.dcache.overall_accesses::cpu0.data 30588062 # number of overall (read+write) accesses 2054system.cpu0.dcache.overall_accesses::total 30588062 # number of overall (read+write) accesses 2055system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039338 # miss rate for ReadReq accesses 2056system.cpu0.dcache.ReadReq_miss_rate::total 0.039338 # miss rate for ReadReq accesses 2057system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131807 # miss rate for WriteReq accesses 2058system.cpu0.dcache.WriteReq_miss_rate::total 0.131807 # miss rate for WriteReq accesses 2059system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319715 # miss rate for SoftPFReq accesses 2060system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319715 # miss rate for SoftPFReq accesses 2061system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses 2062system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses 2063system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054294 # miss rate for StoreCondReq accesses 2064system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054294 # miss rate for StoreCondReq accesses 2065system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082008 # miss rate for demand accesses 2066system.cpu0.dcache.demand_miss_rate::total 0.082008 # miss rate for demand accesses 2067system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085561 # miss rate for overall accesses 2068system.cpu0.dcache.overall_miss_rate::total 0.085561 # miss rate for overall accesses 2069system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12692.679095 # average ReadReq miss latency 2070system.cpu0.dcache.ReadReq_avg_miss_latency::total 12692.679095 # average ReadReq miss latency 2071system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13643.328656 # average WriteReq miss latency 2072system.cpu0.dcache.WriteReq_avg_miss_latency::total 13643.328656 # average WriteReq miss latency 2073system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15888.997838 # average LoadLockedReq miss latency 2074system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15888.997838 # average LoadLockedReq miss latency 2075system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22014.143768 # average StoreCondReq miss latency 2076system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22014.143768 # average StoreCondReq miss latency |
| 2016system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 2017system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2077system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 2078system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2018system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency 2019system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency 2020system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency 2021system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency 2022system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 2023system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked 2024system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked 2025system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked 2026system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 2027system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked | 2079system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13397.745161 # average overall miss latency 2080system.cpu0.dcache.demand_avg_miss_latency::total 13397.745161 # average overall miss latency 2081system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12649.509782 # average overall miss latency 2082system.cpu0.dcache.overall_avg_miss_latency::total 12649.509782 # average overall miss latency 2083system.cpu0.dcache.blocked_cycles::no_mshrs 1233 # number of cycles access was blocked 2084system.cpu0.dcache.blocked_cycles::no_targets 3385599 # number of cycles access was blocked 2085system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked 2086system.cpu0.dcache.blocked::no_targets 191316 # number of cycles access was blocked 2087system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.614286 # average number of cycles each access was blocked 2088system.cpu0.dcache.avg_blocked_cycles::no_targets 17.696371 # average number of cycles each access was blocked |
| 2028system.cpu0.dcache.fast_writes 0 # number of fast writes performed 2029system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 2089system.cpu0.dcache.fast_writes 0 # number of fast writes performed 2090system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 2030system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks 2031system.cpu0.dcache.writebacks::total 228050 # number of writebacks 2032system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits 2033system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits 2034system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits 2035system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits 2036system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits 2037system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits 2038system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits 2039system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits 2040system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits 2041system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits 2042system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses 2043system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses 2044system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses 2045system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses 2046system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses 2047system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses 2048system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses 2049system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses 2050system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses 2051system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses 2052system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses 2053system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses 2054system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses 2055system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses 2056system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles 2057system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles 2058system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles 2059system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles 2060system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles 2061system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles 2062system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles 2063system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles 2064system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles 2065system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles 2066system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles 2067system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles 2068system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles 2069system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles 2070system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles 2071system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles 2072system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles 2073system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles 2074system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles 2075system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles 2076system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles 2077system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles 2078system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses 2079system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses 2080system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses 2081system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses 2082system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses 2083system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses 2084system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses 2085system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses 2086system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses 2087system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses 2088system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses 2089system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses 2090system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses 2091system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses 2092system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency 2093system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency 2094system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency 2095system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency 2096system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency 2097system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency 2098system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency 2099system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency 2100system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency 2101system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency | 2091system.cpu0.dcache.writebacks::writebacks 512498 # number of writebacks 2092system.cpu0.dcache.writebacks::total 512498 # number of writebacks 2093system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248017 # number of ReadReq MSHR hits 2094system.cpu0.dcache.ReadReq_mshr_hits::total 248017 # number of ReadReq MSHR hits 2095system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519903 # number of WriteReq MSHR hits 2096system.cpu0.dcache.WriteReq_mshr_hits::total 1519903 # number of WriteReq MSHR hits 2097system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18417 # number of LoadLockedReq MSHR hits 2098system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits 2099system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767920 # number of demand (read+write) MSHR hits 2100system.cpu0.dcache.demand_mshr_hits::total 1767920 # number of demand (read+write) MSHR hits 2101system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767920 # number of overall MSHR hits 2102system.cpu0.dcache.overall_mshr_hits::total 1767920 # number of overall MSHR hits 2103system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390318 # number of ReadReq MSHR misses 2104system.cpu0.dcache.ReadReq_mshr_misses::total 390318 # number of ReadReq MSHR misses 2105system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312746 # number of WriteReq MSHR misses 2106system.cpu0.dcache.WriteReq_mshr_misses::total 312746 # number of WriteReq MSHR misses 2107system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101547 # number of SoftPFReq MSHR misses 2108system.cpu0.dcache.SoftPFReq_mshr_misses::total 101547 # number of SoftPFReq MSHR misses 2109system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6560 # number of LoadLockedReq MSHR misses 2110system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6560 # number of LoadLockedReq MSHR misses 2111system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20700 # number of StoreCondReq MSHR misses 2112system.cpu0.dcache.StoreCondReq_mshr_misses::total 20700 # number of StoreCondReq MSHR misses 2113system.cpu0.dcache.demand_mshr_misses::cpu0.data 703064 # number of demand (read+write) MSHR misses 2114system.cpu0.dcache.demand_mshr_misses::total 703064 # number of demand (read+write) MSHR misses 2115system.cpu0.dcache.overall_mshr_misses::cpu0.data 804611 # number of overall MSHR misses 2116system.cpu0.dcache.overall_mshr_misses::total 804611 # number of overall MSHR misses 2117system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4171307993 # number of ReadReq MSHR miss cycles 2118system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4171307993 # number of ReadReq MSHR miss cycles 2119system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4996022111 # number of WriteReq MSHR miss cycles 2120system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4996022111 # number of WriteReq MSHR miss cycles 2121system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1423316745 # number of SoftPFReq MSHR miss cycles 2122system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1423316745 # number of SoftPFReq MSHR miss cycles 2123system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98363500 # number of LoadLockedReq MSHR miss cycles 2124system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98363500 # number of LoadLockedReq MSHR miss cycles 2125system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 413570224 # number of StoreCondReq MSHR miss cycles 2126system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 413570224 # number of StoreCondReq MSHR miss cycles 2127system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles 2128system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles 2129system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9167330104 # number of demand (read+write) MSHR miss cycles 2130system.cpu0.dcache.demand_mshr_miss_latency::total 9167330104 # number of demand (read+write) MSHR miss cycles 2131system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10590646849 # number of overall MSHR miss cycles 2132system.cpu0.dcache.overall_mshr_miss_latency::total 10590646849 # number of overall MSHR miss cycles 2133system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216535499 # number of ReadReq MSHR uncacheable cycles 2134system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216535499 # number of ReadReq MSHR uncacheable cycles 2135system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187175989 # number of WriteReq MSHR uncacheable cycles 2136system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187175989 # number of WriteReq MSHR uncacheable cycles 2137system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403711488 # number of overall MSHR uncacheable cycles 2138system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403711488 # number of overall MSHR uncacheable cycles 2139system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024054 # mshr miss rate for ReadReq accesses 2140system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024054 # mshr miss rate for ReadReq accesses 2141system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022493 # mshr miss rate for WriteReq accesses 2142system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022493 # mshr miss rate for WriteReq accesses 2143system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222124 # mshr miss rate for SoftPFReq accesses 2144system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222124 # mshr miss rate for SoftPFReq accesses 2145system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016899 # mshr miss rate for LoadLockedReq accesses 2146system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016899 # mshr miss rate for LoadLockedReq accesses 2147system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054294 # mshr miss rate for StoreCondReq accesses 2148system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054294 # mshr miss rate for StoreCondReq accesses 2149system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023334 # mshr miss rate for demand accesses 2150system.cpu0.dcache.demand_mshr_miss_rate::total 0.023334 # mshr miss rate for demand accesses 2151system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026305 # mshr miss rate for overall accesses 2152system.cpu0.dcache.overall_mshr_miss_rate::total 0.026305 # mshr miss rate for overall accesses 2153system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10686.947548 # average ReadReq mshr miss latency 2154system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10686.947548 # average ReadReq mshr miss latency 2155system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15974.695475 # average WriteReq mshr miss latency 2156system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15974.695475 # average WriteReq mshr miss latency 2157system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14016.334751 # average SoftPFReq mshr miss latency 2158system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14016.334751 # average SoftPFReq mshr miss latency 2159system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14994.435976 # average LoadLockedReq mshr miss latency 2160system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14994.435976 # average LoadLockedReq mshr miss latency 2161system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19979.237874 # average StoreCondReq mshr miss latency 2162system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19979.237874 # average StoreCondReq mshr miss latency |
| 2102system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2103system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2163system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2164system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2104system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency 2105system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency 2106system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency 2107system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency | 2165system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13039.111808 # average overall mshr miss latency 2166system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13039.111808 # average overall mshr miss latency 2167system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13162.443527 # average overall mshr miss latency 2168system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13162.443527 # average overall mshr miss latency |
| 2108system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2109system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2110system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2111system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2112system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2113system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2114system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2169system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2170system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2171system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2172system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2173system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2174system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2175system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2115system.cpu1.branchPred.lookups 9149866 # Number of BP lookups 2116system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted 2117system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect 2118system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups 2119system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits | 2176system.cpu1.branchPred.lookups 33913093 # Number of BP lookups 2177system.cpu1.branchPred.condPredicted 11564399 # Number of conditional branches predicted 2178system.cpu1.branchPred.condIncorrect 305039 # Number of conditional branches incorrect 2179system.cpu1.branchPred.BTBLookups 18757536 # Number of BTB lookups 2180system.cpu1.branchPred.BTBHits 14959019 # Number of BTB hits |
| 2120system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 2181system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 2121system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage 2122system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target. 2123system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions. | 2182system.cpu1.branchPred.BTBHitPct 79.749382 # BTB Hit Percentage 2183system.cpu1.branchPred.usedRAS 12491385 # Number of times the RAS was used to get a target. 2184system.cpu1.branchPred.RASInCorrect 7180 # Number of incorrect RAS predictions. |
| 2124system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2125system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2126system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2127system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2128system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2129system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2130system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2131system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 2139system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2140system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2141system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2142system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2143system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2144system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2145system.cpu1.dtb.inst_hits 0 # ITB inst hits 2146system.cpu1.dtb.inst_misses 0 # ITB inst misses | 2185system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2186system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2187system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2188system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2189system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2190system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2191system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2192system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 2200system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2201system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2202system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2203system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2204system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2205system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2206system.cpu1.dtb.inst_hits 0 # ITB inst hits 2207system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 2147system.cpu1.dtb.read_hits 25102636 # DTB read hits 2148system.cpu1.dtb.read_misses 30137 # DTB read misses 2149system.cpu1.dtb.write_hits 6841685 # DTB write hits 2150system.cpu1.dtb.write_misses 6769 # DTB write misses 2151system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2152system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2153system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2154system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 2155system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB 2156system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions 2157system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch | 2208system.cpu1.dtb.read_hits 10162981 # DTB read hits 2209system.cpu1.dtb.read_misses 18754 # DTB read misses 2210system.cpu1.dtb.write_hits 6542585 # DTB write hits 2211system.cpu1.dtb.write_misses 2848 # DTB write misses 2212system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 2213system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 2214system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2215system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2216system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB 2217system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions 2218system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch |
| 2158system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 2219system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 2159system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions 2160system.cpu1.dtb.read_accesses 25132773 # DTB read accesses 2161system.cpu1.dtb.write_accesses 6848454 # DTB write accesses | 2220system.cpu1.dtb.perms_faults 394 # Number of TLB faults due to permissions restrictions 2221system.cpu1.dtb.read_accesses 10181735 # DTB read accesses 2222system.cpu1.dtb.write_accesses 6545433 # DTB write accesses |
| 2162system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 2223system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 2163system.cpu1.dtb.hits 31944321 # DTB hits 2164system.cpu1.dtb.misses 36906 # DTB misses 2165system.cpu1.dtb.accesses 31981227 # DTB accesses | 2224system.cpu1.dtb.hits 16705566 # DTB hits 2225system.cpu1.dtb.misses 21602 # DTB misses 2226system.cpu1.dtb.accesses 16727168 # DTB accesses |
| 2166system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2167system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2168system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2169system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2170system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2171system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2172system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2173system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 2179system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2180system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2181system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2182system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2183system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2184system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2185system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2186system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 2227system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2228system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2229system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2230system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2231system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2232system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2233system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2234system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 2240system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2241system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2242system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2243system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2244system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2245system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2246system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2247system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 2187system.cpu1.itb.inst_hits 16803682 # ITB inst hits 2188system.cpu1.itb.inst_misses 6173 # ITB inst misses | 2248system.cpu1.itb.inst_hits 43643100 # ITB inst hits 2249system.cpu1.itb.inst_misses 6996 # ITB inst misses |
| 2189system.cpu1.itb.read_hits 0 # DTB read hits 2190system.cpu1.itb.read_misses 0 # DTB read misses 2191system.cpu1.itb.write_hits 0 # DTB write hits 2192system.cpu1.itb.write_misses 0 # DTB write misses | 2250system.cpu1.itb.read_hits 0 # DTB read hits 2251system.cpu1.itb.read_misses 0 # DTB read misses 2252system.cpu1.itb.write_hits 0 # DTB write hits 2253system.cpu1.itb.write_misses 0 # DTB write misses |
| 2193system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 2194system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2195system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2196system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 2197system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB | 2254system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 2255system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 2256system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2257system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2258system.cpu1.itb.flush_entries 1201 # Number of entries that have been flushed from TLB |
| 2198system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2199system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2200system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 2259system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2260system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2261system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 2201system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions | 2262system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions |
| 2202system.cpu1.itb.read_accesses 0 # DTB read accesses 2203system.cpu1.itb.write_accesses 0 # DTB write accesses | 2263system.cpu1.itb.read_accesses 0 # DTB read accesses 2264system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 2204system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses 2205system.cpu1.itb.hits 16803682 # DTB hits 2206system.cpu1.itb.misses 6173 # DTB misses 2207system.cpu1.itb.accesses 16809855 # DTB accesses 2208system.cpu1.numCycles 436917069 # number of cpu cycles simulated | 2265system.cpu1.itb.inst_accesses 43650096 # ITB inst accesses 2266system.cpu1.itb.hits 43643100 # DTB hits 2267system.cpu1.itb.misses 6996 # DTB misses 2268system.cpu1.itb.accesses 43650096 # DTB accesses 2269system.cpu1.numCycles 104633766 # number of cpu cycles simulated |
| 2209system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2210system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 2270system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2271system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2211system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss 2212system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed 2213system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered 2214system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken 2215system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked 2216system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing 2217system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb 2218system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2219system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps 2220system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions 2221system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR 2222system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched 2223system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed 2224system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed 2225system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total) 2226system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total) 2227system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total) | 2272system.cpu1.fetch.icacheStallCycles 9986103 # Number of cycles fetch is stalled on an Icache miss 2273system.cpu1.fetch.Insts 109171918 # Number of instructions fetch has processed 2274system.cpu1.fetch.Branches 33913093 # Number of branches that fetch encountered 2275system.cpu1.fetch.predictedBranches 27450404 # Number of branches that fetch has predicted taken 2276system.cpu1.fetch.Cycles 91805384 # Number of cycles fetch has run and was not squashing or blocked 2277system.cpu1.fetch.SquashCycles 3775592 # Number of cycles fetch has spent squashing 2278system.cpu1.fetch.TlbCycles 78970 # Number of cycles fetch has spent waiting for tlb 2279system.cpu1.fetch.MiscStallCycles 32292 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2280system.cpu1.fetch.PendingTrapStallCycles 198987 # Number of stall cycles due to pending traps 2281system.cpu1.fetch.PendingQuiesceStallCycles 295254 # Number of stall cycles due to pending quiesce instructions 2282system.cpu1.fetch.IcacheWaitRetryStallCycles 7461 # Number of stall cycles due to full MSHR 2283system.cpu1.fetch.CacheLines 43642483 # Number of cache lines fetched 2284system.cpu1.fetch.IcacheSquashes 116201 # Number of outstanding Icache misses that were squashed 2285system.cpu1.fetch.ItlbSquashes 2279 # Number of outstanding ITLB misses that were squashed 2286system.cpu1.fetch.rateDist::samples 104292247 # Number of instructions fetched each cycle (Total) 2287system.cpu1.fetch.rateDist::mean 1.296794 # Number of instructions fetched each cycle (Total) 2288system.cpu1.fetch.rateDist::stdev 1.339797 # Number of instructions fetched each cycle (Total) |
| 2228system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 2289system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 2229system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total) 2230system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total) 2231system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total) 2232system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total) | 2290system.cpu1.fetch.rateDist::0 47342099 45.39% 45.39% # Number of instructions fetched each cycle (Total) 2291system.cpu1.fetch.rateDist::1 14034599 13.46% 58.85% # Number of instructions fetched each cycle (Total) 2292system.cpu1.fetch.rateDist::2 7535653 7.23% 66.08% # Number of instructions fetched each cycle (Total) 2293system.cpu1.fetch.rateDist::3 35379896 33.92% 100.00% # Number of instructions fetched each cycle (Total) |
| 2233system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2234system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2235system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 2294system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2295system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2296system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 2236system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total) 2237system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle 2238system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle 2239system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle 2240system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked 2241system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running 2242system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking 2243system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing 2244system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch 2245system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction 2246system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode 2247system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode 2248system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing 2249system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle 2250system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking 2251system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst 2252system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running 2253system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking 2254system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename 2255system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename 2256system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full 2257system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full 2258system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full 2259system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full 2260system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed 2261system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made 2262system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups 2263system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups 2264system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed 2265system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing 2266system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed 2267system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed 2268system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer 2269system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit. 2270system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit. 2271system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads. 2272system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores. 2273system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec) 2274system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ 2275system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued 2276system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued 2277system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling 2278system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph 2279system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed 2280system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle 2281system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle 2282system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle | 2297system.cpu1.fetch.rateDist::total 104292247 # Number of instructions fetched each cycle (Total) 2298system.cpu1.fetch.branchRate 0.324112 # Number of branch fetches per cycle 2299system.cpu1.fetch.rate 1.043372 # Number of inst fetches per cycle 2300system.cpu1.decode.IdleCycles 13023476 # Number of cycles decode is idle 2301system.cpu1.decode.BlockedCycles 61678123 # Number of cycles decode is blocked 2302system.cpu1.decode.RunCycles 26726804 # Number of cycles decode is running 2303system.cpu1.decode.UnblockCycles 1110708 # Number of cycles decode is unblocking 2304system.cpu1.decode.SquashCycles 1753136 # Number of cycles decode is squashing 2305system.cpu1.decode.BranchResolved 754254 # Number of times decode resolved a branch 2306system.cpu1.decode.BranchMispred 137537 # Number of times decode detected a branch misprediction 2307system.cpu1.decode.DecodedInsts 68065454 # Number of instructions handled by decode 2308system.cpu1.decode.SquashedInsts 1169726 # Number of squashed instructions handled by decode 2309system.cpu1.rename.SquashCycles 1753136 # Number of cycles rename is squashing 2310system.cpu1.rename.IdleCycles 17456234 # Number of cycles rename is idle 2311system.cpu1.rename.BlockCycles 2244493 # Number of cycles rename is blocking 2312system.cpu1.rename.serializeStallCycles 56986986 # count of cycles rename stalled for serializing inst 2313system.cpu1.rename.RunCycles 23381097 # Number of cycles rename is running 2314system.cpu1.rename.UnblockCycles 2470301 # Number of cycles rename is unblocking 2315system.cpu1.rename.RenamedInsts 55158602 # Number of instructions processed by rename 2316system.cpu1.rename.SquashedInsts 230731 # Number of squashed instructions processed by rename 2317system.cpu1.rename.ROBFullEvents 262273 # Number of times rename has blocked due to ROB full 2318system.cpu1.rename.IQFullEvents 35381 # Number of times rename has blocked due to IQ full 2319system.cpu1.rename.LQFullEvents 18008 # Number of times rename has blocked due to LQ full 2320system.cpu1.rename.SQFullEvents 1443637 # Number of times rename has blocked due to SQ full 2321system.cpu1.rename.RenamedOperands 54999686 # Number of destination operands rename has renamed 2322system.cpu1.rename.RenameLookups 260535269 # Number of register rename lookups that rename has made 2323system.cpu1.rename.int_rename_lookups 58684549 # Number of integer rename lookups 2324system.cpu1.rename.fp_rename_lookups 1692 # Number of floating rename lookups 2325system.cpu1.rename.CommittedMaps 52221656 # Number of HB maps that are committed 2326system.cpu1.rename.UndoneMaps 2778030 # Number of HB maps that are undone due to squashing 2327system.cpu1.rename.serializingInsts 1878103 # count of serializing insts renamed 2328system.cpu1.rename.tempSerializingInsts 1805469 # count of temporary serializing insts renamed 2329system.cpu1.rename.skidInsts 13100518 # count of insts added to the skid buffer 2330system.cpu1.memDep0.insertedLoads 10455886 # Number of loads inserted to the mem dependence unit. 2331system.cpu1.memDep0.insertedStores 6917101 # Number of stores inserted to the mem dependence unit. 2332system.cpu1.memDep0.conflictingLoads 629442 # Number of conflicting loads. 2333system.cpu1.memDep0.conflictingStores 825387 # Number of conflicting stores. 2334system.cpu1.iq.iqInstsAdded 54265513 # Number of instructions added to the IQ (excludes non-spec) 2335system.cpu1.iq.iqNonSpecInstsAdded 589015 # Number of non-speculative instructions added to the IQ 2336system.cpu1.iq.iqInstsIssued 53909819 # Number of instructions issued 2337system.cpu1.iq.iqSquashedInstsIssued 113491 # Number of squashed instructions issued 2338system.cpu1.iq.iqSquashedInstsExamined 2298739 # Number of squashed instructions iterated over during squash; mainly for profiling 2339system.cpu1.iq.iqSquashedOperandsExamined 5813202 # Number of squashed operands that are examined and possibly removed from graph 2340system.cpu1.iq.iqSquashedNonSpecRemoved 48820 # Number of squashed non-spec instructions that were removed 2341system.cpu1.iq.issued_per_cycle::samples 104292247 # Number of insts issued each cycle 2342system.cpu1.iq.issued_per_cycle::mean 0.516911 # Number of insts issued each cycle 2343system.cpu1.iq.issued_per_cycle::stdev 0.852558 # Number of insts issued each cycle |
| 2283system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 2344system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 2284system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle 2285system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle 2286system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle 2287system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle 2288system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle 2289system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle | 2345system.cpu1.iq.issued_per_cycle::0 71040936 68.12% 68.12% # Number of insts issued each cycle 2346system.cpu1.iq.issued_per_cycle::1 16527616 15.85% 83.96% # Number of insts issued each cycle 2347system.cpu1.iq.issued_per_cycle::2 13076642 12.54% 96.50% # Number of insts issued each cycle 2348system.cpu1.iq.issued_per_cycle::3 3359306 3.22% 99.72% # Number of insts issued each cycle 2349system.cpu1.iq.issued_per_cycle::4 287734 0.28% 100.00% # Number of insts issued each cycle 2350system.cpu1.iq.issued_per_cycle::5 13 0.00% 100.00% # Number of insts issued each cycle |
| 2290system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2291system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2292system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2293system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2294system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2295system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 2351system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2352system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2353system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2354system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2355system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2356system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 2296system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle | 2357system.cpu1.iq.issued_per_cycle::total 104292247 # Number of insts issued each cycle |
| 2297system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 2358system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 2298system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available 2299system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available 2300system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available 2301system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available 2302system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available 2303system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available 2304system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available 2305system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available 2306system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available 2307system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available 2308system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available 2309system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available 2310system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available 2311system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available 2312system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available 2313system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available 2314system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available 2315system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available 2316system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available 2317system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available 2318system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available 2319system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available 2320system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available 2321system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available 2322system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available 2323system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available 2324system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available 2325system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available 2326system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available 2327system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available 2328system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available | 2359system.cpu1.iq.fu_full::IntAlu 2924694 45.09% 45.09% # attempts to use FU when none available 2360system.cpu1.iq.fu_full::IntMult 678 0.01% 45.10% # attempts to use FU when none available 2361system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.10% # attempts to use FU when none available 2362system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.10% # attempts to use FU when none available 2363system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.10% # attempts to use FU when none available 2364system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.10% # attempts to use FU when none available 2365system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.10% # attempts to use FU when none available 2366system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.10% # attempts to use FU when none available 2367system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.10% # attempts to use FU when none available 2368system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.10% # attempts to use FU when none available 2369system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.10% # attempts to use FU when none available 2370system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.10% # attempts to use FU when none available 2371system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.10% # attempts to use FU when none available 2372system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.10% # attempts to use FU when none available 2373system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.10% # attempts to use FU when none available 2374system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.10% # attempts to use FU when none available 2375system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.10% # attempts to use FU when none available 2376system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.10% # attempts to use FU when none available 2377system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.10% # attempts to use FU when none available 2378system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.10% # attempts to use FU when none available 2379system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.10% # attempts to use FU when none available 2380system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.10% # attempts to use FU when none available 2381system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.10% # attempts to use FU when none available 2382system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.10% # attempts to use FU when none available 2383system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.10% # attempts to use FU when none available 2384system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.10% # attempts to use FU when none available 2385system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.10% # attempts to use FU when none available 2386system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.10% # attempts to use FU when none available 2387system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.10% # attempts to use FU when none available 2388system.cpu1.iq.fu_full::MemRead 1673523 25.80% 70.90% # attempts to use FU when none available 2389system.cpu1.iq.fu_full::MemWrite 1887909 29.10% 100.00% # attempts to use FU when none available |
| 2329system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2330system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 2390system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2391system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 2331system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued 2332system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued 2333system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued 2334system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued 2335system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued 2336system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued 2337system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued 2338system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued 2339system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued 2340system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued 2341system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued 2342system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued 2343system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued 2344system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued 2345system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued 2346system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued 2347system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued 2348system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued 2349system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued 2350system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued 2351system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued 2352system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued 2353system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued 2354system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued 2355system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued 2356system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued 2357system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued 2358system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued 2359system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued 2360system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued 2361system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued 2362system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued | 2392system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued 2393system.cpu1.iq.FU_type_0::IntAlu 36727877 68.13% 68.13% # Type of FU issued 2394system.cpu1.iq.FU_type_0::IntMult 46567 0.09% 68.21% # Type of FU issued 2395system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued 2396system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued 2397system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued 2398system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued 2399system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued 2400system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued 2401system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued 2402system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued 2403system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued 2404system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued 2405system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued 2406system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued 2407system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued 2408system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued 2409system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued 2410system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued 2411system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued 2412system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued 2413system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued 2414system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued 2415system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued 2416system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued 2417system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued 2418system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued 2419system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 2420system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 2421system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued 2422system.cpu1.iq.FU_type_0::MemRead 10379543 19.25% 87.47% # Type of FU issued 2423system.cpu1.iq.FU_type_0::MemWrite 6752424 12.53% 100.00% # Type of FU issued |
| 2363system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2364system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2424system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2425system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2365system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued 2366system.cpu1.iq.rate 0.149104 # Inst issue rate 2367system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested 2368system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst) 2369system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads 2370system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes 2371system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses 2372system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads 2373system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes 2374system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses 2375system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses 2376system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses 2377system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores | 2426system.cpu1.iq.FU_type_0::total 53909819 # Type of FU issued 2427system.cpu1.iq.rate 0.515224 # Inst issue rate 2428system.cpu1.iq.fu_busy_cnt 6486804 # FU busy when requested 2429system.cpu1.iq.fu_busy_rate 0.120327 # FU busy rate (busy events/executed inst) 2430system.cpu1.iq.int_inst_queue_reads 218706402 # Number of integer instruction queue reads 2431system.cpu1.iq.int_inst_queue_writes 57161340 # Number of integer instruction queue writes 2432system.cpu1.iq.int_inst_queue_wakeup_accesses 51920676 # Number of integer instruction queue wakeup accesses 2433system.cpu1.iq.fp_inst_queue_reads 5778 # Number of floating instruction queue reads 2434system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes 2435system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses 2436system.cpu1.iq.int_alu_accesses 60392866 # Number of integer alu accesses 2437system.cpu1.iq.fp_alu_accesses 3691 # Number of floating point alu accesses 2438system.cpu1.iew.lsq.thread0.forwLoads 91423 # Number of loads that had data forwarded from stores |
| 2378system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2439system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2379system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed 2380system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed 2381system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations 2382system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed | 2440system.cpu1.iew.lsq.thread0.squashedLoads 489842 # Number of loads squashed 2441system.cpu1.iew.lsq.thread0.ignoredResponses 678 # Number of memory responses ignored because the instruction is squashed 2442system.cpu1.iew.lsq.thread0.memOrderViolation 10158 # Number of memory ordering violations 2443system.cpu1.iew.lsq.thread0.squashedStores 359303 # Number of stores squashed |
| 2383system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2384system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2444system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2445system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2385system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled 2386system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked | 2446system.cpu1.iew.lsq.thread0.rescheduledLoads 51794 # Number of loads that were rescheduled 2447system.cpu1.iew.lsq.thread0.cacheBlocked 70407 # Number of times an access to memory failed due to the cache being blocked |
| 2387system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2448system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2388system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing 2389system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking 2390system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking 2391system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ | 2449system.cpu1.iew.iewSquashCycles 1753136 # Number of cycles IEW is squashing 2450system.cpu1.iew.iewBlockCycles 542605 # Number of cycles IEW is blocking 2451system.cpu1.iew.iewUnblockCycles 110606 # Number of cycles IEW is unblocking 2452system.cpu1.iew.iewDispatchedInsts 54906673 # Number of instructions dispatched to IQ |
| 2392system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 2453system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 2393system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions 2394system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions 2395system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions 2396system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall 2397system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall 2398system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations 2399system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly 2400system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly 2401system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute 2402system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions 2403system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed 2404system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute | 2454system.cpu1.iew.iewDispLoadInsts 10455886 # Number of dispatched load instructions 2455system.cpu1.iew.iewDispStoreInsts 6917101 # Number of dispatched store instructions 2456system.cpu1.iew.iewDispNonSpecInsts 301543 # Number of dispatched non-speculative instructions 2457system.cpu1.iew.iewIQFullEvents 9870 # Number of times the IQ has become full, causing a stall 2458system.cpu1.iew.iewLSQFullEvents 93230 # Number of times the LSQ has become full, causing a stall 2459system.cpu1.iew.memOrderViolationEvents 10158 # Number of memory order violations 2460system.cpu1.iew.predictedTakenIncorrect 54900 # Number of branches that were predicted taken incorrectly 2461system.cpu1.iew.predictedNotTakenIncorrect 127108 # Number of branches that were predicted not taken incorrectly 2462system.cpu1.iew.branchMispredicts 182008 # Number of branch mispredicts detected at execute 2463system.cpu1.iew.iewExecutedInsts 53638957 # Number of executed instructions 2464system.cpu1.iew.iewExecLoadInsts 10277477 # Number of load instructions executed 2465system.cpu1.iew.iewExecSquashedInsts 249277 # Number of squashed instructions skipped in execute |
| 2405system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2466system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2406system.cpu1.iew.exec_nop 89541 # number of nop insts executed 2407system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed 2408system.cpu1.iew.exec_branches 6846575 # Number of branches executed 2409system.cpu1.iew.exec_stores 7146063 # Number of stores executed 2410system.cpu1.iew.exec_rate 0.147981 # Inst execution rate 2411system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit 2412system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back 2413system.cpu1.iew.wb_producers 25811466 # num instructions producing a value 2414system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value | 2467system.cpu1.iew.exec_nop 52145 # number of nop insts executed 2468system.cpu1.iew.exec_refs 16965020 # number of memory reference insts executed 2469system.cpu1.iew.exec_branches 11808497 # Number of branches executed 2470system.cpu1.iew.exec_stores 6687543 # Number of stores executed 2471system.cpu1.iew.exec_rate 0.512635 # Inst execution rate 2472system.cpu1.iew.wb_sent 53498311 # cumulative count of insts sent to commit 2473system.cpu1.iew.wb_count 51922462 # cumulative count of insts written-back 2474system.cpu1.iew.wb_producers 25227303 # num instructions producing a value 2475system.cpu1.iew.wb_consumers 38487680 # num instructions consuming a value |
| 2415system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2476system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2416system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle 2417system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back | 2477system.cpu1.iew.wb_rate 0.496230 # insts written-back per cycle 2478system.cpu1.iew.wb_fanout 0.655464 # average fanout of values written-back |
| 2418system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2479system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2419system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit 2420system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards 2421system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted 2422system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle 2423system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle 2424system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle | 2480system.cpu1.commit.commitSquashedInsts 3659313 # The number of squashed insts skipped by commit 2481system.cpu1.commit.commitNonSpecStalls 540195 # The number of times commit has been forced to stall to communicate backwards 2482system.cpu1.commit.branchMispredicts 170379 # The number of times a branch was mispredicted 2483system.cpu1.commit.committed_per_cycle::samples 102361190 # Number of insts commited each cycle 2484system.cpu1.commit.committed_per_cycle::mean 0.498018 # Number of insts commited each cycle 2485system.cpu1.commit.committed_per_cycle::stdev 1.158864 # Number of insts commited each cycle |
| 2425system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2486system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2426system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle 2427system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle 2428system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle 2429system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle 2430system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle 2431system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle 2432system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle 2433system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle 2434system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle | 2487system.cpu1.commit.committed_per_cycle::0 76777637 75.01% 75.01% # Number of insts commited each cycle 2488system.cpu1.commit.committed_per_cycle::1 14293980 13.96% 88.97% # Number of insts commited each cycle 2489system.cpu1.commit.committed_per_cycle::2 6079057 5.94% 94.91% # Number of insts commited each cycle 2490system.cpu1.commit.committed_per_cycle::3 703860 0.69% 95.60% # Number of insts commited each cycle 2491system.cpu1.commit.committed_per_cycle::4 1980599 1.93% 97.53% # Number of insts commited each cycle 2492system.cpu1.commit.committed_per_cycle::5 1570719 1.53% 99.07% # Number of insts commited each cycle 2493system.cpu1.commit.committed_per_cycle::6 440748 0.43% 99.50% # Number of insts commited each cycle 2494system.cpu1.commit.committed_per_cycle::7 123191 0.12% 99.62% # Number of insts commited each cycle 2495system.cpu1.commit.committed_per_cycle::8 391399 0.38% 100.00% # Number of insts commited each cycle |
| 2435system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2436system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2437system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2496system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2497system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2498system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2438system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle 2439system.cpu1.commit.committedInsts 38843249 # Number of instructions committed 2440system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed | 2499system.cpu1.commit.committed_per_cycle::total 102361190 # Number of insts commited each cycle 2500system.cpu1.commit.committedInsts 41391892 # Number of instructions committed 2501system.cpu1.commit.committedOps 50977682 # Number of ops (including micro ops) committed |
| 2441system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2502system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2442system.cpu1.commit.refs 15740654 # Number of memory references committed 2443system.cpu1.commit.loads 8748353 # Number of loads committed 2444system.cpu1.commit.membars 195273 # Number of memory barriers committed 2445system.cpu1.commit.branches 6419002 # Number of branches committed 2446system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 2447system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions. 2448system.cpu1.commit.function_calls 553431 # Number of function calls committed. | 2503system.cpu1.commit.refs 16523842 # Number of memory references committed 2504system.cpu1.commit.loads 9966044 # Number of loads committed 2505system.cpu1.commit.membars 209647 # Number of memory barriers committed 2506system.cpu1.commit.branches 11639863 # Number of branches committed 2507system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. 2508system.cpu1.commit.int_insts 45828051 # Number of committed integer instructions. 2509system.cpu1.commit.function_calls 3366801 # Number of function calls committed. |
| 2449system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 2510system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 2450system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction 2451system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction 2452system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction 2453system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction 2454system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction 2455system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction 2456system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction 2457system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction 2458system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction 2459system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction 2460system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction 2461system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction 2462system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction 2463system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction 2464system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction 2465system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction 2466system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction 2467system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction 2468system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction 2469system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction 2470system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction 2471system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction 2472system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction 2473system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction 2474system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction 2475system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction 2476system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction 2477system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction 2478system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction 2479system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction 2480system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction | 2511system.cpu1.commit.op_class_0::IntAlu 34404842 67.49% 67.49% # Class of committed instruction 2512system.cpu1.commit.op_class_0::IntMult 45659 0.09% 67.58% # Class of committed instruction 2513system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction 2514system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction 2515system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction 2516system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction 2517system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction 2518system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction 2519system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction 2520system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction 2521system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.58% # Class of committed instruction 2522system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.58% # Class of committed instruction 2523system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.58% # Class of committed instruction 2524system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.58% # Class of committed instruction 2525system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.58% # Class of committed instruction 2526system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.58% # Class of committed instruction 2527system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.58% # Class of committed instruction 2528system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.58% # Class of committed instruction 2529system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.58% # Class of committed instruction 2530system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.58% # Class of committed instruction 2531system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.58% # Class of committed instruction 2532system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction 2533system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction 2534system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction 2535system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction 2536system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction 2537system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction 2538system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction 2539system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction 2540system.cpu1.commit.op_class_0::MemRead 9966044 19.55% 87.14% # Class of committed instruction 2541system.cpu1.commit.op_class_0::MemWrite 6557798 12.86% 100.00% # Class of committed instruction |
| 2481system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2482system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2542system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2543system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2483system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction 2484system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached | 2544system.cpu1.commit.op_class_0::total 50977682 # Class of committed instruction 2545system.cpu1.commit.bw_lim_events 391399 # number cycles where commit BW limit reached |
| 2485system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 2546system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2486system.cpu1.rob.rob_reads 483317632 # The number of ROB reads 2487system.cpu1.rob.rob_writes 101136219 # The number of ROB writes 2488system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself 2489system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling 2490system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2491system.cpu1.committedInsts 38773610 # Number of Instructions Simulated 2492system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated 2493system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction 2494system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads 2495system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle 2496system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads 2497system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads 2498system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes 2499system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads 2500system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes 2501system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads 2502system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes 2503system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads 2504system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes 2505system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution 2506system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution 2507system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution 2508system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution 2509system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution 2510system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution 2511system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution 2512system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution 2513system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution 2514system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution 2515system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution 2516system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution 2517system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution 2518system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes) 2519system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes) 2520system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes) 2521system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes) 2522system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes) 2523system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes) 2524system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes) 2525system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes) 2526system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes) 2527system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes) 2528system.cpu1.toL2Bus.snoops 595717 # Total snoops (count) 2529system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram 2530system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram 2531system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram | 2547system.cpu1.rob.rob_reads 136568898 # The number of ROB reads 2548system.cpu1.rob.rob_writes 111201426 # The number of ROB writes 2549system.cpu1.timesIdled 53211 # Number of times that the entire CPU went into an idle state and unscheduled itself 2550system.cpu1.idleCycles 341519 # Total number of cycles that the CPU has spent unscheduled due to idling 2551system.cpu1.quiesceCycles 5543537240 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2552system.cpu1.committedInsts 41359038 # Number of Instructions Simulated 2553system.cpu1.committedOps 50944828 # Number of Ops (including micro ops) Simulated 2554system.cpu1.cpi 2.529889 # CPI: Cycles Per Instruction 2555system.cpu1.cpi_total 2.529889 # CPI: Total CPI of All Threads 2556system.cpu1.ipc 0.395274 # IPC: Instructions Per Cycle 2557system.cpu1.ipc_total 0.395274 # IPC: Total IPC of All Threads 2558system.cpu1.int_regfile_reads 56284416 # number of integer regfile reads 2559system.cpu1.int_regfile_writes 35740317 # number of integer regfile writes 2560system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads 2561system.cpu1.fp_regfile_writes 520 # number of floating regfile writes 2562system.cpu1.cc_regfile_reads 191161573 # number of cc regfile reads 2563system.cpu1.cc_regfile_writes 15561298 # number of cc regfile writes 2564system.cpu1.misc_regfile_reads 205957562 # number of misc regfile reads 2565system.cpu1.misc_regfile_writes 388863 # number of misc regfile writes 2566system.cpu1.toL2Bus.trans_dist::ReadReq 1295443 # Transaction distribution 2567system.cpu1.toL2Bus.trans_dist::ReadResp 865390 # Transaction distribution 2568system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution 2569system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution 2570system.cpu1.toL2Bus.trans_dist::Writeback 116918 # Transaction distribution 2571system.cpu1.toL2Bus.trans_dist::HardPFReq 158167 # Transaction distribution 2572system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution 2573system.cpu1.toL2Bus.trans_dist::UpgradeReq 84977 # Transaction distribution 2574system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41950 # Transaction distribution 2575system.cpu1.toL2Bus.trans_dist::UpgradeResp 87258 # Transaction distribution 2576system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 2577system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution 2578system.cpu1.toL2Bus.trans_dist::ReadExReq 79543 # Transaction distribution 2579system.cpu1.toL2Bus.trans_dist::ReadExResp 66388 # Transaction distribution 2580system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215693 # Packet count per connected master and slave (bytes) 2581system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825104 # Packet count per connected master and slave (bytes) 2582system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17440 # Packet count per connected master and slave (bytes) 2583system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38012 # Packet count per connected master and slave (bytes) 2584system.cpu1.toL2Bus.pkt_count::total 2096249 # Packet count per connected master and slave (bytes) 2585system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897120 # Cumulative packet size per connected master and slave (bytes) 2586system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25415568 # Cumulative packet size per connected master and slave (bytes) 2587system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31072 # Cumulative packet size per connected master and slave (bytes) 2588system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67528 # Cumulative packet size per connected master and slave (bytes) 2589system.cpu1.toL2Bus.pkt_size::total 64411288 # Cumulative packet size per connected master and slave (bytes) 2590system.cpu1.toL2Bus.snoops 836156 # Total snoops (count) 2591system.cpu1.toL2Bus.snoop_fanout::samples 1798706 # Request fanout histogram 2592system.cpu1.toL2Bus.snoop_fanout::mean 5.418986 # Request fanout histogram 2593system.cpu1.toL2Bus.snoop_fanout::stdev 0.493393 # Request fanout histogram |
| 2532system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2533system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2534system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2535system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2536system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2537system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 2594system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2595system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2596system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2597system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2598system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2599system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 2538system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram 2539system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram | 2600system.cpu1.toL2Bus.snoop_fanout::5 1045073 58.10% 58.10% # Request fanout histogram 2601system.cpu1.toL2Bus.snoop_fanout::6 753633 41.90% 100.00% # Request fanout histogram |
| 2540system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2541system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2542system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 2602system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2603system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2604system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 2543system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram 2544system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks) 2545system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2546system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks) | 2605system.cpu1.toL2Bus.snoop_fanout::total 1798706 # Request fanout histogram 2606system.cpu1.toL2Bus.reqLayer0.occupancy 658940429 # Layer occupancy (ticks) 2607system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2608system.cpu1.toL2Bus.snoopLayer0.occupancy 81408998 # Layer occupancy (ticks) |
| 2547system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2609system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2548system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks) | 2610system.cpu1.toL2Bus.respLayer0.occupancy 913008604 # Layer occupancy (ticks) |
| 2549system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2611system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2550system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks) 2551system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 2552system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks) | 2612system.cpu1.toL2Bus.respLayer1.occupancy 404124267 # Layer occupancy (ticks) 2613system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2614system.cpu1.toL2Bus.respLayer2.occupancy 9811221 # Layer occupancy (ticks) |
| 2553system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2615system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2554system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks) | 2616system.cpu1.toL2Bus.respLayer3.occupancy 21199862 # Layer occupancy (ticks) |
| 2555system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2617system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2556system.cpu1.icache.tags.replacements 546235 # number of replacements 2557system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use 2558system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks. 2559system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks. 2560system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks. 2561system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit. 2562system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor 2563system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy 2564system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy | 2618system.cpu1.icache.tags.replacements 607230 # number of replacements 2619system.cpu1.icache.tags.tagsinuse 499.524831 # Cycle average of tags in use 2620system.cpu1.icache.tags.total_refs 43017967 # Total number of references to valid blocks. 2621system.cpu1.icache.tags.sampled_refs 607742 # Sample count of references to valid blocks. 2622system.cpu1.icache.tags.avg_refs 70.783272 # Average number of references to valid blocks. 2623system.cpu1.icache.tags.warmup_cycle 78622263500 # Cycle when the warmup percentage was hit. 2624system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524831 # Average occupied blocks per requestor 2625system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy 2626system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy |
| 2565system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 2627system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 2566system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id | 2628system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2629system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id |
| 2567system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2630system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2568system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses 2569system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses 2570system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits 2571system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits 2572system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits 2573system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits 2574system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits 2575system.cpu1.icache.overall_hits::total 16238797 # number of overall hits 2576system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses 2577system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses 2578system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses 2579system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses 2580system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses 2581system.cpu1.icache.overall_misses::total 562244 # number of overall misses 2582system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles 2583system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles 2584system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles 2585system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles 2586system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles 2587system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles 2588system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses) 2589system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses) 2590system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses 2591system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses 2592system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses 2593system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses 2594system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses 2595system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses 2596system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses 2597system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses 2598system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses 2599system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses 2600system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency 2601system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency 2602system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency 2603system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency 2604system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency 2605system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency 2606system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked 2607system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked 2608system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked 2609system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2610system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked 2611system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked | 2631system.cpu1.icache.tags.tag_accesses 87892389 # Number of tag accesses 2632system.cpu1.icache.tags.data_accesses 87892389 # Number of data accesses 2633system.cpu1.icache.ReadReq_hits::cpu1.inst 43017967 # number of ReadReq hits 2634system.cpu1.icache.ReadReq_hits::total 43017967 # number of ReadReq hits 2635system.cpu1.icache.demand_hits::cpu1.inst 43017967 # number of demand (read+write) hits 2636system.cpu1.icache.demand_hits::total 43017967 # number of demand (read+write) hits 2637system.cpu1.icache.overall_hits::cpu1.inst 43017967 # number of overall hits 2638system.cpu1.icache.overall_hits::total 43017967 # number of overall hits 2639system.cpu1.icache.ReadReq_misses::cpu1.inst 624354 # number of ReadReq misses 2640system.cpu1.icache.ReadReq_misses::total 624354 # number of ReadReq misses 2641system.cpu1.icache.demand_misses::cpu1.inst 624354 # number of demand (read+write) misses 2642system.cpu1.icache.demand_misses::total 624354 # number of demand (read+write) misses 2643system.cpu1.icache.overall_misses::cpu1.inst 624354 # number of overall misses 2644system.cpu1.icache.overall_misses::total 624354 # number of overall misses 2645system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095463294 # number of ReadReq miss cycles 2646system.cpu1.icache.ReadReq_miss_latency::total 5095463294 # number of ReadReq miss cycles 2647system.cpu1.icache.demand_miss_latency::cpu1.inst 5095463294 # number of demand (read+write) miss cycles 2648system.cpu1.icache.demand_miss_latency::total 5095463294 # number of demand (read+write) miss cycles 2649system.cpu1.icache.overall_miss_latency::cpu1.inst 5095463294 # number of overall miss cycles 2650system.cpu1.icache.overall_miss_latency::total 5095463294 # number of overall miss cycles 2651system.cpu1.icache.ReadReq_accesses::cpu1.inst 43642321 # number of ReadReq accesses(hits+misses) 2652system.cpu1.icache.ReadReq_accesses::total 43642321 # number of ReadReq accesses(hits+misses) 2653system.cpu1.icache.demand_accesses::cpu1.inst 43642321 # number of demand (read+write) accesses 2654system.cpu1.icache.demand_accesses::total 43642321 # number of demand (read+write) accesses 2655system.cpu1.icache.overall_accesses::cpu1.inst 43642321 # number of overall (read+write) accesses 2656system.cpu1.icache.overall_accesses::total 43642321 # number of overall (read+write) accesses 2657system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses 2658system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses 2659system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses 2660system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses 2661system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses 2662system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses 2663system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8161.176663 # average ReadReq miss latency 2664system.cpu1.icache.ReadReq_avg_miss_latency::total 8161.176663 # average ReadReq miss latency 2665system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency 2666system.cpu1.icache.demand_avg_miss_latency::total 8161.176663 # average overall miss latency 2667system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency 2668system.cpu1.icache.overall_avg_miss_latency::total 8161.176663 # average overall miss latency 2669system.cpu1.icache.blocked_cycles::no_mshrs 277985 # number of cycles access was blocked 2670system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2671system.cpu1.icache.blocked::no_mshrs 36153 # number of cycles access was blocked 2672system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2673system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.689127 # average number of cycles each access was blocked 2674system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2612system.cpu1.icache.fast_writes 0 # number of fast writes performed 2613system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2675system.cpu1.icache.fast_writes 0 # number of fast writes performed 2676system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2614system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits 2615system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits 2616system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits 2617system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits 2618system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits 2619system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits 2620system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses 2621system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses 2622system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses 2623system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses 2624system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses 2625system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses 2626system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles 2627system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles 2628system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles 2629system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles 2630system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles 2631system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles 2632system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles 2633system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles 2634system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles 2635system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles 2636system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses 2637system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses 2638system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses 2639system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses 2640system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses 2641system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses 2642system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency 2643system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency 2644system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency 2645system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency 2646system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency 2647system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency | 2677system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16607 # number of ReadReq MSHR hits 2678system.cpu1.icache.ReadReq_mshr_hits::total 16607 # number of ReadReq MSHR hits 2679system.cpu1.icache.demand_mshr_hits::cpu1.inst 16607 # number of demand (read+write) MSHR hits 2680system.cpu1.icache.demand_mshr_hits::total 16607 # number of demand (read+write) MSHR hits 2681system.cpu1.icache.overall_mshr_hits::cpu1.inst 16607 # number of overall MSHR hits 2682system.cpu1.icache.overall_mshr_hits::total 16607 # number of overall MSHR hits 2683system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607747 # number of ReadReq MSHR misses 2684system.cpu1.icache.ReadReq_mshr_misses::total 607747 # number of ReadReq MSHR misses 2685system.cpu1.icache.demand_mshr_misses::cpu1.inst 607747 # number of demand (read+write) MSHR misses 2686system.cpu1.icache.demand_mshr_misses::total 607747 # number of demand (read+write) MSHR misses 2687system.cpu1.icache.overall_mshr_misses::cpu1.inst 607747 # number of overall MSHR misses 2688system.cpu1.icache.overall_mshr_misses::total 607747 # number of overall MSHR misses 2689system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4104727229 # number of ReadReq MSHR miss cycles 2690system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104727229 # number of ReadReq MSHR miss cycles 2691system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104727229 # number of demand (read+write) MSHR miss cycles 2692system.cpu1.icache.demand_mshr_miss_latency::total 4104727229 # number of demand (read+write) MSHR miss cycles 2693system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104727229 # number of overall MSHR miss cycles 2694system.cpu1.icache.overall_mshr_miss_latency::total 4104727229 # number of overall MSHR miss cycles 2695system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7919750 # number of ReadReq MSHR uncacheable cycles 2696system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7919750 # number of ReadReq MSHR uncacheable cycles 2697system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7919750 # number of overall MSHR uncacheable cycles 2698system.cpu1.icache.overall_mshr_uncacheable_latency::total 7919750 # number of overall MSHR uncacheable cycles 2699system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses 2700system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 2701system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses 2702system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 2703system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses 2704system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses 2705system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average ReadReq mshr miss latency 2706system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.006567 # average ReadReq mshr miss latency 2707system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency 2708system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency 2709system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency 2710system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency |
| 2648system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2649system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2650system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2651system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2652system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2711system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2712system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2713system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2714system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2715system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2653system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5063185 # number of hwpf identified 2654system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 195793 # number of hwpf that were already in mshr 2655system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4609637 # number of hwpf that were already in the cache 2656system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49643 # number of hwpf that were already in the prefetch queue | 2716system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841798 # number of hwpf identified 2717system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 42982 # number of hwpf that were already in mshr 2718system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639721 # number of hwpf that were already in the cache 2719system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 43013 # number of hwpf that were already in the prefetch queue |
| 2657system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 2720system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 2658system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8256 # number of hwpf removed because MSHR allocated 2659system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 199856 # number of hwpf issued 2660system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 430863 # number of hwpf spanning a virtual page | 2721system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6040 # number of hwpf removed because MSHR allocated 2722system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 110042 # number of hwpf issued 2723system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564522 # number of hwpf spanning a virtual page |
| 2661system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 2724system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 2662system.cpu1.l2cache.tags.replacements 189917 # number of replacements 2663system.cpu1.l2cache.tags.tagsinuse 15760.362755 # Cycle average of tags in use 2664system.cpu1.l2cache.tags.total_refs 1051721 # Total number of references to valid blocks. 2665system.cpu1.l2cache.tags.sampled_refs 205349 # Sample count of references to valid blocks. 2666system.cpu1.l2cache.tags.avg_refs 5.121627 # Average number of references to valid blocks. 2667system.cpu1.l2cache.tags.warmup_cycle 2533057390500 # Cycle when the warmup percentage was hit. 2668system.cpu1.l2cache.tags.occ_blocks::writebacks 4796.141133 # Average occupied blocks per requestor 2669system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.055492 # Average occupied blocks per requestor 2670system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.249384 # Average occupied blocks per requestor 2671system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 825.564654 # Average occupied blocks per requestor 2672system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2172.411955 # Average occupied blocks per requestor 2673system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7947.940138 # Average occupied blocks per requestor 2674system.cpu1.l2cache.tags.occ_percent::writebacks 0.292733 # Average percentage of cache occupancy 2675system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001041 # Average percentage of cache occupancy 2676system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000076 # Average percentage of cache occupancy 2677system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.050388 # Average percentage of cache occupancy 2678system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132594 # Average percentage of cache occupancy 2679system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485104 # Average percentage of cache occupancy 2680system.cpu1.l2cache.tags.occ_percent::total 0.961936 # Average percentage of cache occupancy 2681system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id 2682system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 2683system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id 2684system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id 2685system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id 2686system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id 2687system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id 2688system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 2689system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id 2690system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id 2691system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id 2692system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.514404 # Percentage of cache occupancy per task id 2693system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 2694system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426880 # Percentage of cache occupancy per task id 2695system.cpu1.l2cache.tags.tag_accesses 21502320 # Number of tag accesses 2696system.cpu1.l2cache.tags.data_accesses 21502320 # Number of data accesses 2697system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29274 # number of ReadReq hits 2698system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7085 # number of ReadReq hits 2699system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535244 # number of ReadReq hits 2700system.cpu1.l2cache.ReadReq_hits::cpu1.data 196892 # number of ReadReq hits 2701system.cpu1.l2cache.ReadReq_hits::total 768495 # number of ReadReq hits 2702system.cpu1.l2cache.Writeback_hits::writebacks 291031 # number of Writeback hits 2703system.cpu1.l2cache.Writeback_hits::total 291031 # number of Writeback hits 2704system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2209 # number of UpgradeReq hits 2705system.cpu1.l2cache.UpgradeReq_hits::total 2209 # number of UpgradeReq hits 2706system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1205 # number of SCUpgradeReq hits 2707system.cpu1.l2cache.SCUpgradeReq_hits::total 1205 # number of SCUpgradeReq hits 2708system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122716 # number of ReadExReq hits 2709system.cpu1.l2cache.ReadExReq_hits::total 122716 # number of ReadExReq hits 2710system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29274 # number of demand (read+write) hits 2711system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7085 # number of demand (read+write) hits 2712system.cpu1.l2cache.demand_hits::cpu1.inst 535244 # number of demand (read+write) hits 2713system.cpu1.l2cache.demand_hits::cpu1.data 319608 # number of demand (read+write) hits 2714system.cpu1.l2cache.demand_hits::total 891211 # number of demand (read+write) hits 2715system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29274 # number of overall hits 2716system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7085 # number of overall hits 2717system.cpu1.l2cache.overall_hits::cpu1.inst 535244 # number of overall hits 2718system.cpu1.l2cache.overall_hits::cpu1.data 319608 # number of overall hits 2719system.cpu1.l2cache.overall_hits::total 891211 # number of overall hits 2720system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 364 # number of ReadReq misses 2721system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 158 # number of ReadReq misses 2722system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11361 # number of ReadReq misses 2723system.cpu1.l2cache.ReadReq_misses::cpu1.data 60780 # number of ReadReq misses 2724system.cpu1.l2cache.ReadReq_misses::total 72663 # number of ReadReq misses 2725system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses 2726system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses 2727system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20588 # number of UpgradeReq misses 2728system.cpu1.l2cache.UpgradeReq_misses::total 20588 # number of UpgradeReq misses 2729system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13188 # number of SCUpgradeReq misses 2730system.cpu1.l2cache.SCUpgradeReq_misses::total 13188 # number of SCUpgradeReq misses 2731system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2732system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 2733system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25387 # number of ReadExReq misses 2734system.cpu1.l2cache.ReadExReq_misses::total 25387 # number of ReadExReq misses 2735system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 364 # number of demand (read+write) misses 2736system.cpu1.l2cache.demand_misses::cpu1.itb.walker 158 # number of demand (read+write) misses 2737system.cpu1.l2cache.demand_misses::cpu1.inst 11361 # number of demand (read+write) misses 2738system.cpu1.l2cache.demand_misses::cpu1.data 86167 # number of demand (read+write) misses 2739system.cpu1.l2cache.demand_misses::total 98050 # number of demand (read+write) misses 2740system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 364 # number of overall misses 2741system.cpu1.l2cache.overall_misses::cpu1.itb.walker 158 # number of overall misses 2742system.cpu1.l2cache.overall_misses::cpu1.inst 11361 # number of overall misses 2743system.cpu1.l2cache.overall_misses::cpu1.data 86167 # number of overall misses 2744system.cpu1.l2cache.overall_misses::total 98050 # number of overall misses 2745system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8462000 # number of ReadReq miss cycles 2746system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3365000 # number of ReadReq miss cycles 2747system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344449975 # number of ReadReq miss cycles 2748system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612650155 # number of ReadReq miss cycles 2749system.cpu1.l2cache.ReadReq_miss_latency::total 1968927130 # number of ReadReq miss cycles 2750system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 357562229 # number of UpgradeReq miss cycles 2751system.cpu1.l2cache.UpgradeReq_miss_latency::total 357562229 # number of UpgradeReq miss cycles 2752system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267838079 # number of SCUpgradeReq miss cycles 2753system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267838079 # number of SCUpgradeReq miss cycles 2754system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1192000 # number of SCUpgradeFailReq miss cycles 2755system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1192000 # number of SCUpgradeFailReq miss cycles 2756system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1149303620 # number of ReadExReq miss cycles 2757system.cpu1.l2cache.ReadExReq_miss_latency::total 1149303620 # number of ReadExReq miss cycles 2758system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8462000 # number of demand (read+write) miss cycles 2759system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3365000 # number of demand (read+write) miss cycles 2760system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344449975 # number of demand (read+write) miss cycles 2761system.cpu1.l2cache.demand_miss_latency::cpu1.data 2761953775 # number of demand (read+write) miss cycles 2762system.cpu1.l2cache.demand_miss_latency::total 3118230750 # number of demand (read+write) miss cycles 2763system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8462000 # number of overall miss cycles 2764system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3365000 # number of overall miss cycles 2765system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344449975 # number of overall miss cycles 2766system.cpu1.l2cache.overall_miss_latency::cpu1.data 2761953775 # number of overall miss cycles 2767system.cpu1.l2cache.overall_miss_latency::total 3118230750 # number of overall miss cycles 2768system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29638 # number of ReadReq accesses(hits+misses) 2769system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7243 # number of ReadReq accesses(hits+misses) 2770system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses) 2771system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses) 2772system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses) 2773system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses) 2774system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses) 2775system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses) 2776system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses) 2777system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses) 2778system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses) 2779system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2780system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 2781system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148103 # number of ReadExReq accesses(hits+misses) 2782system.cpu1.l2cache.ReadExReq_accesses::total 148103 # number of ReadExReq accesses(hits+misses) 2783system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29638 # number of demand (read+write) accesses 2784system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7243 # number of demand (read+write) accesses 2785system.cpu1.l2cache.demand_accesses::cpu1.inst 546605 # number of demand (read+write) accesses 2786system.cpu1.l2cache.demand_accesses::cpu1.data 405775 # number of demand (read+write) accesses 2787system.cpu1.l2cache.demand_accesses::total 989261 # number of demand (read+write) accesses 2788system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29638 # number of overall (read+write) accesses 2789system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses 2790system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses 2791system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses 2792system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses 2793system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses 2794system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses 2795system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses 2796system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses 2797system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses 2798system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses 2799system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses 2800system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.903101 # miss rate for UpgradeReq accesses 2801system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.903101 # miss rate for UpgradeReq accesses 2802system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.916279 # miss rate for SCUpgradeReq accesses 2803system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.916279 # miss rate for SCUpgradeReq accesses | 2725system.cpu1.l2cache.tags.replacements 85604 # number of replacements 2726system.cpu1.l2cache.tags.tagsinuse 15613.661542 # Cycle average of tags in use 2727system.cpu1.l2cache.tags.total_refs 844840 # Total number of references to valid blocks. 2728system.cpu1.l2cache.tags.sampled_refs 100686 # Sample count of references to valid blocks. 2729system.cpu1.l2cache.tags.avg_refs 8.390839 # Average number of references to valid blocks. 2730system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2731system.cpu1.l2cache.tags.occ_blocks::writebacks 5991.162043 # Average occupied blocks per requestor 2732system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.384982 # Average occupied blocks per requestor 2733system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.931077 # Average occupied blocks per requestor 2734system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 706.431382 # Average occupied blocks per requestor 2735system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1962.742096 # Average occupied blocks per requestor 2736system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6937.009962 # Average occupied blocks per requestor 2737system.cpu1.l2cache.tags.occ_percent::writebacks 0.365672 # Average percentage of cache occupancy 2738system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000878 # Average percentage of cache occupancy 2739system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy 2740system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.043117 # Average percentage of cache occupancy 2741system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.119796 # Average percentage of cache occupancy 2742system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.423401 # Average percentage of cache occupancy 2743system.cpu1.l2cache.tags.occ_percent::total 0.952982 # Average percentage of cache occupancy 2744system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9479 # Occupied blocks per task id 2745system.cpu1.l2cache.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id 2746system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5582 # Occupied blocks per task id 2747system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id 2748system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8003 # Occupied blocks per task id 2749system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1153 # Occupied blocks per task id 2750system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 2751system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 2752system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 2753system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id 2754system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4223 # Occupied blocks per task id 2755system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 941 # Occupied blocks per task id 2756system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.578552 # Percentage of cache occupancy per task id 2757system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001282 # Percentage of cache occupancy per task id 2758system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.340698 # Percentage of cache occupancy per task id 2759system.cpu1.l2cache.tags.tag_accesses 16875679 # Number of tag accesses 2760system.cpu1.l2cache.tags.data_accesses 16875679 # Number of data accesses 2761system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16408 # number of ReadReq hits 2762system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7497 # number of ReadReq hits 2763system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601881 # number of ReadReq hits 2764system.cpu1.l2cache.ReadReq_hits::cpu1.data 101311 # number of ReadReq hits 2765system.cpu1.l2cache.ReadReq_hits::total 727097 # number of ReadReq hits 2766system.cpu1.l2cache.Writeback_hits::writebacks 116917 # number of Writeback hits 2767system.cpu1.l2cache.Writeback_hits::total 116917 # number of Writeback hits 2768system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits 2769system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits 2770system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 836 # number of SCUpgradeReq hits 2771system.cpu1.l2cache.SCUpgradeReq_hits::total 836 # number of SCUpgradeReq hits 2772system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28901 # number of ReadExReq hits 2773system.cpu1.l2cache.ReadExReq_hits::total 28901 # number of ReadExReq hits 2774system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16408 # number of demand (read+write) hits 2775system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7497 # number of demand (read+write) hits 2776system.cpu1.l2cache.demand_hits::cpu1.inst 601881 # number of demand (read+write) hits 2777system.cpu1.l2cache.demand_hits::cpu1.data 130212 # number of demand (read+write) hits 2778system.cpu1.l2cache.demand_hits::total 755998 # number of demand (read+write) hits 2779system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16408 # number of overall hits 2780system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7497 # number of overall hits 2781system.cpu1.l2cache.overall_hits::cpu1.inst 601881 # number of overall hits 2782system.cpu1.l2cache.overall_hits::cpu1.data 130212 # number of overall hits 2783system.cpu1.l2cache.overall_hits::total 755998 # number of overall hits 2784system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 474 # number of ReadReq misses 2785system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses 2786system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5861 # number of ReadReq misses 2787system.cpu1.l2cache.ReadReq_misses::cpu1.data 72219 # number of ReadReq misses 2788system.cpu1.l2cache.ReadReq_misses::total 78825 # number of ReadReq misses 2789system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 2790system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 2791system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28423 # number of UpgradeReq misses 2792system.cpu1.l2cache.UpgradeReq_misses::total 28423 # number of UpgradeReq misses 2793system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22608 # number of SCUpgradeReq misses 2794system.cpu1.l2cache.SCUpgradeReq_misses::total 22608 # number of SCUpgradeReq misses 2795system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2796system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2797system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32938 # number of ReadExReq misses 2798system.cpu1.l2cache.ReadExReq_misses::total 32938 # number of ReadExReq misses 2799system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 474 # number of demand (read+write) misses 2800system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses 2801system.cpu1.l2cache.demand_misses::cpu1.inst 5861 # number of demand (read+write) misses 2802system.cpu1.l2cache.demand_misses::cpu1.data 105157 # number of demand (read+write) misses 2803system.cpu1.l2cache.demand_misses::total 111763 # number of demand (read+write) misses 2804system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 474 # number of overall misses 2805system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses 2806system.cpu1.l2cache.overall_misses::cpu1.inst 5861 # number of overall misses 2807system.cpu1.l2cache.overall_misses::cpu1.data 105157 # number of overall misses 2808system.cpu1.l2cache.overall_misses::total 111763 # number of overall misses 2809system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10500499 # number of ReadReq miss cycles 2810system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5483500 # number of ReadReq miss cycles 2811system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 182847956 # number of ReadReq miss cycles 2812system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610079123 # number of ReadReq miss cycles 2813system.cpu1.l2cache.ReadReq_miss_latency::total 1808911078 # number of ReadReq miss cycles 2814system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536990378 # number of UpgradeReq miss cycles 2815system.cpu1.l2cache.UpgradeReq_miss_latency::total 536990378 # number of UpgradeReq miss cycles 2816system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 443102047 # number of SCUpgradeReq miss cycles 2817system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443102047 # number of SCUpgradeReq miss cycles 2818system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 554000 # number of SCUpgradeFailReq miss cycles 2819system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 554000 # number of SCUpgradeFailReq miss cycles 2820system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1287438029 # number of ReadExReq miss cycles 2821system.cpu1.l2cache.ReadExReq_miss_latency::total 1287438029 # number of ReadExReq miss cycles 2822system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10500499 # number of demand (read+write) miss cycles 2823system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5483500 # number of demand (read+write) miss cycles 2824system.cpu1.l2cache.demand_miss_latency::cpu1.inst 182847956 # number of demand (read+write) miss cycles 2825system.cpu1.l2cache.demand_miss_latency::cpu1.data 2897517152 # number of demand (read+write) miss cycles 2826system.cpu1.l2cache.demand_miss_latency::total 3096349107 # number of demand (read+write) miss cycles 2827system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10500499 # number of overall miss cycles 2828system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5483500 # number of overall miss cycles 2829system.cpu1.l2cache.overall_miss_latency::cpu1.inst 182847956 # number of overall miss cycles 2830system.cpu1.l2cache.overall_miss_latency::cpu1.data 2897517152 # number of overall miss cycles 2831system.cpu1.l2cache.overall_miss_latency::total 3096349107 # number of overall miss cycles 2832system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16882 # number of ReadReq accesses(hits+misses) 2833system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7768 # number of ReadReq accesses(hits+misses) 2834system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607742 # number of ReadReq accesses(hits+misses) 2835system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173530 # number of ReadReq accesses(hits+misses) 2836system.cpu1.l2cache.ReadReq_accesses::total 805922 # number of ReadReq accesses(hits+misses) 2837system.cpu1.l2cache.Writeback_accesses::writebacks 116918 # number of Writeback accesses(hits+misses) 2838system.cpu1.l2cache.Writeback_accesses::total 116918 # number of Writeback accesses(hits+misses) 2839system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30684 # number of UpgradeReq accesses(hits+misses) 2840system.cpu1.l2cache.UpgradeReq_accesses::total 30684 # number of UpgradeReq accesses(hits+misses) 2841system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23444 # number of SCUpgradeReq accesses(hits+misses) 2842system.cpu1.l2cache.SCUpgradeReq_accesses::total 23444 # number of SCUpgradeReq accesses(hits+misses) 2843system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2844system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2845system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61839 # number of ReadExReq accesses(hits+misses) 2846system.cpu1.l2cache.ReadExReq_accesses::total 61839 # number of ReadExReq accesses(hits+misses) 2847system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16882 # number of demand (read+write) accesses 2848system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7768 # number of demand (read+write) accesses 2849system.cpu1.l2cache.demand_accesses::cpu1.inst 607742 # number of demand (read+write) accesses 2850system.cpu1.l2cache.demand_accesses::cpu1.data 235369 # number of demand (read+write) accesses 2851system.cpu1.l2cache.demand_accesses::total 867761 # number of demand (read+write) accesses 2852system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16882 # number of overall (read+write) accesses 2853system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7768 # number of overall (read+write) accesses 2854system.cpu1.l2cache.overall_accesses::cpu1.inst 607742 # number of overall (read+write) accesses 2855system.cpu1.l2cache.overall_accesses::cpu1.data 235369 # number of overall (read+write) accesses 2856system.cpu1.l2cache.overall_accesses::total 867761 # number of overall (read+write) accesses 2857system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for ReadReq accesses 2858system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.034887 # miss rate for ReadReq accesses 2859system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009644 # miss rate for ReadReq accesses 2860system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.416176 # miss rate for ReadReq accesses 2861system.cpu1.l2cache.ReadReq_miss_rate::total 0.097807 # miss rate for ReadReq accesses 2862system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses 2863system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses 2864system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926313 # miss rate for UpgradeReq accesses 2865system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926313 # miss rate for UpgradeReq accesses 2866system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964341 # miss rate for SCUpgradeReq accesses 2867system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964341 # miss rate for SCUpgradeReq accesses |
| 2804system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2805system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2868system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2869system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2806system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171414 # miss rate for ReadExReq accesses 2807system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171414 # miss rate for ReadExReq accesses 2808system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for demand accesses 2809system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.021814 # miss rate for demand accesses 2810system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020785 # miss rate for demand accesses 2811system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212352 # miss rate for demand accesses 2812system.cpu1.l2cache.demand_miss_rate::total 0.099114 # miss rate for demand accesses 2813system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for overall accesses 2814system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.021814 # miss rate for overall accesses 2815system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020785 # miss rate for overall accesses 2816system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212352 # miss rate for overall accesses 2817system.cpu1.l2cache.overall_miss_rate::total 0.099114 # miss rate for overall accesses 2818system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average ReadReq miss latency 2819system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21297.468354 # average ReadReq miss latency 2820system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency 2821system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency 2822system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency 2823system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency 2824system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency 2825system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency 2826system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency 2827system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency 2828system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency 2829system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45271.344389 # average ReadExReq miss latency 2830system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45271.344389 # average ReadExReq miss latency 2831system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency 2832system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency 2833system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency 2834system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency 2835system.cpu1.l2cache.demand_avg_miss_latency::total 31802.455380 # average overall miss latency 2836system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency 2837system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency 2838system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency 2839system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency 2840system.cpu1.l2cache.overall_avg_miss_latency::total 31802.455380 # average overall miss latency 2841system.cpu1.l2cache.blocked_cycles::no_mshrs 8115 # number of cycles access was blocked | 2870system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532641 # miss rate for ReadExReq accesses 2871system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532641 # miss rate for ReadExReq accesses 2872system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for demand accesses 2873system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.034887 # miss rate for demand accesses 2874system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009644 # miss rate for demand accesses 2875system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446775 # miss rate for demand accesses 2876system.cpu1.l2cache.demand_miss_rate::total 0.128795 # miss rate for demand accesses 2877system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for overall accesses 2878system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.034887 # miss rate for overall accesses 2879system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009644 # miss rate for overall accesses 2880system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446775 # miss rate for overall accesses 2881system.cpu1.l2cache.overall_miss_rate::total 0.128795 # miss rate for overall accesses 2882system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average ReadReq miss latency 2883system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20234.317343 # average ReadReq miss latency 2884system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31197.399079 # average ReadReq miss latency 2885system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22294.397915 # average ReadReq miss latency 2886system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22948.443742 # average ReadReq miss latency 2887system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18892.811385 # average UpgradeReq miss latency 2888system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18892.811385 # average UpgradeReq miss latency 2889system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19599.347443 # average SCUpgradeReq miss latency 2890system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19599.347443 # average SCUpgradeReq miss latency 2891system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 184666.666667 # average SCUpgradeFailReq miss latency 2892system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 184666.666667 # average SCUpgradeFailReq miss latency 2893system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39086.709242 # average ReadExReq miss latency 2894system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39086.709242 # average ReadExReq miss latency 2895system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency 2896system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency 2897system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency 2898system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency 2899system.cpu1.l2cache.demand_avg_miss_latency::total 27704.599080 # average overall miss latency 2900system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency 2901system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency 2902system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency 2903system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency 2904system.cpu1.l2cache.overall_avg_miss_latency::total 27704.599080 # average overall miss latency 2905system.cpu1.l2cache.blocked_cycles::no_mshrs 23432 # number of cycles access was blocked |
| 2842system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2906system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2843system.cpu1.l2cache.blocked::no_mshrs 442 # number of cycles access was blocked | 2907system.cpu1.l2cache.blocked::no_mshrs 464 # number of cycles access was blocked |
| 2844system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2908system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2845system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.359729 # average number of cycles each access was blocked | 2909system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked |
| 2846system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2847system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2848system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2910system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2911system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2912system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2849system.cpu1.l2cache.writebacks::writebacks 108849 # number of writebacks 2850system.cpu1.l2cache.writebacks::total 108849 # number of writebacks 2851system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2852system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2853system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2808 # number of ReadReq MSHR hits 2854system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 143 # number of ReadReq MSHR hits 2855system.cpu1.l2cache.ReadReq_mshr_hits::total 2953 # number of ReadReq MSHR hits 2856system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1573 # number of ReadExReq MSHR hits 2857system.cpu1.l2cache.ReadExReq_mshr_hits::total 1573 # number of ReadExReq MSHR hits 2858system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2859system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 2860system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2808 # number of demand (read+write) MSHR hits 2861system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1716 # number of demand (read+write) MSHR hits 2862system.cpu1.l2cache.demand_mshr_hits::total 4526 # number of demand (read+write) MSHR hits 2863system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2864system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 2865system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2808 # number of overall MSHR hits 2866system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1716 # number of overall MSHR hits 2867system.cpu1.l2cache.overall_mshr_hits::total 4526 # number of overall MSHR hits 2868system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 363 # number of ReadReq MSHR misses 2869system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 157 # number of ReadReq MSHR misses 2870system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8553 # number of ReadReq MSHR misses 2871system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60637 # number of ReadReq MSHR misses 2872system.cpu1.l2cache.ReadReq_mshr_misses::total 69710 # number of ReadReq MSHR misses 2873system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses 2874system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses 2875system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of HardPFReq MSHR misses 2876system.cpu1.l2cache.HardPFReq_mshr_misses::total 199848 # number of HardPFReq MSHR misses 2877system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20588 # number of UpgradeReq MSHR misses 2878system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20588 # number of UpgradeReq MSHR misses 2879system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13188 # number of SCUpgradeReq MSHR misses 2880system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13188 # number of SCUpgradeReq MSHR misses 2881system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2882system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2883system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23814 # number of ReadExReq MSHR misses 2884system.cpu1.l2cache.ReadExReq_mshr_misses::total 23814 # number of ReadExReq MSHR misses 2885system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 363 # number of demand (read+write) MSHR misses 2886system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 157 # number of demand (read+write) MSHR misses 2887system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8553 # number of demand (read+write) MSHR misses 2888system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84451 # number of demand (read+write) MSHR misses 2889system.cpu1.l2cache.demand_mshr_misses::total 93524 # number of demand (read+write) MSHR misses 2890system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 363 # number of overall MSHR misses 2891system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 157 # number of overall MSHR misses 2892system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8553 # number of overall MSHR misses 2893system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84451 # number of overall MSHR misses 2894system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of overall MSHR misses 2895system.cpu1.l2cache.overall_mshr_misses::total 293372 # number of overall MSHR misses 2896system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of ReadReq MSHR miss cycles 2897system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2254500 # number of ReadReq MSHR miss cycles 2898system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 234181256 # number of ReadReq MSHR miss cycles 2899system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1184058953 # number of ReadReq MSHR miss cycles 2900system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1426398709 # number of ReadReq MSHR miss cycles 2901system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of HardPFReq MSHR miss cycles 2902system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles 2903system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles 2904system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles 2905system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles 2906system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles 2907system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles 2908system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles 2909system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles 2910system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of ReadExReq MSHR miss cycles 2911system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles 2912system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2254500 # number of demand (read+write) MSHR miss cycles 2913system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 234181256 # number of demand (read+write) MSHR miss cycles 2914system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1874848035 # number of demand (read+write) MSHR miss cycles 2915system.cpu1.l2cache.demand_mshr_miss_latency::total 2117187791 # number of demand (read+write) MSHR miss cycles 2916system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of overall MSHR miss cycles 2917system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2254500 # number of overall MSHR miss cycles 2918system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 234181256 # number of overall MSHR miss cycles 2919system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1874848035 # number of overall MSHR miss cycles 2920system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles 2921system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles 2922system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles 2923system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles 2924system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles 2925system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles 2926system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles 2927system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles 2928system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204307878917 # number of overall MSHR uncacheable cycles 2929system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204312450917 # number of overall MSHR uncacheable cycles 2930system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for ReadReq accesses 2931system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for ReadReq accesses 2932system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for ReadReq accesses 2933system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.235326 # mshr miss rate for ReadReq accesses 2934system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082874 # mshr miss rate for ReadReq accesses 2935system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses 2936system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses | 2913system.cpu1.l2cache.writebacks::writebacks 40723 # number of writebacks 2914system.cpu1.l2cache.writebacks::total 40723 # number of writebacks 2915system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits 2916system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1292 # number of ReadReq MSHR hits 2917system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 76 # number of ReadReq MSHR hits 2918system.cpu1.l2cache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits 2919system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1310 # number of ReadExReq MSHR hits 2920system.cpu1.l2cache.ReadExReq_mshr_hits::total 1310 # number of ReadExReq MSHR hits 2921system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits 2922system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1292 # number of demand (read+write) MSHR hits 2923system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1386 # number of demand (read+write) MSHR hits 2924system.cpu1.l2cache.demand_mshr_hits::total 2692 # number of demand (read+write) MSHR hits 2925system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits 2926system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1292 # number of overall MSHR hits 2927system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1386 # number of overall MSHR hits 2928system.cpu1.l2cache.overall_mshr_hits::total 2692 # number of overall MSHR hits 2929system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 474 # number of ReadReq MSHR misses 2930system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 257 # number of ReadReq MSHR misses 2931system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4569 # number of ReadReq MSHR misses 2932system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72143 # number of ReadReq MSHR misses 2933system.cpu1.l2cache.ReadReq_mshr_misses::total 77443 # number of ReadReq MSHR misses 2934system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 2935system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 2936system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of HardPFReq MSHR misses 2937system.cpu1.l2cache.HardPFReq_mshr_misses::total 110035 # number of HardPFReq MSHR misses 2938system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28423 # number of UpgradeReq MSHR misses 2939system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28423 # number of UpgradeReq MSHR misses 2940system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22608 # number of SCUpgradeReq MSHR misses 2941system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22608 # number of SCUpgradeReq MSHR misses 2942system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2943system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2944system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31628 # number of ReadExReq MSHR misses 2945system.cpu1.l2cache.ReadExReq_mshr_misses::total 31628 # number of ReadExReq MSHR misses 2946system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 474 # number of demand (read+write) MSHR misses 2947system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 257 # number of demand (read+write) MSHR misses 2948system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4569 # number of demand (read+write) MSHR misses 2949system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103771 # number of demand (read+write) MSHR misses 2950system.cpu1.l2cache.demand_mshr_misses::total 109071 # number of demand (read+write) MSHR misses 2951system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 474 # number of overall MSHR misses 2952system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 257 # number of overall MSHR misses 2953system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4569 # number of overall MSHR misses 2954system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103771 # number of overall MSHR misses 2955system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of overall MSHR misses 2956system.cpu1.l2cache.overall_mshr_misses::total 219106 # number of overall MSHR misses 2957system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of ReadReq MSHR miss cycles 2958system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3513000 # number of ReadReq MSHR miss cycles 2959system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 126144777 # number of ReadReq MSHR miss cycles 2960system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1103468683 # number of ReadReq MSHR miss cycles 2961system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1240306961 # number of ReadReq MSHR miss cycles 2962system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of HardPFReq MSHR miss cycles 2963system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3485961286 # number of HardPFReq MSHR miss cycles 2964system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417373575 # number of UpgradeReq MSHR miss cycles 2965system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417373575 # number of UpgradeReq MSHR miss cycles 2966system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308955268 # number of SCUpgradeReq MSHR miss cycles 2967system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308955268 # number of SCUpgradeReq MSHR miss cycles 2968system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 463000 # number of SCUpgradeFailReq MSHR miss cycles 2969system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 463000 # number of SCUpgradeFailReq MSHR miss cycles 2970system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944601401 # number of ReadExReq MSHR miss cycles 2971system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944601401 # number of ReadExReq MSHR miss cycles 2972system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of demand (read+write) MSHR miss cycles 2973system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3513000 # number of demand (read+write) MSHR miss cycles 2974system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 126144777 # number of demand (read+write) MSHR miss cycles 2975system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2048070084 # number of demand (read+write) MSHR miss cycles 2976system.cpu1.l2cache.demand_mshr_miss_latency::total 2184908362 # number of demand (read+write) MSHR miss cycles 2977system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of overall MSHR miss cycles 2978system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3513000 # number of overall MSHR miss cycles 2979system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 126144777 # number of overall MSHR miss cycles 2980system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2048070084 # number of overall MSHR miss cycles 2981system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of overall MSHR miss cycles 2982system.cpu1.l2cache.overall_mshr_miss_latency::total 5670869648 # number of overall MSHR miss cycles 2983system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7061250 # number of ReadReq MSHR uncacheable cycles 2984system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2181994006 # number of ReadReq MSHR uncacheable cycles 2985system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189055256 # number of ReadReq MSHR uncacheable cycles 2986system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737322501 # number of WriteReq MSHR uncacheable cycles 2987system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737322501 # number of WriteReq MSHR uncacheable cycles 2988system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7061250 # number of overall MSHR uncacheable cycles 2989system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919316507 # number of overall MSHR uncacheable cycles 2990system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926377757 # number of overall MSHR uncacheable cycles 2991system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for ReadReq accesses 2992system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for ReadReq accesses 2993system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for ReadReq accesses 2994system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415738 # mshr miss rate for ReadReq accesses 2995system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096092 # mshr miss rate for ReadReq accesses 2996system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses 2997system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses |
| 2937system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2938system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2998system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2999system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2939system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.903101 # mshr miss rate for UpgradeReq accesses 2940system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.903101 # mshr miss rate for UpgradeReq accesses 2941system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.916279 # mshr miss rate for SCUpgradeReq accesses 2942system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916279 # mshr miss rate for SCUpgradeReq accesses | 3000system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926313 # mshr miss rate for UpgradeReq accesses 3001system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926313 # mshr miss rate for UpgradeReq accesses 3002system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964341 # mshr miss rate for SCUpgradeReq accesses 3003system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964341 # mshr miss rate for SCUpgradeReq accesses |
| 2943system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2944system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 3004system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 3005system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2945system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160794 # mshr miss rate for ReadExReq accesses 2946system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160794 # mshr miss rate for ReadExReq accesses 2947system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for demand accesses 2948system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for demand accesses 2949system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for demand accesses 2950system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for demand accesses 2951system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094539 # mshr miss rate for demand accesses 2952system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for overall accesses 2953system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for overall accesses 2954system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for overall accesses 2955system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for overall accesses | 3006system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.511457 # mshr miss rate for ReadExReq accesses 3007system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.511457 # mshr miss rate for ReadExReq accesses 3008system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for demand accesses 3009system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for demand accesses 3010system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for demand accesses 3011system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for demand accesses 3012system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125692 # mshr miss rate for demand accesses 3013system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for overall accesses 3014system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for overall accesses 3015system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for overall accesses 3016system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for overall accesses |
| 2956system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 3017system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2957system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses 2958system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency 2959system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency 2960system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency 2961system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency 2962system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency 2963system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency 2964system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency 2965system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency 2966system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency 2967system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency 2968system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency 2969system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency 2970system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency 2971system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency 2972system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency 2973system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency 2974system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency 2975system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency 2976system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency 2977system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22637.908890 # average overall mshr miss latency 2978system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency 2979system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency 2980system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency 2981system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency 2982system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency 2983system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency | 3018system.cpu1.l2cache.overall_mshr_miss_rate::total 0.252496 # mshr miss rate for overall accesses 3019system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average ReadReq mshr miss latency 3020system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average ReadReq mshr miss latency 3021system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average ReadReq mshr miss latency 3022system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15295.575219 # average ReadReq mshr miss latency 3023system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16015.740106 # average ReadReq mshr miss latency 3024system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average HardPFReq mshr miss latency 3025system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31680.476994 # average HardPFReq mshr miss latency 3026system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14684.360377 # average UpgradeReq mshr miss latency 3027system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14684.360377 # average UpgradeReq mshr miss latency 3028system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.749646 # average SCUpgradeReq mshr miss latency 3029system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.749646 # average SCUpgradeReq mshr miss latency 3030system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 154333.333333 # average SCUpgradeFailReq mshr miss latency 3031system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 154333.333333 # average SCUpgradeFailReq mshr miss latency 3032system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29865.985867 # average ReadExReq mshr miss latency 3033system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29865.985867 # average ReadExReq mshr miss latency 3034system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency 3035system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency 3036system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency 3037system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency 3038system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20031.982488 # average overall mshr miss latency 3039system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency 3040system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency 3041system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency 3042system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency 3043system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average overall mshr miss latency 3044system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25881.854664 # average overall mshr miss latency |
| 2984system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2985system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2986system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2987system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2988system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2989system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2990system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2991system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2992system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 3045system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3046system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3047system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3048system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3049system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3050system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3051system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3052system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3053system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2993system.cpu1.dcache.tags.replacements 381661 # number of replacements 2994system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use 2995system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks. 2996system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks. 2997system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks. 2998system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit. 2999system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor 3000system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940978 # Average percentage of cache occupancy 3001system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy 3002system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 3003system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id 3004system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id 3005system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses 3006system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses 3007system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits 3008system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits 3009system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits 3010system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits 3011system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits 3012system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits 3013system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits 3014system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits 3015system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits 3016system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits 3017system.cpu1.dcache.demand_hits::cpu1.data 12063851 # number of demand (read+write) hits 3018system.cpu1.dcache.demand_hits::total 12063851 # number of demand (read+write) hits 3019system.cpu1.dcache.overall_hits::cpu1.data 12088353 # number of overall hits 3020system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits 3021system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses 3022system.cpu1.dcache.ReadReq_misses::total 362275 # number of ReadReq misses 3023system.cpu1.dcache.WriteReq_misses::cpu1.data 967298 # number of WriteReq misses 3024system.cpu1.dcache.WriteReq_misses::total 967298 # number of WriteReq misses 3025system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses 3026system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses 3027system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses 3028system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses 3029system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses 3030system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses 3031system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses 3032system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses 3033system.cpu1.dcache.overall_misses::cpu1.data 1377109 # number of overall misses 3034system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses 3035system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles 3036system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles 3037system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles 3038system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles 3039system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles 3040system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles 3041system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles 3042system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles 3043system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles 3044system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles 3045system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles 3046system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles 3047system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles 3048system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles 3049system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses) 3050system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses) 3051system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses) 3052system.cpu1.dcache.WriteReq_accesses::total 5825520 # number of WriteReq accesses(hits+misses) 3053system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 72038 # number of SoftPFReq accesses(hits+misses) 3054system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses) 3055system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses) 3056system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses) 3057system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses) 3058system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses) 3059system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses 3060system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses 3061system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses 3062system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses 3063system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses 3064system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses 3065system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses 3066system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses 3067system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses 3068system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses 3069system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses 3070system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses 3071system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses 3072system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses 3073system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses 3074system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses 3075system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses 3076system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses 3077system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency 3078system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency 3079system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency 3080system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency 3081system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency 3082system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency 3083system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency 3084system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency | 3054system.cpu1.dcache.tags.replacements 191151 # number of replacements 3055system.cpu1.dcache.tags.tagsinuse 472.645791 # Cycle average of tags in use 3056system.cpu1.dcache.tags.total_refs 15740842 # Total number of references to valid blocks. 3057system.cpu1.dcache.tags.sampled_refs 191475 # Sample count of references to valid blocks. 3058system.cpu1.dcache.tags.avg_refs 82.208341 # Average number of references to valid blocks. 3059system.cpu1.dcache.tags.warmup_cycle 102871069000 # Cycle when the warmup percentage was hit. 3060system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.645791 # Average occupied blocks per requestor 3061system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923136 # Average percentage of cache occupancy 3062system.cpu1.dcache.tags.occ_percent::total 0.923136 # Average percentage of cache occupancy 3063system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id 3064system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 3065system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 3066system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id 3067system.cpu1.dcache.tags.tag_accesses 32982505 # Number of tag accesses 3068system.cpu1.dcache.tags.data_accesses 32982505 # Number of data accesses 3069system.cpu1.dcache.ReadReq_hits::cpu1.data 9573878 # number of ReadReq hits 3070system.cpu1.dcache.ReadReq_hits::total 9573878 # number of ReadReq hits 3071system.cpu1.dcache.WriteReq_hits::cpu1.data 5910219 # number of WriteReq hits 3072system.cpu1.dcache.WriteReq_hits::total 5910219 # number of WriteReq hits 3073system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49544 # number of SoftPFReq hits 3074system.cpu1.dcache.SoftPFReq_hits::total 49544 # number of SoftPFReq hits 3075system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79107 # number of LoadLockedReq hits 3076system.cpu1.dcache.LoadLockedReq_hits::total 79107 # number of LoadLockedReq hits 3077system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70933 # number of StoreCondReq hits 3078system.cpu1.dcache.StoreCondReq_hits::total 70933 # number of StoreCondReq hits 3079system.cpu1.dcache.demand_hits::cpu1.data 15484097 # number of demand (read+write) hits 3080system.cpu1.dcache.demand_hits::total 15484097 # number of demand (read+write) hits 3081system.cpu1.dcache.overall_hits::cpu1.data 15533641 # number of overall hits 3082system.cpu1.dcache.overall_hits::total 15533641 # number of overall hits 3083system.cpu1.dcache.ReadReq_misses::cpu1.data 219762 # number of ReadReq misses 3084system.cpu1.dcache.ReadReq_misses::total 219762 # number of ReadReq misses 3085system.cpu1.dcache.WriteReq_misses::cpu1.data 398432 # number of WriteReq misses 3086system.cpu1.dcache.WriteReq_misses::total 398432 # number of WriteReq misses 3087system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30092 # number of SoftPFReq misses 3088system.cpu1.dcache.SoftPFReq_misses::total 30092 # number of SoftPFReq misses 3089system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18147 # number of LoadLockedReq misses 3090system.cpu1.dcache.LoadLockedReq_misses::total 18147 # number of LoadLockedReq misses 3091system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23447 # number of StoreCondReq misses 3092system.cpu1.dcache.StoreCondReq_misses::total 23447 # number of StoreCondReq misses 3093system.cpu1.dcache.demand_misses::cpu1.data 618194 # number of demand (read+write) misses 3094system.cpu1.dcache.demand_misses::total 618194 # number of demand (read+write) misses 3095system.cpu1.dcache.overall_misses::cpu1.data 648286 # number of overall misses 3096system.cpu1.dcache.overall_misses::total 648286 # number of overall misses 3097system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3451433990 # number of ReadReq miss cycles 3098system.cpu1.dcache.ReadReq_miss_latency::total 3451433990 # number of ReadReq miss cycles 3099system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8738929077 # number of WriteReq miss cycles 3100system.cpu1.dcache.WriteReq_miss_latency::total 8738929077 # number of WriteReq miss cycles 3101system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362617750 # number of LoadLockedReq miss cycles 3102system.cpu1.dcache.LoadLockedReq_miss_latency::total 362617750 # number of LoadLockedReq miss cycles 3103system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 543339293 # number of StoreCondReq miss cycles 3104system.cpu1.dcache.StoreCondReq_miss_latency::total 543339293 # number of StoreCondReq miss cycles 3105system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 593000 # number of StoreCondFailReq miss cycles 3106system.cpu1.dcache.StoreCondFailReq_miss_latency::total 593000 # number of StoreCondFailReq miss cycles 3107system.cpu1.dcache.demand_miss_latency::cpu1.data 12190363067 # number of demand (read+write) miss cycles 3108system.cpu1.dcache.demand_miss_latency::total 12190363067 # number of demand (read+write) miss cycles 3109system.cpu1.dcache.overall_miss_latency::cpu1.data 12190363067 # number of overall miss cycles 3110system.cpu1.dcache.overall_miss_latency::total 12190363067 # number of overall miss cycles 3111system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793640 # number of ReadReq accesses(hits+misses) 3112system.cpu1.dcache.ReadReq_accesses::total 9793640 # number of ReadReq accesses(hits+misses) 3113system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308651 # number of WriteReq accesses(hits+misses) 3114system.cpu1.dcache.WriteReq_accesses::total 6308651 # number of WriteReq accesses(hits+misses) 3115system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79636 # number of SoftPFReq accesses(hits+misses) 3116system.cpu1.dcache.SoftPFReq_accesses::total 79636 # number of SoftPFReq accesses(hits+misses) 3117system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97254 # number of LoadLockedReq accesses(hits+misses) 3118system.cpu1.dcache.LoadLockedReq_accesses::total 97254 # number of LoadLockedReq accesses(hits+misses) 3119system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94380 # number of StoreCondReq accesses(hits+misses) 3120system.cpu1.dcache.StoreCondReq_accesses::total 94380 # number of StoreCondReq accesses(hits+misses) 3121system.cpu1.dcache.demand_accesses::cpu1.data 16102291 # number of demand (read+write) accesses 3122system.cpu1.dcache.demand_accesses::total 16102291 # number of demand (read+write) accesses 3123system.cpu1.dcache.overall_accesses::cpu1.data 16181927 # number of overall (read+write) accesses 3124system.cpu1.dcache.overall_accesses::total 16181927 # number of overall (read+write) accesses 3125system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022439 # miss rate for ReadReq accesses 3126system.cpu1.dcache.ReadReq_miss_rate::total 0.022439 # miss rate for ReadReq accesses 3127system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063156 # miss rate for WriteReq accesses 3128system.cpu1.dcache.WriteReq_miss_rate::total 0.063156 # miss rate for WriteReq accesses 3129system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377869 # miss rate for SoftPFReq accesses 3130system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377869 # miss rate for SoftPFReq accesses 3131system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186594 # miss rate for LoadLockedReq accesses 3132system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186594 # miss rate for LoadLockedReq accesses 3133system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248432 # miss rate for StoreCondReq accesses 3134system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248432 # miss rate for StoreCondReq accesses 3135system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038392 # miss rate for demand accesses 3136system.cpu1.dcache.demand_miss_rate::total 0.038392 # miss rate for demand accesses 3137system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040062 # miss rate for overall accesses 3138system.cpu1.dcache.overall_miss_rate::total 0.040062 # miss rate for overall accesses 3139system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15705.326626 # average ReadReq miss latency 3140system.cpu1.dcache.ReadReq_avg_miss_latency::total 15705.326626 # average ReadReq miss latency 3141system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21933.301233 # average WriteReq miss latency 3142system.cpu1.dcache.WriteReq_avg_miss_latency::total 21933.301233 # average WriteReq miss latency 3143system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19982.242244 # average LoadLockedReq miss latency 3144system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19982.242244 # average LoadLockedReq miss latency 3145system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.083678 # average StoreCondReq miss latency 3146system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.083678 # average StoreCondReq miss latency |
| 3085system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 3086system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 3147system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 3148system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 3087system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency 3088system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency 3089system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency 3090system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency 3091system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked 3092system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked 3093system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked 3094system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked 3095system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked 3096system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked | 3149system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19719.316375 # average overall miss latency 3150system.cpu1.dcache.demand_avg_miss_latency::total 19719.316375 # average overall miss latency 3151system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18803.989392 # average overall miss latency 3152system.cpu1.dcache.overall_avg_miss_latency::total 18803.989392 # average overall miss latency 3153system.cpu1.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked 3154system.cpu1.dcache.blocked_cycles::no_targets 1116254 # number of cycles access was blocked 3155system.cpu1.dcache.blocked::no_mshrs 47 # number of cycles access was blocked 3156system.cpu1.dcache.blocked::no_targets 39673 # number of cycles access was blocked 3157system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.191489 # average number of cycles each access was blocked 3158system.cpu1.dcache.avg_blocked_cycles::no_targets 28.136365 # average number of cycles each access was blocked |
| 3097system.cpu1.dcache.fast_writes 0 # number of fast writes performed 3098system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 3159system.cpu1.dcache.fast_writes 0 # number of fast writes performed 3160system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 3099system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks 3100system.cpu1.dcache.writebacks::total 291033 # number of writebacks 3101system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits 3102system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits 3103system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits 3104system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits 3105system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits 3106system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits 3107system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits 3108system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits 3109system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits 3110system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits 3111system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses 3112system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses 3113system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses 3114system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses 3115system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses 3116system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses 3117system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses 3118system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses 3119system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses 3120system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses 3121system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses 3122system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses 3123system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses 3124system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses 3125system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles 3126system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles 3127system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles 3128system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles 3129system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles 3130system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles 3131system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles 3132system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles 3133system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles 3134system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles 3135system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles 3136system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles 3137system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles 3138system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles 3139system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles 3140system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles 3141system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles 3142system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles 3143system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles 3144system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles 3145system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles 3146system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles 3147system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses 3148system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses 3149system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses 3150system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses 3151system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses 3152system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses 3153system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses 3154system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses 3155system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses 3156system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses 3157system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses 3158system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses 3159system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses 3160system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses 3161system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency 3162system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency 3163system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency 3164system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency 3165system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency 3166system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency 3167system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency 3168system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency 3169system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency 3170system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency | 3161system.cpu1.dcache.writebacks::writebacks 116918 # number of writebacks 3162system.cpu1.dcache.writebacks::total 116918 # number of writebacks 3163system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79804 # number of ReadReq MSHR hits 3164system.cpu1.dcache.ReadReq_mshr_hits::total 79804 # number of ReadReq MSHR hits 3165system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306588 # number of WriteReq MSHR hits 3166system.cpu1.dcache.WriteReq_mshr_hits::total 306588 # number of WriteReq MSHR hits 3167system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13195 # number of LoadLockedReq MSHR hits 3168system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13195 # number of LoadLockedReq MSHR hits 3169system.cpu1.dcache.demand_mshr_hits::cpu1.data 386392 # number of demand (read+write) MSHR hits 3170system.cpu1.dcache.demand_mshr_hits::total 386392 # number of demand (read+write) MSHR hits 3171system.cpu1.dcache.overall_mshr_hits::cpu1.data 386392 # number of overall MSHR hits 3172system.cpu1.dcache.overall_mshr_hits::total 386392 # number of overall MSHR hits 3173system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139958 # number of ReadReq MSHR misses 3174system.cpu1.dcache.ReadReq_mshr_misses::total 139958 # number of ReadReq MSHR misses 3175system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91844 # number of WriteReq MSHR misses 3176system.cpu1.dcache.WriteReq_mshr_misses::total 91844 # number of WriteReq MSHR misses 3177system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28639 # number of SoftPFReq MSHR misses 3178system.cpu1.dcache.SoftPFReq_mshr_misses::total 28639 # number of SoftPFReq MSHR misses 3179system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4952 # number of LoadLockedReq MSHR misses 3180system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4952 # number of LoadLockedReq MSHR misses 3181system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23447 # number of StoreCondReq MSHR misses 3182system.cpu1.dcache.StoreCondReq_mshr_misses::total 23447 # number of StoreCondReq MSHR misses 3183system.cpu1.dcache.demand_mshr_misses::cpu1.data 231802 # number of demand (read+write) MSHR misses 3184system.cpu1.dcache.demand_mshr_misses::total 231802 # number of demand (read+write) MSHR misses 3185system.cpu1.dcache.overall_mshr_misses::cpu1.data 260441 # number of overall MSHR misses 3186system.cpu1.dcache.overall_mshr_misses::total 260441 # number of overall MSHR misses 3187system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829576308 # number of ReadReq MSHR miss cycles 3188system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829576308 # number of ReadReq MSHR miss cycles 3189system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2203829941 # number of WriteReq MSHR miss cycles 3190system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2203829941 # number of WriteReq MSHR miss cycles 3191system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493924497 # number of SoftPFReq MSHR miss cycles 3192system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493924497 # number of SoftPFReq MSHR miss cycles 3193system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86545750 # number of LoadLockedReq MSHR miss cycles 3194system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86545750 # number of LoadLockedReq MSHR miss cycles 3195system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 495264707 # number of StoreCondReq MSHR miss cycles 3196system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495264707 # number of StoreCondReq MSHR miss cycles 3197system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 567000 # number of StoreCondFailReq MSHR miss cycles 3198system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 567000 # number of StoreCondFailReq MSHR miss cycles 3199system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4033406249 # number of demand (read+write) MSHR miss cycles 3200system.cpu1.dcache.demand_mshr_miss_latency::total 4033406249 # number of demand (read+write) MSHR miss cycles 3201system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4527330746 # number of overall MSHR miss cycles 3202system.cpu1.dcache.overall_mshr_miss_latency::total 4527330746 # number of overall MSHR miss cycles 3203system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298504494 # number of ReadReq MSHR uncacheable cycles 3204system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298504494 # number of ReadReq MSHR uncacheable cycles 3205system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826458496 # number of WriteReq MSHR uncacheable cycles 3206system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826458496 # number of WriteReq MSHR uncacheable cycles 3207system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4124962990 # number of overall MSHR uncacheable cycles 3208system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4124962990 # number of overall MSHR uncacheable cycles 3209system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014291 # mshr miss rate for ReadReq accesses 3210system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014291 # mshr miss rate for ReadReq accesses 3211system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014558 # mshr miss rate for WriteReq accesses 3212system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014558 # mshr miss rate for WriteReq accesses 3213system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359624 # mshr miss rate for SoftPFReq accesses 3214system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359624 # mshr miss rate for SoftPFReq accesses 3215system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050918 # mshr miss rate for LoadLockedReq accesses 3216system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050918 # mshr miss rate for LoadLockedReq accesses 3217system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248432 # mshr miss rate for StoreCondReq accesses 3218system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248432 # mshr miss rate for StoreCondReq accesses 3219system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014396 # mshr miss rate for demand accesses 3220system.cpu1.dcache.demand_mshr_miss_rate::total 0.014396 # mshr miss rate for demand accesses 3221system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for overall accesses 3222system.cpu1.dcache.overall_mshr_miss_rate::total 0.016095 # mshr miss rate for overall accesses 3223system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13072.323897 # average ReadReq mshr miss latency 3224system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13072.323897 # average ReadReq mshr miss latency 3225system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23995.361058 # average WriteReq mshr miss latency 3226system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23995.361058 # average WriteReq mshr miss latency 3227system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17246.569259 # average SoftPFReq mshr miss latency 3228system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17246.569259 # average SoftPFReq mshr miss latency 3229system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17476.928514 # average LoadLockedReq mshr miss latency 3230system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17476.928514 # average LoadLockedReq mshr miss latency 3231system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21122.732418 # average StoreCondReq mshr miss latency 3232system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21122.732418 # average StoreCondReq mshr miss latency |
| 3171system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 3172system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 3233system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 3234system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 3173system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency 3174system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency 3175system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency 3176system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency | 3235system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17400.221952 # average overall mshr miss latency 3236system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.221952 # average overall mshr miss latency 3237system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17383.325767 # average overall mshr miss latency 3238system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17383.325767 # average overall mshr miss latency |
| 3177system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3178system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3179system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3180system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3181system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3182system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3183system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 3239system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3240system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3241system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3242system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3243system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3244system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3245system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 3184system.iocache.tags.replacements 0 # number of replacements 3185system.iocache.tags.tagsinuse 0 # Cycle average of tags in use | 3246system.iocache.tags.replacements 36453 # number of replacements 3247system.iocache.tags.tagsinuse 14.560241 # Cycle average of tags in use |
| 3186system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 3248system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 3187system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 3188system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 3189system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3190system.iocache.tags.tag_accesses 0 # Number of tag accesses 3191system.iocache.tags.data_accesses 0 # Number of data accesses | 3249system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. 3250system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 3251system.iocache.tags.warmup_cycle 254140751000 # Cycle when the warmup percentage was hit. 3252system.iocache.tags.occ_blocks::realview.ide 14.560241 # Average occupied blocks per requestor 3253system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy 3254system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy 3255system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3256system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3257system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3258system.iocache.tags.tag_accesses 328407 # Number of tag accesses 3259system.iocache.tags.data_accesses 328407 # Number of data accesses 3260system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 3261system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 3262system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses 3263system.iocache.ReadReq_misses::total 247 # number of ReadReq misses 3264system.iocache.WriteInvalidateReq_misses::realview.ide 21 # number of WriteInvalidateReq misses 3265system.iocache.WriteInvalidateReq_misses::total 21 # number of WriteInvalidateReq misses 3266system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses 3267system.iocache.demand_misses::total 247 # number of demand (read+write) misses 3268system.iocache.overall_misses::realview.ide 247 # number of overall misses 3269system.iocache.overall_misses::total 247 # number of overall misses 3270system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles 3271system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles 3272system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles 3273system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles 3274system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles 3275system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles 3276system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) 3277system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) 3278system.iocache.WriteInvalidateReq_accesses::realview.ide 36245 # number of WriteInvalidateReq accesses(hits+misses) 3279system.iocache.WriteInvalidateReq_accesses::total 36245 # number of WriteInvalidateReq accesses(hits+misses) 3280system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses 3281system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses 3282system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses 3283system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses 3284system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3285system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3286system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000579 # miss rate for WriteInvalidateReq accesses 3287system.iocache.WriteInvalidateReq_miss_rate::total 0.000579 # miss rate for WriteInvalidateReq accesses 3288system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3289system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3290system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3291system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3292system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency 3293system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency 3294system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency 3295system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency 3296system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency 3297system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency |
| 3192system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3193system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3194system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3195system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3196system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3197system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 3298system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3299system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3300system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3301system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3302system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3303system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 3198system.iocache.fast_writes 0 # number of fast writes performed | 3304system.iocache.fast_writes 36224 # number of fast writes performed |
| 3199system.iocache.cache_copies 0 # number of cache copies performed | 3305system.iocache.cache_copies 0 # number of cache copies performed |
| 3200system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles 3201system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles 3202system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles 3203system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles 3204system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 3205system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3206system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 3207system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 3306system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses 3307system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses 3308system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses 3309system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses 3310system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses 3311system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses 3312system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles 3313system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles 3314system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2249753293 # number of WriteInvalidateReq MSHR miss cycles 3315system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2249753293 # number of WriteInvalidateReq MSHR miss cycles 3316system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles 3317system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles 3318system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles 3319system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles 3320system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3321system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3322system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3323system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3324system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3325system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3326system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency 3327system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency 3328system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 3329system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 3330system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency 3331system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency 3332system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency 3333system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency |
| 3208system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3209system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 3334system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3335system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 3210system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed | 3336system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed |
| 3211system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3337system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 3212system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed | 3338system.cpu1.kern.inst.quiesce 2758 # number of quiesce instructions executed |
| 3213 3214---------- End Simulation Statistics ---------- | 3339 3340---------- End Simulation Statistics ---------- |