| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.621647 # Number of seconds simulated 4sim_ticks 2621647051000 # Number of ticks simulated 5final_tick 2621647051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.607932 # Number of seconds simulated 4sim_ticks 2607931908500 # Number of ticks simulated 5final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 56801 # Simulator instruction rate (inst/s) 8host_op_rate 68443 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2377539464 # Simulator tick rate (ticks/s) 10host_mem_usage 411700 # Number of bytes of host memory used 11host_seconds 1102.67 # Real time elapsed on the host 12sim_insts 62632896 # Number of instructions simulated 13sim_ops 75470296 # Number of ops (including micro ops) simulated | 7host_inst_rate 43892 # Simulator instruction rate (inst/s) 8host_op_rate 52863 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1823841209 # Simulator tick rate (ticks/s) 10host_mem_usage 431084 # Number of bytes of host memory used 11host_seconds 1429.91 # Real time elapsed on the host 12sim_insts 62761278 # Number of instructions simulated 13sim_ops 75589768 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) |
|
| 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory | 34system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 516048 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 6568572 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 301968 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 2981560 # Number of bytes read from this memory 24system.physmem.bytes_read::total 131479316 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 516048 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 301968 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 818016 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 4189696 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu0.data 3029096 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 31system.physmem.bytes_written::total 7218832 # Number of bytes written to this memory | 35system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory 43system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory 44system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory 45system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory 46system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory 47system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory 48system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory 49system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 50system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 51system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory |
| 32system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory | 52system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 10590 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 102693 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 4761 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 46605 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15303475 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 65464 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 757274 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 822748 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46196351 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 171 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 196841 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 2505513 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 115183 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 1137285 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50151418 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 196841 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 115183 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 312024 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 1598116 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.data 1155417 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::total 2753548 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 1598116 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::realview.clcd 46196351 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.dtb.walker 171 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.inst 196841 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 3660931 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 115183 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 1137300 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 52904966 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 15303475 # Number of read requests accepted 72system.physmem.writeReqs 822748 # Number of write requests accepted 73system.physmem.readBursts 15303475 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 822748 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 977402304 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 2020096 # Total number of bytes read from write queue 77system.physmem.bytesWritten 7239040 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 131479316 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 7218832 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 31564 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 709609 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 12033 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 956536 # Per bank write bursts 84system.physmem.perBankRdBursts::1 956505 # Per bank write bursts 85system.physmem.perBankRdBursts::2 953083 # Per bank write bursts 86system.physmem.perBankRdBursts::3 951219 # Per bank write bursts 87system.physmem.perBankRdBursts::4 959451 # Per bank write bursts 88system.physmem.perBankRdBursts::5 955886 # Per bank write bursts 89system.physmem.perBankRdBursts::6 953593 # Per bank write bursts 90system.physmem.perBankRdBursts::7 950807 # Per bank write bursts 91system.physmem.perBankRdBursts::8 956024 # Per bank write bursts 92system.physmem.perBankRdBursts::9 956507 # Per bank write bursts 93system.physmem.perBankRdBursts::10 953309 # Per bank write bursts 94system.physmem.perBankRdBursts::11 950948 # Per bank write bursts 95system.physmem.perBankRdBursts::12 956403 # Per bank write bursts 96system.physmem.perBankRdBursts::13 956390 # Per bank write bursts 97system.physmem.perBankRdBursts::14 954120 # Per bank write bursts 98system.physmem.perBankRdBursts::15 951130 # Per bank write bursts 99system.physmem.perBankWrBursts::0 7301 # Per bank write bursts 100system.physmem.perBankWrBursts::1 7301 # Per bank write bursts 101system.physmem.perBankWrBursts::2 6635 # Per bank write bursts 102system.physmem.perBankWrBursts::3 6826 # Per bank write bursts 103system.physmem.perBankWrBursts::4 7245 # Per bank write bursts 104system.physmem.perBankWrBursts::5 6961 # Per bank write bursts 105system.physmem.perBankWrBursts::6 7187 # Per bank write bursts 106system.physmem.perBankWrBursts::7 6869 # Per bank write bursts 107system.physmem.perBankWrBursts::8 6823 # Per bank write bursts 108system.physmem.perBankWrBursts::9 7301 # Per bank write bursts 109system.physmem.perBankWrBursts::10 6956 # Per bank write bursts 110system.physmem.perBankWrBursts::11 6738 # Per bank write bursts 111system.physmem.perBankWrBursts::12 7232 # Per bank write bursts 112system.physmem.perBankWrBursts::13 7102 # Per bank write bursts 113system.physmem.perBankWrBursts::14 7378 # Per bank write bursts 114system.physmem.perBankWrBursts::15 7255 # Per bank write bursts | 53system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory 60system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory 61system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory 62system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory 63system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory 64system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 65system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 66system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory 67system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s) 76system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s) 77system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s) 78system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s) 79system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s) 80system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s) 81system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) 83system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s) 84system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s) 85system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s) 94system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s) 95system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s) 96system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s) 97system.physmem.readReqs 15317443 # Number of read requests accepted 98system.physmem.writeReqs 825902 # Number of write requests accepted 99system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue 100system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue 101system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM 102system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue 103system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM 104system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side 105system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side 106system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue 107system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one 108system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write 109system.physmem.perBankRdBursts::0 957415 # Per bank write bursts 110system.physmem.perBankRdBursts::1 954356 # Per bank write bursts 111system.physmem.perBankRdBursts::2 951532 # Per bank write bursts 112system.physmem.perBankRdBursts::3 951095 # Per bank write bursts 113system.physmem.perBankRdBursts::4 960453 # Per bank write bursts 114system.physmem.perBankRdBursts::5 954333 # Per bank write bursts 115system.physmem.perBankRdBursts::6 950562 # Per bank write bursts 116system.physmem.perBankRdBursts::7 950350 # Per bank write bursts 117system.physmem.perBankRdBursts::8 957423 # Per bank write bursts 118system.physmem.perBankRdBursts::9 955252 # Per bank write bursts 119system.physmem.perBankRdBursts::10 950399 # Per bank write bursts 120system.physmem.perBankRdBursts::11 949996 # Per bank write bursts 121system.physmem.perBankRdBursts::12 957025 # Per bank write bursts 122system.physmem.perBankRdBursts::13 954231 # Per bank write bursts 123system.physmem.perBankRdBursts::14 950565 # Per bank write bursts 124system.physmem.perBankRdBursts::15 950154 # Per bank write bursts 125system.physmem.perBankWrBursts::0 7537 # Per bank write bursts 126system.physmem.perBankWrBursts::1 7271 # Per bank write bursts 127system.physmem.perBankWrBursts::2 7519 # Per bank write bursts 128system.physmem.perBankWrBursts::3 7339 # Per bank write bursts 129system.physmem.perBankWrBursts::4 7525 # Per bank write bursts 130system.physmem.perBankWrBursts::5 7506 # Per bank write bursts 131system.physmem.perBankWrBursts::6 7304 # Per bank write bursts 132system.physmem.perBankWrBursts::7 7173 # Per bank write bursts 133system.physmem.perBankWrBursts::8 7520 # Per bank write bursts 134system.physmem.perBankWrBursts::9 7613 # Per bank write bursts 135system.physmem.perBankWrBursts::10 6934 # Per bank write bursts 136system.physmem.perBankWrBursts::11 6533 # Per bank write bursts 137system.physmem.perBankWrBursts::12 7225 # Per bank write bursts 138system.physmem.perBankWrBursts::13 7011 # Per bank write bursts 139system.physmem.perBankWrBursts::14 7249 # Per bank write bursts 140system.physmem.perBankWrBursts::15 7053 # Per bank write bursts |
| 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 141system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 142system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 117system.physmem.totGap 2621645657000 # Total gap between requests | 143system.physmem.totGap 2607930021000 # Total gap between requests |
| 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 59 # Read request sizes (log2) 121system.physmem.readPktSize::3 15138841 # Read request sizes (log2) | 144system.physmem.readPktSize::0 0 # Read request sizes (log2) 145system.physmem.readPktSize::1 0 # Read request sizes (log2) 146system.physmem.readPktSize::2 59 # Read request sizes (log2) 147system.physmem.readPktSize::3 15138841 # Read request sizes (log2) |
| 122system.physmem.readPktSize::4 3426 # Read request sizes (log2) | 148system.physmem.readPktSize::4 3437 # Read request sizes (log2) |
| 123system.physmem.readPktSize::5 0 # Read request sizes (log2) | 149system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 124system.physmem.readPktSize::6 161149 # Read request sizes (log2) | 150system.physmem.readPktSize::6 175106 # Read request sizes (log2) |
| 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 757284 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) | 151system.physmem.writePktSize::0 0 # Write request sizes (log2) 152system.physmem.writePktSize::1 0 # Write request sizes (log2) 153system.physmem.writePktSize::2 757284 # Write request sizes (log2) 154system.physmem.writePktSize::3 0 # Write request sizes (log2) 155system.physmem.writePktSize::4 0 # Write request sizes (log2) 156system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 131system.physmem.writePktSize::6 65464 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 1118217 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 965108 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 965171 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 1074431 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 973448 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 1034951 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 2682221 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 2590422 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 3372339 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 127125 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 101918 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 97549 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 20170 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 19294 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 19015 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::16 55 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 157system.physmem.writePktSize::6 68618 # Write request sizes (log2) 158system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see 187system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 190system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 179system.physmem.wrQLenPdf::15 2804 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 3130 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 5680 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 6732 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 6830 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 6759 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 6721 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 7049 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 6856 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 6768 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 6678 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 6706 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 6721 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 6692 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 6660 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 6637 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see | 205system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see |
| 205system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see | 231system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see |
| 206system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see | 232system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see |
| 219system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 245system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 246system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 247system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 248system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 249system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 250system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 251system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 252system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 253system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 228system.physmem.bytesPerActivate::samples 1014826 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::mean 970.256324 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::gmean 901.955292 # Bytes accessed per row activation 231system.physmem.bytesPerActivate::stdev 206.811149 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::0-127 24748 2.44% 2.44% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::128-255 20792 2.05% 4.49% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::256-383 9109 0.90% 5.39% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::384-511 2441 0.24% 5.63% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::512-639 2631 0.26% 5.88% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::640-767 1759 0.17% 6.06% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::768-895 9074 0.89% 6.95% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::896-1023 1088 0.11% 7.06% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1024-1151 943184 92.94% 100.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::total 1014826 # Bytes accessed per row activation 242system.physmem.rdPerTurnAround::samples 6619 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::mean 2307.281009 # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::stdev 96810.313262 # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::0-262143 6612 99.89% 99.89% # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.91% # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.94% # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 2 0.03% 99.97% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6619 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6619 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 17.088684 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 17.037372 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 1.359683 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16 3686 55.69% 55.69% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::17 52 0.79% 56.47% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::18 1827 27.60% 84.08% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::19 927 14.01% 98.08% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::20 37 0.56% 98.64% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::21 27 0.41% 99.05% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::22 28 0.42% 99.47% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::23 21 0.32% 99.79% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::24 11 0.17% 99.95% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 6619 # Writes before turning the bus around for reads 269system.physmem.totQLat 395207982750 # Total ticks spent queuing 270system.physmem.totMemAccLat 681556314000 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 76359555000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 25878.10 # Average queueing delay per DRAM burst | 254system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation 255system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation 256system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation 257system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation 258system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation 268system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes 269system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes 270system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes 271system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes 272system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes 273system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes 274system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes 275system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes 276system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes 277system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes 278system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads 298system.physmem.totQLat 400005056750 # Total ticks spent queuing 299system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst |
| 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 274system.physmem.avgMemAccLat 44628.10 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 372.82 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 2.76 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 50.15 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s | 303system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s |
| 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 280system.physmem.busUtil 2.93 # Data bus utilization in percentage 281system.physmem.busUtilRead 2.91 # Data bus utilization in percentage for reads | 309system.physmem.busUtil 2.95 # Data bus utilization in percentage 310system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads |
| 282system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 311system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 283system.physmem.avgRdQLen 5.85 # Average read queue length when enqueuing 284system.physmem.avgWrQLen 27.60 # Average write queue length when enqueuing 285system.physmem.readRowHits 14274861 # Number of row buffer hits during reads 286system.physmem.writeRowHits 95334 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes 289system.physmem.avgGap 162570.35 # Average gap between requests 290system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined 291system.physmem.memoryStateTime::IDLE 2271344460000 # Time in different power states 292system.physmem.memoryStateTime::REF 87542520000 # Time in different power states | 312system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing 314system.physmem.readRowHits 14262971 # Number of row buffer hits during reads 315system.physmem.writeRowHits 87526 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes 318system.physmem.avgGap 161548.30 # Average gap between requests 319system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined 320system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states 321system.physmem.memoryStateTime::REF 87084400000 # Time in different power states |
| 293system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 322system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 294system.physmem.memoryStateTime::ACT 262759227500 # Time in different power states | 323system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states |
| 295system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 324system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 296system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory 297system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 298system.realview.nvmem.bytes_read::total 192 # Number of bytes read from this memory 299system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory 300system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 301system.realview.nvmem.bytes_inst_read::total 192 # Number of instructions bytes read from this memory 302system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory 303system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 304system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory 305system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) 306system.realview.nvmem.bw_read::cpu1.inst 55 # Total read bandwidth from this memory (bytes/s) 307system.realview.nvmem.bw_read::total 73 # Total read bandwidth from this memory (bytes/s) 308system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) 309system.realview.nvmem.bw_inst_read::cpu1.inst 55 # Instruction read bandwidth from this memory (bytes/s) 310system.realview.nvmem.bw_inst_read::total 73 # Instruction read bandwidth from this memory (bytes/s) 311system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) 312system.realview.nvmem.bw_total::cpu1.inst 55 # Total bandwidth to/from this memory (bytes/s) 313system.realview.nvmem.bw_total::total 73 # Total bandwidth to/from this memory (bytes/s) 314system.membus.throughput 53827614 # Throughput (bytes/s) 315system.membus.trans_dist::ReadReq 16353736 # Transaction distribution 316system.membus.trans_dist::ReadResp 16353736 # Transaction distribution 317system.membus.trans_dist::WriteReq 768463 # Transaction distribution 318system.membus.trans_dist::WriteResp 768463 # Transaction distribution 319system.membus.trans_dist::Writeback 65464 # Transaction distribution 320system.membus.trans_dist::UpgradeReq 28363 # Transaction distribution 321system.membus.trans_dist::SCUpgradeReq 16887 # Transaction distribution 322system.membus.trans_dist::UpgradeResp 12033 # Transaction distribution 323system.membus.trans_dist::ReadExReq 137713 # Transaction distribution 324system.membus.trans_dist::ReadExResp 137251 # Transaction distribution 325system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384346 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10950 # Packet count per connected master and slave (bytes) | 325system.membus.trans_dist::ReadReq 16496763 # Transaction distribution 326system.membus.trans_dist::ReadResp 16496763 # Transaction distribution 327system.membus.trans_dist::WriteReq 769202 # Transaction distribution 328system.membus.trans_dist::WriteResp 769202 # Transaction distribution 329system.membus.trans_dist::Writeback 68618 # Transaction distribution 330system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution 331system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution 332system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution 333system.membus.trans_dist::ReadExReq 15703 # Transaction distribution 334system.membus.trans_dist::ReadExResp 8933 # Transaction distribution 335system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes) |
| 328system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) | 338system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) |
| 329system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2058 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967095 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.l2c.mem_side::total 4364477 # Packet count per connected master and slave (bytes) | 339system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes) |
| 332system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) | 342system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) |
| 334system.membus.pkt_count::total 34642109 # Packet count per connected master and slave (bytes) 335system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392641 # Cumulative packet size per connected master and slave (bytes) 336system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 192 # Cumulative packet size per connected master and slave (bytes) 337system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 21900 # Cumulative packet size per connected master and slave (bytes) 338system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 339system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4116 # Cumulative packet size per connected master and slave (bytes) 340system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17587620 # Cumulative packet size per connected master and slave (bytes) 341system.membus.tot_pkt_size_system.l2c.mem_side::total 20006477 # Cumulative packet size per connected master and slave (bytes) 342system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 343system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 344system.membus.tot_pkt_size::total 141117005 # Cumulative packet size per connected master and slave (bytes) 345system.membus.data_through_bus 141117005 # Total data (bytes) 346system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 347system.membus.reqLayer0.occupancy 1559281500 # Layer occupancy (ticks) | 344system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes) 345system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes) 352system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 353system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 354system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes) 355system.membus.snoops 72850 # Total snoops (count) 356system.membus.snoop_fanout::samples 332577 # Request fanout histogram 357system.membus.snoop_fanout::mean 1 # Request fanout histogram 358system.membus.snoop_fanout::stdev 0 # Request fanout histogram 359system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 360system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 361system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram 362system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 363system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::min_value 1 # Request fanout histogram 365system.membus.snoop_fanout::max_value 1 # Request fanout histogram 366system.membus.snoop_fanout::total 332577 # Request fanout histogram 367system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks) |
| 348system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 368system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 349system.membus.reqLayer1.occupancy 14500 # Layer occupancy (ticks) | 369system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) |
| 350system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 370system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 351system.membus.reqLayer2.occupancy 9763000 # Layer occupancy (ticks) | 371system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks) |
| 352system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 372system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 353system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) | 373system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) |
| 354system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 374system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 355system.membus.reqLayer5.occupancy 1786500 # Layer occupancy (ticks) | 375system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks) |
| 356system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 376system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 357system.membus.reqLayer6.occupancy 17605374000 # Layer occupancy (ticks) | 377system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks) |
| 358system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 378system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 359system.membus.respLayer1.occupancy 4830238688 # Layer occupancy (ticks) | 379system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks) |
| 360system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 380system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 361system.membus.respLayer2.occupancy 37428300697 # Layer occupancy (ticks) | 381system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks) |
| 362system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 363system.cpu_clk_domain.clock 500 # Clock period in ticks | 382system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 383system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 364system.l2c.tags.replacements 71035 # number of replacements 365system.l2c.tags.tagsinuse 52844.560777 # Cycle average of tags in use 366system.l2c.tags.total_refs 1830685 # Total number of references to valid blocks. 367system.l2c.tags.sampled_refs 136207 # Sample count of references to valid blocks. 368system.l2c.tags.avg_refs 13.440462 # Average number of references to valid blocks. | 384system.l2c.tags.replacements 91666 # number of replacements 385system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use 386system.l2c.tags.total_refs 387443 # Total number of references to valid blocks. 387system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks. 388system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks. |
| 369system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 389system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 370system.l2c.tags.occ_blocks::writebacks 37821.803984 # Average occupied blocks per requestor 371system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.739512 # Average occupied blocks per requestor 372system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000522 # Average occupied blocks per requestor 373system.l2c.tags.occ_blocks::cpu0.inst 5415.027395 # Average occupied blocks per requestor 374system.l2c.tags.occ_blocks::cpu0.data 6377.582658 # Average occupied blocks per requestor 375system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.953654 # Average occupied blocks per requestor 376system.l2c.tags.occ_blocks::cpu1.inst 2390.174334 # Average occupied blocks per requestor 377system.l2c.tags.occ_blocks::cpu1.data 833.278718 # Average occupied blocks per requestor 378system.l2c.tags.occ_percent::writebacks 0.577115 # Average percentage of cache occupancy 379system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000088 # Average percentage of cache occupancy 380system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 381system.l2c.tags.occ_percent::cpu0.inst 0.082627 # Average percentage of cache occupancy 382system.l2c.tags.occ_percent::cpu0.data 0.097314 # Average percentage of cache occupancy 383system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 384system.l2c.tags.occ_percent::cpu1.inst 0.036471 # Average percentage of cache occupancy 385system.l2c.tags.occ_percent::cpu1.data 0.012715 # Average percentage of cache occupancy 386system.l2c.tags.occ_percent::total 0.806344 # Average percentage of cache occupancy 387system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 388system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id 389system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 390system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 391system.l2c.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id 392system.l2c.tags.age_task_id_blocks_1024::2 3098 # Occupied blocks per task id 393system.l2c.tags.age_task_id_blocks_1024::3 8323 # Occupied blocks per task id 394system.l2c.tags.age_task_id_blocks_1024::4 53527 # Occupied blocks per task id 395system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 396system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 397system.l2c.tags.tag_accesses 18484845 # Number of tag accesses 398system.l2c.tags.data_accesses 18484845 # Number of data accesses 399system.l2c.ReadReq_hits::cpu0.dtb.walker 20873 # number of ReadReq hits 400system.l2c.ReadReq_hits::cpu0.itb.walker 5362 # number of ReadReq hits 401system.l2c.ReadReq_hits::cpu0.inst 546777 # number of ReadReq hits 402system.l2c.ReadReq_hits::cpu0.data 243323 # number of ReadReq hits 403system.l2c.ReadReq_hits::cpu1.dtb.walker 15709 # number of ReadReq hits 404system.l2c.ReadReq_hits::cpu1.itb.walker 4324 # number of ReadReq hits 405system.l2c.ReadReq_hits::cpu1.inst 434561 # number of ReadReq hits 406system.l2c.ReadReq_hits::cpu1.data 119239 # number of ReadReq hits 407system.l2c.ReadReq_hits::total 1390168 # number of ReadReq hits 408system.l2c.Writeback_hits::writebacks 583269 # number of Writeback hits 409system.l2c.Writeback_hits::total 583269 # number of Writeback hits 410system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits 411system.l2c.UpgradeReq_hits::cpu1.data 378 # number of UpgradeReq hits 412system.l2c.UpgradeReq_hits::total 1712 # number of UpgradeReq hits 413system.l2c.SCUpgradeReq_hits::cpu0.data 271 # number of SCUpgradeReq hits 414system.l2c.SCUpgradeReq_hits::cpu1.data 117 # number of SCUpgradeReq hits 415system.l2c.SCUpgradeReq_hits::total 388 # number of SCUpgradeReq hits 416system.l2c.ReadExReq_hits::cpu0.data 65538 # number of ReadExReq hits 417system.l2c.ReadExReq_hits::cpu1.data 44550 # number of ReadExReq hits 418system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits 419system.l2c.demand_hits::cpu0.dtb.walker 20873 # number of demand (read+write) hits 420system.l2c.demand_hits::cpu0.itb.walker 5362 # number of demand (read+write) hits 421system.l2c.demand_hits::cpu0.inst 546777 # number of demand (read+write) hits 422system.l2c.demand_hits::cpu0.data 308861 # number of demand (read+write) hits 423system.l2c.demand_hits::cpu1.dtb.walker 15709 # number of demand (read+write) hits 424system.l2c.demand_hits::cpu1.itb.walker 4324 # number of demand (read+write) hits 425system.l2c.demand_hits::cpu1.inst 434561 # number of demand (read+write) hits 426system.l2c.demand_hits::cpu1.data 163789 # number of demand (read+write) hits 427system.l2c.demand_hits::total 1500256 # number of demand (read+write) hits 428system.l2c.overall_hits::cpu0.dtb.walker 20873 # number of overall hits 429system.l2c.overall_hits::cpu0.itb.walker 5362 # number of overall hits 430system.l2c.overall_hits::cpu0.inst 546777 # number of overall hits 431system.l2c.overall_hits::cpu0.data 308861 # number of overall hits 432system.l2c.overall_hits::cpu1.dtb.walker 15709 # number of overall hits 433system.l2c.overall_hits::cpu1.itb.walker 4324 # number of overall hits 434system.l2c.overall_hits::cpu1.inst 434561 # number of overall hits 435system.l2c.overall_hits::cpu1.data 163789 # number of overall hits 436system.l2c.overall_hits::total 1500256 # number of overall hits 437system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses 438system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 439system.l2c.ReadReq_misses::cpu0.inst 7230 # number of ReadReq misses 440system.l2c.ReadReq_misses::cpu0.data 9897 # number of ReadReq misses 441system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses 442system.l2c.ReadReq_misses::cpu1.inst 4714 # number of ReadReq misses 443system.l2c.ReadReq_misses::cpu1.data 2106 # number of ReadReq misses 444system.l2c.ReadReq_misses::total 23958 # number of ReadReq misses 445system.l2c.UpgradeReq_misses::cpu0.data 4509 # number of UpgradeReq misses 446system.l2c.UpgradeReq_misses::cpu1.data 3863 # number of UpgradeReq misses 447system.l2c.UpgradeReq_misses::total 8372 # number of UpgradeReq misses 448system.l2c.SCUpgradeReq_misses::cpu0.data 516 # number of SCUpgradeReq misses 449system.l2c.SCUpgradeReq_misses::cpu1.data 628 # number of SCUpgradeReq misses 450system.l2c.SCUpgradeReq_misses::total 1144 # number of SCUpgradeReq misses 451system.l2c.ReadExReq_misses::cpu0.data 94130 # number of ReadExReq misses 452system.l2c.ReadExReq_misses::cpu1.data 45638 # number of ReadExReq misses 453system.l2c.ReadExReq_misses::total 139768 # number of ReadExReq misses 454system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 455system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 456system.l2c.demand_misses::cpu0.inst 7230 # number of demand (read+write) misses 457system.l2c.demand_misses::cpu0.data 104027 # number of demand (read+write) misses 458system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 459system.l2c.demand_misses::cpu1.inst 4714 # number of demand (read+write) misses 460system.l2c.demand_misses::cpu1.data 47744 # number of demand (read+write) misses 461system.l2c.demand_misses::total 163726 # number of demand (read+write) misses 462system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 463system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 464system.l2c.overall_misses::cpu0.inst 7230 # number of overall misses 465system.l2c.overall_misses::cpu0.data 104027 # number of overall misses 466system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 467system.l2c.overall_misses::cpu1.inst 4714 # number of overall misses 468system.l2c.overall_misses::cpu1.data 47744 # number of overall misses 469system.l2c.overall_misses::total 163726 # number of overall misses 470system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 551500 # number of ReadReq miss cycles 471system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles 472system.l2c.ReadReq_miss_latency::cpu0.inst 522312750 # number of ReadReq miss cycles 473system.l2c.ReadReq_miss_latency::cpu0.data 733828247 # number of ReadReq miss cycles 474system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 83500 # number of ReadReq miss cycles 475system.l2c.ReadReq_miss_latency::cpu1.inst 334292999 # number of ReadReq miss cycles 476system.l2c.ReadReq_miss_latency::cpu1.data 165107999 # number of ReadReq miss cycles 477system.l2c.ReadReq_miss_latency::total 1756326995 # number of ReadReq miss cycles 478system.l2c.UpgradeReq_miss_latency::cpu0.data 11295015 # number of UpgradeReq miss cycles 479system.l2c.UpgradeReq_miss_latency::cpu1.data 12799954 # number of UpgradeReq miss cycles 480system.l2c.UpgradeReq_miss_latency::total 24094969 # number of UpgradeReq miss cycles 481system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1793923 # number of SCUpgradeReq miss cycles 482system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1118952 # number of SCUpgradeReq miss cycles 483system.l2c.SCUpgradeReq_miss_latency::total 2912875 # number of SCUpgradeReq miss cycles 484system.l2c.ReadExReq_miss_latency::cpu0.data 6378706625 # number of ReadExReq miss cycles 485system.l2c.ReadExReq_miss_latency::cpu1.data 3294603599 # number of ReadExReq miss cycles 486system.l2c.ReadExReq_miss_latency::total 9673310224 # number of ReadExReq miss cycles 487system.l2c.demand_miss_latency::cpu0.dtb.walker 551500 # number of demand (read+write) miss cycles 488system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles 489system.l2c.demand_miss_latency::cpu0.inst 522312750 # number of demand (read+write) miss cycles 490system.l2c.demand_miss_latency::cpu0.data 7112534872 # number of demand (read+write) miss cycles 491system.l2c.demand_miss_latency::cpu1.dtb.walker 83500 # number of demand (read+write) miss cycles 492system.l2c.demand_miss_latency::cpu1.inst 334292999 # number of demand (read+write) miss cycles 493system.l2c.demand_miss_latency::cpu1.data 3459711598 # number of demand (read+write) miss cycles 494system.l2c.demand_miss_latency::total 11429637219 # number of demand (read+write) miss cycles 495system.l2c.overall_miss_latency::cpu0.dtb.walker 551500 # number of overall miss cycles 496system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles 497system.l2c.overall_miss_latency::cpu0.inst 522312750 # number of overall miss cycles 498system.l2c.overall_miss_latency::cpu0.data 7112534872 # number of overall miss cycles 499system.l2c.overall_miss_latency::cpu1.dtb.walker 83500 # number of overall miss cycles 500system.l2c.overall_miss_latency::cpu1.inst 334292999 # number of overall miss cycles 501system.l2c.overall_miss_latency::cpu1.data 3459711598 # number of overall miss cycles 502system.l2c.overall_miss_latency::total 11429637219 # number of overall miss cycles 503system.l2c.ReadReq_accesses::cpu0.dtb.walker 20881 # number of ReadReq accesses(hits+misses) 504system.l2c.ReadReq_accesses::cpu0.itb.walker 5364 # number of ReadReq accesses(hits+misses) 505system.l2c.ReadReq_accesses::cpu0.inst 554007 # number of ReadReq accesses(hits+misses) 506system.l2c.ReadReq_accesses::cpu0.data 253220 # number of ReadReq accesses(hits+misses) 507system.l2c.ReadReq_accesses::cpu1.dtb.walker 15710 # number of ReadReq accesses(hits+misses) 508system.l2c.ReadReq_accesses::cpu1.itb.walker 4324 # number of ReadReq accesses(hits+misses) 509system.l2c.ReadReq_accesses::cpu1.inst 439275 # number of ReadReq accesses(hits+misses) 510system.l2c.ReadReq_accesses::cpu1.data 121345 # number of ReadReq accesses(hits+misses) 511system.l2c.ReadReq_accesses::total 1414126 # number of ReadReq accesses(hits+misses) 512system.l2c.Writeback_accesses::writebacks 583269 # number of Writeback accesses(hits+misses) 513system.l2c.Writeback_accesses::total 583269 # number of Writeback accesses(hits+misses) 514system.l2c.UpgradeReq_accesses::cpu0.data 5843 # number of UpgradeReq accesses(hits+misses) 515system.l2c.UpgradeReq_accesses::cpu1.data 4241 # number of UpgradeReq accesses(hits+misses) 516system.l2c.UpgradeReq_accesses::total 10084 # number of UpgradeReq accesses(hits+misses) 517system.l2c.SCUpgradeReq_accesses::cpu0.data 787 # number of SCUpgradeReq accesses(hits+misses) 518system.l2c.SCUpgradeReq_accesses::cpu1.data 745 # number of SCUpgradeReq accesses(hits+misses) 519system.l2c.SCUpgradeReq_accesses::total 1532 # number of SCUpgradeReq accesses(hits+misses) 520system.l2c.ReadExReq_accesses::cpu0.data 159668 # number of ReadExReq accesses(hits+misses) 521system.l2c.ReadExReq_accesses::cpu1.data 90188 # number of ReadExReq accesses(hits+misses) 522system.l2c.ReadExReq_accesses::total 249856 # number of ReadExReq accesses(hits+misses) 523system.l2c.demand_accesses::cpu0.dtb.walker 20881 # number of demand (read+write) accesses 524system.l2c.demand_accesses::cpu0.itb.walker 5364 # number of demand (read+write) accesses 525system.l2c.demand_accesses::cpu0.inst 554007 # number of demand (read+write) accesses 526system.l2c.demand_accesses::cpu0.data 412888 # number of demand (read+write) accesses 527system.l2c.demand_accesses::cpu1.dtb.walker 15710 # number of demand (read+write) accesses 528system.l2c.demand_accesses::cpu1.itb.walker 4324 # number of demand (read+write) accesses 529system.l2c.demand_accesses::cpu1.inst 439275 # number of demand (read+write) accesses 530system.l2c.demand_accesses::cpu1.data 211533 # number of demand (read+write) accesses 531system.l2c.demand_accesses::total 1663982 # number of demand (read+write) accesses 532system.l2c.overall_accesses::cpu0.dtb.walker 20881 # number of overall (read+write) accesses 533system.l2c.overall_accesses::cpu0.itb.walker 5364 # number of overall (read+write) accesses 534system.l2c.overall_accesses::cpu0.inst 554007 # number of overall (read+write) accesses 535system.l2c.overall_accesses::cpu0.data 412888 # number of overall (read+write) accesses 536system.l2c.overall_accesses::cpu1.dtb.walker 15710 # number of overall (read+write) accesses 537system.l2c.overall_accesses::cpu1.itb.walker 4324 # number of overall (read+write) accesses 538system.l2c.overall_accesses::cpu1.inst 439275 # number of overall (read+write) accesses 539system.l2c.overall_accesses::cpu1.data 211533 # number of overall (read+write) accesses 540system.l2c.overall_accesses::total 1663982 # number of overall (read+write) accesses 541system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for ReadReq accesses 542system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000373 # miss rate for ReadReq accesses 543system.l2c.ReadReq_miss_rate::cpu0.inst 0.013050 # miss rate for ReadReq accesses 544system.l2c.ReadReq_miss_rate::cpu0.data 0.039085 # miss rate for ReadReq accesses 545system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for ReadReq accesses 546system.l2c.ReadReq_miss_rate::cpu1.inst 0.010731 # miss rate for ReadReq accesses 547system.l2c.ReadReq_miss_rate::cpu1.data 0.017355 # miss rate for ReadReq accesses 548system.l2c.ReadReq_miss_rate::total 0.016942 # miss rate for ReadReq accesses 549system.l2c.UpgradeReq_miss_rate::cpu0.data 0.771693 # miss rate for UpgradeReq accesses 550system.l2c.UpgradeReq_miss_rate::cpu1.data 0.910870 # miss rate for UpgradeReq accesses 551system.l2c.UpgradeReq_miss_rate::total 0.830226 # miss rate for UpgradeReq accesses 552system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.655654 # miss rate for SCUpgradeReq accesses 553system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.842953 # miss rate for SCUpgradeReq accesses 554system.l2c.SCUpgradeReq_miss_rate::total 0.746736 # miss rate for SCUpgradeReq accesses 555system.l2c.ReadExReq_miss_rate::cpu0.data 0.589536 # miss rate for ReadExReq accesses 556system.l2c.ReadExReq_miss_rate::cpu1.data 0.506032 # miss rate for ReadExReq accesses 557system.l2c.ReadExReq_miss_rate::total 0.559394 # miss rate for ReadExReq accesses 558system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for demand accesses 559system.l2c.demand_miss_rate::cpu0.itb.walker 0.000373 # miss rate for demand accesses 560system.l2c.demand_miss_rate::cpu0.inst 0.013050 # miss rate for demand accesses 561system.l2c.demand_miss_rate::cpu0.data 0.251950 # miss rate for demand accesses 562system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for demand accesses 563system.l2c.demand_miss_rate::cpu1.inst 0.010731 # miss rate for demand accesses 564system.l2c.demand_miss_rate::cpu1.data 0.225705 # miss rate for demand accesses 565system.l2c.demand_miss_rate::total 0.098394 # miss rate for demand accesses 566system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for overall accesses 567system.l2c.overall_miss_rate::cpu0.itb.walker 0.000373 # miss rate for overall accesses 568system.l2c.overall_miss_rate::cpu0.inst 0.013050 # miss rate for overall accesses 569system.l2c.overall_miss_rate::cpu0.data 0.251950 # miss rate for overall accesses 570system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for overall accesses 571system.l2c.overall_miss_rate::cpu1.inst 0.010731 # miss rate for overall accesses 572system.l2c.overall_miss_rate::cpu1.data 0.225705 # miss rate for overall accesses 573system.l2c.overall_miss_rate::total 0.098394 # miss rate for overall accesses 574system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average ReadReq miss latency 575system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 576system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72242.427386 # average ReadReq miss latency 577system.l2c.ReadReq_avg_miss_latency::cpu0.data 74146.534000 # average ReadReq miss latency 578system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83500 # average ReadReq miss latency 579system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70914.934026 # average ReadReq miss latency 580system.l2c.ReadReq_avg_miss_latency::cpu1.data 78398.859924 # average ReadReq miss latency 581system.l2c.ReadReq_avg_miss_latency::total 73308.581476 # average ReadReq miss latency 582system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2504.993347 # average UpgradeReq miss latency 583system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3313.475019 # average UpgradeReq miss latency 584system.l2c.UpgradeReq_avg_miss_latency::total 2878.042164 # average UpgradeReq miss latency 585system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3476.594961 # average SCUpgradeReq miss latency 586system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1781.770701 # average SCUpgradeReq miss latency 587system.l2c.SCUpgradeReq_avg_miss_latency::total 2546.219406 # average SCUpgradeReq miss latency 588system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67764.863752 # average ReadExReq miss latency 589system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72189.920658 # average ReadExReq miss latency 590system.l2c.ReadExReq_avg_miss_latency::total 69209.763494 # average ReadExReq miss latency 591system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average overall miss latency 592system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 593system.l2c.demand_avg_miss_latency::cpu0.inst 72242.427386 # average overall miss latency 594system.l2c.demand_avg_miss_latency::cpu0.data 68372.007959 # average overall miss latency 595system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency 596system.l2c.demand_avg_miss_latency::cpu1.inst 70914.934026 # average overall miss latency 597system.l2c.demand_avg_miss_latency::cpu1.data 72463.798551 # average overall miss latency 598system.l2c.demand_avg_miss_latency::total 69809.542889 # average overall miss latency 599system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average overall miss latency 600system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 601system.l2c.overall_avg_miss_latency::cpu0.inst 72242.427386 # average overall miss latency 602system.l2c.overall_avg_miss_latency::cpu0.data 68372.007959 # average overall miss latency 603system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency 604system.l2c.overall_avg_miss_latency::cpu1.inst 70914.934026 # average overall miss latency 605system.l2c.overall_avg_miss_latency::cpu1.data 72463.798551 # average overall miss latency 606system.l2c.overall_avg_miss_latency::total 69809.542889 # average overall miss latency 607system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 390system.l2c.tags.occ_blocks::writebacks 7736.589041 # Average occupied blocks per requestor 391system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.331203 # Average occupied blocks per requestor 392system.l2c.tags.occ_blocks::cpu0.itb.walker 1.025467 # Average occupied blocks per requestor 393system.l2c.tags.occ_blocks::cpu0.inst 672.803532 # Average occupied blocks per requestor 394system.l2c.tags.occ_blocks::cpu0.data 1677.780077 # Average occupied blocks per requestor 395system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24285.244228 # Average occupied blocks per requestor 396system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.407687 # Average occupied blocks per requestor 397system.l2c.tags.occ_blocks::cpu1.inst 678.722766 # Average occupied blocks per requestor 398system.l2c.tags.occ_blocks::cpu1.data 3493.963497 # Average occupied blocks per requestor 399system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16278.332216 # Average occupied blocks per requestor 400system.l2c.tags.occ_percent::writebacks 0.118051 # Average percentage of cache occupancy 401system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy 402system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 403system.l2c.tags.occ_percent::cpu0.inst 0.010266 # Average percentage of cache occupancy 404system.l2c.tags.occ_percent::cpu0.data 0.025601 # Average percentage of cache occupancy 405system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370563 # Average percentage of cache occupancy 406system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy 407system.l2c.tags.occ_percent::cpu1.inst 0.010356 # Average percentage of cache occupancy 408system.l2c.tags.occ_percent::cpu1.data 0.053314 # Average percentage of cache occupancy 409system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248388 # Average percentage of cache occupancy 410system.l2c.tags.occ_percent::total 0.836658 # Average percentage of cache occupancy 411system.l2c.tags.occ_task_id_blocks::1022 52524 # Occupied blocks per task id 412system.l2c.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 413system.l2c.tags.occ_task_id_blocks::1024 12291 # Occupied blocks per task id 414system.l2c.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id 415system.l2c.tags.age_task_id_blocks_1022::3 5897 # Occupied blocks per task id 416system.l2c.tags.age_task_id_blocks_1022::4 46469 # Occupied blocks per task id 417system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 418system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 419system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 420system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id 421system.l2c.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id 422system.l2c.tags.age_task_id_blocks_1024::3 2272 # Occupied blocks per task id 423system.l2c.tags.age_task_id_blocks_1024::4 9679 # Occupied blocks per task id 424system.l2c.tags.occ_task_id_percent::1022 0.801453 # Percentage of cache occupancy per task id 425system.l2c.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id 426system.l2c.tags.occ_task_id_percent::1024 0.187546 # Percentage of cache occupancy per task id 427system.l2c.tags.tag_accesses 5049935 # Number of tag accesses 428system.l2c.tags.data_accesses 5049935 # Number of data accesses 429system.l2c.ReadReq_hits::cpu0.dtb.walker 116 # number of ReadReq hits 430system.l2c.ReadReq_hits::cpu0.itb.walker 44 # number of ReadReq hits 431system.l2c.ReadReq_hits::cpu0.inst 4746 # number of ReadReq hits 432system.l2c.ReadReq_hits::cpu0.data 14884 # number of ReadReq hits 433system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72204 # number of ReadReq hits 434system.l2c.ReadReq_hits::cpu1.dtb.walker 168 # number of ReadReq hits 435system.l2c.ReadReq_hits::cpu1.itb.walker 72 # number of ReadReq hits 436system.l2c.ReadReq_hits::cpu1.inst 7407 # number of ReadReq hits 437system.l2c.ReadReq_hits::cpu1.data 16636 # number of ReadReq hits 438system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 74707 # number of ReadReq hits 439system.l2c.ReadReq_hits::total 190984 # number of ReadReq hits 440system.l2c.Writeback_hits::writebacks 213987 # number of Writeback hits 441system.l2c.Writeback_hits::total 213987 # number of Writeback hits 442system.l2c.UpgradeReq_hits::cpu0.data 3107 # number of UpgradeReq hits 443system.l2c.UpgradeReq_hits::cpu1.data 2045 # number of UpgradeReq hits 444system.l2c.UpgradeReq_hits::total 5152 # number of UpgradeReq hits 445system.l2c.SCUpgradeReq_hits::cpu0.data 90 # number of SCUpgradeReq hits 446system.l2c.SCUpgradeReq_hits::cpu1.data 245 # number of SCUpgradeReq hits 447system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits 448system.l2c.ReadExReq_hits::cpu0.data 1803 # number of ReadExReq hits 449system.l2c.ReadExReq_hits::cpu1.data 2746 # number of ReadExReq hits 450system.l2c.ReadExReq_hits::total 4549 # number of ReadExReq hits 451system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits 452system.l2c.demand_hits::cpu0.itb.walker 44 # number of demand (read+write) hits 453system.l2c.demand_hits::cpu0.inst 4746 # number of demand (read+write) hits 454system.l2c.demand_hits::cpu0.data 16687 # number of demand (read+write) hits 455system.l2c.demand_hits::cpu0.l2cache.prefetcher 72204 # number of demand (read+write) hits 456system.l2c.demand_hits::cpu1.dtb.walker 168 # number of demand (read+write) hits 457system.l2c.demand_hits::cpu1.itb.walker 72 # number of demand (read+write) hits 458system.l2c.demand_hits::cpu1.inst 7407 # number of demand (read+write) hits 459system.l2c.demand_hits::cpu1.data 19382 # number of demand (read+write) hits 460system.l2c.demand_hits::cpu1.l2cache.prefetcher 74707 # number of demand (read+write) hits 461system.l2c.demand_hits::total 195533 # number of demand (read+write) hits 462system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits 463system.l2c.overall_hits::cpu0.itb.walker 44 # number of overall hits 464system.l2c.overall_hits::cpu0.inst 4746 # number of overall hits 465system.l2c.overall_hits::cpu0.data 16687 # number of overall hits 466system.l2c.overall_hits::cpu0.l2cache.prefetcher 72204 # number of overall hits 467system.l2c.overall_hits::cpu1.dtb.walker 168 # number of overall hits 468system.l2c.overall_hits::cpu1.itb.walker 72 # number of overall hits 469system.l2c.overall_hits::cpu1.inst 7407 # number of overall hits 470system.l2c.overall_hits::cpu1.data 19382 # number of overall hits 471system.l2c.overall_hits::cpu1.l2cache.prefetcher 74707 # number of overall hits 472system.l2c.overall_hits::total 195533 # number of overall hits 473system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses 474system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 475system.l2c.ReadReq_misses::cpu0.inst 1063 # number of ReadReq misses 476system.l2c.ReadReq_misses::cpu0.data 3259 # number of ReadReq misses 477system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq misses 478system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses 479system.l2c.ReadReq_misses::cpu1.inst 1104 # number of ReadReq misses 480system.l2c.ReadReq_misses::cpu1.data 4621 # number of ReadReq misses 481system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq misses 482system.l2c.ReadReq_misses::total 166173 # number of ReadReq misses 483system.l2c.UpgradeReq_misses::cpu0.data 7830 # number of UpgradeReq misses 484system.l2c.UpgradeReq_misses::cpu1.data 5610 # number of UpgradeReq misses 485system.l2c.UpgradeReq_misses::total 13440 # number of UpgradeReq misses 486system.l2c.SCUpgradeReq_misses::cpu0.data 1272 # number of SCUpgradeReq misses 487system.l2c.SCUpgradeReq_misses::cpu1.data 1187 # number of SCUpgradeReq misses 488system.l2c.SCUpgradeReq_misses::total 2459 # number of SCUpgradeReq misses 489system.l2c.ReadExReq_misses::cpu0.data 3945 # number of ReadExReq misses 490system.l2c.ReadExReq_misses::cpu1.data 5092 # number of ReadExReq misses 491system.l2c.ReadExReq_misses::total 9037 # number of ReadExReq misses 492system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses 493system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 494system.l2c.demand_misses::cpu0.inst 1063 # number of demand (read+write) misses 495system.l2c.demand_misses::cpu0.data 7204 # number of demand (read+write) misses 496system.l2c.demand_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) misses 497system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses 498system.l2c.demand_misses::cpu1.inst 1104 # number of demand (read+write) misses 499system.l2c.demand_misses::cpu1.data 9713 # number of demand (read+write) misses 500system.l2c.demand_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) misses 501system.l2c.demand_misses::total 175210 # number of demand (read+write) misses 502system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses 503system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 504system.l2c.overall_misses::cpu0.inst 1063 # number of overall misses 505system.l2c.overall_misses::cpu0.data 7204 # number of overall misses 506system.l2c.overall_misses::cpu0.l2cache.prefetcher 72015 # number of overall misses 507system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses 508system.l2c.overall_misses::cpu1.inst 1104 # number of overall misses 509system.l2c.overall_misses::cpu1.data 9713 # number of overall misses 510system.l2c.overall_misses::cpu1.l2cache.prefetcher 84097 # number of overall misses 511system.l2c.overall_misses::total 175210 # number of overall misses 512system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195250 # number of ReadReq miss cycles 513system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182000 # number of ReadReq miss cycles 514system.l2c.ReadReq_miss_latency::cpu0.inst 88517249 # number of ReadReq miss cycles 515system.l2c.ReadReq_miss_latency::cpu0.data 251848999 # number of ReadReq miss cycles 516system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of ReadReq miss cycles 517system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 744500 # number of ReadReq miss cycles 518system.l2c.ReadReq_miss_latency::cpu1.inst 96486500 # number of ReadReq miss cycles 519system.l2c.ReadReq_miss_latency::cpu1.data 359268498 # number of ReadReq miss cycles 520system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of ReadReq miss cycles 521system.l2c.ReadReq_miss_latency::total 17143743646 # number of ReadReq miss cycles 522system.l2c.UpgradeReq_miss_latency::cpu0.data 12214974 # number of UpgradeReq miss cycles 523system.l2c.UpgradeReq_miss_latency::cpu1.data 6369731 # number of UpgradeReq miss cycles 524system.l2c.UpgradeReq_miss_latency::total 18584705 # number of UpgradeReq miss cycles 525system.l2c.SCUpgradeReq_miss_latency::cpu0.data 508980 # number of SCUpgradeReq miss cycles 526system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4358314 # number of SCUpgradeReq miss cycles 527system.l2c.SCUpgradeReq_miss_latency::total 4867294 # number of SCUpgradeReq miss cycles 528system.l2c.ReadExReq_miss_latency::cpu0.data 294129193 # number of ReadExReq miss cycles 529system.l2c.ReadExReq_miss_latency::cpu1.data 380271953 # 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number of demand (read+write) miss cycles 540system.l2c.demand_miss_latency::total 17818144792 # number of demand (read+write) miss cycles 541system.l2c.overall_miss_latency::cpu0.dtb.walker 195250 # number of overall miss cycles 542system.l2c.overall_miss_latency::cpu0.itb.walker 182000 # number of overall miss cycles 543system.l2c.overall_miss_latency::cpu0.inst 88517249 # number of overall miss cycles 544system.l2c.overall_miss_latency::cpu0.data 545978192 # number of overall miss cycles 545system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of overall miss cycles 546system.l2c.overall_miss_latency::cpu1.dtb.walker 744500 # number of overall miss cycles 547system.l2c.overall_miss_latency::cpu1.inst 96486500 # number of overall miss cycles 548system.l2c.overall_miss_latency::cpu1.data 739540451 # number of overall miss cycles 549system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of overall miss cycles 550system.l2c.overall_miss_latency::total 17818144792 # number of overall miss cycles 551system.l2c.ReadReq_accesses::cpu0.dtb.walker 119 # number of ReadReq accesses(hits+misses) 552system.l2c.ReadReq_accesses::cpu0.itb.walker 47 # number of ReadReq accesses(hits+misses) 553system.l2c.ReadReq_accesses::cpu0.inst 5809 # number of ReadReq accesses(hits+misses) 554system.l2c.ReadReq_accesses::cpu0.data 18143 # number of ReadReq accesses(hits+misses) 555system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144219 # number of ReadReq accesses(hits+misses) 556system.l2c.ReadReq_accesses::cpu1.dtb.walker 176 # number of ReadReq accesses(hits+misses) 557system.l2c.ReadReq_accesses::cpu1.itb.walker 72 # number of ReadReq accesses(hits+misses) 558system.l2c.ReadReq_accesses::cpu1.inst 8511 # number of ReadReq accesses(hits+misses) 559system.l2c.ReadReq_accesses::cpu1.data 21257 # number of ReadReq accesses(hits+misses) 560system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 158804 # number of ReadReq accesses(hits+misses) 561system.l2c.ReadReq_accesses::total 357157 # number of ReadReq accesses(hits+misses) 562system.l2c.Writeback_accesses::writebacks 213987 # number of Writeback accesses(hits+misses) 563system.l2c.Writeback_accesses::total 213987 # number of Writeback accesses(hits+misses) 564system.l2c.UpgradeReq_accesses::cpu0.data 10937 # number of UpgradeReq accesses(hits+misses) 565system.l2c.UpgradeReq_accesses::cpu1.data 7655 # number of UpgradeReq accesses(hits+misses) 566system.l2c.UpgradeReq_accesses::total 18592 # number of UpgradeReq accesses(hits+misses) 567system.l2c.SCUpgradeReq_accesses::cpu0.data 1362 # number of SCUpgradeReq accesses(hits+misses) 568system.l2c.SCUpgradeReq_accesses::cpu1.data 1432 # number of SCUpgradeReq accesses(hits+misses) 569system.l2c.SCUpgradeReq_accesses::total 2794 # number of SCUpgradeReq accesses(hits+misses) 570system.l2c.ReadExReq_accesses::cpu0.data 5748 # number of ReadExReq accesses(hits+misses) 571system.l2c.ReadExReq_accesses::cpu1.data 7838 # number of ReadExReq accesses(hits+misses) 572system.l2c.ReadExReq_accesses::total 13586 # number of ReadExReq accesses(hits+misses) 573system.l2c.demand_accesses::cpu0.dtb.walker 119 # number of demand (read+write) accesses 574system.l2c.demand_accesses::cpu0.itb.walker 47 # number of demand (read+write) accesses 575system.l2c.demand_accesses::cpu0.inst 5809 # number of demand (read+write) accesses 576system.l2c.demand_accesses::cpu0.data 23891 # number of demand (read+write) accesses 577system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144219 # number of demand (read+write) accesses 578system.l2c.demand_accesses::cpu1.dtb.walker 176 # number of demand (read+write) accesses 579system.l2c.demand_accesses::cpu1.itb.walker 72 # number of demand (read+write) accesses 580system.l2c.demand_accesses::cpu1.inst 8511 # number of demand (read+write) accesses 581system.l2c.demand_accesses::cpu1.data 29095 # number of demand (read+write) accesses 582system.l2c.demand_accesses::cpu1.l2cache.prefetcher 158804 # number of demand (read+write) accesses 583system.l2c.demand_accesses::total 370743 # number of demand (read+write) accesses 584system.l2c.overall_accesses::cpu0.dtb.walker 119 # number of overall (read+write) accesses 585system.l2c.overall_accesses::cpu0.itb.walker 47 # number of overall (read+write) accesses 586system.l2c.overall_accesses::cpu0.inst 5809 # number of overall (read+write) accesses 587system.l2c.overall_accesses::cpu0.data 23891 # number of overall (read+write) accesses 588system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144219 # number of overall (read+write) accesses 589system.l2c.overall_accesses::cpu1.dtb.walker 176 # number of overall (read+write) accesses 590system.l2c.overall_accesses::cpu1.itb.walker 72 # number of overall (read+write) accesses 591system.l2c.overall_accesses::cpu1.inst 8511 # number of overall (read+write) accesses 592system.l2c.overall_accesses::cpu1.data 29095 # number of overall (read+write) accesses 593system.l2c.overall_accesses::cpu1.l2cache.prefetcher 158804 # number of overall (read+write) accesses 594system.l2c.overall_accesses::total 370743 # number of overall (read+write) accesses 595system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for ReadReq accesses 596system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.063830 # miss rate for ReadReq accesses 597system.l2c.ReadReq_miss_rate::cpu0.inst 0.182992 # miss rate for ReadReq accesses 598system.l2c.ReadReq_miss_rate::cpu0.data 0.179629 # miss rate for ReadReq accesses 599system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for ReadReq accesses 600system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses 601system.l2c.ReadReq_miss_rate::cpu1.inst 0.129714 # miss rate for ReadReq accesses 602system.l2c.ReadReq_miss_rate::cpu1.data 0.217387 # miss rate for ReadReq accesses 603system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for ReadReq accesses 604system.l2c.ReadReq_miss_rate::total 0.465266 # miss rate for ReadReq accesses 605system.l2c.UpgradeReq_miss_rate::cpu0.data 0.715918 # miss rate for UpgradeReq accesses 606system.l2c.UpgradeReq_miss_rate::cpu1.data 0.732854 # miss rate for UpgradeReq accesses 607system.l2c.UpgradeReq_miss_rate::total 0.722892 # miss rate for UpgradeReq accesses 608system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.933921 # miss rate for SCUpgradeReq accesses 609system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828911 # miss rate for SCUpgradeReq accesses 610system.l2c.SCUpgradeReq_miss_rate::total 0.880100 # miss rate for SCUpgradeReq accesses 611system.l2c.ReadExReq_miss_rate::cpu0.data 0.686326 # miss rate for ReadExReq accesses 612system.l2c.ReadExReq_miss_rate::cpu1.data 0.649656 # miss rate for ReadExReq accesses 613system.l2c.ReadExReq_miss_rate::total 0.665170 # miss rate for ReadExReq accesses 614system.l2c.demand_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for demand accesses 615system.l2c.demand_miss_rate::cpu0.itb.walker 0.063830 # miss rate for demand accesses 616system.l2c.demand_miss_rate::cpu0.inst 0.182992 # miss rate for demand accesses 617system.l2c.demand_miss_rate::cpu0.data 0.301536 # miss rate for demand accesses 618system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for demand accesses 619system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses 620system.l2c.demand_miss_rate::cpu1.inst 0.129714 # miss rate for demand accesses 621system.l2c.demand_miss_rate::cpu1.data 0.333837 # miss rate for demand accesses 622system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for demand accesses 623system.l2c.demand_miss_rate::total 0.472592 # miss rate for demand accesses 624system.l2c.overall_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for overall accesses 625system.l2c.overall_miss_rate::cpu0.itb.walker 0.063830 # miss rate for overall accesses 626system.l2c.overall_miss_rate::cpu0.inst 0.182992 # miss rate for overall accesses 627system.l2c.overall_miss_rate::cpu0.data 0.301536 # miss rate for overall accesses 628system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for overall accesses 629system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses 630system.l2c.overall_miss_rate::cpu1.inst 0.129714 # miss rate for overall accesses 631system.l2c.overall_miss_rate::cpu1.data 0.333837 # miss rate for overall accesses 632system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for overall accesses 633system.l2c.overall_miss_rate::total 0.472592 # miss rate for overall accesses 634system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average ReadReq miss latency 635system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq miss latency 636system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83271.165569 # average ReadReq miss latency 637system.l2c.ReadReq_avg_miss_latency::cpu0.data 77277.999079 # average ReadReq miss latency 638system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average ReadReq miss latency 639system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average ReadReq miss latency 640system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87397.192029 # average ReadReq miss latency 641system.l2c.ReadReq_avg_miss_latency::cpu1.data 77746.915819 # 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average ReadExReq miss latency 653system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency 654system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency 655system.l2c.demand_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency 656system.l2c.demand_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency 657system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency 658system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency 659system.l2c.demand_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency 660system.l2c.demand_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency 661system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency 662system.l2c.demand_avg_miss_latency::total 101695.935118 # average overall miss latency 663system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency 664system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency 665system.l2c.overall_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency 666system.l2c.overall_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency 667system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency 668system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency 669system.l2c.overall_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency 670system.l2c.overall_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency 671system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency 672system.l2c.overall_avg_miss_latency::total 101695.935118 # average overall miss latency 673system.l2c.blocked_cycles::no_mshrs 369 # number of cycles access was blocked |
| 608system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 674system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 609system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked | 675system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked |
| 610system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 676system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 611system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 677system.l2c.avg_blocked_cycles::no_mshrs 36.900000 # average number of cycles each access was blocked |
| 612system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 613system.l2c.fast_writes 0 # number of fast writes performed 614system.l2c.cache_copies 0 # number of cache copies performed | 678system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 679system.l2c.fast_writes 0 # number of fast writes performed 680system.l2c.cache_copies 0 # number of cache copies performed |
| 615system.l2c.writebacks::writebacks 65464 # number of writebacks 616system.l2c.writebacks::total 65464 # number of writebacks 617system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 618system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits 619system.l2c.ReadReq_mshr_hits::cpu0.data 28 # number of ReadReq MSHR hits 620system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits 621system.l2c.ReadReq_mshr_hits::cpu1.data 12 # number of ReadReq MSHR hits 622system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits 623system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 624system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 625system.l2c.demand_mshr_hits::cpu0.data 28 # number of demand (read+write) MSHR hits 626system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 627system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits 628system.l2c.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits 629system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 630system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 631system.l2c.overall_mshr_hits::cpu0.data 28 # number of overall MSHR hits 632system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 633system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits 634system.l2c.overall_mshr_hits::total 60 # number of overall MSHR hits 635system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses 636system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 637system.l2c.ReadReq_mshr_misses::cpu0.inst 7221 # number of ReadReq MSHR misses 638system.l2c.ReadReq_mshr_misses::cpu0.data 9869 # number of ReadReq MSHR misses 639system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses 640system.l2c.ReadReq_mshr_misses::cpu1.inst 4704 # number of ReadReq MSHR misses 641system.l2c.ReadReq_mshr_misses::cpu1.data 2094 # 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number of SCUpgradeReq MSHR miss cycles 738system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 244772807 # number of ReadExReq MSHR miss cycles 739system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 316260047 # number of ReadExReq MSHR miss cycles 740system.l2c.ReadExReq_mshr_miss_latency::total 561032854 # number of ReadExReq MSHR miss cycles 741system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158750 # number of demand (read+write) MSHR miss cycles 742system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145000 # number of demand (read+write) MSHR miss cycles 743system.l2c.demand_mshr_miss_latency::cpu0.inst 75361749 # number of demand (read+write) MSHR miss cycles 744system.l2c.demand_mshr_miss_latency::cpu0.data 455874306 # number of demand (read+write) MSHR miss cycles 745system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of demand (read+write) MSHR miss cycles 746system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 645000 # number of demand (read+write) MSHR miss cycles 747system.l2c.demand_mshr_miss_latency::cpu1.inst 82874000 # number of demand (read+write) MSHR miss cycles 748system.l2c.demand_mshr_miss_latency::cpu1.data 617936045 # number of demand (read+write) MSHR miss cycles 749system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of demand (read+write) MSHR miss cycles 750system.l2c.demand_mshr_miss_latency::total 15652479510 # number of demand (read+write) MSHR miss cycles 751system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158750 # number of overall MSHR miss cycles 752system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145000 # number of overall MSHR miss cycles 753system.l2c.overall_mshr_miss_latency::cpu0.inst 75361749 # number of overall MSHR miss cycles 754system.l2c.overall_mshr_miss_latency::cpu0.data 455874306 # number of overall MSHR miss cycles 755system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of overall MSHR miss cycles 756system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 645000 # number of overall MSHR miss cycles 757system.l2c.overall_mshr_miss_latency::cpu1.inst 82874000 # number of overall MSHR miss cycles 758system.l2c.overall_mshr_miss_latency::cpu1.data 617936045 # number of overall MSHR miss cycles 759system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of overall MSHR miss cycles 760system.l2c.overall_mshr_miss_latency::total 15652479510 # number of overall MSHR miss cycles 761system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 178129250 # number of ReadReq MSHR uncacheable cycles 762system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343853503 # number of ReadReq MSHR uncacheable cycles 763system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3278250 # number of ReadReq MSHR uncacheable cycles 764system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154953535743 # number of ReadReq MSHR uncacheable cycles 765system.l2c.ReadReq_mshr_uncacheable_latency::total 167478796746 # number of ReadReq MSHR uncacheable cycles 766system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076363997 # number of WriteReq MSHR uncacheable cycles 767system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16025248776 # number of WriteReq MSHR uncacheable cycles 768system.l2c.WriteReq_mshr_uncacheable_latency::total 17101612773 # number of WriteReq MSHR uncacheable cycles 769system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles 770system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles 771system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles 772system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles 773system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles 774system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses 775system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses 776system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses 777system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses 778system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses 779system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses 780system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses 781system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses 782system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses 783system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses 784system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses 785system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses 786system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses 787system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses 788system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses 789system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses 790system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses 791system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses 792system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses 793system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses 794system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses 795system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses 796system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses 797system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses 798system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses 799system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses 800system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses 801system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses 802system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses 803system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses 804system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses 805system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses 806system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses 807system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses 808system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses 809system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses 810system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses 811system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses 812system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses 813system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency 814system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency 815system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency 816system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency 817system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency 818system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency 819system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency 820system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency 821system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency 822system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency 823system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency 824system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency 825system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency 826system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency 827system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency 828system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency 829system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency 830system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency 831system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency 832system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency 833system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency 834system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency 835system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency 836system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency 837system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency 838system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency 839system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency 840system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency 841system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency 842system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency 843system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency 844system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency 845system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency 846system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency 847system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency 848system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency 849system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency 850system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency 851system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency |
| 780system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 781system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 782system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 783system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 784system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 785system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 786system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 787system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 792system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 793system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 794system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 795system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 796system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 797system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 798system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 799system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 852system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 853system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 854system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 855system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 856system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 857system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 858system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 859system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 864system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 865system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 866system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 867system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 868system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 869system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 870system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 871system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 800system.toL2Bus.throughput 57560286 # Throughput (bytes/s) 801system.toL2Bus.trans_dist::ReadReq 2682607 # Transaction distribution 802system.toL2Bus.trans_dist::ReadResp 2682607 # Transaction distribution 803system.toL2Bus.trans_dist::WriteReq 768463 # Transaction distribution 804system.toL2Bus.trans_dist::WriteResp 768463 # Transaction distribution 805system.toL2Bus.trans_dist::Writeback 583269 # Transaction distribution 806system.toL2Bus.trans_dist::UpgradeReq 27558 # Transaction distribution 807system.toL2Bus.trans_dist::SCUpgradeReq 17275 # Transaction distribution 808system.toL2Bus.trans_dist::UpgradeResp 44833 # Transaction distribution 809system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 810system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution 811system.toL2Bus.trans_dist::ReadExReq 261997 # Transaction distribution 812system.toL2Bus.trans_dist::ReadExResp 261997 # Transaction distribution 813system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1115277 # Packet count per connected master and slave (bytes) 814system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2956767 # Packet count per connected master and slave (bytes) 815system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14518 # Packet count per connected master and slave (bytes) 816system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50368 # Packet count per connected master and slave (bytes) 817system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 879187 # Packet count per connected master and slave (bytes) 818system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2909426 # Packet count per connected master and slave (bytes) 819system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 12099 # Packet count per connected master and slave (bytes) 820system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 38611 # Packet count per connected master and slave (bytes) 821system.toL2Bus.pkt_count::total 7976253 # Packet count per connected master and slave (bytes) 822system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 35510400 # Cumulative packet size per connected master and slave (bytes) 823system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53724619 # Cumulative packet size per connected master and slave (bytes) 824system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21456 # Cumulative packet size per connected master and slave (bytes) 825system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83524 # Cumulative packet size per connected master and slave (bytes) 826system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 28114656 # Cumulative packet size per connected master and slave (bytes) 827system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 29015778 # Cumulative packet size per connected master and slave (bytes) 828system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 17296 # Cumulative packet size per connected master and slave (bytes) 829system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62840 # Cumulative packet size per connected master and slave (bytes) 830system.toL2Bus.tot_pkt_size::total 146550569 # Cumulative packet size per connected master and slave (bytes) 831system.toL2Bus.data_through_bus 146550569 # Total data (bytes) 832system.toL2Bus.snoop_data_through_bus 4352184 # Total snoop data (bytes) 833system.toL2Bus.reqLayer0.occupancy 4888594820 # Layer occupancy (ticks) 834system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 835system.toL2Bus.respLayer0.occupancy 2503079453 # Layer occupancy (ticks) 836system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 837system.toL2Bus.respLayer1.occupancy 2482730980 # Layer occupancy (ticks) | 872system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution 873system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution 874system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution 875system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution 876system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution 877system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution 878system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution 879system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution 880system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 881system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution 882system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution 883system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution 884system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes) 885system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes) 886system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes) 887system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes) 888system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes) 889system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes) 890system.toL2Bus.snoops 177868 # Total snoops (count) 891system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram 892system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 893system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 894system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 895system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 896system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram 897system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 898system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 899system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 900system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 901system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram 902system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks) 903system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 904system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks) 905system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 906system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks) |
| 838system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 907system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 839system.toL2Bus.respLayer2.occupancy 9171959 # Layer occupancy (ticks) 840system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 841system.toL2Bus.respLayer3.occupancy 29595779 # Layer occupancy (ticks) 842system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 843system.toL2Bus.respLayer6.occupancy 1980581418 # Layer occupancy (ticks) 844system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) 845system.toL2Bus.respLayer7.occupancy 2244583247 # Layer occupancy (ticks) 846system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) 847system.toL2Bus.respLayer8.occupancy 7797450 # Layer occupancy (ticks) 848system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 849system.toL2Bus.respLayer9.occupancy 22968355 # Layer occupancy (ticks) 850system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 851system.iobus.throughput 47108999 # Throughput (bytes/s) 852system.iobus.trans_dist::ReadReq 16322906 # Transaction distribution 853system.iobus.trans_dist::ReadResp 16322906 # Transaction distribution 854system.iobus.trans_dist::WriteReq 8083 # Transaction distribution 855system.iobus.trans_dist::WriteResp 8083 # Transaction distribution 856system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) 857system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8814 # Packet count per connected master and slave (bytes) | 908system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution 909system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution 910system.iobus.trans_dist::WriteReq 8084 # Transaction distribution 911system.iobus.trans_dist::WriteResp 8084 # Transaction distribution 912system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) 913system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes) |
| 858system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) | 914system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 859system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1034 # Packet count per connected master and slave (bytes) | 915system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) |
| 860system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 861system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 916system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 917system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 862system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) | 918system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes) |
| 863system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 864system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 865system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 866system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 867system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 868system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 869system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 871system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 872system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 873system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 874system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 875system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 876system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 877system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 878system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 919system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 920system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 921system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 922system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 923system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 924system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 925system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 926system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 927system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 928system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 929system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 930system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 931system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 932system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 933system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 934system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 879system.iobus.pkt_count_system.bridge.master::total 2384346 # Packet count per connected master and slave (bytes) | 935system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes) |
| 880system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 881system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) | 936system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 937system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) |
| 882system.iobus.pkt_count::total 32661978 # Packet count per connected master and slave (bytes) 883system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) 884system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17628 # Cumulative packet size per connected master and slave (bytes) 885system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 886system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2068 # Cumulative packet size per connected master and slave (bytes) 887system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 888system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 889system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) 890system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 891system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 892system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 893system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 894system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 895system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 898system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 900system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 901system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 905system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 906system.iobus.tot_pkt_size_system.bridge.master::total 2392641 # Cumulative packet size per connected master and slave (bytes) 907system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 908system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 909system.iobus.tot_pkt_size::total 123503169 # Cumulative packet size per connected master and slave (bytes) 910system.iobus.data_through_bus 123503169 # Total data (bytes) 911system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) | 938system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes) 939system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) 940system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes) 941system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 942system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 943system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 944system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 945system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes) 946system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 947system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 948system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 949system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 950system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 951system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 952system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 953system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 954system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 955system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 956system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 957system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 958system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 959system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 960system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 962system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) 963system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 964system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 965system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) 966system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) |
| 912system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 967system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 913system.iobus.reqLayer1.occupancy 4413000 # Layer occupancy (ticks) | 968system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks) |
| 914system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 915system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 916system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 969system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 970system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 971system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 917system.iobus.reqLayer3.occupancy 523000 # Layer occupancy (ticks) | 972system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) |
| 918system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 919system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 920system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 921system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 922system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) | 973system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 974system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 975system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 976system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 977system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 923system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) | 978system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks) |
| 924system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 925system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 926system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 927system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 928system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 929system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 930system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 931system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) --- 17 unchanged lines hidden (view full) --- 949system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 950system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 951system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 952system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 953system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 954system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 955system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 956system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 979system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 980system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 981system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 982system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 983system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 984system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 985system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 986system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) --- 17 unchanged lines hidden (view full) --- 1004system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1005system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1006system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1007system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1008system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1009system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1010system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1011system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 957system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 958system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 959system.iobus.respLayer0.occupancy 2376263000 # Layer occupancy (ticks) | 1012system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) 1013system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 1014system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks) |
| 960system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 1015system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 961system.iobus.respLayer1.occupancy 38168032303 # Layer occupancy (ticks) | 1016system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks) |
| 962system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) | 1017system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) |
| 963system.cpu0.branchPred.lookups 8682194 # Number of BP lookups 964system.cpu0.branchPred.condPredicted 6490987 # Number of conditional branches predicted 965system.cpu0.branchPred.condIncorrect 415813 # Number of conditional branches incorrect 966system.cpu0.branchPred.BTBLookups 5217710 # Number of BTB lookups 967system.cpu0.branchPred.BTBHits 4131218 # Number of BTB hits | 1018system.cpu0.branchPred.lookups 6445077 # Number of BP lookups 1019system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted 1020system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect 1021system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups 1022system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits |
| 968system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1023system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 969system.cpu0.branchPred.BTBHitPct 79.176842 # BTB Hit Percentage 970system.cpu0.branchPred.usedRAS 908190 # Number of times the RAS was used to get a target. 971system.cpu0.branchPred.RASInCorrect 19748 # Number of incorrect RAS predictions. | 1024system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage 1025system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target. 1026system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions. |
| 972system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 973system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 974system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 975system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 976system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 977system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 978system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 979system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 987system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 988system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 989system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 990system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 991system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 992system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 993system.cpu0.dtb.inst_hits 0 # ITB inst hits 994system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1027system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1028system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1029system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1030system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1031system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1032system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1033system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1034system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1042system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1043system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1044system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1045system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1046system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1047system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1048system.cpu0.dtb.inst_hits 0 # ITB inst hits 1049system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 995system.cpu0.dtb.read_hits 10917771 # DTB read hits 996system.cpu0.dtb.read_misses 23643 # DTB read misses 997system.cpu0.dtb.write_hits 7767808 # DTB write hits 998system.cpu0.dtb.write_misses 8146 # DTB write misses | 1050system.cpu0.dtb.read_hits 6738270 # DTB read hits 1051system.cpu0.dtb.read_misses 20792 # DTB read misses 1052system.cpu0.dtb.write_hits 5108254 # DTB write hits 1053system.cpu0.dtb.write_misses 4938 # DTB write misses |
| 999system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1000system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1001system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1002system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1054system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1055system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1056system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1057system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1003system.cpu0.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB 1004system.cpu0.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions 1005system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch | 1058system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB 1059system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions 1060system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch |
| 1006system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1061system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1007system.cpu0.dtb.perms_faults 598 # Number of TLB faults due to permissions restrictions 1008system.cpu0.dtb.read_accesses 10941414 # DTB read accesses 1009system.cpu0.dtb.write_accesses 7775954 # DTB write accesses | 1062system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions 1063system.cpu0.dtb.read_accesses 6759062 # DTB read accesses 1064system.cpu0.dtb.write_accesses 5113192 # DTB write accesses |
| 1010system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1065system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1011system.cpu0.dtb.hits 18685579 # DTB hits 1012system.cpu0.dtb.misses 31789 # DTB misses 1013system.cpu0.dtb.accesses 18717368 # DTB accesses | 1066system.cpu0.dtb.hits 11846524 # DTB hits 1067system.cpu0.dtb.misses 25730 # DTB misses 1068system.cpu0.dtb.accesses 11872254 # DTB accesses |
| 1014system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1015system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1016system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1017system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1018system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1019system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1020system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1021system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1027system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1028system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1029system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1030system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1031system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1032system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1033system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1034system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1069system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1070system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1071system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1072system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1073system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1074system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1075system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1076system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1082system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1083system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1084system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1085system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1086system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1087system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1088system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1089system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1035system.cpu0.itb.inst_hits 16449037 # ITB inst hits 1036system.cpu0.itb.inst_misses 5743 # ITB inst misses | 1090system.cpu0.itb.inst_hits 11251934 # ITB inst hits 1091system.cpu0.itb.inst_misses 5844 # ITB inst misses |
| 1037system.cpu0.itb.read_hits 0 # DTB read hits 1038system.cpu0.itb.read_misses 0 # DTB read misses 1039system.cpu0.itb.write_hits 0 # DTB write hits 1040system.cpu0.itb.write_misses 0 # DTB write misses 1041system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1042system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1043system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1044system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1092system.cpu0.itb.read_hits 0 # DTB read hits 1093system.cpu0.itb.read_misses 0 # DTB read misses 1094system.cpu0.itb.write_hits 0 # DTB write hits 1095system.cpu0.itb.write_misses 0 # DTB write misses 1096system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1097system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1098system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1099system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1045system.cpu0.itb.flush_entries 1206 # Number of entries that have been flushed from TLB | 1100system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB |
| 1046system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1047system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1048system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1101system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1102system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1103system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1049system.cpu0.itb.perms_faults 2114 # Number of TLB faults due to permissions restrictions | 1104system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions |
| 1050system.cpu0.itb.read_accesses 0 # DTB read accesses 1051system.cpu0.itb.write_accesses 0 # DTB write accesses | 1105system.cpu0.itb.read_accesses 0 # DTB read accesses 1106system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1052system.cpu0.itb.inst_accesses 16454780 # ITB inst accesses 1053system.cpu0.itb.hits 16449037 # DTB hits 1054system.cpu0.itb.misses 5743 # DTB misses 1055system.cpu0.itb.accesses 16454780 # DTB accesses 1056system.cpu0.numCycles 110984158 # number of cpu cycles simulated | 1107system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses 1108system.cpu0.itb.hits 11251934 # DTB hits 1109system.cpu0.itb.misses 5844 # DTB misses 1110system.cpu0.itb.accesses 11257778 # DTB accesses 1111system.cpu0.numCycles 70547986 # number of cpu cycles simulated |
| 1057system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1058system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1112system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1113system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1059system.cpu0.fetch.icacheStallCycles 29010417 # Number of cycles fetch is stalled on an Icache miss 1060system.cpu0.fetch.Insts 51007104 # Number of instructions fetch has processed 1061system.cpu0.fetch.Branches 8682194 # Number of branches that fetch encountered 1062system.cpu0.fetch.predictedBranches 5039408 # Number of branches that fetch has predicted taken 1063system.cpu0.fetch.Cycles 76702951 # Number of cycles fetch has run and was not squashing or blocked 1064system.cpu0.fetch.SquashCycles 1090474 # Number of cycles fetch has spent squashing 1065system.cpu0.fetch.TlbCycles 80643 # Number of cycles fetch has spent waiting for tlb 1066system.cpu0.fetch.MiscStallCycles 23949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1067system.cpu0.fetch.PendingTrapStallCycles 71996 # Number of stall cycles due to pending traps 1068system.cpu0.fetch.PendingQuiesceStallCycles 1961272 # Number of stall cycles due to pending quiesce instructions 1069system.cpu0.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR 1070system.cpu0.fetch.CacheLines 16450117 # Number of cache lines fetched 1071system.cpu0.fetch.IcacheSquashes 242573 # Number of outstanding Icache misses that were squashed 1072system.cpu0.fetch.ItlbSquashes 2510 # Number of outstanding ITLB misses that were squashed 1073system.cpu0.fetch.rateDist::samples 108396478 # Number of instructions fetched each cycle (Total) 1074system.cpu0.fetch.rateDist::mean 0.561251 # Number of instructions fetched each cycle (Total) 1075system.cpu0.fetch.rateDist::stdev 1.057421 # Number of instructions fetched each cycle (Total) | 1114system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss 1115system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed 1116system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered 1117system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken 1118system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked 1119system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing 1120system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb 1121system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1122system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps 1123system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions 1124system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR 1125system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched 1126system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed 1127system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed 1128system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total) 1129system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total) 1130system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total) |
| 1076system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1131system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1077system.cpu0.fetch.rateDist::0 80471532 74.24% 74.24% # Number of instructions fetched each cycle (Total) 1078system.cpu0.fetch.rateDist::1 9354408 8.63% 82.87% # Number of instructions fetched each cycle (Total) 1079system.cpu0.fetch.rateDist::2 4228353 3.90% 86.77% # Number of instructions fetched each cycle (Total) 1080system.cpu0.fetch.rateDist::3 14342185 13.23% 100.00% # Number of instructions fetched each cycle (Total) | 1132system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total) 1133system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total) 1134system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total) 1135system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total) |
| 1081system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1082system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1083system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1136system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1137system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1138system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1084system.cpu0.fetch.rateDist::total 108396478 # Number of instructions fetched each cycle (Total) 1085system.cpu0.fetch.branchRate 0.078229 # Number of branch fetches per cycle 1086system.cpu0.fetch.rate 0.459589 # Number of inst fetches per cycle 1087system.cpu0.decode.IdleCycles 24273364 # Number of cycles decode is idle 1088system.cpu0.decode.BlockedCycles 59696324 # Number of cycles decode is blocked 1089system.cpu0.decode.RunCycles 21865637 # Number of cycles decode is running 1090system.cpu0.decode.UnblockCycles 2148424 # Number of cycles decode is unblocking 1091system.cpu0.decode.SquashCycles 412729 # Number of cycles decode is squashing 1092system.cpu0.decode.BranchResolved 1100967 # Number of times decode resolved a branch 1093system.cpu0.decode.BranchMispred 134603 # Number of times decode detected a branch misprediction 1094system.cpu0.decode.DecodedInsts 56048449 # Number of instructions handled by decode 1095system.cpu0.decode.SquashedInsts 1161275 # Number of squashed instructions handled by decode 1096system.cpu0.rename.SquashCycles 412729 # Number of cycles rename is squashing 1097system.cpu0.rename.IdleCycles 26181144 # Number of cycles rename is idle 1098system.cpu0.rename.BlockCycles 23163659 # Number of cycles rename is blocking 1099system.cpu0.rename.serializeStallCycles 11818847 # count of cycles rename stalled for serializing inst 1100system.cpu0.rename.RunCycles 22001270 # Number of cycles rename is running 1101system.cpu0.rename.UnblockCycles 24818829 # Number of cycles rename is unblocking 1102system.cpu0.rename.RenamedInsts 54863842 # Number of instructions processed by rename 1103system.cpu0.rename.SquashedInsts 371818 # Number of squashed instructions processed by rename 1104system.cpu0.rename.ROBFullEvents 4330145 # Number of times rename has blocked due to ROB full 1105system.cpu0.rename.IQFullEvents 2622839 # Number of times rename has blocked due to IQ full 1106system.cpu0.rename.LQFullEvents 9842391 # Number of times rename has blocked due to LQ full 1107system.cpu0.rename.SQFullEvents 13156385 # Number of times rename has blocked due to SQ full 1108system.cpu0.rename.RenamedOperands 58083982 # Number of destination operands rename has renamed 1109system.cpu0.rename.RenameLookups 254404471 # Number of register rename lookups that rename has made 1110system.cpu0.rename.int_rename_lookups 69151408 # Number of integer rename lookups 1111system.cpu0.rename.fp_rename_lookups 3820 # Number of floating rename lookups 1112system.cpu0.rename.CommittedMaps 54276662 # Number of HB maps that are committed 1113system.cpu0.rename.UndoneMaps 3807314 # Number of HB maps that are undone due to squashing 1114system.cpu0.rename.serializingInsts 540800 # count of serializing insts renamed 1115system.cpu0.rename.tempSerializingInsts 442723 # count of temporary serializing insts renamed 1116system.cpu0.rename.skidInsts 4591136 # count of insts added to the skid buffer 1117system.cpu0.memDep0.insertedLoads 9492850 # Number of loads inserted to the mem dependence unit. 1118system.cpu0.memDep0.insertedStores 8297955 # Number of stores inserted to the mem dependence unit. 1119system.cpu0.memDep0.conflictingLoads 506397 # Number of conflicting loads. 1120system.cpu0.memDep0.conflictingStores 589876 # Number of conflicting stores. 1121system.cpu0.iq.iqInstsAdded 53569882 # Number of instructions added to the IQ (excludes non-spec) 1122system.cpu0.iq.iqNonSpecInstsAdded 859573 # Number of non-speculative instructions added to the IQ 1123system.cpu0.iq.iqInstsIssued 55433156 # Number of instructions issued 1124system.cpu0.iq.iqSquashedInstsIssued 105167 # Number of squashed instructions issued 1125system.cpu0.iq.iqSquashedInstsExamined 2762956 # Number of squashed instructions iterated over during squash; mainly for profiling 1126system.cpu0.iq.iqSquashedOperandsExamined 5503873 # Number of squashed operands that are examined and possibly removed from graph 1127system.cpu0.iq.iqSquashedNonSpecRemoved 84823 # Number of squashed non-spec instructions that were removed 1128system.cpu0.iq.issued_per_cycle::samples 108396478 # Number of insts issued each cycle 1129system.cpu0.iq.issued_per_cycle::mean 0.511393 # Number of insts issued each cycle 1130system.cpu0.iq.issued_per_cycle::stdev 0.864824 # Number of insts issued each cycle | 1139system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total) 1140system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle 1141system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle 1142system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle 1143system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked 1144system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running 1145system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking 1146system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing 1147system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch 1148system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction 1149system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode 1150system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode 1151system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing 1152system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle 1153system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking 1154system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst 1155system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running 1156system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking 1157system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename 1158system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename 1159system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full 1160system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full 1161system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full 1162system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full 1163system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed 1164system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made 1165system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups 1166system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups 1167system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed 1168system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing 1169system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed 1170system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed 1171system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer 1172system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit. 1173system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit. 1174system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads. 1175system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores. 1176system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec) 1177system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ 1178system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued 1179system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued 1180system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling 1181system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph 1182system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed 1183system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle 1184system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle 1185system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle |
| 1131system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1186system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1132system.cpu0.iq.issued_per_cycle::0 74367725 68.61% 68.61% # Number of insts issued each cycle 1133system.cpu0.iq.issued_per_cycle::1 17769290 16.39% 85.00% # Number of insts issued each cycle 1134system.cpu0.iq.issued_per_cycle::2 11558620 10.66% 95.66% # Number of insts issued each cycle 1135system.cpu0.iq.issued_per_cycle::3 4256755 3.93% 99.59% # Number of insts issued each cycle 1136system.cpu0.iq.issued_per_cycle::4 444079 0.41% 100.00% # Number of insts issued each cycle 1137system.cpu0.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle | 1187system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle 1188system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle 1189system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle 1190system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle 1191system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle 1192system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle |
| 1138system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1139system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1140system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1141system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1142system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1143system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1193system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1194system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1195system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1196system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1197system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1198system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1144system.cpu0.iq.issued_per_cycle::total 108396478 # Number of insts issued each cycle | 1199system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle |
| 1145system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1200system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1146system.cpu0.iq.fu_full::IntAlu 3788078 33.87% 33.87% # attempts to use FU when none available 1147system.cpu0.iq.fu_full::IntMult 172 0.00% 33.87% # attempts to use FU when none available 1148system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.87% # attempts to use FU when none available 1149system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available 1150system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available 1151system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available 1152system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available 1153system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available 1154system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available 1155system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available 1156system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available 1157system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available 1158system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available 1159system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available 1160system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available 1161system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available 1162system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available 1163system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available 1164system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available 1165system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available 1166system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available 1167system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available 1168system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available 1169system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available 1170system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available 1171system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available 1172system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available 1173system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available 1174system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available 1175system.cpu0.iq.fu_full::MemRead 3595287 32.14% 66.01% # attempts to use FU when none available 1176system.cpu0.iq.fu_full::MemWrite 3801407 33.99% 100.00% # attempts to use FU when none available | 1201system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available 1202system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available 1203system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available 1204system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available 1205system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available 1206system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available 1207system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available 1208system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available 1209system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available 1210system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available 1211system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available 1212system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available 1213system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available 1214system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available 1215system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available 1216system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available 1217system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available 1218system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available 1219system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available 1220system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available 1221system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available 1222system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available 1223system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available 1224system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available 1225system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available 1226system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available 1227system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available 1228system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available 1229system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available 1230system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available 1231system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available |
| 1177system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1178system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1232system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1233system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1179system.cpu0.iq.FU_type_0::No_OpClass 14948 0.03% 0.03% # Type of FU issued 1180system.cpu0.iq.FU_type_0::IntAlu 35826739 64.63% 64.66% # Type of FU issued 1181system.cpu0.iq.FU_type_0::IntMult 64782 0.12% 64.77% # Type of FU issued 1182system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 64.77% # Type of FU issued 1183system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 64.77% # Type of FU issued 1184system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 64.77% # Type of FU issued 1185system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 64.77% # Type of FU issued 1186system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 64.77% # Type of FU issued 1187system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 64.77% # Type of FU issued 1188system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 64.77% # Type of FU issued 1189system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 64.77% # Type of FU issued 1190system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 64.77% # Type of FU issued 1191system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 64.77% # Type of FU issued 1192system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 64.77% # Type of FU issued 1193system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 64.77% # Type of FU issued 1194system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 64.77% # Type of FU issued 1195system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 64.77% # Type of FU issued 1196system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 64.77% # Type of FU issued 1197system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 64.77% # Type of FU issued 1198system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.77% # Type of FU issued 1199system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 64.77% # Type of FU issued 1200system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.77% # Type of FU issued 1201system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.77% # Type of FU issued 1202system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.77% # Type of FU issued 1203system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.77% # Type of FU issued 1204system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.77% # Type of FU issued 1205system.cpu0.iq.FU_type_0::SimdFloatMisc 722 0.00% 64.78% # Type of FU issued 1206system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 64.78% # Type of FU issued 1207system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.78% # Type of FU issued 1208system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.78% # Type of FU issued 1209system.cpu0.iq.FU_type_0::MemRead 11302035 20.39% 85.16% # Type of FU issued 1210system.cpu0.iq.FU_type_0::MemWrite 8223930 14.84% 100.00% # Type of FU issued | 1234system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued 1235system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued 1236system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued 1237system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued 1238system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued 1239system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued 1240system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued 1241system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued 1242system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued 1243system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued 1244system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued 1245system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued 1246system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued 1247system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued 1248system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued 1249system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued 1250system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued 1251system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued 1252system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued 1253system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued 1254system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued 1255system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued 1256system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued 1257system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued 1258system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued 1259system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued 1260system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued 1261system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued 1262system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued 1263system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued 1264system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued 1265system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued |
| 1211system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1212system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1266system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1267system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1213system.cpu0.iq.FU_type_0::total 55433156 # Type of FU issued 1214system.cpu0.iq.rate 0.499469 # Inst issue rate 1215system.cpu0.iq.fu_busy_cnt 11184944 # FU busy when requested 1216system.cpu0.iq.fu_busy_rate 0.201774 # FU busy rate (busy events/executed inst) 1217system.cpu0.iq.int_inst_queue_reads 230540772 # Number of integer instruction queue reads 1218system.cpu0.iq.int_inst_queue_writes 57191232 # Number of integer instruction queue writes 1219system.cpu0.iq.int_inst_queue_wakeup_accesses 52885161 # Number of integer instruction queue wakeup accesses 1220system.cpu0.iq.fp_inst_queue_reads 12129 # Number of floating instruction queue reads 1221system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes | 1268system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued 1269system.cpu0.iq.rate 0.464855 # Inst issue rate 1270system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested 1271system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst) 1272system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads 1273system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes 1274system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses 1275system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads 1276system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes |
| 1222system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses | 1277system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses |
| 1223system.cpu0.iq.int_alu_accesses 66595213 # Number of integer alu accesses 1224system.cpu0.iq.fp_alu_accesses 7939 # Number of floating point alu accesses 1225system.cpu0.iew.lsq.thread0.forwLoads 146965 # Number of loads that had data forwarded from stores | 1278system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses 1279system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses 1280system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores |
| 1226system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1281system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1227system.cpu0.iew.lsq.thread0.squashedLoads 634189 # Number of loads squashed 1228system.cpu0.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed 1229system.cpu0.iew.lsq.thread0.memOrderViolation 3442 # Number of memory ordering violations 1230system.cpu0.iew.lsq.thread0.squashedStores 242149 # Number of stores squashed | 1282system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed 1283system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed 1284system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations 1285system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed |
| 1231system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1232system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1286system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1287system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1233system.cpu0.iew.lsq.thread0.rescheduledLoads 1082260 # Number of loads that were rescheduled 1234system.cpu0.iew.lsq.thread0.cacheBlocked 1003693 # Number of times an access to memory failed due to the cache being blocked | 1288system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled 1289system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked |
| 1235system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1290system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1236system.cpu0.iew.iewSquashCycles 412729 # Number of cycles IEW is squashing 1237system.cpu0.iew.iewBlockCycles 7302695 # Number of cycles IEW is blocking 1238system.cpu0.iew.iewUnblockCycles 6441595 # Number of cycles IEW is unblocking 1239system.cpu0.iew.iewDispatchedInsts 54523303 # Number of instructions dispatched to IQ | 1291system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing 1292system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking 1293system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking 1294system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ |
| 1240system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 1295system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 1241system.cpu0.iew.iewDispLoadInsts 9492850 # Number of dispatched load instructions 1242system.cpu0.iew.iewDispStoreInsts 8297955 # Number of dispatched store instructions 1243system.cpu0.iew.iewDispNonSpecInsts 524870 # Number of dispatched non-speculative instructions 1244system.cpu0.iew.iewIQFullEvents 12318 # Number of times the IQ has become full, causing a stall 1245system.cpu0.iew.iewLSQFullEvents 6420937 # Number of times the LSQ has become full, causing a stall 1246system.cpu0.iew.memOrderViolationEvents 3442 # Number of memory order violations 1247system.cpu0.iew.predictedTakenIncorrect 134210 # Number of branches that were predicted taken incorrectly 1248system.cpu0.iew.predictedNotTakenIncorrect 165432 # Number of branches that were predicted not taken incorrectly 1249system.cpu0.iew.branchMispredicts 299642 # Number of branch mispredicts detected at execute 1250system.cpu0.iew.iewExecutedInsts 55026621 # Number of executed instructions 1251system.cpu0.iew.iewExecLoadInsts 11133456 # Number of load instructions executed 1252system.cpu0.iew.iewExecSquashedInsts 374843 # Number of squashed instructions skipped in execute | 1296system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions 1297system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions 1298system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions 1299system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall 1300system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall 1301system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations 1302system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly 1303system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly 1304system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute 1305system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions 1306system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed 1307system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute |
| 1253system.cpu0.iew.exec_swp 0 # number of swp insts executed | 1308system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 1254system.cpu0.iew.exec_nop 93848 # number of nop insts executed 1255system.cpu0.iew.exec_refs 19301977 # number of memory reference insts executed 1256system.cpu0.iew.exec_branches 7332190 # Number of branches executed 1257system.cpu0.iew.exec_stores 8168521 # Number of stores executed 1258system.cpu0.iew.exec_rate 0.495806 # Inst execution rate 1259system.cpu0.iew.wb_sent 54039254 # cumulative count of insts sent to commit 1260system.cpu0.iew.wb_count 52888999 # cumulative count of insts written-back 1261system.cpu0.iew.wb_producers 25110485 # num instructions producing a value 1262system.cpu0.iew.wb_consumers 37735585 # num instructions consuming a value | 1309system.cpu0.iew.exec_nop 102446 # number of nop insts executed 1310system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed 1311system.cpu0.iew.exec_branches 4700114 # Number of branches executed 1312system.cpu0.iew.exec_stores 5379801 # Number of stores executed 1313system.cpu0.iew.exec_rate 0.459648 # Inst execution rate 1314system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit 1315system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back 1316system.cpu0.iew.wb_producers 15739944 # num instructions producing a value 1317system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value |
| 1263system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1318system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1264system.cpu0.iew.wb_rate 0.476545 # insts written-back per cycle 1265system.cpu0.iew.wb_fanout 0.665433 # average fanout of values written-back | 1319system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle 1320system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back |
| 1266system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1321system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1267system.cpu0.commit.commitSquashedInsts 2480238 # The number of squashed insts skipped by commit 1268system.cpu0.commit.commitNonSpecStalls 774750 # The number of times commit has been forced to stall to communicate backwards 1269system.cpu0.commit.branchMispredicts 283305 # The number of times a branch was mispredicted 1270system.cpu0.commit.committed_per_cycle::samples 107840192 # Number of insts commited each cycle 1271system.cpu0.commit.committed_per_cycle::mean 0.477624 # Number of insts commited each cycle 1272system.cpu0.commit.committed_per_cycle::stdev 1.224539 # Number of insts commited each cycle | 1322system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit 1323system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards 1324system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted 1325system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle 1326system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle 1327system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle |
| 1273system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1328system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1274system.cpu0.commit.committed_per_cycle::0 82912194 76.88% 76.88% # Number of insts commited each cycle 1275system.cpu0.commit.committed_per_cycle::1 14339479 13.30% 90.18% # Number of insts commited each cycle 1276system.cpu0.commit.committed_per_cycle::2 5152045 4.78% 94.96% # Number of insts commited each cycle 1277system.cpu0.commit.committed_per_cycle::3 1572745 1.46% 96.42% # Number of insts commited each cycle 1278system.cpu0.commit.committed_per_cycle::4 1370622 1.27% 97.69% # Number of insts commited each cycle 1279system.cpu0.commit.committed_per_cycle::5 690625 0.64% 98.33% # Number of insts commited each cycle 1280system.cpu0.commit.committed_per_cycle::6 401555 0.37% 98.70% # Number of insts commited each cycle 1281system.cpu0.commit.committed_per_cycle::7 407085 0.38% 99.08% # Number of insts commited each cycle 1282system.cpu0.commit.committed_per_cycle::8 993842 0.92% 100.00% # Number of insts commited each cycle | 1329system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle 1330system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle 1331system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle 1332system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle 1333system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle 1334system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle 1335system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle 1336system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle 1337system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle |
| 1283system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1284system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1285system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1338system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1339system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1340system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1286system.cpu0.commit.committed_per_cycle::total 107840192 # Number of insts commited each cycle 1287system.cpu0.commit.committedInsts 43173906 # Number of instructions committed 1288system.cpu0.commit.committedOps 51507078 # Number of ops (including micro ops) committed | 1341system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle 1342system.cpu0.commit.committedInsts 24068410 # Number of instructions committed 1343system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed |
| 1289system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 1344system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 1290system.cpu0.commit.refs 16914467 # Number of memory references committed 1291system.cpu0.commit.loads 8858661 # Number of loads committed 1292system.cpu0.commit.membars 263890 # Number of memory barriers committed 1293system.cpu0.commit.branches 7043091 # Number of branches committed | 1345system.cpu0.commit.refs 10570507 # Number of memory references committed 1346system.cpu0.commit.loads 5342633 # Number of loads committed 1347system.cpu0.commit.membars 231974 # Number of memory barriers committed 1348system.cpu0.commit.branches 4351471 # Number of branches committed |
| 1294system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. | 1349system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. |
| 1295system.cpu0.commit.int_insts 45505753 # Number of committed integer instructions. 1296system.cpu0.commit.function_calls 666034 # Number of function calls committed. | 1350system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions. 1351system.cpu0.commit.function_calls 499778 # Number of function calls committed. |
| 1297system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 1352system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 1298system.cpu0.commit.op_class_0::IntAlu 34530023 67.04% 67.04% # Class of committed instruction 1299system.cpu0.commit.op_class_0::IntMult 61866 0.12% 67.16% # Class of committed instruction 1300system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.16% # Class of committed instruction 1301system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.16% # Class of committed instruction 1302system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.16% # Class of committed instruction 1303system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.16% # Class of committed instruction 1304system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.16% # Class of committed instruction 1305system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.16% # Class of committed instruction 1306system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.16% # Class of committed instruction 1307system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.16% # Class of committed instruction 1308system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.16% # Class of committed instruction 1309system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.16% # Class of committed instruction 1310system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.16% # Class of committed instruction 1311system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.16% # Class of committed instruction 1312system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.16% # Class of committed instruction 1313system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.16% # Class of committed instruction 1314system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.16% # Class of committed instruction 1315system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.16% # Class of committed instruction 1316system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.16% # Class of committed instruction 1317system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.16% # Class of committed instruction 1318system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.16% # Class of committed instruction 1319system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.16% # Class of committed instruction 1320system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.16% # Class of committed instruction 1321system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.16% # Class of committed instruction 1322system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.16% # Class of committed instruction 1323system.cpu0.commit.op_class_0::SimdFloatMisc 722 0.00% 67.16% # Class of committed instruction 1324system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.16% # Class of committed instruction 1325system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.16% # Class of committed instruction 1326system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.16% # Class of committed instruction 1327system.cpu0.commit.op_class_0::MemRead 8858661 17.20% 84.36% # Class of committed instruction 1328system.cpu0.commit.op_class_0::MemWrite 8055806 15.64% 100.00% # Class of committed instruction | 1353system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction 1354system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction 1355system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction 1356system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction 1357system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction 1358system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction 1359system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction 1360system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction 1361system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction 1362system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction 1363system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction 1364system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction 1365system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction 1366system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction 1367system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction 1368system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction 1369system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction 1370system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction 1371system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction 1372system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction 1373system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction 1374system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction 1375system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction 1376system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction 1377system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction 1378system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction 1379system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction 1380system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction 1381system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction 1382system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction 1383system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction |
| 1329system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1330system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1384system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1385system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1331system.cpu0.commit.op_class_0::total 51507078 # Class of committed instruction 1332system.cpu0.commit.bw_lim_events 993842 # number cycles where commit BW limit reached | 1386system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction 1387system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached |
| 1333system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 1388system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1334system.cpu0.rob.rob_reads 159811836 # The number of ROB reads 1335system.cpu0.rob.rob_writes 108530018 # The number of ROB writes 1336system.cpu0.timesIdled 338876 # Number of times that the entire CPU went into an idle state and unscheduled itself 1337system.cpu0.idleCycles 2587680 # Total number of cycles that the CPU has spent unscheduled due to idling 1338system.cpu0.quiesceCycles 5132257518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1339system.cpu0.committedInsts 43093164 # Number of Instructions Simulated 1340system.cpu0.committedOps 51426336 # Number of Ops (including micro ops) Simulated 1341system.cpu0.cpi 2.575447 # CPI: Cycles Per Instruction 1342system.cpu0.cpi_total 2.575447 # CPI: Total CPI of All Threads 1343system.cpu0.ipc 0.388282 # IPC: Instructions Per Cycle 1344system.cpu0.ipc_total 0.388282 # IPC: Total IPC of All Threads 1345system.cpu0.int_regfile_reads 67127966 # number of integer regfile reads 1346system.cpu0.int_regfile_writes 33211893 # number of integer regfile writes 1347system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads | 1389system.cpu0.rob.rob_reads 99997744 # The number of ROB reads 1390system.cpu0.rob.rob_writes 65895627 # The number of ROB writes 1391system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself 1392system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling 1393system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1394system.cpu0.committedInsts 23987668 # Number of Instructions Simulated 1395system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated 1396system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction 1397system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads 1398system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle 1399system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads 1400system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads 1401system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes 1402system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads |
| 1348system.cpu0.fp_regfile_writes 840 # number of floating regfile writes | 1403system.cpu0.fp_regfile_writes 840 # number of floating regfile writes |
| 1349system.cpu0.cc_regfile_reads 191848471 # number of cc regfile reads 1350system.cpu0.cc_regfile_writes 22040987 # number of cc regfile writes 1351system.cpu0.misc_regfile_reads 169210728 # number of misc regfile reads 1352system.cpu0.misc_regfile_writes 593502 # number of misc regfile writes 1353system.cpu0.icache.tags.replacements 554010 # number of replacements 1354system.cpu0.icache.tags.tagsinuse 511.387606 # Cycle average of tags in use 1355system.cpu0.icache.tags.total_refs 15866984 # Total number of references to valid blocks. 1356system.cpu0.icache.tags.sampled_refs 554522 # Sample count of references to valid blocks. 1357system.cpu0.icache.tags.avg_refs 28.613804 # Average number of references to valid blocks. 1358system.cpu0.icache.tags.warmup_cycle 18806389250 # Cycle when the warmup percentage was hit. 1359system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.387606 # Average occupied blocks per requestor 1360system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998804 # Average percentage of cache occupancy 1361system.cpu0.icache.tags.occ_percent::total 0.998804 # Average percentage of cache occupancy | 1404system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads 1405system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes 1406system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads 1407system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes 1408system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution 1409system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution 1410system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution 1411system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution 1412system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution 1413system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution 1414system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution 1415system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution 1416system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution 1417system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution 1418system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution 1419system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution 1420system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution 1421system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes) 1422system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes) 1423system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes) 1424system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes) 1425system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes) 1426system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes) 1427system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes) 1428system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes) 1429system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes) 1430system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes) 1431system.cpu0.toL2Bus.snoops 640729 # Total snoops (count) 1432system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram 1433system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram 1434system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram 1435system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1436system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1437system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1438system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1439system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1440system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1441system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram 1442system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram 1443system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1444system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1445system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1446system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram 1447system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks) 1448system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1449system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks) 1450system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1451system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks) 1452system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1453system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks) 1454system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1455system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks) 1456system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1457system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks) 1458system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1459system.cpu0.icache.tags.replacements 322116 # number of replacements 1460system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use 1461system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks. 1462system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks. 1463system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks. 1464system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit. 1465system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor 1466system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy 1467system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy |
| 1362system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1468system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1363system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 1364system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id 1365system.cpu0.icache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id 1366system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id | 1469system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 1470system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 1471system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 1472system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id |
| 1367system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1473system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1368system.cpu0.icache.tags.tag_accesses 17001271 # Number of tag accesses 1369system.cpu0.icache.tags.data_accesses 17001271 # Number of data accesses 1370system.cpu0.icache.ReadReq_hits::cpu0.inst 15866984 # number of ReadReq hits 1371system.cpu0.icache.ReadReq_hits::total 15866984 # number of ReadReq hits 1372system.cpu0.icache.demand_hits::cpu0.inst 15866984 # number of demand (read+write) hits 1373system.cpu0.icache.demand_hits::total 15866984 # number of demand (read+write) hits 1374system.cpu0.icache.overall_hits::cpu0.inst 15866984 # number of overall hits 1375system.cpu0.icache.overall_hits::total 15866984 # number of overall hits 1376system.cpu0.icache.ReadReq_misses::cpu0.inst 579761 # number of ReadReq misses 1377system.cpu0.icache.ReadReq_misses::total 579761 # number of ReadReq misses 1378system.cpu0.icache.demand_misses::cpu0.inst 579761 # number of demand (read+write) misses 1379system.cpu0.icache.demand_misses::total 579761 # number of demand (read+write) misses 1380system.cpu0.icache.overall_misses::cpu0.inst 579761 # number of overall misses 1381system.cpu0.icache.overall_misses::total 579761 # number of overall misses 1382system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8029558142 # number of ReadReq miss cycles 1383system.cpu0.icache.ReadReq_miss_latency::total 8029558142 # number of ReadReq miss cycles 1384system.cpu0.icache.demand_miss_latency::cpu0.inst 8029558142 # number of demand (read+write) miss cycles 1385system.cpu0.icache.demand_miss_latency::total 8029558142 # number of demand (read+write) miss cycles 1386system.cpu0.icache.overall_miss_latency::cpu0.inst 8029558142 # number of overall miss cycles 1387system.cpu0.icache.overall_miss_latency::total 8029558142 # number of overall miss cycles 1388system.cpu0.icache.ReadReq_accesses::cpu0.inst 16446745 # number of ReadReq accesses(hits+misses) 1389system.cpu0.icache.ReadReq_accesses::total 16446745 # number of ReadReq accesses(hits+misses) 1390system.cpu0.icache.demand_accesses::cpu0.inst 16446745 # number of demand (read+write) accesses 1391system.cpu0.icache.demand_accesses::total 16446745 # number of demand (read+write) accesses 1392system.cpu0.icache.overall_accesses::cpu0.inst 16446745 # number of overall (read+write) accesses 1393system.cpu0.icache.overall_accesses::total 16446745 # number of overall (read+write) accesses 1394system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035251 # miss rate for ReadReq accesses 1395system.cpu0.icache.ReadReq_miss_rate::total 0.035251 # miss rate for ReadReq accesses 1396system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035251 # miss rate for demand accesses 1397system.cpu0.icache.demand_miss_rate::total 0.035251 # miss rate for demand accesses 1398system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035251 # miss rate for overall accesses 1399system.cpu0.icache.overall_miss_rate::total 0.035251 # miss rate for overall accesses 1400system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13849.772824 # average ReadReq miss latency 1401system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824 # average ReadReq miss latency 1402system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency 1403system.cpu0.icache.demand_avg_miss_latency::total 13849.772824 # average overall miss latency 1404system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency 1405system.cpu0.icache.overall_avg_miss_latency::total 13849.772824 # average overall miss latency 1406system.cpu0.icache.blocked_cycles::no_mshrs 739 # number of cycles access was blocked 1407system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1408system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked 1409system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1410system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.436364 # average number of cycles each access was blocked 1411system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1474system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses 1475system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses 1476system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits 1477system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits 1478system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits 1479system.cpu0.icache.demand_hits::total 10915164 # number of demand (read+write) hits 1480system.cpu0.icache.overall_hits::cpu0.inst 10915164 # number of overall hits 1481system.cpu0.icache.overall_hits::total 10915164 # number of overall hits 1482system.cpu0.icache.ReadReq_misses::cpu0.inst 334091 # number of ReadReq misses 1483system.cpu0.icache.ReadReq_misses::total 334091 # number of ReadReq misses 1484system.cpu0.icache.demand_misses::cpu0.inst 334091 # number of demand (read+write) misses 1485system.cpu0.icache.demand_misses::total 334091 # number of demand (read+write) misses 1486system.cpu0.icache.overall_misses::cpu0.inst 334091 # number of overall misses 1487system.cpu0.icache.overall_misses::total 334091 # number of overall misses 1488system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863305358 # number of ReadReq miss cycles 1489system.cpu0.icache.ReadReq_miss_latency::total 2863305358 # number of ReadReq miss cycles 1490system.cpu0.icache.demand_miss_latency::cpu0.inst 2863305358 # number of demand (read+write) miss cycles 1491system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles 1492system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles 1493system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles 1494system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses) 1495system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses) 1496system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses 1497system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses 1498system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses 1499system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses 1500system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses 1501system.cpu0.icache.ReadReq_miss_rate::total 0.029699 # miss rate for ReadReq accesses 1502system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029699 # miss rate for demand accesses 1503system.cpu0.icache.demand_miss_rate::total 0.029699 # miss rate for demand accesses 1504system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029699 # miss rate for overall accesses 1505system.cpu0.icache.overall_miss_rate::total 0.029699 # miss rate for overall accesses 1506system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8570.435474 # average ReadReq miss latency 1507system.cpu0.icache.ReadReq_avg_miss_latency::total 8570.435474 # average ReadReq miss latency 1508system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency 1509system.cpu0.icache.demand_avg_miss_latency::total 8570.435474 # average overall miss latency 1510system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency 1511system.cpu0.icache.overall_avg_miss_latency::total 8570.435474 # average overall miss latency 1512system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked 1513system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked 1514system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked 1515system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked 1516system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked 1517system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked |
| 1412system.cpu0.icache.fast_writes 0 # number of fast writes performed 1413system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1518system.cpu0.icache.fast_writes 0 # number of fast writes performed 1519system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1414system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 25235 # number of ReadReq MSHR hits 1415system.cpu0.icache.ReadReq_mshr_hits::total 25235 # number of ReadReq MSHR hits 1416system.cpu0.icache.demand_mshr_hits::cpu0.inst 25235 # number of demand (read+write) MSHR hits 1417system.cpu0.icache.demand_mshr_hits::total 25235 # number of demand (read+write) MSHR hits 1418system.cpu0.icache.overall_mshr_hits::cpu0.inst 25235 # number of overall MSHR hits 1419system.cpu0.icache.overall_mshr_hits::total 25235 # number of overall MSHR hits 1420system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 554526 # number of ReadReq MSHR misses 1421system.cpu0.icache.ReadReq_mshr_misses::total 554526 # number of ReadReq MSHR misses 1422system.cpu0.icache.demand_mshr_misses::cpu0.inst 554526 # number of demand (read+write) MSHR misses 1423system.cpu0.icache.demand_mshr_misses::total 554526 # number of demand (read+write) MSHR misses 1424system.cpu0.icache.overall_mshr_misses::cpu0.inst 554526 # number of overall MSHR misses 1425system.cpu0.icache.overall_mshr_misses::total 554526 # number of overall MSHR misses 1426system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6629844046 # number of ReadReq MSHR miss cycles 1427system.cpu0.icache.ReadReq_mshr_miss_latency::total 6629844046 # number of ReadReq MSHR miss cycles 1428system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6629844046 # number of demand (read+write) MSHR miss cycles 1429system.cpu0.icache.demand_mshr_miss_latency::total 6629844046 # number of demand (read+write) MSHR miss cycles 1430system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6629844046 # number of overall MSHR miss cycles 1431system.cpu0.icache.overall_mshr_miss_latency::total 6629844046 # number of overall MSHR miss cycles 1432system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 226658500 # number of ReadReq MSHR uncacheable cycles 1433system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 226658500 # number of ReadReq MSHR uncacheable cycles 1434system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 226658500 # number of overall MSHR uncacheable cycles 1435system.cpu0.icache.overall_mshr_uncacheable_latency::total 226658500 # number of overall MSHR uncacheable cycles 1436system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for ReadReq accesses 1437system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033716 # mshr miss rate for ReadReq accesses 1438system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for demand accesses 1439system.cpu0.icache.demand_mshr_miss_rate::total 0.033716 # mshr miss rate for demand accesses 1440system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for overall accesses 1441system.cpu0.icache.overall_mshr_miss_rate::total 0.033716 # mshr miss rate for overall accesses 1442system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average ReadReq mshr miss latency 1443system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11955.875912 # average ReadReq mshr miss latency 1444system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency 1445system.cpu0.icache.demand_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency 1446system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency 1447system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency | 1520system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits 1521system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits 1522system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits 1523system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits 1524system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits 1525system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits 1526system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses 1527system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses 1528system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses 1529system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses 1530system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses 1531system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses 1532system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles 1533system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles 1534system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles 1535system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles 1536system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles 1537system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles 1538system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles 1539system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 272886999 # number of ReadReq MSHR uncacheable cycles 1540system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 272886999 # number of overall MSHR uncacheable cycles 1541system.cpu0.icache.overall_mshr_uncacheable_latency::total 272886999 # number of overall MSHR uncacheable cycles 1542system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for ReadReq accesses 1543system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028681 # mshr miss rate for ReadReq accesses 1544system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for demand accesses 1545system.cpu0.icache.demand_mshr_miss_rate::total 0.028681 # mshr miss rate for demand accesses 1546system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for overall accesses 1547system.cpu0.icache.overall_mshr_miss_rate::total 0.028681 # mshr miss rate for overall accesses 1548system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average ReadReq mshr miss latency 1549system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency 1550system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency 1551system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency 1552system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency 1553system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency |
| 1448system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1449system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1450system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1451system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1452system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1554system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1555system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1556system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1557system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1558system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1453system.cpu0.dcache.tags.replacements 409126 # number of replacements 1454system.cpu0.dcache.tags.tagsinuse 483.194796 # Cycle average of tags in use 1455system.cpu0.dcache.tags.total_refs 12942599 # Total number of references to valid blocks. 1456system.cpu0.dcache.tags.sampled_refs 409638 # Sample count of references to valid blocks. 1457system.cpu0.dcache.tags.avg_refs 31.595211 # Average number of references to valid blocks. 1458system.cpu0.dcache.tags.warmup_cycle 271704250 # Cycle when the warmup percentage was hit. 1459system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.194796 # Average occupied blocks per requestor 1460system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943740 # Average percentage of cache occupancy 1461system.cpu0.dcache.tags.occ_percent::total 0.943740 # Average percentage of cache occupancy | 1559system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified 1560system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr 1561system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache 1562system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue 1563system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1564system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated 1565system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued 1566system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page 1567system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1568system.cpu0.l2cache.tags.replacements 165160 # number of replacements 1569system.cpu0.l2cache.tags.tagsinuse 15951.411231 # Cycle average of tags in use 1570system.cpu0.l2cache.tags.total_refs 747099 # Total number of references to valid blocks. 1571system.cpu0.l2cache.tags.sampled_refs 181321 # Sample count of references to valid blocks. 1572system.cpu0.l2cache.tags.avg_refs 4.120311 # Average number of references to valid blocks. 1573system.cpu0.l2cache.tags.warmup_cycle 4999805500 # Cycle when the warmup percentage was hit. 1574system.cpu0.l2cache.tags.occ_blocks::writebacks 4772.372752 # Average occupied blocks per requestor 1575system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.637155 # Average occupied blocks per requestor 1576system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.084033 # Average occupied blocks per requestor 1577system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor 1578system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor 1579system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor 1580system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy 1581system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy 1582system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy 1583system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy 1584system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy 1585system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy 1586system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy 1587system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id 1588system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id 1589system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8811 # Occupied blocks per task id 1590system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id 1591system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id 1592system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1027 # Occupied blocks per task id 1593system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id 1594system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 943 # Occupied blocks per task id 1595system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1596system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1597system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 1598system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1599system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id 1600system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id 1601system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6017 # Occupied blocks per task id 1602system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id 1603system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.447876 # Percentage of cache occupancy per task id 1604system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 1605system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.537781 # Percentage of cache occupancy per task id 1606system.cpu0.l2cache.tags.tag_accesses 15517001 # Number of tag accesses 1607system.cpu0.l2cache.tags.data_accesses 15517001 # Number of data accesses 1608system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 19658 # number of ReadReq hits 1609system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6554 # number of ReadReq hits 1610system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314769 # number of ReadReq hits 1611system.cpu0.l2cache.ReadReq_hits::cpu0.data 162769 # number of ReadReq hits 1612system.cpu0.l2cache.ReadReq_hits::total 503750 # number of ReadReq hits 1613system.cpu0.l2cache.Writeback_hits::writebacks 228045 # number of Writeback hits 1614system.cpu0.l2cache.Writeback_hits::total 228045 # number of Writeback hits 1615system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6593 # number of UpgradeReq hits 1616system.cpu0.l2cache.UpgradeReq_hits::total 6593 # number of UpgradeReq hits 1617system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 622 # number of SCUpgradeReq hits 1618system.cpu0.l2cache.SCUpgradeReq_hits::total 622 # number of SCUpgradeReq hits 1619system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95529 # number of ReadExReq hits 1620system.cpu0.l2cache.ReadExReq_hits::total 95529 # number of ReadExReq hits 1621system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 19658 # number of demand (read+write) hits 1622system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6554 # number of demand (read+write) hits 1623system.cpu0.l2cache.demand_hits::cpu0.inst 314769 # number of demand (read+write) hits 1624system.cpu0.l2cache.demand_hits::cpu0.data 258298 # number of demand (read+write) hits 1625system.cpu0.l2cache.demand_hits::total 599279 # number of demand (read+write) hits 1626system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 19658 # number of overall hits 1627system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6554 # number of overall hits 1628system.cpu0.l2cache.overall_hits::cpu0.inst 314769 # number of overall hits 1629system.cpu0.l2cache.overall_hits::cpu0.data 258298 # number of overall hits 1630system.cpu0.l2cache.overall_hits::total 599279 # number of overall hits 1631system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 345 # number of ReadReq misses 1632system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses 1633system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7801 # number of ReadReq misses 1634system.cpu0.l2cache.ReadReq_misses::cpu0.data 50805 # number of ReadReq misses 1635system.cpu0.l2cache.ReadReq_misses::total 59122 # number of ReadReq misses 1636system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses 1637system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses 1638system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19680 # number of UpgradeReq misses 1639system.cpu0.l2cache.UpgradeReq_misses::total 19680 # number of UpgradeReq misses 1640system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10856 # number of SCUpgradeReq misses 1641system.cpu0.l2cache.SCUpgradeReq_misses::total 10856 # number of SCUpgradeReq misses 1642system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1643system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1644system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23597 # number of ReadExReq misses 1645system.cpu0.l2cache.ReadExReq_misses::total 23597 # number of ReadExReq misses 1646system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 345 # number of demand (read+write) misses 1647system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses 1648system.cpu0.l2cache.demand_misses::cpu0.inst 7801 # number of demand (read+write) misses 1649system.cpu0.l2cache.demand_misses::cpu0.data 74402 # number of demand (read+write) misses 1650system.cpu0.l2cache.demand_misses::total 82719 # number of demand (read+write) misses 1651system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 345 # number of overall misses 1652system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses 1653system.cpu0.l2cache.overall_misses::cpu0.inst 7801 # number of overall misses 1654system.cpu0.l2cache.overall_misses::cpu0.data 74402 # number of overall misses 1655system.cpu0.l2cache.overall_misses::total 82719 # number of overall misses 1656system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7498249 # number of ReadReq miss cycles 1657system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3753000 # number of ReadReq miss cycles 1658system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 255179729 # number of ReadReq miss cycles 1659system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1303745054 # number of ReadReq miss cycles 1660system.cpu0.l2cache.ReadReq_miss_latency::total 1570176032 # number of ReadReq miss cycles 1661system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 310997961 # number of UpgradeReq miss cycles 1662system.cpu0.l2cache.UpgradeReq_miss_latency::total 310997961 # number of UpgradeReq miss cycles 1663system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 212766148 # number of SCUpgradeReq miss cycles 1664system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 212766148 # number of SCUpgradeReq miss cycles 1665system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 609000 # number of SCUpgradeFailReq miss cycles 1666system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 609000 # number of SCUpgradeFailReq miss cycles 1667system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 893661798 # number of ReadExReq miss cycles 1668system.cpu0.l2cache.ReadExReq_miss_latency::total 893661798 # number of ReadExReq miss cycles 1669system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7498249 # number of demand (read+write) miss cycles 1670system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3753000 # number of demand (read+write) miss cycles 1671system.cpu0.l2cache.demand_miss_latency::cpu0.inst 255179729 # number of demand (read+write) miss cycles 1672system.cpu0.l2cache.demand_miss_latency::cpu0.data 2197406852 # number of demand (read+write) miss cycles 1673system.cpu0.l2cache.demand_miss_latency::total 2463837830 # number of demand (read+write) miss cycles 1674system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7498249 # number of overall miss cycles 1675system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3753000 # number of overall miss cycles 1676system.cpu0.l2cache.overall_miss_latency::cpu0.inst 255179729 # number of overall miss cycles 1677system.cpu0.l2cache.overall_miss_latency::cpu0.data 2197406852 # number of overall miss cycles 1678system.cpu0.l2cache.overall_miss_latency::total 2463837830 # number of overall miss cycles 1679system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20003 # number of ReadReq accesses(hits+misses) 1680system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6725 # number of ReadReq accesses(hits+misses) 1681system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322570 # number of ReadReq accesses(hits+misses) 1682system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213574 # number of ReadReq accesses(hits+misses) 1683system.cpu0.l2cache.ReadReq_accesses::total 562872 # number of ReadReq accesses(hits+misses) 1684system.cpu0.l2cache.Writeback_accesses::writebacks 228050 # number of Writeback accesses(hits+misses) 1685system.cpu0.l2cache.Writeback_accesses::total 228050 # number of Writeback accesses(hits+misses) 1686system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) 1687system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) 1688system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11478 # number of SCUpgradeReq accesses(hits+misses) 1689system.cpu0.l2cache.SCUpgradeReq_accesses::total 11478 # number of SCUpgradeReq accesses(hits+misses) 1690system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1691system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1692system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119126 # number of ReadExReq accesses(hits+misses) 1693system.cpu0.l2cache.ReadExReq_accesses::total 119126 # number of ReadExReq accesses(hits+misses) 1694system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20003 # number of demand (read+write) accesses 1695system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6725 # number of demand (read+write) accesses 1696system.cpu0.l2cache.demand_accesses::cpu0.inst 322570 # number of demand (read+write) accesses 1697system.cpu0.l2cache.demand_accesses::cpu0.data 332700 # number of demand (read+write) accesses 1698system.cpu0.l2cache.demand_accesses::total 681998 # number of demand (read+write) accesses 1699system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20003 # number of overall (read+write) accesses 1700system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6725 # number of overall (read+write) accesses 1701system.cpu0.l2cache.overall_accesses::cpu0.inst 322570 # number of overall (read+write) accesses 1702system.cpu0.l2cache.overall_accesses::cpu0.data 332700 # number of overall (read+write) accesses 1703system.cpu0.l2cache.overall_accesses::total 681998 # number of overall (read+write) accesses 1704system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for ReadReq accesses 1705system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025428 # miss rate for ReadReq accesses 1706system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024184 # miss rate for ReadReq accesses 1707system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.237880 # miss rate for ReadReq accesses 1708system.cpu0.l2cache.ReadReq_miss_rate::total 0.105036 # miss rate for ReadReq accesses 1709system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000022 # miss rate for Writeback accesses 1710system.cpu0.l2cache.Writeback_miss_rate::total 0.000022 # miss rate for Writeback accesses 1711system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.749058 # miss rate for UpgradeReq accesses 1712system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses 1713system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.945809 # miss rate for SCUpgradeReq accesses 1714system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.945809 # miss rate for SCUpgradeReq accesses 1715system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1716system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1717system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198084 # miss rate for ReadExReq accesses 1718system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198084 # miss rate for ReadExReq accesses 1719system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for demand accesses 1720system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025428 # miss rate for demand accesses 1721system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024184 # miss rate for demand accesses 1722system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223631 # miss rate for demand accesses 1723system.cpu0.l2cache.demand_miss_rate::total 0.121289 # miss rate for demand accesses 1724system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for overall accesses 1725system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025428 # miss rate for overall accesses 1726system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024184 # miss rate for overall accesses 1727system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223631 # miss rate for overall accesses 1728system.cpu0.l2cache.overall_miss_rate::total 0.121289 # miss rate for overall accesses 1729system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average ReadReq miss latency 1730system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21947.368421 # average ReadReq miss latency 1731system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32711.156134 # average ReadReq miss latency 1732system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency 1733system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26558.236054 # average ReadReq miss latency 1734system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15802.741921 # average UpgradeReq miss latency 1735system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency 1736system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19598.945099 # average SCUpgradeReq miss latency 1737system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency 1738system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 609000 # average SCUpgradeFailReq miss latency 1739system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 609000 # average SCUpgradeFailReq miss latency 1740system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37871.839556 # average ReadExReq miss latency 1741system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37871.839556 # average ReadExReq miss latency 1742system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency 1743system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency 1744system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency 1745system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency 1746system.cpu0.l2cache.demand_avg_miss_latency::total 29785.633651 # average overall miss latency 1747system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency 1748system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency 1749system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency 1750system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency 1751system.cpu0.l2cache.overall_avg_miss_latency::total 29785.633651 # average overall miss latency 1752system.cpu0.l2cache.blocked_cycles::no_mshrs 4781 # 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number of ReadReq MSHR hits 1765system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 997 # number of ReadReq MSHR hits 1766system.cpu0.l2cache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits 1767system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 936 # number of ReadExReq MSHR hits 1768system.cpu0.l2cache.ReadExReq_mshr_hits::total 936 # number of ReadExReq MSHR hits 1769system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1770system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1771system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1845 # number of demand (read+write) MSHR hits 1772system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1933 # number of demand (read+write) MSHR hits 1773system.cpu0.l2cache.demand_mshr_hits::total 3780 # number of demand (read+write) MSHR hits 1774system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1775system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1776system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1845 # number of overall MSHR hits 1777system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1933 # number of overall MSHR hits 1778system.cpu0.l2cache.overall_mshr_hits::total 3780 # number of overall MSHR hits 1779system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses 1780system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 170 # number of ReadReq MSHR misses 1781system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5956 # number of ReadReq MSHR misses 1782system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49808 # number of ReadReq MSHR misses 1783system.cpu0.l2cache.ReadReq_mshr_misses::total 56278 # number of ReadReq MSHR misses 1784system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses 1785system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses 1786system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 198779 # 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number of SCUpgradeReq MSHR miss cycles 1817system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles 1818system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles 1819system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles 1820system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # number of ReadExReq MSHR miss cycles 1821system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 601346170 # number of ReadExReq MSHR miss cycles 1822system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of demand (read+write) MSHR miss cycles 1823system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2550500 # number of demand (read+write) MSHR miss cycles 1824system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 181100759 # number of demand (read+write) MSHR miss cycles 1825system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541770762 # number of demand (read+write) MSHR miss cycles 1826system.cpu0.l2cache.demand_mshr_miss_latency::total 1730426772 # number of demand (read+write) MSHR miss cycles 1827system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of overall MSHR miss cycles 1828system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2550500 # number of overall MSHR miss cycles 1829system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles 1830system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles 1831system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles 1832system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles 1833system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles 1834system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles 1835system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles 1836system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles 1837system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles 1838system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles 1839system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles 1840system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles 1841system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses 1842system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses 1843system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses 1844system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses 1845system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses 1846system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses 1847system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses 1848system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1849system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1850system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses 1851system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses 1852system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses 1853system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses 1854system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1855system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1856system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses 1857system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses 1858system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses 1859system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses 1860system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses 1861system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses 1862system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses 1863system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses 1864system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses 1865system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses 1866system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses 1867system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1868system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses 1869system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency 1870system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency 1871system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency 1872system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency 1873system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency 1874system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency 1875system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency 1876system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency 1877system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency 1878system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency 1879system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency 1880system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency 1881system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency 1882system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency 1883system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency 1884system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency 1885system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency 1886system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency 1887system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency 1888system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency 1889system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency 1890system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency 1891system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency 1892system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency 1893system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency 1894system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency 1895system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1896system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1897system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1898system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1899system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1900system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1901system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1902system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1903system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1904system.cpu0.dcache.tags.replacements 297335 # number of replacements 1905system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use 1906system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks. 1907system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks. 1908system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks. 1909system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. 1910system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor 1911system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy 1912system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy |
| 1462system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1913system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1463system.cpu0.dcache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id 1464system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id 1465system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 1466system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 1914system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 1915system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id 1916system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id |
| 1467system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1917system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1468system.cpu0.dcache.tags.tag_accesses 63030887 # Number of tag accesses 1469system.cpu0.dcache.tags.data_accesses 63030887 # Number of data accesses 1470system.cpu0.dcache.ReadReq_hits::cpu0.data 8037454 # number of ReadReq hits 1471system.cpu0.dcache.ReadReq_hits::total 8037454 # number of ReadReq hits 1472system.cpu0.dcache.WriteReq_hits::cpu0.data 4509267 # number of WriteReq hits 1473system.cpu0.dcache.WriteReq_hits::total 4509267 # number of WriteReq hits 1474system.cpu0.dcache.SoftPFReq_hits::cpu0.data 46089 # number of SoftPFReq hits 1475system.cpu0.dcache.SoftPFReq_hits::total 46089 # number of SoftPFReq hits 1476system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156971 # number of LoadLockedReq hits 1477system.cpu0.dcache.LoadLockedReq_hits::total 156971 # number of LoadLockedReq hits 1478system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159079 # number of StoreCondReq hits 1479system.cpu0.dcache.StoreCondReq_hits::total 159079 # number of StoreCondReq hits 1480system.cpu0.dcache.demand_hits::cpu0.data 12546721 # number of demand (read+write) hits 1481system.cpu0.dcache.demand_hits::total 12546721 # number of demand (read+write) hits 1482system.cpu0.dcache.overall_hits::cpu0.data 12592810 # number of overall hits 1483system.cpu0.dcache.overall_hits::total 12592810 # number of overall hits 1484system.cpu0.dcache.ReadReq_misses::cpu0.data 406720 # number of ReadReq misses 1485system.cpu0.dcache.ReadReq_misses::total 406720 # number of ReadReq misses 1486system.cpu0.dcache.WriteReq_misses::cpu0.data 2221250 # number of WriteReq misses 1487system.cpu0.dcache.WriteReq_misses::total 2221250 # number of WriteReq misses 1488system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92142 # number of SoftPFReq misses 1489system.cpu0.dcache.SoftPFReq_misses::total 92142 # number of SoftPFReq misses 1490system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10979 # number of LoadLockedReq misses 1491system.cpu0.dcache.LoadLockedReq_misses::total 10979 # number of LoadLockedReq misses 1492system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7659 # number of StoreCondReq misses 1493system.cpu0.dcache.StoreCondReq_misses::total 7659 # number of StoreCondReq misses 1494system.cpu0.dcache.demand_misses::cpu0.data 2627970 # number of demand (read+write) misses 1495system.cpu0.dcache.demand_misses::total 2627970 # number of demand (read+write) misses 1496system.cpu0.dcache.overall_misses::cpu0.data 2720112 # number of overall misses 1497system.cpu0.dcache.overall_misses::total 2720112 # number of overall misses 1498system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5668958645 # number of ReadReq miss cycles 1499system.cpu0.dcache.ReadReq_miss_latency::total 5668958645 # number of ReadReq miss cycles 1500system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686 # number of WriteReq miss cycles 1501system.cpu0.dcache.WriteReq_miss_latency::total 107130503686 # number of WriteReq miss cycles 1502system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114563996 # number of LoadLockedReq miss cycles 1503system.cpu0.dcache.LoadLockedReq_miss_latency::total 114563996 # number of LoadLockedReq miss cycles 1504system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44413016 # number of StoreCondReq miss cycles 1505system.cpu0.dcache.StoreCondReq_miss_latency::total 44413016 # number of StoreCondReq miss cycles 1506system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331 # number of demand (read+write) miss cycles 1507system.cpu0.dcache.demand_miss_latency::total 112799462331 # number of demand (read+write) miss cycles 1508system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331 # number of overall miss cycles 1509system.cpu0.dcache.overall_miss_latency::total 112799462331 # number of overall miss cycles 1510system.cpu0.dcache.ReadReq_accesses::cpu0.data 8444174 # number of ReadReq accesses(hits+misses) 1511system.cpu0.dcache.ReadReq_accesses::total 8444174 # number of ReadReq accesses(hits+misses) 1512system.cpu0.dcache.WriteReq_accesses::cpu0.data 6730517 # number of WriteReq accesses(hits+misses) 1513system.cpu0.dcache.WriteReq_accesses::total 6730517 # number of WriteReq accesses(hits+misses) 1514system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 138231 # number of SoftPFReq accesses(hits+misses) 1515system.cpu0.dcache.SoftPFReq_accesses::total 138231 # number of SoftPFReq accesses(hits+misses) 1516system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167950 # number of LoadLockedReq accesses(hits+misses) 1517system.cpu0.dcache.LoadLockedReq_accesses::total 167950 # number of LoadLockedReq accesses(hits+misses) 1518system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166738 # number of StoreCondReq accesses(hits+misses) 1519system.cpu0.dcache.StoreCondReq_accesses::total 166738 # number of StoreCondReq accesses(hits+misses) 1520system.cpu0.dcache.demand_accesses::cpu0.data 15174691 # number of demand (read+write) accesses 1521system.cpu0.dcache.demand_accesses::total 15174691 # number of demand (read+write) accesses 1522system.cpu0.dcache.overall_accesses::cpu0.data 15312922 # number of overall (read+write) accesses 1523system.cpu0.dcache.overall_accesses::total 15312922 # number of overall (read+write) accesses 1524system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048166 # miss rate for ReadReq accesses 1525system.cpu0.dcache.ReadReq_miss_rate::total 0.048166 # miss rate for ReadReq accesses 1526system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330027 # miss rate for WriteReq accesses 1527system.cpu0.dcache.WriteReq_miss_rate::total 0.330027 # miss rate for WriteReq accesses 1528system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.666580 # miss rate for SoftPFReq accesses 1529system.cpu0.dcache.SoftPFReq_miss_rate::total 0.666580 # miss rate for SoftPFReq accesses 1530system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065371 # miss rate for LoadLockedReq accesses 1531system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065371 # miss rate for LoadLockedReq accesses 1532system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.045934 # miss rate for StoreCondReq accesses 1533system.cpu0.dcache.StoreCondReq_miss_rate::total 0.045934 # miss rate for StoreCondReq accesses 1534system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173181 # miss rate for demand accesses 1535system.cpu0.dcache.demand_miss_rate::total 0.173181 # miss rate for demand accesses 1536system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177635 # miss rate for overall accesses 1537system.cpu0.dcache.overall_miss_rate::total 0.177635 # miss rate for overall accesses 1538system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277 # average ReadReq miss latency 1539system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277 # average ReadReq miss latency 1540system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208 # average WriteReq miss latency 1541system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208 # average WriteReq miss latency 1542system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766 # average LoadLockedReq miss latency 1543system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766 # average LoadLockedReq miss latency 1544system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5798.800888 # average StoreCondReq miss latency 1545system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5798.800888 # average StoreCondReq miss latency 1546system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821 # average overall miss latency 1547system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821 # average overall miss latency 1548system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029 # average overall miss latency 1549system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029 # average overall miss latency 1550system.cpu0.dcache.blocked_cycles::no_mshrs 14275 # number of cycles access was blocked 1551system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1552system.cpu0.dcache.blocked::no_mshrs 1041 # number of cycles access was blocked 1553system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1554system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.712776 # average number of cycles each access was blocked 1555system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1918system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses 1919system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses 1920system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits 1921system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits 1922system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits 1923system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits 1924system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits 1925system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits 1926system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits 1927system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits 1928system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits 1929system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits 1930system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits 1931system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits 1932system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits 1933system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits 1934system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses 1935system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses 1936system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses 1937system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses 1938system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses 1939system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses 1940system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses 1941system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses 1942system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses 1943system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses 1944system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses 1945system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses 1946system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses 1947system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses 1948system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles 1949system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles 1950system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles 1951system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles 1952system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles 1953system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles 1954system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273467244 # number of StoreCondReq miss cycles 1955system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles 1956system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles 1957system.cpu0.dcache.StoreCondFailReq_miss_latency::total 660000 # number of StoreCondFailReq miss cycles 1958system.cpu0.dcache.demand_miss_latency::cpu0.data 16742760911 # number of demand (read+write) miss cycles 1959system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles 1960system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles 1961system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles 1962system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses) 1963system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses) 1964system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses) 1965system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses) 1966system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses) 1967system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses) 1968system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses) 1969system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses) 1970system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses) 1971system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses) 1972system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses 1973system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses 1974system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses 1975system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses 1976system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses 1977system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses 1978system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses 1979system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses 1980system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses 1981system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses 1982system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses 1983system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses 1984system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses 1985system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses 1986system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses 1987system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses 1988system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses 1989system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses 1990system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency 1991system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency 1992system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency 1993system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency 1994system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency 1995system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency 1996system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency 1997system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency 1998system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1999system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2000system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency 2001system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency 2002system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency 2003system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency 2004system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 2005system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked 2006system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked 2007system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked 2008system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 2009system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked |
| 1556system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1557system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 2010system.cpu0.dcache.fast_writes 0 # number of fast writes performed 2011system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1558system.cpu0.dcache.writebacks::writebacks 375988 # number of writebacks 1559system.cpu0.dcache.writebacks::total 375988 # number of writebacks 1560system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 193747 # number of ReadReq MSHR hits 1561system.cpu0.dcache.ReadReq_mshr_hits::total 193747 # number of ReadReq MSHR hits 1562system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2045363 # number of WriteReq MSHR hits 1563system.cpu0.dcache.WriteReq_mshr_hits::total 2045363 # number of WriteReq MSHR hits 1564system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1054 # number of LoadLockedReq MSHR hits 1565system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1054 # number of LoadLockedReq MSHR hits 1566system.cpu0.dcache.demand_mshr_hits::cpu0.data 2239110 # number of demand (read+write) MSHR hits 1567system.cpu0.dcache.demand_mshr_hits::total 2239110 # number of demand (read+write) MSHR hits 1568system.cpu0.dcache.overall_mshr_hits::cpu0.data 2239110 # number of overall MSHR hits 1569system.cpu0.dcache.overall_mshr_hits::total 2239110 # number of overall MSHR hits 1570system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212973 # number of ReadReq MSHR misses 1571system.cpu0.dcache.ReadReq_mshr_misses::total 212973 # number of ReadReq MSHR misses 1572system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175887 # number of WriteReq MSHR misses 1573system.cpu0.dcache.WriteReq_mshr_misses::total 175887 # number of WriteReq MSHR misses 1574system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54623 # number of SoftPFReq MSHR misses 1575system.cpu0.dcache.SoftPFReq_mshr_misses::total 54623 # number of SoftPFReq MSHR misses 1576system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses 1577system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses 1578system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7659 # number of StoreCondReq MSHR misses 1579system.cpu0.dcache.StoreCondReq_mshr_misses::total 7659 # number of StoreCondReq MSHR misses 1580system.cpu0.dcache.demand_mshr_misses::cpu0.data 388860 # number of demand (read+write) MSHR misses 1581system.cpu0.dcache.demand_mshr_misses::total 388860 # number of demand (read+write) MSHR misses 1582system.cpu0.dcache.overall_mshr_misses::cpu0.data 443483 # number of overall MSHR misses 1583system.cpu0.dcache.overall_mshr_misses::total 443483 # number of overall MSHR misses 1584system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2487825853 # number of ReadReq MSHR miss cycles 1585system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2487825853 # number of ReadReq MSHR miss cycles 1586system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7369362883 # number of WriteReq MSHR miss cycles 1587system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7369362883 # number of WriteReq MSHR miss cycles 1588system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1035896777 # number of SoftPFReq MSHR miss cycles 1589system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035896777 # number of SoftPFReq MSHR miss cycles 1590system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82981003 # number of LoadLockedReq MSHR miss cycles 1591system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 82981003 # number of LoadLockedReq MSHR miss cycles 1592system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29093984 # number of StoreCondReq MSHR miss cycles 1593system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29093984 # number of StoreCondReq MSHR miss cycles 1594system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9857188736 # number of demand (read+write) MSHR miss cycles 1595system.cpu0.dcache.demand_mshr_miss_latency::total 9857188736 # number of demand (read+write) MSHR miss cycles 1596system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10893085513 # number of overall MSHR miss cycles 1597system.cpu0.dcache.overall_mshr_miss_latency::total 10893085513 # number of overall MSHR miss cycles 1598system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13737621002 # number of ReadReq MSHR uncacheable cycles 1599system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13737621002 # number of ReadReq MSHR uncacheable cycles 1600system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 26275689041 # number of WriteReq MSHR uncacheable cycles 1601system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26275689041 # number of WriteReq MSHR uncacheable cycles 1602system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 40013310043 # number of overall MSHR uncacheable cycles 1603system.cpu0.dcache.overall_mshr_uncacheable_latency::total 40013310043 # number of overall MSHR uncacheable cycles 1604system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for ReadReq accesses 1605system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025221 # mshr miss rate for ReadReq accesses 1606system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026133 # mshr miss rate for WriteReq accesses 1607system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026133 # mshr miss rate for WriteReq accesses 1608system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.395157 # mshr miss rate for SoftPFReq accesses 1609system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.395157 # mshr miss rate for SoftPFReq accesses 1610system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059095 # mshr miss rate for LoadLockedReq accesses 1611system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059095 # mshr miss rate for LoadLockedReq accesses 1612system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.045934 # mshr miss rate for StoreCondReq accesses 1613system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.045934 # mshr miss rate for StoreCondReq accesses 1614system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025626 # mshr miss rate for demand accesses 1615system.cpu0.dcache.demand_mshr_miss_rate::total 0.025626 # mshr miss rate for demand accesses 1616system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028961 # mshr miss rate for overall accesses 1617system.cpu0.dcache.overall_mshr_miss_rate::total 0.028961 # mshr miss rate for overall accesses 1618system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325 # average ReadReq mshr miss latency 1619system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325 # average ReadReq mshr miss latency 1620system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618 # average WriteReq mshr miss latency 1621system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618 # average WriteReq mshr miss latency 1622system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743 # average SoftPFReq mshr miss latency 1623system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743 # average SoftPFReq mshr miss latency 1624system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8360.806348 # average LoadLockedReq mshr miss latency 1625system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8360.806348 # average LoadLockedReq mshr miss latency 1626system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3798.666144 # average StoreCondReq mshr miss latency 1627system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3798.666144 # average StoreCondReq mshr miss latency 1628system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814 # average overall mshr miss latency 1629system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814 # average overall mshr miss latency 1630system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400 # average overall mshr miss latency 1631system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400 # average overall mshr miss latency | 2012system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks 2013system.cpu0.dcache.writebacks::total 228050 # number of writebacks 2014system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits 2015system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits 2016system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits 2017system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits 2018system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits 2019system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits 2020system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits 2021system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits 2022system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits 2023system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits 2024system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses 2025system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses 2026system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses 2027system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses 2028system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses 2029system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses 2030system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses 2031system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses 2032system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses 2033system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses 2034system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses 2035system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses 2036system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses 2037system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses 2038system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles 2039system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles 2040system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles 2041system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles 2042system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles 2043system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles 2044system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles 2045system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles 2046system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles 2047system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles 2048system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles 2049system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles 2050system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles 2051system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles 2052system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles 2053system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles 2054system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles 2055system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles 2056system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles 2057system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles 2058system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles 2059system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles 2060system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses 2061system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses 2062system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses 2063system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses 2064system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses 2065system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses 2066system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses 2067system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses 2068system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses 2069system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses 2070system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses 2071system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses 2072system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses 2073system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses 2074system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency 2075system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency 2076system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency 2077system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency 2078system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency 2079system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency 2080system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency 2081system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency 2082system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency 2083system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency 2084system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2085system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2086system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency 2087system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency 2088system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency 2089system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency |
| 1632system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1633system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1634system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1635system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1636system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1637system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1638system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2090system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2091system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2092system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2093system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2094system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2096system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1639system.cpu1.branchPred.lookups 5001209 # Number of BP lookups 1640system.cpu1.branchPred.condPredicted 3530067 # Number of conditional branches predicted 1641system.cpu1.branchPred.condIncorrect 291977 # Number of conditional branches incorrect 1642system.cpu1.branchPred.BTBLookups 3184313 # Number of BTB lookups 1643system.cpu1.branchPred.BTBHits 2141032 # Number of BTB hits | 2097system.cpu1.branchPred.lookups 9149866 # Number of BP lookups 2098system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted 2099system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect 2100system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups 2101system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits |
| 1644system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 2102system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1645system.cpu1.branchPred.BTBHitPct 67.236858 # BTB Hit Percentage 1646system.cpu1.branchPred.usedRAS 582225 # Number of times the RAS was used to get a target. 1647system.cpu1.branchPred.RASInCorrect 13211 # Number of incorrect RAS predictions. | 2103system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage 2104system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target. 2105system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions. |
| 1648system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1649system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1650system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1651system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1652system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1653system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1654system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1655system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1663system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1664system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1665system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1666system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1667system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1668system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1669system.cpu1.dtb.inst_hits 0 # ITB inst hits 1670system.cpu1.dtb.inst_misses 0 # ITB inst misses | 2106system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2107system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2108system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2109system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2110system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2111system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2112system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2113system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 2121system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2122system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2123system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2124system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2125system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2126system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2127system.cpu1.dtb.inst_hits 0 # ITB inst hits 2128system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1671system.cpu1.dtb.read_hits 21293354 # DTB read hits 1672system.cpu1.dtb.read_misses 17527 # DTB read misses 1673system.cpu1.dtb.write_hits 4063342 # DTB write hits 1674system.cpu1.dtb.write_misses 3266 # DTB write misses | 2129system.cpu1.dtb.read_hits 25102636 # DTB read hits 2130system.cpu1.dtb.read_misses 30137 # DTB read misses 2131system.cpu1.dtb.write_hits 6841685 # DTB write hits 2132system.cpu1.dtb.write_misses 6769 # DTB write misses |
| 1675system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1676system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1677system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1678system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 2133system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2134system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2135system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2136system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1679system.cpu1.dtb.flush_entries 1908 # Number of entries that have been flushed from TLB 1680system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions 1681system.cpu1.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch | 2137system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB 2138system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions 2139system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch |
| 1682system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 2140system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1683system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions 1684system.cpu1.dtb.read_accesses 21310881 # DTB read accesses 1685system.cpu1.dtb.write_accesses 4066608 # DTB write accesses | 2141system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions 2142system.cpu1.dtb.read_accesses 25132773 # DTB read accesses 2143system.cpu1.dtb.write_accesses 6848454 # DTB write accesses |
| 1686system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 2144system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1687system.cpu1.dtb.hits 25356696 # DTB hits 1688system.cpu1.dtb.misses 20793 # DTB misses 1689system.cpu1.dtb.accesses 25377489 # DTB accesses | 2145system.cpu1.dtb.hits 31944321 # DTB hits 2146system.cpu1.dtb.misses 36906 # DTB misses 2147system.cpu1.dtb.accesses 31981227 # DTB accesses |
| 1690system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1691system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1692system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1693system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1694system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1695system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1696system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1697system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1703system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1704system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1705system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1706system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1707system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1708system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1709system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1710system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 2148system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2149system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2150system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2151system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2152system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2153system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2154system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2155system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 2161system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2162system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2163system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2164system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2165system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2166system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2167system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2168system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1711system.cpu1.itb.inst_hits 8626509 # ITB inst hits 1712system.cpu1.itb.inst_misses 4363 # ITB inst misses | 2169system.cpu1.itb.inst_hits 16803682 # ITB inst hits 2170system.cpu1.itb.inst_misses 6173 # ITB inst misses |
| 1713system.cpu1.itb.read_hits 0 # DTB read hits 1714system.cpu1.itb.read_misses 0 # DTB read misses 1715system.cpu1.itb.write_hits 0 # DTB write hits 1716system.cpu1.itb.write_misses 0 # DTB write misses 1717system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1718system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1719system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1720system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 2171system.cpu1.itb.read_hits 0 # DTB read hits 2172system.cpu1.itb.read_misses 0 # DTB read misses 2173system.cpu1.itb.write_hits 0 # DTB write hits 2174system.cpu1.itb.write_misses 0 # DTB write misses 2175system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 2176system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2177system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2178system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1721system.cpu1.itb.flush_entries 1319 # Number of entries that have been flushed from TLB | 2179system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB |
| 1722system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1723system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1724system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 2180system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2181system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2182system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1725system.cpu1.itb.perms_faults 2055 # Number of TLB faults due to permissions restrictions | 2183system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions |
| 1726system.cpu1.itb.read_accesses 0 # DTB read accesses 1727system.cpu1.itb.write_accesses 0 # DTB write accesses | 2184system.cpu1.itb.read_accesses 0 # DTB read accesses 2185system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1728system.cpu1.itb.inst_accesses 8630872 # ITB inst accesses 1729system.cpu1.itb.hits 8626509 # DTB hits 1730system.cpu1.itb.misses 4363 # DTB misses 1731system.cpu1.itb.accesses 8630872 # DTB accesses 1732system.cpu1.numCycles 396849081 # number of cpu cycles simulated | 2186system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses 2187system.cpu1.itb.hits 16803682 # DTB hits 2188system.cpu1.itb.misses 6173 # DTB misses 2189system.cpu1.itb.accesses 16809855 # DTB accesses 2190system.cpu1.numCycles 436917069 # number of cpu cycles simulated |
| 1733system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1734system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 2191system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2192system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1735system.cpu1.fetch.icacheStallCycles 18444788 # Number of cycles fetch is stalled on an Icache miss 1736system.cpu1.fetch.Insts 25760845 # Number of instructions fetch has processed 1737system.cpu1.fetch.Branches 5001209 # Number of branches that fetch encountered 1738system.cpu1.fetch.predictedBranches 2723257 # Number of branches that fetch has predicted taken 1739system.cpu1.fetch.Cycles 375027882 # Number of cycles fetch has run and was not squashing or blocked 1740system.cpu1.fetch.SquashCycles 802688 # Number of cycles fetch has spent squashing 1741system.cpu1.fetch.TlbCycles 60706 # Number of cycles fetch has spent waiting for tlb 1742system.cpu1.fetch.MiscStallCycles 28139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1743system.cpu1.fetch.PendingTrapStallCycles 75697 # Number of stall cycles due to pending traps 1744system.cpu1.fetch.PendingQuiesceStallCycles 1303305 # Number of stall cycles due to pending quiesce instructions 1745system.cpu1.fetch.CacheLines 8624270 # Number of cache lines fetched 1746system.cpu1.fetch.IcacheSquashes 181619 # Number of outstanding Icache misses that were squashed 1747system.cpu1.fetch.ItlbSquashes 1774 # Number of outstanding ITLB misses that were squashed 1748system.cpu1.fetch.rateDist::samples 395341861 # Number of instructions fetched each cycle (Total) 1749system.cpu1.fetch.rateDist::mean 0.079415 # Number of instructions fetched each cycle (Total) 1750system.cpu1.fetch.rateDist::stdev 0.442124 # Number of instructions fetched each cycle (Total) | 2193system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss 2194system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed 2195system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered 2196system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken 2197system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked 2198system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing 2199system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb 2200system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2201system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps 2202system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions 2203system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR 2204system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched 2205system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed 2206system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed 2207system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total) 2208system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total) 2209system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total) |
| 1751system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 2210system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1752system.cpu1.fetch.rateDist::0 380851246 96.33% 96.33% # Number of instructions fetched each cycle (Total) 1753system.cpu1.fetch.rateDist::1 4867429 1.23% 97.57% # Number of instructions fetched each cycle (Total) 1754system.cpu1.fetch.rateDist::2 2340779 0.59% 98.16% # Number of instructions fetched each cycle (Total) 1755system.cpu1.fetch.rateDist::3 7282407 1.84% 100.00% # Number of instructions fetched each cycle (Total) | 2211system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total) 2212system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total) 2213system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total) 2214system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total) |
| 1756system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1757system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1758system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 2215system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2216system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2217system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1759system.cpu1.fetch.rateDist::total 395341861 # Number of instructions fetched each cycle (Total) 1760system.cpu1.fetch.branchRate 0.012602 # Number of branch fetches per cycle 1761system.cpu1.fetch.rate 0.064913 # Number of inst fetches per cycle 1762system.cpu1.decode.IdleCycles 15111141 # Number of cycles decode is idle 1763system.cpu1.decode.BlockedCycles 368322319 # Number of cycles decode is blocked 1764system.cpu1.decode.RunCycles 9619404 # Number of cycles decode is running 1765system.cpu1.decode.UnblockCycles 1988623 # Number of cycles decode is unblocking 1766system.cpu1.decode.SquashCycles 300374 # Number of cycles decode is squashing 1767system.cpu1.decode.BranchResolved 680085 # Number of times decode resolved a branch 1768system.cpu1.decode.BranchMispred 102949 # Number of times decode detected a branch misprediction 1769system.cpu1.decode.DecodedInsts 27336312 # Number of instructions handled by decode 1770system.cpu1.decode.SquashedInsts 828595 # Number of squashed instructions handled by decode 1771system.cpu1.rename.SquashCycles 300374 # Number of cycles rename is squashing 1772system.cpu1.rename.IdleCycles 16508550 # Number of cycles rename is idle 1773system.cpu1.rename.BlockCycles 196017158 # Number of cycles rename is blocking 1774system.cpu1.rename.serializeStallCycles 17889321 # count of cycles rename stalled for serializing inst 1775system.cpu1.rename.RunCycles 9851688 # Number of cycles rename is running 1776system.cpu1.rename.UnblockCycles 154774770 # Number of cycles rename is unblocking 1777system.cpu1.rename.RenamedInsts 26427025 # Number of instructions processed by rename 1778system.cpu1.rename.SquashedInsts 243114 # Number of squashed instructions processed by rename 1779system.cpu1.rename.ROBFullEvents 56891125 # Number of times rename has blocked due to ROB full 1780system.cpu1.rename.IQFullEvents 39780893 # Number of times rename has blocked due to IQ full 1781system.cpu1.rename.LQFullEvents 150628157 # Number of times rename has blocked due to LQ full 1782system.cpu1.rename.SQFullEvents 2138867 # Number of times rename has blocked due to SQ full 1783system.cpu1.rename.RenamedOperands 27113530 # Number of destination operands rename has renamed 1784system.cpu1.rename.RenameLookups 124075273 # Number of register rename lookups that rename has made 1785system.cpu1.rename.int_rename_lookups 31437770 # Number of integer rename lookups 1786system.cpu1.rename.fp_rename_lookups 6241 # Number of floating rename lookups 1787system.cpu1.rename.CommittedMaps 24483458 # Number of HB maps that are committed 1788system.cpu1.rename.UndoneMaps 2630072 # Number of HB maps that are undone due to squashing 1789system.cpu1.rename.serializingInsts 642693 # count of serializing insts renamed 1790system.cpu1.rename.tempSerializingInsts 559165 # count of temporary serializing insts renamed 1791system.cpu1.rename.skidInsts 4862604 # count of insts added to the skid buffer 1792system.cpu1.memDep0.insertedLoads 5657845 # Number of loads inserted to the mem dependence unit. 1793system.cpu1.memDep0.insertedStores 4330093 # Number of stores inserted to the mem dependence unit. 1794system.cpu1.memDep0.conflictingLoads 343073 # Number of conflicting loads. 1795system.cpu1.memDep0.conflictingStores 498131 # Number of conflicting stores. 1796system.cpu1.iq.iqInstsAdded 25260320 # Number of instructions added to the IQ (excludes non-spec) 1797system.cpu1.iq.iqNonSpecInstsAdded 861912 # Number of non-speculative instructions added to the IQ 1798system.cpu1.iq.iqInstsIssued 41442639 # Number of instructions issued 1799system.cpu1.iq.iqSquashedInstsIssued 78274 # Number of squashed instructions issued 1800system.cpu1.iq.iqSquashedInstsExamined 1902061 # Number of squashed instructions iterated over during squash; mainly for profiling 1801system.cpu1.iq.iqSquashedOperandsExamined 3789747 # Number of squashed operands that are examined and possibly removed from graph 1802system.cpu1.iq.iqSquashedNonSpecRemoved 92749 # Number of squashed non-spec instructions that were removed 1803system.cpu1.iq.issued_per_cycle::samples 395341861 # Number of insts issued each cycle 1804system.cpu1.iq.issued_per_cycle::mean 0.104827 # Number of insts issued each cycle 1805system.cpu1.iq.issued_per_cycle::stdev 0.383209 # Number of insts issued each cycle | 2218system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total) 2219system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle 2220system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle 2221system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle 2222system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked 2223system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running 2224system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking 2225system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing 2226system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch 2227system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction 2228system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode 2229system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode 2230system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing 2231system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle 2232system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking 2233system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst 2234system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running 2235system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking 2236system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename 2237system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename 2238system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full 2239system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full 2240system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full 2241system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full 2242system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed 2243system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made 2244system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups 2245system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups 2246system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed 2247system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing 2248system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed 2249system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed 2250system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer 2251system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit. 2252system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit. 2253system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads. 2254system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores. 2255system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec) 2256system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ 2257system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued 2258system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued 2259system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling 2260system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph 2261system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed 2262system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle 2263system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle 2264system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle |
| 1806system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 2265system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1807system.cpu1.iq.issued_per_cycle::0 362283147 91.64% 91.64% # Number of insts issued each cycle 1808system.cpu1.iq.issued_per_cycle::1 26570133 6.72% 98.36% # Number of insts issued each cycle 1809system.cpu1.iq.issued_per_cycle::2 4792582 1.21% 99.57% # Number of insts issued each cycle 1810system.cpu1.iq.issued_per_cycle::3 1496663 0.38% 99.95% # Number of insts issued each cycle 1811system.cpu1.iq.issued_per_cycle::4 199327 0.05% 100.00% # Number of insts issued each cycle 1812system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle | 2266system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle 2267system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle 2268system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle 2269system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle 2270system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle 2271system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle |
| 1813system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1814system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1815system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1816system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1817system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1818system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 2272system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2273system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2274system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2275system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2276system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2277system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1819system.cpu1.iq.issued_per_cycle::total 395341861 # Number of insts issued each cycle | 2278system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle |
| 1820system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 2279system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1821system.cpu1.iq.fu_full::IntAlu 1195141 5.96% 5.96% # attempts to use FU when none available 1822system.cpu1.iq.fu_full::IntMult 685 0.00% 5.96% # attempts to use FU when none available 1823system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.96% # attempts to use FU when none available 1824system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.96% # attempts to use FU when none available 1825system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.96% # attempts to use FU when none available 1826system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.96% # attempts to use FU when none available 1827system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.96% # attempts to use FU when none available 1828system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.96% # attempts to use FU when none available 1829system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.96% # attempts to use FU when none available 1830system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.96% # attempts to use FU when none available 1831system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.96% # attempts to use FU when none available 1832system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.96% # attempts to use FU when none available 1833system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.96% # attempts to use FU when none available 1834system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.96% # attempts to use FU when none available 1835system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.96% # attempts to use FU when none available 1836system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.96% # attempts to use FU when none available 1837system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.96% # attempts to use FU when none available 1838system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.96% # attempts to use FU when none available 1839system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.96% # attempts to use FU when none available 1840system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.96% # attempts to use FU when none available 1841system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.96% # attempts to use FU when none available 1842system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.96% # attempts to use FU when none available 1843system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.96% # attempts to use FU when none available 1844system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.96% # attempts to use FU when none available 1845system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.96% # attempts to use FU when none available 1846system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.96% # attempts to use FU when none available 1847system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.96% # attempts to use FU when none available 1848system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.96% # attempts to use FU when none available 1849system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.96% # attempts to use FU when none available 1850system.cpu1.iq.fu_full::MemRead 16909984 84.32% 90.29% # attempts to use FU when none available 1851system.cpu1.iq.fu_full::MemWrite 1947822 9.71% 100.00% # attempts to use FU when none available | 2280system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available 2281system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available 2282system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available 2283system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available 2284system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available 2285system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available 2286system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available 2287system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available 2288system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available 2289system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available 2290system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available 2291system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available 2292system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available 2293system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available 2294system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available 2295system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available 2296system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available 2297system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available 2298system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available 2299system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available 2300system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available 2301system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available 2302system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available 2303system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available 2304system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available 2305system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available 2306system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available 2307system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available 2308system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available 2309system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available 2310system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available |
| 1852system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1853system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 2311system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2312system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1854system.cpu1.iq.FU_type_0::No_OpClass 13868 0.03% 0.03% # Type of FU issued 1855system.cpu1.iq.FU_type_0::IntAlu 15563362 37.55% 37.59% # Type of FU issued 1856system.cpu1.iq.FU_type_0::IntMult 33954 0.08% 37.67% # Type of FU issued 1857system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 37.67% # Type of FU issued 1858system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 37.67% # Type of FU issued 1859system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 37.67% # Type of FU issued 1860system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 37.67% # Type of FU issued 1861system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 37.67% # Type of FU issued 1862system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 37.67% # Type of FU issued 1863system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 37.67% # Type of FU issued 1864system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 37.67% # Type of FU issued 1865system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 37.67% # Type of FU issued 1866system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 37.67% # Type of FU issued 1867system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 37.67% # Type of FU issued 1868system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 37.67% # Type of FU issued 1869system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 37.67% # Type of FU issued 1870system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 37.67% # Type of FU issued 1871system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 37.67% # Type of FU issued 1872system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 37.67% # Type of FU issued 1873system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.67% # Type of FU issued 1874system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 37.67% # Type of FU issued 1875system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.67% # Type of FU issued 1876system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.67% # Type of FU issued 1877system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.67% # Type of FU issued 1878system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.67% # Type of FU issued 1879system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.67% # Type of FU issued 1880system.cpu1.iq.FU_type_0::SimdFloatMisc 1648 0.00% 37.67% # Type of FU issued 1881system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 37.67% # Type of FU issued 1882system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.67% # Type of FU issued 1883system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.67% # Type of FU issued 1884system.cpu1.iq.FU_type_0::MemRead 21553207 52.01% 89.68% # Type of FU issued 1885system.cpu1.iq.FU_type_0::MemWrite 4276600 10.32% 100.00% # Type of FU issued | 2313system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued 2314system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued 2315system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued 2316system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued 2317system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued 2318system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued 2319system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued 2320system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued 2321system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued 2322system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued 2323system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued 2324system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued 2325system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued 2326system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued 2327system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued 2328system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued 2329system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued 2330system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued 2331system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued 2332system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued 2333system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued 2334system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued 2335system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued 2336system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued 2337system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued 2338system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued 2339system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued 2340system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued 2341system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued 2342system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued 2343system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued 2344system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued |
| 1886system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1887system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2345system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2346system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1888system.cpu1.iq.FU_type_0::total 41442639 # Type of FU issued 1889system.cpu1.iq.rate 0.104429 # Inst issue rate 1890system.cpu1.iq.fu_busy_cnt 20053632 # FU busy when requested 1891system.cpu1.iq.fu_busy_rate 0.483889 # FU busy rate (busy events/executed inst) 1892system.cpu1.iq.int_inst_queue_reads 498337881 # Number of integer instruction queue reads 1893system.cpu1.iq.int_inst_queue_writes 28019357 # Number of integer instruction queue writes 1894system.cpu1.iq.int_inst_queue_wakeup_accesses 25018416 # Number of integer instruction queue wakeup accesses 1895system.cpu1.iq.fp_inst_queue_reads 21164 # Number of floating instruction queue reads 1896system.cpu1.iq.fp_inst_queue_writes 7936 # Number of floating instruction queue writes 1897system.cpu1.iq.fp_inst_queue_wakeup_accesses 6759 # Number of floating instruction queue wakeup accesses 1898system.cpu1.iq.int_alu_accesses 61468547 # Number of integer alu accesses 1899system.cpu1.iq.fp_alu_accesses 13856 # Number of floating point alu accesses 1900system.cpu1.iew.lsq.thread0.forwLoads 72058 # Number of loads that had data forwarded from stores | 2347system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued 2348system.cpu1.iq.rate 0.149104 # Inst issue rate 2349system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested 2350system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst) 2351system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads 2352system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes 2353system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses 2354system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads 2355system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes 2356system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses 2357system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses 2358system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses 2359system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores |
| 1901system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2360system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1902system.cpu1.iew.lsq.thread0.squashedLoads 455146 # Number of loads squashed 1903system.cpu1.iew.lsq.thread0.ignoredResponses 306 # Number of memory responses ignored because the instruction is squashed 1904system.cpu1.iew.lsq.thread0.memOrderViolation 3014 # Number of memory ordering violations 1905system.cpu1.iew.lsq.thread0.squashedStores 163146 # Number of stores squashed | 2361system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed 2362system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed 2363system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations 2364system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed |
| 1906system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1907system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2365system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2366system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1908system.cpu1.iew.lsq.thread0.rescheduledLoads 15996057 # Number of loads that were rescheduled 1909system.cpu1.iew.lsq.thread0.cacheBlocked 1487 # Number of times an access to memory failed due to the cache being blocked | 2367system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled 2368system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked |
| 1910system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2369system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1911system.cpu1.iew.iewSquashCycles 300374 # Number of cycles IEW is squashing 1912system.cpu1.iew.iewBlockCycles 87167513 # Number of cycles IEW is blocking 1913system.cpu1.iew.iewUnblockCycles 92299631 # Number of cycles IEW is unblocking 1914system.cpu1.iew.iewDispatchedInsts 26204459 # Number of instructions dispatched to IQ | 2370system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing 2371system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking 2372system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking 2373system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ |
| 1915system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 2374system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 1916system.cpu1.iew.iewDispLoadInsts 5657845 # Number of dispatched load instructions 1917system.cpu1.iew.iewDispStoreInsts 4330093 # Number of dispatched store instructions 1918system.cpu1.iew.iewDispNonSpecInsts 630570 # Number of dispatched non-speculative instructions 1919system.cpu1.iew.iewIQFullEvents 9334 # Number of times the IQ has become full, causing a stall 1920system.cpu1.iew.iewLSQFullEvents 92232105 # Number of times the LSQ has become full, causing a stall 1921system.cpu1.iew.memOrderViolationEvents 3014 # Number of memory order violations 1922system.cpu1.iew.predictedTakenIncorrect 83298 # Number of branches that were predicted taken incorrectly 1923system.cpu1.iew.predictedNotTakenIncorrect 118271 # Number of branches that were predicted not taken incorrectly 1924system.cpu1.iew.branchMispredicts 201569 # Number of branch mispredicts detected at execute 1925system.cpu1.iew.iewExecutedInsts 41178523 # Number of executed instructions 1926system.cpu1.iew.iewExecLoadInsts 21441390 # Number of load instructions executed 1927system.cpu1.iew.iewExecSquashedInsts 243431 # Number of squashed instructions skipped in execute | 2375system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions 2376system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions 2377system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions 2378system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall 2379system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall 2380system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations 2381system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly 2382system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly 2383system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute 2384system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions 2385system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed 2386system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute |
| 1928system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2387system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1929system.cpu1.iew.exec_nop 82227 # number of nop insts executed 1930system.cpu1.iew.exec_refs 25682989 # number of memory reference insts executed 1931system.cpu1.iew.exec_branches 3899404 # Number of branches executed 1932system.cpu1.iew.exec_stores 4241599 # Number of stores executed 1933system.cpu1.iew.exec_rate 0.103764 # Inst execution rate 1934system.cpu1.iew.wb_sent 41086324 # cumulative count of insts sent to commit 1935system.cpu1.iew.wb_count 25025175 # cumulative count of insts written-back 1936system.cpu1.iew.wb_producers 11348419 # num instructions producing a value 1937system.cpu1.iew.wb_consumers 16538487 # num instructions consuming a value | 2388system.cpu1.iew.exec_nop 89541 # number of nop insts executed 2389system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed 2390system.cpu1.iew.exec_branches 6846575 # Number of branches executed 2391system.cpu1.iew.exec_stores 7146063 # Number of stores executed 2392system.cpu1.iew.exec_rate 0.147981 # Inst execution rate 2393system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit 2394system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back 2395system.cpu1.iew.wb_producers 25811466 # num instructions producing a value 2396system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value |
| 1938system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2397system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1939system.cpu1.iew.wb_rate 0.063060 # insts written-back per cycle 1940system.cpu1.iew.wb_fanout 0.686182 # average fanout of values written-back | 2398system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle 2399system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back |
| 1941system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2400system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1942system.cpu1.commit.commitSquashedInsts 1702265 # The number of squashed insts skipped by commit 1943system.cpu1.commit.commitNonSpecStalls 769163 # The number of times commit has been forced to stall to communicate backwards 1944system.cpu1.commit.branchMispredicts 191007 # The number of times a branch was mispredicted 1945system.cpu1.commit.committed_per_cycle::samples 394940200 # Number of insts commited each cycle 1946system.cpu1.commit.committed_per_cycle::mean 0.061056 # Number of insts commited each cycle 1947system.cpu1.commit.committed_per_cycle::stdev 0.422241 # Number of insts commited each cycle | 2401system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit 2402system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards 2403system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted 2404system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle 2405system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle 2406system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle |
| 1948system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2407system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1949system.cpu1.commit.committed_per_cycle::0 381244473 96.53% 96.53% # Number of insts commited each cycle 1950system.cpu1.commit.committed_per_cycle::1 9114140 2.31% 98.84% # Number of insts commited each cycle 1951system.cpu1.commit.committed_per_cycle::2 2236589 0.57% 99.41% # Number of insts commited each cycle 1952system.cpu1.commit.committed_per_cycle::3 955406 0.24% 99.65% # Number of insts commited each cycle 1953system.cpu1.commit.committed_per_cycle::4 446570 0.11% 99.76% # Number of insts commited each cycle 1954system.cpu1.commit.committed_per_cycle::5 403381 0.10% 99.86% # Number of insts commited each cycle 1955system.cpu1.commit.committed_per_cycle::6 181575 0.05% 99.91% # Number of insts commited each cycle 1956system.cpu1.commit.committed_per_cycle::7 97100 0.02% 99.93% # Number of insts commited each cycle 1957system.cpu1.commit.committed_per_cycle::8 260966 0.07% 100.00% # Number of insts commited each cycle | 2408system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle 2409system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle 2410system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle 2411system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle 2412system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle 2413system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle 2414system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle 2415system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle 2416system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle |
| 1958system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1959system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1960system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2417system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2418system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2419system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1961system.cpu1.commit.committed_per_cycle::total 394940200 # Number of insts commited each cycle 1962system.cpu1.commit.committedInsts 19609371 # Number of instructions committed 1963system.cpu1.commit.committedOps 24113599 # Number of ops (including micro ops) committed | 2420system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle 2421system.cpu1.commit.committedInsts 38843249 # Number of instructions committed 2422system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed |
| 1964system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2423system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1965system.cpu1.commit.refs 9369646 # Number of memory references committed 1966system.cpu1.commit.loads 5202699 # Number of loads committed 1967system.cpu1.commit.membars 162322 # Number of memory barriers committed 1968system.cpu1.commit.branches 3698878 # Number of branches committed | 2424system.cpu1.commit.refs 15740654 # Number of memory references committed 2425system.cpu1.commit.loads 8748353 # Number of loads committed 2426system.cpu1.commit.membars 195273 # Number of memory barriers committed 2427system.cpu1.commit.branches 6419002 # Number of branches committed |
| 1969system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. | 2428system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. |
| 1970system.cpu1.commit.int_insts 21204966 # Number of committed integer instructions. 1971system.cpu1.commit.function_calls 385194 # Number of function calls committed. | 2429system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions. 2430system.cpu1.commit.function_calls 553431 # Number of function calls committed. |
| 1972system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 2431system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 1973system.cpu1.commit.op_class_0::IntAlu 14709151 61.00% 61.00% # Class of committed instruction 1974system.cpu1.commit.op_class_0::IntMult 33154 0.14% 61.14% # Class of committed instruction 1975system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.14% # Class of committed instruction 1976system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.14% # Class of committed instruction 1977system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.14% # Class of committed instruction 1978system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.14% # Class of committed instruction 1979system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.14% # Class of committed instruction 1980system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.14% # Class of committed instruction 1981system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.14% # Class of committed instruction 1982system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.14% # Class of committed instruction 1983system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.14% # Class of committed instruction 1984system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.14% # Class of committed instruction 1985system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.14% # Class of committed instruction 1986system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.14% # Class of committed instruction 1987system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.14% # Class of committed instruction 1988system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.14% # Class of committed instruction 1989system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.14% # Class of committed instruction 1990system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.14% # Class of committed instruction 1991system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.14% # Class of committed instruction 1992system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.14% # Class of committed instruction 1993system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.14% # Class of committed instruction 1994system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.14% # Class of committed instruction 1995system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.14% # Class of committed instruction 1996system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.14% # Class of committed instruction 1997system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.14% # Class of committed instruction 1998system.cpu1.commit.op_class_0::SimdFloatMisc 1648 0.01% 61.14% # Class of committed instruction 1999system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.14% # Class of committed instruction 2000system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.14% # Class of committed instruction 2001system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.14% # Class of committed instruction 2002system.cpu1.commit.op_class_0::MemRead 5202699 21.58% 82.72% # Class of committed instruction 2003system.cpu1.commit.op_class_0::MemWrite 4166947 17.28% 100.00% # Class of committed instruction | 2432system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction 2433system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction 2434system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction 2435system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction 2436system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction 2437system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction 2438system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction 2439system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction 2440system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction 2441system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction 2442system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction 2443system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction 2444system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction 2445system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction 2446system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction 2447system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction 2448system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction 2449system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction 2450system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction 2451system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction 2452system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction 2453system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction 2454system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction 2455system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction 2456system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction 2457system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction 2458system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction 2459system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction 2460system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction 2461system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction 2462system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction |
| 2004system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2005system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2463system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2464system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2006system.cpu1.commit.op_class_0::total 24113599 # Class of committed instruction 2007system.cpu1.commit.bw_lim_events 260966 # number cycles where commit BW limit reached | 2465system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction 2466system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached |
| 2008system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 2467system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2009system.cpu1.rob.rob_reads 419589246 # The number of ROB reads 2010system.cpu1.rob.rob_writes 52032512 # The number of ROB writes 2011system.cpu1.timesIdled 248745 # Number of times that the entire CPU went into an idle state and unscheduled itself 2012system.cpu1.idleCycles 1507220 # Total number of cycles that the CPU has spent unscheduled due to idling 2013system.cpu1.quiesceCycles 4845699469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2014system.cpu1.committedInsts 19539732 # Number of Instructions Simulated 2015system.cpu1.committedOps 24043960 # Number of Ops (including micro ops) Simulated 2016system.cpu1.cpi 20.309853 # CPI: Cycles Per Instruction 2017system.cpu1.cpi_total 20.309853 # CPI: Total CPI of All Threads 2018system.cpu1.ipc 0.049237 # IPC: Instructions Per Cycle 2019system.cpu1.ipc_total 0.049237 # IPC: Total IPC of All Threads 2020system.cpu1.int_regfile_reads 45343306 # number of integer regfile reads 2021system.cpu1.int_regfile_writes 15599183 # number of integer regfile writes 2022system.cpu1.fp_regfile_reads 5046 # number of floating regfile reads | 2468system.cpu1.rob.rob_reads 483317632 # The number of ROB reads 2469system.cpu1.rob.rob_writes 101136219 # The number of ROB writes 2470system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself 2471system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling 2472system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2473system.cpu1.committedInsts 38773610 # Number of Instructions Simulated 2474system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated 2475system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction 2476system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads 2477system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle 2478system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads 2479system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads 2480system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes 2481system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads |
| 2023system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes | 2482system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes |
| 2024system.cpu1.cc_regfile_reads 139131439 # number of cc regfile reads 2025system.cpu1.cc_regfile_writes 9348976 # number of cc regfile writes 2026system.cpu1.misc_regfile_reads 454367618 # number of misc regfile reads 2027system.cpu1.misc_regfile_writes 623445 # number of misc regfile writes 2028system.cpu1.icache.tags.replacements 439266 # number of replacements 2029system.cpu1.icache.tags.tagsinuse 497.815366 # Cycle average of tags in use 2030system.cpu1.icache.tags.total_refs 8166304 # Total number of references to valid blocks. 2031system.cpu1.icache.tags.sampled_refs 439778 # Sample count of references to valid blocks. 2032system.cpu1.icache.tags.avg_refs 18.569151 # Average number of references to valid blocks. 2033system.cpu1.icache.tags.warmup_cycle 119618152250 # Cycle when the warmup percentage was hit. 2034system.cpu1.icache.tags.occ_blocks::cpu1.inst 497.815366 # Average occupied blocks per requestor 2035system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972296 # Average percentage of cache occupancy 2036system.cpu1.icache.tags.occ_percent::total 0.972296 # Average percentage of cache occupancy | 2483system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads 2484system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes 2485system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads 2486system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes 2487system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution 2488system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution 2489system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution 2490system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution 2491system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution 2492system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution 2493system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution 2494system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution 2495system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution 2496system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution 2497system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution 2498system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution 2499system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution 2500system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes) 2501system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes) 2502system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes) 2503system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes) 2504system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes) 2505system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes) 2506system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes) 2507system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes) 2508system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes) 2509system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes) 2510system.cpu1.toL2Bus.snoops 595717 # Total snoops (count) 2511system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram 2512system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram 2513system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram 2514system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2515system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2516system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2517system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2518system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2519system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2520system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram 2521system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram 2522system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2523system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2524system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2525system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram 2526system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks) 2527system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2528system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks) 2529system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2530system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks) 2531system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2532system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks) 2533system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 2534system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks) 2535system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2536system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks) 2537system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2538system.cpu1.icache.tags.replacements 546235 # number of replacements 2539system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use 2540system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks. 2541system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks. 2542system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks. 2543system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit. 2544system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor 2545system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy 2546system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy |
| 2037system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 2547system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 2038system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id 2039system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id | 2548system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id |
| 2040system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2549system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2041system.cpu1.icache.tags.tag_accesses 9063984 # Number of tag accesses 2042system.cpu1.icache.tags.data_accesses 9063984 # Number of data accesses 2043system.cpu1.icache.ReadReq_hits::cpu1.inst 8166304 # number of ReadReq hits 2044system.cpu1.icache.ReadReq_hits::total 8166304 # number of ReadReq hits 2045system.cpu1.icache.demand_hits::cpu1.inst 8166304 # number of demand (read+write) hits 2046system.cpu1.icache.demand_hits::total 8166304 # number of demand (read+write) hits 2047system.cpu1.icache.overall_hits::cpu1.inst 8166304 # number of overall hits 2048system.cpu1.icache.overall_hits::total 8166304 # number of overall hits 2049system.cpu1.icache.ReadReq_misses::cpu1.inst 457900 # number of ReadReq misses 2050system.cpu1.icache.ReadReq_misses::total 457900 # number of ReadReq misses 2051system.cpu1.icache.demand_misses::cpu1.inst 457900 # number of demand (read+write) misses 2052system.cpu1.icache.demand_misses::total 457900 # number of demand (read+write) misses 2053system.cpu1.icache.overall_misses::cpu1.inst 457900 # number of overall misses 2054system.cpu1.icache.overall_misses::total 457900 # number of overall misses 2055system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6264180115 # number of ReadReq miss cycles 2056system.cpu1.icache.ReadReq_miss_latency::total 6264180115 # number of ReadReq miss cycles 2057system.cpu1.icache.demand_miss_latency::cpu1.inst 6264180115 # number of demand (read+write) miss cycles 2058system.cpu1.icache.demand_miss_latency::total 6264180115 # number of demand (read+write) miss cycles 2059system.cpu1.icache.overall_miss_latency::cpu1.inst 6264180115 # number of overall miss cycles 2060system.cpu1.icache.overall_miss_latency::total 6264180115 # number of overall miss cycles 2061system.cpu1.icache.ReadReq_accesses::cpu1.inst 8624204 # number of ReadReq accesses(hits+misses) 2062system.cpu1.icache.ReadReq_accesses::total 8624204 # number of ReadReq accesses(hits+misses) 2063system.cpu1.icache.demand_accesses::cpu1.inst 8624204 # number of demand (read+write) accesses 2064system.cpu1.icache.demand_accesses::total 8624204 # number of demand (read+write) accesses 2065system.cpu1.icache.overall_accesses::cpu1.inst 8624204 # number of overall (read+write) accesses 2066system.cpu1.icache.overall_accesses::total 8624204 # number of overall (read+write) accesses 2067system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.053095 # miss rate for ReadReq accesses 2068system.cpu1.icache.ReadReq_miss_rate::total 0.053095 # miss rate for ReadReq accesses 2069system.cpu1.icache.demand_miss_rate::cpu1.inst 0.053095 # miss rate for demand accesses 2070system.cpu1.icache.demand_miss_rate::total 0.053095 # miss rate for demand accesses 2071system.cpu1.icache.overall_miss_rate::cpu1.inst 0.053095 # miss rate for overall accesses 2072system.cpu1.icache.overall_miss_rate::total 0.053095 # miss rate for overall accesses 2073system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111 # average ReadReq miss latency 2074system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111 # average ReadReq miss latency 2075system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency 2076system.cpu1.icache.demand_avg_miss_latency::total 13680.236111 # average overall miss latency 2077system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency 2078system.cpu1.icache.overall_avg_miss_latency::total 13680.236111 # average overall miss latency 2079system.cpu1.icache.blocked_cycles::no_mshrs 882 # number of cycles access was blocked 2080system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2081system.cpu1.icache.blocked::no_mshrs 53 # number of cycles access was blocked 2082system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2083system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.641509 # average number of cycles each access was blocked 2084system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2550system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses 2551system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses 2552system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits 2553system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits 2554system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits 2555system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits 2556system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits 2557system.cpu1.icache.overall_hits::total 16238797 # number of overall hits 2558system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses 2559system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses 2560system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses 2561system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses 2562system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses 2563system.cpu1.icache.overall_misses::total 562244 # number of overall misses 2564system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles 2565system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles 2566system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles 2567system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles 2568system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles 2569system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles 2570system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses) 2571system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses) 2572system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses 2573system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses 2574system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses 2575system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses 2576system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses 2577system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses 2578system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses 2579system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses 2580system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses 2581system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses 2582system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency 2583system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency 2584system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency 2585system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency 2586system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency 2587system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency 2588system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked 2589system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked 2590system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked 2591system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2592system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked 2593system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked |
| 2085system.cpu1.icache.fast_writes 0 # number of fast writes performed 2086system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2594system.cpu1.icache.fast_writes 0 # number of fast writes performed 2595system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2087system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18120 # number of ReadReq MSHR hits 2088system.cpu1.icache.ReadReq_mshr_hits::total 18120 # number of ReadReq MSHR hits 2089system.cpu1.icache.demand_mshr_hits::cpu1.inst 18120 # number of demand (read+write) MSHR hits 2090system.cpu1.icache.demand_mshr_hits::total 18120 # number of demand (read+write) MSHR hits 2091system.cpu1.icache.overall_mshr_hits::cpu1.inst 18120 # number of overall MSHR hits 2092system.cpu1.icache.overall_mshr_hits::total 18120 # number of overall MSHR hits 2093system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 439780 # number of ReadReq MSHR misses 2094system.cpu1.icache.ReadReq_mshr_misses::total 439780 # number of ReadReq MSHR misses 2095system.cpu1.icache.demand_mshr_misses::cpu1.inst 439780 # number of demand (read+write) MSHR misses 2096system.cpu1.icache.demand_mshr_misses::total 439780 # number of demand (read+write) MSHR misses 2097system.cpu1.icache.overall_mshr_misses::cpu1.inst 439780 # number of overall MSHR misses 2098system.cpu1.icache.overall_mshr_misses::total 439780 # number of overall MSHR misses 2099system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5188034078 # number of ReadReq MSHR miss cycles 2100system.cpu1.icache.ReadReq_mshr_miss_latency::total 5188034078 # number of ReadReq MSHR miss cycles 2101system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5188034078 # number of demand (read+write) MSHR miss cycles 2102system.cpu1.icache.demand_mshr_miss_latency::total 5188034078 # number of demand (read+write) MSHR miss cycles 2103system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5188034078 # number of overall MSHR miss cycles 2104system.cpu1.icache.overall_mshr_miss_latency::total 5188034078 # number of overall MSHR miss cycles 2105system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4304000 # number of ReadReq MSHR uncacheable cycles 2106system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4304000 # number of ReadReq MSHR uncacheable cycles 2107system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4304000 # number of overall MSHR uncacheable cycles 2108system.cpu1.icache.overall_mshr_uncacheable_latency::total 4304000 # number of overall MSHR uncacheable cycles 2109system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for ReadReq accesses 2110system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.050994 # mshr miss rate for ReadReq accesses 2111system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for demand accesses 2112system.cpu1.icache.demand_mshr_miss_rate::total 0.050994 # mshr miss rate for demand accesses 2113system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for overall accesses 2114system.cpu1.icache.overall_mshr_miss_rate::total 0.050994 # mshr miss rate for overall accesses 2115system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average ReadReq mshr miss latency 2116system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983 # average ReadReq mshr miss latency 2117system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency 2118system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency 2119system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency 2120system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency | 2596system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits 2597system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits 2598system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits 2599system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits 2600system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits 2601system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits 2602system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses 2603system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses 2604system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses 2605system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses 2606system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses 2607system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses 2608system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles 2609system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles 2610system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles 2611system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles 2612system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles 2613system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles 2614system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles 2615system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles 2616system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles 2617system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles 2618system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses 2619system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses 2620system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses 2621system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses 2622system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses 2623system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses 2624system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency 2625system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency 2626system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency 2627system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency 2628system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency 2629system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency |
| 2121system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2122system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2123system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2124system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2125system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2630system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2631system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2632system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2633system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2634system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2126system.cpu1.dcache.tags.replacements 227040 # number of replacements 2127system.cpu1.dcache.tags.tagsinuse 492.830733 # Cycle average of tags in use 2128system.cpu1.dcache.tags.total_refs 7082160 # Total number of references to valid blocks. 2129system.cpu1.dcache.tags.sampled_refs 227406 # Sample count of references to valid blocks. 2130system.cpu1.dcache.tags.avg_refs 31.143242 # Average number of references to valid blocks. 2131system.cpu1.dcache.tags.warmup_cycle 99092137500 # Cycle when the warmup percentage was hit. 2132system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.830733 # Average occupied blocks per requestor 2133system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962560 # Average percentage of cache occupancy 2134system.cpu1.dcache.tags.occ_percent::total 0.962560 # Average percentage of cache occupancy 2135system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id 2136system.cpu1.dcache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id 2137system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id 2138system.cpu1.dcache.tags.tag_accesses 32684037 # Number of tag accesses 2139system.cpu1.dcache.tags.data_accesses 32684037 # Number of data accesses 2140system.cpu1.dcache.ReadReq_hits::cpu1.data 3792757 # number of ReadReq hits 2141system.cpu1.dcache.ReadReq_hits::total 3792757 # number of ReadReq hits 2142system.cpu1.dcache.WriteReq_hits::cpu1.data 3094601 # number of WriteReq hits 2143system.cpu1.dcache.WriteReq_hits::total 3094601 # number of WriteReq hits 2144system.cpu1.dcache.SoftPFReq_hits::cpu1.data 14161 # number of SoftPFReq hits 2145system.cpu1.dcache.SoftPFReq_hits::total 14161 # number of SoftPFReq hits 2146system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75622 # number of LoadLockedReq hits 2147system.cpu1.dcache.LoadLockedReq_hits::total 75622 # number of LoadLockedReq hits 2148system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75613 # number of StoreCondReq hits 2149system.cpu1.dcache.StoreCondReq_hits::total 75613 # number of StoreCondReq hits 2150system.cpu1.dcache.demand_hits::cpu1.data 6887358 # number of demand (read+write) hits 2151system.cpu1.dcache.demand_hits::total 6887358 # number of demand (read+write) hits 2152system.cpu1.dcache.overall_hits::cpu1.data 6901519 # number of overall hits 2153system.cpu1.dcache.overall_hits::total 6901519 # number of overall hits 2154system.cpu1.dcache.ReadReq_misses::cpu1.data 187422 # number of ReadReq misses 2155system.cpu1.dcache.ReadReq_misses::total 187422 # number of ReadReq misses 2156system.cpu1.dcache.WriteReq_misses::cpu1.data 806941 # number of WriteReq misses 2157system.cpu1.dcache.WriteReq_misses::total 806941 # number of WriteReq misses 2158system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41483 # number of SoftPFReq misses 2159system.cpu1.dcache.SoftPFReq_misses::total 41483 # number of SoftPFReq misses 2160system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10414 # number of LoadLockedReq misses 2161system.cpu1.dcache.LoadLockedReq_misses::total 10414 # number of LoadLockedReq misses 2162system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9617 # number of StoreCondReq misses 2163system.cpu1.dcache.StoreCondReq_misses::total 9617 # number of StoreCondReq misses 2164system.cpu1.dcache.demand_misses::cpu1.data 994363 # number of demand (read+write) misses 2165system.cpu1.dcache.demand_misses::total 994363 # number of demand (read+write) misses 2166system.cpu1.dcache.overall_misses::cpu1.data 1035846 # number of overall misses 2167system.cpu1.dcache.overall_misses::total 1035846 # number of overall misses 2168system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2444126213 # number of ReadReq miss cycles 2169system.cpu1.dcache.ReadReq_miss_latency::total 2444126213 # number of ReadReq miss cycles 2170system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27779707617 # number of WriteReq miss cycles 2171system.cpu1.dcache.WriteReq_miss_latency::total 27779707617 # number of WriteReq miss cycles 2172system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 86490246 # number of LoadLockedReq miss cycles 2173system.cpu1.dcache.LoadLockedReq_miss_latency::total 86490246 # number of LoadLockedReq miss cycles 2174system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53209125 # number of StoreCondReq miss cycles 2175system.cpu1.dcache.StoreCondReq_miss_latency::total 53209125 # number of StoreCondReq miss cycles 2176system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 14000 # number of StoreCondFailReq miss cycles 2177system.cpu1.dcache.StoreCondFailReq_miss_latency::total 14000 # number of StoreCondFailReq miss cycles 2178system.cpu1.dcache.demand_miss_latency::cpu1.data 30223833830 # number of demand (read+write) miss cycles 2179system.cpu1.dcache.demand_miss_latency::total 30223833830 # number of demand (read+write) miss cycles 2180system.cpu1.dcache.overall_miss_latency::cpu1.data 30223833830 # number of overall miss cycles 2181system.cpu1.dcache.overall_miss_latency::total 30223833830 # number of overall miss cycles 2182system.cpu1.dcache.ReadReq_accesses::cpu1.data 3980179 # number of ReadReq accesses(hits+misses) 2183system.cpu1.dcache.ReadReq_accesses::total 3980179 # number of ReadReq accesses(hits+misses) 2184system.cpu1.dcache.WriteReq_accesses::cpu1.data 3901542 # number of WriteReq accesses(hits+misses) 2185system.cpu1.dcache.WriteReq_accesses::total 3901542 # number of WriteReq accesses(hits+misses) 2186system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 55644 # number of SoftPFReq accesses(hits+misses) 2187system.cpu1.dcache.SoftPFReq_accesses::total 55644 # number of SoftPFReq accesses(hits+misses) 2188system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86036 # number of LoadLockedReq accesses(hits+misses) 2189system.cpu1.dcache.LoadLockedReq_accesses::total 86036 # number of LoadLockedReq accesses(hits+misses) 2190system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85230 # number of StoreCondReq accesses(hits+misses) 2191system.cpu1.dcache.StoreCondReq_accesses::total 85230 # number of StoreCondReq accesses(hits+misses) 2192system.cpu1.dcache.demand_accesses::cpu1.data 7881721 # number of demand (read+write) accesses 2193system.cpu1.dcache.demand_accesses::total 7881721 # number of demand (read+write) accesses 2194system.cpu1.dcache.overall_accesses::cpu1.data 7937365 # number of overall (read+write) accesses 2195system.cpu1.dcache.overall_accesses::total 7937365 # number of overall (read+write) accesses 2196system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047089 # miss rate for ReadReq accesses 2197system.cpu1.dcache.ReadReq_miss_rate::total 0.047089 # miss rate for ReadReq accesses 2198system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.206826 # miss rate for WriteReq accesses 2199system.cpu1.dcache.WriteReq_miss_rate::total 0.206826 # miss rate for WriteReq accesses 2200system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745507 # miss rate for SoftPFReq accesses 2201system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745507 # miss rate for SoftPFReq accesses 2202system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121042 # miss rate for LoadLockedReq accesses 2203system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121042 # miss rate for LoadLockedReq accesses 2204system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112836 # miss rate for StoreCondReq accesses 2205system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112836 # miss rate for StoreCondReq accesses 2206system.cpu1.dcache.demand_miss_rate::cpu1.data 0.126161 # miss rate for demand accesses 2207system.cpu1.dcache.demand_miss_rate::total 0.126161 # miss rate for demand accesses 2208system.cpu1.dcache.overall_miss_rate::cpu1.data 0.130503 # miss rate for overall accesses 2209system.cpu1.dcache.overall_miss_rate::total 0.130503 # miss rate for overall accesses 2210system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761 # average ReadReq miss latency 2211system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761 # average ReadReq miss latency 2212system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404 # average WriteReq miss latency 2213system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404 # average WriteReq miss latency 2214system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8305.189745 # average LoadLockedReq miss latency 2215system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8305.189745 # average LoadLockedReq miss latency 2216system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5532.819486 # average StoreCondReq miss latency 2217system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5532.819486 # average StoreCondReq miss latency | 2635system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5063185 # number of hwpf identified 2636system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 195793 # number of hwpf that were already in mshr 2637system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4609637 # number of hwpf that were already in the cache 2638system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49643 # number of hwpf that were already in the prefetch queue 2639system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 2640system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8256 # number of hwpf removed because MSHR allocated 2641system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 199856 # number of hwpf issued 2642system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 430863 # number of hwpf spanning a virtual page 2643system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 2644system.cpu1.l2cache.tags.replacements 189917 # number of replacements 2645system.cpu1.l2cache.tags.tagsinuse 15760.362755 # Cycle average of tags in use 2646system.cpu1.l2cache.tags.total_refs 1051721 # Total number of references to valid blocks. 2647system.cpu1.l2cache.tags.sampled_refs 205349 # Sample count of references to valid blocks. 2648system.cpu1.l2cache.tags.avg_refs 5.121627 # Average number of references to valid blocks. 2649system.cpu1.l2cache.tags.warmup_cycle 2533057390500 # Cycle when the warmup percentage was hit. 2650system.cpu1.l2cache.tags.occ_blocks::writebacks 4796.141133 # Average occupied blocks per requestor 2651system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.055492 # Average occupied blocks per requestor 2652system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.249384 # Average occupied blocks per requestor 2653system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 825.564654 # Average occupied blocks per requestor 2654system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2172.411955 # Average occupied blocks per requestor 2655system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7947.940138 # Average occupied blocks per requestor 2656system.cpu1.l2cache.tags.occ_percent::writebacks 0.292733 # Average percentage of cache occupancy 2657system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001041 # Average percentage of cache occupancy 2658system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000076 # Average percentage of cache occupancy 2659system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.050388 # Average percentage of cache occupancy 2660system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132594 # Average percentage of cache occupancy 2661system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485104 # Average percentage of cache occupancy 2662system.cpu1.l2cache.tags.occ_percent::total 0.961936 # Average percentage of cache occupancy 2663system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id 2664system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 2665system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id 2666system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id 2667system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id 2668system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id 2669system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id 2670system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 2671system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id 2672system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id 2673system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id 2674system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.514404 # Percentage of cache occupancy per task id 2675system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 2676system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426880 # Percentage of cache occupancy per task id 2677system.cpu1.l2cache.tags.tag_accesses 21502320 # Number of tag accesses 2678system.cpu1.l2cache.tags.data_accesses 21502320 # Number of data accesses 2679system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29274 # number of ReadReq hits 2680system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7085 # number of ReadReq hits 2681system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535244 # number of ReadReq hits 2682system.cpu1.l2cache.ReadReq_hits::cpu1.data 196892 # number of ReadReq hits 2683system.cpu1.l2cache.ReadReq_hits::total 768495 # number of ReadReq hits 2684system.cpu1.l2cache.Writeback_hits::writebacks 291031 # number of Writeback hits 2685system.cpu1.l2cache.Writeback_hits::total 291031 # number of Writeback hits 2686system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2209 # number of UpgradeReq hits 2687system.cpu1.l2cache.UpgradeReq_hits::total 2209 # number of UpgradeReq hits 2688system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1205 # number of SCUpgradeReq hits 2689system.cpu1.l2cache.SCUpgradeReq_hits::total 1205 # number of SCUpgradeReq hits 2690system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122716 # number of ReadExReq hits 2691system.cpu1.l2cache.ReadExReq_hits::total 122716 # number of ReadExReq hits 2692system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29274 # number of demand (read+write) hits 2693system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7085 # number of demand (read+write) hits 2694system.cpu1.l2cache.demand_hits::cpu1.inst 535244 # number of demand (read+write) hits 2695system.cpu1.l2cache.demand_hits::cpu1.data 319608 # number of demand (read+write) hits 2696system.cpu1.l2cache.demand_hits::total 891211 # number of demand (read+write) hits 2697system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29274 # number of overall hits 2698system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7085 # number of overall hits 2699system.cpu1.l2cache.overall_hits::cpu1.inst 535244 # number of overall hits 2700system.cpu1.l2cache.overall_hits::cpu1.data 319608 # number of overall hits 2701system.cpu1.l2cache.overall_hits::total 891211 # number of overall hits 2702system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 364 # number of ReadReq misses 2703system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 158 # number of ReadReq misses 2704system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11361 # number of ReadReq misses 2705system.cpu1.l2cache.ReadReq_misses::cpu1.data 60780 # number of ReadReq misses 2706system.cpu1.l2cache.ReadReq_misses::total 72663 # number of ReadReq misses 2707system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses 2708system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses 2709system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20588 # number of UpgradeReq misses 2710system.cpu1.l2cache.UpgradeReq_misses::total 20588 # number of UpgradeReq misses 2711system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13188 # number of SCUpgradeReq misses 2712system.cpu1.l2cache.SCUpgradeReq_misses::total 13188 # number of SCUpgradeReq misses 2713system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2714system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 2715system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25387 # number of ReadExReq misses 2716system.cpu1.l2cache.ReadExReq_misses::total 25387 # number of ReadExReq misses 2717system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 364 # number of demand (read+write) misses 2718system.cpu1.l2cache.demand_misses::cpu1.itb.walker 158 # number of demand (read+write) misses 2719system.cpu1.l2cache.demand_misses::cpu1.inst 11361 # number of demand (read+write) misses 2720system.cpu1.l2cache.demand_misses::cpu1.data 86167 # number of demand (read+write) misses 2721system.cpu1.l2cache.demand_misses::total 98050 # number of demand (read+write) misses 2722system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 364 # number of overall misses 2723system.cpu1.l2cache.overall_misses::cpu1.itb.walker 158 # number of overall misses 2724system.cpu1.l2cache.overall_misses::cpu1.inst 11361 # number of overall misses 2725system.cpu1.l2cache.overall_misses::cpu1.data 86167 # number of overall misses 2726system.cpu1.l2cache.overall_misses::total 98050 # number of overall misses 2727system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8462000 # number of ReadReq miss cycles 2728system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3365000 # number of ReadReq miss cycles 2729system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344449975 # number of ReadReq miss cycles 2730system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612650155 # number of ReadReq miss cycles 2731system.cpu1.l2cache.ReadReq_miss_latency::total 1968927130 # number of ReadReq miss cycles 2732system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 357562229 # number of UpgradeReq miss cycles 2733system.cpu1.l2cache.UpgradeReq_miss_latency::total 357562229 # number of UpgradeReq miss cycles 2734system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267838079 # number of SCUpgradeReq miss cycles 2735system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267838079 # number of SCUpgradeReq miss cycles 2736system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1192000 # number of SCUpgradeFailReq miss cycles 2737system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1192000 # number of SCUpgradeFailReq miss cycles 2738system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1149303620 # number of ReadExReq miss cycles 2739system.cpu1.l2cache.ReadExReq_miss_latency::total 1149303620 # number of ReadExReq miss cycles 2740system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8462000 # number of demand (read+write) miss cycles 2741system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3365000 # number of demand (read+write) miss cycles 2742system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344449975 # number of demand (read+write) miss cycles 2743system.cpu1.l2cache.demand_miss_latency::cpu1.data 2761953775 # number of demand (read+write) miss cycles 2744system.cpu1.l2cache.demand_miss_latency::total 3118230750 # number of demand (read+write) miss cycles 2745system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8462000 # number of overall miss cycles 2746system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3365000 # number of overall miss cycles 2747system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344449975 # number of overall miss cycles 2748system.cpu1.l2cache.overall_miss_latency::cpu1.data 2761953775 # number of overall miss cycles 2749system.cpu1.l2cache.overall_miss_latency::total 3118230750 # number of overall miss cycles 2750system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29638 # number of ReadReq accesses(hits+misses) 2751system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7243 # number of ReadReq accesses(hits+misses) 2752system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses) 2753system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses) 2754system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses) 2755system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses) 2756system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses) 2757system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses) 2758system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses) 2759system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses) 2760system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses) 2761system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2762system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 2763system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148103 # number of ReadExReq accesses(hits+misses) 2764system.cpu1.l2cache.ReadExReq_accesses::total 148103 # number of ReadExReq accesses(hits+misses) 2765system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29638 # number of demand (read+write) accesses 2766system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7243 # number of demand (read+write) accesses 2767system.cpu1.l2cache.demand_accesses::cpu1.inst 546605 # number of demand (read+write) accesses 2768system.cpu1.l2cache.demand_accesses::cpu1.data 405775 # number of demand (read+write) accesses 2769system.cpu1.l2cache.demand_accesses::total 989261 # number of demand (read+write) accesses 2770system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29638 # number of overall (read+write) accesses 2771system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses 2772system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses 2773system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses 2774system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses 2775system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses 2776system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses 2777system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses 2778system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses 2779system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses 2780system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses 2781system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses 2782system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.903101 # miss rate for UpgradeReq accesses 2783system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.903101 # miss rate for UpgradeReq accesses 2784system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.916279 # miss rate for SCUpgradeReq accesses 2785system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.916279 # miss rate for SCUpgradeReq accesses 2786system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2787system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2788system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171414 # miss rate for ReadExReq accesses 2789system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171414 # miss rate for ReadExReq accesses 2790system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for demand accesses 2791system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.021814 # miss rate for demand accesses 2792system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020785 # miss rate for demand accesses 2793system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212352 # miss rate for demand accesses 2794system.cpu1.l2cache.demand_miss_rate::total 0.099114 # miss rate for demand accesses 2795system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for overall accesses 2796system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.021814 # miss rate for overall accesses 2797system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020785 # miss rate for overall accesses 2798system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212352 # miss rate for overall accesses 2799system.cpu1.l2cache.overall_miss_rate::total 0.099114 # miss rate for overall accesses 2800system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average ReadReq miss latency 2801system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21297.468354 # average ReadReq miss latency 2802system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency 2803system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency 2804system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency 2805system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency 2806system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency 2807system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency 2808system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency 2809system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency 2810system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency 2811system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45271.344389 # average ReadExReq miss latency 2812system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45271.344389 # average ReadExReq miss latency 2813system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency 2814system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency 2815system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency 2816system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency 2817system.cpu1.l2cache.demand_avg_miss_latency::total 31802.455380 # average overall miss latency 2818system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency 2819system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency 2820system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency 2821system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency 2822system.cpu1.l2cache.overall_avg_miss_latency::total 31802.455380 # average overall miss latency 2823system.cpu1.l2cache.blocked_cycles::no_mshrs 8115 # number of cycles access was blocked 2824system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2825system.cpu1.l2cache.blocked::no_mshrs 442 # number of cycles access was blocked 2826system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2827system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.359729 # average number of cycles each access was blocked 2828system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2829system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2830system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2831system.cpu1.l2cache.writebacks::writebacks 108849 # number of writebacks 2832system.cpu1.l2cache.writebacks::total 108849 # number of writebacks 2833system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2834system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2835system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2808 # number of ReadReq MSHR hits 2836system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 143 # number of ReadReq MSHR hits 2837system.cpu1.l2cache.ReadReq_mshr_hits::total 2953 # number of ReadReq MSHR hits 2838system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1573 # number of ReadExReq MSHR hits 2839system.cpu1.l2cache.ReadExReq_mshr_hits::total 1573 # number of ReadExReq MSHR hits 2840system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2841system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 2842system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2808 # number of demand (read+write) MSHR hits 2843system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1716 # number of demand (read+write) MSHR hits 2844system.cpu1.l2cache.demand_mshr_hits::total 4526 # number of demand (read+write) MSHR hits 2845system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2846system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 2847system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2808 # number of overall MSHR hits 2848system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1716 # number of overall MSHR hits 2849system.cpu1.l2cache.overall_mshr_hits::total 4526 # number of overall MSHR hits 2850system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 363 # number of ReadReq MSHR misses 2851system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 157 # number of ReadReq MSHR misses 2852system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8553 # number of ReadReq MSHR misses 2853system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60637 # number of ReadReq MSHR misses 2854system.cpu1.l2cache.ReadReq_mshr_misses::total 69710 # number of ReadReq MSHR misses 2855system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses 2856system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses 2857system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of HardPFReq MSHR misses 2858system.cpu1.l2cache.HardPFReq_mshr_misses::total 199848 # number of HardPFReq MSHR misses 2859system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20588 # number of UpgradeReq MSHR misses 2860system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20588 # number of UpgradeReq MSHR misses 2861system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13188 # number of SCUpgradeReq MSHR misses 2862system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13188 # number of SCUpgradeReq MSHR misses 2863system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2864system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2865system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23814 # number of ReadExReq MSHR misses 2866system.cpu1.l2cache.ReadExReq_mshr_misses::total 23814 # number of ReadExReq MSHR misses 2867system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 363 # number of demand (read+write) MSHR misses 2868system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 157 # number of demand (read+write) MSHR misses 2869system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8553 # number of demand (read+write) MSHR misses 2870system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84451 # number of demand (read+write) MSHR misses 2871system.cpu1.l2cache.demand_mshr_misses::total 93524 # number of demand (read+write) MSHR misses 2872system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 363 # number of overall MSHR misses 2873system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 157 # number of overall MSHR misses 2874system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8553 # number of overall MSHR misses 2875system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84451 # number of overall MSHR misses 2876system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of overall MSHR misses 2877system.cpu1.l2cache.overall_mshr_misses::total 293372 # number of overall MSHR misses 2878system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of ReadReq MSHR miss cycles 2879system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2254500 # number of ReadReq MSHR miss cycles 2880system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 234181256 # number of ReadReq MSHR miss cycles 2881system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1184058953 # number of ReadReq MSHR miss cycles 2882system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1426398709 # number of ReadReq MSHR miss cycles 2883system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of HardPFReq MSHR miss cycles 2884system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles 2885system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles 2886system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles 2887system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles 2888system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles 2889system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles 2890system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles 2891system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles 2892system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of ReadExReq MSHR miss cycles 2893system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles 2894system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2254500 # number of demand (read+write) MSHR miss cycles 2895system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 234181256 # number of demand (read+write) MSHR miss cycles 2896system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1874848035 # number of demand (read+write) MSHR miss cycles 2897system.cpu1.l2cache.demand_mshr_miss_latency::total 2117187791 # number of demand (read+write) MSHR miss cycles 2898system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of overall MSHR miss cycles 2899system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2254500 # number of overall MSHR miss cycles 2900system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 234181256 # number of overall MSHR miss cycles 2901system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1874848035 # number of overall MSHR miss cycles 2902system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles 2903system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles 2904system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles 2905system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles 2906system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles 2907system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles 2908system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles 2909system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles 2910system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204307878917 # number of overall MSHR uncacheable cycles 2911system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204312450917 # number of overall MSHR uncacheable cycles 2912system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for ReadReq accesses 2913system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for ReadReq accesses 2914system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for ReadReq accesses 2915system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.235326 # mshr miss rate for ReadReq accesses 2916system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082874 # mshr miss rate for ReadReq accesses 2917system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses 2918system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses 2919system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2920system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2921system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.903101 # mshr miss rate for UpgradeReq accesses 2922system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.903101 # mshr miss rate for UpgradeReq accesses 2923system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.916279 # mshr miss rate for SCUpgradeReq accesses 2924system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916279 # mshr miss rate for SCUpgradeReq accesses 2925system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2926system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2927system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160794 # mshr miss rate for ReadExReq accesses 2928system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160794 # mshr miss rate for ReadExReq accesses 2929system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for demand accesses 2930system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for demand accesses 2931system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for demand accesses 2932system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for demand accesses 2933system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094539 # mshr miss rate for demand accesses 2934system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for overall accesses 2935system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for overall accesses 2936system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for overall accesses 2937system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for overall accesses 2938system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2939system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses 2940system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency 2941system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency 2942system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency 2943system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency 2944system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency 2945system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency 2946system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency 2947system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency 2948system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency 2949system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency 2950system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency 2951system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency 2952system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency 2953system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency 2954system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency 2955system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency 2956system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency 2957system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency 2958system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency 2959system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22637.908890 # average overall mshr miss latency 2960system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency 2961system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency 2962system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency 2963system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency 2964system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency 2965system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency 2966system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2967system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2968system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2969system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2970system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2971system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2972system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2973system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2974system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2975system.cpu1.dcache.tags.replacements 381661 # number of replacements 2976system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use 2977system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks. 2978system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks. 2979system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks. 2980system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit. 2981system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor 2982system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940978 # Average percentage of cache occupancy 2983system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy 2984system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 2985system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id 2986system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id 2987system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses 2988system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses 2989system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits 2990system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits 2991system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits 2992system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits 2993system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits 2994system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits 2995system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits 2996system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits 2997system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits 2998system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits 2999system.cpu1.dcache.demand_hits::cpu1.data 12063851 # number of demand (read+write) hits 3000system.cpu1.dcache.demand_hits::total 12063851 # number of demand (read+write) hits 3001system.cpu1.dcache.overall_hits::cpu1.data 12088353 # number of overall hits 3002system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits 3003system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses 3004system.cpu1.dcache.ReadReq_misses::total 362275 # number of ReadReq misses 3005system.cpu1.dcache.WriteReq_misses::cpu1.data 967298 # number of WriteReq misses 3006system.cpu1.dcache.WriteReq_misses::total 967298 # number of WriteReq misses 3007system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses 3008system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses 3009system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses 3010system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses 3011system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses 3012system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses 3013system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses 3014system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses 3015system.cpu1.dcache.overall_misses::cpu1.data 1377109 # number of overall misses 3016system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses 3017system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles 3018system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles 3019system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles 3020system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles 3021system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles 3022system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles 3023system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles 3024system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles 3025system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles 3026system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles 3027system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles 3028system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles 3029system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles 3030system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles 3031system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses) 3032system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses) 3033system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses) 3034system.cpu1.dcache.WriteReq_accesses::total 5825520 # number of WriteReq accesses(hits+misses) 3035system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 72038 # number of SoftPFReq accesses(hits+misses) 3036system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses) 3037system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses) 3038system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses) 3039system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses) 3040system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses) 3041system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses 3042system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses 3043system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses 3044system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses 3045system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses 3046system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses 3047system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses 3048system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses 3049system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses 3050system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses 3051system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses 3052system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses 3053system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses 3054system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses 3055system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses 3056system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses 3057system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses 3058system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses 3059system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency 3060system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency 3061system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency 3062system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency 3063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency 3064system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency 3065system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency 3066system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency |
| 2218system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2219system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 3067system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 3068system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2220system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411 # average overall miss latency 2221system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411 # average overall miss latency 2222system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037 # average overall miss latency 2223system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037 # average overall miss latency 2224system.cpu1.dcache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked 2225system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2226system.cpu1.dcache.blocked::no_mshrs 723 # number of cycles access was blocked 2227system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2228system.cpu1.dcache.avg_blocked_cycles::no_mshrs 6.190871 # average number of cycles each access was blocked 2229system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 3069system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency 3070system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency 3071system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency 3072system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency 3073system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked 3074system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked 3075system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked 3076system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked 3077system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked 3078system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked |
| 2230system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2231system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 3079system.cpu1.dcache.fast_writes 0 # number of fast writes performed 3080system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2232system.cpu1.dcache.writebacks::writebacks 207281 # number of writebacks 2233system.cpu1.dcache.writebacks::total 207281 # number of writebacks 2234system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 70540 # number of ReadReq MSHR hits 2235system.cpu1.dcache.ReadReq_mshr_hits::total 70540 # number of ReadReq MSHR hits 2236system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 693700 # number of WriteReq MSHR hits 2237system.cpu1.dcache.WriteReq_mshr_hits::total 693700 # number of WriteReq MSHR hits 2238system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 500 # number of LoadLockedReq MSHR hits 2239system.cpu1.dcache.LoadLockedReq_mshr_hits::total 500 # number of LoadLockedReq MSHR hits 2240system.cpu1.dcache.demand_mshr_hits::cpu1.data 764240 # number of demand (read+write) MSHR hits 2241system.cpu1.dcache.demand_mshr_hits::total 764240 # number of demand (read+write) MSHR hits 2242system.cpu1.dcache.overall_mshr_hits::cpu1.data 764240 # number of overall MSHR hits 2243system.cpu1.dcache.overall_mshr_hits::total 764240 # number of overall MSHR hits 2244system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116882 # number of ReadReq MSHR misses 2245system.cpu1.dcache.ReadReq_mshr_misses::total 116882 # number of ReadReq MSHR misses 2246system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 113241 # number of WriteReq MSHR misses 2247system.cpu1.dcache.WriteReq_mshr_misses::total 113241 # number of WriteReq MSHR misses 2248system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23891 # number of SoftPFReq MSHR misses 2249system.cpu1.dcache.SoftPFReq_mshr_misses::total 23891 # number of SoftPFReq MSHR misses 2250system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9914 # number of LoadLockedReq MSHR misses 2251system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9914 # number of LoadLockedReq MSHR misses 2252system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9617 # number of StoreCondReq MSHR misses 2253system.cpu1.dcache.StoreCondReq_mshr_misses::total 9617 # number of StoreCondReq MSHR misses 2254system.cpu1.dcache.demand_mshr_misses::cpu1.data 230123 # number of demand (read+write) MSHR misses 2255system.cpu1.dcache.demand_mshr_misses::total 230123 # number of demand (read+write) MSHR misses 2256system.cpu1.dcache.overall_mshr_misses::cpu1.data 254014 # number of overall MSHR misses 2257system.cpu1.dcache.overall_mshr_misses::total 254014 # number of overall MSHR misses 2258system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203808322 # number of ReadReq MSHR miss cycles 2259system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203808322 # number of ReadReq MSHR miss cycles 2260system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3988299754 # number of WriteReq MSHR miss cycles 2261system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3988299754 # number of WriteReq MSHR miss cycles 2262system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 341716536 # number of SoftPFReq MSHR miss cycles 2263system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 341716536 # number of SoftPFReq MSHR miss cycles 2264system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60834504 # number of LoadLockedReq MSHR miss cycles 2265system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 60834504 # number of LoadLockedReq MSHR miss cycles 2266system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33974875 # number of StoreCondReq MSHR miss cycles 2267system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33974875 # number of StoreCondReq MSHR miss cycles 2268system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 12000 # number of StoreCondFailReq MSHR miss cycles 2269system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 12000 # number of StoreCondFailReq MSHR miss cycles 2270system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5192108076 # number of demand (read+write) MSHR miss cycles 2271system.cpu1.dcache.demand_mshr_miss_latency::total 5192108076 # number of demand (read+write) MSHR miss cycles 2272system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5533824612 # number of overall MSHR miss cycles 2273system.cpu1.dcache.overall_mshr_miss_latency::total 5533824612 # number of overall MSHR miss cycles 2274system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758 # number of ReadReq MSHR uncacheable cycles 2275system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758 # number of ReadReq MSHR uncacheable cycles 2276system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 522517625 # number of WriteReq MSHR uncacheable cycles 2277system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 522517625 # number of WriteReq MSHR uncacheable cycles 2278system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383 # number of overall MSHR uncacheable cycles 2279system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383 # number of overall MSHR uncacheable cycles 2280system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029366 # mshr miss rate for ReadReq accesses 2281system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029366 # mshr miss rate for ReadReq accesses 2282system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029025 # mshr miss rate for WriteReq accesses 2283system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029025 # mshr miss rate for WriteReq accesses 2284system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.429354 # mshr miss rate for SoftPFReq accesses 2285system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.429354 # mshr miss rate for SoftPFReq accesses 2286system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.115231 # mshr miss rate for LoadLockedReq accesses 2287system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.115231 # mshr miss rate for LoadLockedReq accesses 2288system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112836 # mshr miss rate for StoreCondReq accesses 2289system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112836 # mshr miss rate for StoreCondReq accesses 2290system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029197 # mshr miss rate for demand accesses 2291system.cpu1.dcache.demand_mshr_miss_rate::total 0.029197 # mshr miss rate for demand accesses 2292system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032002 # mshr miss rate for overall accesses 2293system.cpu1.dcache.overall_mshr_miss_rate::total 0.032002 # mshr miss rate for overall accesses 2294system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393 # average ReadReq mshr miss latency 2295system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393 # average ReadReq mshr miss latency 2296system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776 # average WriteReq mshr miss latency 2297system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776 # average WriteReq mshr miss latency 2298system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136 # average SoftPFReq mshr miss latency 2299system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136 # average SoftPFReq mshr miss latency 2300system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6136.221908 # average LoadLockedReq mshr miss latency 2301system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6136.221908 # average LoadLockedReq mshr miss latency 2302system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3532.793491 # average StoreCondReq mshr miss latency 2303system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3532.793491 # average StoreCondReq mshr miss latency | 3081system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks 3082system.cpu1.dcache.writebacks::total 291033 # number of writebacks 3083system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits 3084system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits 3085system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits 3086system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits 3087system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits 3088system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits 3089system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits 3090system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits 3091system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits 3092system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits 3093system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses 3094system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses 3095system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses 3096system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses 3097system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses 3098system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses 3099system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses 3100system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses 3101system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses 3102system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses 3103system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses 3104system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses 3105system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses 3106system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses 3107system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles 3108system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles 3109system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles 3110system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles 3111system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles 3112system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles 3113system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles 3114system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles 3115system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles 3116system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles 3117system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles 3118system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles 3119system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles 3120system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles 3121system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles 3122system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles 3123system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles 3124system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles 3125system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles 3126system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles 3127system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles 3128system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles 3129system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses 3130system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses 3131system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses 3132system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses 3133system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses 3134system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses 3135system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses 3136system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses 3137system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses 3138system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses 3139system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses 3140system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses 3141system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses 3142system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses 3143system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency 3144system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency 3145system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency 3146system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency 3147system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency 3148system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency 3149system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency 3150system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency 3151system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency 3152system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency |
| 2304system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2305system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 3153system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 3154system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2306system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004 # average overall mshr miss latency 2307system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004 # average overall mshr miss latency 2308system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295 # average overall mshr miss latency 2309system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295 # average overall mshr miss latency | 3155system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency 3156system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency 3157system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency 3158system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency |
| 2310system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2311system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2312system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2313system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2314system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2315system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2316system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2317system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 2325system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2326system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2327system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2328system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2329system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2330system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2331system.iocache.fast_writes 0 # number of fast writes performed 2332system.iocache.cache_copies 0 # number of cache copies performed | 3159system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3160system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3161system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3162system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3163system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3164system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3165system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3166system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 3174system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3175system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3176system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3177system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3178system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3179system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3180system.iocache.fast_writes 0 # number of fast writes performed 3181system.iocache.cache_copies 0 # number of cache copies performed |
| 2333system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of ReadReq MSHR uncacheable cycles 2334system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303 # number of ReadReq MSHR uncacheable cycles 2335system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of overall MSHR uncacheable cycles 2336system.iocache.overall_mshr_uncacheable_latency::total 1736665659303 # number of overall MSHR uncacheable cycles | 3182system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles 3183system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles 3184system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles 3185system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles |
| 2337system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2338system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2339system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2340system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2341system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2342system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 3186system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 3187system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3188system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 3189system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3190system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3191system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 2343system.cpu0.kern.inst.quiesce 52427 # number of quiesce instructions executed | 3192system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed |
| 2344system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3193system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 2345system.cpu1.kern.inst.quiesce 40685 # number of quiesce instructions executed | 3194system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed |
| 2346 2347---------- End Simulation Statistics ---------- | 3195 3196---------- End Simulation Statistics ---------- |