| stats.txt (10038:7eccd14e2610) | stats.txt (10072:fa5c8a8a7bab) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.605645 # Number of seconds simulated 4sim_ticks 2605645191500 # Number of ticks simulated 5final_tick 2605645191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.605623 # Number of seconds simulated 4sim_ticks 2605623216500 # Number of ticks simulated 5final_tick 2605623216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 69894 # Simulator instruction rate (inst/s) 8host_op_rate 90000 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2899968268 # Simulator tick rate (ticks/s) 10host_mem_usage 430484 # Number of bytes of host memory used 11host_seconds 898.51 # Real time elapsed on the host 12sim_insts 62800764 # Number of instructions simulated 13sim_ops 80866121 # Number of ops (including micro ops) simulated | 7host_inst_rate 60428 # Simulator instruction rate (inst/s) 8host_op_rate 77810 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2507107577 # Simulator tick rate (ticks/s) 10host_mem_usage 430512 # Number of bytes of host memory used 11host_seconds 1039.29 # Real time elapsed on the host 12sim_insts 62801984 # Number of instructions simulated 13sim_ops 80867321 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu0.inst 392704 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 4367548 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 428032 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 5265336 # Number of bytes read from this memory 24system.physmem.bytes_read::total 131566132 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 392704 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 428032 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 820736 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 4282176 # Number of bytes written to this memory | 19system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 4350396 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 426880 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 5253880 # Number of bytes read from this memory 24system.physmem.bytes_read::total 131538740 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 426880 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 821888 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 4261184 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory | 29system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::total 7311312 # Number of bytes written to this memory | 31system.physmem.bytes_written::total 7290320 # Number of bytes written to this memory |
| 32system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.inst 6136 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 68317 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6688 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 82299 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15302287 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66909 # Number of write requests responded to by this memory | 35system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 68049 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6670 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15301859 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66581 # Number of write requests responded to by this memory |
| 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory | 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory |
| 44system.physmem.num_writes::total 824193 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46480054 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.num_writes::total 823865 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46480446 # Total read bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_read::cpu0.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu0.inst 150713 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 1676187 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 164271 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 2020742 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50492727 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 150713 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 164271 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 314984 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 1643423 # Write bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu0.inst 151598 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 1669618 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 163830 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 2016362 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50482640 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 151598 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 163830 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 315429 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 1635380 # Write bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) | 58system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::total 2805951 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 1643423 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::realview.clcd 46480054 # Total bandwidth to/from this memory (bytes/s) | 59system.physmem.bw_write::cpu1.data 1156014 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::total 2797918 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 1635380 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::realview.clcd 46480446 # Total bandwidth to/from this memory (bytes/s) |
| 63system.physmem.bw_total::cpu0.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::cpu0.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) |
| 65system.physmem.bw_total::cpu0.inst 150713 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 1682711 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 164271 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 3176746 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 53298678 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 15302287 # Number of read requests accepted 72system.physmem.writeReqs 824193 # Number of write requests accepted 73system.physmem.readBursts 15302287 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 824193 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 976879168 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 2467200 # Total number of bytes read from write queue 77system.physmem.bytesWritten 7418176 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 131566132 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 7311312 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 38550 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 708272 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 956326 # Per bank write bursts 84system.physmem.perBankRdBursts::1 956081 # Per bank write bursts 85system.physmem.perBankRdBursts::2 952133 # Per bank write bursts 86system.physmem.perBankRdBursts::3 952389 # Per bank write bursts 87system.physmem.perBankRdBursts::4 956868 # Per bank write bursts 88system.physmem.perBankRdBursts::5 956262 # Per bank write bursts 89system.physmem.perBankRdBursts::6 951633 # Per bank write bursts 90system.physmem.perBankRdBursts::7 951532 # Per bank write bursts 91system.physmem.perBankRdBursts::8 956738 # Per bank write bursts 92system.physmem.perBankRdBursts::9 956585 # Per bank write bursts 93system.physmem.perBankRdBursts::10 951315 # Per bank write bursts 94system.physmem.perBankRdBursts::11 950633 # Per bank write bursts 95system.physmem.perBankRdBursts::12 956323 # Per bank write bursts 96system.physmem.perBankRdBursts::13 956319 # Per bank write bursts 97system.physmem.perBankRdBursts::14 951484 # Per bank write bursts 98system.physmem.perBankRdBursts::15 951116 # Per bank write bursts 99system.physmem.perBankWrBursts::0 7149 # Per bank write bursts 100system.physmem.perBankWrBursts::1 7007 # Per bank write bursts 101system.physmem.perBankWrBursts::2 7292 # Per bank write bursts 102system.physmem.perBankWrBursts::3 7274 # Per bank write bursts 103system.physmem.perBankWrBursts::4 7928 # Per bank write bursts 104system.physmem.perBankWrBursts::5 7489 # Per bank write bursts 105system.physmem.perBankWrBursts::6 7090 # Per bank write bursts 106system.physmem.perBankWrBursts::7 7095 # Per bank write bursts 107system.physmem.perBankWrBursts::8 7536 # Per bank write bursts 108system.physmem.perBankWrBursts::9 7648 # Per bank write bursts 109system.physmem.perBankWrBursts::10 6979 # Per bank write bursts 110system.physmem.perBankWrBursts::11 6633 # Per bank write bursts 111system.physmem.perBankWrBursts::12 7251 # Per bank write bursts 112system.physmem.perBankWrBursts::13 7189 # Per bank write bursts 113system.physmem.perBankWrBursts::14 7290 # Per bank write bursts 114system.physmem.perBankWrBursts::15 7059 # Per bank write bursts | 65system.physmem.bw_total::cpu0.inst 151598 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 1676143 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 163830 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 3172376 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 53280558 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 15301859 # Number of read requests accepted 72system.physmem.writeReqs 823865 # Number of write requests accepted 73system.physmem.readBursts 15301859 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 823865 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 976840512 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 2478464 # Total number of bytes read from write queue 77system.physmem.bytesWritten 7393984 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 131538740 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 7290320 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 38726 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 708315 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 14211 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 956322 # Per bank write bursts 84system.physmem.perBankRdBursts::1 955904 # Per bank write bursts 85system.physmem.perBankRdBursts::2 952374 # Per bank write bursts 86system.physmem.perBankRdBursts::3 952254 # Per bank write bursts 87system.physmem.perBankRdBursts::4 956762 # Per bank write bursts 88system.physmem.perBankRdBursts::5 955994 # Per bank write bursts 89system.physmem.perBankRdBursts::6 951679 # Per bank write bursts 90system.physmem.perBankRdBursts::7 951390 # Per bank write bursts 91system.physmem.perBankRdBursts::8 956653 # Per bank write bursts 92system.physmem.perBankRdBursts::9 956558 # Per bank write bursts 93system.physmem.perBankRdBursts::10 951325 # Per bank write bursts 94system.physmem.perBankRdBursts::11 950816 # Per bank write bursts 95system.physmem.perBankRdBursts::12 956256 # Per bank write bursts 96system.physmem.perBankRdBursts::13 956091 # Per bank write bursts 97system.physmem.perBankRdBursts::14 951432 # Per bank write bursts 98system.physmem.perBankRdBursts::15 951323 # Per bank write bursts 99system.physmem.perBankWrBursts::0 7131 # Per bank write bursts 100system.physmem.perBankWrBursts::1 6969 # Per bank write bursts 101system.physmem.perBankWrBursts::2 7487 # Per bank write bursts 102system.physmem.perBankWrBursts::3 7380 # Per bank write bursts 103system.physmem.perBankWrBursts::4 7843 # Per bank write bursts 104system.physmem.perBankWrBursts::5 7402 # Per bank write bursts 105system.physmem.perBankWrBursts::6 7084 # Per bank write bursts 106system.physmem.perBankWrBursts::7 7084 # Per bank write bursts 107system.physmem.perBankWrBursts::8 7461 # Per bank write bursts 108system.physmem.perBankWrBursts::9 7519 # Per bank write bursts 109system.physmem.perBankWrBursts::10 6987 # Per bank write bursts 110system.physmem.perBankWrBursts::11 6657 # Per bank write bursts 111system.physmem.perBankWrBursts::12 7185 # Per bank write bursts 112system.physmem.perBankWrBursts::13 7089 # Per bank write bursts 113system.physmem.perBankWrBursts::14 7212 # Per bank write bursts 114system.physmem.perBankWrBursts::15 7041 # Per bank write bursts |
| 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 117system.physmem.totGap 2605643958000 # Total gap between requests | 117system.physmem.totGap 2605622062000 # Total gap between requests |
| 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 109 # Read request sizes (log2) 121system.physmem.readPktSize::3 15138816 # Read request sizes (log2) 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) | 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 109 # Read request sizes (log2) 121system.physmem.readPktSize::3 15138816 # Read request sizes (log2) 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 124system.physmem.readPktSize::6 163362 # Read request sizes (log2) | 124system.physmem.readPktSize::6 162934 # Read request sizes (log2) |
| 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 757284 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) | 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 757284 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 131system.physmem.writePktSize::6 66909 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 1182621 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 1128295 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 1080999 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 3674790 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 2650191 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 2638240 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 2645126 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 56320 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 60148 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 21515 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 21310 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 21179 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 20896 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 20716 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 20584 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 20486 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::16 211 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::18 7 # What read queue length does an incoming req see | 131system.physmem.writePktSize::6 66581 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 1184108 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 1129171 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 1082709 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 3674312 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 2649053 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 2636381 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 2643445 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 56452 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 60541 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 21670 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 21240 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 21122 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 20880 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 20711 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 20560 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 20478 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::16 196 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see |
| 151system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see | 151system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see |
| 152system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see | 152system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see |
| 153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::0 5125 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 5806 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 5252 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 5476 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 5561 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 5241 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 5234 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 5253 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 5193 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 5153 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 5143 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 5152 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 5154 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::15 5149 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 5149 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 5172 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 5172 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 5585 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 163 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see | 164system.physmem.wrQLenPdf::0 5109 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 5790 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 5234 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 5460 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 5588 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 5210 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 5203 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 5223 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 5160 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 5157 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 5138 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 5130 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 5134 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 5143 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::15 5144 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 5140 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 5173 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 5188 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 5156 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 5520 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 156 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 71 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see |
| 190system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 190system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 91629 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 10742.195593 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 915.011801 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 16529.689653 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::64-71 25868 28.23% 28.23% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-135 14885 16.24% 44.48% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::192-199 3175 3.47% 47.94% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-263 2307 2.52% 50.46% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::320-327 1552 1.69% 52.15% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::384-391 1265 1.38% 53.53% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::448-455 967 1.06% 54.59% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::512-519 1319 1.44% 56.03% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::576-583 664 0.72% 56.75% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-647 632 0.69% 57.44% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::704-711 552 0.60% 58.04% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-775 612 0.67% 58.71% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::832-839 295 0.32% 59.03% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::896-903 299 0.33% 59.36% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::960-967 170 0.19% 59.55% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1024-1031 591 0.64% 60.19% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1088-1095 145 0.16% 60.35% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1152-1159 120 0.13% 60.48% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1216-1223 94 0.10% 60.58% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1280-1287 139 0.15% 60.74% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1344-1351 69 0.08% 60.81% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1408-1415 555 0.61% 61.42% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1472-1479 36 0.04% 61.46% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1536-1543 297 0.32% 61.78% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1600-1607 26 0.03% 61.81% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1664-1671 93 0.10% 61.91% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1728-1735 18 0.02% 61.93% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1792-1799 171 0.19% 62.12% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1856-1863 18 0.02% 62.14% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::1920-1927 53 0.06% 62.19% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::1984-1991 22 0.02% 62.22% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2048-2055 386 0.42% 62.64% # Bytes accessed per row activation | 196system.physmem.bytesPerActivate::samples 91489 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 10757.948868 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 916.821036 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 16539.903542 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::64-71 25786 28.18% 28.18% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-135 14910 16.30% 44.48% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::192-199 3164 3.46% 47.94% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-263 2339 2.56% 50.50% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::320-327 1506 1.65% 52.14% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::384-391 1246 1.36% 53.50% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::448-455 1021 1.12% 54.62% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::512-519 1185 1.30% 55.92% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::576-583 667 0.73% 56.65% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-647 658 0.72% 57.36% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::704-711 602 0.66% 58.02% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-775 572 0.63% 58.65% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::832-839 315 0.34% 58.99% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::896-903 283 0.31% 59.30% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::960-967 170 0.19% 59.49% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1024-1031 580 0.63% 60.12% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1088-1095 115 0.13% 60.25% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1152-1159 145 0.16% 60.41% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1216-1223 84 0.09% 60.50% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1280-1287 210 0.23% 60.73% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1344-1351 59 0.06% 60.79% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1408-1415 551 0.60% 61.39% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1472-1479 52 0.06% 61.45% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1536-1543 273 0.30% 61.75% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1600-1607 29 0.03% 61.78% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1664-1671 104 0.11% 61.89% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1728-1735 17 0.02% 61.91% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1792-1799 169 0.18% 62.10% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1856-1863 21 0.02% 62.12% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::1920-1927 56 0.06% 62.18% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::1984-1991 21 0.02% 62.20% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2048-2055 399 0.44% 62.64% # Bytes accessed per row activation |
| 232system.physmem.bytesPerActivate::2112-2119 9 0.01% 62.65% # Bytes accessed per row activation | 232system.physmem.bytesPerActivate::2112-2119 9 0.01% 62.65% # Bytes accessed per row activation |
| 233system.physmem.bytesPerActivate::2176-2183 41 0.04% 62.69% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2240-2247 10 0.01% 62.70% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2304-2311 62 0.07% 62.77% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2368-2375 6 0.01% 62.78% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2432-2439 32 0.03% 62.81% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2496-2503 10 0.01% 62.82% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2560-2567 171 0.19% 63.01% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2624-2631 4 0.00% 63.01% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2688-2695 16 0.02% 63.03% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2752-2759 7 0.01% 63.04% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2816-2823 87 0.09% 63.14% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::2880-2887 9 0.01% 63.14% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::2944-2951 23 0.03% 63.17% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3008-3015 8 0.01% 63.18% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3072-3079 355 0.39% 63.57% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3136-3143 3 0.00% 63.57% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3200-3207 16 0.02% 63.59% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3264-3271 6 0.01% 63.59% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3328-3335 101 0.11% 63.70% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3392-3399 10 0.01% 63.71% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3456-3463 14 0.02% 63.73% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3520-3527 7 0.01% 63.74% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3584-3591 93 0.10% 63.84% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3648-3655 11 0.01% 63.85% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3712-3719 22 0.02% 63.87% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3776-3783 7 0.01% 63.88% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3840-3847 109 0.12% 64.00% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::3904-3911 11 0.01% 64.01% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::3968-3975 14 0.02% 64.03% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4032-4039 9 0.01% 64.04% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4096-4103 384 0.42% 64.46% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4160-4167 10 0.01% 64.47% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4224-4231 16 0.02% 64.49% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4288-4295 6 0.01% 64.49% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4352-4359 99 0.11% 64.60% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4416-4423 15 0.02% 64.62% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4480-4487 11 0.01% 64.63% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4544-4551 7 0.01% 64.64% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4608-4615 45 0.05% 64.69% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4672-4679 4 0.00% 64.69% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4736-4743 10 0.01% 64.70% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4800-4807 11 0.01% 64.71% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::4864-4871 152 0.17% 64.88% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::4928-4935 9 0.01% 64.89% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::4992-4999 16 0.02% 64.91% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5056-5063 3 0.00% 64.91% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5120-5127 484 0.53% 65.44% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5184-5191 5 0.01% 65.44% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5248-5255 12 0.01% 65.46% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5312-5319 8 0.01% 65.47% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5376-5383 12 0.01% 65.48% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5440-5447 6 0.01% 65.48% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5504-5511 6 0.01% 65.49% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::5568-5575 3 0.00% 65.49% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::5632-5639 100 0.11% 65.60% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::5696-5703 6 0.01% 65.61% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::5760-5767 10 0.01% 65.62% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::5824-5831 6 0.01% 65.63% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::5888-5895 142 0.15% 65.78% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::5952-5959 4 0.00% 65.79% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6016-6023 15 0.02% 65.80% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6080-6087 4 0.00% 65.81% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6144-6151 300 0.33% 66.14% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6208-6215 4 0.00% 66.14% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::6272-6279 14 0.02% 66.15% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::6336-6343 2 0.00% 66.16% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::6400-6407 89 0.10% 66.25% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::6464-6471 2 0.00% 66.26% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::6528-6535 8 0.01% 66.27% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::6592-6599 1 0.00% 66.27% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::6656-6663 160 0.17% 66.44% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::6720-6727 7 0.01% 66.45% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::6784-6791 20 0.02% 66.47% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::6848-6855 7 0.01% 66.48% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::6912-6919 31 0.03% 66.51% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::6976-6983 3 0.00% 66.51% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7040-7047 11 0.01% 66.53% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::7104-7111 4 0.00% 66.53% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::7168-7175 463 0.51% 67.04% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::7232-7239 3 0.00% 67.04% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::7296-7303 5 0.01% 67.05% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::7360-7367 6 0.01% 67.05% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::7424-7431 163 0.18% 67.23% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::7488-7495 4 0.00% 67.23% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::7552-7559 11 0.01% 67.25% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::7616-7623 5 0.01% 67.25% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::7680-7687 15 0.02% 67.27% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::7744-7751 1 0.00% 67.27% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::7808-7815 2 0.00% 67.27% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::7872-7879 1 0.00% 67.27% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::7936-7943 91 0.10% 67.37% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::8000-8007 6 0.01% 67.38% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::8064-8071 9 0.01% 67.39% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::8128-8135 1 0.00% 67.39% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::8192-8199 397 0.43% 67.82% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::8320-8327 1 0.00% 67.82% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::8384-8391 1 0.00% 67.82% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::8448-8455 85 0.09% 67.92% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::8512-8519 1 0.00% 67.92% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::8576-8583 2 0.00% 67.92% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::8704-8711 6 0.01% 67.93% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::8768-8775 1 0.00% 67.93% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::8832-8839 2 0.00% 67.93% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::8960-8967 154 0.17% 68.10% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::9088-9095 3 0.00% 68.10% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::9152-9159 1 0.00% 68.10% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::9216-9223 460 0.50% 68.60% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::9472-9479 24 0.03% 68.63% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::9536-9543 1 0.00% 68.63% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::9600-9607 5 0.01% 68.64% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::9728-9735 143 0.16% 68.79% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::9792-9799 1 0.00% 68.79% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::9856-9863 1 0.00% 68.80% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::9920-9927 1 0.00% 68.80% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::9984-9991 82 0.09% 68.89% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::10112-10119 1 0.00% 68.89% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::10240-10247 282 0.31% 69.20% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::10304-10311 1 0.00% 69.20% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::10432-10439 1 0.00% 69.20% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::10496-10503 93 0.10% 69.30% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::10560-10567 2 0.00% 69.30% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::10624-10631 1 0.00% 69.30% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::10688-10695 2 0.00% 69.30% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::10752-10759 93 0.10% 69.41% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::10816-10823 1 0.00% 69.41% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::11008-11015 7 0.01% 69.41% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::11136-11143 2 0.00% 69.42% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::11200-11207 1 0.00% 69.42% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::11264-11271 476 0.52% 69.94% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::11328-11335 1 0.00% 69.94% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::11392-11399 1 0.00% 69.94% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::11520-11527 141 0.15% 70.09% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::11584-11591 2 0.00% 70.10% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::11648-11655 1 0.00% 70.10% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::11776-11783 20 0.02% 70.12% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::11904-11911 2 0.00% 70.12% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::12032-12039 75 0.08% 70.20% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::12160-12167 1 0.00% 70.20% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::12224-12231 1 0.00% 70.20% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::12288-12295 353 0.39% 70.59% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::12352-12359 1 0.00% 70.59% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::12416-12423 1 0.00% 70.59% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::12544-12551 89 0.10% 70.69% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::12672-12679 1 0.00% 70.69% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::12736-12743 1 0.00% 70.69% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::12800-12807 73 0.08% 70.77% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::12992-12999 2 0.00% 70.77% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::13056-13063 85 0.09% 70.87% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::13120-13127 1 0.00% 70.87% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::13184-13191 4 0.00% 70.87% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::13248-13255 1 0.00% 70.87% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::13312-13319 331 0.36% 71.23% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::13568-13575 70 0.08% 71.31% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::13696-13703 2 0.00% 71.31% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::13824-13831 145 0.16% 71.47% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::13952-13959 2 0.00% 71.47% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::14080-14087 17 0.02% 71.49% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::14208-14215 2 0.00% 71.49% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::14272-14279 1 0.00% 71.49% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::14336-14343 336 0.37% 71.86% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::14464-14471 4 0.00% 71.87% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::14592-14599 80 0.09% 71.95% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::14656-14663 1 0.00% 71.95% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::14848-14855 83 0.09% 72.04% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::15104-15111 18 0.02% 72.06% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::15168-15175 2 0.00% 72.07% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::15232-15239 1 0.00% 72.07% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::15296-15303 1 0.00% 72.07% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::15360-15367 400 0.44% 72.51% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::15488-15495 1 0.00% 72.51% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::15616-15623 77 0.08% 72.59% # Bytes accessed per row activation | 233system.physmem.bytesPerActivate::2176-2183 43 0.05% 62.70% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2240-2247 10 0.01% 62.71% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2304-2311 57 0.06% 62.77% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2368-2375 5 0.01% 62.78% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2432-2439 24 0.03% 62.80% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2496-2503 13 0.01% 62.82% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2560-2567 166 0.18% 63.00% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2624-2631 7 0.01% 63.01% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2688-2695 16 0.02% 63.02% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2752-2759 4 0.00% 63.03% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2816-2823 30 0.03% 63.06% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::2880-2887 6 0.01% 63.07% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::2944-2951 23 0.03% 63.09% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3008-3015 4 0.00% 63.10% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3072-3079 317 0.35% 63.44% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3136-3143 3 0.00% 63.45% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3200-3207 20 0.02% 63.47% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3264-3271 11 0.01% 63.48% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3328-3335 167 0.18% 63.66% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3392-3399 13 0.01% 63.68% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3456-3463 17 0.02% 63.70% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3520-3527 7 0.01% 63.70% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3584-3591 159 0.17% 63.88% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3648-3655 8 0.01% 63.89% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.90% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3776-3783 11 0.01% 63.92% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3840-3847 119 0.13% 64.05% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::3904-3911 7 0.01% 64.05% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::3968-3975 21 0.02% 64.08% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4032-4039 9 0.01% 64.09% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4096-4103 498 0.54% 64.63% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4160-4167 8 0.01% 64.64% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4224-4231 12 0.01% 64.65% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4288-4295 9 0.01% 64.66% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4352-4359 21 0.02% 64.69% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4416-4423 17 0.02% 64.70% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4480-4487 15 0.02% 64.72% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4544-4551 10 0.01% 64.73% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4608-4615 32 0.03% 64.77% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4672-4679 2 0.00% 64.77% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4736-4743 10 0.01% 64.78% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4800-4807 9 0.01% 64.79% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::4864-4871 144 0.16% 64.95% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::4928-4935 10 0.01% 64.96% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::4992-4999 10 0.01% 64.97% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5056-5063 5 0.01% 64.97% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5120-5127 298 0.33% 65.30% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5184-5191 8 0.01% 65.31% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5248-5255 12 0.01% 65.32% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5312-5319 6 0.01% 65.33% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5376-5383 14 0.02% 65.34% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5440-5447 7 0.01% 65.35% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5504-5511 8 0.01% 65.36% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::5568-5575 5 0.01% 65.37% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::5632-5639 74 0.08% 65.45% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::5696-5703 2 0.00% 65.45% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::5760-5767 15 0.02% 65.46% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::5824-5831 4 0.00% 65.47% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::5888-5895 253 0.28% 65.75% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::5952-5959 4 0.00% 65.75% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6016-6023 13 0.01% 65.76% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6080-6087 13 0.01% 65.78% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6144-6151 396 0.43% 66.21% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6208-6215 4 0.00% 66.22% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::6272-6279 10 0.01% 66.23% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::6336-6343 4 0.00% 66.23% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::6400-6407 85 0.09% 66.32% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::6464-6471 5 0.01% 66.33% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::6528-6535 8 0.01% 66.34% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::6592-6599 5 0.01% 66.34% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::6656-6663 103 0.11% 66.46% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::6720-6727 8 0.01% 66.46% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::6784-6791 22 0.02% 66.49% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::6848-6855 2 0.00% 66.49% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::6912-6919 29 0.03% 66.52% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::6976-6983 4 0.00% 66.53% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7040-7047 7 0.01% 66.53% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::7104-7111 3 0.00% 66.54% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::7168-7175 296 0.32% 66.86% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::7232-7239 3 0.00% 66.86% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::7296-7303 7 0.01% 66.87% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::7360-7367 10 0.01% 66.88% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::7424-7431 167 0.18% 67.07% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::7488-7495 5 0.01% 67.07% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::7552-7559 11 0.01% 67.08% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::7616-7623 5 0.01% 67.09% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::7680-7687 20 0.02% 67.11% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::7744-7751 1 0.00% 67.11% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::7808-7815 5 0.01% 67.12% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::7936-7943 73 0.08% 67.20% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::8000-8007 3 0.00% 67.20% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::8064-8071 9 0.01% 67.21% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::8192-8199 634 0.69% 67.90% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::8320-8327 2 0.00% 67.91% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::8448-8455 75 0.08% 67.99% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::8576-8583 2 0.00% 67.99% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::8704-8711 13 0.01% 68.00% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::8832-8839 1 0.00% 68.00% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::8960-8967 157 0.17% 68.18% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::9024-9031 1 0.00% 68.18% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::9088-9095 2 0.00% 68.18% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::9152-9159 1 0.00% 68.18% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::9216-9223 285 0.31% 68.49% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::9472-9479 15 0.02% 68.51% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::9536-9543 1 0.00% 68.51% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::9600-9607 1 0.00% 68.51% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::9728-9735 93 0.10% 68.61% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::9792-9799 1 0.00% 68.61% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::9856-9863 1 0.00% 68.61% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::9984-9991 77 0.08% 68.70% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::10048-10055 1 0.00% 68.70% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::10112-10119 4 0.00% 68.70% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::10240-10247 396 0.43% 69.14% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::10368-10375 2 0.00% 69.14% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::10432-10439 1 0.00% 69.14% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::10496-10503 200 0.22% 69.36% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::10688-10695 1 0.00% 69.36% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::10752-10759 71 0.08% 69.44% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::10816-10823 1 0.00% 69.44% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::10880-10887 1 0.00% 69.44% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::10944-10951 1 0.00% 69.44% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::11008-11015 10 0.01% 69.45% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::11136-11143 1 0.00% 69.45% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::11264-11271 289 0.32% 69.77% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::11328-11335 1 0.00% 69.77% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::11392-11399 1 0.00% 69.77% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::11520-11527 139 0.15% 69.92% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::11584-11591 1 0.00% 69.92% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::11776-11783 14 0.02% 69.94% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::12032-12039 10 0.01% 69.95% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::12160-12167 5 0.01% 69.96% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::12224-12231 2 0.00% 69.96% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::12288-12295 463 0.51% 70.46% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::12352-12359 1 0.00% 70.47% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::12480-12487 1 0.00% 70.47% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::12544-12551 93 0.10% 70.57% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::12608-12615 1 0.00% 70.57% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::12672-12679 1 0.00% 70.57% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::12800-12807 146 0.16% 70.73% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::12864-12871 1 0.00% 70.73% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::12928-12935 1 0.00% 70.73% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::12992-12999 1 0.00% 70.73% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::13056-13063 146 0.16% 70.89% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::13120-13127 1 0.00% 70.89% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::13184-13191 1 0.00% 70.89% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::13312-13319 294 0.32% 71.22% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::13568-13575 17 0.02% 71.23% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::13632-13639 1 0.00% 71.24% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::13696-13703 1 0.00% 71.24% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::13824-13831 141 0.15% 71.39% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::13952-13959 1 0.00% 71.39% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::14080-14087 14 0.02% 71.41% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::14208-14215 3 0.00% 71.41% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::14336-14343 345 0.38% 71.79% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::14400-14407 1 0.00% 71.79% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::14464-14471 2 0.00% 71.79% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::14528-14535 1 0.00% 71.79% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::14592-14599 78 0.09% 71.88% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::14656-14663 1 0.00% 71.88% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::14720-14727 2 0.00% 71.88% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::14848-14855 78 0.09% 71.97% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::14976-14983 3 0.00% 71.97% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::15104-15111 81 0.09% 72.06% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::15168-15175 1 0.00% 72.06% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::15232-15239 1 0.00% 72.06% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::15296-15303 2 0.00% 72.06% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::15360-15367 392 0.43% 72.49% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::15616-15623 92 0.10% 72.59% # Bytes accessed per row activation |
| 404system.physmem.bytesPerActivate::15808-15815 1 0.00% 72.59% # Bytes accessed per row activation | 401system.physmem.bytesPerActivate::15808-15815 1 0.00% 72.59% # Bytes accessed per row activation |
| 405system.physmem.bytesPerActivate::15872-15879 147 0.16% 72.75% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::15936-15943 1 0.00% 72.75% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::16000-16007 3 0.00% 72.76% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::16128-16135 74 0.08% 72.84% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::16256-16263 4 0.00% 72.84% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::16384-16391 514 0.56% 73.40% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::16512-16519 1 0.00% 73.40% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::16640-16647 75 0.08% 73.49% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::16704-16711 1 0.00% 73.49% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::16896-16903 140 0.15% 73.64% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::17024-17031 1 0.00% 73.64% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::17152-17159 75 0.08% 73.72% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::17280-17287 3 0.00% 73.73% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::17344-17351 1 0.00% 73.73% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::17408-17415 397 0.43% 74.16% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::17472-17479 1 0.00% 74.16% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::17536-17543 1 0.00% 74.16% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::17664-17671 22 0.02% 74.19% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::17728-17735 2 0.00% 74.19% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::17920-17927 82 0.09% 74.28% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::18048-18055 3 0.00% 74.28% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::18112-18119 2 0.00% 74.28% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::18176-18183 77 0.08% 74.37% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::18240-18247 1 0.00% 74.37% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::18304-18311 4 0.00% 74.37% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::18368-18375 1 0.00% 74.37% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::18432-18439 337 0.37% 74.74% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::18496-18503 1 0.00% 74.74% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::18688-18695 20 0.02% 74.76% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::18752-18759 1 0.00% 74.77% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::18816-18823 2 0.00% 74.77% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::18944-18951 146 0.16% 74.93% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.93% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::19136-19143 1 0.00% 74.93% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::19200-19207 69 0.08% 75.00% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::19328-19335 4 0.00% 75.01% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::19392-19399 2 0.00% 75.01% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::19456-19463 330 0.36% 75.37% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::19520-19527 1 0.00% 75.37% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::19712-19719 82 0.09% 75.46% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::19968-19975 77 0.08% 75.55% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::20160-20167 1 0.00% 75.55% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::20224-20231 92 0.10% 75.65% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::20352-20359 2 0.00% 75.65% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::20416-20423 1 0.00% 75.65% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::20480-20487 348 0.38% 76.03% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::20544-20551 1 0.00% 76.03% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::20608-20615 3 0.00% 76.03% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::20672-20679 1 0.00% 76.04% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::20736-20743 78 0.09% 76.12% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::20992-20999 26 0.03% 76.15% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::21120-21127 1 0.00% 76.15% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::21184-21191 1 0.00% 76.15% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::21248-21255 140 0.15% 76.30% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::21312-21319 1 0.00% 76.31% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::21376-21383 3 0.00% 76.31% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::21440-21447 2 0.00% 76.31% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::21504-21511 469 0.51% 76.82% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::21760-21767 6 0.01% 76.83% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.83% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::22016-22023 94 0.10% 76.93% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::22144-22151 1 0.00% 76.93% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::22208-22215 4 0.00% 76.94% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::22272-22279 92 0.10% 77.04% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::22400-22407 3 0.00% 77.04% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::22464-22471 1 0.00% 77.04% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::22528-22535 276 0.30% 77.34% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::22592-22599 1 0.00% 77.35% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::22656-22663 1 0.00% 77.35% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::22784-22791 77 0.08% 77.43% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::22912-22919 2 0.00% 77.43% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::22976-22983 1 0.00% 77.43% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::23040-23047 140 0.15% 77.59% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::23168-23175 1 0.00% 77.59% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::23232-23239 1 0.00% 77.59% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::23296-23303 28 0.03% 77.62% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::23360-23367 1 0.00% 77.62% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::23424-23431 2 0.00% 77.62% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::23552-23559 459 0.50% 78.12% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::23680-23687 3 0.00% 78.13% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::23808-23815 146 0.16% 78.29% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::23872-23879 1 0.00% 78.29% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::23936-23943 1 0.00% 78.29% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::24064-24071 7 0.01% 78.30% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::24128-24135 1 0.00% 78.30% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::24192-24199 1 0.00% 78.30% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::24320-24327 88 0.10% 78.39% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::24384-24391 1 0.00% 78.40% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::24448-24455 5 0.01% 78.40% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::24512-24519 2 0.00% 78.40% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::24576-24583 281 0.31% 78.71% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::24640-24647 1 0.00% 78.71% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::24832-24839 86 0.09% 78.80% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.81% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::25088-25095 6 0.01% 78.81% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::25344-25351 153 0.17% 78.98% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::25472-25479 4 0.00% 78.98% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::25536-25543 1 0.00% 78.98% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::25600-25607 454 0.50% 79.48% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::25792-25799 1 0.00% 79.48% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::25856-25863 26 0.03% 79.51% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::25984-25991 1 0.00% 79.51% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::26112-26119 144 0.16% 79.67% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::26240-26247 3 0.00% 79.67% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::26368-26375 79 0.09% 79.76% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::26432-26439 2 0.00% 79.76% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::26496-26503 5 0.01% 79.77% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::26624-26631 276 0.30% 80.07% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::26752-26759 1 0.00% 80.07% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::26816-26823 2 0.00% 80.07% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::26880-26887 94 0.10% 80.17% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::26944-26951 1 0.00% 80.17% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::27008-27015 2 0.00% 80.18% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::27072-27079 1 0.00% 80.18% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::27136-27143 92 0.10% 80.28% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::27200-27207 1 0.00% 80.28% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::27264-27271 1 0.00% 80.28% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::27392-27399 9 0.01% 80.29% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::27456-27463 1 0.00% 80.29% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::27520-27527 4 0.00% 80.29% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::27648-27655 472 0.52% 80.81% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::27712-27719 2 0.00% 80.81% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::27776-27783 2 0.00% 80.81% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::27904-27911 140 0.15% 80.97% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::27968-27975 1 0.00% 80.97% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::28160-28167 21 0.02% 80.99% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::28224-28231 2 0.00% 80.99% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::28288-28295 2 0.00% 81.00% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::28416-28423 78 0.09% 81.08% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::28480-28487 2 0.00% 81.08% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::28544-28551 4 0.00% 81.09% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::28672-28679 344 0.38% 81.46% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::28736-28743 1 0.00% 81.46% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::28800-28807 2 0.00% 81.47% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::28864-28871 1 0.00% 81.47% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::28928-28935 87 0.09% 81.56% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::28992-28999 1 0.00% 81.56% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::29184-29191 75 0.08% 81.64% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::29312-29319 2 0.00% 81.65% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::29376-29383 2 0.00% 81.65% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::29440-29447 81 0.09% 81.74% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::29504-29511 1 0.00% 81.74% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::29568-29575 2 0.00% 81.74% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::29632-29639 2 0.00% 81.74% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::29696-29703 325 0.35% 82.10% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::29760-29767 3 0.00% 82.10% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::29824-29831 2 0.00% 82.10% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::29952-29959 72 0.08% 82.18% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::30016-30023 2 0.00% 82.18% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::30080-30087 2 0.00% 82.19% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::30144-30151 3 0.00% 82.19% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::30208-30215 142 0.15% 82.34% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::30272-30279 1 0.00% 82.35% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::30336-30343 1 0.00% 82.35% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::30464-30471 20 0.02% 82.37% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::30528-30535 1 0.00% 82.37% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::30592-30599 3 0.00% 82.37% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::30656-30663 1 0.00% 82.37% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::30720-30727 331 0.36% 82.73% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::30848-30855 1 0.00% 82.74% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::30976-30983 75 0.08% 82.82% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::31040-31047 2 0.00% 82.82% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::31104-31111 4 0.00% 82.82% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::31168-31175 2 0.00% 82.83% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::31232-31239 80 0.09% 82.91% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::31360-31367 2 0.00% 82.92% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::31488-31495 17 0.02% 82.93% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::31616-31623 2 0.00% 82.94% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::31680-31687 3 0.00% 82.94% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::31744-31751 402 0.44% 83.38% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::32000-32007 74 0.08% 83.46% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::32128-32135 2 0.00% 83.46% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::32256-32263 141 0.15% 83.62% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::32384-32391 1 0.00% 83.62% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::32512-32519 73 0.08% 83.70% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.70% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::32768-32775 516 0.56% 84.26% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::32896-32903 3 0.00% 84.26% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::33024-33031 69 0.08% 84.34% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::33088-33095 1 0.00% 84.34% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::33280-33287 142 0.15% 84.50% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::33408-33415 2 0.00% 84.50% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::33536-33543 81 0.09% 84.59% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::33664-33671 2 0.00% 84.59% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::33792-33799 419 0.46% 85.05% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::33856-33863 1 0.00% 85.05% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::33920-33927 2 0.00% 85.05% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::34048-34055 17 0.02% 85.07% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::34176-34183 1 0.00% 85.07% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::34304-34311 80 0.09% 85.16% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::34368-34375 1 0.00% 85.16% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::34432-34439 2 0.00% 85.16% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::34496-34503 1 0.00% 85.16% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::34560-34567 75 0.08% 85.24% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::34816-34823 329 0.36% 85.60% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.60% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::35072-35079 20 0.02% 85.62% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.63% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.63% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::35328-35335 143 0.16% 85.78% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.79% # Bytes accessed per row activation 606system.physmem.bytesPerActivate::35584-35591 69 0.08% 85.86% # Bytes accessed per row activation 607system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.86% # Bytes accessed per row activation 608system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.86% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::35776-35783 1 0.00% 85.86% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::35840-35847 324 0.35% 86.22% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::36096-36103 79 0.09% 86.30% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::36160-36167 2 0.00% 86.31% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::36224-36231 2 0.00% 86.31% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::36352-36359 71 0.08% 86.39% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::36480-36487 2 0.00% 86.39% # Bytes accessed per row activation 616system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.39% # Bytes accessed per row activation 617system.physmem.bytesPerActivate::36608-36615 87 0.09% 86.48% # Bytes accessed per row activation 618system.physmem.bytesPerActivate::36864-36871 344 0.38% 86.86% # Bytes accessed per row activation 619system.physmem.bytesPerActivate::37120-37127 77 0.08% 86.94% # Bytes accessed per row activation 620system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.94% # Bytes accessed per row activation 621system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.95% # Bytes accessed per row activation 622system.physmem.bytesPerActivate::37376-37383 23 0.03% 86.97% # Bytes accessed per row activation 623system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.97% # Bytes accessed per row activation 624system.physmem.bytesPerActivate::37632-37639 141 0.15% 87.13% # Bytes accessed per row activation 625system.physmem.bytesPerActivate::37760-37767 1 0.00% 87.13% # Bytes accessed per row activation 626system.physmem.bytesPerActivate::37888-37895 468 0.51% 87.64% # Bytes accessed per row activation 627system.physmem.bytesPerActivate::38144-38151 6 0.01% 87.64% # Bytes accessed per row activation 628system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.65% # Bytes accessed per row activation 629system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.65% # Bytes accessed per row activation 630system.physmem.bytesPerActivate::38400-38407 91 0.10% 87.75% # Bytes accessed per row activation 631system.physmem.bytesPerActivate::38528-38535 6 0.01% 87.75% # Bytes accessed per row activation 632system.physmem.bytesPerActivate::38656-38663 98 0.11% 87.86% # Bytes accessed per row activation 633system.physmem.bytesPerActivate::38784-38791 2 0.00% 87.86% # Bytes accessed per row activation 634system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.86% # Bytes accessed per row activation 635system.physmem.bytesPerActivate::38912-38919 273 0.30% 88.16% # Bytes accessed per row activation 636system.physmem.bytesPerActivate::39168-39175 79 0.09% 88.25% # Bytes accessed per row activation 637system.physmem.bytesPerActivate::39424-39431 143 0.16% 88.40% # Bytes accessed per row activation 638system.physmem.bytesPerActivate::39552-39559 3 0.00% 88.41% # Bytes accessed per row activation 639system.physmem.bytesPerActivate::39616-39623 1 0.00% 88.41% # Bytes accessed per row activation 640system.physmem.bytesPerActivate::39680-39687 23 0.03% 88.43% # Bytes accessed per row activation 641system.physmem.bytesPerActivate::39744-39751 1 0.00% 88.43% # Bytes accessed per row activation 642system.physmem.bytesPerActivate::39936-39943 454 0.50% 88.93% # Bytes accessed per row activation 643system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.93% # Bytes accessed per row activation 644system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.93% # Bytes accessed per row activation 645system.physmem.bytesPerActivate::40192-40199 151 0.16% 89.10% # Bytes accessed per row activation 646system.physmem.bytesPerActivate::40448-40455 4 0.00% 89.10% # Bytes accessed per row activation 647system.physmem.bytesPerActivate::40576-40583 4 0.00% 89.11% # Bytes accessed per row activation 648system.physmem.bytesPerActivate::40704-40711 86 0.09% 89.20% # Bytes accessed per row activation 649system.physmem.bytesPerActivate::40960-40967 275 0.30% 89.50% # Bytes accessed per row activation 650system.physmem.bytesPerActivate::41024-41031 2 0.00% 89.50% # Bytes accessed per row activation 651system.physmem.bytesPerActivate::41088-41095 1 0.00% 89.50% # Bytes accessed per row activation 652system.physmem.bytesPerActivate::41216-41223 85 0.09% 89.60% # Bytes accessed per row activation 653system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.60% # Bytes accessed per row activation 654system.physmem.bytesPerActivate::41472-41479 4 0.00% 89.60% # Bytes accessed per row activation 655system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.60% # Bytes accessed per row activation 656system.physmem.bytesPerActivate::41728-41735 148 0.16% 89.77% # Bytes accessed per row activation 657system.physmem.bytesPerActivate::41984-41991 453 0.49% 90.26% # Bytes accessed per row activation 658system.physmem.bytesPerActivate::42112-42119 3 0.00% 90.26% # Bytes accessed per row activation 659system.physmem.bytesPerActivate::42176-42183 1 0.00% 90.27% # Bytes accessed per row activation 660system.physmem.bytesPerActivate::42240-42247 24 0.03% 90.29% # Bytes accessed per row activation 661system.physmem.bytesPerActivate::42304-42311 1 0.00% 90.29% # Bytes accessed per row activation 662system.physmem.bytesPerActivate::42432-42439 1 0.00% 90.29% # Bytes accessed per row activation 663system.physmem.bytesPerActivate::42496-42503 142 0.15% 90.45% # Bytes accessed per row activation 664system.physmem.bytesPerActivate::42560-42567 1 0.00% 90.45% # Bytes accessed per row activation 665system.physmem.bytesPerActivate::42624-42631 2 0.00% 90.45% # Bytes accessed per row activation 666system.physmem.bytesPerActivate::42752-42759 76 0.08% 90.53% # Bytes accessed per row activation 667system.physmem.bytesPerActivate::43008-43015 275 0.30% 90.83% # Bytes accessed per row activation 668system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.84% # Bytes accessed per row activation 669system.physmem.bytesPerActivate::43264-43271 88 0.10% 90.93% # Bytes accessed per row activation 670system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.93% # Bytes accessed per row activation 671system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.93% # Bytes accessed per row activation 672system.physmem.bytesPerActivate::43520-43527 89 0.10% 91.03% # Bytes accessed per row activation 673system.physmem.bytesPerActivate::43648-43655 3 0.00% 91.03% # Bytes accessed per row activation 674system.physmem.bytesPerActivate::43776-43783 6 0.01% 91.04% # Bytes accessed per row activation 675system.physmem.bytesPerActivate::43904-43911 1 0.00% 91.04% # Bytes accessed per row activation 676system.physmem.bytesPerActivate::43968-43975 2 0.00% 91.04% # Bytes accessed per row activation 677system.physmem.bytesPerActivate::44032-44039 468 0.51% 91.56% # Bytes accessed per row activation 678system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.56% # Bytes accessed per row activation 679system.physmem.bytesPerActivate::44288-44295 137 0.15% 91.71% # Bytes accessed per row activation 680system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.71% # Bytes accessed per row activation 681system.physmem.bytesPerActivate::44544-44551 25 0.03% 91.73% # Bytes accessed per row activation 682system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.74% # Bytes accessed per row activation 683system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.74% # Bytes accessed per row activation 684system.physmem.bytesPerActivate::44800-44807 78 0.09% 91.82% # Bytes accessed per row activation 685system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.82% # Bytes accessed per row activation 686system.physmem.bytesPerActivate::44992-44999 2 0.00% 91.83% # Bytes accessed per row activation 687system.physmem.bytesPerActivate::45056-45063 347 0.38% 92.20% # Bytes accessed per row activation 688system.physmem.bytesPerActivate::45184-45191 1 0.00% 92.21% # Bytes accessed per row activation 689system.physmem.bytesPerActivate::45312-45319 91 0.10% 92.30% # Bytes accessed per row activation 690system.physmem.bytesPerActivate::45440-45447 1 0.00% 92.31% # Bytes accessed per row activation 691system.physmem.bytesPerActivate::45504-45511 1 0.00% 92.31% # Bytes accessed per row activation 692system.physmem.bytesPerActivate::45568-45575 81 0.09% 92.40% # Bytes accessed per row activation 693system.physmem.bytesPerActivate::45696-45703 3 0.00% 92.40% # Bytes accessed per row activation | 402system.physmem.bytesPerActivate::15872-15879 13 0.01% 72.61% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::15936-15943 1 0.00% 72.61% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::16000-16007 1 0.00% 72.61% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::16128-16135 74 0.08% 72.69% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::16192-16199 1 0.00% 72.69% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::16256-16263 10 0.01% 72.70% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::16384-16391 676 0.74% 73.44% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::16640-16647 76 0.08% 73.52% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::16896-16903 13 0.01% 73.54% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::16960-16967 2 0.00% 73.54% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::17152-17159 98 0.11% 73.65% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::17216-17223 1 0.00% 73.65% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::17280-17287 2 0.00% 73.65% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::17344-17351 1 0.00% 73.65% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::17408-17415 394 0.43% 74.08% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::17472-17479 4 0.00% 74.09% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::17536-17543 1 0.00% 74.09% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::17600-17607 2 0.00% 74.09% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::17664-17671 80 0.09% 74.18% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::17728-17735 1 0.00% 74.18% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::17792-17799 1 0.00% 74.18% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::17856-17863 1 0.00% 74.18% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::17920-17927 77 0.08% 74.26% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::18112-18119 1 0.00% 74.27% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::18176-18183 83 0.09% 74.36% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::18304-18311 3 0.00% 74.36% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::18432-18439 341 0.37% 74.73% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::18688-18695 14 0.02% 74.75% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::18816-18823 2 0.00% 74.75% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::18944-18951 141 0.15% 74.90% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.91% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::19200-19207 23 0.03% 74.93% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::19328-19335 2 0.00% 74.93% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::19456-19463 287 0.31% 75.25% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::19520-19527 3 0.00% 75.25% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::19584-19591 3 0.00% 75.25% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::19648-19655 1 0.00% 75.25% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::19712-19719 144 0.16% 75.41% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::19776-19783 2 0.00% 75.41% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::19968-19975 144 0.16% 75.57% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::20160-20167 1 0.00% 75.57% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::20224-20231 97 0.11% 75.68% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::20288-20295 1 0.00% 75.68% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::20352-20359 3 0.00% 75.68% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::20480-20487 470 0.51% 76.20% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::20544-20551 1 0.00% 76.20% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::20672-20679 1 0.00% 76.20% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::20736-20743 10 0.01% 76.21% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::20992-20999 16 0.02% 76.23% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::21056-21063 1 0.00% 76.23% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::21120-21127 1 0.00% 76.23% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::21248-21255 142 0.16% 76.38% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::21376-21383 4 0.00% 76.39% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::21440-21447 3 0.00% 76.39% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::21504-21511 283 0.31% 76.70% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::21760-21767 9 0.01% 76.71% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::21824-21831 1 0.00% 76.71% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.71% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::22016-22023 72 0.08% 76.79% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::22144-22151 2 0.00% 76.79% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::22272-22279 194 0.21% 77.01% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::22400-22407 3 0.00% 77.01% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::22464-22471 1 0.00% 77.01% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::22528-22535 387 0.42% 77.43% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::22592-22599 2 0.00% 77.44% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::22656-22663 1 0.00% 77.44% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::22720-22727 2 0.00% 77.44% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::22784-22791 79 0.09% 77.53% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::22848-22855 1 0.00% 77.53% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::22976-22983 2 0.00% 77.53% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::23040-23047 89 0.10% 77.63% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::23104-23111 1 0.00% 77.63% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::23168-23175 2 0.00% 77.63% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::23296-23303 21 0.02% 77.65% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::23424-23431 1 0.00% 77.65% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::23552-23559 286 0.31% 77.97% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::23680-23687 2 0.00% 77.97% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::23808-23815 151 0.17% 78.13% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::24064-24071 13 0.01% 78.15% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::24256-24263 2 0.00% 78.15% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::24320-24327 73 0.08% 78.23% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::24384-24391 1 0.00% 78.23% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::24448-24455 6 0.01% 78.24% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::24576-24583 527 0.58% 78.81% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.81% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::24768-24775 1 0.00% 78.82% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::24832-24839 73 0.08% 78.90% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.90% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::25088-25095 14 0.02% 78.91% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::25152-25159 1 0.00% 78.91% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::25216-25223 1 0.00% 78.91% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.92% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::25344-25351 156 0.17% 79.09% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::25408-25415 2 0.00% 79.09% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::25472-25479 3 0.00% 79.09% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::25600-25607 278 0.30% 79.40% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::25664-25671 2 0.00% 79.40% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::25856-25863 13 0.01% 79.41% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::25984-25991 3 0.00% 79.42% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::26048-26055 1 0.00% 79.42% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::26112-26119 89 0.10% 79.51% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::26176-26183 4 0.00% 79.52% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::26240-26247 1 0.00% 79.52% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::26368-26375 78 0.09% 79.60% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::26496-26503 4 0.00% 79.61% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::26624-26631 385 0.42% 80.03% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::26752-26759 1 0.00% 80.03% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::26816-26823 2 0.00% 80.03% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::26880-26887 196 0.21% 80.25% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::26944-26951 1 0.00% 80.25% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::27008-27015 1 0.00% 80.25% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::27072-27079 2 0.00% 80.25% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::27136-27143 71 0.08% 80.33% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::27200-27207 1 0.00% 80.33% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::27392-27399 10 0.01% 80.34% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::27456-27463 2 0.00% 80.34% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::27520-27527 2 0.00% 80.35% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::27648-27655 285 0.31% 80.66% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::27712-27719 1 0.00% 80.66% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::27776-27783 2 0.00% 80.66% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::27904-27911 137 0.15% 80.81% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::28096-28103 1 0.00% 80.81% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::28160-28167 20 0.02% 80.83% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::28224-28231 1 0.00% 80.83% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.83% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.84% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::28416-28423 15 0.02% 80.85% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.86% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.86% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::28672-28679 454 0.50% 81.36% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::28800-28807 1 0.00% 81.36% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::28864-28871 1 0.00% 81.36% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::28928-28935 95 0.10% 81.46% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::29056-29063 2 0.00% 81.46% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::29120-29127 2 0.00% 81.47% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::29184-29191 143 0.16% 81.62% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::29312-29319 3 0.00% 81.63% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::29376-29383 2 0.00% 81.63% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::29440-29447 147 0.16% 81.79% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::29568-29575 5 0.01% 81.79% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::29632-29639 1 0.00% 81.79% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::29696-29703 291 0.32% 82.11% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::29760-29767 1 0.00% 82.11% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::29824-29831 1 0.00% 82.11% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::29952-29959 18 0.02% 82.13% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::30080-30087 2 0.00% 82.14% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::30144-30151 1 0.00% 82.14% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::30208-30215 139 0.15% 82.29% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::30272-30279 2 0.00% 82.29% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::30464-30471 17 0.02% 82.31% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::30528-30535 2 0.00% 82.31% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::30592-30599 5 0.01% 82.32% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::30720-30727 334 0.37% 82.68% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::30784-30791 2 0.00% 82.69% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::30976-30983 75 0.08% 82.77% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::31040-31047 2 0.00% 82.77% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::31104-31111 1 0.00% 82.77% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.77% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::31232-31239 77 0.08% 82.86% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::31424-31431 2 0.00% 82.86% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::31488-31495 84 0.09% 82.95% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::31616-31623 6 0.01% 82.96% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.96% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::31744-31751 392 0.43% 83.39% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::31808-31815 1 0.00% 83.39% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::31872-31879 1 0.00% 83.39% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::32000-32007 91 0.10% 83.49% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::32128-32135 2 0.00% 83.49% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::32256-32263 14 0.02% 83.51% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::32384-32391 2 0.00% 83.51% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::32512-32519 81 0.09% 83.60% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::32576-32583 1 0.00% 83.60% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::32640-32647 2 0.00% 83.60% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::32768-32775 668 0.73% 84.33% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::33024-33031 70 0.08% 84.41% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::33280-33287 13 0.01% 84.42% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::33344-33351 1 0.00% 84.42% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::33408-33415 3 0.00% 84.42% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::33536-33543 95 0.10% 84.53% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::33600-33607 1 0.00% 84.53% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::33664-33671 3 0.00% 84.53% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::33792-33799 402 0.44% 84.97% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.97% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::34048-34055 82 0.09% 85.06% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::34304-34311 76 0.08% 85.15% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::34432-34439 4 0.00% 85.15% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::34560-34567 80 0.09% 85.24% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::34688-34695 1 0.00% 85.24% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::34752-34759 1 0.00% 85.24% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::34816-34823 334 0.37% 85.60% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.61% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::35008-35015 1 0.00% 85.61% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::35072-35079 12 0.01% 85.62% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.62% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.62% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::35264-35271 1 0.00% 85.62% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::35328-35335 138 0.15% 85.78% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.78% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::35584-35591 16 0.02% 85.80% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::35712-35719 3 0.00% 85.80% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::35840-35847 289 0.32% 86.12% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::35904-35911 1 0.00% 86.12% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::35968-35975 1 0.00% 86.12% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::36096-36103 143 0.16% 86.27% # Bytes accessed per row activation 606system.physmem.bytesPerActivate::36352-36359 143 0.16% 86.43% # Bytes accessed per row activation 607system.physmem.bytesPerActivate::36416-36423 2 0.00% 86.43% # Bytes accessed per row activation 608system.physmem.bytesPerActivate::36480-36487 4 0.00% 86.44% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::36608-36615 101 0.11% 86.55% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::36864-36871 455 0.50% 87.04% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::37056-37063 1 0.00% 87.05% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::37120-37127 7 0.01% 87.05% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::37248-37255 2 0.00% 87.06% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::37312-37319 1 0.00% 87.06% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::37376-37383 19 0.02% 87.08% # Bytes accessed per row activation 616system.physmem.bytesPerActivate::37504-37511 2 0.00% 87.08% # Bytes accessed per row activation 617system.physmem.bytesPerActivate::37632-37639 137 0.15% 87.23% # Bytes accessed per row activation 618system.physmem.bytesPerActivate::37888-37895 277 0.30% 87.53% # Bytes accessed per row activation 619system.physmem.bytesPerActivate::38016-38023 1 0.00% 87.53% # Bytes accessed per row activation 620system.physmem.bytesPerActivate::38144-38151 9 0.01% 87.54% # Bytes accessed per row activation 621system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.54% # Bytes accessed per row activation 622system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.54% # Bytes accessed per row activation 623system.physmem.bytesPerActivate::38400-38407 70 0.08% 87.62% # Bytes accessed per row activation 624system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.62% # Bytes accessed per row activation 625system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.62% # Bytes accessed per row activation 626system.physmem.bytesPerActivate::38656-38663 197 0.22% 87.84% # Bytes accessed per row activation 627system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.84% # Bytes accessed per row activation 628system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.84% # Bytes accessed per row activation 629system.physmem.bytesPerActivate::38912-38919 387 0.42% 88.27% # Bytes accessed per row activation 630system.physmem.bytesPerActivate::39040-39047 2 0.00% 88.27% # Bytes accessed per row activation 631system.physmem.bytesPerActivate::39168-39175 74 0.08% 88.35% # Bytes accessed per row activation 632system.physmem.bytesPerActivate::39424-39431 86 0.09% 88.44% # Bytes accessed per row activation 633system.physmem.bytesPerActivate::39488-39495 2 0.00% 88.44% # Bytes accessed per row activation 634system.physmem.bytesPerActivate::39552-39559 4 0.00% 88.45% # Bytes accessed per row activation 635system.physmem.bytesPerActivate::39680-39687 16 0.02% 88.47% # Bytes accessed per row activation 636system.physmem.bytesPerActivate::39808-39815 2 0.00% 88.47% # Bytes accessed per row activation 637system.physmem.bytesPerActivate::39872-39879 1 0.00% 88.47% # Bytes accessed per row activation 638system.physmem.bytesPerActivate::39936-39943 277 0.30% 88.77% # Bytes accessed per row activation 639system.physmem.bytesPerActivate::40192-40199 154 0.17% 88.94% # Bytes accessed per row activation 640system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.94% # Bytes accessed per row activation 641system.physmem.bytesPerActivate::40448-40455 11 0.01% 88.95% # Bytes accessed per row activation 642system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.96% # Bytes accessed per row activation 643system.physmem.bytesPerActivate::40704-40711 77 0.08% 89.04% # Bytes accessed per row activation 644system.physmem.bytesPerActivate::40960-40967 525 0.57% 89.62% # Bytes accessed per row activation 645system.physmem.bytesPerActivate::41088-41095 1 0.00% 89.62% # Bytes accessed per row activation 646system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.69% # Bytes accessed per row activation 647system.physmem.bytesPerActivate::41344-41351 3 0.00% 89.69% # Bytes accessed per row activation 648system.physmem.bytesPerActivate::41472-41479 14 0.02% 89.71% # Bytes accessed per row activation 649system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.71% # Bytes accessed per row activation 650system.physmem.bytesPerActivate::41728-41735 154 0.17% 89.88% # Bytes accessed per row activation 651system.physmem.bytesPerActivate::41984-41991 280 0.31% 90.19% # Bytes accessed per row activation 652system.physmem.bytesPerActivate::42112-42119 1 0.00% 90.19% # Bytes accessed per row activation 653system.physmem.bytesPerActivate::42240-42247 18 0.02% 90.21% # Bytes accessed per row activation 654system.physmem.bytesPerActivate::42304-42311 2 0.00% 90.21% # Bytes accessed per row activation 655system.physmem.bytesPerActivate::42368-42375 1 0.00% 90.21% # Bytes accessed per row activation 656system.physmem.bytesPerActivate::42496-42503 88 0.10% 90.31% # Bytes accessed per row activation 657system.physmem.bytesPerActivate::42624-42631 2 0.00% 90.31% # Bytes accessed per row activation 658system.physmem.bytesPerActivate::42752-42759 77 0.08% 90.39% # Bytes accessed per row activation 659system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.39% # Bytes accessed per row activation 660system.physmem.bytesPerActivate::43008-43015 387 0.42% 90.82% # Bytes accessed per row activation 661system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.82% # Bytes accessed per row activation 662system.physmem.bytesPerActivate::43264-43271 193 0.21% 91.03% # Bytes accessed per row activation 663system.physmem.bytesPerActivate::43520-43527 69 0.08% 91.10% # Bytes accessed per row activation 664system.physmem.bytesPerActivate::43648-43655 2 0.00% 91.11% # Bytes accessed per row activation 665system.physmem.bytesPerActivate::43776-43783 13 0.01% 91.12% # Bytes accessed per row activation 666system.physmem.bytesPerActivate::43904-43911 2 0.00% 91.12% # Bytes accessed per row activation 667system.physmem.bytesPerActivate::44032-44039 277 0.30% 91.43% # Bytes accessed per row activation 668system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.43% # Bytes accessed per row activation 669system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.43% # Bytes accessed per row activation 670system.physmem.bytesPerActivate::44288-44295 139 0.15% 91.58% # Bytes accessed per row activation 671system.physmem.bytesPerActivate::44544-44551 17 0.02% 91.60% # Bytes accessed per row activation 672system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.60% # Bytes accessed per row activation 673system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.61% # Bytes accessed per row activation 674system.physmem.bytesPerActivate::44800-44807 11 0.01% 91.62% # Bytes accessed per row activation 675system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.62% # Bytes accessed per row activation 676system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.62% # Bytes accessed per row activation 677system.physmem.bytesPerActivate::45056-45063 459 0.50% 92.12% # Bytes accessed per row activation 678system.physmem.bytesPerActivate::45184-45191 1 0.00% 92.12% # Bytes accessed per row activation 679system.physmem.bytesPerActivate::45312-45319 99 0.11% 92.23% # Bytes accessed per row activation 680system.physmem.bytesPerActivate::45376-45383 3 0.00% 92.23% # Bytes accessed per row activation 681system.physmem.bytesPerActivate::45440-45447 3 0.00% 92.24% # Bytes accessed per row activation 682system.physmem.bytesPerActivate::45568-45575 148 0.16% 92.40% # Bytes accessed per row activation 683system.physmem.bytesPerActivate::45696-45703 2 0.00% 92.40% # Bytes accessed per row activation |
| 694system.physmem.bytesPerActivate::45760-45767 1 0.00% 92.40% # Bytes accessed per row activation | 684system.physmem.bytesPerActivate::45760-45767 1 0.00% 92.40% # Bytes accessed per row activation |
| 695system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.49% # Bytes accessed per row activation 696system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.49% # Bytes accessed per row activation 697system.physmem.bytesPerActivate::46080-46087 326 0.36% 92.85% # Bytes accessed per row activation 698system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.85% # Bytes accessed per row activation 699system.physmem.bytesPerActivate::46336-46343 68 0.07% 92.92% # Bytes accessed per row activation 700system.physmem.bytesPerActivate::46400-46407 1 0.00% 92.92% # Bytes accessed per row activation 701system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.92% # Bytes accessed per row activation 702system.physmem.bytesPerActivate::46592-46599 144 0.16% 93.08% # Bytes accessed per row activation 703system.physmem.bytesPerActivate::46656-46663 1 0.00% 93.08% # Bytes accessed per row activation 704system.physmem.bytesPerActivate::46720-46727 1 0.00% 93.08% # Bytes accessed per row activation 705system.physmem.bytesPerActivate::46848-46855 21 0.02% 93.11% # Bytes accessed per row activation 706system.physmem.bytesPerActivate::46912-46919 1 0.00% 93.11% # Bytes accessed per row activation 707system.physmem.bytesPerActivate::46976-46983 2 0.00% 93.11% # Bytes accessed per row activation 708system.physmem.bytesPerActivate::47104-47111 330 0.36% 93.47% # Bytes accessed per row activation 709system.physmem.bytesPerActivate::47168-47175 2 0.00% 93.47% # Bytes accessed per row activation 710system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.47% # Bytes accessed per row activation 711system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.56% # Bytes accessed per row activation 712system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.56% # Bytes accessed per row activation 713system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.56% # Bytes accessed per row activation 714system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.56% # Bytes accessed per row activation 715system.physmem.bytesPerActivate::47616-47623 85 0.09% 93.65% # Bytes accessed per row activation 716system.physmem.bytesPerActivate::47744-47751 2 0.00% 93.66% # Bytes accessed per row activation 717system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.68% # Bytes accessed per row activation 718system.physmem.bytesPerActivate::48000-48007 2 0.00% 93.68% # Bytes accessed per row activation 719system.physmem.bytesPerActivate::48128-48135 398 0.43% 94.11% # Bytes accessed per row activation 720system.physmem.bytesPerActivate::48384-48391 77 0.08% 94.20% # Bytes accessed per row activation 721system.physmem.bytesPerActivate::48512-48519 1 0.00% 94.20% # Bytes accessed per row activation 722system.physmem.bytesPerActivate::48640-48647 140 0.15% 94.35% # Bytes accessed per row activation 723system.physmem.bytesPerActivate::48768-48775 56 0.06% 94.41% # Bytes accessed per row activation 724system.physmem.bytesPerActivate::48896-48903 70 0.08% 94.49% # Bytes accessed per row activation 725system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.49% # Bytes accessed per row activation 726system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.49% # Bytes accessed per row activation 727system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.50% # Bytes accessed per row activation 728system.physmem.bytesPerActivate::49152-49159 5010 5.47% 99.96% # Bytes accessed per row activation 729system.physmem.bytesPerActivate::49600-49607 2 0.00% 99.97% # Bytes accessed per row activation 730system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation | 685system.physmem.bytesPerActivate::45824-45831 151 0.17% 92.57% # Bytes accessed per row activation 686system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.57% # Bytes accessed per row activation 687system.physmem.bytesPerActivate::46080-46087 285 0.31% 92.88% # Bytes accessed per row activation 688system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.88% # Bytes accessed per row activation 689system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.88% # Bytes accessed per row activation 690system.physmem.bytesPerActivate::46336-46343 17 0.02% 92.90% # Bytes accessed per row activation 691system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.90% # Bytes accessed per row activation 692system.physmem.bytesPerActivate::46592-46599 140 0.15% 93.05% # Bytes accessed per row activation 693system.physmem.bytesPerActivate::46720-46727 2 0.00% 93.06% # Bytes accessed per row activation 694system.physmem.bytesPerActivate::46848-46855 15 0.02% 93.07% # Bytes accessed per row activation 695system.physmem.bytesPerActivate::47104-47111 339 0.37% 93.44% # Bytes accessed per row activation 696system.physmem.bytesPerActivate::47296-47303 2 0.00% 93.45% # Bytes accessed per row activation 697system.physmem.bytesPerActivate::47360-47367 80 0.09% 93.53% # Bytes accessed per row activation 698system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.53% # Bytes accessed per row activation 699system.physmem.bytesPerActivate::47616-47623 79 0.09% 93.62% # Bytes accessed per row activation 700system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.62% # Bytes accessed per row activation 701system.physmem.bytesPerActivate::47872-47879 82 0.09% 93.71% # Bytes accessed per row activation 702system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.72% # Bytes accessed per row activation 703system.physmem.bytesPerActivate::48128-48135 389 0.43% 94.14% # Bytes accessed per row activation 704system.physmem.bytesPerActivate::48192-48199 1 0.00% 94.14% # Bytes accessed per row activation 705system.physmem.bytesPerActivate::48320-48327 1 0.00% 94.14% # Bytes accessed per row activation 706system.physmem.bytesPerActivate::48384-48391 92 0.10% 94.24% # Bytes accessed per row activation 707system.physmem.bytesPerActivate::48640-48647 12 0.01% 94.26% # Bytes accessed per row activation 708system.physmem.bytesPerActivate::48704-48711 2 0.00% 94.26% # Bytes accessed per row activation 709system.physmem.bytesPerActivate::48768-48775 69 0.08% 94.33% # Bytes accessed per row activation 710system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.41% # Bytes accessed per row activation 711system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.41% # Bytes accessed per row activation 712system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.42% # Bytes accessed per row activation 713system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.42% # Bytes accessed per row activation 714system.physmem.bytesPerActivate::49152-49159 5070 5.54% 99.96% # Bytes accessed per row activation 715system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.96% # Bytes accessed per row activation 716system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.96% # Bytes accessed per row activation 717system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation 718system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.97% # Bytes accessed per row activation |
| 731system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation | 719system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation |
| 732system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation | 720system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.97% # Bytes accessed per row activation |
| 733system.physmem.bytesPerActivate::50112-50119 2 0.00% 99.97% # Bytes accessed per row activation | 721system.physmem.bytesPerActivate::50112-50119 2 0.00% 99.97% # Bytes accessed per row activation |
| 734system.physmem.bytesPerActivate::50240-50247 2 0.00% 99.97% # Bytes accessed per row activation 735system.physmem.bytesPerActivate::50432-50439 1 0.00% 99.97% # Bytes accessed per row activation 736system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation 737system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation 738system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation 739system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation 740system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation 741system.physmem.bytesPerActivate::51136-51143 2 0.00% 99.98% # Bytes accessed per row activation 742system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.98% # Bytes accessed per row activation 743system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation 744system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation 745system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation 746system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation 747system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation 748system.physmem.bytesPerActivate::51776-51783 1 0.00% 100.00% # Bytes accessed per row activation | 722system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation 723system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation 724system.physmem.bytesPerActivate::50368-50375 3 0.00% 99.98% # Bytes accessed per row activation 725system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.98% # Bytes accessed per row activation 726system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation 727system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation 728system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation 729system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.98% # Bytes accessed per row activation 730system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.99% # Bytes accessed per row activation 731system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.99% # Bytes accessed per row activation 732system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.99% # Bytes accessed per row activation 733system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation 734system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation 735system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation 736system.physmem.bytesPerActivate::51584-51591 2 0.00% 100.00% # Bytes accessed per row activation 737system.physmem.bytesPerActivate::51648-51655 1 0.00% 100.00% # Bytes accessed per row activation |
| 749system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation | 738system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation |
| 750system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation 751system.physmem.bytesPerActivate::52032-52039 1 0.00% 100.00% # Bytes accessed per row activation 752system.physmem.bytesPerActivate::total 91629 # Bytes accessed per row activation 753system.physmem.totQLat 370859657500 # Total ticks spent queuing 754system.physmem.totMemAccLat 464833837500 # Total ticks spent from burst creation until serviced by the DRAM 755system.physmem.totBusLat 76318685000 # Total ticks spent in databus transfers 756system.physmem.totBankLat 17655495000 # Total ticks spent accessing banks 757system.physmem.avgQLat 24296.78 # Average queueing delay per DRAM burst 758system.physmem.avgBankLat 1156.70 # Average bank access latency per DRAM burst | 739system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation 740system.physmem.bytesPerActivate::52224-52231 1 0.00% 100.00% # Bytes accessed per row activation 741system.physmem.bytesPerActivate::total 91489 # Bytes accessed per row activation 742system.physmem.totQLat 370803624750 # Total ticks spent queuing 743system.physmem.totMemAccLat 464795231000 # Total ticks spent from burst creation until serviced by the DRAM 744system.physmem.totBusLat 76315665000 # Total ticks spent in databus transfers 745system.physmem.totBankLat 17675941250 # Total ticks spent accessing banks 746system.physmem.avgQLat 24294.07 # Average queueing delay per DRAM burst 747system.physmem.avgBankLat 1158.08 # Average bank access latency per DRAM burst |
| 759system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 748system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 760system.physmem.avgMemAccLat 30453.48 # Average memory access latency per DRAM burst 761system.physmem.avgRdBW 374.91 # Average DRAM read bandwidth in MiByte/s 762system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s 763system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s 764system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s | 749system.physmem.avgMemAccLat 30452.15 # Average memory access latency per DRAM burst 750system.physmem.avgRdBW 374.90 # Average DRAM read bandwidth in MiByte/s 751system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s 752system.physmem.avgRdBWSys 50.48 # Average system read bandwidth in MiByte/s 753system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s |
| 765system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 766system.physmem.busUtil 2.95 # Data bus utilization in percentage 767system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads 768system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 769system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing | 754system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 755system.physmem.busUtil 2.95 # Data bus utilization in percentage 756system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads 757system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 758system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing |
| 770system.physmem.avgWrQLen 12.21 # Average write queue length when enqueuing 771system.physmem.readRowHits 15189856 # Number of row buffer hits during reads 772system.physmem.writeRowHits 98161 # Number of row buffer hits during writes | 759system.physmem.avgWrQLen 14.44 # Average write queue length when enqueuing 760system.physmem.readRowHits 15189237 # Number of row buffer hits during reads 761system.physmem.writeRowHits 97938 # Number of row buffer hits during writes |
| 773system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads | 762system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads |
| 774system.physmem.writeRowHitRate 84.68 # Row buffer hit rate for writes 775system.physmem.avgGap 161575.49 # Average gap between requests | 763system.physmem.writeRowHitRate 84.76 # Row buffer hit rate for writes 764system.physmem.avgGap 161581.71 # Average gap between requests |
| 776system.physmem.pageHitRate 99.40 # Row buffer hit rate, read and write combined | 765system.physmem.pageHitRate 99.40 # Row buffer hit rate, read and write combined |
| 777system.physmem.prechargeAllPercent 2.44 # Percentage of time for which DRAM has all the banks in precharge state | 766system.physmem.prechargeAllPercent 2.46 # Percentage of time for which DRAM has all the banks in precharge state |
| 778system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 779system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 780system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 781system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 782system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 783system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 784system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 785system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 786system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 787system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 788system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 789system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) 790system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 791system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 792system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) 793system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 794system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 795system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) | 767system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 768system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 769system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 770system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 771system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 772system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 773system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 774system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 775system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 776system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 777system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 778system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) 779system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 780system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 781system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) 782system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 783system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 784system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) |
| 796system.membus.throughput 54229250 # Throughput (bytes/s) 797system.membus.trans_dist::ReadReq 16352579 # Transaction distribution 798system.membus.trans_dist::ReadResp 16352579 # Transaction distribution 799system.membus.trans_dist::WriteReq 769165 # Transaction distribution 800system.membus.trans_dist::WriteResp 769165 # Transaction distribution 801system.membus.trans_dist::Writeback 66909 # Transaction distribution 802system.membus.trans_dist::UpgradeReq 35978 # Transaction distribution 803system.membus.trans_dist::SCUpgradeReq 18300 # Transaction distribution 804system.membus.trans_dist::UpgradeResp 14191 # Transaction distribution 805system.membus.trans_dist::ReadExReq 138286 # Transaction distribution 806system.membus.trans_dist::ReadExResp 137908 # Transaction distribution 807system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384274 # Packet count per connected master and slave (bytes) | 785system.membus.throughput 54211188 # Throughput (bytes/s) 786system.membus.trans_dist::ReadReq 16352626 # Transaction distribution 787system.membus.trans_dist::ReadResp 16352626 # Transaction distribution 788system.membus.trans_dist::WriteReq 769179 # Transaction distribution 789system.membus.trans_dist::WriteResp 769179 # Transaction distribution 790system.membus.trans_dist::Writeback 66581 # Transaction distribution 791system.membus.trans_dist::UpgradeReq 35757 # Transaction distribution 792system.membus.trans_dist::SCUpgradeReq 18322 # Transaction distribution 793system.membus.trans_dist::UpgradeResp 14211 # Transaction distribution 794system.membus.trans_dist::ReadExReq 137874 # Transaction distribution 795system.membus.trans_dist::ReadExResp 137463 # Transaction distribution 796system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384372 # Packet count per connected master and slave (bytes) |
| 808system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) | 797system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) |
| 809system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13828 # Packet count per connected master and slave (bytes) | 798system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13818 # Packet count per connected master and slave (bytes) |
| 810system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 811system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) | 799system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 800system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) |
| 812system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1977266 # Packet count per connected master and slave (bytes) 813system.membus.pkt_count_system.l2c.mem_side::total 4377428 # Packet count per connected master and slave (bytes) | 801system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975936 # Packet count per connected master and slave (bytes) 802system.membus.pkt_count_system.l2c.mem_side::total 4376186 # Packet count per connected master and slave (bytes) |
| 814system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 815system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) | 803system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 804system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) |
| 816system.membus.pkt_count::total 34655060 # Packet count per connected master and slave (bytes) 817system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392545 # Cumulative packet size per connected master and slave (bytes) | 805system.membus.pkt_count::total 34653818 # Packet count per connected master and slave (bytes) 806system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392693 # Cumulative packet size per connected master and slave (bytes) |
| 818system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) | 807system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) |
| 819system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27656 # Cumulative packet size per connected master and slave (bytes) | 808system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27636 # Cumulative packet size per connected master and slave (bytes) |
| 820system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 821system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) | 809system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 810system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) |
| 822system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17766916 # Cumulative packet size per connected master and slave (bytes) 823system.membus.tot_pkt_size_system.l2c.mem_side::total 20191657 # Cumulative packet size per connected master and slave (bytes) | 811system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17718532 # Cumulative packet size per connected master and slave (bytes) 812system.membus.tot_pkt_size_system.l2c.mem_side::total 20143401 # Cumulative packet size per connected master and slave (bytes) |
| 824system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 825system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) | 813system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 814system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) |
| 826system.membus.tot_pkt_size::total 141302185 # Cumulative packet size per connected master and slave (bytes) 827system.membus.data_through_bus 141302185 # Total data (bytes) | 815system.membus.tot_pkt_size::total 141253929 # Cumulative packet size per connected master and slave (bytes) 816system.membus.data_through_bus 141253929 # Total data (bytes) |
| 828system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 817system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 829system.membus.reqLayer0.occupancy 1488154000 # Layer occupancy (ticks) | 818system.membus.reqLayer0.occupancy 1488197499 # Layer occupancy (ticks) |
| 830system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 819system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 831system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) | 820system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) |
| 832system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 821system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 833system.membus.reqLayer2.occupancy 11766000 # Layer occupancy (ticks) | 822system.membus.reqLayer2.occupancy 11766500 # Layer occupancy (ticks) |
| 834system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 835system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 836system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 823system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 824system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 825system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 837system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) | 826system.membus.reqLayer5.occupancy 1797499 # Layer occupancy (ticks) |
| 838system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 827system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 839system.membus.reqLayer6.occupancy 17661743000 # Layer occupancy (ticks) | 828system.membus.reqLayer6.occupancy 17658492000 # Layer occupancy (ticks) |
| 840system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 829system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 841system.membus.respLayer1.occupancy 4847485258 # Layer occupancy (ticks) | 830system.membus.respLayer1.occupancy 4844234238 # Layer occupancy (ticks) |
| 842system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 831system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 843system.membus.respLayer2.occupancy 34183780195 # Layer occupancy (ticks) | 832system.membus.respLayer2.occupancy 34183641699 # Layer occupancy (ticks) |
| 844system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 845system.cpu_clk_domain.clock 500 # Clock period in ticks | 833system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 834system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 846system.l2c.tags.replacements 73073 # number of replacements 847system.l2c.tags.tagsinuse 53003.397460 # Cycle average of tags in use 848system.l2c.tags.total_refs 1874154 # Total number of references to valid blocks. 849system.l2c.tags.sampled_refs 138227 # Sample count of references to valid blocks. 850system.l2c.tags.avg_refs 13.558523 # Average number of references to valid blocks. | 835system.l2c.tags.replacements 72645 # number of replacements 836system.l2c.tags.tagsinuse 53020.689119 # Cycle average of tags in use 837system.l2c.tags.total_refs 1874829 # Total number of references to valid blocks. 838system.l2c.tags.sampled_refs 137818 # Sample count of references to valid blocks. 839system.l2c.tags.avg_refs 13.603658 # Average number of references to valid blocks. |
| 851system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 840system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 852system.l2c.tags.occ_blocks::writebacks 37718.016524 # Average occupied blocks per requestor 853system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.174616 # Average occupied blocks per requestor | 841system.l2c.tags.occ_blocks::writebacks 37720.403327 # Average occupied blocks per requestor 842system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.416210 # Average occupied blocks per requestor |
| 854system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000363 # Average occupied blocks per requestor | 843system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000363 # Average occupied blocks per requestor |
| 855system.l2c.tags.occ_blocks::cpu0.inst 4163.072469 # Average occupied blocks per requestor 856system.l2c.tags.occ_blocks::cpu0.data 2965.510583 # Average occupied blocks per requestor 857system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.620056 # Average occupied blocks per requestor 858system.l2c.tags.occ_blocks::cpu1.inst 4041.319246 # Average occupied blocks per requestor 859system.l2c.tags.occ_blocks::cpu1.data 4099.683602 # Average occupied blocks per requestor 860system.l2c.tags.occ_percent::writebacks 0.575531 # Average percentage of cache occupancy 861system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy | 844system.l2c.tags.occ_blocks::cpu0.inst 4180.066464 # Average occupied blocks per requestor 845system.l2c.tags.occ_blocks::cpu0.data 2958.458343 # Average occupied blocks per requestor 846system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.364086 # Average occupied blocks per requestor 847system.l2c.tags.occ_blocks::cpu1.inst 4038.603525 # Average occupied blocks per requestor 848system.l2c.tags.occ_blocks::cpu1.data 4106.376802 # Average occupied blocks per requestor 849system.l2c.tags.occ_percent::writebacks 0.575568 # Average percentage of cache occupancy 850system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy |
| 862system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 851system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 863system.l2c.tags.occ_percent::cpu0.inst 0.063523 # Average percentage of cache occupancy 864system.l2c.tags.occ_percent::cpu0.data 0.045250 # Average percentage of cache occupancy 865system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy 866system.l2c.tags.occ_percent::cpu1.inst 0.061666 # Average percentage of cache occupancy 867system.l2c.tags.occ_percent::cpu1.data 0.062556 # Average percentage of cache occupancy 868system.l2c.tags.occ_percent::total 0.808768 # Average percentage of cache occupancy 869system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 870system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id 871system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 872system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 873system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 874system.l2c.tags.age_task_id_blocks_1024::2 3081 # Occupied blocks per task id 875system.l2c.tags.age_task_id_blocks_1024::3 9065 # Occupied blocks per task id 876system.l2c.tags.age_task_id_blocks_1024::4 52647 # Occupied blocks per task id 877system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 878system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id 879system.l2c.tags.tag_accesses 18858156 # Number of tag accesses 880system.l2c.tags.data_accesses 18858156 # Number of data accesses 881system.l2c.ReadReq_hits::cpu0.dtb.walker 22538 # number of ReadReq hits 882system.l2c.ReadReq_hits::cpu0.itb.walker 4343 # number of ReadReq hits 883system.l2c.ReadReq_hits::cpu0.inst 393811 # number of ReadReq hits 884system.l2c.ReadReq_hits::cpu0.data 165625 # number of ReadReq hits 885system.l2c.ReadReq_hits::cpu1.dtb.walker 33531 # number of ReadReq hits 886system.l2c.ReadReq_hits::cpu1.itb.walker 5781 # number of ReadReq hits 887system.l2c.ReadReq_hits::cpu1.inst 608221 # number of ReadReq hits 888system.l2c.ReadReq_hits::cpu1.data 201520 # number of ReadReq hits 889system.l2c.ReadReq_hits::total 1435370 # number of ReadReq hits 890system.l2c.Writeback_hits::writebacks 583255 # number of Writeback hits 891system.l2c.Writeback_hits::total 583255 # number of Writeback hits 892system.l2c.UpgradeReq_hits::cpu0.data 1158 # number of UpgradeReq hits 893system.l2c.UpgradeReq_hits::cpu1.data 763 # number of UpgradeReq hits 894system.l2c.UpgradeReq_hits::total 1921 # number of UpgradeReq hits 895system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits 896system.l2c.SCUpgradeReq_hits::cpu1.data 161 # number of SCUpgradeReq hits 897system.l2c.SCUpgradeReq_hits::total 371 # number of SCUpgradeReq hits 898system.l2c.ReadExReq_hits::cpu0.data 47894 # number of ReadExReq hits 899system.l2c.ReadExReq_hits::cpu1.data 59257 # number of ReadExReq hits 900system.l2c.ReadExReq_hits::total 107151 # number of ReadExReq hits 901system.l2c.demand_hits::cpu0.dtb.walker 22538 # number of demand (read+write) hits 902system.l2c.demand_hits::cpu0.itb.walker 4343 # number of demand (read+write) hits 903system.l2c.demand_hits::cpu0.inst 393811 # number of demand (read+write) hits 904system.l2c.demand_hits::cpu0.data 213519 # number of demand (read+write) hits 905system.l2c.demand_hits::cpu1.dtb.walker 33531 # number of demand (read+write) hits 906system.l2c.demand_hits::cpu1.itb.walker 5781 # number of demand (read+write) hits 907system.l2c.demand_hits::cpu1.inst 608221 # number of demand (read+write) hits 908system.l2c.demand_hits::cpu1.data 260777 # number of demand (read+write) hits 909system.l2c.demand_hits::total 1542521 # number of demand (read+write) hits 910system.l2c.overall_hits::cpu0.dtb.walker 22538 # number of overall hits 911system.l2c.overall_hits::cpu0.itb.walker 4343 # number of overall hits 912system.l2c.overall_hits::cpu0.inst 393811 # number of overall hits 913system.l2c.overall_hits::cpu0.data 213519 # number of overall hits 914system.l2c.overall_hits::cpu1.dtb.walker 33531 # number of overall hits 915system.l2c.overall_hits::cpu1.itb.walker 5781 # number of overall hits 916system.l2c.overall_hits::cpu1.inst 608221 # number of overall hits 917system.l2c.overall_hits::cpu1.data 260777 # number of overall hits 918system.l2c.overall_hits::total 1542521 # number of overall hits | 852system.l2c.tags.occ_percent::cpu0.inst 0.063783 # Average percentage of cache occupancy 853system.l2c.tags.occ_percent::cpu0.data 0.045142 # Average percentage of cache occupancy 854system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000173 # Average percentage of cache occupancy 855system.l2c.tags.occ_percent::cpu1.inst 0.061624 # Average percentage of cache occupancy 856system.l2c.tags.occ_percent::cpu1.data 0.062658 # Average percentage of cache occupancy 857system.l2c.tags.occ_percent::total 0.809032 # Average percentage of cache occupancy 858system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 859system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id 860system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 861system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 862system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id 863system.l2c.tags.age_task_id_blocks_1024::2 3126 # Occupied blocks per task id 864system.l2c.tags.age_task_id_blocks_1024::3 8643 # Occupied blocks per task id 865system.l2c.tags.age_task_id_blocks_1024::4 53076 # Occupied blocks per task id 866system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 867system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 868system.l2c.tags.tag_accesses 18857930 # Number of tag accesses 869system.l2c.tags.data_accesses 18857930 # Number of data accesses 870system.l2c.ReadReq_hits::cpu0.dtb.walker 23180 # number of ReadReq hits 871system.l2c.ReadReq_hits::cpu0.itb.walker 4676 # number of ReadReq hits 872system.l2c.ReadReq_hits::cpu0.inst 393299 # number of ReadReq hits 873system.l2c.ReadReq_hits::cpu0.data 166186 # number of ReadReq hits 874system.l2c.ReadReq_hits::cpu1.dtb.walker 33047 # number of ReadReq hits 875system.l2c.ReadReq_hits::cpu1.itb.walker 5717 # number of ReadReq hits 876system.l2c.ReadReq_hits::cpu1.inst 607435 # number of ReadReq hits 877system.l2c.ReadReq_hits::cpu1.data 201334 # number of ReadReq hits 878system.l2c.ReadReq_hits::total 1434874 # number of ReadReq hits 879system.l2c.Writeback_hits::writebacks 583828 # number of Writeback hits 880system.l2c.Writeback_hits::total 583828 # number of Writeback hits 881system.l2c.UpgradeReq_hits::cpu0.data 1113 # number of UpgradeReq hits 882system.l2c.UpgradeReq_hits::cpu1.data 796 # number of UpgradeReq hits 883system.l2c.UpgradeReq_hits::total 1909 # number of UpgradeReq hits 884system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits 885system.l2c.SCUpgradeReq_hits::cpu1.data 162 # number of SCUpgradeReq hits 886system.l2c.SCUpgradeReq_hits::total 374 # number of SCUpgradeReq hits 887system.l2c.ReadExReq_hits::cpu0.data 48382 # number of ReadExReq hits 888system.l2c.ReadExReq_hits::cpu1.data 59141 # number of ReadExReq hits 889system.l2c.ReadExReq_hits::total 107523 # number of ReadExReq hits 890system.l2c.demand_hits::cpu0.dtb.walker 23180 # number of demand (read+write) hits 891system.l2c.demand_hits::cpu0.itb.walker 4676 # number of demand (read+write) hits 892system.l2c.demand_hits::cpu0.inst 393299 # number of demand (read+write) hits 893system.l2c.demand_hits::cpu0.data 214568 # number of demand (read+write) hits 894system.l2c.demand_hits::cpu1.dtb.walker 33047 # number of demand (read+write) hits 895system.l2c.demand_hits::cpu1.itb.walker 5717 # number of demand (read+write) hits 896system.l2c.demand_hits::cpu1.inst 607435 # number of demand (read+write) hits 897system.l2c.demand_hits::cpu1.data 260475 # number of demand (read+write) hits 898system.l2c.demand_hits::total 1542397 # number of demand (read+write) hits 899system.l2c.overall_hits::cpu0.dtb.walker 23180 # number of overall hits 900system.l2c.overall_hits::cpu0.itb.walker 4676 # number of overall hits 901system.l2c.overall_hits::cpu0.inst 393299 # number of overall hits 902system.l2c.overall_hits::cpu0.data 214568 # number of overall hits 903system.l2c.overall_hits::cpu1.dtb.walker 33047 # number of overall hits 904system.l2c.overall_hits::cpu1.itb.walker 5717 # number of overall hits 905system.l2c.overall_hits::cpu1.inst 607435 # number of overall hits 906system.l2c.overall_hits::cpu1.data 260475 # number of overall hits 907system.l2c.overall_hits::total 1542397 # number of overall hits |
| 919system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses 920system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 908system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses 909system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 921system.l2c.ReadReq_misses::cpu0.inst 6016 # number of ReadReq misses 922system.l2c.ReadReq_misses::cpu0.data 6332 # number of ReadReq misses 923system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses 924system.l2c.ReadReq_misses::cpu1.inst 6652 # number of ReadReq misses 925system.l2c.ReadReq_misses::cpu1.data 6334 # number of ReadReq misses 926system.l2c.ReadReq_misses::total 25365 # number of ReadReq misses 927system.l2c.UpgradeReq_misses::cpu0.data 5730 # number of UpgradeReq misses 928system.l2c.UpgradeReq_misses::cpu1.data 4444 # number of UpgradeReq misses 929system.l2c.UpgradeReq_misses::total 10174 # number of UpgradeReq misses 930system.l2c.SCUpgradeReq_misses::cpu0.data 769 # number of SCUpgradeReq misses 931system.l2c.SCUpgradeReq_misses::cpu1.data 591 # number of SCUpgradeReq misses 932system.l2c.SCUpgradeReq_misses::total 1360 # number of SCUpgradeReq misses 933system.l2c.ReadExReq_misses::cpu0.data 63376 # number of ReadExReq misses 934system.l2c.ReadExReq_misses::cpu1.data 77189 # number of ReadExReq misses 935system.l2c.ReadExReq_misses::total 140565 # number of ReadExReq misses | 910system.l2c.ReadReq_misses::cpu0.inst 6052 # number of ReadReq misses 911system.l2c.ReadReq_misses::cpu0.data 6313 # number of ReadReq misses 912system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses 913system.l2c.ReadReq_misses::cpu1.inst 6634 # number of ReadReq misses 914system.l2c.ReadReq_misses::cpu1.data 6349 # number of ReadReq misses 915system.l2c.ReadReq_misses::total 25380 # number of ReadReq misses 916system.l2c.UpgradeReq_misses::cpu0.data 5741 # number of UpgradeReq misses 917system.l2c.UpgradeReq_misses::cpu1.data 4448 # number of UpgradeReq misses 918system.l2c.UpgradeReq_misses::total 10189 # number of UpgradeReq misses 919system.l2c.SCUpgradeReq_misses::cpu0.data 772 # number of SCUpgradeReq misses 920system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses 921system.l2c.SCUpgradeReq_misses::total 1361 # number of SCUpgradeReq misses 922system.l2c.ReadExReq_misses::cpu0.data 63128 # number of ReadExReq misses 923system.l2c.ReadExReq_misses::cpu1.data 76996 # number of ReadExReq misses 924system.l2c.ReadExReq_misses::total 140124 # number of ReadExReq misses |
| 936system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses 937system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 925system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses 926system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 938system.l2c.demand_misses::cpu0.inst 6016 # number of demand (read+write) misses 939system.l2c.demand_misses::cpu0.data 69708 # number of demand (read+write) misses 940system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses 941system.l2c.demand_misses::cpu1.inst 6652 # number of demand (read+write) misses 942system.l2c.demand_misses::cpu1.data 83523 # number of demand (read+write) misses 943system.l2c.demand_misses::total 165930 # number of demand (read+write) misses | 927system.l2c.demand_misses::cpu0.inst 6052 # number of demand (read+write) misses 928system.l2c.demand_misses::cpu0.data 69441 # number of demand (read+write) misses 929system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses 930system.l2c.demand_misses::cpu1.inst 6634 # number of demand (read+write) misses 931system.l2c.demand_misses::cpu1.data 83345 # number of demand (read+write) misses 932system.l2c.demand_misses::total 165504 # number of demand (read+write) misses |
| 944system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses 945system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 933system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses 934system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 946system.l2c.overall_misses::cpu0.inst 6016 # number of overall misses 947system.l2c.overall_misses::cpu0.data 69708 # number of overall misses 948system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses 949system.l2c.overall_misses::cpu1.inst 6652 # number of overall misses 950system.l2c.overall_misses::cpu1.data 83523 # number of overall misses 951system.l2c.overall_misses::total 165930 # number of overall misses 952system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1304750 # number of ReadReq miss cycles | 935system.l2c.overall_misses::cpu0.inst 6052 # number of overall misses 936system.l2c.overall_misses::cpu0.data 69441 # number of overall misses 937system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses 938system.l2c.overall_misses::cpu1.inst 6634 # number of overall misses 939system.l2c.overall_misses::cpu1.data 83345 # number of overall misses 940system.l2c.overall_misses::total 165504 # number of overall misses 941system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1319500 # number of ReadReq miss cycles |
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number of demand (read+write) accesses 1013system.l2c.demand_accesses::total 1708451 # number of demand (read+write) accesses 1014system.l2c.overall_accesses::cpu0.dtb.walker 22551 # number of overall (read+write) accesses 1015system.l2c.overall_accesses::cpu0.itb.walker 4345 # number of overall (read+write) accesses 1016system.l2c.overall_accesses::cpu0.inst 399827 # number of overall (read+write) accesses 1017system.l2c.overall_accesses::cpu0.data 283227 # number of overall (read+write) accesses 1018system.l2c.overall_accesses::cpu1.dtb.walker 33547 # number of overall (read+write) accesses 1019system.l2c.overall_accesses::cpu1.itb.walker 5781 # number of overall (read+write) accesses 1020system.l2c.overall_accesses::cpu1.inst 614873 # number of overall (read+write) accesses 1021system.l2c.overall_accesses::cpu1.data 344300 # number of overall (read+write) accesses 1022system.l2c.overall_accesses::total 1708451 # number of overall (read+write) accesses 1023system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000576 # miss rate for ReadReq accesses 1024system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000460 # miss rate for ReadReq accesses 1025system.l2c.ReadReq_miss_rate::cpu0.inst 0.015047 # miss rate for ReadReq accesses 1026system.l2c.ReadReq_miss_rate::cpu0.data 0.036823 # miss rate for ReadReq accesses 1027system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000477 # miss rate for ReadReq accesses 1028system.l2c.ReadReq_miss_rate::cpu1.inst 0.010818 # miss rate for ReadReq accesses 1029system.l2c.ReadReq_miss_rate::cpu1.data 0.030473 # miss rate for ReadReq accesses 1030system.l2c.ReadReq_miss_rate::total 0.017365 # miss rate for ReadReq accesses 1031system.l2c.UpgradeReq_miss_rate::cpu0.data 0.831882 # miss rate for UpgradeReq accesses 1032system.l2c.UpgradeReq_miss_rate::cpu1.data 0.853466 # miss rate for UpgradeReq accesses 1033system.l2c.UpgradeReq_miss_rate::total 0.841174 # miss rate for UpgradeReq accesses 1034system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.785495 # miss rate for SCUpgradeReq accesses 1035system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.785904 # miss rate for SCUpgradeReq accesses 1036system.l2c.SCUpgradeReq_miss_rate::total 0.785673 # miss rate for SCUpgradeReq accesses 1037system.l2c.ReadExReq_miss_rate::cpu0.data 0.569570 # miss rate for ReadExReq accesses 1038system.l2c.ReadExReq_miss_rate::cpu1.data 0.565711 # miss rate for ReadExReq accesses 1039system.l2c.ReadExReq_miss_rate::total 0.567444 # miss rate for ReadExReq accesses 1040system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000576 # miss rate for demand accesses 1041system.l2c.demand_miss_rate::cpu0.itb.walker 0.000460 # miss rate for demand accesses 1042system.l2c.demand_miss_rate::cpu0.inst 0.015047 # miss rate for demand accesses 1043system.l2c.demand_miss_rate::cpu0.data 0.246121 # miss rate for demand accesses 1044system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000477 # miss rate for demand accesses 1045system.l2c.demand_miss_rate::cpu1.inst 0.010818 # miss rate for demand accesses 1046system.l2c.demand_miss_rate::cpu1.data 0.242588 # miss rate for demand accesses 1047system.l2c.demand_miss_rate::total 0.097123 # miss rate for demand accesses 1048system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000576 # miss rate for overall accesses 1049system.l2c.overall_miss_rate::cpu0.itb.walker 0.000460 # miss rate for overall accesses 1050system.l2c.overall_miss_rate::cpu0.inst 0.015047 # miss rate for overall accesses 1051system.l2c.overall_miss_rate::cpu0.data 0.246121 # miss rate for overall accesses 1052system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000477 # miss rate for overall accesses 1053system.l2c.overall_miss_rate::cpu1.inst 0.010818 # miss rate for overall accesses 1054system.l2c.overall_miss_rate::cpu1.data 0.242588 # miss rate for overall accesses 1055system.l2c.overall_miss_rate::total 0.097123 # miss rate for overall accesses 1056system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 100365.384615 # average ReadReq miss latency | 968system.l2c.overall_miss_latency::cpu0.inst 442132250 # number of overall miss cycles 969system.l2c.overall_miss_latency::cpu0.data 4889249309 # number of overall miss cycles 970system.l2c.overall_miss_latency::cpu1.dtb.walker 1532000 # number of overall miss cycles 971system.l2c.overall_miss_latency::cpu1.inst 492031750 # number of overall miss cycles 972system.l2c.overall_miss_latency::cpu1.data 6572601771 # number of overall miss cycles 973system.l2c.overall_miss_latency::total 12399314580 # number of overall miss cycles 974system.l2c.ReadReq_accesses::cpu0.dtb.walker 23193 # number of ReadReq accesses(hits+misses) 975system.l2c.ReadReq_accesses::cpu0.itb.walker 4678 # number of ReadReq accesses(hits+misses) 976system.l2c.ReadReq_accesses::cpu0.inst 399351 # number of ReadReq accesses(hits+misses) 977system.l2c.ReadReq_accesses::cpu0.data 172499 # number of ReadReq accesses(hits+misses) 978system.l2c.ReadReq_accesses::cpu1.dtb.walker 33064 # number of ReadReq accesses(hits+misses) 979system.l2c.ReadReq_accesses::cpu1.itb.walker 5717 # number of ReadReq accesses(hits+misses) 980system.l2c.ReadReq_accesses::cpu1.inst 614069 # number of ReadReq accesses(hits+misses) 981system.l2c.ReadReq_accesses::cpu1.data 207683 # number of ReadReq accesses(hits+misses) 982system.l2c.ReadReq_accesses::total 1460254 # number of ReadReq accesses(hits+misses) 983system.l2c.Writeback_accesses::writebacks 583828 # number of Writeback accesses(hits+misses) 984system.l2c.Writeback_accesses::total 583828 # number of Writeback accesses(hits+misses) 985system.l2c.UpgradeReq_accesses::cpu0.data 6854 # number of UpgradeReq accesses(hits+misses) 986system.l2c.UpgradeReq_accesses::cpu1.data 5244 # number of UpgradeReq accesses(hits+misses) 987system.l2c.UpgradeReq_accesses::total 12098 # number of UpgradeReq accesses(hits+misses) 988system.l2c.SCUpgradeReq_accesses::cpu0.data 984 # number of SCUpgradeReq accesses(hits+misses) 989system.l2c.SCUpgradeReq_accesses::cpu1.data 751 # number of SCUpgradeReq accesses(hits+misses) 990system.l2c.SCUpgradeReq_accesses::total 1735 # number of SCUpgradeReq accesses(hits+misses) 991system.l2c.ReadExReq_accesses::cpu0.data 111510 # number of ReadExReq accesses(hits+misses) 992system.l2c.ReadExReq_accesses::cpu1.data 136137 # number of ReadExReq accesses(hits+misses) 993system.l2c.ReadExReq_accesses::total 247647 # number of ReadExReq accesses(hits+misses) 994system.l2c.demand_accesses::cpu0.dtb.walker 23193 # number of demand (read+write) accesses 995system.l2c.demand_accesses::cpu0.itb.walker 4678 # number of demand (read+write) accesses 996system.l2c.demand_accesses::cpu0.inst 399351 # number of demand (read+write) accesses 997system.l2c.demand_accesses::cpu0.data 284009 # number of demand (read+write) accesses 998system.l2c.demand_accesses::cpu1.dtb.walker 33064 # number of demand (read+write) accesses 999system.l2c.demand_accesses::cpu1.itb.walker 5717 # number of demand (read+write) accesses 1000system.l2c.demand_accesses::cpu1.inst 614069 # number of demand (read+write) accesses 1001system.l2c.demand_accesses::cpu1.data 343820 # number of demand (read+write) accesses 1002system.l2c.demand_accesses::total 1707901 # number of demand (read+write) accesses 1003system.l2c.overall_accesses::cpu0.dtb.walker 23193 # number of overall (read+write) accesses 1004system.l2c.overall_accesses::cpu0.itb.walker 4678 # number of overall (read+write) accesses 1005system.l2c.overall_accesses::cpu0.inst 399351 # number of overall (read+write) accesses 1006system.l2c.overall_accesses::cpu0.data 284009 # number of overall (read+write) accesses 1007system.l2c.overall_accesses::cpu1.dtb.walker 33064 # number of overall (read+write) accesses 1008system.l2c.overall_accesses::cpu1.itb.walker 5717 # number of overall (read+write) accesses 1009system.l2c.overall_accesses::cpu1.inst 614069 # number of overall (read+write) accesses 1010system.l2c.overall_accesses::cpu1.data 343820 # number of overall (read+write) accesses 1011system.l2c.overall_accesses::total 1707901 # number of overall (read+write) accesses 1012system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000561 # miss rate for ReadReq accesses 1013system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000428 # miss rate for ReadReq accesses 1014system.l2c.ReadReq_miss_rate::cpu0.inst 0.015155 # miss rate for ReadReq accesses 1015system.l2c.ReadReq_miss_rate::cpu0.data 0.036597 # miss rate for ReadReq accesses 1016system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000514 # miss rate for ReadReq accesses 1017system.l2c.ReadReq_miss_rate::cpu1.inst 0.010803 # miss rate for ReadReq accesses 1018system.l2c.ReadReq_miss_rate::cpu1.data 0.030571 # miss rate for ReadReq accesses 1019system.l2c.ReadReq_miss_rate::total 0.017381 # miss rate for ReadReq accesses 1020system.l2c.UpgradeReq_miss_rate::cpu0.data 0.837613 # miss rate for UpgradeReq accesses 1021system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848207 # miss rate for UpgradeReq accesses 1022system.l2c.UpgradeReq_miss_rate::total 0.842205 # miss rate for UpgradeReq accesses 1023system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784553 # miss rate for SCUpgradeReq accesses 1024system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784288 # miss rate for SCUpgradeReq accesses 1025system.l2c.SCUpgradeReq_miss_rate::total 0.784438 # miss rate for SCUpgradeReq accesses 1026system.l2c.ReadExReq_miss_rate::cpu0.data 0.566120 # miss rate for ReadExReq accesses 1027system.l2c.ReadExReq_miss_rate::cpu1.data 0.565577 # miss rate for ReadExReq accesses 1028system.l2c.ReadExReq_miss_rate::total 0.565822 # miss rate for ReadExReq accesses 1029system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000561 # miss rate for demand accesses 1030system.l2c.demand_miss_rate::cpu0.itb.walker 0.000428 # miss rate for demand accesses 1031system.l2c.demand_miss_rate::cpu0.inst 0.015155 # miss rate for demand accesses 1032system.l2c.demand_miss_rate::cpu0.data 0.244503 # miss rate for demand accesses 1033system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000514 # miss rate for demand accesses 1034system.l2c.demand_miss_rate::cpu1.inst 0.010803 # miss rate for demand accesses 1035system.l2c.demand_miss_rate::cpu1.data 0.242409 # miss rate for demand accesses 1036system.l2c.demand_miss_rate::total 0.096905 # miss rate for demand accesses 1037system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000561 # miss rate for overall accesses 1038system.l2c.overall_miss_rate::cpu0.itb.walker 0.000428 # miss rate for overall accesses 1039system.l2c.overall_miss_rate::cpu0.inst 0.015155 # miss rate for overall accesses 1040system.l2c.overall_miss_rate::cpu0.data 0.244503 # miss rate for overall accesses 1041system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000514 # miss rate for overall accesses 1042system.l2c.overall_miss_rate::cpu1.inst 0.010803 # miss rate for overall accesses 1043system.l2c.overall_miss_rate::cpu1.data 0.242409 # miss rate for overall accesses 1044system.l2c.overall_miss_rate::total 0.096905 # miss rate for overall accesses 1045system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 101500 # average ReadReq miss latency |
| 1057system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 224000 # average ReadReq miss latency | 1046system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 224000 # average ReadReq miss latency |
| 1058system.l2c.ReadReq_avg_miss_latency::cpu0.inst 74222.573138 # average ReadReq miss latency 1059system.l2c.ReadReq_avg_miss_latency::cpu0.data 75137.002527 # average ReadReq miss latency 1060system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 125187.500000 # average ReadReq miss latency 1061system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75756.238725 # average ReadReq miss latency 1062system.l2c.ReadReq_avg_miss_latency::cpu1.data 77378.512630 # average ReadReq miss latency 1063system.l2c.ReadReq_avg_miss_latency::total 75698.491977 # average ReadReq miss latency 1064system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1577.154276 # average UpgradeReq miss latency 1065system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2757.195995 # average UpgradeReq miss latency 1066system.l2c.UpgradeReq_avg_miss_latency::total 2092.596127 # average UpgradeReq miss latency 1067system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 698.279584 # average SCUpgradeReq miss latency 1068system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5398.248731 # average SCUpgradeReq miss latency 1069system.l2c.SCUpgradeReq_avg_miss_latency::total 2740.692647 # average SCUpgradeReq miss latency 1070system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70100.630554 # average ReadExReq miss latency 1071system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79057.343326 # average ReadExReq miss latency 1072system.l2c.ReadExReq_avg_miss_latency::total 75019.064746 # average ReadExReq miss latency 1073system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100365.384615 # average overall miss latency | 1047system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73055.560145 # average ReadReq miss latency 1048system.l2c.ReadReq_avg_miss_latency::cpu0.data 75180.421036 # average ReadReq miss latency 1049system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90117.647059 # average ReadReq miss latency 1050system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74168.186614 # average ReadReq miss latency 1051system.l2c.ReadReq_avg_miss_latency::cpu1.data 77590.880454 # average ReadReq miss latency 1052system.l2c.ReadReq_avg_miss_latency::total 75047.360047 # average ReadReq miss latency 1053system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1610.797074 # average UpgradeReq miss latency 1054system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2813.954137 # average UpgradeReq miss latency 1055system.l2c.UpgradeReq_avg_miss_latency::total 2136.034351 # average UpgradeReq miss latency 1056system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 753.853627 # average SCUpgradeReq miss latency 1057system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5411.480475 # average SCUpgradeReq miss latency 1058system.l2c.SCUpgradeReq_avg_miss_latency::total 2769.534901 # average SCUpgradeReq miss latency 1059system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69931.493331 # average ReadExReq miss latency 1060system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78964.845849 # average ReadExReq miss latency 1061system.l2c.ReadExReq_avg_miss_latency::total 74895.182710 # average ReadExReq miss latency 1062system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101500 # average overall miss latency |
| 1074system.l2c.demand_avg_miss_latency::cpu0.itb.walker 224000 # average overall miss latency | 1063system.l2c.demand_avg_miss_latency::cpu0.itb.walker 224000 # average overall miss latency |
| 1075system.l2c.demand_avg_miss_latency::cpu0.inst 74222.573138 # average overall miss latency 1076system.l2c.demand_avg_miss_latency::cpu0.data 70558.114736 # average overall miss latency 1077system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 125187.500000 # average overall miss latency 1078system.l2c.demand_avg_miss_latency::cpu1.inst 75756.238725 # average overall miss latency 1079system.l2c.demand_avg_miss_latency::cpu1.data 78930.028531 # average overall miss latency 1080system.l2c.demand_avg_miss_latency::total 75122.925842 # average overall miss latency 1081system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100365.384615 # average overall miss latency | 1064system.l2c.demand_avg_miss_latency::cpu0.inst 73055.560145 # average overall miss latency 1065system.l2c.demand_avg_miss_latency::cpu0.data 70408.682320 # average overall miss latency 1066system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90117.647059 # average overall miss latency 1067system.l2c.demand_avg_miss_latency::cpu1.inst 74168.186614 # average overall miss latency 1068system.l2c.demand_avg_miss_latency::cpu1.data 78860.180827 # average overall miss latency 1069system.l2c.demand_avg_miss_latency::total 74918.519069 # average overall miss latency 1070system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101500 # average overall miss latency |
| 1082system.l2c.overall_avg_miss_latency::cpu0.itb.walker 224000 # average overall miss latency | 1071system.l2c.overall_avg_miss_latency::cpu0.itb.walker 224000 # average overall miss latency |
| 1083system.l2c.overall_avg_miss_latency::cpu0.inst 74222.573138 # average overall miss latency 1084system.l2c.overall_avg_miss_latency::cpu0.data 70558.114736 # average overall miss latency 1085system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 125187.500000 # average overall miss latency 1086system.l2c.overall_avg_miss_latency::cpu1.inst 75756.238725 # average overall miss latency 1087system.l2c.overall_avg_miss_latency::cpu1.data 78930.028531 # average overall miss latency 1088system.l2c.overall_avg_miss_latency::total 75122.925842 # average overall miss latency | 1072system.l2c.overall_avg_miss_latency::cpu0.inst 73055.560145 # average overall miss latency 1073system.l2c.overall_avg_miss_latency::cpu0.data 70408.682320 # average overall miss latency 1074system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90117.647059 # average overall miss latency 1075system.l2c.overall_avg_miss_latency::cpu1.inst 74168.186614 # average overall miss latency 1076system.l2c.overall_avg_miss_latency::cpu1.data 78860.180827 # average overall miss latency 1077system.l2c.overall_avg_miss_latency::total 74918.519069 # average overall miss latency |
| 1089system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1090system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1091system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1092system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1093system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1094system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1095system.l2c.fast_writes 0 # number of fast writes performed 1096system.l2c.cache_copies 0 # number of cache copies performed | 1078system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1082system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.l2c.fast_writes 0 # number of fast writes performed 1085system.l2c.cache_copies 0 # number of cache copies performed |
| 1097system.l2c.writebacks::writebacks 66909 # number of writebacks 1098system.l2c.writebacks::total 66909 # number of writebacks | 1086system.l2c.writebacks::writebacks 66581 # number of writebacks 1087system.l2c.writebacks::total 66581 # number of writebacks |
| 1099system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits | 1088system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits |
| 1100system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits | 1089system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits |
| 1101system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 1102system.l2c.ReadReq_mshr_hits::cpu1.data 28 # number of ReadReq MSHR hits | 1090system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 1091system.l2c.ReadReq_mshr_hits::cpu1.data 28 # number of ReadReq MSHR hits |
| 1103system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits | 1092system.l2c.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits |
| 1104system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits | 1093system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits |
| 1105system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits | 1094system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits |
| 1106system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 1107system.l2c.demand_mshr_hits::cpu1.data 28 # number of demand (read+write) MSHR hits | 1095system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 1096system.l2c.demand_mshr_hits::cpu1.data 28 # number of demand (read+write) MSHR hits |
| 1108system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits | 1097system.l2c.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits |
| 1109system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits | 1098system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits |
| 1110system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits | 1099system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits |
| 1111system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 1112system.l2c.overall_mshr_hits::cpu1.data 28 # number of overall MSHR hits | 1100system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 1101system.l2c.overall_mshr_hits::cpu1.data 28 # number of overall MSHR hits |
| 1113system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits | 1102system.l2c.overall_mshr_hits::total 76 # number of overall MSHR hits |
| 1114system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses 1115system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses | 1103system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses 1104system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses |
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| 1139system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses 1140system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses | 1128system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses 1129system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses |
| 1141system.l2c.overall_mshr_misses::cpu0.inst 6012 # number of overall MSHR misses 1142system.l2c.overall_mshr_misses::cpu0.data 69669 # number of overall MSHR misses 1143system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses 1144system.l2c.overall_mshr_misses::cpu1.inst 6645 # number of overall MSHR misses 1145system.l2c.overall_mshr_misses::cpu1.data 83495 # number of overall MSHR misses 1146system.l2c.overall_mshr_misses::total 165852 # number of overall MSHR misses 1147system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1144250 # number of ReadReq MSHR miss cycles | 1130system.l2c.overall_mshr_misses::cpu0.inst 6048 # number of overall MSHR misses 1131system.l2c.overall_mshr_misses::cpu0.data 69404 # number of overall MSHR misses 1132system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses 1133system.l2c.overall_mshr_misses::cpu1.inst 6627 # number of overall MSHR misses 1134system.l2c.overall_mshr_misses::cpu1.data 83317 # number of overall MSHR misses 1135system.l2c.overall_mshr_misses::total 165428 # number of overall MSHR misses 1136system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1158500 # number of ReadReq MSHR miss cycles |
| 1148system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 423500 # number of ReadReq MSHR miss cycles | 1137system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 423500 # number of ReadReq MSHR miss cycles |
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| 1165system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 423500 # number of demand (read+write) MSHR miss cycles | 1154system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 423500 # number of demand (read+write) MSHR miss cycles |
| 1166system.l2c.demand_mshr_miss_latency::cpu0.inst 370171500 # number of demand (read+write) MSHR miss cycles 1167system.l2c.demand_mshr_miss_latency::cpu0.data 4041786922 # number of demand (read+write) MSHR miss cycles 1168system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1806000 # number of demand (read+write) MSHR miss cycles 1169system.l2c.demand_mshr_miss_latency::cpu1.inst 419977000 # number of demand (read+write) MSHR miss cycles 1170system.l2c.demand_mshr_miss_latency::cpu1.data 5553277967 # number of demand (read+write) MSHR miss cycles 1171system.l2c.demand_mshr_miss_latency::total 10388587139 # number of demand (read+write) MSHR miss cycles 1172system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1144250 # number of overall MSHR miss cycles | 1155system.l2c.demand_mshr_miss_latency::cpu0.inst 365788500 # number of demand (read+write) MSHR miss cycles 1156system.l2c.demand_mshr_miss_latency::cpu0.data 4016261423 # number of demand (read+write) MSHR miss cycles 1157system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1324000 # number of demand (read+write) MSHR miss cycles 1158system.l2c.demand_mshr_miss_latency::cpu1.inst 408302500 # number of demand (read+write) MSHR miss cycles 1159system.l2c.demand_mshr_miss_latency::cpu1.data 5535692219 # number of demand (read+write) MSHR miss cycles 1160system.l2c.demand_mshr_miss_latency::total 10328950642 # number of demand (read+write) MSHR miss cycles 1161system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1158500 # number of overall MSHR miss cycles |
| 1173system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 423500 # number of overall MSHR miss cycles | 1162system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 423500 # number of overall MSHR miss cycles |
| 1174system.l2c.overall_mshr_miss_latency::cpu0.inst 370171500 # number of overall MSHR miss cycles 1175system.l2c.overall_mshr_miss_latency::cpu0.data 4041786922 # number of overall MSHR miss cycles 1176system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1806000 # number of overall MSHR miss cycles 1177system.l2c.overall_mshr_miss_latency::cpu1.inst 419977000 # number of overall MSHR miss cycles 1178system.l2c.overall_mshr_miss_latency::cpu1.data 5553277967 # number of overall MSHR miss cycles 1179system.l2c.overall_mshr_miss_latency::total 10388587139 # number of overall MSHR miss cycles | 1163system.l2c.overall_mshr_miss_latency::cpu0.inst 365788500 # number of overall MSHR miss cycles 1164system.l2c.overall_mshr_miss_latency::cpu0.data 4016261423 # number of overall MSHR miss cycles 1165system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1324000 # number of overall MSHR miss cycles 1166system.l2c.overall_mshr_miss_latency::cpu1.inst 408302500 # number of overall MSHR miss cycles 1167system.l2c.overall_mshr_miss_latency::cpu1.data 5535692219 # number of overall MSHR miss cycles 1168system.l2c.overall_mshr_miss_latency::total 10328950642 # number of overall MSHR miss cycles |
| 1180system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6844749 # number of ReadReq MSHR uncacheable cycles | 1169system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6844749 # number of ReadReq MSHR uncacheable cycles |
| 1181system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12329934488 # number of ReadReq MSHR uncacheable cycles | 1170system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12336851490 # number of ReadReq MSHR uncacheable cycles |
| 1182system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2547499 # number of ReadReq MSHR uncacheable cycles | 1171system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2547499 # number of ReadReq MSHR uncacheable cycles |
| 1183system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154880876489 # number of ReadReq MSHR uncacheable cycles 1184system.l2c.ReadReq_mshr_uncacheable_latency::total 167220203225 # number of ReadReq MSHR uncacheable cycles 1185system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1069838998 # number of WriteReq MSHR uncacheable cycles 1186system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16519194406 # number of WriteReq MSHR uncacheable cycles 1187system.l2c.WriteReq_mshr_uncacheable_latency::total 17589033404 # number of WriteReq MSHR uncacheable cycles | 1172system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154880596991 # number of ReadReq MSHR uncacheable cycles 1173system.l2c.ReadReq_mshr_uncacheable_latency::total 167226840729 # number of ReadReq MSHR uncacheable cycles 1174system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1073381000 # number of WriteReq MSHR uncacheable cycles 1175system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16517452398 # number of WriteReq MSHR uncacheable cycles 1176system.l2c.WriteReq_mshr_uncacheable_latency::total 17590833398 # number of WriteReq MSHR uncacheable cycles |
| 1188system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6844749 # number of overall MSHR uncacheable cycles | 1177system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6844749 # number of overall MSHR uncacheable cycles |
| 1189system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13399773486 # number of overall MSHR uncacheable cycles | 1178system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13410232490 # number of overall MSHR uncacheable cycles |
| 1190system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2547499 # number of overall MSHR uncacheable cycles | 1179system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2547499 # number of overall MSHR uncacheable cycles |
| 1191system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171400070895 # number of overall MSHR uncacheable cycles 1192system.l2c.overall_mshr_uncacheable_latency::total 184809236629 # number of overall MSHR uncacheable cycles 1193system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for ReadReq accesses 1194system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for ReadReq accesses 1195system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for ReadReq accesses 1196system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036596 # mshr miss rate for ReadReq accesses 1197system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for ReadReq accesses 1198system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for ReadReq accesses 1199system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030339 # mshr miss rate for ReadReq accesses 1200system.l2c.ReadReq_mshr_miss_rate::total 0.017311 # mshr miss rate for ReadReq accesses 1201system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.831882 # mshr miss rate for UpgradeReq accesses 1202system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.853466 # mshr miss rate for UpgradeReq accesses 1203system.l2c.UpgradeReq_mshr_miss_rate::total 0.841174 # mshr miss rate for UpgradeReq accesses 1204system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.785495 # mshr miss rate for SCUpgradeReq accesses 1205system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.785904 # mshr miss rate for SCUpgradeReq accesses 1206system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.785673 # mshr miss rate for SCUpgradeReq accesses 1207system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569570 # mshr miss rate for ReadExReq accesses 1208system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565711 # mshr miss rate for ReadExReq accesses 1209system.l2c.ReadExReq_mshr_miss_rate::total 0.567444 # mshr miss rate for ReadExReq accesses 1210system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for demand accesses 1211system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for demand accesses 1212system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for demand accesses 1213system.l2c.demand_mshr_miss_rate::cpu0.data 0.245983 # mshr miss rate for demand accesses 1214system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for demand accesses 1215system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for demand accesses 1216system.l2c.demand_mshr_miss_rate::cpu1.data 0.242507 # mshr miss rate for demand accesses 1217system.l2c.demand_mshr_miss_rate::total 0.097077 # mshr miss rate for demand accesses 1218system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for overall accesses 1219system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for overall accesses 1220system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for overall accesses 1221system.l2c.overall_mshr_miss_rate::cpu0.data 0.245983 # mshr miss rate for overall accesses 1222system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for overall accesses 1223system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for overall accesses 1224system.l2c.overall_mshr_miss_rate::cpu1.data 0.242507 # mshr miss rate for overall accesses 1225system.l2c.overall_mshr_miss_rate::total 0.097077 # mshr miss rate for overall accesses 1226system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average ReadReq mshr miss latency | 1180system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171398049389 # number of overall MSHR uncacheable cycles 1181system.l2c.overall_mshr_uncacheable_latency::total 184817674127 # number of overall MSHR uncacheable cycles 1182system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000561 # mshr miss rate for ReadReq accesses 1183system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000428 # mshr miss rate for ReadReq accesses 1184system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015145 # mshr miss rate for ReadReq accesses 1185system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036383 # mshr miss rate for ReadReq accesses 1186system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000514 # mshr miss rate for ReadReq accesses 1187system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for ReadReq accesses 1188system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030436 # mshr miss rate for ReadReq accesses 1189system.l2c.ReadReq_mshr_miss_rate::total 0.017328 # mshr miss rate for ReadReq accesses 1190system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.837613 # mshr miss rate for UpgradeReq accesses 1191system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848207 # mshr miss rate for UpgradeReq accesses 1192system.l2c.UpgradeReq_mshr_miss_rate::total 0.842205 # mshr miss rate for UpgradeReq accesses 1193system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784553 # mshr miss rate for SCUpgradeReq accesses 1194system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784288 # mshr miss rate for SCUpgradeReq accesses 1195system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784438 # mshr miss rate for SCUpgradeReq accesses 1196system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566120 # mshr miss rate for ReadExReq accesses 1197system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565577 # mshr miss rate for ReadExReq accesses 1198system.l2c.ReadExReq_mshr_miss_rate::total 0.565822 # mshr miss rate for ReadExReq accesses 1199system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000561 # mshr miss rate for demand accesses 1200system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000428 # mshr miss rate for demand accesses 1201system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015145 # mshr miss rate for demand accesses 1202system.l2c.demand_mshr_miss_rate::cpu0.data 0.244373 # mshr miss rate for demand accesses 1203system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000514 # mshr miss rate for demand accesses 1204system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for demand accesses 1205system.l2c.demand_mshr_miss_rate::cpu1.data 0.242327 # mshr miss rate for demand accesses 1206system.l2c.demand_mshr_miss_rate::total 0.096860 # mshr miss rate for demand accesses 1207system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000561 # mshr miss rate for overall accesses 1208system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000428 # mshr miss rate for overall accesses 1209system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015145 # mshr miss rate for overall accesses 1210system.l2c.overall_mshr_miss_rate::cpu0.data 0.244373 # mshr miss rate for overall accesses 1211system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000514 # mshr miss rate for overall accesses 1212system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for overall accesses 1213system.l2c.overall_mshr_miss_rate::cpu1.data 0.242327 # mshr miss rate for overall accesses 1214system.l2c.overall_mshr_miss_rate::total 0.096860 # mshr miss rate for overall accesses 1215system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 89115.384615 # average ReadReq mshr miss latency |
| 1227system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average ReadReq mshr miss latency | 1216system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average ReadReq mshr miss latency |
| 1228system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average ReadReq mshr miss latency 1229system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62624.185603 # average ReadReq mshr miss latency 1230system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average ReadReq mshr miss latency 1231system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average ReadReq mshr miss latency 1232system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64978.710593 # average ReadReq mshr miss latency 1233system.l2c.ReadReq_avg_mshr_miss_latency::total 63169.691897 # average ReadReq mshr miss latency 1234system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.441012 # average UpgradeReq mshr miss latency 1235system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.003150 # average UpgradeReq mshr miss latency 1236system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10046.641734 # average UpgradeReq mshr miss latency 1237system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.247074 # average SCUpgradeReq mshr miss latency 1238system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10034.830795 # average SCUpgradeReq mshr miss latency 1239system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.537500 # average SCUpgradeReq mshr miss latency 1240system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57556.376578 # average ReadExReq mshr miss latency 1241system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66635.430152 # average ReadExReq mshr miss latency 1242system.l2c.ReadExReq_avg_mshr_miss_latency::total 62541.992246 # average ReadExReq mshr miss latency 1243system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average overall mshr miss latency | 1217system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60480.902778 # average ReadReq mshr miss latency 1218system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62714.586998 # average ReadReq mshr miss latency 1219system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77882.352941 # average ReadReq mshr miss latency 1220system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61611.966199 # average ReadReq mshr miss latency 1221system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.629489 # average ReadReq mshr miss latency 1222system.l2c.ReadReq_avg_mshr_miss_latency::total 62548.737275 # average ReadReq mshr miss latency 1223system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.898101 # average UpgradeReq mshr miss latency 1224system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10075.734487 # average UpgradeReq mshr miss latency 1225system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10047.654137 # average UpgradeReq mshr miss latency 1226system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.827720 # average SCUpgradeReq mshr miss latency 1227system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.331070 # average SCUpgradeReq mshr miss latency 1228system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.343865 # average SCUpgradeReq mshr miss latency 1229system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57386.020070 # average ReadExReq mshr miss latency 1230system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66543.102486 # average ReadExReq mshr miss latency 1231system.l2c.ReadExReq_avg_mshr_miss_latency::total 62417.697140 # average ReadExReq mshr miss latency 1232system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89115.384615 # average overall mshr miss latency |
| 1244system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency | 1233system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency |
| 1245system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average overall mshr miss latency 1246system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58014.137163 # average overall mshr miss latency 1247system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average overall mshr miss latency 1248system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average overall mshr miss latency 1249system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66510.305611 # average overall mshr miss latency 1250system.l2c.demand_avg_mshr_miss_latency::total 62637.695892 # average overall mshr miss latency 1251system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average overall mshr miss latency | 1234system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60480.902778 # average overall mshr miss latency 1235system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57867.866737 # average overall mshr miss latency 1236system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77882.352941 # average overall mshr miss latency 1237system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61611.966199 # average overall mshr miss latency 1238system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66441.329129 # average overall mshr miss latency 1239system.l2c.demand_avg_mshr_miss_latency::total 62437.741144 # average overall mshr miss latency 1240system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89115.384615 # average overall mshr miss latency |
| 1252system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency | 1241system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency |
| 1253system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average overall mshr miss latency 1254system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58014.137163 # average overall mshr miss latency 1255system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average overall mshr miss latency 1256system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average overall mshr miss latency 1257system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66510.305611 # average overall mshr miss latency 1258system.l2c.overall_avg_mshr_miss_latency::total 62637.695892 # average overall mshr miss latency | 1242system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60480.902778 # average overall mshr miss latency 1243system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57867.866737 # average overall mshr miss latency 1244system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77882.352941 # average overall mshr miss latency 1245system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61611.966199 # average overall mshr miss latency 1246system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66441.329129 # average overall mshr miss latency 1247system.l2c.overall_avg_mshr_miss_latency::total 62437.741144 # average overall mshr miss latency |
| 1259system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1260system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1261system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1262system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1263system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1264system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1265system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1266system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1271system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1272system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1273system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1274system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1275system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1276system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1277system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1278system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 1248system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1249system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1250system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1251system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1252system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1253system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1254system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1255system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1260system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1261system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1262system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1263system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1264system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1265system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1266system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1267system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 1279system.toL2Bus.throughput 58740655 # Throughput (bytes/s) 1280system.toL2Bus.trans_dist::ReadReq 2741580 # Transaction distribution 1281system.toL2Bus.trans_dist::ReadResp 2741579 # Transaction distribution 1282system.toL2Bus.trans_dist::WriteReq 769165 # Transaction distribution 1283system.toL2Bus.trans_dist::WriteResp 769165 # Transaction distribution 1284system.toL2Bus.trans_dist::Writeback 583255 # Transaction distribution 1285system.toL2Bus.trans_dist::UpgradeReq 35242 # Transaction distribution 1286system.toL2Bus.trans_dist::SCUpgradeReq 18671 # Transaction distribution 1287system.toL2Bus.trans_dist::UpgradeResp 53913 # Transaction distribution 1288system.toL2Bus.trans_dist::ReadExReq 259438 # Transaction distribution 1289system.toL2Bus.trans_dist::ReadExResp 259438 # Transaction distribution 1290system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800468 # Packet count per connected master and slave (bytes) 1291system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073661 # Packet count per connected master and slave (bytes) 1292system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13619 # Packet count per connected master and slave (bytes) 1293system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56672 # Packet count per connected master and slave (bytes) 1294system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1230417 # Packet count per connected master and slave (bytes) 1295system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820854 # Packet count per connected master and slave (bytes) 1296system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15509 # Packet count per connected master and slave (bytes) 1297system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 76068 # Packet count per connected master and slave (bytes) 1298system.toL2Bus.pkt_count::total 8087268 # Packet count per connected master and slave (bytes) 1299system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25596864 # Cumulative packet size per connected master and slave (bytes) 1300system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34696353 # Cumulative packet size per connected master and slave (bytes) 1301system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17380 # Cumulative packet size per connected master and slave (bytes) 1302system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90204 # Cumulative packet size per connected master and slave (bytes) 1303system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39355008 # Cumulative packet size per connected master and slave (bytes) 1304system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48247560 # Cumulative packet size per connected master and slave (bytes) 1305system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23124 # Cumulative packet size per connected master and slave (bytes) 1306system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 134188 # Cumulative packet size per connected master and slave (bytes) 1307system.toL2Bus.tot_pkt_size::total 148160681 # Cumulative packet size per connected master and slave (bytes) 1308system.toL2Bus.data_through_bus 148160681 # Total data (bytes) 1309system.toL2Bus.snoop_data_through_bus 4896624 # Total snoop data (bytes) 1310system.toL2Bus.reqLayer0.occupancy 4922304939 # Layer occupancy (ticks) | 1268system.toL2Bus.throughput 58734643 # Throughput (bytes/s) 1269system.toL2Bus.trans_dist::ReadReq 2740334 # Transaction distribution 1270system.toL2Bus.trans_dist::ReadResp 2740333 # Transaction distribution 1271system.toL2Bus.trans_dist::WriteReq 769179 # Transaction distribution 1272system.toL2Bus.trans_dist::WriteResp 769179 # Transaction distribution 1273system.toL2Bus.trans_dist::Writeback 583828 # Transaction distribution 1274system.toL2Bus.trans_dist::UpgradeReq 35005 # Transaction distribution 1275system.toL2Bus.trans_dist::SCUpgradeReq 18696 # Transaction distribution 1276system.toL2Bus.trans_dist::UpgradeResp 53701 # Transaction distribution 1277system.toL2Bus.trans_dist::ReadExReq 259560 # Transaction distribution 1278system.toL2Bus.trans_dist::ReadExResp 259560 # Transaction distribution 1279system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799508 # Packet count per connected master and slave (bytes) 1280system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1075466 # Packet count per connected master and slave (bytes) 1281system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14045 # Packet count per connected master and slave (bytes) 1282system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57080 # Packet count per connected master and slave (bytes) 1283system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1228838 # Packet count per connected master and slave (bytes) 1284system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820247 # Packet count per connected master and slave (bytes) 1285system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15511 # Packet count per connected master and slave (bytes) 1286system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75325 # Packet count per connected master and slave (bytes) 1287system.toL2Bus.pkt_count::total 8086020 # Packet count per connected master and slave (bytes) 1288system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25566400 # Cumulative packet size per connected master and slave (bytes) 1289system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34789221 # Cumulative packet size per connected master and slave (bytes) 1290system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18712 # Cumulative packet size per connected master and slave (bytes) 1291system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 92772 # Cumulative packet size per connected master and slave (bytes) 1292system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39303552 # Cumulative packet size per connected master and slave (bytes) 1293system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48210820 # Cumulative packet size per connected master and slave (bytes) 1294system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22868 # Cumulative packet size per connected master and slave (bytes) 1295system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132256 # Cumulative packet size per connected master and slave (bytes) 1296system.toL2Bus.tot_pkt_size::total 148136601 # Cumulative packet size per connected master and slave (bytes) 1297system.toL2Bus.data_through_bus 148136601 # Total data (bytes) 1298system.toL2Bus.snoop_data_through_bus 4903748 # Total snoop data (bytes) 1299system.toL2Bus.reqLayer0.occupancy 4924229951 # Layer occupancy (ticks) |
| 1311system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1300system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1312system.toL2Bus.respLayer0.occupancy 1803966688 # Layer occupancy (ticks) | 1301system.toL2Bus.respLayer0.occupancy 1801808391 # Layer occupancy (ticks) |
| 1313system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1302system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1314system.toL2Bus.respLayer1.occupancy 1516604948 # Layer occupancy (ticks) | 1303system.toL2Bus.respLayer1.occupancy 1518829470 # Layer occupancy (ticks) |
| 1315system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1304system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1316system.toL2Bus.respLayer2.occupancy 9296947 # Layer occupancy (ticks) | 1305system.toL2Bus.respLayer2.occupancy 9386457 # Layer occupancy (ticks) |
| 1317system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1306system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1318system.toL2Bus.respLayer3.occupancy 34267946 # Layer occupancy (ticks) | 1307system.toL2Bus.respLayer3.occupancy 34051657 # Layer occupancy (ticks) |
| 1319system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1308system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1320system.toL2Bus.respLayer6.occupancy 2771620829 # Layer occupancy (ticks) | 1309system.toL2Bus.respLayer6.occupancy 2768216654 # Layer occupancy (ticks) |
| 1321system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) | 1310system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) |
| 1322system.toL2Bus.respLayer7.occupancy 3258153300 # Layer occupancy (ticks) | 1311system.toL2Bus.respLayer7.occupancy 3257831802 # Layer occupancy (ticks) |
| 1323system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) | 1312system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) |
| 1324system.toL2Bus.respLayer8.occupancy 9753444 # Layer occupancy (ticks) | 1313system.toL2Bus.respLayer8.occupancy 9819444 # Layer occupancy (ticks) |
| 1325system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) | 1314system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) |
| 1326system.toL2Bus.respLayer9.occupancy 42798427 # Layer occupancy (ticks) | 1315system.toL2Bus.respLayer9.occupancy 42547912 # Layer occupancy (ticks) |
| 1327system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) | 1316system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) |
| 1328system.iobus.throughput 47398269 # Throughput (bytes/s) 1329system.iobus.trans_dist::ReadReq 16322887 # Transaction distribution 1330system.iobus.trans_dist::ReadResp 16322887 # Transaction distribution 1331system.iobus.trans_dist::WriteReq 8066 # Transaction distribution 1332system.iobus.trans_dist::WriteResp 8066 # Transaction distribution 1333system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) 1334system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8846 # Packet count per connected master and slave (bytes) | 1317system.iobus.throughput 47398726 # Throughput (bytes/s) 1318system.iobus.trans_dist::ReadReq 16322919 # Transaction distribution 1319system.iobus.trans_dist::ReadResp 16322919 # Transaction distribution 1320system.iobus.trans_dist::WriteReq 8083 # Transaction distribution 1321system.iobus.trans_dist::WriteResp 8083 # Transaction distribution 1322system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) 1323system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8844 # Packet count per connected master and slave (bytes) |
| 1335system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1336system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 1324system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1327system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 1339system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) | 1328system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) |
| 1340system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1342system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1343system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1344system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1345system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1346system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1347system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1348system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1349system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1350system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1351system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1352system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1353system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1354system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1355system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 1329system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1330system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1331system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1332system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1333system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1334system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1335system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1336system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1339system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1340system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1342system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1343system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1344system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 1356system.iobus.pkt_count_system.bridge.master::total 2384274 # Packet count per connected master and slave (bytes) | 1345system.iobus.pkt_count_system.bridge.master::total 2384372 # Packet count per connected master and slave (bytes) |
| 1357system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 1358system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) | 1346system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 1347system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) |
| 1359system.iobus.pkt_count::total 32661906 # Packet count per connected master and slave (bytes) 1360system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) 1361system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17692 # Cumulative packet size per connected master and slave (bytes) | 1348system.iobus.pkt_count::total 32662004 # Packet count per connected master and slave (bytes) 1349system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) 1350system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17688 # Cumulative packet size per connected master and slave (bytes) |
| 1362system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1363system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) 1364system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1365system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) | 1351system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1352system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) 1353system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1354system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
| 1366system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) | 1355system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) |
| 1367system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1368system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1369system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1370system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1371system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1372system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1373system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1374system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1375system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1376system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1377system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1378system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1379system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1380system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1381system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1382system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1356system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1357system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1358system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1359system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1360system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1361system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1362system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1363system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1364system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1365system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1366system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1367system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1368system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1369system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1370system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1371system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 1383system.iobus.tot_pkt_size_system.bridge.master::total 2392545 # Cumulative packet size per connected master and slave (bytes) | 1372system.iobus.tot_pkt_size_system.bridge.master::total 2392693 # Cumulative packet size per connected master and slave (bytes) |
| 1384system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 1385system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) | 1373system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 1374system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) |
| 1386system.iobus.tot_pkt_size::total 123503073 # Cumulative packet size per connected master and slave (bytes) 1387system.iobus.data_through_bus 123503073 # Total data (bytes) 1388system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) | 1375system.iobus.tot_pkt_size::total 123503221 # Cumulative packet size per connected master and slave (bytes) 1376system.iobus.data_through_bus 123503221 # Total data (bytes) 1377system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) |
| 1389system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1378system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1390system.iobus.reqLayer1.occupancy 4429000 # Layer occupancy (ticks) | 1379system.iobus.reqLayer1.occupancy 4428000 # Layer occupancy (ticks) |
| 1391system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1392system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1393system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1394system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) 1395system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1396system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1397system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1398system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1399system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1380system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1381system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1382system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1383system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) 1384system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1385system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1386system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1387system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1388system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1400system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) | 1389system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) |
| 1401system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1402system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 1403system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1404system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1405system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1406system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1407system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1408system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) --- 19 unchanged lines hidden (view full) --- 1428system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1429system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1430system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1431system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1432system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1433system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1434system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 1435system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) | 1390system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1391system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 1392system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1393system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1394system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1395system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1396system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1397system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) --- 19 unchanged lines hidden (view full) --- 1417system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1418system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1419system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1420system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1421system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1422system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1423system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 1424system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) |
| 1436system.iobus.respLayer0.occupancy 2376208000 # Layer occupancy (ticks) | 1425system.iobus.respLayer0.occupancy 2376289000 # Layer occupancy (ticks) |
| 1437system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 1426system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1438system.iobus.respLayer1.occupancy 41458010805 # Layer occupancy (ticks) | 1427system.iobus.respLayer1.occupancy 41457903301 # Layer occupancy (ticks) |
| 1439system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) | 1428system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) |
| 1440system.cpu0.branchPred.lookups 6118154 # Number of BP lookups 1441system.cpu0.branchPred.condPredicted 4670367 # Number of conditional branches predicted 1442system.cpu0.branchPred.condIncorrect 295970 # Number of conditional branches incorrect 1443system.cpu0.branchPred.BTBLookups 3816631 # Number of BTB lookups 1444system.cpu0.branchPred.BTBHits 2949053 # Number of BTB hits | 1429system.cpu0.branchPred.lookups 6116113 # Number of BP lookups 1430system.cpu0.branchPred.condPredicted 4670014 # Number of conditional branches predicted 1431system.cpu0.branchPred.condIncorrect 294465 # Number of conditional branches incorrect 1432system.cpu0.branchPred.BTBLookups 3791796 # Number of BTB lookups 1433system.cpu0.branchPred.BTBHits 2947023 # Number of BTB hits |
| 1445system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1434system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1446system.cpu0.branchPred.BTBHitPct 77.268486 # BTB Hit Percentage 1447system.cpu0.branchPred.usedRAS 684315 # Number of times the RAS was used to get a target. 1448system.cpu0.branchPred.RASInCorrect 28445 # Number of incorrect RAS predictions. | 1435system.cpu0.branchPred.BTBHitPct 77.721032 # BTB Hit Percentage 1436system.cpu0.branchPred.usedRAS 683382 # Number of times the RAS was used to get a target. 1437system.cpu0.branchPred.RASInCorrect 28116 # Number of incorrect RAS predictions. |
| 1449system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1450system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1451system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1452system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1453system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1454system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1455system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1456system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1464system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1465system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1466system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1467system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1468system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1469system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1470system.cpu0.dtb.inst_hits 0 # ITB inst hits 1471system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1438system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1439system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1440system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1441system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1442system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1443system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1444system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1445system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1453system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1454system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1455system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1456system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1457system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1458system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1459system.cpu0.dtb.inst_hits 0 # ITB inst hits 1460system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1472system.cpu0.dtb.read_hits 8969635 # DTB read hits 1473system.cpu0.dtb.read_misses 28952 # DTB read misses 1474system.cpu0.dtb.write_hits 5211846 # DTB write hits 1475system.cpu0.dtb.write_misses 5698 # DTB write misses | 1461system.cpu0.dtb.read_hits 8971213 # DTB read hits 1462system.cpu0.dtb.read_misses 29038 # DTB read misses 1463system.cpu0.dtb.write_hits 5214205 # DTB write hits 1464system.cpu0.dtb.write_misses 5642 # DTB write misses |
| 1476system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1477system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1478system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1479system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1465system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1466system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1467system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1468system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1480system.cpu0.dtb.flush_entries 1738 # Number of entries that have been flushed from TLB 1481system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions 1482system.cpu0.dtb.prefetch_faults 275 # Number of TLB faults due to prefetch | 1469system.cpu0.dtb.flush_entries 1740 # Number of entries that have been flushed from TLB 1470system.cpu0.dtb.align_faults 972 # Number of TLB faults due to alignment restrictions 1471system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch |
| 1483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1472system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1484system.cpu0.dtb.perms_faults 590 # Number of TLB faults due to permissions restrictions 1485system.cpu0.dtb.read_accesses 8998587 # DTB read accesses 1486system.cpu0.dtb.write_accesses 5217544 # DTB write accesses | 1473system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions 1474system.cpu0.dtb.read_accesses 9000251 # DTB read accesses 1475system.cpu0.dtb.write_accesses 5219847 # DTB write accesses |
| 1487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1476system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1488system.cpu0.dtb.hits 14181481 # DTB hits 1489system.cpu0.dtb.misses 34650 # DTB misses 1490system.cpu0.dtb.accesses 14216131 # DTB accesses | 1477system.cpu0.dtb.hits 14185418 # DTB hits 1478system.cpu0.dtb.misses 34680 # DTB misses 1479system.cpu0.dtb.accesses 14220098 # DTB accesses |
| 1491system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1492system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1493system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1494system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1495system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1496system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1504system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1505system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1506system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1507system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1508system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1509system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1510system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1511system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1480system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1481system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1482system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1483system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1484system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1485system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1486system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1487system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1493system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1494system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1495system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1496system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1497system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1498system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1499system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1500system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1512system.cpu0.itb.inst_hits 4279077 # ITB inst hits 1513system.cpu0.itb.inst_misses 5117 # ITB inst misses | 1501system.cpu0.itb.inst_hits 4275051 # ITB inst hits 1502system.cpu0.itb.inst_misses 5189 # ITB inst misses |
| 1514system.cpu0.itb.read_hits 0 # DTB read hits 1515system.cpu0.itb.read_misses 0 # DTB read misses 1516system.cpu0.itb.write_hits 0 # DTB write hits 1517system.cpu0.itb.write_misses 0 # DTB write misses 1518system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1519system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1520system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1521system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1503system.cpu0.itb.read_hits 0 # DTB read hits 1504system.cpu0.itb.read_misses 0 # DTB read misses 1505system.cpu0.itb.write_hits 0 # DTB write hits 1506system.cpu0.itb.write_misses 0 # DTB write misses 1507system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1508system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1509system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1510system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1522system.cpu0.itb.flush_entries 1212 # Number of entries that have been flushed from TLB | 1511system.cpu0.itb.flush_entries 1217 # Number of entries that have been flushed from TLB |
| 1523system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1524system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1525system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1512system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1513system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1514system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1526system.cpu0.itb.perms_faults 1385 # Number of TLB faults due to permissions restrictions | 1515system.cpu0.itb.perms_faults 1383 # Number of TLB faults due to permissions restrictions |
| 1527system.cpu0.itb.read_accesses 0 # DTB read accesses 1528system.cpu0.itb.write_accesses 0 # DTB write accesses | 1516system.cpu0.itb.read_accesses 0 # DTB read accesses 1517system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1529system.cpu0.itb.inst_accesses 4284194 # ITB inst accesses 1530system.cpu0.itb.hits 4279077 # DTB hits 1531system.cpu0.itb.misses 5117 # DTB misses 1532system.cpu0.itb.accesses 4284194 # DTB accesses 1533system.cpu0.numCycles 70223968 # number of cpu cycles simulated | 1518system.cpu0.itb.inst_accesses 4280240 # ITB inst accesses 1519system.cpu0.itb.hits 4275051 # DTB hits 1520system.cpu0.itb.misses 5189 # DTB misses 1521system.cpu0.itb.accesses 4280240 # DTB accesses 1522system.cpu0.numCycles 70241745 # number of cpu cycles simulated |
| 1534system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1535system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1523system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1524system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1536system.cpu0.fetch.icacheStallCycles 11927082 # Number of cycles fetch is stalled on an Icache miss 1537system.cpu0.fetch.Insts 32438478 # Number of instructions fetch has processed 1538system.cpu0.fetch.Branches 6118154 # Number of branches that fetch encountered 1539system.cpu0.fetch.predictedBranches 3633368 # Number of branches that fetch has predicted taken 1540system.cpu0.fetch.Cycles 7610656 # Number of cycles fetch has run and was not squashing or blocked 1541system.cpu0.fetch.SquashCycles 1458202 # Number of cycles fetch has spent squashing 1542system.cpu0.fetch.TlbCycles 60559 # Number of cycles fetch has spent waiting for tlb 1543system.cpu0.fetch.BlockedCycles 20342851 # Number of cycles fetch has spent blocked 1544system.cpu0.fetch.MiscStallCycles 5497 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1545system.cpu0.fetch.PendingTrapStallCycles 47160 # Number of stall cycles due to pending traps 1546system.cpu0.fetch.PendingQuiesceStallCycles 1383184 # Number of stall cycles due to pending quiesce instructions 1547system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR 1548system.cpu0.fetch.CacheLines 4277582 # Number of cache lines fetched 1549system.cpu0.fetch.IcacheSquashes 158526 # Number of outstanding Icache misses that were squashed 1550system.cpu0.fetch.ItlbSquashes 2073 # Number of outstanding ITLB misses that were squashed 1551system.cpu0.fetch.rateDist::samples 42423154 # Number of instructions fetched each cycle (Total) 1552system.cpu0.fetch.rateDist::mean 0.988026 # Number of instructions fetched each cycle (Total) 1553system.cpu0.fetch.rateDist::stdev 2.369139 # Number of instructions fetched each cycle (Total) | 1525system.cpu0.fetch.icacheStallCycles 11929498 # Number of cycles fetch is stalled on an Icache miss 1526system.cpu0.fetch.Insts 32445295 # Number of instructions fetch has processed 1527system.cpu0.fetch.Branches 6116113 # Number of branches that fetch encountered 1528system.cpu0.fetch.predictedBranches 3630405 # Number of branches that fetch has predicted taken 1529system.cpu0.fetch.Cycles 7610256 # Number of cycles fetch has run and was not squashing or blocked 1530system.cpu0.fetch.SquashCycles 1455955 # Number of cycles fetch has spent squashing 1531system.cpu0.fetch.TlbCycles 63581 # Number of cycles fetch has spent waiting for tlb 1532system.cpu0.fetch.BlockedCycles 20356712 # Number of cycles fetch has spent blocked 1533system.cpu0.fetch.MiscStallCycles 5910 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1534system.cpu0.fetch.PendingTrapStallCycles 46897 # Number of stall cycles due to pending traps 1535system.cpu0.fetch.PendingQuiesceStallCycles 1384514 # Number of stall cycles due to pending quiesce instructions 1536system.cpu0.fetch.IcacheWaitRetryStallCycles 336 # Number of stall cycles due to full MSHR 1537system.cpu0.fetch.CacheLines 4273539 # Number of cache lines fetched 1538system.cpu0.fetch.IcacheSquashes 157097 # Number of outstanding Icache misses that were squashed 1539system.cpu0.fetch.ItlbSquashes 2132 # Number of outstanding ITLB misses that were squashed 1540system.cpu0.fetch.rateDist::samples 42442805 # Number of instructions fetched each cycle (Total) 1541system.cpu0.fetch.rateDist::mean 0.987587 # Number of instructions fetched each cycle (Total) 1542system.cpu0.fetch.rateDist::stdev 2.368800 # Number of instructions fetched each cycle (Total) |
| 1554system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1543system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1555system.cpu0.fetch.rateDist::0 34819772 82.08% 82.08% # Number of instructions fetched each cycle (Total) 1556system.cpu0.fetch.rateDist::1 571665 1.35% 83.42% # Number of instructions fetched each cycle (Total) 1557system.cpu0.fetch.rateDist::2 825898 1.95% 85.37% # Number of instructions fetched each cycle (Total) 1558system.cpu0.fetch.rateDist::3 684492 1.61% 86.99% # Number of instructions fetched each cycle (Total) 1559system.cpu0.fetch.rateDist::4 779946 1.84% 88.82% # Number of instructions fetched each cycle (Total) 1560system.cpu0.fetch.rateDist::5 566234 1.33% 90.16% # Number of instructions fetched each cycle (Total) 1561system.cpu0.fetch.rateDist::6 677676 1.60% 91.76% # Number of instructions fetched each cycle (Total) 1562system.cpu0.fetch.rateDist::7 358556 0.85% 92.60% # Number of instructions fetched each cycle (Total) 1563system.cpu0.fetch.rateDist::8 3138915 7.40% 100.00% # Number of instructions fetched each cycle (Total) | 1544system.cpu0.fetch.rateDist::0 34839840 82.09% 82.09% # Number of instructions fetched each cycle (Total) 1545system.cpu0.fetch.rateDist::1 572205 1.35% 83.43% # Number of instructions fetched each cycle (Total) 1546system.cpu0.fetch.rateDist::2 825004 1.94% 85.38% # Number of instructions fetched each cycle (Total) 1547system.cpu0.fetch.rateDist::3 684840 1.61% 86.99% # Number of instructions fetched each cycle (Total) 1548system.cpu0.fetch.rateDist::4 778500 1.83% 88.83% # Number of instructions fetched each cycle (Total) 1549system.cpu0.fetch.rateDist::5 566486 1.33% 90.16% # Number of instructions fetched each cycle (Total) 1550system.cpu0.fetch.rateDist::6 678699 1.60% 91.76% # Number of instructions fetched each cycle (Total) 1551system.cpu0.fetch.rateDist::7 357241 0.84% 92.60% # Number of instructions fetched each cycle (Total) 1552system.cpu0.fetch.rateDist::8 3139990 7.40% 100.00% # Number of instructions fetched each cycle (Total) |
| 1564system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1565system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1566system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1553system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1554system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1555system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1567system.cpu0.fetch.rateDist::total 42423154 # Number of instructions fetched each cycle (Total) 1568system.cpu0.fetch.branchRate 0.087123 # Number of branch fetches per cycle 1569system.cpu0.fetch.rate 0.461929 # Number of inst fetches per cycle 1570system.cpu0.decode.IdleCycles 12476093 # Number of cycles decode is idle 1571system.cpu0.decode.BlockedCycles 21540045 # Number of cycles decode is blocked 1572system.cpu0.decode.RunCycles 6871897 # Number of cycles decode is running 1573system.cpu0.decode.UnblockCycles 553157 # Number of cycles decode is unblocking 1574system.cpu0.decode.SquashCycles 981962 # Number of cycles decode is squashing 1575system.cpu0.decode.BranchResolved 949644 # Number of times decode resolved a branch 1576system.cpu0.decode.BranchMispred 64975 # Number of times decode detected a branch misprediction 1577system.cpu0.decode.DecodedInsts 40551006 # Number of instructions handled by decode 1578system.cpu0.decode.SquashedInsts 213850 # Number of squashed instructions handled by decode 1579system.cpu0.rename.SquashCycles 981962 # Number of cycles rename is squashing 1580system.cpu0.rename.IdleCycles 13051542 # Number of cycles rename is idle 1581system.cpu0.rename.BlockCycles 5910563 # Number of cycles rename is blocking 1582system.cpu0.rename.serializeStallCycles 13528575 # count of cycles rename stalled for serializing inst 1583system.cpu0.rename.RunCycles 6803012 # Number of cycles rename is running 1584system.cpu0.rename.UnblockCycles 2147500 # Number of cycles rename is unblocking 1585system.cpu0.rename.RenamedInsts 39435352 # Number of instructions processed by rename 1586system.cpu0.rename.ROBFullEvents 334 # Number of times rename has blocked due to ROB full 1587system.cpu0.rename.IQFullEvents 441883 # Number of times rename has blocked due to IQ full 1588system.cpu0.rename.LSQFullEvents 1170709 # Number of times rename has blocked due to LSQ full 1589system.cpu0.rename.FullRegisterEvents 119 # Number of times there has been no free registers 1590system.cpu0.rename.RenamedOperands 39847910 # Number of destination operands rename has renamed 1591system.cpu0.rename.RenameLookups 180543493 # Number of register rename lookups that rename has made 1592system.cpu0.rename.int_rename_lookups 163844376 # Number of integer rename lookups 1593system.cpu0.rename.fp_rename_lookups 4138 # Number of floating rename lookups 1594system.cpu0.rename.CommittedMaps 31495709 # Number of HB maps that are committed 1595system.cpu0.rename.UndoneMaps 8352200 # Number of HB maps that are undone due to squashing 1596system.cpu0.rename.serializingInsts 460642 # count of serializing insts renamed 1597system.cpu0.rename.tempSerializingInsts 417076 # count of temporary serializing insts renamed 1598system.cpu0.rename.skidInsts 5513022 # count of insts added to the skid buffer 1599system.cpu0.memDep0.insertedLoads 7756413 # Number of loads inserted to the mem dependence unit. 1600system.cpu0.memDep0.insertedStores 5773431 # Number of stores inserted to the mem dependence unit. 1601system.cpu0.memDep0.conflictingLoads 1120554 # Number of conflicting loads. 1602system.cpu0.memDep0.conflictingStores 1217575 # Number of conflicting stores. 1603system.cpu0.iq.iqInstsAdded 37342460 # Number of instructions added to the IQ (excludes non-spec) 1604system.cpu0.iq.iqNonSpecInstsAdded 905810 # Number of non-speculative instructions added to the IQ 1605system.cpu0.iq.iqInstsIssued 37712626 # Number of instructions issued 1606system.cpu0.iq.iqSquashedInstsIssued 83166 # Number of squashed instructions issued 1607system.cpu0.iq.iqSquashedInstsExamined 6296628 # Number of squashed instructions iterated over during squash; mainly for profiling 1608system.cpu0.iq.iqSquashedOperandsExamined 13228023 # Number of squashed operands that are examined and possibly removed from graph 1609system.cpu0.iq.iqSquashedNonSpecRemoved 256791 # Number of squashed non-spec instructions that were removed 1610system.cpu0.iq.issued_per_cycle::samples 42423154 # Number of insts issued each cycle 1611system.cpu0.iq.issued_per_cycle::mean 0.888963 # Number of insts issued each cycle 1612system.cpu0.iq.issued_per_cycle::stdev 1.506683 # Number of insts issued each cycle | 1556system.cpu0.fetch.rateDist::total 42442805 # Number of instructions fetched each cycle (Total) 1557system.cpu0.fetch.branchRate 0.087072 # Number of branch fetches per cycle 1558system.cpu0.fetch.rate 0.461909 # Number of inst fetches per cycle 1559system.cpu0.decode.IdleCycles 12488007 # Number of cycles decode is idle 1560system.cpu0.decode.BlockedCycles 21548451 # Number of cycles decode is blocked 1561system.cpu0.decode.RunCycles 6870426 # Number of cycles decode is running 1562system.cpu0.decode.UnblockCycles 554367 # Number of cycles decode is unblocking 1563system.cpu0.decode.SquashCycles 981554 # Number of cycles decode is squashing 1564system.cpu0.decode.BranchResolved 948390 # Number of times decode resolved a branch 1565system.cpu0.decode.BranchMispred 64682 # Number of times decode detected a branch misprediction 1566system.cpu0.decode.DecodedInsts 40553105 # Number of instructions handled by decode 1567system.cpu0.decode.SquashedInsts 211793 # Number of squashed instructions handled by decode 1568system.cpu0.rename.SquashCycles 981554 # Number of cycles rename is squashing 1569system.cpu0.rename.IdleCycles 13063645 # Number of cycles rename is idle 1570system.cpu0.rename.BlockCycles 5927392 # Number of cycles rename is blocking 1571system.cpu0.rename.serializeStallCycles 13516172 # count of cycles rename stalled for serializing inst 1572system.cpu0.rename.RunCycles 6803229 # Number of cycles rename is running 1573system.cpu0.rename.UnblockCycles 2150813 # Number of cycles rename is unblocking 1574system.cpu0.rename.RenamedInsts 39442908 # Number of instructions processed by rename 1575system.cpu0.rename.ROBFullEvents 349 # Number of times rename has blocked due to ROB full 1576system.cpu0.rename.IQFullEvents 442190 # Number of times rename has blocked due to IQ full 1577system.cpu0.rename.LSQFullEvents 1172580 # Number of times rename has blocked due to LSQ full 1578system.cpu0.rename.FullRegisterEvents 108 # Number of times there has been no free registers 1579system.cpu0.rename.RenamedOperands 39856158 # Number of destination operands rename has renamed 1580system.cpu0.rename.RenameLookups 180580051 # Number of register rename lookups that rename has made 1581system.cpu0.rename.int_rename_lookups 163873696 # Number of integer rename lookups 1582system.cpu0.rename.fp_rename_lookups 4140 # Number of floating rename lookups 1583system.cpu0.rename.CommittedMaps 31502925 # Number of HB maps that are committed 1584system.cpu0.rename.UndoneMaps 8353232 # Number of HB maps that are undone due to squashing 1585system.cpu0.rename.serializingInsts 459972 # count of serializing insts renamed 1586system.cpu0.rename.tempSerializingInsts 416665 # count of temporary serializing insts renamed 1587system.cpu0.rename.skidInsts 5510720 # count of insts added to the skid buffer 1588system.cpu0.memDep0.insertedLoads 7760142 # Number of loads inserted to the mem dependence unit. 1589system.cpu0.memDep0.insertedStores 5773435 # Number of stores inserted to the mem dependence unit. 1590system.cpu0.memDep0.conflictingLoads 1130797 # Number of conflicting loads. 1591system.cpu0.memDep0.conflictingStores 1218383 # Number of conflicting stores. 1592system.cpu0.iq.iqInstsAdded 37351008 # Number of instructions added to the IQ (excludes non-spec) 1593system.cpu0.iq.iqNonSpecInstsAdded 906143 # Number of non-speculative instructions added to the IQ 1594system.cpu0.iq.iqInstsIssued 37719109 # Number of instructions issued 1595system.cpu0.iq.iqSquashedInstsIssued 82376 # Number of squashed instructions issued 1596system.cpu0.iq.iqSquashedInstsExamined 6300240 # Number of squashed instructions iterated over during squash; mainly for profiling 1597system.cpu0.iq.iqSquashedOperandsExamined 13226792 # Number of squashed operands that are examined and possibly removed from graph 1598system.cpu0.iq.iqSquashedNonSpecRemoved 257129 # Number of squashed non-spec instructions that were removed 1599system.cpu0.iq.issued_per_cycle::samples 42442805 # Number of insts issued each cycle 1600system.cpu0.iq.issued_per_cycle::mean 0.888704 # Number of insts issued each cycle 1601system.cpu0.iq.issued_per_cycle::stdev 1.506616 # Number of insts issued each cycle |
| 1613system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1602system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1614system.cpu0.iq.issued_per_cycle::0 27070740 63.81% 63.81% # Number of insts issued each cycle 1615system.cpu0.iq.issued_per_cycle::1 5892236 13.89% 77.70% # Number of insts issued each cycle 1616system.cpu0.iq.issued_per_cycle::2 3160742 7.45% 85.15% # Number of insts issued each cycle 1617system.cpu0.iq.issued_per_cycle::3 2473733 5.83% 90.98% # Number of insts issued each cycle 1618system.cpu0.iq.issued_per_cycle::4 2116122 4.99% 95.97% # Number of insts issued each cycle 1619system.cpu0.iq.issued_per_cycle::5 945480 2.23% 98.20% # Number of insts issued each cycle 1620system.cpu0.iq.issued_per_cycle::6 519157 1.22% 99.42% # Number of insts issued each cycle 1621system.cpu0.iq.issued_per_cycle::7 188675 0.44% 99.87% # Number of insts issued each cycle 1622system.cpu0.iq.issued_per_cycle::8 56269 0.13% 100.00% # Number of insts issued each cycle | 1603system.cpu0.iq.issued_per_cycle::0 27084248 63.81% 63.81% # Number of insts issued each cycle 1604system.cpu0.iq.issued_per_cycle::1 5900278 13.90% 77.72% # Number of insts issued each cycle 1605system.cpu0.iq.issued_per_cycle::2 3162124 7.45% 85.17% # Number of insts issued each cycle 1606system.cpu0.iq.issued_per_cycle::3 2465638 5.81% 90.97% # Number of insts issued each cycle 1607system.cpu0.iq.issued_per_cycle::4 2124054 5.00% 95.98% # Number of insts issued each cycle 1608system.cpu0.iq.issued_per_cycle::5 938721 2.21% 98.19% # Number of insts issued each cycle 1609system.cpu0.iq.issued_per_cycle::6 522569 1.23% 99.42% # Number of insts issued each cycle 1610system.cpu0.iq.issued_per_cycle::7 188950 0.45% 99.87% # Number of insts issued each cycle 1611system.cpu0.iq.issued_per_cycle::8 56223 0.13% 100.00% # Number of insts issued each cycle |
| 1623system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1624system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1625system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1612system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1613system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1614system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1626system.cpu0.iq.issued_per_cycle::total 42423154 # Number of insts issued each cycle | 1615system.cpu0.iq.issued_per_cycle::total 42442805 # Number of insts issued each cycle |
| 1627system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1616system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1628system.cpu0.iq.fu_full::IntAlu 27921 2.59% 2.59% # attempts to use FU when none available 1629system.cpu0.iq.fu_full::IntMult 464 0.04% 2.64% # attempts to use FU when none available 1630system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available 1631system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available 1632system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available 1633system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available 1634system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available 1635system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available 1636system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available 1637system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available 1638system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available 1639system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available 1640system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available 1641system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available 1642system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available 1643system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available 1644system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available 1645system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available 1646system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available 1647system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available 1648system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available 1649system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available 1650system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available 1651system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available 1652system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available 1653system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available 1654system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available 1655system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available 1656system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available 1657system.cpu0.iq.fu_full::MemRead 839960 77.98% 80.61% # attempts to use FU when none available 1658system.cpu0.iq.fu_full::MemWrite 208811 19.39% 100.00% # attempts to use FU when none available | 1617system.cpu0.iq.fu_full::IntAlu 27701 2.58% 2.58% # attempts to use FU when none available 1618system.cpu0.iq.fu_full::IntMult 461 0.04% 2.62% # attempts to use FU when none available 1619system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available 1620system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available 1621system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available 1622system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available 1623system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available 1624system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available 1625system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available 1626system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available 1627system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available 1628system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available 1629system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available 1630system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available 1631system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available 1632system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available 1633system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available 1634system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available 1635system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available 1636system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available 1637system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available 1638system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available 1639system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available 1640system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available 1641system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available 1642system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available 1643system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available 1644system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available 1645system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available 1646system.cpu0.iq.fu_full::MemRead 838727 78.09% 80.71% # attempts to use FU when none available 1647system.cpu0.iq.fu_full::MemWrite 207210 19.29% 100.00% # attempts to use FU when none available |
| 1659system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1660system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1648system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1649system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1661system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued 1662system.cpu0.iq.FU_type_0::IntAlu 22686320 60.16% 60.19% # Type of FU issued 1663system.cpu0.iq.FU_type_0::IntMult 48095 0.13% 60.32% # Type of FU issued | 1650system.cpu0.iq.FU_type_0::No_OpClass 14552 0.04% 0.04% # Type of FU issued 1651system.cpu0.iq.FU_type_0::IntAlu 22689290 60.15% 60.19% # Type of FU issued 1652system.cpu0.iq.FU_type_0::IntMult 48124 0.13% 60.32% # Type of FU issued |
| 1664system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued 1665system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued 1666system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued 1667system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued 1668system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued 1669system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued 1670system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued 1671system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued 1672system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued 1673system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued 1674system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued 1675system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued 1676system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued 1677system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued 1678system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued 1679system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued | 1653system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued 1654system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued 1655system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued 1656system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued 1657system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued 1658system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued 1659system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued 1660system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued 1661system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued 1662system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued 1663system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued 1664system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued 1665system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued 1666system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued 1667system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued 1668system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued |
| 1680system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.32% # Type of FU issued | 1669system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.32% # Type of FU issued |
| 1681system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued 1682system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued 1683system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued 1684system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued 1685system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued 1686system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued 1687system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued 1688system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued 1689system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued 1690system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued | 1670system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued 1671system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued 1672system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued 1673system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued 1674system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued 1675system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued 1676system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued 1677system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued 1678system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued 1679system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued |
| 1691system.cpu0.iq.FU_type_0::MemRead 9430202 25.01% 85.33% # Type of FU issued 1692system.cpu0.iq.FU_type_0::MemWrite 5532744 14.67% 100.00% # Type of FU issued | 1680system.cpu0.iq.FU_type_0::MemRead 9432418 25.01% 85.33% # Type of FU issued 1681system.cpu0.iq.FU_type_0::MemWrite 5534012 14.67% 100.00% # Type of FU issued |
| 1693system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1694system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1682system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1683system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1695system.cpu0.iq.FU_type_0::total 37712626 # Type of FU issued 1696system.cpu0.iq.rate 0.537034 # Inst issue rate 1697system.cpu0.iq.fu_busy_cnt 1077156 # FU busy when requested 1698system.cpu0.iq.fu_busy_rate 0.028562 # FU busy rate (busy events/executed inst) 1699system.cpu0.iq.int_inst_queue_reads 119034571 # Number of integer instruction queue reads 1700system.cpu0.iq.int_inst_queue_writes 44552771 # Number of integer instruction queue writes 1701system.cpu0.iq.int_inst_queue_wakeup_accesses 34849273 # Number of integer instruction queue wakeup accesses 1702system.cpu0.iq.fp_inst_queue_reads 8516 # Number of floating instruction queue reads 1703system.cpu0.iq.fp_inst_queue_writes 4702 # Number of floating instruction queue writes 1704system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses 1705system.cpu0.iq.int_alu_accesses 38770775 # Number of integer alu accesses 1706system.cpu0.iq.fp_alu_accesses 4456 # Number of floating point alu accesses 1707system.cpu0.iew.lsq.thread0.forwLoads 316259 # Number of loads that had data forwarded from stores | 1684system.cpu0.iq.FU_type_0::total 37719109 # Type of FU issued 1685system.cpu0.iq.rate 0.536990 # Inst issue rate 1686system.cpu0.iq.fu_busy_cnt 1074099 # FU busy when requested 1687system.cpu0.iq.fu_busy_rate 0.028476 # FU busy rate (busy events/executed inst) 1688system.cpu0.iq.int_inst_queue_reads 119063513 # Number of integer instruction queue reads 1689system.cpu0.iq.int_inst_queue_writes 44565262 # Number of integer instruction queue writes 1690system.cpu0.iq.int_inst_queue_wakeup_accesses 34855631 # Number of integer instruction queue wakeup accesses 1691system.cpu0.iq.fp_inst_queue_reads 8367 # Number of floating instruction queue reads 1692system.cpu0.iq.fp_inst_queue_writes 4694 # Number of floating instruction queue writes 1693system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses 1694system.cpu0.iq.int_alu_accesses 38774303 # Number of integer alu accesses 1695system.cpu0.iq.fp_alu_accesses 4353 # Number of floating point alu accesses 1696system.cpu0.iew.lsq.thread0.forwLoads 316534 # Number of loads that had data forwarded from stores |
| 1708system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1697system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1709system.cpu0.iew.lsq.thread0.squashedLoads 1371122 # Number of loads squashed 1710system.cpu0.iew.lsq.thread0.ignoredResponses 2677 # Number of memory responses ignored because the instruction is squashed 1711system.cpu0.iew.lsq.thread0.memOrderViolation 13108 # Number of memory ordering violations 1712system.cpu0.iew.lsq.thread0.squashedStores 538058 # Number of stores squashed | 1698system.cpu0.iew.lsq.thread0.squashedLoads 1373139 # Number of loads squashed 1699system.cpu0.iew.lsq.thread0.ignoredResponses 2492 # Number of memory responses ignored because the instruction is squashed 1700system.cpu0.iew.lsq.thread0.memOrderViolation 13119 # Number of memory ordering violations 1701system.cpu0.iew.lsq.thread0.squashedStores 536810 # Number of stores squashed |
| 1713system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1714system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1702system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1703system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1715system.cpu0.iew.lsq.thread0.rescheduledLoads 2149551 # Number of loads that were rescheduled 1716system.cpu0.iew.lsq.thread0.cacheBlocked 5893 # Number of times an access to memory failed due to the cache being blocked | 1704system.cpu0.iew.lsq.thread0.rescheduledLoads 2149889 # Number of loads that were rescheduled 1705system.cpu0.iew.lsq.thread0.cacheBlocked 5851 # Number of times an access to memory failed due to the cache being blocked |
| 1717system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1706system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1718system.cpu0.iew.iewSquashCycles 981962 # Number of cycles IEW is squashing 1719system.cpu0.iew.iewBlockCycles 4290254 # Number of cycles IEW is blocking 1720system.cpu0.iew.iewUnblockCycles 101346 # Number of cycles IEW is unblocking 1721system.cpu0.iew.iewDispatchedInsts 38366333 # Number of instructions dispatched to IQ 1722system.cpu0.iew.iewDispSquashedInsts 82356 # Number of squashed instructions skipped by dispatch 1723system.cpu0.iew.iewDispLoadInsts 7756413 # Number of dispatched load instructions 1724system.cpu0.iew.iewDispStoreInsts 5773431 # Number of dispatched store instructions 1725system.cpu0.iew.iewDispNonSpecInsts 579216 # Number of dispatched non-speculative instructions 1726system.cpu0.iew.iewIQFullEvents 40773 # Number of times the IQ has become full, causing a stall 1727system.cpu0.iew.iewLSQFullEvents 5894 # Number of times the LSQ has become full, causing a stall 1728system.cpu0.iew.memOrderViolationEvents 13108 # Number of memory order violations 1729system.cpu0.iew.predictedTakenIncorrect 150282 # Number of branches that were predicted taken incorrectly 1730system.cpu0.iew.predictedNotTakenIncorrect 117544 # Number of branches that were predicted not taken incorrectly 1731system.cpu0.iew.branchMispredicts 267826 # Number of branch mispredicts detected at execute 1732system.cpu0.iew.iewExecutedInsts 37333576 # Number of executed instructions 1733system.cpu0.iew.iewExecLoadInsts 9286892 # Number of load instructions executed 1734system.cpu0.iew.iewExecSquashedInsts 379050 # Number of squashed instructions skipped in execute | 1707system.cpu0.iew.iewSquashCycles 981554 # Number of cycles IEW is squashing 1708system.cpu0.iew.iewBlockCycles 4303712 # Number of cycles IEW is blocking 1709system.cpu0.iew.iewUnblockCycles 102086 # Number of cycles IEW is unblocking 1710system.cpu0.iew.iewDispatchedInsts 38375609 # Number of instructions dispatched to IQ 1711system.cpu0.iew.iewDispSquashedInsts 82190 # Number of squashed instructions skipped by dispatch 1712system.cpu0.iew.iewDispLoadInsts 7760142 # Number of dispatched load instructions 1713system.cpu0.iew.iewDispStoreInsts 5773435 # Number of dispatched store instructions 1714system.cpu0.iew.iewDispNonSpecInsts 578535 # Number of dispatched non-speculative instructions 1715system.cpu0.iew.iewIQFullEvents 41087 # Number of times the IQ has become full, causing a stall 1716system.cpu0.iew.iewLSQFullEvents 6130 # Number of times the LSQ has become full, causing a stall 1717system.cpu0.iew.memOrderViolationEvents 13119 # Number of memory order violations 1718system.cpu0.iew.predictedTakenIncorrect 149567 # Number of branches that were predicted taken incorrectly 1719system.cpu0.iew.predictedNotTakenIncorrect 117143 # Number of branches that were predicted not taken incorrectly 1720system.cpu0.iew.branchMispredicts 266710 # Number of branch mispredicts detected at execute 1721system.cpu0.iew.iewExecutedInsts 37339391 # Number of executed instructions 1722system.cpu0.iew.iewExecLoadInsts 9288472 # Number of load instructions executed 1723system.cpu0.iew.iewExecSquashedInsts 379718 # Number of squashed instructions skipped in execute |
| 1735system.cpu0.iew.exec_swp 0 # number of swp insts executed | 1724system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 1736system.cpu0.iew.exec_nop 118063 # number of nop insts executed 1737system.cpu0.iew.exec_refs 14771553 # number of memory reference insts executed 1738system.cpu0.iew.exec_branches 4961106 # Number of branches executed 1739system.cpu0.iew.exec_stores 5484661 # Number of stores executed 1740system.cpu0.iew.exec_rate 0.531636 # Inst execution rate 1741system.cpu0.iew.wb_sent 37138785 # cumulative count of insts sent to commit 1742system.cpu0.iew.wb_count 34853166 # cumulative count of insts written-back 1743system.cpu0.iew.wb_producers 18592793 # num instructions producing a value 1744system.cpu0.iew.wb_consumers 35689861 # num instructions consuming a value | 1725system.cpu0.iew.exec_nop 118458 # number of nop insts executed 1726system.cpu0.iew.exec_refs 14775675 # number of memory reference insts executed 1727system.cpu0.iew.exec_branches 4960531 # Number of branches executed 1728system.cpu0.iew.exec_stores 5487203 # Number of stores executed 1729system.cpu0.iew.exec_rate 0.531584 # Inst execution rate 1730system.cpu0.iew.wb_sent 37145263 # cumulative count of insts sent to commit 1731system.cpu0.iew.wb_count 34859509 # cumulative count of insts written-back 1732system.cpu0.iew.wb_producers 18586335 # num instructions producing a value 1733system.cpu0.iew.wb_consumers 35686170 # num instructions consuming a value |
| 1745system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1734system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1746system.cpu0.iew.wb_rate 0.496314 # insts written-back per cycle 1747system.cpu0.iew.wb_fanout 0.520954 # average fanout of values written-back | 1735system.cpu0.iew.wb_rate 0.496279 # insts written-back per cycle 1736system.cpu0.iew.wb_fanout 0.520827 # average fanout of values written-back |
| 1748system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1737system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1749system.cpu0.commit.commitSquashedInsts 6112781 # The number of squashed insts skipped by commit 1750system.cpu0.commit.commitNonSpecStalls 649019 # The number of times commit has been forced to stall to communicate backwards 1751system.cpu0.commit.branchMispredicts 232084 # The number of times a branch was mispredicted 1752system.cpu0.commit.committed_per_cycle::samples 41441192 # Number of insts commited each cycle 1753system.cpu0.commit.committed_per_cycle::mean 0.767334 # Number of insts commited each cycle 1754system.cpu0.commit.committed_per_cycle::stdev 1.727698 # Number of insts commited each cycle | 1738system.cpu0.commit.commitSquashedInsts 6112161 # The number of squashed insts skipped by commit 1739system.cpu0.commit.commitNonSpecStalls 649014 # The number of times commit has been forced to stall to communicate backwards 1740system.cpu0.commit.branchMispredicts 230918 # The number of times a branch was mispredicted 1741system.cpu0.commit.committed_per_cycle::samples 41461251 # Number of insts commited each cycle 1742system.cpu0.commit.committed_per_cycle::mean 0.767144 # Number of insts commited each cycle 1743system.cpu0.commit.committed_per_cycle::stdev 1.727678 # Number of insts commited each cycle |
| 1755system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1744system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1756system.cpu0.commit.committed_per_cycle::0 29493448 71.17% 71.17% # Number of insts commited each cycle 1757system.cpu0.commit.committed_per_cycle::1 5926009 14.30% 85.47% # Number of insts commited each cycle 1758system.cpu0.commit.committed_per_cycle::2 1935659 4.67% 90.14% # Number of insts commited each cycle 1759system.cpu0.commit.committed_per_cycle::3 1007052 2.43% 92.57% # Number of insts commited each cycle 1760system.cpu0.commit.committed_per_cycle::4 761622 1.84% 94.41% # Number of insts commited each cycle 1761system.cpu0.commit.committed_per_cycle::5 520069 1.25% 95.66% # Number of insts commited each cycle 1762system.cpu0.commit.committed_per_cycle::6 411110 0.99% 96.65% # Number of insts commited each cycle 1763system.cpu0.commit.committed_per_cycle::7 222523 0.54% 97.19% # Number of insts commited each cycle 1764system.cpu0.commit.committed_per_cycle::8 1163700 2.81% 100.00% # Number of insts commited each cycle | 1745system.cpu0.commit.committed_per_cycle::0 29511356 71.18% 71.18% # Number of insts commited each cycle 1746system.cpu0.commit.committed_per_cycle::1 5920392 14.28% 85.46% # Number of insts commited each cycle 1747system.cpu0.commit.committed_per_cycle::2 1945303 4.69% 90.15% # Number of insts commited each cycle 1748system.cpu0.commit.committed_per_cycle::3 1006881 2.43% 92.58% # Number of insts commited each cycle 1749system.cpu0.commit.committed_per_cycle::4 766693 1.85% 94.43% # Number of insts commited each cycle 1750system.cpu0.commit.committed_per_cycle::5 514145 1.24% 95.67% # Number of insts commited each cycle 1751system.cpu0.commit.committed_per_cycle::6 405651 0.98% 96.65% # Number of insts commited each cycle 1752system.cpu0.commit.committed_per_cycle::7 222934 0.54% 97.18% # Number of insts commited each cycle 1753system.cpu0.commit.committed_per_cycle::8 1167896 2.82% 100.00% # Number of insts commited each cycle |
| 1765system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1766system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1767system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1754system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1755system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1756system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1768system.cpu0.commit.committed_per_cycle::total 41441192 # Number of insts commited each cycle 1769system.cpu0.commit.committedInsts 24076968 # Number of instructions committed 1770system.cpu0.commit.committedOps 31799237 # Number of ops (including micro ops) committed | 1757system.cpu0.commit.committed_per_cycle::total 41461251 # Number of insts commited each cycle 1758system.cpu0.commit.committedInsts 24081359 # Number of instructions committed 1759system.cpu0.commit.committedOps 31806750 # Number of ops (including micro ops) committed |
| 1771system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 1760system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 1772system.cpu0.commit.refs 11620664 # Number of memory references committed 1773system.cpu0.commit.loads 6385291 # Number of loads committed 1774system.cpu0.commit.membars 231891 # Number of memory barriers committed 1775system.cpu0.commit.branches 4352331 # Number of branches committed | 1761system.cpu0.commit.refs 11623628 # Number of memory references committed 1762system.cpu0.commit.loads 6387003 # Number of loads committed 1763system.cpu0.commit.membars 231881 # Number of memory barriers committed 1764system.cpu0.commit.branches 4353159 # Number of branches committed |
| 1776system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. | 1765system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. |
| 1777system.cpu0.commit.int_insts 28144226 # Number of committed integer instructions. 1778system.cpu0.commit.function_calls 499126 # Number of function calls committed. 1779system.cpu0.commit.bw_lim_events 1163700 # number cycles where commit BW limit reached | 1766system.cpu0.commit.int_insts 28151052 # Number of committed integer instructions. 1767system.cpu0.commit.function_calls 499153 # Number of function calls committed. 1768system.cpu0.commit.bw_lim_events 1167896 # number cycles where commit BW limit reached |
| 1780system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 1769system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1781system.cpu0.rob.rob_reads 77320455 # The number of ROB reads 1782system.cpu0.rob.rob_writes 76807713 # The number of ROB writes 1783system.cpu0.timesIdled 366523 # Number of times that the entire CPU went into an idle state and unscheduled itself 1784system.cpu0.idleCycles 27800814 # Total number of cycles that the CPU has spent unscheduled due to idling 1785system.cpu0.quiesceCycles 5141023759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1786system.cpu0.committedInsts 23996226 # Number of Instructions Simulated 1787system.cpu0.committedOps 31718495 # Number of Ops (including micro ops) Simulated 1788system.cpu0.committedInsts_total 23996226 # Number of Instructions Simulated 1789system.cpu0.cpi 2.926459 # CPI: Cycles Per Instruction 1790system.cpu0.cpi_total 2.926459 # CPI: Total CPI of All Threads 1791system.cpu0.ipc 0.341710 # IPC: Instructions Per Cycle 1792system.cpu0.ipc_total 0.341710 # IPC: Total IPC of All Threads 1793system.cpu0.int_regfile_reads 174280890 # number of integer regfile reads 1794system.cpu0.int_regfile_writes 34606104 # number of integer regfile writes 1795system.cpu0.fp_regfile_reads 3371 # number of floating regfile reads 1796system.cpu0.fp_regfile_writes 930 # number of floating regfile writes 1797system.cpu0.misc_regfile_reads 79193882 # number of misc regfile reads 1798system.cpu0.misc_regfile_writes 501030 # number of misc regfile writes 1799system.cpu0.icache.tags.replacements 399855 # number of replacements 1800system.cpu0.icache.tags.tagsinuse 511.561575 # Cycle average of tags in use 1801system.cpu0.icache.tags.total_refs 3845551 # Total number of references to valid blocks. 1802system.cpu0.icache.tags.sampled_refs 400367 # Sample count of references to valid blocks. 1803system.cpu0.icache.tags.avg_refs 9.605065 # Average number of references to valid blocks. 1804system.cpu0.icache.tags.warmup_cycle 7054920250 # Cycle when the warmup percentage was hit. 1805system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.561575 # Average occupied blocks per requestor 1806system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy 1807system.cpu0.icache.tags.occ_percent::total 0.999144 # Average percentage of cache occupancy | 1770system.cpu0.rob.rob_reads 77343282 # The number of ROB reads 1771system.cpu0.rob.rob_writes 76821100 # The number of ROB writes 1772system.cpu0.timesIdled 366365 # Number of times that the entire CPU went into an idle state and unscheduled itself 1773system.cpu0.idleCycles 27798940 # Total number of cycles that the CPU has spent unscheduled due to idling 1774system.cpu0.quiesceCycles 5140962052 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1775system.cpu0.committedInsts 24000617 # Number of Instructions Simulated 1776system.cpu0.committedOps 31726008 # Number of Ops (including micro ops) Simulated 1777system.cpu0.committedInsts_total 24000617 # Number of Instructions Simulated 1778system.cpu0.cpi 2.926664 # CPI: Cycles Per Instruction 1779system.cpu0.cpi_total 2.926664 # CPI: Total CPI of All Threads 1780system.cpu0.ipc 0.341686 # IPC: Instructions Per Cycle 1781system.cpu0.ipc_total 0.341686 # IPC: Total IPC of All Threads 1782system.cpu0.int_regfile_reads 174312752 # number of integer regfile reads 1783system.cpu0.int_regfile_writes 34607985 # number of integer regfile writes 1784system.cpu0.fp_regfile_reads 3310 # number of floating regfile reads 1785system.cpu0.fp_regfile_writes 918 # number of floating regfile writes 1786system.cpu0.misc_regfile_reads 79392098 # number of misc regfile reads 1787system.cpu0.misc_regfile_writes 500989 # number of misc regfile writes 1788system.cpu0.icache.tags.replacements 399371 # number of replacements 1789system.cpu0.icache.tags.tagsinuse 511.568929 # Cycle average of tags in use 1790system.cpu0.icache.tags.total_refs 3842185 # Total number of references to valid blocks. 1791system.cpu0.icache.tags.sampled_refs 399883 # Sample count of references to valid blocks. 1792system.cpu0.icache.tags.avg_refs 9.608273 # Average number of references to valid blocks. 1793system.cpu0.icache.tags.warmup_cycle 7067442000 # Cycle when the warmup percentage was hit. 1794system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568929 # Average occupied blocks per requestor 1795system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999158 # Average percentage of cache occupancy 1796system.cpu0.icache.tags.occ_percent::total 0.999158 # Average percentage of cache occupancy |
| 1808system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1797system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1809system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 1810system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id 1811system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id 1812system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id | 1798system.cpu0.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id 1799system.cpu0.icache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id 1800system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id 1801system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id |
| 1813system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1802system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1814system.cpu0.icache.tags.tag_accesses 4677842 # Number of tag accesses 1815system.cpu0.icache.tags.data_accesses 4677842 # Number of data accesses 1816system.cpu0.icache.ReadReq_hits::cpu0.inst 3845551 # number of ReadReq hits 1817system.cpu0.icache.ReadReq_hits::total 3845551 # number of ReadReq hits 1818system.cpu0.icache.demand_hits::cpu0.inst 3845551 # number of demand (read+write) hits 1819system.cpu0.icache.demand_hits::total 3845551 # number of demand (read+write) hits 1820system.cpu0.icache.overall_hits::cpu0.inst 3845551 # number of overall hits 1821system.cpu0.icache.overall_hits::total 3845551 # number of overall hits 1822system.cpu0.icache.ReadReq_misses::cpu0.inst 431900 # number of ReadReq misses 1823system.cpu0.icache.ReadReq_misses::total 431900 # number of ReadReq misses 1824system.cpu0.icache.demand_misses::cpu0.inst 431900 # number of demand (read+write) misses 1825system.cpu0.icache.demand_misses::total 431900 # number of demand (read+write) misses 1826system.cpu0.icache.overall_misses::cpu0.inst 431900 # number of overall misses 1827system.cpu0.icache.overall_misses::total 431900 # number of overall misses 1828system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5980648802 # number of ReadReq miss cycles 1829system.cpu0.icache.ReadReq_miss_latency::total 5980648802 # number of ReadReq miss cycles 1830system.cpu0.icache.demand_miss_latency::cpu0.inst 5980648802 # number of demand (read+write) miss cycles 1831system.cpu0.icache.demand_miss_latency::total 5980648802 # number of demand (read+write) miss cycles 1832system.cpu0.icache.overall_miss_latency::cpu0.inst 5980648802 # number of overall miss cycles 1833system.cpu0.icache.overall_miss_latency::total 5980648802 # number of overall miss cycles 1834system.cpu0.icache.ReadReq_accesses::cpu0.inst 4277451 # number of ReadReq accesses(hits+misses) 1835system.cpu0.icache.ReadReq_accesses::total 4277451 # number of ReadReq accesses(hits+misses) 1836system.cpu0.icache.demand_accesses::cpu0.inst 4277451 # number of demand (read+write) accesses 1837system.cpu0.icache.demand_accesses::total 4277451 # number of demand (read+write) accesses 1838system.cpu0.icache.overall_accesses::cpu0.inst 4277451 # number of overall (read+write) accesses 1839system.cpu0.icache.overall_accesses::total 4277451 # number of overall (read+write) accesses 1840system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100971 # miss rate for ReadReq accesses 1841system.cpu0.icache.ReadReq_miss_rate::total 0.100971 # miss rate for ReadReq accesses 1842system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100971 # miss rate for demand accesses 1843system.cpu0.icache.demand_miss_rate::total 0.100971 # miss rate for demand accesses 1844system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100971 # miss rate for overall accesses 1845system.cpu0.icache.overall_miss_rate::total 0.100971 # miss rate for overall accesses 1846system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13847.299843 # average ReadReq miss latency 1847system.cpu0.icache.ReadReq_avg_miss_latency::total 13847.299843 # average ReadReq miss latency 1848system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13847.299843 # average overall miss latency 1849system.cpu0.icache.demand_avg_miss_latency::total 13847.299843 # average overall miss latency 1850system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13847.299843 # average overall miss latency 1851system.cpu0.icache.overall_avg_miss_latency::total 13847.299843 # average overall miss latency 1852system.cpu0.icache.blocked_cycles::no_mshrs 3472 # number of cycles access was blocked | 1803system.cpu0.icache.tags.tag_accesses 4673316 # Number of tag accesses 1804system.cpu0.icache.tags.data_accesses 4673316 # Number of data accesses 1805system.cpu0.icache.ReadReq_hits::cpu0.inst 3842185 # number of ReadReq hits 1806system.cpu0.icache.ReadReq_hits::total 3842185 # number of ReadReq hits 1807system.cpu0.icache.demand_hits::cpu0.inst 3842185 # number of demand (read+write) hits 1808system.cpu0.icache.demand_hits::total 3842185 # number of demand (read+write) hits 1809system.cpu0.icache.overall_hits::cpu0.inst 3842185 # number of overall hits 1810system.cpu0.icache.overall_hits::total 3842185 # number of overall hits 1811system.cpu0.icache.ReadReq_misses::cpu0.inst 431224 # number of ReadReq misses 1812system.cpu0.icache.ReadReq_misses::total 431224 # number of ReadReq misses 1813system.cpu0.icache.demand_misses::cpu0.inst 431224 # number of demand (read+write) misses 1814system.cpu0.icache.demand_misses::total 431224 # number of demand (read+write) misses 1815system.cpu0.icache.overall_misses::cpu0.inst 431224 # number of overall misses 1816system.cpu0.icache.overall_misses::total 431224 # number of overall misses 1817system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969029520 # number of ReadReq miss cycles 1818system.cpu0.icache.ReadReq_miss_latency::total 5969029520 # number of ReadReq miss cycles 1819system.cpu0.icache.demand_miss_latency::cpu0.inst 5969029520 # number of demand (read+write) miss cycles 1820system.cpu0.icache.demand_miss_latency::total 5969029520 # number of demand (read+write) miss cycles 1821system.cpu0.icache.overall_miss_latency::cpu0.inst 5969029520 # number of overall miss cycles 1822system.cpu0.icache.overall_miss_latency::total 5969029520 # number of overall miss cycles 1823system.cpu0.icache.ReadReq_accesses::cpu0.inst 4273409 # number of ReadReq accesses(hits+misses) 1824system.cpu0.icache.ReadReq_accesses::total 4273409 # number of ReadReq accesses(hits+misses) 1825system.cpu0.icache.demand_accesses::cpu0.inst 4273409 # number of demand (read+write) accesses 1826system.cpu0.icache.demand_accesses::total 4273409 # number of demand (read+write) accesses 1827system.cpu0.icache.overall_accesses::cpu0.inst 4273409 # number of overall (read+write) accesses 1828system.cpu0.icache.overall_accesses::total 4273409 # number of overall (read+write) accesses 1829system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100909 # miss rate for ReadReq accesses 1830system.cpu0.icache.ReadReq_miss_rate::total 0.100909 # miss rate for ReadReq accesses 1831system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100909 # miss rate for demand accesses 1832system.cpu0.icache.demand_miss_rate::total 0.100909 # miss rate for demand accesses 1833system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100909 # miss rate for overall accesses 1834system.cpu0.icache.overall_miss_rate::total 0.100909 # miss rate for overall accesses 1835system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13842.062408 # average ReadReq miss latency 1836system.cpu0.icache.ReadReq_avg_miss_latency::total 13842.062408 # average ReadReq miss latency 1837system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13842.062408 # average overall miss latency 1838system.cpu0.icache.demand_avg_miss_latency::total 13842.062408 # average overall miss latency 1839system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13842.062408 # average overall miss latency 1840system.cpu0.icache.overall_avg_miss_latency::total 13842.062408 # average overall miss latency 1841system.cpu0.icache.blocked_cycles::no_mshrs 4009 # number of cycles access was blocked |
| 1853system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1842system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1854system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked | 1843system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked |
| 1855system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 1844system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1856system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.993377 # average number of cycles each access was blocked | 1845system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.308140 # average number of cycles each access was blocked |
| 1857system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1858system.cpu0.icache.fast_writes 0 # number of fast writes performed 1859system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1846system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1847system.cpu0.icache.fast_writes 0 # number of fast writes performed 1848system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1860system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31508 # number of ReadReq MSHR hits 1861system.cpu0.icache.ReadReq_mshr_hits::total 31508 # number of ReadReq MSHR hits 1862system.cpu0.icache.demand_mshr_hits::cpu0.inst 31508 # number of demand (read+write) MSHR hits 1863system.cpu0.icache.demand_mshr_hits::total 31508 # number of demand (read+write) MSHR hits 1864system.cpu0.icache.overall_mshr_hits::cpu0.inst 31508 # number of overall MSHR hits 1865system.cpu0.icache.overall_mshr_hits::total 31508 # number of overall MSHR hits 1866system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400392 # number of ReadReq MSHR misses 1867system.cpu0.icache.ReadReq_mshr_misses::total 400392 # number of ReadReq MSHR misses 1868system.cpu0.icache.demand_mshr_misses::cpu0.inst 400392 # number of demand (read+write) MSHR misses 1869system.cpu0.icache.demand_mshr_misses::total 400392 # number of demand (read+write) MSHR misses 1870system.cpu0.icache.overall_mshr_misses::cpu0.inst 400392 # number of overall MSHR misses 1871system.cpu0.icache.overall_mshr_misses::total 400392 # number of overall MSHR misses 1872system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4871658304 # number of ReadReq MSHR miss cycles 1873system.cpu0.icache.ReadReq_mshr_miss_latency::total 4871658304 # number of ReadReq MSHR miss cycles 1874system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4871658304 # number of demand (read+write) MSHR miss cycles 1875system.cpu0.icache.demand_mshr_miss_latency::total 4871658304 # number of demand (read+write) MSHR miss cycles 1876system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4871658304 # number of overall MSHR miss cycles 1877system.cpu0.icache.overall_mshr_miss_latency::total 4871658304 # number of overall MSHR miss cycles | 1849system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31316 # number of ReadReq MSHR hits 1850system.cpu0.icache.ReadReq_mshr_hits::total 31316 # number of ReadReq MSHR hits 1851system.cpu0.icache.demand_mshr_hits::cpu0.inst 31316 # number of demand (read+write) MSHR hits 1852system.cpu0.icache.demand_mshr_hits::total 31316 # number of demand (read+write) MSHR hits 1853system.cpu0.icache.overall_mshr_hits::cpu0.inst 31316 # number of overall MSHR hits 1854system.cpu0.icache.overall_mshr_hits::total 31316 # number of overall MSHR hits 1855system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399908 # number of ReadReq MSHR misses 1856system.cpu0.icache.ReadReq_mshr_misses::total 399908 # number of ReadReq MSHR misses 1857system.cpu0.icache.demand_mshr_misses::cpu0.inst 399908 # number of demand (read+write) MSHR misses 1858system.cpu0.icache.demand_mshr_misses::total 399908 # number of demand (read+write) MSHR misses 1859system.cpu0.icache.overall_mshr_misses::cpu0.inst 399908 # number of overall MSHR misses 1860system.cpu0.icache.overall_mshr_misses::total 399908 # number of overall MSHR misses 1861system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4860978096 # number of ReadReq MSHR miss cycles 1862system.cpu0.icache.ReadReq_mshr_miss_latency::total 4860978096 # number of ReadReq MSHR miss cycles 1863system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4860978096 # number of demand (read+write) MSHR miss cycles 1864system.cpu0.icache.demand_mshr_miss_latency::total 4860978096 # number of demand (read+write) MSHR miss cycles 1865system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4860978096 # number of overall MSHR miss cycles 1866system.cpu0.icache.overall_mshr_miss_latency::total 4860978096 # number of overall MSHR miss cycles |
| 1878system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9448000 # number of ReadReq MSHR uncacheable cycles 1879system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9448000 # number of ReadReq MSHR uncacheable cycles 1880system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9448000 # number of overall MSHR uncacheable cycles 1881system.cpu0.icache.overall_mshr_uncacheable_latency::total 9448000 # number of overall MSHR uncacheable cycles | 1867system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9448000 # number of ReadReq MSHR uncacheable cycles 1868system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9448000 # number of ReadReq MSHR uncacheable cycles 1869system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9448000 # number of overall MSHR uncacheable cycles 1870system.cpu0.icache.overall_mshr_uncacheable_latency::total 9448000 # number of overall MSHR uncacheable cycles |
| 1882system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for ReadReq accesses 1883system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093605 # mshr miss rate for ReadReq accesses 1884system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for demand accesses 1885system.cpu0.icache.demand_mshr_miss_rate::total 0.093605 # mshr miss rate for demand accesses 1886system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for overall accesses 1887system.cpu0.icache.overall_mshr_miss_rate::total 0.093605 # mshr miss rate for overall accesses 1888system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average ReadReq mshr miss latency 1889system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12167.221883 # average ReadReq mshr miss latency 1890system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average overall mshr miss latency 1891system.cpu0.icache.demand_avg_mshr_miss_latency::total 12167.221883 # average overall mshr miss latency 1892system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average overall mshr miss latency 1893system.cpu0.icache.overall_avg_mshr_miss_latency::total 12167.221883 # average overall mshr miss latency | 1871system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for ReadReq accesses 1872system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093581 # mshr miss rate for ReadReq accesses 1873system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for demand accesses 1874system.cpu0.icache.demand_mshr_miss_rate::total 0.093581 # mshr miss rate for demand accesses 1875system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for overall accesses 1876system.cpu0.icache.overall_mshr_miss_rate::total 0.093581 # mshr miss rate for overall accesses 1877system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average ReadReq mshr miss latency 1878system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12155.240945 # average ReadReq mshr miss latency 1879system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average overall mshr miss latency 1880system.cpu0.icache.demand_avg_mshr_miss_latency::total 12155.240945 # average overall mshr miss latency 1881system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average overall mshr miss latency 1882system.cpu0.icache.overall_avg_mshr_miss_latency::total 12155.240945 # average overall mshr miss latency |
| 1894system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1895system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1896system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1897system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1898system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1883system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1884system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1885system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1886system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1887system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1899system.cpu0.dcache.tags.replacements 275331 # number of replacements 1900system.cpu0.dcache.tags.tagsinuse 480.265935 # Cycle average of tags in use 1901system.cpu0.dcache.tags.total_refs 9430413 # Total number of references to valid blocks. 1902system.cpu0.dcache.tags.sampled_refs 275843 # Sample count of references to valid blocks. 1903system.cpu0.dcache.tags.avg_refs 34.187610 # Average number of references to valid blocks. | 1888system.cpu0.dcache.tags.replacements 275793 # number of replacements 1889system.cpu0.dcache.tags.tagsinuse 480.388822 # Cycle average of tags in use 1890system.cpu0.dcache.tags.total_refs 9427243 # Total number of references to valid blocks. 1891system.cpu0.dcache.tags.sampled_refs 276305 # Sample count of references to valid blocks. 1892system.cpu0.dcache.tags.avg_refs 34.118974 # Average number of references to valid blocks. |
| 1904system.cpu0.dcache.tags.warmup_cycle 43744250 # Cycle when the warmup percentage was hit. | 1893system.cpu0.dcache.tags.warmup_cycle 43744250 # Cycle when the warmup percentage was hit. |
| 1905system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.265935 # Average occupied blocks per requestor 1906system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938019 # Average percentage of cache occupancy 1907system.cpu0.dcache.tags.occ_percent::total 0.938019 # Average percentage of cache occupancy | 1894system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.388822 # Average occupied blocks per requestor 1895system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938259 # Average percentage of cache occupancy 1896system.cpu0.dcache.tags.occ_percent::total 0.938259 # Average percentage of cache occupancy |
| 1908system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1897system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1909system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 1910system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 1911system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id | 1898system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 1899system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 1900system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id |
| 1912system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1901system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1913system.cpu0.dcache.tags.tag_accesses 45818436 # Number of tag accesses 1914system.cpu0.dcache.tags.data_accesses 45818436 # Number of data accesses 1915system.cpu0.dcache.ReadReq_hits::cpu0.data 5876487 # number of ReadReq hits 1916system.cpu0.dcache.ReadReq_hits::total 5876487 # number of ReadReq hits 1917system.cpu0.dcache.WriteReq_hits::cpu0.data 3229447 # number of WriteReq hits 1918system.cpu0.dcache.WriteReq_hits::total 3229447 # number of WriteReq hits 1919system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139508 # number of LoadLockedReq hits 1920system.cpu0.dcache.LoadLockedReq_hits::total 139508 # number of LoadLockedReq hits 1921system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137243 # number of StoreCondReq hits 1922system.cpu0.dcache.StoreCondReq_hits::total 137243 # number of StoreCondReq hits 1923system.cpu0.dcache.demand_hits::cpu0.data 9105934 # number of demand (read+write) hits 1924system.cpu0.dcache.demand_hits::total 9105934 # number of demand (read+write) hits 1925system.cpu0.dcache.overall_hits::cpu0.data 9105934 # number of overall hits 1926system.cpu0.dcache.overall_hits::total 9105934 # number of overall hits 1927system.cpu0.dcache.ReadReq_misses::cpu0.data 392643 # number of ReadReq misses 1928system.cpu0.dcache.ReadReq_misses::total 392643 # number of ReadReq misses 1929system.cpu0.dcache.WriteReq_misses::cpu0.data 1584583 # number of WriteReq misses 1930system.cpu0.dcache.WriteReq_misses::total 1584583 # number of WriteReq misses 1931system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8921 # number of LoadLockedReq misses 1932system.cpu0.dcache.LoadLockedReq_misses::total 8921 # number of LoadLockedReq misses 1933system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7758 # number of StoreCondReq misses 1934system.cpu0.dcache.StoreCondReq_misses::total 7758 # number of StoreCondReq misses 1935system.cpu0.dcache.demand_misses::cpu0.data 1977226 # number of demand (read+write) misses 1936system.cpu0.dcache.demand_misses::total 1977226 # number of demand (read+write) misses 1937system.cpu0.dcache.overall_misses::cpu0.data 1977226 # number of overall misses 1938system.cpu0.dcache.overall_misses::total 1977226 # number of overall misses 1939system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519657990 # number of ReadReq miss cycles 1940system.cpu0.dcache.ReadReq_miss_latency::total 5519657990 # number of ReadReq miss cycles 1941system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80059065889 # number of WriteReq miss cycles 1942system.cpu0.dcache.WriteReq_miss_latency::total 80059065889 # number of WriteReq miss cycles 1943system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91816480 # number of LoadLockedReq miss cycles 1944system.cpu0.dcache.LoadLockedReq_miss_latency::total 91816480 # number of LoadLockedReq miss cycles 1945system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49938268 # number of StoreCondReq miss cycles 1946system.cpu0.dcache.StoreCondReq_miss_latency::total 49938268 # number of StoreCondReq miss cycles 1947system.cpu0.dcache.demand_miss_latency::cpu0.data 85578723879 # number of demand (read+write) miss cycles 1948system.cpu0.dcache.demand_miss_latency::total 85578723879 # number of demand (read+write) miss cycles 1949system.cpu0.dcache.overall_miss_latency::cpu0.data 85578723879 # number of overall miss cycles 1950system.cpu0.dcache.overall_miss_latency::total 85578723879 # number of overall miss cycles 1951system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269130 # number of ReadReq accesses(hits+misses) 1952system.cpu0.dcache.ReadReq_accesses::total 6269130 # number of ReadReq accesses(hits+misses) 1953system.cpu0.dcache.WriteReq_accesses::cpu0.data 4814030 # number of WriteReq accesses(hits+misses) 1954system.cpu0.dcache.WriteReq_accesses::total 4814030 # number of WriteReq accesses(hits+misses) 1955system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148429 # number of LoadLockedReq accesses(hits+misses) 1956system.cpu0.dcache.LoadLockedReq_accesses::total 148429 # number of LoadLockedReq accesses(hits+misses) 1957system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145001 # number of StoreCondReq accesses(hits+misses) 1958system.cpu0.dcache.StoreCondReq_accesses::total 145001 # number of StoreCondReq accesses(hits+misses) 1959system.cpu0.dcache.demand_accesses::cpu0.data 11083160 # number of demand (read+write) accesses 1960system.cpu0.dcache.demand_accesses::total 11083160 # number of demand (read+write) accesses 1961system.cpu0.dcache.overall_accesses::cpu0.data 11083160 # number of overall (read+write) accesses 1962system.cpu0.dcache.overall_accesses::total 11083160 # number of overall (read+write) accesses 1963system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062631 # miss rate for ReadReq accesses 1964system.cpu0.dcache.ReadReq_miss_rate::total 0.062631 # miss rate for ReadReq accesses 1965system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329159 # miss rate for WriteReq accesses 1966system.cpu0.dcache.WriteReq_miss_rate::total 0.329159 # miss rate for WriteReq accesses 1967system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060103 # miss rate for LoadLockedReq accesses 1968system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060103 # miss rate for LoadLockedReq accesses 1969system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053503 # miss rate for StoreCondReq accesses 1970system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053503 # miss rate for StoreCondReq accesses 1971system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178399 # miss rate for demand accesses 1972system.cpu0.dcache.demand_miss_rate::total 0.178399 # miss rate for demand accesses 1973system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178399 # miss rate for overall accesses 1974system.cpu0.dcache.overall_miss_rate::total 0.178399 # miss rate for overall accesses 1975system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14057.701245 # average ReadReq miss latency 1976system.cpu0.dcache.ReadReq_avg_miss_latency::total 14057.701245 # average ReadReq miss latency 1977system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50523.744032 # average WriteReq miss latency 1978system.cpu0.dcache.WriteReq_avg_miss_latency::total 50523.744032 # average WriteReq miss latency 1979system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10292.173523 # average LoadLockedReq miss latency 1980system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10292.173523 # average LoadLockedReq miss latency 1981system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6437.002836 # average StoreCondReq miss latency 1982system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6437.002836 # average StoreCondReq miss latency 1983system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency 1984system.cpu0.dcache.demand_avg_miss_latency::total 43282.216539 # average overall miss latency 1985system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency 1986system.cpu0.dcache.overall_avg_miss_latency::total 43282.216539 # average overall miss latency 1987system.cpu0.dcache.blocked_cycles::no_mshrs 9306 # number of cycles access was blocked 1988system.cpu0.dcache.blocked_cycles::no_targets 7994 # number of cycles access was blocked 1989system.cpu0.dcache.blocked::no_mshrs 611 # number of cycles access was blocked 1990system.cpu0.dcache.blocked::no_targets 137 # number of cycles access was blocked 1991system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.230769 # average number of cycles each access was blocked 1992system.cpu0.dcache.avg_blocked_cycles::no_targets 58.350365 # average number of cycles each access was blocked | 1902system.cpu0.dcache.tags.tag_accesses 45827663 # Number of tag accesses 1903system.cpu0.dcache.tags.data_accesses 45827663 # Number of data accesses 1904system.cpu0.dcache.ReadReq_hits::cpu0.data 5876905 # number of ReadReq hits 1905system.cpu0.dcache.ReadReq_hits::total 5876905 # number of ReadReq hits 1906system.cpu0.dcache.WriteReq_hits::cpu0.data 3228758 # number of WriteReq hits 1907system.cpu0.dcache.WriteReq_hits::total 3228758 # number of WriteReq hits 1908system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139532 # number of LoadLockedReq hits 1909system.cpu0.dcache.LoadLockedReq_hits::total 139532 # number of LoadLockedReq hits 1910system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137231 # number of StoreCondReq hits 1911system.cpu0.dcache.StoreCondReq_hits::total 137231 # number of StoreCondReq hits 1912system.cpu0.dcache.demand_hits::cpu0.data 9105663 # number of demand (read+write) hits 1913system.cpu0.dcache.demand_hits::total 9105663 # number of demand (read+write) hits 1914system.cpu0.dcache.overall_hits::cpu0.data 9105663 # number of overall hits 1915system.cpu0.dcache.overall_hits::total 9105663 # number of overall hits 1916system.cpu0.dcache.ReadReq_misses::cpu0.data 393187 # number of ReadReq misses 1917system.cpu0.dcache.ReadReq_misses::total 393187 # number of ReadReq misses 1918system.cpu0.dcache.WriteReq_misses::cpu0.data 1586487 # number of WriteReq misses 1919system.cpu0.dcache.WriteReq_misses::total 1586487 # number of WriteReq misses 1920system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses 1921system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses 1922system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7768 # number of StoreCondReq misses 1923system.cpu0.dcache.StoreCondReq_misses::total 7768 # number of StoreCondReq misses 1924system.cpu0.dcache.demand_misses::cpu0.data 1979674 # number of demand (read+write) misses 1925system.cpu0.dcache.demand_misses::total 1979674 # number of demand (read+write) misses 1926system.cpu0.dcache.overall_misses::cpu0.data 1979674 # number of overall misses 1927system.cpu0.dcache.overall_misses::total 1979674 # number of overall misses 1928system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5526786247 # number of ReadReq miss cycles 1929system.cpu0.dcache.ReadReq_miss_latency::total 5526786247 # number of ReadReq miss cycles 1930system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79724845605 # number of WriteReq miss cycles 1931system.cpu0.dcache.WriteReq_miss_latency::total 79724845605 # number of WriteReq miss cycles 1932system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91251732 # number of LoadLockedReq miss cycles 1933system.cpu0.dcache.LoadLockedReq_miss_latency::total 91251732 # number of LoadLockedReq miss cycles 1934system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50083768 # number of StoreCondReq miss cycles 1935system.cpu0.dcache.StoreCondReq_miss_latency::total 50083768 # number of StoreCondReq miss cycles 1936system.cpu0.dcache.demand_miss_latency::cpu0.data 85251631852 # number of demand (read+write) miss cycles 1937system.cpu0.dcache.demand_miss_latency::total 85251631852 # number of demand (read+write) miss cycles 1938system.cpu0.dcache.overall_miss_latency::cpu0.data 85251631852 # number of overall miss cycles 1939system.cpu0.dcache.overall_miss_latency::total 85251631852 # number of overall miss cycles 1940system.cpu0.dcache.ReadReq_accesses::cpu0.data 6270092 # number of ReadReq accesses(hits+misses) 1941system.cpu0.dcache.ReadReq_accesses::total 6270092 # number of ReadReq accesses(hits+misses) 1942system.cpu0.dcache.WriteReq_accesses::cpu0.data 4815245 # number of WriteReq accesses(hits+misses) 1943system.cpu0.dcache.WriteReq_accesses::total 4815245 # number of WriteReq accesses(hits+misses) 1944system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148435 # number of LoadLockedReq accesses(hits+misses) 1945system.cpu0.dcache.LoadLockedReq_accesses::total 148435 # number of LoadLockedReq accesses(hits+misses) 1946system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144999 # number of StoreCondReq accesses(hits+misses) 1947system.cpu0.dcache.StoreCondReq_accesses::total 144999 # number of StoreCondReq accesses(hits+misses) 1948system.cpu0.dcache.demand_accesses::cpu0.data 11085337 # number of demand (read+write) accesses 1949system.cpu0.dcache.demand_accesses::total 11085337 # number of demand (read+write) accesses 1950system.cpu0.dcache.overall_accesses::cpu0.data 11085337 # number of overall (read+write) accesses 1951system.cpu0.dcache.overall_accesses::total 11085337 # number of overall (read+write) accesses 1952system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062708 # miss rate for ReadReq accesses 1953system.cpu0.dcache.ReadReq_miss_rate::total 0.062708 # miss rate for ReadReq accesses 1954system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329472 # miss rate for WriteReq accesses 1955system.cpu0.dcache.WriteReq_miss_rate::total 0.329472 # miss rate for WriteReq accesses 1956system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059979 # miss rate for LoadLockedReq accesses 1957system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059979 # miss rate for LoadLockedReq accesses 1958system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053573 # miss rate for StoreCondReq accesses 1959system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053573 # miss rate for StoreCondReq accesses 1960system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178585 # miss rate for demand accesses 1961system.cpu0.dcache.demand_miss_rate::total 0.178585 # miss rate for demand accesses 1962system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178585 # miss rate for overall accesses 1963system.cpu0.dcache.overall_miss_rate::total 0.178585 # miss rate for overall accesses 1964system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14056.380926 # average ReadReq miss latency 1965system.cpu0.dcache.ReadReq_avg_miss_latency::total 14056.380926 # average ReadReq miss latency 1966system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50252.441782 # average WriteReq miss latency 1967system.cpu0.dcache.WriteReq_avg_miss_latency::total 50252.441782 # average WriteReq miss latency 1968system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10249.548691 # average LoadLockedReq miss latency 1969system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10249.548691 # average LoadLockedReq miss latency 1970system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6447.446962 # average StoreCondReq miss latency 1971system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6447.446962 # average StoreCondReq miss latency 1972system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43063.469971 # average overall miss latency 1973system.cpu0.dcache.demand_avg_miss_latency::total 43063.469971 # average overall miss latency 1974system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43063.469971 # average overall miss latency 1975system.cpu0.dcache.overall_avg_miss_latency::total 43063.469971 # average overall miss latency 1976system.cpu0.dcache.blocked_cycles::no_mshrs 8922 # number of cycles access was blocked 1977system.cpu0.dcache.blocked_cycles::no_targets 7566 # number of cycles access was blocked 1978system.cpu0.dcache.blocked::no_mshrs 589 # number of cycles access was blocked 1979system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked 1980system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.147708 # average number of cycles each access was blocked 1981system.cpu0.dcache.avg_blocked_cycles::no_targets 55.632353 # average number of cycles each access was blocked |
| 1993system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1994system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1982system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1983system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1995system.cpu0.dcache.writebacks::writebacks 255436 # number of writebacks 1996system.cpu0.dcache.writebacks::total 255436 # number of writebacks 1997system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203336 # number of ReadReq MSHR hits 1998system.cpu0.dcache.ReadReq_mshr_hits::total 203336 # number of ReadReq MSHR hits 1999system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453472 # number of WriteReq MSHR hits 2000system.cpu0.dcache.WriteReq_mshr_hits::total 1453472 # number of WriteReq MSHR hits 2001system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits 2002system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits 2003system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656808 # number of demand (read+write) MSHR hits 2004system.cpu0.dcache.demand_mshr_hits::total 1656808 # number of demand (read+write) MSHR hits 2005system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656808 # number of overall MSHR hits 2006system.cpu0.dcache.overall_mshr_hits::total 1656808 # number of overall MSHR hits 2007system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189307 # number of ReadReq MSHR misses 2008system.cpu0.dcache.ReadReq_mshr_misses::total 189307 # number of ReadReq MSHR misses 2009system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131111 # number of WriteReq MSHR misses 2010system.cpu0.dcache.WriteReq_mshr_misses::total 131111 # number of WriteReq MSHR misses 2011system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8437 # number of LoadLockedReq MSHR misses 2012system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8437 # number of LoadLockedReq MSHR misses 2013system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses 2014system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses 2015system.cpu0.dcache.demand_mshr_misses::cpu0.data 320418 # number of demand (read+write) MSHR misses 2016system.cpu0.dcache.demand_mshr_misses::total 320418 # number of demand (read+write) MSHR misses 2017system.cpu0.dcache.overall_mshr_misses::cpu0.data 320418 # number of overall MSHR misses 2018system.cpu0.dcache.overall_mshr_misses::total 320418 # number of overall MSHR misses 2019system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2405173678 # number of ReadReq MSHR miss cycles 2020system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2405173678 # number of ReadReq MSHR miss cycles 2021system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5317055578 # number of WriteReq MSHR miss cycles 2022system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5317055578 # number of WriteReq MSHR miss cycles 2023system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69940520 # number of LoadLockedReq MSHR miss cycles 2024system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69940520 # number of LoadLockedReq MSHR miss cycles 2025system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34423732 # number of StoreCondReq MSHR miss cycles 2026system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34423732 # number of StoreCondReq MSHR miss cycles | 1984system.cpu0.dcache.writebacks::writebacks 256103 # number of writebacks 1985system.cpu0.dcache.writebacks::total 256103 # number of writebacks 1986system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203673 # number of ReadReq MSHR hits 1987system.cpu0.dcache.ReadReq_mshr_hits::total 203673 # number of ReadReq MSHR hits 1988system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455296 # number of WriteReq MSHR hits 1989system.cpu0.dcache.WriteReq_mshr_hits::total 1455296 # number of WriteReq MSHR hits 1990system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits 1991system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits 1992system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658969 # number of demand (read+write) MSHR hits 1993system.cpu0.dcache.demand_mshr_hits::total 1658969 # number of demand (read+write) MSHR hits 1994system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658969 # number of overall MSHR hits 1995system.cpu0.dcache.overall_mshr_hits::total 1658969 # number of overall MSHR hits 1996system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189514 # number of ReadReq MSHR misses 1997system.cpu0.dcache.ReadReq_mshr_misses::total 189514 # number of ReadReq MSHR misses 1998system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131191 # number of WriteReq MSHR misses 1999system.cpu0.dcache.WriteReq_mshr_misses::total 131191 # number of WriteReq MSHR misses 2000system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8434 # number of LoadLockedReq MSHR misses 2001system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8434 # number of LoadLockedReq MSHR misses 2002system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7768 # number of StoreCondReq MSHR misses 2003system.cpu0.dcache.StoreCondReq_mshr_misses::total 7768 # number of StoreCondReq MSHR misses 2004system.cpu0.dcache.demand_mshr_misses::cpu0.data 320705 # number of demand (read+write) MSHR misses 2005system.cpu0.dcache.demand_mshr_misses::total 320705 # number of demand (read+write) MSHR misses 2006system.cpu0.dcache.overall_mshr_misses::cpu0.data 320705 # number of overall MSHR misses 2007system.cpu0.dcache.overall_mshr_misses::total 320705 # number of overall MSHR misses 2008system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2409533443 # number of ReadReq MSHR miss cycles 2009system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2409533443 # number of ReadReq MSHR miss cycles 2010system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5292752283 # number of WriteReq MSHR miss cycles 2011system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5292752283 # number of WriteReq MSHR miss cycles 2012system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69541268 # number of LoadLockedReq MSHR miss cycles 2013system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69541268 # number of LoadLockedReq MSHR miss cycles 2014system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34547232 # number of StoreCondReq MSHR miss cycles 2015system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34547232 # number of StoreCondReq MSHR miss cycles |
| 2027system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles 2028system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles | 2016system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles 2017system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles |
| 2029system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7722229256 # number of demand (read+write) MSHR miss cycles 2030system.cpu0.dcache.demand_mshr_miss_latency::total 7722229256 # number of demand (read+write) MSHR miss cycles 2031system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7722229256 # number of overall MSHR miss cycles 2032system.cpu0.dcache.overall_mshr_miss_latency::total 7722229256 # number of overall MSHR miss cycles 2033system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13428836532 # number of ReadReq MSHR uncacheable cycles 2034system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13428836532 # number of ReadReq MSHR uncacheable cycles 2035system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1202345879 # number of WriteReq MSHR uncacheable cycles 2036system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1202345879 # number of WriteReq MSHR uncacheable cycles 2037system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631182411 # number of overall MSHR uncacheable cycles 2038system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631182411 # number of overall MSHR uncacheable cycles 2039system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030197 # mshr miss rate for ReadReq accesses 2040system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030197 # mshr miss rate for ReadReq accesses 2041system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027235 # mshr miss rate for WriteReq accesses 2042system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027235 # mshr miss rate for WriteReq accesses 2043system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056842 # mshr miss rate for LoadLockedReq accesses 2044system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056842 # mshr miss rate for LoadLockedReq accesses 2045system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053503 # mshr miss rate for StoreCondReq accesses 2046system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053503 # mshr miss rate for StoreCondReq accesses 2047system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for demand accesses 2048system.cpu0.dcache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses 2049system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for overall accesses 2050system.cpu0.dcache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses 2051system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.149192 # average ReadReq mshr miss latency 2052system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.149192 # average ReadReq mshr miss latency 2053system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40553.848098 # average WriteReq mshr miss latency 2054system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40553.848098 # average WriteReq mshr miss latency 2055system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8289.738059 # average LoadLockedReq mshr miss latency 2056system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8289.738059 # average LoadLockedReq mshr miss latency 2057system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4437.191544 # average StoreCondReq mshr miss latency 2058system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4437.191544 # average StoreCondReq mshr miss latency | 2018system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7702285726 # number of demand (read+write) MSHR miss cycles 2019system.cpu0.dcache.demand_mshr_miss_latency::total 7702285726 # number of demand (read+write) MSHR miss cycles 2020system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7702285726 # number of overall MSHR miss cycles 2021system.cpu0.dcache.overall_mshr_miss_latency::total 7702285726 # number of overall MSHR miss cycles 2022system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13436185037 # number of ReadReq MSHR uncacheable cycles 2023system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13436185037 # number of ReadReq MSHR uncacheable cycles 2024system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206083884 # number of WriteReq MSHR uncacheable cycles 2025system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206083884 # number of WriteReq MSHR uncacheable cycles 2026system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14642268921 # number of overall MSHR uncacheable cycles 2027system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14642268921 # number of overall MSHR uncacheable cycles 2028system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030225 # mshr miss rate for ReadReq accesses 2029system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030225 # mshr miss rate for ReadReq accesses 2030system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027245 # mshr miss rate for WriteReq accesses 2031system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027245 # mshr miss rate for WriteReq accesses 2032system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056819 # mshr miss rate for LoadLockedReq accesses 2033system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056819 # mshr miss rate for LoadLockedReq accesses 2034system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053573 # mshr miss rate for StoreCondReq accesses 2035system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053573 # mshr miss rate for StoreCondReq accesses 2036system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028931 # mshr miss rate for demand accesses 2037system.cpu0.dcache.demand_mshr_miss_rate::total 0.028931 # mshr miss rate for demand accesses 2038system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028931 # mshr miss rate for overall accesses 2039system.cpu0.dcache.overall_mshr_miss_rate::total 0.028931 # mshr miss rate for overall accesses 2040system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12714.276745 # average ReadReq mshr miss latency 2041system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12714.276745 # average ReadReq mshr miss latency 2042system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40343.867209 # average WriteReq mshr miss latency 2043system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40343.867209 # average WriteReq mshr miss latency 2044system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8245.348352 # average LoadLockedReq mshr miss latency 2045system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8245.348352 # average LoadLockedReq mshr miss latency 2046system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4447.377961 # average StoreCondReq mshr miss latency 2047system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4447.377961 # average StoreCondReq mshr miss latency |
| 2059system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2060system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2048system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2049system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2061system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency 2062system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency 2063system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency 2064system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency | 2050system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24016.731033 # average overall mshr miss latency 2051system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24016.731033 # average overall mshr miss latency 2052system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24016.731033 # average overall mshr miss latency 2053system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24016.731033 # average overall mshr miss latency |
| 2065system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2066system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2067system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2068system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2069system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2070system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2071system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2054system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2055system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2056system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2057system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2058system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2059system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2060system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2072system.cpu1.branchPred.lookups 9295999 # Number of BP lookups 2073system.cpu1.branchPred.condPredicted 7633656 # Number of conditional branches predicted 2074system.cpu1.branchPred.condIncorrect 416141 # Number of conditional branches incorrect 2075system.cpu1.branchPred.BTBLookups 5924050 # Number of BTB lookups 2076system.cpu1.branchPred.BTBHits 5051274 # Number of BTB hits | 2061system.cpu1.branchPred.lookups 9293568 # Number of BP lookups 2062system.cpu1.branchPred.condPredicted 7630023 # Number of conditional branches predicted 2063system.cpu1.branchPred.condIncorrect 416409 # Number of conditional branches incorrect 2064system.cpu1.branchPred.BTBLookups 5939121 # Number of BTB lookups 2065system.cpu1.branchPred.BTBHits 5050753 # Number of BTB hits |
| 2077system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 2066system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 2078system.cpu1.branchPred.BTBHitPct 85.267241 # BTB Hit Percentage 2079system.cpu1.branchPred.usedRAS 796895 # Number of times the RAS was used to get a target. 2080system.cpu1.branchPred.RASInCorrect 43453 # Number of incorrect RAS predictions. | 2067system.cpu1.branchPred.BTBHitPct 85.042096 # BTB Hit Percentage 2068system.cpu1.branchPred.usedRAS 798930 # Number of times the RAS was used to get a target. 2069system.cpu1.branchPred.RASInCorrect 43976 # Number of incorrect RAS predictions. |
| 2081system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2082system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2083system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2084system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2085system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2086system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2087system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2088system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 2096system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2097system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2098system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2099system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2100system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2101system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2102system.cpu1.dtb.inst_hits 0 # ITB inst hits 2103system.cpu1.dtb.inst_misses 0 # ITB inst misses | 2070system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2071system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2072system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2073system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2074system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2075system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2076system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2077system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 2085system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2086system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2087system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2088system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2089system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2090system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2091system.cpu1.dtb.inst_hits 0 # ITB inst hits 2092system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 2104system.cpu1.dtb.read_hits 42971577 # DTB read hits 2105system.cpu1.dtb.read_misses 38230 # DTB read misses 2106system.cpu1.dtb.write_hits 6978417 # DTB write hits 2107system.cpu1.dtb.write_misses 10824 # DTB write misses | 2093system.cpu1.dtb.read_hits 42973192 # DTB read hits 2094system.cpu1.dtb.read_misses 37885 # DTB read misses 2095system.cpu1.dtb.write_hits 6980403 # DTB write hits 2096system.cpu1.dtb.write_misses 10788 # DTB write misses |
| 2108system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2109system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2110system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2111system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 2097system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2098system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2099system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2100system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 2112system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB 2113system.cpu1.dtb.align_faults 2766 # Number of TLB faults due to alignment restrictions 2114system.cpu1.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch | 2101system.cpu1.dtb.flush_entries 1925 # Number of entries that have been flushed from TLB 2102system.cpu1.dtb.align_faults 2835 # Number of TLB faults due to alignment restrictions 2103system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch |
| 2115system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2116system.cpu1.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions | 2104system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2105system.cpu1.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions |
| 2117system.cpu1.dtb.read_accesses 43009807 # DTB read accesses 2118system.cpu1.dtb.write_accesses 6989241 # DTB write accesses | 2106system.cpu1.dtb.read_accesses 43011077 # DTB read accesses 2107system.cpu1.dtb.write_accesses 6991191 # DTB write accesses |
| 2119system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 2108system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 2120system.cpu1.dtb.hits 49949994 # DTB hits 2121system.cpu1.dtb.misses 49054 # DTB misses 2122system.cpu1.dtb.accesses 49999048 # DTB accesses | 2109system.cpu1.dtb.hits 49953595 # DTB hits 2110system.cpu1.dtb.misses 48673 # DTB misses 2111system.cpu1.dtb.accesses 50002268 # DTB accesses |
| 2123system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2124system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2125system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2126system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2127system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2128system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2129system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2130system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 2136system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2137system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2138system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2139system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2140system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2141system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2142system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2143system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 2112system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2113system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2114system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2115system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2116system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2117system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2118system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2119system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 2125system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2126system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2127system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2128system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2129system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2130system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2131system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2132system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 2144system.cpu1.itb.inst_hits 7718441 # ITB inst hits 2145system.cpu1.itb.inst_misses 5545 # ITB inst misses | 2133system.cpu1.itb.inst_hits 7723190 # ITB inst hits 2134system.cpu1.itb.inst_misses 5562 # ITB inst misses |
| 2146system.cpu1.itb.read_hits 0 # DTB read hits 2147system.cpu1.itb.read_misses 0 # DTB read misses 2148system.cpu1.itb.write_hits 0 # DTB write hits 2149system.cpu1.itb.write_misses 0 # DTB write misses 2150system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 2151system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2152system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2153system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 2135system.cpu1.itb.read_hits 0 # DTB read hits 2136system.cpu1.itb.read_misses 0 # DTB read misses 2137system.cpu1.itb.write_hits 0 # DTB write hits 2138system.cpu1.itb.write_misses 0 # DTB write misses 2139system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 2140system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2141system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2142system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 2154system.cpu1.itb.flush_entries 1355 # Number of entries that have been flushed from TLB | 2143system.cpu1.itb.flush_entries 1359 # Number of entries that have been flushed from TLB |
| 2155system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2156system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2157system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 2144system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2145system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2146system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 2158system.cpu1.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions | 2147system.cpu1.itb.perms_faults 1471 # Number of TLB faults due to permissions restrictions |
| 2159system.cpu1.itb.read_accesses 0 # DTB read accesses 2160system.cpu1.itb.write_accesses 0 # DTB write accesses | 2148system.cpu1.itb.read_accesses 0 # DTB read accesses 2149system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 2161system.cpu1.itb.inst_accesses 7723986 # ITB inst accesses 2162system.cpu1.itb.hits 7718441 # DTB hits 2163system.cpu1.itb.misses 5545 # DTB misses 2164system.cpu1.itb.accesses 7723986 # DTB accesses 2165system.cpu1.numCycles 413843853 # number of cpu cycles simulated | 2150system.cpu1.itb.inst_accesses 7728752 # ITB inst accesses 2151system.cpu1.itb.hits 7723190 # DTB hits 2152system.cpu1.itb.misses 5562 # DTB misses 2153system.cpu1.itb.accesses 7728752 # DTB accesses 2154system.cpu1.numCycles 413796923 # number of cpu cycles simulated |
| 2166system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2167system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 2155system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2156system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2168system.cpu1.fetch.icacheStallCycles 19379988 # Number of cycles fetch is stalled on an Icache miss 2169system.cpu1.fetch.Insts 61315433 # Number of instructions fetch has processed 2170system.cpu1.fetch.Branches 9295999 # Number of branches that fetch encountered 2171system.cpu1.fetch.predictedBranches 5848169 # Number of branches that fetch has predicted taken 2172system.cpu1.fetch.Cycles 13365504 # Number of cycles fetch has run and was not squashing or blocked 2173system.cpu1.fetch.SquashCycles 3344948 # Number of cycles fetch has spent squashing 2174system.cpu1.fetch.TlbCycles 69502 # Number of cycles fetch has spent waiting for tlb 2175system.cpu1.fetch.BlockedCycles 81000911 # Number of cycles fetch has spent blocked 2176system.cpu1.fetch.MiscStallCycles 5955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2177system.cpu1.fetch.PendingTrapStallCycles 40728 # Number of stall cycles due to pending traps 2178system.cpu1.fetch.PendingQuiesceStallCycles 1501346 # Number of stall cycles due to pending quiesce instructions 2179system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR 2180system.cpu1.fetch.CacheLines 7716683 # Number of cache lines fetched 2181system.cpu1.fetch.IcacheSquashes 552961 # Number of outstanding Icache misses that were squashed 2182system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed 2183system.cpu1.fetch.rateDist::samples 117651923 # Number of instructions fetched each cycle (Total) 2184system.cpu1.fetch.rateDist::mean 0.637947 # Number of instructions fetched each cycle (Total) 2185system.cpu1.fetch.rateDist::stdev 1.959423 # Number of instructions fetched each cycle (Total) | 2157system.cpu1.fetch.icacheStallCycles 19367440 # Number of cycles fetch is stalled on an Icache miss 2158system.cpu1.fetch.Insts 61322975 # Number of instructions fetch has processed 2159system.cpu1.fetch.Branches 9293568 # Number of branches that fetch encountered 2160system.cpu1.fetch.predictedBranches 5849683 # Number of branches that fetch has predicted taken 2161system.cpu1.fetch.Cycles 13369526 # Number of cycles fetch has run and was not squashing or blocked 2162system.cpu1.fetch.SquashCycles 3346649 # Number of cycles fetch has spent squashing 2163system.cpu1.fetch.TlbCycles 69265 # Number of cycles fetch has spent waiting for tlb 2164system.cpu1.fetch.BlockedCycles 80967245 # Number of cycles fetch has spent blocked 2165system.cpu1.fetch.MiscStallCycles 6008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2166system.cpu1.fetch.PendingTrapStallCycles 41697 # Number of stall cycles due to pending traps 2167system.cpu1.fetch.PendingQuiesceStallCycles 1506074 # Number of stall cycles due to pending quiesce instructions 2168system.cpu1.fetch.IcacheWaitRetryStallCycles 288 # Number of stall cycles due to full MSHR 2169system.cpu1.fetch.CacheLines 7721399 # Number of cache lines fetched 2170system.cpu1.fetch.IcacheSquashes 552563 # Number of outstanding Icache misses that were squashed 2171system.cpu1.fetch.ItlbSquashes 2913 # Number of outstanding ITLB misses that were squashed 2172system.cpu1.fetch.rateDist::samples 117616541 # Number of instructions fetched each cycle (Total) 2173system.cpu1.fetch.rateDist::mean 0.638291 # Number of instructions fetched each cycle (Total) 2174system.cpu1.fetch.rateDist::stdev 1.959867 # Number of instructions fetched each cycle (Total) |
| 2186system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 2175system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 2187system.cpu1.fetch.rateDist::0 104293797 88.65% 88.65% # Number of instructions fetched each cycle (Total) 2188system.cpu1.fetch.rateDist::1 816533 0.69% 89.34% # Number of instructions fetched each cycle (Total) 2189system.cpu1.fetch.rateDist::2 959642 0.82% 90.16% # Number of instructions fetched each cycle (Total) 2190system.cpu1.fetch.rateDist::3 1712278 1.46% 91.61% # Number of instructions fetched each cycle (Total) 2191system.cpu1.fetch.rateDist::4 1420540 1.21% 92.82% # Number of instructions fetched each cycle (Total) 2192system.cpu1.fetch.rateDist::5 586826 0.50% 93.32% # Number of instructions fetched each cycle (Total) 2193system.cpu1.fetch.rateDist::6 1954913 1.66% 94.98% # Number of instructions fetched each cycle (Total) 2194system.cpu1.fetch.rateDist::7 421869 0.36% 95.34% # Number of instructions fetched each cycle (Total) 2195system.cpu1.fetch.rateDist::8 5485525 4.66% 100.00% # Number of instructions fetched each cycle (Total) | 2176system.cpu1.fetch.rateDist::0 104254528 88.64% 88.64% # Number of instructions fetched each cycle (Total) 2177system.cpu1.fetch.rateDist::1 816257 0.69% 89.33% # Number of instructions fetched each cycle (Total) 2178system.cpu1.fetch.rateDist::2 960958 0.82% 90.15% # Number of instructions fetched each cycle (Total) 2179system.cpu1.fetch.rateDist::3 1713992 1.46% 91.61% # Number of instructions fetched each cycle (Total) 2180system.cpu1.fetch.rateDist::4 1419991 1.21% 92.81% # Number of instructions fetched each cycle (Total) 2181system.cpu1.fetch.rateDist::5 586388 0.50% 93.31% # Number of instructions fetched each cycle (Total) 2182system.cpu1.fetch.rateDist::6 1955965 1.66% 94.98% # Number of instructions fetched each cycle (Total) 2183system.cpu1.fetch.rateDist::7 421912 0.36% 95.34% # Number of instructions fetched each cycle (Total) 2184system.cpu1.fetch.rateDist::8 5486550 4.66% 100.00% # Number of instructions fetched each cycle (Total) |
| 2196system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2197system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2198system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 2185system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2186system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2187system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 2199system.cpu1.fetch.rateDist::total 117651923 # Number of instructions fetched each cycle (Total) 2200system.cpu1.fetch.branchRate 0.022463 # Number of branch fetches per cycle 2201system.cpu1.fetch.rate 0.148161 # Number of inst fetches per cycle 2202system.cpu1.decode.IdleCycles 20970716 # Number of cycles decode is idle 2203system.cpu1.decode.BlockedCycles 81766548 # Number of cycles decode is blocked 2204system.cpu1.decode.RunCycles 11917801 # Number of cycles decode is running 2205system.cpu1.decode.UnblockCycles 808551 # Number of cycles decode is unblocking 2206system.cpu1.decode.SquashCycles 2188307 # Number of cycles decode is squashing 2207system.cpu1.decode.BranchResolved 1138241 # Number of times decode resolved a branch 2208system.cpu1.decode.BranchMispred 101191 # Number of times decode detected a branch misprediction 2209system.cpu1.decode.DecodedInsts 71099803 # Number of instructions handled by decode 2210system.cpu1.decode.SquashedInsts 336135 # Number of squashed instructions handled by decode 2211system.cpu1.rename.SquashCycles 2188307 # Number of cycles rename is squashing 2212system.cpu1.rename.IdleCycles 22164827 # Number of cycles rename is idle 2213system.cpu1.rename.BlockCycles 33899952 # Number of cycles rename is blocking 2214system.cpu1.rename.serializeStallCycles 43340583 # count of cycles rename stalled for serializing inst 2215system.cpu1.rename.RunCycles 11475244 # Number of cycles rename is running 2216system.cpu1.rename.UnblockCycles 4583010 # Number of cycles rename is unblocking 2217system.cpu1.rename.RenamedInsts 67141114 # Number of instructions processed by rename 2218system.cpu1.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full 2219system.cpu1.rename.IQFullEvents 681863 # Number of times rename has blocked due to IQ full 2220system.cpu1.rename.LSQFullEvents 3070840 # Number of times rename has blocked due to LSQ full 2221system.cpu1.rename.FullRegisterEvents 445 # Number of times there has been no free registers 2222system.cpu1.rename.RenamedOperands 70764915 # Number of destination operands rename has renamed 2223system.cpu1.rename.RenameLookups 313106059 # Number of register rename lookups that rename has made 2224system.cpu1.rename.int_rename_lookups 286755701 # Number of integer rename lookups 2225system.cpu1.rename.fp_rename_lookups 6517 # Number of floating rename lookups 2226system.cpu1.rename.CommittedMaps 50418755 # Number of HB maps that are committed 2227system.cpu1.rename.UndoneMaps 20346160 # Number of HB maps that are undone due to squashing 2228system.cpu1.rename.serializingInsts 765693 # count of serializing insts renamed 2229system.cpu1.rename.tempSerializingInsts 705478 # count of temporary serializing insts renamed 2230system.cpu1.rename.skidInsts 8425217 # count of insts added to the skid buffer 2231system.cpu1.memDep0.insertedLoads 12844634 # Number of loads inserted to the mem dependence unit. 2232system.cpu1.memDep0.insertedStores 8117566 # Number of stores inserted to the mem dependence unit. 2233system.cpu1.memDep0.conflictingLoads 1057819 # Number of conflicting loads. 2234system.cpu1.memDep0.conflictingStores 1511606 # Number of conflicting stores. 2235system.cpu1.iq.iqInstsAdded 61861483 # Number of instructions added to the IQ (excludes non-spec) 2236system.cpu1.iq.iqNonSpecInstsAdded 1182497 # Number of non-speculative instructions added to the IQ 2237system.cpu1.iq.iqInstsIssued 88912346 # Number of instructions issued 2238system.cpu1.iq.iqSquashedInstsIssued 94590 # Number of squashed instructions issued 2239system.cpu1.iq.iqSquashedInstsExamined 13560397 # Number of squashed instructions iterated over during squash; mainly for profiling 2240system.cpu1.iq.iqSquashedOperandsExamined 36234299 # Number of squashed operands that are examined and possibly removed from graph 2241system.cpu1.iq.iqSquashedNonSpecRemoved 282991 # Number of squashed non-spec instructions that were removed 2242system.cpu1.iq.issued_per_cycle::samples 117651923 # Number of insts issued each cycle 2243system.cpu1.iq.issued_per_cycle::mean 0.755724 # Number of insts issued each cycle 2244system.cpu1.iq.issued_per_cycle::stdev 1.498826 # Number of insts issued each cycle | 2188system.cpu1.fetch.rateDist::total 117616541 # Number of instructions fetched each cycle (Total) 2189system.cpu1.fetch.branchRate 0.022459 # Number of branch fetches per cycle 2190system.cpu1.fetch.rate 0.148196 # Number of inst fetches per cycle 2191system.cpu1.decode.IdleCycles 20958094 # Number of cycles decode is idle 2192system.cpu1.decode.BlockedCycles 81738883 # Number of cycles decode is blocked 2193system.cpu1.decode.RunCycles 11922126 # Number of cycles decode is running 2194system.cpu1.decode.UnblockCycles 807725 # Number of cycles decode is unblocking 2195system.cpu1.decode.SquashCycles 2189713 # Number of cycles decode is squashing 2196system.cpu1.decode.BranchResolved 1139186 # Number of times decode resolved a branch 2197system.cpu1.decode.BranchMispred 101010 # Number of times decode detected a branch misprediction 2198system.cpu1.decode.DecodedInsts 71114524 # Number of instructions handled by decode 2199system.cpu1.decode.SquashedInsts 335626 # Number of squashed instructions handled by decode 2200system.cpu1.rename.SquashCycles 2189713 # Number of cycles rename is squashing 2201system.cpu1.rename.IdleCycles 22150930 # Number of cycles rename is idle 2202system.cpu1.rename.BlockCycles 33873368 # Number of cycles rename is blocking 2203system.cpu1.rename.serializeStallCycles 43341870 # count of cycles rename stalled for serializing inst 2204system.cpu1.rename.RunCycles 11481154 # Number of cycles rename is running 2205system.cpu1.rename.UnblockCycles 4579506 # Number of cycles rename is unblocking 2206system.cpu1.rename.RenamedInsts 67156903 # Number of instructions processed by rename 2207system.cpu1.rename.ROBFullEvents 160 # Number of times rename has blocked due to ROB full 2208system.cpu1.rename.IQFullEvents 681335 # Number of times rename has blocked due to IQ full 2209system.cpu1.rename.LSQFullEvents 3069410 # Number of times rename has blocked due to LSQ full 2210system.cpu1.rename.FullRegisterEvents 515 # Number of times there has been no free registers 2211system.cpu1.rename.RenamedOperands 70770910 # Number of destination operands rename has renamed 2212system.cpu1.rename.RenameLookups 313189992 # Number of register rename lookups that rename has made 2213system.cpu1.rename.int_rename_lookups 286825978 # Number of integer rename lookups 2214system.cpu1.rename.fp_rename_lookups 6578 # Number of floating rename lookups 2215system.cpu1.rename.CommittedMaps 50413534 # Number of HB maps that are committed 2216system.cpu1.rename.UndoneMaps 20357376 # Number of HB maps that are undone due to squashing 2217system.cpu1.rename.serializingInsts 766049 # count of serializing insts renamed 2218system.cpu1.rename.tempSerializingInsts 705865 # count of temporary serializing insts renamed 2219system.cpu1.rename.skidInsts 8415941 # count of insts added to the skid buffer 2220system.cpu1.memDep0.insertedLoads 12847707 # Number of loads inserted to the mem dependence unit. 2221system.cpu1.memDep0.insertedStores 8121662 # Number of stores inserted to the mem dependence unit. 2222system.cpu1.memDep0.conflictingLoads 1063533 # Number of conflicting loads. 2223system.cpu1.memDep0.conflictingStores 1519311 # Number of conflicting stores. 2224system.cpu1.iq.iqInstsAdded 61868936 # Number of instructions added to the IQ (excludes non-spec) 2225system.cpu1.iq.iqNonSpecInstsAdded 1182413 # Number of non-speculative instructions added to the IQ 2226system.cpu1.iq.iqInstsIssued 88920941 # Number of instructions issued 2227system.cpu1.iq.iqSquashedInstsIssued 95302 # Number of squashed instructions issued 2228system.cpu1.iq.iqSquashedInstsExamined 13575964 # Number of squashed instructions iterated over during squash; mainly for profiling 2229system.cpu1.iq.iqSquashedOperandsExamined 36252507 # Number of squashed operands that are examined and possibly removed from graph 2230system.cpu1.iq.iqSquashedNonSpecRemoved 283075 # Number of squashed non-spec instructions that were removed 2231system.cpu1.iq.issued_per_cycle::samples 117616541 # Number of insts issued each cycle 2232system.cpu1.iq.issued_per_cycle::mean 0.756024 # Number of insts issued each cycle 2233system.cpu1.iq.issued_per_cycle::stdev 1.499146 # Number of insts issued each cycle |
| 2245system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 2234system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 2246system.cpu1.iq.issued_per_cycle::0 86792358 73.77% 73.77% # Number of insts issued each cycle 2247system.cpu1.iq.issued_per_cycle::1 9289300 7.90% 81.67% # Number of insts issued each cycle 2248system.cpu1.iq.issued_per_cycle::2 4170595 3.54% 85.21% # Number of insts issued each cycle 2249system.cpu1.iq.issued_per_cycle::3 3605495 3.06% 88.28% # Number of insts issued each cycle 2250system.cpu1.iq.issued_per_cycle::4 10372617 8.82% 97.09% # Number of insts issued each cycle 2251system.cpu1.iq.issued_per_cycle::5 1993778 1.69% 98.79% # Number of insts issued each cycle 2252system.cpu1.iq.issued_per_cycle::6 1066938 0.91% 99.69% # Number of insts issued each cycle 2253system.cpu1.iq.issued_per_cycle::7 282351 0.24% 99.93% # Number of insts issued each cycle 2254system.cpu1.iq.issued_per_cycle::8 78491 0.07% 100.00% # Number of insts issued each cycle | 2235system.cpu1.iq.issued_per_cycle::0 86757290 73.76% 73.76% # Number of insts issued each cycle 2236system.cpu1.iq.issued_per_cycle::1 9288969 7.90% 81.66% # Number of insts issued each cycle 2237system.cpu1.iq.issued_per_cycle::2 4169197 3.54% 85.21% # Number of insts issued each cycle 2238system.cpu1.iq.issued_per_cycle::3 3602778 3.06% 88.27% # Number of insts issued each cycle 2239system.cpu1.iq.issued_per_cycle::4 10372979 8.82% 97.09% # Number of insts issued each cycle 2240system.cpu1.iq.issued_per_cycle::5 1998574 1.70% 98.79% # Number of insts issued each cycle 2241system.cpu1.iq.issued_per_cycle::6 1065464 0.91% 99.69% # Number of insts issued each cycle 2242system.cpu1.iq.issued_per_cycle::7 282646 0.24% 99.93% # Number of insts issued each cycle 2243system.cpu1.iq.issued_per_cycle::8 78644 0.07% 100.00% # Number of insts issued each cycle |
| 2255system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2256system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2257system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 2244system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2245system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2246system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 2258system.cpu1.iq.issued_per_cycle::total 117651923 # Number of insts issued each cycle | 2247system.cpu1.iq.issued_per_cycle::total 117616541 # Number of insts issued each cycle |
| 2259system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 2248system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 2260system.cpu1.iq.fu_full::IntAlu 32498 0.41% 0.41% # attempts to use FU when none available 2261system.cpu1.iq.fu_full::IntMult 992 0.01% 0.42% # attempts to use FU when none available | 2249system.cpu1.iq.fu_full::IntAlu 32554 0.41% 0.41% # attempts to use FU when none available 2250system.cpu1.iq.fu_full::IntMult 991 0.01% 0.42% # attempts to use FU when none available |
| 2262system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 2263system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 2264system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2265system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2266system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 2267system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2268system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 2269system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 2281system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 2282system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2283system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2284system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2285system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 2286system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 2287system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 2288system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available | 2251system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 2252system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 2253system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2254system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2255system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 2256system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2257system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 2258system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 2270system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 2271system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 2272system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 2273system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 2274system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 2275system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 2276system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 2277system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available |
| 2289system.cpu1.iq.fu_full::MemRead 7572169 95.70% 96.13% # attempts to use FU when none available 2290system.cpu1.iq.fu_full::MemWrite 306556 3.87% 100.00% # attempts to use FU when none available | 2278system.cpu1.iq.fu_full::MemRead 7574498 95.71% 96.13% # attempts to use FU when none available 2279system.cpu1.iq.fu_full::MemWrite 306293 3.87% 100.00% # attempts to use FU when none available |
| 2291system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2292system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 2280system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2281system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 2293system.cpu1.iq.FU_type_0::No_OpClass 14270 0.02% 0.02% # Type of FU issued 2294system.cpu1.iq.FU_type_0::IntAlu 37625981 42.32% 42.33% # Type of FU issued 2295system.cpu1.iq.FU_type_0::IntMult 61252 0.07% 42.40% # Type of FU issued | 2282system.cpu1.iq.FU_type_0::No_OpClass 14269 0.02% 0.02% # Type of FU issued 2283system.cpu1.iq.FU_type_0::IntAlu 37628828 42.32% 42.33% # Type of FU issued 2284system.cpu1.iq.FU_type_0::IntMult 61233 0.07% 42.40% # Type of FU issued |
| 2296system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued 2297system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued 2298system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued 2299system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued 2300system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued 2301system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued 2302system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued 2303system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued 2304system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued 2305system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued 2306system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued 2307system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued | 2285system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued 2286system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued 2287system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued 2288system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued 2289system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued 2290system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued 2291system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued 2292system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued 2293system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued 2294system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued 2295system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued 2296system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued |
| 2308system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.40% # Type of FU issued | 2297system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.40% # Type of FU issued |
| 2309system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued 2310system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued 2311system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued | 2298system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued 2299system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued 2300system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued |
| 2312system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.40% # Type of FU issued | 2301system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued |
| 2313system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued 2314system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued 2315system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued 2316system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued 2317system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued 2318system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued 2319system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.40% # Type of FU issued 2320system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued | 2302system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued 2303system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued 2304system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued 2305system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued 2306system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued 2307system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued 2308system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.40% # Type of FU issued 2309system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued |
| 2321system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.40% # Type of FU issued | 2310system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.40% # Type of FU issued |
| 2322system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued | 2311system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued |
| 2323system.cpu1.iq.FU_type_0::MemRead 43860086 49.33% 91.73% # Type of FU issued 2324system.cpu1.iq.FU_type_0::MemWrite 7349035 8.27% 100.00% # Type of FU issued | 2312system.cpu1.iq.FU_type_0::MemRead 43862772 49.33% 91.73% # Type of FU issued 2313system.cpu1.iq.FU_type_0::MemWrite 7352107 8.27% 100.00% # Type of FU issued |
| 2325system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2326system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2314system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2315system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2327system.cpu1.iq.FU_type_0::total 88912346 # Type of FU issued 2328system.cpu1.iq.rate 0.214845 # Inst issue rate 2329system.cpu1.iq.fu_busy_cnt 7912215 # FU busy when requested 2330system.cpu1.iq.fu_busy_rate 0.088989 # FU busy rate (busy events/executed inst) 2331system.cpu1.iq.int_inst_queue_reads 303516932 # Number of integer instruction queue reads 2332system.cpu1.iq.int_inst_queue_writes 76613298 # Number of integer instruction queue writes 2333system.cpu1.iq.int_inst_queue_wakeup_accesses 54268341 # Number of integer instruction queue wakeup accesses 2334system.cpu1.iq.fp_inst_queue_reads 15366 # Number of floating instruction queue reads 2335system.cpu1.iq.fp_inst_queue_writes 8022 # Number of floating instruction queue writes 2336system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses 2337system.cpu1.iq.int_alu_accesses 96802135 # Number of integer alu accesses 2338system.cpu1.iq.fp_alu_accesses 8156 # Number of floating point alu accesses 2339system.cpu1.iew.lsq.thread0.forwLoads 354682 # Number of loads that had data forwarded from stores | 2316system.cpu1.iq.FU_type_0::total 88920941 # Type of FU issued 2317system.cpu1.iq.rate 0.214890 # Inst issue rate 2318system.cpu1.iq.fu_busy_cnt 7914336 # FU busy when requested 2319system.cpu1.iq.fu_busy_rate 0.089004 # FU busy rate (busy events/executed inst) 2320system.cpu1.iq.int_inst_queue_reads 303501191 # Number of integer instruction queue reads 2321system.cpu1.iq.int_inst_queue_writes 76636250 # Number of integer instruction queue writes 2322system.cpu1.iq.int_inst_queue_wakeup_accesses 54272980 # Number of integer instruction queue wakeup accesses 2323system.cpu1.iq.fp_inst_queue_reads 15357 # Number of floating instruction queue reads 2324system.cpu1.iq.fp_inst_queue_writes 8072 # Number of floating instruction queue writes 2325system.cpu1.iq.fp_inst_queue_wakeup_accesses 6822 # Number of floating instruction queue wakeup accesses 2326system.cpu1.iq.int_alu_accesses 96812856 # Number of integer alu accesses 2327system.cpu1.iq.fp_alu_accesses 8152 # Number of floating point alu accesses 2328system.cpu1.iew.lsq.thread0.forwLoads 352971 # Number of loads that had data forwarded from stores |
| 2340system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2329system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2341system.cpu1.iew.lsq.thread0.squashedLoads 2862502 # Number of loads squashed 2342system.cpu1.iew.lsq.thread0.ignoredResponses 4198 # Number of memory responses ignored because the instruction is squashed 2343system.cpu1.iew.lsq.thread0.memOrderViolation 17495 # Number of memory ordering violations 2344system.cpu1.iew.lsq.thread0.squashedStores 1113245 # Number of stores squashed | 2330system.cpu1.iew.lsq.thread0.squashedLoads 2867339 # Number of loads squashed 2331system.cpu1.iew.lsq.thread0.ignoredResponses 4206 # Number of memory responses ignored because the instruction is squashed 2332system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations 2333system.cpu1.iew.lsq.thread0.squashedStores 1118674 # Number of stores squashed |
| 2345system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2346system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2334system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2335system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2347system.cpu1.iew.lsq.thread0.rescheduledLoads 31965664 # Number of loads that were rescheduled 2348system.cpu1.iew.lsq.thread0.cacheBlocked 675731 # Number of times an access to memory failed due to the cache being blocked | 2336system.cpu1.iew.lsq.thread0.rescheduledLoads 31965666 # Number of loads that were rescheduled 2337system.cpu1.iew.lsq.thread0.cacheBlocked 675765 # Number of times an access to memory failed due to the cache being blocked |
| 2349system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2338system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2350system.cpu1.iew.iewSquashCycles 2188307 # Number of cycles IEW is squashing 2351system.cpu1.iew.iewBlockCycles 26389520 # Number of cycles IEW is blocking 2352system.cpu1.iew.iewUnblockCycles 363046 # Number of cycles IEW is unblocking 2353system.cpu1.iew.iewDispatchedInsts 63147070 # Number of instructions dispatched to IQ 2354system.cpu1.iew.iewDispSquashedInsts 115346 # Number of squashed instructions skipped by dispatch 2355system.cpu1.iew.iewDispLoadInsts 12844634 # Number of dispatched load instructions 2356system.cpu1.iew.iewDispStoreInsts 8117566 # Number of dispatched store instructions 2357system.cpu1.iew.iewDispNonSpecInsts 886491 # Number of dispatched non-speculative instructions 2358system.cpu1.iew.iewIQFullEvents 65999 # Number of times the IQ has become full, causing a stall 2359system.cpu1.iew.iewLSQFullEvents 3974 # Number of times the LSQ has become full, causing a stall 2360system.cpu1.iew.memOrderViolationEvents 17495 # Number of memory order violations 2361system.cpu1.iew.predictedTakenIncorrect 203953 # Number of branches that were predicted taken incorrectly 2362system.cpu1.iew.predictedNotTakenIncorrect 158404 # Number of branches that were predicted not taken incorrectly 2363system.cpu1.iew.branchMispredicts 362357 # Number of branch mispredicts detected at execute 2364system.cpu1.iew.iewExecutedInsts 87176512 # Number of executed instructions 2365system.cpu1.iew.iewExecLoadInsts 43353711 # Number of load instructions executed 2366system.cpu1.iew.iewExecSquashedInsts 1735834 # Number of squashed instructions skipped in execute | 2339system.cpu1.iew.iewSquashCycles 2189713 # Number of cycles IEW is squashing 2340system.cpu1.iew.iewBlockCycles 26359334 # Number of cycles IEW is blocking 2341system.cpu1.iew.iewUnblockCycles 362918 # Number of cycles IEW is unblocking 2342system.cpu1.iew.iewDispatchedInsts 63155083 # Number of instructions dispatched to IQ 2343system.cpu1.iew.iewDispSquashedInsts 115853 # Number of squashed instructions skipped by dispatch 2344system.cpu1.iew.iewDispLoadInsts 12847707 # Number of dispatched load instructions 2345system.cpu1.iew.iewDispStoreInsts 8121662 # Number of dispatched store instructions 2346system.cpu1.iew.iewDispNonSpecInsts 886435 # Number of dispatched non-speculative instructions 2347system.cpu1.iew.iewIQFullEvents 65883 # Number of times the IQ has become full, causing a stall 2348system.cpu1.iew.iewLSQFullEvents 4133 # Number of times the LSQ has become full, causing a stall 2349system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations 2350system.cpu1.iew.predictedTakenIncorrect 204959 # Number of branches that were predicted taken incorrectly 2351system.cpu1.iew.predictedNotTakenIncorrect 158107 # Number of branches that were predicted not taken incorrectly 2352system.cpu1.iew.branchMispredicts 363066 # Number of branch mispredicts detected at execute 2353system.cpu1.iew.iewExecutedInsts 87182630 # Number of executed instructions 2354system.cpu1.iew.iewExecLoadInsts 43355393 # Number of load instructions executed 2355system.cpu1.iew.iewExecSquashedInsts 1738311 # Number of squashed instructions skipped in execute |
| 2367system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2356system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2368system.cpu1.iew.exec_nop 103090 # number of nop insts executed 2369system.cpu1.iew.exec_refs 50638153 # number of memory reference insts executed 2370system.cpu1.iew.exec_branches 7380246 # Number of branches executed 2371system.cpu1.iew.exec_stores 7284442 # Number of stores executed 2372system.cpu1.iew.exec_rate 0.210651 # Inst execution rate 2373system.cpu1.iew.wb_sent 86413088 # cumulative count of insts sent to commit 2374system.cpu1.iew.wb_count 54275144 # cumulative count of insts written-back 2375system.cpu1.iew.wb_producers 30296614 # num instructions producing a value 2376system.cpu1.iew.wb_consumers 53882453 # num instructions consuming a value | 2357system.cpu1.iew.exec_nop 103734 # number of nop insts executed 2358system.cpu1.iew.exec_refs 50641864 # number of memory reference insts executed 2359system.cpu1.iew.exec_branches 7379983 # Number of branches executed 2360system.cpu1.iew.exec_stores 7286471 # Number of stores executed 2361system.cpu1.iew.exec_rate 0.210689 # Inst execution rate 2362system.cpu1.iew.wb_sent 86418752 # cumulative count of insts sent to commit 2363system.cpu1.iew.wb_count 54279802 # cumulative count of insts written-back 2364system.cpu1.iew.wb_producers 30301489 # num instructions producing a value 2365system.cpu1.iew.wb_consumers 53896999 # num instructions consuming a value |
| 2377system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2366system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2378system.cpu1.iew.wb_rate 0.131149 # insts written-back per cycle 2379system.cpu1.iew.wb_fanout 0.562272 # average fanout of values written-back | 2367system.cpu1.iew.wb_rate 0.131175 # insts written-back per cycle 2368system.cpu1.iew.wb_fanout 0.562211 # average fanout of values written-back |
| 2380system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2369system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2381system.cpu1.commit.commitSquashedInsts 13436842 # The number of squashed insts skipped by commit 2382system.cpu1.commit.commitNonSpecStalls 899506 # The number of times commit has been forced to stall to communicate backwards 2383system.cpu1.commit.branchMispredicts 316660 # The number of times a branch was mispredicted 2384system.cpu1.commit.committed_per_cycle::samples 115463616 # Number of insts commited each cycle 2385system.cpu1.commit.committed_per_cycle::mean 0.426258 # Number of insts commited each cycle 2386system.cpu1.commit.committed_per_cycle::stdev 1.378914 # Number of insts commited each cycle | 2370system.cpu1.commit.commitSquashedInsts 13446942 # The number of squashed insts skipped by commit 2371system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards 2372system.cpu1.commit.branchMispredicts 317124 # The number of times a branch was mispredicted 2373system.cpu1.commit.committed_per_cycle::samples 115426828 # Number of insts commited each cycle 2374system.cpu1.commit.committed_per_cycle::mean 0.426339 # Number of insts commited each cycle 2375system.cpu1.commit.committed_per_cycle::stdev 1.379011 # Number of insts commited each cycle |
| 2387system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2376system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2388system.cpu1.commit.committed_per_cycle::0 97442898 84.39% 84.39% # Number of insts commited each cycle 2389system.cpu1.commit.committed_per_cycle::1 9592965 8.31% 92.70% # Number of insts commited each cycle 2390system.cpu1.commit.committed_per_cycle::2 2168696 1.88% 94.58% # Number of insts commited each cycle 2391system.cpu1.commit.committed_per_cycle::3 1301481 1.13% 95.71% # Number of insts commited each cycle 2392system.cpu1.commit.committed_per_cycle::4 990246 0.86% 96.56% # Number of insts commited each cycle 2393system.cpu1.commit.committed_per_cycle::5 587576 0.51% 97.07% # Number of insts commited each cycle 2394system.cpu1.commit.committed_per_cycle::6 1009945 0.87% 97.95% # Number of insts commited each cycle 2395system.cpu1.commit.committed_per_cycle::7 534541 0.46% 98.41% # Number of insts commited each cycle 2396system.cpu1.commit.committed_per_cycle::8 1835268 1.59% 100.00% # Number of insts commited each cycle | 2377system.cpu1.commit.committed_per_cycle::0 97406330 84.39% 84.39% # Number of insts commited each cycle 2378system.cpu1.commit.committed_per_cycle::1 9593486 8.31% 92.70% # Number of insts commited each cycle 2379system.cpu1.commit.committed_per_cycle::2 2169699 1.88% 94.58% # Number of insts commited each cycle 2380system.cpu1.commit.committed_per_cycle::3 1301842 1.13% 95.71% # Number of insts commited each cycle 2381system.cpu1.commit.committed_per_cycle::4 990133 0.86% 96.56% # Number of insts commited each cycle 2382system.cpu1.commit.committed_per_cycle::5 584983 0.51% 97.07% # Number of insts commited each cycle 2383system.cpu1.commit.committed_per_cycle::6 1011097 0.88% 97.95% # Number of insts commited each cycle 2384system.cpu1.commit.committed_per_cycle::7 533551 0.46% 98.41% # Number of insts commited each cycle 2385system.cpu1.commit.committed_per_cycle::8 1835707 1.59% 100.00% # Number of insts commited each cycle |
| 2397system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2398system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2399system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2386system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2387system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2388system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2400system.cpu1.commit.committed_per_cycle::total 115463616 # Number of insts commited each cycle 2401system.cpu1.commit.committedInsts 38874177 # Number of instructions committed 2402system.cpu1.commit.committedOps 49217265 # Number of ops (including micro ops) committed | 2389system.cpu1.commit.committed_per_cycle::total 115426828 # Number of insts commited each cycle 2390system.cpu1.commit.committedInsts 38871006 # Number of instructions committed 2391system.cpu1.commit.committedOps 49210952 # Number of ops (including micro ops) committed |
| 2403system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2392system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2404system.cpu1.commit.refs 16986453 # Number of memory references committed 2405system.cpu1.commit.loads 9982132 # Number of loads committed 2406system.cpu1.commit.membars 195521 # Number of memory barriers committed 2407system.cpu1.commit.branches 6425226 # Number of branches committed | 2393system.cpu1.commit.refs 16983356 # Number of memory references committed 2394system.cpu1.commit.loads 9980368 # Number of loads committed 2395system.cpu1.commit.membars 195496 # Number of memory barriers committed 2396system.cpu1.commit.branches 6424614 # Number of branches committed |
| 2408system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. | 2397system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. |
| 2409system.cpu1.commit.int_insts 43929395 # Number of committed integer instructions. 2410system.cpu1.commit.function_calls 553319 # Number of function calls committed. 2411system.cpu1.commit.bw_lim_events 1835268 # number cycles where commit BW limit reached | 2398system.cpu1.commit.int_insts 43923604 # Number of committed integer instructions. 2399system.cpu1.commit.function_calls 553281 # Number of function calls committed. 2400system.cpu1.commit.bw_lim_events 1835707 # number cycles where commit BW limit reached |
| 2412system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 2401system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2413system.cpu1.rob.rob_reads 175215898 # The number of ROB reads 2414system.cpu1.rob.rob_writes 127579322 # The number of ROB writes 2415system.cpu1.timesIdled 1429072 # Number of times that the entire CPU went into an idle state and unscheduled itself 2416system.cpu1.idleCycles 296191930 # Total number of cycles that the CPU has spent unscheduled due to idling 2417system.cpu1.quiesceCycles 4796799037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2418system.cpu1.committedInsts 38804538 # Number of Instructions Simulated 2419system.cpu1.committedOps 49147626 # Number of Ops (including micro ops) Simulated 2420system.cpu1.committedInsts_total 38804538 # Number of Instructions Simulated 2421system.cpu1.cpi 10.664831 # CPI: Cycles Per Instruction 2422system.cpu1.cpi_total 10.664831 # CPI: Total CPI of All Threads 2423system.cpu1.ipc 0.093766 # IPC: Instructions Per Cycle 2424system.cpu1.ipc_total 0.093766 # IPC: Total IPC of All Threads 2425system.cpu1.int_regfile_reads 391691607 # number of integer regfile reads 2426system.cpu1.int_regfile_writes 56383706 # number of integer regfile writes 2427system.cpu1.fp_regfile_reads 5043 # number of floating regfile reads 2428system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes 2429system.cpu1.misc_regfile_reads 202850334 # number of misc regfile reads 2430system.cpu1.misc_regfile_writes 723182 # number of misc regfile writes 2431system.cpu1.icache.tags.replacements 614906 # number of replacements 2432system.cpu1.icache.tags.tagsinuse 498.718219 # Cycle average of tags in use 2433system.cpu1.icache.tags.total_refs 7054617 # Total number of references to valid blocks. 2434system.cpu1.icache.tags.sampled_refs 615418 # Sample count of references to valid blocks. 2435system.cpu1.icache.tags.avg_refs 11.463131 # Average number of references to valid blocks. 2436system.cpu1.icache.tags.warmup_cycle 74929846000 # Cycle when the warmup percentage was hit. 2437system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.718219 # Average occupied blocks per requestor 2438system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974059 # Average percentage of cache occupancy 2439system.cpu1.icache.tags.occ_percent::total 0.974059 # Average percentage of cache occupancy | 2402system.cpu1.rob.rob_reads 175182622 # The number of ROB reads 2403system.cpu1.rob.rob_writes 127588630 # The number of ROB writes 2404system.cpu1.timesIdled 1428402 # Number of times that the entire CPU went into an idle state and unscheduled itself 2405system.cpu1.idleCycles 296180382 # Total number of cycles that the CPU has spent unscheduled due to idling 2406system.cpu1.quiesceCycles 4796803337 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2407system.cpu1.committedInsts 38801367 # Number of Instructions Simulated 2408system.cpu1.committedOps 49141313 # Number of Ops (including micro ops) Simulated 2409system.cpu1.committedInsts_total 38801367 # Number of Instructions Simulated 2410system.cpu1.cpi 10.664493 # CPI: Cycles Per Instruction 2411system.cpu1.cpi_total 10.664493 # CPI: Total CPI of All Threads 2412system.cpu1.ipc 0.093769 # IPC: Instructions Per Cycle 2413system.cpu1.ipc_total 0.093769 # IPC: Total IPC of All Threads 2414system.cpu1.int_regfile_reads 391717330 # number of integer regfile reads 2415system.cpu1.int_regfile_writes 56386728 # number of integer regfile writes 2416system.cpu1.fp_regfile_reads 5093 # number of floating regfile reads 2417system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes 2418system.cpu1.misc_regfile_reads 202967536 # number of misc regfile reads 2419system.cpu1.misc_regfile_writes 722997 # number of misc regfile writes 2420system.cpu1.icache.tags.replacements 614130 # number of replacements 2421system.cpu1.icache.tags.tagsinuse 498.669942 # Cycle average of tags in use 2422system.cpu1.icache.tags.total_refs 7060189 # Total number of references to valid blocks. 2423system.cpu1.icache.tags.sampled_refs 614642 # Sample count of references to valid blocks. 2424system.cpu1.icache.tags.avg_refs 11.486669 # Average number of references to valid blocks. 2425system.cpu1.icache.tags.warmup_cycle 74938249500 # Cycle when the warmup percentage was hit. 2426system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.669942 # Average occupied blocks per requestor 2427system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973965 # Average percentage of cache occupancy 2428system.cpu1.icache.tags.occ_percent::total 0.973965 # Average percentage of cache occupancy |
| 2440system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2441system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 2442system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2429system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2430system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 2431system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2443system.cpu1.icache.tags.tag_accesses 8332076 # Number of tag accesses 2444system.cpu1.icache.tags.data_accesses 8332076 # Number of data accesses 2445system.cpu1.icache.ReadReq_hits::cpu1.inst 7054617 # number of ReadReq hits 2446system.cpu1.icache.ReadReq_hits::total 7054617 # number of ReadReq hits 2447system.cpu1.icache.demand_hits::cpu1.inst 7054617 # number of demand (read+write) hits 2448system.cpu1.icache.demand_hits::total 7054617 # number of demand (read+write) hits 2449system.cpu1.icache.overall_hits::cpu1.inst 7054617 # number of overall hits 2450system.cpu1.icache.overall_hits::total 7054617 # number of overall hits 2451system.cpu1.icache.ReadReq_misses::cpu1.inst 662013 # number of ReadReq misses 2452system.cpu1.icache.ReadReq_misses::total 662013 # number of ReadReq misses 2453system.cpu1.icache.demand_misses::cpu1.inst 662013 # number of demand (read+write) misses 2454system.cpu1.icache.demand_misses::total 662013 # number of demand (read+write) misses 2455system.cpu1.icache.overall_misses::cpu1.inst 662013 # number of overall misses 2456system.cpu1.icache.overall_misses::total 662013 # number of overall misses 2457system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8999563943 # number of ReadReq miss cycles 2458system.cpu1.icache.ReadReq_miss_latency::total 8999563943 # number of ReadReq miss cycles 2459system.cpu1.icache.demand_miss_latency::cpu1.inst 8999563943 # number of demand (read+write) miss cycles 2460system.cpu1.icache.demand_miss_latency::total 8999563943 # number of demand (read+write) miss cycles 2461system.cpu1.icache.overall_miss_latency::cpu1.inst 8999563943 # number of overall miss cycles 2462system.cpu1.icache.overall_miss_latency::total 8999563943 # number of overall miss cycles 2463system.cpu1.icache.ReadReq_accesses::cpu1.inst 7716630 # number of ReadReq accesses(hits+misses) 2464system.cpu1.icache.ReadReq_accesses::total 7716630 # number of ReadReq accesses(hits+misses) 2465system.cpu1.icache.demand_accesses::cpu1.inst 7716630 # number of demand (read+write) accesses 2466system.cpu1.icache.demand_accesses::total 7716630 # number of demand (read+write) accesses 2467system.cpu1.icache.overall_accesses::cpu1.inst 7716630 # number of overall (read+write) accesses 2468system.cpu1.icache.overall_accesses::total 7716630 # number of overall (read+write) accesses 2469system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085790 # miss rate for ReadReq accesses 2470system.cpu1.icache.ReadReq_miss_rate::total 0.085790 # miss rate for ReadReq accesses 2471system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085790 # miss rate for demand accesses 2472system.cpu1.icache.demand_miss_rate::total 0.085790 # miss rate for demand accesses 2473system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085790 # miss rate for overall accesses 2474system.cpu1.icache.overall_miss_rate::total 0.085790 # miss rate for overall accesses 2475system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13594.240510 # average ReadReq miss latency 2476system.cpu1.icache.ReadReq_avg_miss_latency::total 13594.240510 # average ReadReq miss latency 2477system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13594.240510 # average overall miss latency 2478system.cpu1.icache.demand_avg_miss_latency::total 13594.240510 # average overall miss latency 2479system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13594.240510 # average overall miss latency 2480system.cpu1.icache.overall_avg_miss_latency::total 13594.240510 # average overall miss latency 2481system.cpu1.icache.blocked_cycles::no_mshrs 3570 # number of cycles access was blocked 2482system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2483system.cpu1.icache.blocked::no_mshrs 201 # number of cycles access was blocked 2484system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2485system.cpu1.icache.avg_blocked_cycles::no_mshrs 17.761194 # average number of cycles each access was blocked 2486system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2432system.cpu1.icache.tags.tag_accesses 8336018 # Number of tag accesses 2433system.cpu1.icache.tags.data_accesses 8336018 # Number of data accesses 2434system.cpu1.icache.ReadReq_hits::cpu1.inst 7060189 # number of ReadReq hits 2435system.cpu1.icache.ReadReq_hits::total 7060189 # number of ReadReq hits 2436system.cpu1.icache.demand_hits::cpu1.inst 7060189 # number of demand (read+write) hits 2437system.cpu1.icache.demand_hits::total 7060189 # number of demand (read+write) hits 2438system.cpu1.icache.overall_hits::cpu1.inst 7060189 # number of overall hits 2439system.cpu1.icache.overall_hits::total 7060189 # number of overall hits 2440system.cpu1.icache.ReadReq_misses::cpu1.inst 661158 # number of ReadReq misses 2441system.cpu1.icache.ReadReq_misses::total 661158 # number of ReadReq misses 2442system.cpu1.icache.demand_misses::cpu1.inst 661158 # number of demand (read+write) misses 2443system.cpu1.icache.demand_misses::total 661158 # number of demand (read+write) misses 2444system.cpu1.icache.overall_misses::cpu1.inst 661158 # number of overall misses 2445system.cpu1.icache.overall_misses::total 661158 # number of overall misses 2446system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8979670253 # number of ReadReq miss cycles 2447system.cpu1.icache.ReadReq_miss_latency::total 8979670253 # number of ReadReq miss cycles 2448system.cpu1.icache.demand_miss_latency::cpu1.inst 8979670253 # number of demand (read+write) miss cycles 2449system.cpu1.icache.demand_miss_latency::total 8979670253 # number of demand (read+write) miss cycles 2450system.cpu1.icache.overall_miss_latency::cpu1.inst 8979670253 # number of overall miss cycles 2451system.cpu1.icache.overall_miss_latency::total 8979670253 # number of overall miss cycles 2452system.cpu1.icache.ReadReq_accesses::cpu1.inst 7721347 # number of ReadReq accesses(hits+misses) 2453system.cpu1.icache.ReadReq_accesses::total 7721347 # number of ReadReq accesses(hits+misses) 2454system.cpu1.icache.demand_accesses::cpu1.inst 7721347 # number of demand (read+write) accesses 2455system.cpu1.icache.demand_accesses::total 7721347 # number of demand (read+write) accesses 2456system.cpu1.icache.overall_accesses::cpu1.inst 7721347 # number of overall (read+write) accesses 2457system.cpu1.icache.overall_accesses::total 7721347 # number of overall (read+write) accesses 2458system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085627 # miss rate for ReadReq accesses 2459system.cpu1.icache.ReadReq_miss_rate::total 0.085627 # miss rate for ReadReq accesses 2460system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085627 # miss rate for demand accesses 2461system.cpu1.icache.demand_miss_rate::total 0.085627 # miss rate for demand accesses 2462system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085627 # miss rate for overall accesses 2463system.cpu1.icache.overall_miss_rate::total 0.085627 # miss rate for overall accesses 2464system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13581.731225 # average ReadReq miss latency 2465system.cpu1.icache.ReadReq_avg_miss_latency::total 13581.731225 # average ReadReq miss latency 2466system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13581.731225 # average overall miss latency 2467system.cpu1.icache.demand_avg_miss_latency::total 13581.731225 # average overall miss latency 2468system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13581.731225 # average overall miss latency 2469system.cpu1.icache.overall_avg_miss_latency::total 13581.731225 # average overall miss latency 2470system.cpu1.icache.blocked_cycles::no_mshrs 3157 # number of cycles access was blocked 2471system.cpu1.icache.blocked_cycles::no_targets 541 # number of cycles access was blocked 2472system.cpu1.icache.blocked::no_mshrs 208 # number of cycles access was blocked 2473system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2474system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.177885 # average number of cycles each access was blocked 2475system.cpu1.icache.avg_blocked_cycles::no_targets 541 # average number of cycles each access was blocked |
| 2487system.cpu1.icache.fast_writes 0 # number of fast writes performed 2488system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2476system.cpu1.icache.fast_writes 0 # number of fast writes performed 2477system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2489system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46567 # number of ReadReq MSHR hits 2490system.cpu1.icache.ReadReq_mshr_hits::total 46567 # number of ReadReq MSHR hits 2491system.cpu1.icache.demand_mshr_hits::cpu1.inst 46567 # number of demand (read+write) MSHR hits 2492system.cpu1.icache.demand_mshr_hits::total 46567 # number of demand (read+write) MSHR hits 2493system.cpu1.icache.overall_mshr_hits::cpu1.inst 46567 # number of overall MSHR hits 2494system.cpu1.icache.overall_mshr_hits::total 46567 # number of overall MSHR hits 2495system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615446 # number of ReadReq MSHR misses 2496system.cpu1.icache.ReadReq_mshr_misses::total 615446 # number of ReadReq MSHR misses 2497system.cpu1.icache.demand_mshr_misses::cpu1.inst 615446 # number of demand (read+write) MSHR misses 2498system.cpu1.icache.demand_mshr_misses::total 615446 # number of demand (read+write) MSHR misses 2499system.cpu1.icache.overall_mshr_misses::cpu1.inst 615446 # number of overall MSHR misses 2500system.cpu1.icache.overall_mshr_misses::total 615446 # number of overall MSHR misses 2501system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343690408 # number of ReadReq MSHR miss cycles 2502system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343690408 # number of ReadReq MSHR miss cycles 2503system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343690408 # number of demand (read+write) MSHR miss cycles 2504system.cpu1.icache.demand_mshr_miss_latency::total 7343690408 # number of demand (read+write) MSHR miss cycles 2505system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343690408 # number of overall MSHR miss cycles 2506system.cpu1.icache.overall_mshr_miss_latency::total 7343690408 # number of overall MSHR miss cycles 2507system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3568500 # number of ReadReq MSHR uncacheable cycles 2508system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3568500 # number of ReadReq MSHR uncacheable cycles 2509system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3568500 # number of overall MSHR uncacheable cycles 2510system.cpu1.icache.overall_mshr_uncacheable_latency::total 3568500 # number of overall MSHR uncacheable cycles 2511system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for ReadReq accesses 2512system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079756 # mshr miss rate for ReadReq accesses 2513system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for demand accesses 2514system.cpu1.icache.demand_mshr_miss_rate::total 0.079756 # mshr miss rate for demand accesses 2515system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for overall accesses 2516system.cpu1.icache.overall_mshr_miss_rate::total 0.079756 # mshr miss rate for overall accesses 2517system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average ReadReq mshr miss latency 2518system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11932.306665 # average ReadReq mshr miss latency 2519system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average overall mshr miss latency 2520system.cpu1.icache.demand_avg_mshr_miss_latency::total 11932.306665 # average overall mshr miss latency 2521system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average overall mshr miss latency 2522system.cpu1.icache.overall_avg_mshr_miss_latency::total 11932.306665 # average overall mshr miss latency | 2478system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46487 # number of ReadReq MSHR hits 2479system.cpu1.icache.ReadReq_mshr_hits::total 46487 # number of ReadReq MSHR hits 2480system.cpu1.icache.demand_mshr_hits::cpu1.inst 46487 # number of demand (read+write) MSHR hits 2481system.cpu1.icache.demand_mshr_hits::total 46487 # number of demand (read+write) MSHR hits 2482system.cpu1.icache.overall_mshr_hits::cpu1.inst 46487 # number of overall MSHR hits 2483system.cpu1.icache.overall_mshr_hits::total 46487 # number of overall MSHR hits 2484system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 614671 # number of ReadReq MSHR misses 2485system.cpu1.icache.ReadReq_mshr_misses::total 614671 # number of ReadReq MSHR misses 2486system.cpu1.icache.demand_mshr_misses::cpu1.inst 614671 # number of demand (read+write) MSHR misses 2487system.cpu1.icache.demand_mshr_misses::total 614671 # number of demand (read+write) MSHR misses 2488system.cpu1.icache.overall_mshr_misses::cpu1.inst 614671 # number of overall MSHR misses 2489system.cpu1.icache.overall_mshr_misses::total 614671 # number of overall MSHR misses 2490system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7323309836 # number of ReadReq MSHR miss cycles 2491system.cpu1.icache.ReadReq_mshr_miss_latency::total 7323309836 # number of ReadReq MSHR miss cycles 2492system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7323309836 # number of demand (read+write) MSHR miss cycles 2493system.cpu1.icache.demand_mshr_miss_latency::total 7323309836 # number of demand (read+write) MSHR miss cycles 2494system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7323309836 # number of overall MSHR miss cycles 2495system.cpu1.icache.overall_mshr_miss_latency::total 7323309836 # number of overall MSHR miss cycles 2496system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3568000 # number of ReadReq MSHR uncacheable cycles 2497system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3568000 # number of ReadReq MSHR uncacheable cycles 2498system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3568000 # number of overall MSHR uncacheable cycles 2499system.cpu1.icache.overall_mshr_uncacheable_latency::total 3568000 # number of overall MSHR uncacheable cycles 2500system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for ReadReq accesses 2501system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079607 # mshr miss rate for ReadReq accesses 2502system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for demand accesses 2503system.cpu1.icache.demand_mshr_miss_rate::total 0.079607 # mshr miss rate for demand accesses 2504system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for overall accesses 2505system.cpu1.icache.overall_mshr_miss_rate::total 0.079607 # mshr miss rate for overall accesses 2506system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average ReadReq mshr miss latency 2507system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.194481 # average ReadReq mshr miss latency 2508system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average overall mshr miss latency 2509system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.194481 # average overall mshr miss latency 2510system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average overall mshr miss latency 2511system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.194481 # average overall mshr miss latency |
| 2523system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2524system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2525system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2526system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2527system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2512system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2513system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2514system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2515system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2516system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2528system.cpu1.dcache.tags.replacements 363287 # number of replacements 2529system.cpu1.dcache.tags.tagsinuse 485.536511 # Cycle average of tags in use 2530system.cpu1.dcache.tags.total_refs 13021437 # Total number of references to valid blocks. 2531system.cpu1.dcache.tags.sampled_refs 363669 # Sample count of references to valid blocks. 2532system.cpu1.dcache.tags.avg_refs 35.805738 # Average number of references to valid blocks. 2533system.cpu1.dcache.tags.warmup_cycle 70976822000 # Cycle when the warmup percentage was hit. 2534system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.536511 # Average occupied blocks per requestor 2535system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948313 # Average percentage of cache occupancy 2536system.cpu1.dcache.tags.occ_percent::total 0.948313 # Average percentage of cache occupancy 2537system.cpu1.dcache.tags.occ_task_id_blocks::1024 382 # Occupied blocks per task id 2538system.cpu1.dcache.tags.age_task_id_blocks_1024::2 382 # Occupied blocks per task id 2539system.cpu1.dcache.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id 2540system.cpu1.dcache.tags.tag_accesses 60298440 # Number of tag accesses 2541system.cpu1.dcache.tags.data_accesses 60298440 # Number of data accesses 2542system.cpu1.dcache.ReadReq_hits::cpu1.data 8515057 # number of ReadReq hits 2543system.cpu1.dcache.ReadReq_hits::total 8515057 # number of ReadReq hits 2544system.cpu1.dcache.WriteReq_hits::cpu1.data 4269820 # number of WriteReq hits 2545system.cpu1.dcache.WriteReq_hits::total 4269820 # number of WriteReq hits 2546system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99795 # number of LoadLockedReq hits 2547system.cpu1.dcache.LoadLockedReq_hits::total 99795 # number of LoadLockedReq hits 2548system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97086 # number of StoreCondReq hits 2549system.cpu1.dcache.StoreCondReq_hits::total 97086 # number of StoreCondReq hits 2550system.cpu1.dcache.demand_hits::cpu1.data 12784877 # number of demand (read+write) hits 2551system.cpu1.dcache.demand_hits::total 12784877 # number of demand (read+write) hits 2552system.cpu1.dcache.overall_hits::cpu1.data 12784877 # number of overall hits 2553system.cpu1.dcache.overall_hits::total 12784877 # number of overall hits 2554system.cpu1.dcache.ReadReq_misses::cpu1.data 402462 # number of ReadReq misses 2555system.cpu1.dcache.ReadReq_misses::total 402462 # number of ReadReq misses 2556system.cpu1.dcache.WriteReq_misses::cpu1.data 1568055 # number of WriteReq misses 2557system.cpu1.dcache.WriteReq_misses::total 1568055 # number of WriteReq misses 2558system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14174 # number of LoadLockedReq misses 2559system.cpu1.dcache.LoadLockedReq_misses::total 14174 # number of LoadLockedReq misses 2560system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10915 # number of StoreCondReq misses 2561system.cpu1.dcache.StoreCondReq_misses::total 10915 # number of StoreCondReq misses 2562system.cpu1.dcache.demand_misses::cpu1.data 1970517 # number of demand (read+write) misses 2563system.cpu1.dcache.demand_misses::total 1970517 # number of demand (read+write) misses 2564system.cpu1.dcache.overall_misses::cpu1.data 1970517 # number of overall misses 2565system.cpu1.dcache.overall_misses::total 1970517 # number of overall misses 2566system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6127843210 # number of ReadReq miss cycles 2567system.cpu1.dcache.ReadReq_miss_latency::total 6127843210 # number of ReadReq miss cycles 2568system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 79461121233 # number of WriteReq miss cycles 2569system.cpu1.dcache.WriteReq_miss_latency::total 79461121233 # number of WriteReq miss cycles 2570system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 130724743 # number of LoadLockedReq miss cycles 2571system.cpu1.dcache.LoadLockedReq_miss_latency::total 130724743 # number of LoadLockedReq miss cycles 2572system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58221587 # number of StoreCondReq miss cycles 2573system.cpu1.dcache.StoreCondReq_miss_latency::total 58221587 # number of StoreCondReq miss cycles 2574system.cpu1.dcache.demand_miss_latency::cpu1.data 85588964443 # number of demand (read+write) miss cycles 2575system.cpu1.dcache.demand_miss_latency::total 85588964443 # number of demand (read+write) miss cycles 2576system.cpu1.dcache.overall_miss_latency::cpu1.data 85588964443 # number of overall miss cycles 2577system.cpu1.dcache.overall_miss_latency::total 85588964443 # number of overall miss cycles 2578system.cpu1.dcache.ReadReq_accesses::cpu1.data 8917519 # number of ReadReq accesses(hits+misses) 2579system.cpu1.dcache.ReadReq_accesses::total 8917519 # number of ReadReq accesses(hits+misses) 2580system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837875 # number of WriteReq accesses(hits+misses) 2581system.cpu1.dcache.WriteReq_accesses::total 5837875 # number of WriteReq accesses(hits+misses) 2582system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113969 # number of LoadLockedReq accesses(hits+misses) 2583system.cpu1.dcache.LoadLockedReq_accesses::total 113969 # number of LoadLockedReq accesses(hits+misses) 2584system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108001 # number of StoreCondReq accesses(hits+misses) 2585system.cpu1.dcache.StoreCondReq_accesses::total 108001 # number of StoreCondReq accesses(hits+misses) 2586system.cpu1.dcache.demand_accesses::cpu1.data 14755394 # number of demand (read+write) accesses 2587system.cpu1.dcache.demand_accesses::total 14755394 # number of demand (read+write) accesses 2588system.cpu1.dcache.overall_accesses::cpu1.data 14755394 # number of overall (read+write) accesses 2589system.cpu1.dcache.overall_accesses::total 14755394 # number of overall (read+write) accesses 2590system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045132 # miss rate for ReadReq accesses 2591system.cpu1.dcache.ReadReq_miss_rate::total 0.045132 # miss rate for ReadReq accesses 2592system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268600 # miss rate for WriteReq accesses 2593system.cpu1.dcache.WriteReq_miss_rate::total 0.268600 # miss rate for WriteReq accesses 2594system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124367 # miss rate for LoadLockedReq accesses 2595system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124367 # miss rate for LoadLockedReq accesses 2596system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101064 # miss rate for StoreCondReq accesses 2597system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101064 # miss rate for StoreCondReq accesses 2598system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133546 # miss rate for demand accesses 2599system.cpu1.dcache.demand_miss_rate::total 0.133546 # miss rate for demand accesses 2600system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133546 # miss rate for overall accesses 2601system.cpu1.dcache.overall_miss_rate::total 0.133546 # miss rate for overall accesses 2602system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15225.892656 # average ReadReq miss latency 2603system.cpu1.dcache.ReadReq_avg_miss_latency::total 15225.892656 # average ReadReq miss latency 2604system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50674.957979 # average WriteReq miss latency 2605system.cpu1.dcache.WriteReq_avg_miss_latency::total 50674.957979 # average WriteReq miss latency 2606system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9222.854734 # average LoadLockedReq miss latency 2607system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9222.854734 # average LoadLockedReq miss latency 2608system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.089510 # average StoreCondReq miss latency 2609system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.089510 # average StoreCondReq miss latency 2610system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43434.775971 # average overall miss latency 2611system.cpu1.dcache.demand_avg_miss_latency::total 43434.775971 # average overall miss latency 2612system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43434.775971 # average overall miss latency 2613system.cpu1.dcache.overall_avg_miss_latency::total 43434.775971 # average overall miss latency 2614system.cpu1.dcache.blocked_cycles::no_mshrs 28687 # number of cycles access was blocked 2615system.cpu1.dcache.blocked_cycles::no_targets 20050 # number of cycles access was blocked | 2517system.cpu1.dcache.tags.replacements 363457 # number of replacements 2518system.cpu1.dcache.tags.tagsinuse 485.510277 # Cycle average of tags in use 2519system.cpu1.dcache.tags.total_refs 13025047 # Total number of references to valid blocks. 2520system.cpu1.dcache.tags.sampled_refs 363822 # Sample count of references to valid blocks. 2521system.cpu1.dcache.tags.avg_refs 35.800603 # Average number of references to valid blocks. 2522system.cpu1.dcache.tags.warmup_cycle 70981354000 # Cycle when the warmup percentage was hit. 2523system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.510277 # Average occupied blocks per requestor 2524system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948262 # Average percentage of cache occupancy 2525system.cpu1.dcache.tags.occ_percent::total 0.948262 # Average percentage of cache occupancy 2526system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 2527system.cpu1.dcache.tags.age_task_id_blocks_1024::2 365 # Occupied blocks per task id 2528system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 2529system.cpu1.dcache.tags.tag_accesses 60307713 # Number of tag accesses 2530system.cpu1.dcache.tags.data_accesses 60307713 # Number of data accesses 2531system.cpu1.dcache.ReadReq_hits::cpu1.data 8518372 # number of ReadReq hits 2532system.cpu1.dcache.ReadReq_hits::total 8518372 # number of ReadReq hits 2533system.cpu1.dcache.WriteReq_hits::cpu1.data 4270609 # number of WriteReq hits 2534system.cpu1.dcache.WriteReq_hits::total 4270609 # number of WriteReq hits 2535system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99866 # number of LoadLockedReq hits 2536system.cpu1.dcache.LoadLockedReq_hits::total 99866 # number of LoadLockedReq hits 2537system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97035 # number of StoreCondReq hits 2538system.cpu1.dcache.StoreCondReq_hits::total 97035 # number of StoreCondReq hits 2539system.cpu1.dcache.demand_hits::cpu1.data 12788981 # number of demand (read+write) hits 2540system.cpu1.dcache.demand_hits::total 12788981 # number of demand (read+write) hits 2541system.cpu1.dcache.overall_hits::cpu1.data 12788981 # number of overall hits 2542system.cpu1.dcache.overall_hits::total 12788981 # number of overall hits 2543system.cpu1.dcache.ReadReq_misses::cpu1.data 402659 # number of ReadReq misses 2544system.cpu1.dcache.ReadReq_misses::total 402659 # number of ReadReq misses 2545system.cpu1.dcache.WriteReq_misses::cpu1.data 1566002 # number of WriteReq misses 2546system.cpu1.dcache.WriteReq_misses::total 1566002 # number of WriteReq misses 2547system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14224 # number of LoadLockedReq misses 2548system.cpu1.dcache.LoadLockedReq_misses::total 14224 # number of LoadLockedReq misses 2549system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10931 # number of StoreCondReq misses 2550system.cpu1.dcache.StoreCondReq_misses::total 10931 # number of StoreCondReq misses 2551system.cpu1.dcache.demand_misses::cpu1.data 1968661 # number of demand (read+write) misses 2552system.cpu1.dcache.demand_misses::total 1968661 # number of demand (read+write) misses 2553system.cpu1.dcache.overall_misses::cpu1.data 1968661 # number of overall misses 2554system.cpu1.dcache.overall_misses::total 1968661 # number of overall misses 2555system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6122123976 # number of ReadReq miss cycles 2556system.cpu1.dcache.ReadReq_miss_latency::total 6122123976 # number of ReadReq miss cycles 2557system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 79209493026 # number of WriteReq miss cycles 2558system.cpu1.dcache.WriteReq_miss_latency::total 79209493026 # number of WriteReq miss cycles 2559system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131211992 # number of LoadLockedReq miss cycles 2560system.cpu1.dcache.LoadLockedReq_miss_latency::total 131211992 # number of LoadLockedReq miss cycles 2561system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58251087 # number of StoreCondReq miss cycles 2562system.cpu1.dcache.StoreCondReq_miss_latency::total 58251087 # number of StoreCondReq miss cycles 2563system.cpu1.dcache.demand_miss_latency::cpu1.data 85331617002 # number of demand (read+write) miss cycles 2564system.cpu1.dcache.demand_miss_latency::total 85331617002 # number of demand (read+write) miss cycles 2565system.cpu1.dcache.overall_miss_latency::cpu1.data 85331617002 # number of overall miss cycles 2566system.cpu1.dcache.overall_miss_latency::total 85331617002 # number of overall miss cycles 2567system.cpu1.dcache.ReadReq_accesses::cpu1.data 8921031 # number of ReadReq accesses(hits+misses) 2568system.cpu1.dcache.ReadReq_accesses::total 8921031 # number of ReadReq accesses(hits+misses) 2569system.cpu1.dcache.WriteReq_accesses::cpu1.data 5836611 # number of WriteReq accesses(hits+misses) 2570system.cpu1.dcache.WriteReq_accesses::total 5836611 # number of WriteReq accesses(hits+misses) 2571system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 114090 # number of LoadLockedReq accesses(hits+misses) 2572system.cpu1.dcache.LoadLockedReq_accesses::total 114090 # number of LoadLockedReq accesses(hits+misses) 2573system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107966 # number of StoreCondReq accesses(hits+misses) 2574system.cpu1.dcache.StoreCondReq_accesses::total 107966 # number of StoreCondReq accesses(hits+misses) 2575system.cpu1.dcache.demand_accesses::cpu1.data 14757642 # number of demand (read+write) accesses 2576system.cpu1.dcache.demand_accesses::total 14757642 # number of demand (read+write) accesses 2577system.cpu1.dcache.overall_accesses::cpu1.data 14757642 # number of overall (read+write) accesses 2578system.cpu1.dcache.overall_accesses::total 14757642 # number of overall (read+write) accesses 2579system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045136 # miss rate for ReadReq accesses 2580system.cpu1.dcache.ReadReq_miss_rate::total 0.045136 # miss rate for ReadReq accesses 2581system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268307 # miss rate for WriteReq accesses 2582system.cpu1.dcache.WriteReq_miss_rate::total 0.268307 # miss rate for WriteReq accesses 2583system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124674 # miss rate for LoadLockedReq accesses 2584system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124674 # miss rate for LoadLockedReq accesses 2585system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101245 # miss rate for StoreCondReq accesses 2586system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101245 # miss rate for StoreCondReq accesses 2587system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133399 # miss rate for demand accesses 2588system.cpu1.dcache.demand_miss_rate::total 0.133399 # miss rate for demand accesses 2589system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133399 # miss rate for overall accesses 2590system.cpu1.dcache.overall_miss_rate::total 0.133399 # miss rate for overall accesses 2591system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15204.239756 # average ReadReq miss latency 2592system.cpu1.dcache.ReadReq_avg_miss_latency::total 15204.239756 # average ReadReq miss latency 2593system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50580.710003 # average WriteReq miss latency 2594system.cpu1.dcache.WriteReq_avg_miss_latency::total 50580.710003 # average WriteReq miss latency 2595system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9224.690101 # average LoadLockedReq miss latency 2596system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9224.690101 # average LoadLockedReq miss latency 2597system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5328.980606 # average StoreCondReq miss latency 2598system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5328.980606 # average StoreCondReq miss latency 2599system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43345.003026 # average overall miss latency 2600system.cpu1.dcache.demand_avg_miss_latency::total 43345.003026 # average overall miss latency 2601system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43345.003026 # average overall miss latency 2602system.cpu1.dcache.overall_avg_miss_latency::total 43345.003026 # average overall miss latency 2603system.cpu1.dcache.blocked_cycles::no_mshrs 29359 # number of cycles access was blocked 2604system.cpu1.dcache.blocked_cycles::no_targets 20069 # number of cycles access was blocked |
| 2616system.cpu1.dcache.blocked::no_mshrs 3274 # number of cycles access was blocked | 2605system.cpu1.dcache.blocked::no_mshrs 3274 # number of cycles access was blocked |
| 2617system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked 2618system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.762065 # average number of cycles each access was blocked 2619system.cpu1.dcache.avg_blocked_cycles::no_targets 115.229885 # average number of cycles each access was blocked | 2606system.cpu1.dcache.blocked::no_targets 177 # number of cycles access was blocked 2607system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.967318 # average number of cycles each access was blocked 2608system.cpu1.dcache.avg_blocked_cycles::no_targets 113.384181 # average number of cycles each access was blocked |
| 2620system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2621system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2609system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2610system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2622system.cpu1.dcache.writebacks::writebacks 327819 # number of writebacks 2623system.cpu1.dcache.writebacks::total 327819 # number of writebacks 2624system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171130 # number of ReadReq MSHR hits 2625system.cpu1.dcache.ReadReq_mshr_hits::total 171130 # number of ReadReq MSHR hits 2626system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1404670 # number of WriteReq MSHR hits 2627system.cpu1.dcache.WriteReq_mshr_hits::total 1404670 # number of WriteReq MSHR hits 2628system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1454 # number of LoadLockedReq MSHR hits 2629system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1454 # number of LoadLockedReq MSHR hits 2630system.cpu1.dcache.demand_mshr_hits::cpu1.data 1575800 # number of demand (read+write) MSHR hits 2631system.cpu1.dcache.demand_mshr_hits::total 1575800 # number of demand (read+write) MSHR hits 2632system.cpu1.dcache.overall_mshr_hits::cpu1.data 1575800 # number of overall MSHR hits 2633system.cpu1.dcache.overall_mshr_hits::total 1575800 # number of overall MSHR hits 2634system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231332 # number of ReadReq MSHR misses 2635system.cpu1.dcache.ReadReq_mshr_misses::total 231332 # number of ReadReq MSHR misses 2636system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163385 # number of WriteReq MSHR misses 2637system.cpu1.dcache.WriteReq_mshr_misses::total 163385 # number of WriteReq MSHR misses 2638system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses 2639system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses 2640system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10915 # number of StoreCondReq MSHR misses 2641system.cpu1.dcache.StoreCondReq_mshr_misses::total 10915 # number of StoreCondReq MSHR misses 2642system.cpu1.dcache.demand_mshr_misses::cpu1.data 394717 # number of demand (read+write) MSHR misses 2643system.cpu1.dcache.demand_mshr_misses::total 394717 # number of demand (read+write) MSHR misses 2644system.cpu1.dcache.overall_mshr_misses::cpu1.data 394717 # number of overall MSHR misses 2645system.cpu1.dcache.overall_mshr_misses::total 394717 # number of overall MSHR misses 2646system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2884558137 # number of ReadReq MSHR miss cycles 2647system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2884558137 # number of ReadReq MSHR miss cycles 2648system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7099464771 # number of WriteReq MSHR miss cycles 2649system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7099464771 # number of WriteReq MSHR miss cycles 2650system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89380256 # number of LoadLockedReq MSHR miss cycles 2651system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89380256 # number of LoadLockedReq MSHR miss cycles 2652system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36390413 # number of StoreCondReq MSHR miss cycles 2653system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36390413 # number of StoreCondReq MSHR miss cycles 2654system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9984022908 # number of demand (read+write) MSHR miss cycles 2655system.cpu1.dcache.demand_mshr_miss_latency::total 9984022908 # number of demand (read+write) MSHR miss cycles 2656system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9984022908 # number of overall MSHR miss cycles 2657system.cpu1.dcache.overall_mshr_miss_latency::total 9984022908 # number of overall MSHR miss cycles 2658system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231255506 # number of ReadReq MSHR uncacheable cycles 2659system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231255506 # number of ReadReq MSHR uncacheable cycles 2660system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25855700445 # number of WriteReq MSHR uncacheable cycles 2661system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25855700445 # number of WriteReq MSHR uncacheable cycles 2662system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195086955951 # number of overall MSHR uncacheable cycles 2663system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195086955951 # number of overall MSHR uncacheable cycles 2664system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025941 # mshr miss rate for ReadReq accesses 2665system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025941 # mshr miss rate for ReadReq accesses 2666system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027987 # mshr miss rate for WriteReq accesses 2667system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027987 # mshr miss rate for WriteReq accesses 2668system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111609 # mshr miss rate for LoadLockedReq accesses 2669system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111609 # mshr miss rate for LoadLockedReq accesses 2670system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101064 # mshr miss rate for StoreCondReq accesses 2671system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101064 # mshr miss rate for StoreCondReq accesses 2672system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for demand accesses 2673system.cpu1.dcache.demand_mshr_miss_rate::total 0.026751 # mshr miss rate for demand accesses 2674system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for overall accesses 2675system.cpu1.dcache.overall_mshr_miss_rate::total 0.026751 # mshr miss rate for overall accesses 2676system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12469.343355 # average ReadReq mshr miss latency 2677system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12469.343355 # average ReadReq mshr miss latency 2678system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43452.365707 # average WriteReq mshr miss latency 2679system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43452.365707 # average WriteReq mshr miss latency 2680system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7026.749686 # average LoadLockedReq mshr miss latency 2681system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7026.749686 # average LoadLockedReq mshr miss latency 2682system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3333.981951 # average StoreCondReq mshr miss latency 2683system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3333.981951 # average StoreCondReq mshr miss latency 2684system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency 2685system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency 2686system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency 2687system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency | 2611system.cpu1.dcache.writebacks::writebacks 327725 # number of writebacks 2612system.cpu1.dcache.writebacks::total 327725 # number of writebacks 2613system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171279 # number of ReadReq MSHR hits 2614system.cpu1.dcache.ReadReq_mshr_hits::total 171279 # number of ReadReq MSHR hits 2615system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402802 # number of WriteReq MSHR hits 2616system.cpu1.dcache.WriteReq_mshr_hits::total 1402802 # number of WriteReq MSHR hits 2617system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits 2618system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits 2619system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574081 # number of demand (read+write) MSHR hits 2620system.cpu1.dcache.demand_mshr_hits::total 1574081 # number of demand (read+write) MSHR hits 2621system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574081 # number of overall MSHR hits 2622system.cpu1.dcache.overall_mshr_hits::total 1574081 # number of overall MSHR hits 2623system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231380 # number of ReadReq MSHR misses 2624system.cpu1.dcache.ReadReq_mshr_misses::total 231380 # number of ReadReq MSHR misses 2625system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163200 # number of WriteReq MSHR misses 2626system.cpu1.dcache.WriteReq_mshr_misses::total 163200 # number of WriteReq MSHR misses 2627system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12769 # number of LoadLockedReq MSHR misses 2628system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses 2629system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10931 # number of StoreCondReq MSHR misses 2630system.cpu1.dcache.StoreCondReq_mshr_misses::total 10931 # number of StoreCondReq MSHR misses 2631system.cpu1.dcache.demand_mshr_misses::cpu1.data 394580 # number of demand (read+write) MSHR misses 2632system.cpu1.dcache.demand_mshr_misses::total 394580 # number of demand (read+write) MSHR misses 2633system.cpu1.dcache.overall_mshr_misses::cpu1.data 394580 # number of overall MSHR misses 2634system.cpu1.dcache.overall_mshr_misses::total 394580 # number of overall MSHR misses 2635system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2885564133 # number of ReadReq MSHR miss cycles 2636system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2885564133 # number of ReadReq MSHR miss cycles 2637system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7076211500 # number of WriteReq MSHR miss cycles 2638system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7076211500 # number of WriteReq MSHR miss cycles 2639system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89844256 # number of LoadLockedReq MSHR miss cycles 2640system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89844256 # number of LoadLockedReq MSHR miss cycles 2641system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36388913 # number of StoreCondReq MSHR miss cycles 2642system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36388913 # number of StoreCondReq MSHR miss cycles 2643system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 2644system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 2645system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9961775633 # number of demand (read+write) MSHR miss cycles 2646system.cpu1.dcache.demand_mshr_miss_latency::total 9961775633 # number of demand (read+write) MSHR miss cycles 2647system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9961775633 # number of overall MSHR miss cycles 2648system.cpu1.dcache.overall_mshr_miss_latency::total 9961775633 # number of overall MSHR miss cycles 2649system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169230997009 # number of ReadReq MSHR uncacheable cycles 2650system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169230997009 # number of ReadReq MSHR uncacheable cycles 2651system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25854670209 # number of WriteReq MSHR uncacheable cycles 2652system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25854670209 # number of WriteReq MSHR uncacheable cycles 2653system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195085667218 # number of overall MSHR uncacheable cycles 2654system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195085667218 # number of overall MSHR uncacheable cycles 2655system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025936 # mshr miss rate for ReadReq accesses 2656system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025936 # mshr miss rate for ReadReq accesses 2657system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027961 # mshr miss rate for WriteReq accesses 2658system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027961 # mshr miss rate for WriteReq accesses 2659system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111920 # mshr miss rate for LoadLockedReq accesses 2660system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111920 # mshr miss rate for LoadLockedReq accesses 2661system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101245 # mshr miss rate for StoreCondReq accesses 2662system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101245 # mshr miss rate for StoreCondReq accesses 2663system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026737 # mshr miss rate for demand accesses 2664system.cpu1.dcache.demand_mshr_miss_rate::total 0.026737 # mshr miss rate for demand accesses 2665system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026737 # mshr miss rate for overall accesses 2666system.cpu1.dcache.overall_mshr_miss_rate::total 0.026737 # mshr miss rate for overall accesses 2667system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12471.104387 # average ReadReq mshr miss latency 2668system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12471.104387 # average ReadReq mshr miss latency 2669system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43359.139093 # average WriteReq mshr miss latency 2670system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43359.139093 # average WriteReq mshr miss latency 2671system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7036.123111 # average LoadLockedReq mshr miss latency 2672system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7036.123111 # average LoadLockedReq mshr miss latency 2673system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3328.964688 # average StoreCondReq mshr miss latency 2674system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3328.964688 # average StoreCondReq mshr miss latency 2675system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2676system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2677system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25246.529558 # average overall mshr miss latency 2678system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25246.529558 # average overall mshr miss latency 2679system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25246.529558 # average overall mshr miss latency 2680system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25246.529558 # average overall mshr miss latency |
| 2688system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2689system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2690system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2691system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2692system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2693system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2694system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2695system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 2703system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2704system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2705system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2706system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2707system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2708system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2709system.iocache.fast_writes 0 # number of fast writes performed 2710system.iocache.cache_copies 0 # number of cache copies performed | 2681system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2682system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2683system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2684system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2685system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2686system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2687system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2688system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 2696system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2697system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2698system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2699system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2700system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2701system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2702system.iocache.fast_writes 0 # number of fast writes performed 2703system.iocache.cache_copies 0 # number of cache copies performed |
| 2711system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of ReadReq MSHR uncacheable cycles 2712system.iocache.ReadReq_mshr_uncacheable_latency::total 1519279146805 # number of ReadReq MSHR uncacheable cycles 2713system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of overall MSHR uncacheable cycles 2714system.iocache.overall_mshr_uncacheable_latency::total 1519279146805 # number of overall MSHR uncacheable cycles | 2704system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519280505301 # number of ReadReq MSHR uncacheable cycles 2705system.iocache.ReadReq_mshr_uncacheable_latency::total 1519280505301 # number of ReadReq MSHR uncacheable cycles 2706system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519280505301 # number of overall MSHR uncacheable cycles 2707system.iocache.overall_mshr_uncacheable_latency::total 1519280505301 # number of overall MSHR uncacheable cycles |
| 2715system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2716system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2717system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2718system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2719system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2720system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 2708system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2709system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2710system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2711system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2712system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2713system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 2721system.cpu0.kern.inst.quiesce 42657 # number of quiesce instructions executed | 2714system.cpu0.kern.inst.quiesce 42637 # number of quiesce instructions executed |
| 2722system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 2715system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 2723system.cpu1.kern.inst.quiesce 50405 # number of quiesce instructions executed | 2716system.cpu1.kern.inst.quiesce 50394 # number of quiesce instructions executed |
| 2724 2725---------- End Simulation Statistics ---------- | 2717 2718---------- End Simulation Statistics ---------- |