3,5c3,5
< sim_seconds 1.102950 # Number of seconds simulated
< sim_ticks 1102950399000 # Number of ticks simulated
< final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.102940 # Number of seconds simulated
> sim_ticks 1102940172000 # Number of ticks simulated
> final_tick 1102940172000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 57810 # Simulator instruction rate (inst/s)
< host_op_rate 74418 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1035290197 # Simulator tick rate (ticks/s)
< host_mem_usage 414988 # Number of bytes of host memory used
< host_seconds 1065.35 # Real time elapsed on the host
< sim_insts 61588287 # Number of instructions simulated
< sim_ops 79281553 # Number of ops (including micro ops) simulated
---
> host_inst_rate 65652 # Simulator instruction rate (inst/s)
> host_op_rate 84510 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1175755462 # Simulator tick rate (ticks/s)
> host_mem_usage 411412 # Number of bytes of host memory used
> host_seconds 938.07 # Real time elapsed on the host
> sim_insts 61586245 # Number of instructions simulated
> sim_ops 79276446 # Number of ops (including micro ops) simulated
16,18c16,18
< system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 409472 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 4368500 # Number of bytes read from this memory
22,24c22,24
< system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory
< system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory
> system.physmem.bytes_read::total 59192100 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 409472 # Number of instructions bytes read from this memory
26,27c26,27
< system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory
---
> system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4269568 # Number of bytes written to this memory
30c30
< system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7296912 # Number of bytes written to this memory
33,35c33,35
< system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 6398 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 68330 # Number of read requests responded to by this memory
39,41c39,41
< system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 6257967 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66712 # Number of write requests responded to by this memory
44,45c44,45
< system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 823548 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 44208004 # Total read bandwidth from this memory (bytes/s)
47,49c47,49
< system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.itb.walker 290 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 371255 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 3960777 # Total read bandwidth from this memory (bytes/s)
52,58c52,58
< system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 367773 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 4757770 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 53667553 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 371255 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 367773 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 739028 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3871079 # Write bandwidth from this memory (bytes/s)
60,63c60,63
< system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::cpu1.data 2729381 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 6615873 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3871079 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 44208004 # Total bandwidth to/from this memory (bytes/s)
65,67c65,67
< system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.itb.walker 290 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 371255 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 3976190 # Total bandwidth to/from this memory (bytes/s)
70,79c70,79
< system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 6257953 # Total number of read requests seen
< system.physmem.writeReqs 823537 # Total number of write requests seen
< system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 400508992 # Total number of bytes read from memory
< system.physmem.bytesWritten 52706368 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize()
---
> system.physmem.bw_total::cpu1.inst 367773 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 7487151 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 60283426 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 6257967 # Total number of read requests seen
> system.physmem.writeReqs 823548 # Total number of write requests seen
> system.physmem.cpureqs 242288 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 400509888 # Total number of bytes read from memory
> system.physmem.bytesWritten 52707072 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 59192100 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7296912 # bytesWritten derated as per pkt->getSize()
81,83c81,83
< system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis
---
> system.physmem.neitherReadNorWrite 12562 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 391387 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 391216 # Track reads on a per bank basis
85,88c85,88
< system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::3 391623 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 391542 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 390911 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 390957 # Track reads on a per bank basis
90,91c90,91
< system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 390709 # Track reads on a per bank basis
93,95c93,95
< system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::11 391233 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 391227 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 390512 # Track reads on a per bank basis
97,99c97,99
< system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis
---
> system.physmem.perBankRdReqs::15 391259 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 51233 # Track writes on a per bank basis
101,108c101,108
< system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::3 51696 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 51565 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 51001 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 51007 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 51680 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 52040 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 51500 # Track writes on a per bank basis
110,113c110,113
< system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 51252 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis
116c116
< system.physmem.totGap 1102949217500 # Total gap between requests
---
> system.physmem.totGap 1102939019000 # Total gap between requests
123c123
< system.physmem.readPktSize::6 163000 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 163014 # Categorize read packet sizes
130,146c130,146
< system.physmem.writePktSize::6 66701 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 66712 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 493693 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 430180 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 391390 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1441411 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 1086258 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1098726 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1064578 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 26935 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 24930 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 44513 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 63858 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 44248 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 12053 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 11796 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 17166 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 5937 # What read queue length does an incoming req see
163,172c163,172
< system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 2968 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 3047 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 3073 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 3096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 3128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 3152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 3172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 35807 # What write queue length does an incoming req see
185,186c185,186
< system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::22 35806 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see
195,200c195,200
< system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests
< system.physmem.totBusLat 31289160000 # Total cycles spent in databus access
< system.physmem.totBankLat 8530335000 # Total cycles spent in bank access
< system.physmem.avgQLat 31830.81 # Average queueing delay per request
< system.physmem.avgBankLat 1363.15 # Average bank access latency per request
---
> system.physmem.totQLat 199192058500 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 239013617250 # Sum of mem lat for all requests
> system.physmem.totBusLat 31289230000 # Total cycles spent in databus access
> system.physmem.totBankLat 8532328750 # Total cycles spent in bank access
> system.physmem.avgQLat 31830.77 # Average queueing delay per request
> system.physmem.avgBankLat 1363.46 # Average bank access latency per request
202c202
< system.physmem.avgMemAccLat 38193.95 # Average memory access latency
---
> system.physmem.avgMemAccLat 38194.23 # Average memory access latency
210,212c210,212
< system.physmem.avgWrQLen 11.98 # Average write queue length over time
< system.physmem.readRowHits 6213974 # Number of row buffer hits during reads
< system.physmem.writeRowHits 800028 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 12.05 # Average write queue length over time
> system.physmem.readRowHits 6213954 # Number of row buffer hits during reads
> system.physmem.writeRowHits 800040 # Number of row buffer hits during writes
215c215
< system.physmem.avgGap 155751.01 # Average gap between requests
---
> system.physmem.avgGap 155749.02 # Average gap between requests
234,238c234,238
< system.l2c.replacements 72704 # number of replacements
< system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use
< system.l2c.total_refs 1840692 # Total number of references to valid blocks.
< system.l2c.sampled_refs 137860 # Sample count of references to valid blocks.
< system.l2c.avg_refs 13.351893 # Average number of references to valid blocks.
---
> system.l2c.replacements 72718 # number of replacements
> system.l2c.tagsinuse 53743.140165 # Cycle average of tags in use
> system.l2c.total_refs 1840331 # Total number of references to valid blocks.
> system.l2c.sampled_refs 137862 # Sample count of references to valid blocks.
> system.l2c.avg_refs 13.349081 # Average number of references to valid blocks.
240,249c240,249
< system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::writebacks 39373.587396 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.dtb.walker 3.826422 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.itb.walker 1.187080 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.inst 4008.736100 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 2822.118244 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.dtb.walker 11.062372 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.itb.walker 0.921462 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.inst 3716.187342 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 3805.513745 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.600793 # Average percentage of cache occupancy
252,253c252,253
< system.l2c.occ_percent::cpu0.inst 0.061165 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.data 0.043063 # Average percentage of cache occupancy
---
> system.l2c.occ_percent::cpu0.inst 0.061168 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.data 0.043062 # Average percentage of cache occupancy
256,257c256,257
< system.l2c.occ_percent::cpu1.inst 0.056709 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.data 0.058067 # Average percentage of cache occupancy
---
> system.l2c.occ_percent::cpu1.inst 0.056705 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.data 0.058068 # Average percentage of cache occupancy
259,296c259,296
< system.l2c.ReadReq_hits::cpu0.dtb.walker 21930 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 4443 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 386616 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 166642 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 30274 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 5231 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 590416 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 197851 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1403403 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 581067 # number of Writeback hits
< system.l2c.Writeback_hits::total 581067 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 1230 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 737 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1967 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 342 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 48406 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 58608 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 107014 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 21930 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 4443 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 386616 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 215048 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 30274 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 5231 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 590416 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 256459 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1510417 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 21930 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 4443 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 386616 # number of overall hits
< system.l2c.overall_hits::cpu0.data 215048 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 30274 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 5231 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 590416 # number of overall hits
< system.l2c.overall_hits::cpu1.data 256459 # number of overall hits
< system.l2c.overall_hits::total 1510417 # number of overall hits
---
> system.l2c.ReadReq_hits::cpu0.dtb.walker 22141 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 4502 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 386239 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 166660 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 30329 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 5168 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 590386 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 197820 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1403245 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 580806 # number of Writeback hits
> system.l2c.Writeback_hits::total 580806 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 1235 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 1978 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 346 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 48231 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 58599 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 106830 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 22141 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4502 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 386239 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 214891 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 30329 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 5168 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 590386 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 256419 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1510075 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 22141 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4502 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 386239 # number of overall hits
> system.l2c.overall_hits::cpu0.data 214891 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 30329 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 5168 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 590386 # number of overall hits
> system.l2c.overall_hits::cpu1.data 256419 # number of overall hits
> system.l2c.overall_hits::total 1510075 # number of overall hits
298,300c298,300
< system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.inst 6270 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 6414 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.inst 6277 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 6416 # number of ReadReq misses
305,306c305,306
< system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 5137 # number of UpgradeReq misses
---
> system.l2c.ReadReq_misses::total 25330 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 5125 # number of UpgradeReq misses
308,312c308,312
< system.l2c.UpgradeReq_misses::total 8911 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 414 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1055 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 63277 # number of ReadExReq misses
---
> system.l2c.UpgradeReq_misses::total 8899 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 638 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 411 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1049 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 63279 # number of ReadExReq misses
314c314
< system.l2c.ReadExReq_misses::total 140200 # number of ReadExReq misses
---
> system.l2c.ReadExReq_misses::total 140202 # number of ReadExReq misses
316,318c316,318
< system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 6270 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 69691 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 6277 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 69695 # number of demand (read+write) misses
323c323
< system.l2c.demand_misses::total 165520 # number of demand (read+write) misses
---
> system.l2c.demand_misses::total 165532 # number of demand (read+write) misses
325,327c325,327
< system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 6270 # number of overall misses
< system.l2c.overall_misses::cpu0.data 69691 # number of overall misses
---
> system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 6277 # number of overall misses
> system.l2c.overall_misses::cpu0.data 69695 # number of overall misses
332c332
< system.l2c.overall_misses::total 165520 # number of overall misses
---
> system.l2c.overall_misses::total 165532 # number of overall misses
334,336c334,336
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 345548000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 371089999 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 324500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 347861000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 370402499 # number of ReadReq miss cycles
339,350c339,350
< system.l2c.ReadReq_miss_latency::cpu1.inst 378000500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 393265500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1490340499 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 8952484 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 11872000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 20824484 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2820500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 3434500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 3142895481 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 4127198996 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 7270094477 # number of ReadExReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 379078500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 392453000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1492300499 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 8816984 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 11833500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 20650484 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 568000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2844000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 3412000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 3138283486 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 4133582496 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 7271865982 # number of ReadExReq miss cycles
352,354c352,354
< system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 345548000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 3513985480 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.itb.walker 324500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 347861000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 3508685985 # number of demand (read+write) miss cycles
357,359c357,359
< system.l2c.demand_miss_latency::cpu1.inst 378000500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 4520464496 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 8760434976 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu1.inst 379078500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 4526035496 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 8764166481 # number of demand (read+write) miss cycles
361,363c361,363
< system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 345548000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 3513985480 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.itb.walker 324500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 347861000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 3508685985 # number of overall miss cycles
366,442c366,442
< system.l2c.overall_miss_latency::cpu1.inst 378000500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 4520464496 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 8760434976 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 21941 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 4447 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 392886 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 173056 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 30291 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 5232 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 596718 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 204152 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1428723 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 581067 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 581067 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 6367 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 4511 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 10878 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 840 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1397 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 111683 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 135531 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 247214 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 21941 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 4447 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 392886 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 284739 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 30291 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 5232 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 596718 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 339683 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1675937 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 21941 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 4447 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 392886 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 284739 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 30291 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 5232 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 596718 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 339683 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1675937 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000899 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.015959 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.037063 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.010561 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.030864 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.017722 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806816 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836622 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.819176 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.763095 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.743268 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.755190 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.566577 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.567568 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.567120 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.000899 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.015959 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.244754 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.010561 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.245005 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.098763 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.000899 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.015959 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.244754 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.010561 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.245005 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.098763 # miss rate for overall accesses
---
> system.l2c.overall_miss_latency::cpu1.inst 379078500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 4526035496 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 8764166481 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 22152 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 4507 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 392516 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 173076 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 30346 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 5169 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 596688 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 204121 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1428575 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 580806 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 580806 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 6360 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 4517 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 10877 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 839 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 556 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1395 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 111510 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 135522 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 247032 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 22152 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 4507 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 392516 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 284586 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 30346 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 5169 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 596688 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 339643 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1675607 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 22152 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 4507 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 392516 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 284586 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 30346 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 5169 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 596688 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 339643 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1675607 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001109 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.015992 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.037070 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000193 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.010562 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.030869 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.017731 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805818 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835510 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.818148 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.760429 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.739209 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.751971 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.567474 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.567605 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.567546 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.001109 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.015992 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.244900 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.000193 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.010562 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.245034 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.098789 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.001109 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.015992 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.244900 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.000193 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.010562 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.245034 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.098789 # miss rate for overall accesses
444,446c444,446
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55111.323764 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 57856.251793 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 64900 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55418.352716 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 57731.062812 # average ReadReq miss latency
449,460c449,460
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59981.037766 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 62413.188383 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 58860.209281 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1742.745571 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3145.733969 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2336.941308 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 957.878315 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6812.801932 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3255.450237 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49668.844620 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53653.640602 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 51855.167454 # average ReadExReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60152.094573 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 62284.240597 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 58914.350533 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1720.387122 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3135.532591 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2320.539836 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 890.282132 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6919.708029 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.621544 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49594.391283 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53736.626185 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 51867.063109 # average ReadExReq miss latency
462,464c462,464
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency
467,469c467,469
< system.l2c.demand_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 52926.745868 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 52945.451520 # average overall miss latency
471,473c471,473
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency
476,478c476,478
< system.l2c.overall_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 52926.745868 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 52945.451520 # average overall miss latency
487,488c487,488
< system.l2c.writebacks::writebacks 66701 # number of writebacks
< system.l2c.writebacks::total 66701 # number of writebacks
---
> system.l2c.writebacks::writebacks 66712 # number of writebacks
> system.l2c.writebacks::total 66712 # number of writebacks
505,507c505,507
< system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.inst 6266 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 6377 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.inst 6273 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 6379 # number of ReadReq MSHR misses
512,513c512,513
< system.l2c.ReadReq_mshr_misses::total 25248 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 5137 # number of UpgradeReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::total 25258 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 5125 # number of UpgradeReq MSHR misses
515,519c515,519
< system.l2c.UpgradeReq_mshr_misses::total 8911 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 641 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 414 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1055 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 63277 # number of ReadExReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::total 8899 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 638 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 411 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1049 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 63279 # number of ReadExReq MSHR misses
521c521
< system.l2c.ReadExReq_mshr_misses::total 140200 # number of ReadExReq MSHR misses
---
> system.l2c.ReadExReq_mshr_misses::total 140202 # number of ReadExReq MSHR misses
523,525c523,525
< system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 6266 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 69654 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 6273 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 69658 # number of demand (read+write) MSHR misses
530c530
< system.l2c.demand_mshr_misses::total 165448 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::total 165460 # number of demand (read+write) MSHR misses
532,534c532,534
< system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 6266 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 69654 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 6273 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 69658 # number of overall MSHR misses
539c539
< system.l2c.overall_mshr_misses::total 165448 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::total 165460 # number of overall MSHR misses
541,543c541,543
< system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 205753 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 267326853 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 290309543 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 262004 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 269548612 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 289309796 # number of ReadReq MSHR miss cycles
546,557c546,557
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 299283802 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 313561196 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 1172505926 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51651498 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38386206 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 90037704 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6474116 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4151410 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 10625526 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2358673626 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165005465 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 5523679091 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300356052 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312753448 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 1174048691 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51546985 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38368705 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 89915690 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6444113 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4119409 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 10563522 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354035161 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3171377741 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 5525412902 # number of ReadExReq MSHR miss cycles
559,561c559,561
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 267326853 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2648983169 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 262004 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 269548612 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2643344957 # number of demand (read+write) MSHR miss cycles
564,566c564,566
< system.l2c.demand_mshr_miss_latency::cpu1.inst 299283802 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 3478566661 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 6696185017 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu1.inst 300356052 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 3484131189 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 6699461593 # number of demand (read+write) MSHR miss cycles
568,570c568,570
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 267326853 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2648983169 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 262004 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 269548612 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2643344957 # number of overall MSHR miss cycles
573,575c573,575
< system.l2c.overall_mshr_miss_latency::cpu1.inst 299283802 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 3478566661 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 6696185017 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu1.inst 300356052 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 3484131189 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 6699461593 # number of overall MSHR miss cycles
577c577
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408173048 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408099047 # number of ReadReq MSHR uncacheable cycles
579,583c579,583
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667335749 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 167082908164 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050136738 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922783304 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 26972920042 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667429748 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 167082928162 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050132738 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922779804 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 26972912542 # number of WriteReq MSHR uncacheable cycles
585c585
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458309786 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458231785 # number of overall MSHR uncacheable cycles
587,624c587,624
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590119053 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 194055828206 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036849 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030747 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.017672 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806816 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836622 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.819176 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.763095 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.743268 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755190 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566577 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567568 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.567120 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.098720 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590209552 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 194055840704 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036857 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030751 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.017681 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805818 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835510 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.818148 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.760429 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.739209 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.751971 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567474 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567605 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.567546 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.098746 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.098746 # mshr miss rate for overall accesses
626,628c626,628
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45353.471704 # average ReadReq mshr miss latency
631,642c631,642
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49825.306357 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 46482.250812 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.948293 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10166.588500 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.021800 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.490596 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892944 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10070.087703 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37200.890675 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41227.951861 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 39410.371478 # average ReadExReq mshr miss latency
644,646c644,646
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency
649,651c649,651
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency
653,655c653,655
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency
658,660c658,660
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency
681,685c681,685
< system.cpu0.branchPred.lookups 6001263 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 5998401 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 4575821 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 294349 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 3757481 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 2911128 # Number of BTB hits
687,689c687,689
< system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 77.475521 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 672992 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 28616 # Number of incorrect RAS predictions.
692,695c692,695
< system.cpu0.dtb.read_hits 8907872 # DTB read hits
< system.cpu0.dtb.read_misses 28815 # DTB read misses
< system.cpu0.dtb.write_hits 5138143 # DTB write hits
< system.cpu0.dtb.write_misses 5606 # DTB write misses
---
> system.cpu0.dtb.read_hits 8907261 # DTB read hits
> system.cpu0.dtb.read_misses 28773 # DTB read misses
> system.cpu0.dtb.write_hits 5136781 # DTB write hits
> system.cpu0.dtb.write_misses 5705 # DTB write misses
700,701c700,701
< system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions
---
> system.cpu0.dtb.flush_entries 1814 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions
704,706c704,706
< system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 8936687 # DTB read accesses
< system.cpu0.dtb.write_accesses 5143749 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 560 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 8936034 # DTB read accesses
> system.cpu0.dtb.write_accesses 5142486 # DTB write accesses
708,712c708,712
< system.cpu0.dtb.hits 14046015 # DTB hits
< system.cpu0.dtb.misses 34421 # DTB misses
< system.cpu0.dtb.accesses 14080436 # DTB accesses
< system.cpu0.itb.inst_hits 4220167 # ITB inst hits
< system.cpu0.itb.inst_misses 5223 # ITB inst misses
---
> system.cpu0.dtb.hits 14044042 # DTB hits
> system.cpu0.dtb.misses 34478 # DTB misses
> system.cpu0.dtb.accesses 14078520 # DTB accesses
> system.cpu0.itb.inst_hits 4215431 # ITB inst hits
> system.cpu0.itb.inst_misses 5154 # ITB inst misses
721c721
< system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
725c725
< system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions
728,732c728,732
< system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses
< system.cpu0.itb.hits 4220167 # DTB hits
< system.cpu0.itb.misses 5223 # DTB misses
< system.cpu0.itb.accesses 4225390 # DTB accesses
< system.cpu0.numCycles 67827032 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 4220585 # ITB inst accesses
> system.cpu0.itb.hits 4215431 # DTB hits
> system.cpu0.itb.misses 5154 # DTB misses
> system.cpu0.itb.accesses 4220585 # DTB accesses
> system.cpu0.numCycles 67803924 # number of cpu cycles simulated
735,745c735,745
< system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions
---
> system.cpu0.fetch.icacheStallCycles 11747073 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 32000754 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 5998401 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 3584120 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 7510773 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1450164 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 64498 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.BlockedCycles 20642358 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 4878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 46878 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 85526 # Number of stall cycles due to pending quiesce instructions
747,752c747,752
< system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.CacheLines 4213800 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 157670 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 2178 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 41143503 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 1.004869 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.385262 # Number of instructions fetched each cycle (Total)
754,762c754,762
< system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 33640113 81.76% 81.76% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 564874 1.37% 83.14% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 815232 1.98% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 675522 1.64% 86.76% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 773200 1.88% 88.64% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 558709 1.36% 90.00% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 669860 1.63% 91.62% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 351529 0.85% 92.48% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 3094464 7.52% 100.00% # Number of instructions fetched each cycle (Total)
766,811c766,811
< system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers
< system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 41143503 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.088467 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.471960 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 12253117 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 20585756 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 6814381 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 512539 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 977710 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 934268 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 64694 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 39987776 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 212486 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 977710 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 12820427 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 5742393 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 12731772 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 6709970 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 2161231 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 38889294 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 1829 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 434890 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1234500 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.FullRegisterEvents 47 # Number of times there has been no free registers
> system.cpu0.rename.RenamedOperands 39244828 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 175643455 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 175609334 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 34121 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 30926653 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 8318174 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 411256 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 370334 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 5351915 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 7647673 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 5682766 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1124413 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 1217910 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 36816448 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 895564 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 37227077 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 80165 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 6275180 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 13166441 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 256842 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 41143503 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.904811 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.512506 # Number of insts issued each cycle
813,821c813,821
< system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 26013518 63.23% 63.23% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 5726772 13.92% 77.15% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 3163675 7.69% 84.83% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2471330 6.01% 90.84% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2096927 5.10% 95.94% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 946781 2.30% 98.24% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 487184 1.18% 99.42% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 184280 0.45% 99.87% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 53036 0.13% 100.00% # Number of insts issued each cycle
825c825
< system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 41143503 # Number of insts issued each cycle
827,857c827,857
< system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 25911 2.42% 2.42% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 452 0.04% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 841841 78.68% 81.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 201703 18.85% 100.00% # attempts to use FU when none available
860,885c860,885
< system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 22320567 59.96% 60.10% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 46962 0.13% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
890,891c890,891
< system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::MemRead 9363552 25.15% 85.38% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5443123 14.62% 100.00% # Type of FU issued
894,906c894,906
< system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued
< system.cpu0.iq.rate 0.549010 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 37227077 # Type of FU issued
> system.cpu0.iq.rate 0.549040 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 1069907 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.028740 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 116773591 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 43995152 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 34325365 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 8374 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 4656 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 38240450 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 4385 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 307272 # Number of loads that had data forwarded from stores
908,911c908,911
< system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1372635 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2428 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 13158 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 533443 # Number of stores squashed
914,915c914,915
< system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 2192715 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 5605 # Number of times an access to memory failed due to the cache being blocked
917,933c917,933
< system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 977710 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 4125178 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 98819 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 37830480 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 84891 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 7647673 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 5682766 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 571414 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 40435 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 2836 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 13158 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 149420 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 117102 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 266522 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 36852561 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 9222790 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 374516 # Number of squashed instructions skipped in execute
935,943c935,943
< system.cpu0.iew.exec_nop 118689 # number of nop insts executed
< system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 4854206 # Number of branches executed
< system.cpu0.iew.exec_stores 5397839 # Number of stores executed
< system.cpu0.iew.exec_rate 0.543462 # Inst execution rate
< system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 18281082 # num instructions producing a value
< system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 118468 # number of nop insts executed
> system.cpu0.iew.exec_refs 14619280 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 4853073 # Number of branches executed
> system.cpu0.iew.exec_stores 5396490 # Number of stores executed
> system.cpu0.iew.exec_rate 0.543517 # Inst execution rate
> system.cpu0.iew.wb_sent 36658484 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 34329238 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 18277167 # num instructions producing a value
> system.cpu0.iew.wb_consumers 35166979 # num instructions consuming a value
945,946c945,946
< system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.506302 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.519725 # average fanout of values written-back
948,953c948,953
< system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 6089898 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 638722 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 230765 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 40165793 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.778810 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.740848 # Number of insts commited each cycle
955,963c955,963
< system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 28496220 70.95% 70.95% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 5717219 14.23% 85.18% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 1914261 4.77% 89.95% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 974261 2.43% 92.37% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 784320 1.95% 94.32% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 523319 1.30% 95.63% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 386116 0.96% 96.59% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 218199 0.54% 97.13% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1151878 2.87% 100.00% # Number of insts commited each cycle
967,969c967,969
< system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 23679748 # Number of instructions committed
< system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 40165793 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 23678008 # Number of instructions committed
> system.cpu0.commit.committedOps 31281512 # Number of ops (including micro ops) committed
971,974c971,974
< system.cpu0.commit.refs 11426897 # Number of memory references committed
< system.cpu0.commit.loads 6276420 # Number of loads committed
< system.cpu0.commit.membars 229667 # Number of memory barriers committed
< system.cpu0.commit.branches 4245051 # Number of branches committed
---
> system.cpu0.commit.refs 11424361 # Number of memory references committed
> system.cpu0.commit.loads 6275038 # Number of loads committed
> system.cpu0.commit.membars 229662 # Number of memory barriers committed
> system.cpu0.commit.branches 4244821 # Number of branches committed
976,978c976,978
< system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 489354 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached
---
> system.cpu0.commit.int_insts 27638419 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 489334 # Number of function calls committed.
> system.cpu0.commit.bw_lim_events 1151878 # number cycles where commit BW limit reached
980,1002c980,1002
< system.cpu0.rob.rob_reads 75566033 # The number of ROB reads
< system.cpu0.rob.rob_writes 75750322 # The number of ROB writes
< system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 23599006 # Number of Instructions Simulated
< system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated
< system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads
< system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 900 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes
< system.cpu0.icache.replacements 392871 # number of replacements
< system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use
< system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks.
---
> system.cpu0.rob.rob_reads 75534199 # The number of ROB reads
> system.cpu0.rob.rob_writes 75722713 # The number of ROB writes
> system.cpu0.timesIdled 360446 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 26660421 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 2138034694 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 23597266 # Number of Instructions Simulated
> system.cpu0.committedOps 31200770 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 23597266 # Number of Instructions Simulated
> system.cpu0.cpi 2.873381 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.873381 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.348022 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.348022 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 171786019 # number of integer regfile reads
> system.cpu0.int_regfile_writes 34080976 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 3260 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 902 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 13006141 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 451094 # number of misc regfile writes
> system.cpu0.icache.replacements 392511 # number of replacements
> system.cpu0.icache.tagsinuse 511.076367 # Cycle average of tags in use
> system.cpu0.icache.total_refs 3789958 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 393023 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 9.643095 # Average number of references to valid blocks.
1004c1004
< system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor
---
> system.cpu0.icache.occ_blocks::cpu0.inst 511.076367 # Average occupied blocks per requestor
1007,1043c1007,1043
< system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits
< system.cpu0.icache.overall_hits::total 3794104 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses
< system.cpu0.icache.overall_misses::total 424196 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked
---
> system.cpu0.icache.ReadReq_hits::cpu0.inst 3789958 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 3789958 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 3789958 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 3789958 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 3789958 # number of overall hits
> system.cpu0.icache.overall_hits::total 3789958 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 423709 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 423709 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 423709 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 423709 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 423709 # number of overall misses
> system.cpu0.icache.overall_misses::total 423709 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803688497 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 5803688497 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 5803688497 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 5803688497 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 5803688497 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 5803688497 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213667 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 4213667 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 4213667 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 4213667 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 4213667 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 4213667 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13697.345341 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13697.345341 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 2656 # number of cycles access was blocked
1045c1045
< system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 149 # number of cycles access was blocked
1047c1047
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.825503 # average number of cycles each access was blocked
1051,1068c1051,1068
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30672 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 30672 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 30672 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 30672 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 30672 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 30672 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393037 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 393037 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 393037 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 393037 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 393037 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 393037 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4746801497 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 4746801497 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4746801497 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 4746801497 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4746801497 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 4746801497 # number of overall MSHR miss cycles
1073,1084c1073,1084
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093277 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.093277 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.093277 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency
1090,1094c1090,1094
< system.cpu0.dcache.replacements 276008 # number of replacements
< system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks.
---
> system.cpu0.dcache.replacements 275921 # number of replacements
> system.cpu0.dcache.tagsinuse 460.698692 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 9260016 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 276433 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 33.498229 # Average number of references to valid blocks.
1096,1176c1096,1176
< system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits
< system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked
---
> system.cpu0.dcache.occ_blocks::cpu0.data 460.698692 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.899802 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.899802 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 5779987 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 5779987 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3159663 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3159663 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139233 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 139233 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137076 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 137076 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 8939650 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 8939650 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 8939650 # number of overall hits
> system.cpu0.dcache.overall_hits::total 8939650 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 392818 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 392818 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1582384 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1582384 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8769 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 8769 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1975202 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1975202 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1975202 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1975202 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5481439500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5481439500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60566359369 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 60566359369 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87760500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 87760500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46440000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 46440000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 66047798869 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 66047798869 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 66047798869 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 66047798869 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172805 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 6172805 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4742047 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4742047 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144540 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 144540 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 10914852 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 10914852 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 10914852 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 10914852 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063637 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.063637 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333692 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.333692 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059249 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059249 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051640 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051640 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180965 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.180965 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180965 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.180965 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.864952 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.864952 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 8565 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 5561 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 643 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.320373 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 68.654321 # average number of cycles each access was blocked
1179,1244c1179,1244
< system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks
< system.cpu0.dcache.writebacks::total 256612 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks
> system.cpu0.dcache.writebacks::total 256512 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204354 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 204354 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452130 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1452130 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 476 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 476 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656484 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1656484 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656484 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1656484 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188464 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 188464 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130254 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 130254 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8293 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8293 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7464 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 7464 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 318718 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 318718 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 318718 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 318718 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378480500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378480500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4031341491 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4031341491 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65938500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65938500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31512000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31512000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6409821991 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 6409821991 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6409821991 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 6409821991 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514864500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514864500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180302878 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180302878 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695167378 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695167378 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030531 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030531 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027468 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027468 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056033 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056033 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051640 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051640 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.029200 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.029200 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7951.103340 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7951.103340 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4221.864952 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4221.864952 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency
1252,1256c1252,1256
< system.cpu1.branchPred.lookups 9071093 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 9068423 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 7455270 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 408018 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 6064102 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 5241151 # Number of BTB hits
1258,1260c1258,1260
< system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 86.429137 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 772299 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 42697 # Number of incorrect RAS predictions.
1263,1266c1263,1266
< system.cpu1.dtb.read_hits 42899284 # DTB read hits
< system.cpu1.dtb.read_misses 36667 # DTB read misses
< system.cpu1.dtb.write_hits 6823776 # DTB write hits
< system.cpu1.dtb.write_misses 10740 # DTB write misses
---
> system.cpu1.dtb.read_hits 42898238 # DTB read hits
> system.cpu1.dtb.read_misses 36741 # DTB read misses
> system.cpu1.dtb.write_hits 6823025 # DTB write hits
> system.cpu1.dtb.write_misses 10725 # DTB write misses
1271,1273c1271,1273
< system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 2008 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 2490 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch
1275,1277c1275,1277
< system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 42935951 # DTB read accesses
< system.cpu1.dtb.write_accesses 6834516 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 42934979 # DTB read accesses
> system.cpu1.dtb.write_accesses 6833750 # DTB write accesses
1279,1283c1279,1283
< system.cpu1.dtb.hits 49723060 # DTB hits
< system.cpu1.dtb.misses 47407 # DTB misses
< system.cpu1.dtb.accesses 49770467 # DTB accesses
< system.cpu1.itb.inst_hits 8396614 # ITB inst hits
< system.cpu1.itb.inst_misses 5496 # ITB inst misses
---
> system.cpu1.dtb.hits 49721263 # DTB hits
> system.cpu1.dtb.misses 47466 # DTB misses
> system.cpu1.dtb.accesses 49768729 # DTB accesses
> system.cpu1.itb.inst_hits 8394494 # ITB inst hits
> system.cpu1.itb.inst_misses 5446 # ITB inst misses
1292c1292
< system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1530 # Number of entries that have been flushed from TLB
1296c1296
< system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 1510 # Number of TLB faults due to permissions restrictions
1299,1303c1299,1303
< system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses
< system.cpu1.itb.hits 8396614 # DTB hits
< system.cpu1.itb.misses 5496 # DTB misses
< system.cpu1.itb.accesses 8402110 # DTB accesses
< system.cpu1.numCycles 408759365 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 8399940 # ITB inst accesses
> system.cpu1.itb.hits 8394494 # DTB hits
> system.cpu1.itb.misses 5446 # DTB misses
> system.cpu1.itb.accesses 8399940 # DTB accesses
> system.cpu1.numCycles 408755802 # number of cpu cycles simulated
1306,1316c1306,1316
< system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions
---
> system.cpu1.fetch.icacheStallCycles 19793701 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 66043012 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 9068423 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 6013450 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 14139093 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 3958938 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 65451 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.BlockedCycles 77253219 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 4575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 41710 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 129512 # Number of stall cycles due to pending quiesce instructions
1318,1323c1318,1323
< system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.CacheLines 8392686 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 740378 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 2825 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 114124947 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.700718 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.045131 # Number of instructions fetched each cycle (Total)
1325,1333c1325,1333
< system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 99993030 87.62% 87.62% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 796567 0.70% 88.32% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 937489 0.82% 89.14% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 1887963 1.65% 90.79% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 1516591 1.33% 92.12% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 569617 0.50% 92.62% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 2129815 1.87% 94.49% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 410324 0.36% 94.84% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 5883551 5.16% 100.00% # Number of instructions fetched each cycle (Total)
1337,1382c1337,1382
< system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 114124947 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.022185 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.161571 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 21308374 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 76909285 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 12783383 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 523008 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 2600897 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 1105255 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 98147 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 75181804 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 327202 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 2600897 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 22691617 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 31944842 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 40730815 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 11827860 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 4328916 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 69723383 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 18766 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 668457 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 3086605 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.FullRegisterEvents 426 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 73713482 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 321023926 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 320964994 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 58932 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 49048009 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 24665473 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 444684 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 387735 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 7872422 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 13201823 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 8142648 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 1033883 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 1534096 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 63487985 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 1158001 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 89118015 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 94635 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 16215431 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 45695453 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 277388 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 114124947 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.780881 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.519165 # Number of insts issued each cycle
1384,1392c1384,1392
< system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 83732864 73.37% 73.37% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 8404718 7.36% 80.73% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 4298594 3.77% 84.50% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 3768314 3.30% 87.80% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 10582090 9.27% 97.07% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 1967507 1.72% 98.80% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 1024622 0.90% 99.70% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 272364 0.24% 99.94% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 73874 0.06% 100.00% # Number of insts issued each cycle
1396c1396
< system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 114124947 # Number of insts issued each cycle
1398,1399c1398,1399
< system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 29701 0.38% 0.38% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available
1427,1428c1427,1428
< system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::MemRead 7545557 95.86% 96.25% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 295033 3.75% 100.00% # attempts to use FU when none available
1432,1433c1432,1433
< system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 37610156 42.20% 42.55% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 59163 0.07% 42.62% # Type of FU issued
1446c1446
< system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.62% # Type of FU issued
1450c1450
< system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.62% # Type of FU issued
1459c1459
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.62% # Type of FU issued
1461,1462c1461,1462
< system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::MemRead 43962640 49.33% 91.95% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 7170532 8.05% 100.00% # Type of FU issued
1465,1477c1465,1477
< system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued
< system.cpu1.iq.rate 0.218037 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 89118015 # Type of FU issued
> system.cpu1.iq.rate 0.218023 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 7871289 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.088324 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 300359292 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 80869896 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 53629107 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 8062 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 6802 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 96667481 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 7826 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 342650 # Number of loads that had data forwarded from stores
1479,1482c1479,1482
< system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 3449296 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 3766 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 17093 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 1304806 # Number of stores squashed
1485,1486c1485,1486
< system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 31906048 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 888017 # Number of times an access to memory failed due to the cache being blocked
1488,1504c1488,1504
< system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 2600897 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 24182074 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 360611 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 64750813 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 110749 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 13201823 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 8142648 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 869251 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 65576 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 3534 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 17093 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 201242 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 155476 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 356718 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 86688682 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 43267985 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 2429333 # Number of squashed instructions skipped in execute
1506,1514c1506,1514
< system.cpu1.iew.exec_nop 104622 # number of nop insts executed
< system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 7000416 # Number of branches executed
< system.cpu1.iew.exec_stores 7109526 # Number of stores executed
< system.cpu1.iew.exec_rate 0.212092 # Inst execution rate
< system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 29911901 # num instructions producing a value
< system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 104827 # number of nop insts executed
> system.cpu1.iew.exec_refs 50376799 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 6999376 # Number of branches executed
> system.cpu1.iew.exec_stores 7108814 # Number of stores executed
> system.cpu1.iew.exec_rate 0.212079 # Inst execution rate
> system.cpu1.iew.wb_sent 85711710 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 53635909 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 29908204 # num instructions producing a value
> system.cpu1.iew.wb_consumers 53361522 # num instructions consuming a value
1516,1517c1516,1517
< system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.131217 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.560483 # average fanout of values written-back
1519,1524c1519,1524
< system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 16119527 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 880613 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 311377 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 111524050 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.431703 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.400207 # Number of insts commited each cycle
1526,1534c1526,1534
< system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 94787660 84.99% 84.99% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 8229182 7.38% 92.37% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 2114661 1.90% 94.27% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 1254724 1.13% 95.39% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1244333 1.12% 96.51% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 567856 0.51% 97.02% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 997712 0.89% 97.91% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 503621 0.45% 98.36% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 1824301 1.64% 100.00% # Number of insts commited each cycle
1538,1540c1538,1540
< system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 38058920 # Number of instructions committed
< system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 111524050 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 38058618 # Number of instructions committed
> system.cpu1.commit.committedOps 48145315 # Number of ops (including micro ops) committed
1542,1545c1542,1545
< system.cpu1.commit.refs 16590474 # Number of memory references committed
< system.cpu1.commit.loads 9752596 # Number of loads committed
< system.cpu1.commit.membars 190088 # Number of memory barriers committed
< system.cpu1.commit.branches 5966646 # Number of branches committed
---
> system.cpu1.commit.refs 16590369 # Number of memory references committed
> system.cpu1.commit.loads 9752527 # Number of loads committed
> system.cpu1.commit.membars 190082 # Number of memory barriers committed
> system.cpu1.commit.branches 5966603 # Number of branches committed
1547,1549c1547,1549
< system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 534484 # Number of function calls committed.
< system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached
---
> system.cpu1.commit.int_insts 42681078 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 534481 # Number of function calls committed.
> system.cpu1.commit.bw_lim_events 1824301 # number cycles where commit BW limit reached
1551,1560c1551,1560
< system.cpu1.rob.rob_reads 172926580 # The number of ROB reads
< system.cpu1.rob.rob_writes 131236338 # The number of ROB writes
< system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 37989281 # Number of Instructions Simulated
< system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated
< system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads
---
> system.cpu1.rob.rob_reads 172920681 # The number of ROB reads
> system.cpu1.rob.rob_writes 131224345 # The number of ROB writes
> system.cpu1.timesIdled 1408365 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 294630855 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 1796488086 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 37988979 # Number of Instructions Simulated
> system.cpu1.committedOps 48075676 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 37988979 # Number of Instructions Simulated
> system.cpu1.cpi 10.759852 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 10.759852 # CPI: Total CPI of All Threads
1563,1573c1563,1573
< system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads
< system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes
< system.cpu1.icache.replacements 596801 # number of replacements
< system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use
< system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks.
---
> system.cpu1.int_regfile_reads 387889245 # number of integer regfile reads
> system.cpu1.int_regfile_writes 56198451 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 4879 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 18462900 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 405383 # number of misc regfile writes
> system.cpu1.icache.replacements 596769 # number of replacements
> system.cpu1.icache.tagsinuse 480.741673 # Cycle average of tags in use
> system.cpu1.icache.total_refs 7750669 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 597281 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 12.976587 # Average number of references to valid blocks.
1575,1614c1575,1614
< system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor
< system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy
< system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits
< system.cpu1.icache.overall_hits::total 7752714 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses
< system.cpu1.icache.overall_misses::total 641884 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked
---
> system.cpu1.icache.occ_blocks::cpu1.inst 480.741673 # Average occupied blocks per requestor
> system.cpu1.icache.occ_percent::cpu1.inst 0.938949 # Average percentage of cache occupancy
> system.cpu1.icache.occ_percent::total 0.938949 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 7750669 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 7750669 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 7750669 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 7750669 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 7750669 # number of overall hits
> system.cpu1.icache.overall_hits::total 7750669 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 641966 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 641966 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 641966 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 641966 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 641966 # number of overall misses
> system.cpu1.icache.overall_misses::total 641966 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8653423491 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 8653423491 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 8653423491 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 8653423491 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 8653423491 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 8653423491 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 8392635 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 8392635 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 8392635 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 8392635 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 8392635 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 8392635 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076492 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.076492 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076492 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.076492 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076492 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.076492 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.566661 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13479.566661 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13479.566661 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13479.566661 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 2249 # number of cycles access was blocked
1618c1618
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.630303 # average number of cycles each access was blocked
1622,1639c1622,1639
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44655 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 44655 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 44655 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 44655 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 44655 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 44655 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597311 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 597311 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 597311 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 597311 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 597311 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 597311 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076959992 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076959992 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076959992 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 7076959992 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076959992 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 7076959992 # number of overall MSHR miss cycles
1644,1655c1644,1655
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071158 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.071158 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071171 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.071171 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.071171 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency
1661,1665c1661,1665
< system.cpu1.dcache.replacements 360372 # number of replacements
< system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks.
---
> system.cpu1.dcache.replacements 360267 # number of replacements
> system.cpu1.dcache.tagsinuse 474.654017 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 12671092 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 360637 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 35.135308 # Average number of references to valid blocks.
1667,1743c1667,1743
< system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 97570 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94868 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 94868 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 12441592 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 12441592 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 12441592 # number of overall hits
< system.cpu1.dcache.overall_hits::total 12441592 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 400129 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 400129 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1556605 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1556605 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13952 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 13952 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10604 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 10604 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 1956734 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 1956734 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 1956734 # number of overall misses
< system.cpu1.dcache.overall_misses::total 1956734 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6110776000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 6110776000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61798994997 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 61798994997 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128780500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 128780500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 67909770997 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703766 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 8703766 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694560 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 5694560 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111522 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 111522 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105472 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 105472 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 14398326 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 14398326 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 14398326 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 14398326 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045972 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.045972 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273349 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.273349 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125105 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125105 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100539 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100539 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135900 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.135900 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked
---
> system.cpu1.dcache.occ_blocks::cpu1.data 474.654017 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.927059 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.927059 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 8304151 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 8304151 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 4137952 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 4137952 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97565 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 97565 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94853 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 94853 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 12442103 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 12442103 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 12442103 # number of overall hits
> system.cpu1.dcache.overall_hits::total 12442103 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 399179 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 399179 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1556589 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1556589 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13972 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 13972 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10605 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 10605 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 1955768 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 1955768 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 1955768 # number of overall misses
> system.cpu1.dcache.overall_misses::total 1955768 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6101251500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 6101251500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61874023496 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 61874023496 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129109000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 129109000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53792000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 53792000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 67975274996 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 67975274996 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 67975274996 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 67975274996 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703330 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 8703330 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694541 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 5694541 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111537 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 111537 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105458 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 105458 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 14397871 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 14397871 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 14397871 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 14397871 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045865 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.045865 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273348 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.273348 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125268 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125268 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100561 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100561 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135837 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.135837 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135837 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.135837 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9240.552534 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9240.552534 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.324375 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.324375 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 25344 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 13325 # number of cycles access was blocked
1745,1747c1745,1747
< system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked
---
> system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.610811 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 84.872611 # average number of cycles each access was blocked
1750,1767c1750,1767
< system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks
< system.cpu1.dcache.writebacks::total 324455 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses
---
> system.cpu1.dcache.writebacks::writebacks 324294 # number of writebacks
> system.cpu1.dcache.writebacks::total 324294 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171223 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 171223 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395128 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 1395128 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566351 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1566351 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566351 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1566351 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227956 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 227956 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161461 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 161461 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12522 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12522 # number of LoadLockedReq MSHR misses
1770,1793c1770,1795
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses
---
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 389417 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 389417 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 389417 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 389417 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2851782000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2851782000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5138031205 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5138031205 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88180500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88180500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32594000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32594000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989813205 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 7989813205 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989813205 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 7989813205 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691035962 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691035962 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026192 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026192 # mshr miss rate for ReadReq accesses
1796,1815c1798,1819
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency
---
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112268 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112268 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100514 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100514 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.027047 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.027047 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7042.045999 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7042.045999 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.905660 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.905660 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency
1837,1840c1841,1844
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 540139410201 # number of overall MSHR uncacheable cycles
1847c1851
< system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 41727 # number of quiesce instructions executed
1849c1853
< system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed