3,5c3,5
< sim_seconds 2.603317 # Number of seconds simulated
< sim_ticks 2603316759000 # Number of ticks simulated
< final_tick 2603316759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.593146 # Number of seconds simulated
> sim_ticks 2593146078000 # Number of ticks simulated
> final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 64170 # Simulator instruction rate (inst/s)
< host_op_rate 82590 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2648964509 # Simulator tick rate (ticks/s)
< host_mem_usage 407980 # Number of bytes of host memory used
< host_seconds 982.77 # Real time elapsed on the host
< sim_insts 63063787 # Number of instructions simulated
< sim_ops 81167171 # Number of ops (including micro ops) simulated
---
> host_inst_rate 66425 # Simulator instruction rate (inst/s)
> host_op_rate 85503 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2731005239 # Simulator tick rate (ticks/s)
> host_mem_usage 409388 # Number of bytes of host memory used
> host_seconds 949.52 # Real time elapsed on the host
> sim_insts 63072130 # Number of instructions simulated
> sim_ops 81187111 # Number of ops (including micro ops) simulated
15c15
< system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory
17,26c17,27
< system.physmem.bytes_read::cpu0.inst 396352 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 4375860 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 425408 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 5260720 # Number of bytes read from this memory
< system.physmem.bytes_read::total 131570852 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 396352 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 425408 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4284288 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory
29c30
< system.physmem.bytes_written::total 7313424 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory
31c32
< system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory
33,39c34,41
< system.physmem.num_reads::cpu0.inst 6193 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 68445 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 6647 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 82225 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15302357 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 66942 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory
42,44c44,46
< system.physmem.num_writes::total 824226 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 46521626 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.dtb.walker 320 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s)
46,61c48,64
< system.physmem.bw_read::cpu0.inst 152249 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 1680879 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 163410 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 2020776 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 50539702 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 152249 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 163410 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 315659 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1645704 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu1.data 1157038 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2809272 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1645704 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 46521626 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 320 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s)
63,109c66,113
< system.physmem.bw_total::cpu0.inst 152249 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 1687409 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 163410 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 3177814 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53348973 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15302357 # Total number of read requests seen
< system.physmem.writeReqs 824226 # Total number of write requests seen
< system.physmem.cpureqs 284853 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 979350848 # Total number of bytes read from memory
< system.physmem.bytesWritten 52750464 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 131570852 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7313424 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 375 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 14171 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 956419 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 956744 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 956349 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 956561 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 956521 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 956118 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 955968 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 956063 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 957003 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 956395 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 956361 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 956664 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 956312 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 956494 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 956128 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 955882 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 50798 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 51080 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 50753 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 50993 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 51913 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 51591 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 51530 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 52149 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 51821 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 51633 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 51817 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 51645 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 51480 # Track writes on a per bank basis
---
> system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15302381 # Total number of read requests seen
> system.physmem.writeReqs 824191 # Total number of write requests seen
> system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 979352384 # Total number of bytes read from memory
> system.physmem.bytesWritten 52748224 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis
111,112c115,116
< system.physmem.numWrRetry 1152088 # Number of times wr buffer was full causing retry
< system.physmem.totGap 2603315545500 # Total gap between requests
---
> system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry
> system.physmem.totGap 2593144762500 # Total gap between requests
119c123
< system.physmem.readPktSize::6 163436 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 163460 # Categorize read packet sizes
124c128
< system.physmem.writePktSize::2 1909372 # categorize write packet sizes
---
> system.physmem.writePktSize::2 1907771 # categorize write packet sizes
128c132
< system.physmem.writePktSize::6 66942 # categorize write packet sizes
---
> system.physmem.writePktSize::6 66907 # categorize write packet sizes
137c141
< system.physmem.neitherpktsize::6 14171 # categorize neither packet sizes
---
> system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes
140,156c144,160
< system.physmem.rdQLenPdf::0 15151636 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 94017 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 8640 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 3524 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2842 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2641 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2454 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2030 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1454 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1352 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1387 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 6499 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 9632 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 13082 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 603 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see
159c163
< system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
173,204c177,208
< system.physmem.wrQLenPdf::0 3194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3392 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 3540 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 3651 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 3816 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 4008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 4231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 4426 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 4620 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 35836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 35835 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 35835 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 32642 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 32444 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 32296 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 32185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 32020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 31828 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 31605 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 31410 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 31216 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see
206,211c210,215
< system.physmem.totQLat 48061683883 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 322412499883 # Sum of mem lat for all requests
< system.physmem.totBusLat 61207928000 # Total cycles spent in databus access
< system.physmem.totBankLat 213142888000 # Total cycles spent in bank access
< system.physmem.avgQLat 3140.88 # Average queueing delay per request
< system.physmem.avgBankLat 13929.10 # Average bank access latency per request
---
> system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests
> system.physmem.totBusLat 61208184000 # Total cycles spent in databus access
> system.physmem.totBankLat 213133396000 # Total cycles spent in bank access
> system.physmem.avgQLat 3128.25 # Average queueing delay per request
> system.physmem.avgBankLat 13928.42 # Average bank access latency per request
213,217c217,221
< system.physmem.avgMemAccLat 21069.98 # Average memory access latency
< system.physmem.avgRdBW 376.19 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 21056.67 # Average memory access latency
> system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s
219c223
< system.physmem.busUtil 2.48 # Data bus utilization in percentage
---
> system.physmem.busUtil 2.49 # Data bus utilization in percentage
221,223c225,227
< system.physmem.avgWrQLen 11.94 # Average write queue length over time
< system.physmem.readRowHits 15253098 # Number of row buffer hits during reads
< system.physmem.writeRowHits 789391 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 10.88 # Average write queue length over time
> system.physmem.readRowHits 15253448 # Number of row buffer hits during reads
> system.physmem.writeRowHits 789566 # Number of row buffer hits during writes
225,226c229,230
< system.physmem.writeRowHitRate 95.77 # Row buffer hit rate for writes
< system.physmem.avgGap 161430.08 # Average gap between requests
---
> system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes
> system.physmem.avgGap 160799.50 # Average gap between requests
238c242
< system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
---
> system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s)
241c245
< system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
---
> system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s)
244,249c248,253
< system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
< system.l2c.replacements 73153 # number of replacements
< system.l2c.tagsinuse 53083.361452 # Cycle average of tags in use
< system.l2c.total_refs 1922203 # Total number of references to valid blocks.
< system.l2c.sampled_refs 138333 # Sample count of references to valid blocks.
< system.l2c.avg_refs 13.895477 # Average number of references to valid blocks.
---
> system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s)
> system.l2c.replacements 73184 # number of replacements
> system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use
> system.l2c.total_refs 1906265 # Total number of references to valid blocks.
> system.l2c.sampled_refs 138351 # Sample count of references to valid blocks.
> system.l2c.avg_refs 13.778469 # Average number of references to valid blocks.
251,281c255,287
< system.l2c.occ_blocks::writebacks 37742.975736 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.dtb.walker 6.244346 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.itb.walker 0.876765 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.inst 4208.985983 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 2954.129199 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.dtb.walker 11.276001 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.inst 4048.165548 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 4110.707874 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.575912 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.dtb.walker 0.000095 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.inst 0.064224 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.data 0.045076 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.dtb.walker 0.000172 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.inst 0.061770 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.data 0.062724 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.809988 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.dtb.walker 35828 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 5516 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 398518 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 165446 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 53941 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 6316 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 614017 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 202060 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1481642 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 584379 # number of Writeback hits
< system.l2c.Writeback_hits::total 584379 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 1214 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1952 # number of UpgradeReq hits
---
> system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.inst 0.064179 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.data 0.045171 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.dtb.walker 0.000171 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.inst 0.061934 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.data 0.062833 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.810185 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.dtb.walker 33579 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 4963 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 393016 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 165084 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 53008 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 6038 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 608232 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 201468 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1465388 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 583960 # number of Writeback hits
> system.l2c.Writeback_hits::total 583960 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 1107 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 848 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 1955 # number of UpgradeReq hits
283,306c289,312
< system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 47923 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 58901 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 106824 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 35828 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 5516 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 398518 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 213369 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 53941 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 6316 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 614017 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 260961 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1588466 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 35828 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 5516 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 398518 # number of overall hits
< system.l2c.overall_hits::cpu0.data 213369 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 53941 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 6316 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 614017 # number of overall hits
< system.l2c.overall_hits::cpu1.data 260961 # number of overall hits
< system.l2c.overall_hits::total 1588466 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses
---
> system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 368 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 47823 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 59123 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 106946 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 33579 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4963 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 393016 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 212907 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 53008 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 6038 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 608232 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 260591 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1572334 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 33579 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4963 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 393016 # number of overall hits
> system.l2c.overall_hits::cpu0.data 212907 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 53008 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 6038 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 608232 # number of overall hits
> system.l2c.overall_hits::cpu1.data 260591 # number of overall hits
> system.l2c.overall_hits::total 1572334 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses
308,323c314,330
< system.l2c.ReadReq_misses::cpu0.inst 6067 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 6359 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 25310 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 5733 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 4361 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 10094 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 775 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 597 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1372 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 63477 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 77252 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 140729 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu0.inst 6056 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 6345 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 6633 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 6362 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 25428 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 5684 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 4404 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 10088 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 773 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 585 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1358 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 63519 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 77106 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 140625 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses
325,331c332,339
< system.l2c.demand_misses::cpu0.inst 6067 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 69836 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 6609 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 83496 # number of demand (read+write) misses
< system.l2c.demand_misses::total 166039 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 6056 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 69864 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 6633 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 83468 # number of demand (read+write) misses
> system.l2c.demand_misses::total 166053 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses
333,339c341,348
< system.l2c.overall_misses::cpu0.inst 6067 # number of overall misses
< system.l2c.overall_misses::cpu0.data 69836 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 6609 # number of overall misses
< system.l2c.overall_misses::cpu1.data 83496 # number of overall misses
< system.l2c.overall_misses::total 166039 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 935000 # number of ReadReq miss cycles
---
> system.l2c.overall_misses::cpu0.inst 6056 # number of overall misses
> system.l2c.overall_misses::cpu0.data 69864 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 6633 # number of overall misses
> system.l2c.overall_misses::cpu1.data 83468 # number of overall misses
> system.l2c.overall_misses::total 166053 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1175500 # number of ReadReq miss cycles
341,356c350,366
< system.l2c.ReadReq_miss_latency::cpu0.inst 317714000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 346268999 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1088500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 363822000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 365563000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1395509499 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 9087986 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 11973500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 21061486 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 478000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3102500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 3580500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 3187413984 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 4286901491 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 7474315475 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 935000 # number of demand (read+write) miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.inst 320358500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 344253498 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1038500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 122500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 371653000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 369594500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1408313998 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 9084989 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 12192500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 21277489 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2932000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 3523000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 3155374488 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 4272368491 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 7427742979 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 1175500 # number of demand (read+write) miss cycles
358,364c368,375
< system.l2c.demand_miss_latency::cpu0.inst 317714000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 3533682983 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 1088500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 363822000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 4652464491 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 8869824974 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 935000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 320358500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 3499627986 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 1038500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 371653000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 4641962991 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 8836056977 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 1175500 # number of overall miss cycles
366,443c377,458
< system.l2c.overall_miss_latency::cpu0.inst 317714000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 3533682983 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 1088500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 363822000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 4652464491 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 8869824974 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 35841 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 5518 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 404585 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 171805 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 53957 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 6316 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 620626 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 208304 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1506952 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 584379 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 584379 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 6947 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5099 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 12046 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 984 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 753 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1737 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 111400 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 136153 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 247553 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 35841 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 5518 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 404585 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 283205 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 53957 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 6316 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 620626 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 344457 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1754505 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 35841 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 5518 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 404585 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 283205 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 53957 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 6316 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 620626 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 344457 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1754505 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000363 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000362 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.014996 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.037013 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000297 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.010649 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.029975 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.016795 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.825248 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855266 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.837955 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787602 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.792829 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.789868 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.569811 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.567391 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.568480 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000363 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.000362 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.014996 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.246592 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000297 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.010649 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.242399 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.094636 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000363 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.000362 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.014996 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.246592 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000297 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.010649 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.242399 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.094636 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 71923.076923 # average ReadReq miss latency
---
> system.l2c.overall_miss_latency::cpu0.inst 320358500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 3499627986 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 1038500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 122500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 371653000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 4641962991 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 8836056977 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 33593 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 4965 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 399072 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 171429 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 53023 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 6039 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 614865 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 207830 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1490816 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 583960 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 583960 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 6791 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5252 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 12043 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 744 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1726 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 111342 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 136229 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 247571 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 33593 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 4965 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 399072 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 282771 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 53023 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 6039 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 614865 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 344059 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1738387 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 33593 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 4965 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 399072 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 282771 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 53023 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 6039 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 614865 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 344059 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1738387 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000403 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.015175 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.037012 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000166 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.010788 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.030612 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.017056 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.836990 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.838538 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.837665 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787169 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.786290 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.786790 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.570486 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.566003 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.568019 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.000403 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.015175 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.247069 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.000166 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.010788 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.242598 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.095521 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.000403 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.015175 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.247069 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.000166 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.010788 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.242598 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.095521 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average ReadReq miss latency
445,460c460,476
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52367.562222 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 54453.373015 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68031.250000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55049.477985 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 58546.284433 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 55136.685065 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1585.206000 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2745.585875 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2086.535169 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 616.774194 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5196.817420 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 2609.693878 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 50213.683444 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55492.433736 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 53111.408985 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 71923.076923 # average overall miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52899.356011 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 54255.870449 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 122500 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56030.906076 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 58094.074191 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 55384.379346 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1598.344300 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2768.505904 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2109.188045 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 764.553687 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5011.965812 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 2594.256259 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49676.073112 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55409.027715 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 52819.505628 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average overall miss latency
462,468c478,485
< system.l2c.demand_avg_miss_latency::cpu0.inst 52367.562222 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 50599.733418 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68031.250000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 55049.477985 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 55720.806877 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 53420.130054 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 71923.076923 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 52899.356011 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 50092.007128 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 122500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 56030.906076 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 55613.684178 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 53212.269438 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average overall miss latency
470,475c487,493
< system.l2c.overall_avg_miss_latency::cpu0.inst 52367.562222 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 50599.733418 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68031.250000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 55049.477985 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 55720.806877 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 53420.130054 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.inst 52899.356011 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 50092.007128 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 122500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 56030.906076 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 55613.684178 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 53212.269438 # average overall miss latency
484,501c502,519
< system.l2c.writebacks::writebacks 66942 # number of writebacks
< system.l2c.writebacks::total 66942 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses
---
> system.l2c.writebacks::writebacks 66907 # number of writebacks
> system.l2c.writebacks::total 66907 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses
503,518c521,537
< system.l2c.ReadReq_mshr_misses::cpu0.inst 6063 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 6321 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 6602 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 6220 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 25237 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 5733 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 4361 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 10094 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 775 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 597 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1372 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 63477 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 77252 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 140729 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 6053 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 6306 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 6625 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 6337 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 25353 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 5684 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 4404 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 10088 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 773 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 585 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1358 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 63519 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 77106 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 140625 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses
520,526c539,546
< system.l2c.demand_mshr_misses::cpu0.inst 6063 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 69798 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 6602 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 83472 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 165966 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 6053 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 69825 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 6625 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 83443 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 165978 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses
528,534c548,555
< system.l2c.overall_mshr_misses::cpu0.inst 6063 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 69798 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 6602 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 83472 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 165966 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 769524 # number of ReadReq MSHR miss cycles
---
> system.l2c.overall_mshr_misses::cpu0.inst 6053 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 69825 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 6625 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 83443 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 165978 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 998025 # number of ReadReq MSHR miss cycles
536,551c557,573
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 240985728 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 264114875 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 885028 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 280065375 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 285358123 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 1072271655 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57814013 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44321751 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 102135764 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7773761 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5990089 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 13763850 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2401729527 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3326209366 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 5727938893 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 769524 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 243809691 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 262215347 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 849526 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 109502 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 287575375 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 287912849 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 1083563317 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57255976 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44756275 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 102012251 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7762758 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5877575 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 13640333 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2369346199 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3313598990 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 5682945189 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 998025 # number of demand (read+write) MSHR miss cycles
553,559c575,582
< system.l2c.demand_mshr_miss_latency::cpu0.inst 240985728 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2665844402 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 885028 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 280065375 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 3611567489 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 6800210548 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 769524 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 243809691 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2631561546 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 849526 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 109502 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 287575375 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 3601511839 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 6766508506 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 998025 # number of overall MSHR miss cycles
561,613c584,640
< system.l2c.overall_mshr_miss_latency::cpu0.inst 240985728 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2665844402 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 885028 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 280065375 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 3611567489 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 6800210548 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4694165 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330499053 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1876066 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154911224998 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 167248294282 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062750734 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17129759420 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 18192510154 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4694165 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13393249787 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1876066 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172040984418 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 185440804436 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036792 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029860 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.016747 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.825248 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855266 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.837955 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787602 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.792829 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.789868 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569811 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567391 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.568480 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.246458 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.242329 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.094594 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.246458 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.242329 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.094594 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average ReadReq mshr miss latency
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 243809691 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2631561546 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 849526 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 109502 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 287575375 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 3601511839 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 6766508506 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4558163 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330302064 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1815064 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154912119500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 167248794791 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062521236 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17116054868 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 18178576104 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4558163 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13392823300 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1815064 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172028174368 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 185427370895 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036785 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030491 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.017006 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.836990 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.838538 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.837665 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787169 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786290 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786790 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570486 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566003 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.568019 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.095478 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.095478 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average ReadReq mshr miss latency
615,630c642,658
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41783.716975 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45877.511736 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 42488.079209 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10084.425781 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10163.208209 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10118.462849 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10030.659355 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.649916 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.960641 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37836.216693 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43056.611686 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40701.908583 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41581.881859 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45433.619852 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 42739.057192 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.183673 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10162.641916 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.237411 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.377749 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.136752 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10044.427835 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37301.377525 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42974.593287 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40412.054677 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency
632,638c660,667
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency
640,645c669,675
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency
668,671c698,701
< system.cpu0.dtb.read_hits 9063545 # DTB read hits
< system.cpu0.dtb.read_misses 36220 # DTB read misses
< system.cpu0.dtb.write_hits 5280653 # DTB write hits
< system.cpu0.dtb.write_misses 6480 # DTB write misses
---
> system.cpu0.dtb.read_hits 9014303 # DTB read hits
> system.cpu0.dtb.read_misses 34965 # DTB read misses
> system.cpu0.dtb.write_hits 5253714 # DTB write hits
> system.cpu0.dtb.write_misses 6399 # DTB write misses
676,678c706,708
< system.cpu0.dtb.flush_entries 2158 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1224 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 336 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch
680,682c710,712
< system.cpu0.dtb.perms_faults 569 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 9099765 # DTB read accesses
< system.cpu0.dtb.write_accesses 5287133 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 9049268 # DTB read accesses
> system.cpu0.dtb.write_accesses 5260113 # DTB write accesses
684,688c714,718
< system.cpu0.dtb.hits 14344198 # DTB hits
< system.cpu0.dtb.misses 42700 # DTB misses
< system.cpu0.dtb.accesses 14386898 # DTB accesses
< system.cpu0.itb.inst_hits 4425189 # ITB inst hits
< system.cpu0.itb.inst_misses 5562 # ITB inst misses
---
> system.cpu0.dtb.hits 14268017 # DTB hits
> system.cpu0.dtb.misses 41364 # DTB misses
> system.cpu0.dtb.accesses 14309381 # DTB accesses
> system.cpu0.itb.inst_hits 4294311 # ITB inst hits
> system.cpu0.itb.inst_misses 5261 # ITB inst misses
697c727
< system.cpu0.itb.flush_entries 1395 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB
701c731
< system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions
704,708c734,738
< system.cpu0.itb.inst_accesses 4430751 # ITB inst accesses
< system.cpu0.itb.hits 4425189 # DTB hits
< system.cpu0.itb.misses 5562 # DTB misses
< system.cpu0.itb.accesses 4430751 # DTB accesses
< system.cpu0.numCycles 69436793 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses
> system.cpu0.itb.hits 4294311 # DTB hits
> system.cpu0.itb.misses 5261 # DTB misses
> system.cpu0.itb.accesses 4299572 # DTB accesses
> system.cpu0.numCycles 69013505 # number of cpu cycles simulated
711,715c741,745
< system.cpu0.BPredUnit.lookups 6232893 # Number of BP lookups
< system.cpu0.BPredUnit.condPredicted 4743306 # Number of conditional branches predicted
< system.cpu0.BPredUnit.condIncorrect 327822 # Number of conditional branches incorrect
< system.cpu0.BPredUnit.BTBLookups 3788300 # Number of BTB lookups
< system.cpu0.BPredUnit.BTBHits 3047807 # Number of BTB hits
---
> system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups
> system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted
> system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect
> system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups
> system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits
717,736c747,766
< system.cpu0.BPredUnit.usedRAS 701189 # Number of times the RAS was used to get a target.
< system.cpu0.BPredUnit.RASInCorrect 31986 # Number of incorrect RAS predictions.
< system.cpu0.fetch.icacheStallCycles 12165372 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 33223009 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 6232893 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 3748996 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 7801748 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1579515 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 70495 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.BlockedCycles 21773574 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 5807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 55458 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 92257 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 4423471 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 173760 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 2652 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 43098147 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.994806 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.374305 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target.
> system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions.
> system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total)
738,746c768,776
< system.cpu0.fetch.rateDist::0 35304381 81.92% 81.92% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 609582 1.41% 83.33% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 823952 1.91% 85.24% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 710643 1.65% 86.89% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 795409 1.85% 88.74% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 570879 1.32% 90.06% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 720960 1.67% 91.73% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 375620 0.87% 92.61% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 3186721 7.39% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total)
750,795c780,825
< system.cpu0.fetch.rateDist::total 43098147 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.089764 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.478464 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 12694368 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 21733151 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 7021973 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 580158 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1068497 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 974425 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 66014 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 41440720 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 216131 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 1068497 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 13283568 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 5811502 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 13763022 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 6961604 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 2209954 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 40230567 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 2204 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 441496 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 1232571 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.FullRegisterEvents 70 # Number of times there has been no free registers
< system.cpu0.rename.RenamedOperands 40628697 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 181762207 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 181727693 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 34514 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 31673882 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 8954814 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 460934 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 417253 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 5454618 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 7893877 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 5899231 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1129288 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 1250491 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 37987189 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 942287 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 38211306 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 88088 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 6766776 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 14417426 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 253739 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 43098147 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.886611 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.498890 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers
> system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle
797,805c827,835
< system.cpu0.iq.issued_per_cycle::0 27429044 63.64% 63.64% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 6069688 14.08% 77.73% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 3249267 7.54% 85.27% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2519397 5.85% 91.11% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2120550 4.92% 96.03% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 959758 2.23% 98.26% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 504062 1.17% 99.43% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 191517 0.44% 99.87% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 54864 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle
809c839
< system.cpu0.iq.issued_per_cycle::total 43098147 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle
811,841c841,871
< system.cpu0.iq.fu_full::IntAlu 25519 2.38% 2.38% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 464 0.04% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 839951 78.37% 80.80% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 205830 19.20% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available
844,875c874,905
< system.cpu0.iq.FU_type_0::No_OpClass 52084 0.14% 0.14% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 22953142 60.07% 60.21% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 49969 0.13% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 683 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 9542960 24.97% 85.31% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5612439 14.69% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued
878,890c908,920
< system.cpu0.iq.FU_type_0::total 38211306 # Type of FU issued
< system.cpu0.iq.rate 0.550303 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 1071764 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.028048 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 120714498 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 45704259 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 35275992 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 8506 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 4731 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 3909 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 39226540 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 4446 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 323503 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued
> system.cpu0.iq.rate 0.549915 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores
892,895c922,925
< system.cpu0.iew.lsq.thread0.squashedLoads 1474665 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 3677 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 13402 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 626328 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed
898,899c928,929
< system.cpu0.iew.lsq.thread0.rescheduledLoads 2149439 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked
901,917c931,947
< system.cpu0.iew.iewSquashCycles 1068497 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 4177933 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 101495 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 39049116 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 95858 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 7893877 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 5899231 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 616112 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 40709 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 3360 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 13402 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 173604 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 128122 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 301726 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 37794024 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 9381421 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 417282 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute
919,927c949,957
< system.cpu0.iew.exec_nop 119640 # number of nop insts executed
< system.cpu0.iew.exec_refs 14935051 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 4997979 # Number of branches executed
< system.cpu0.iew.exec_stores 5553630 # Number of stores executed
< system.cpu0.iew.exec_rate 0.544294 # Inst execution rate
< system.cpu0.iew.wb_sent 37576425 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 35279901 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 18742857 # num instructions producing a value
< system.cpu0.iew.wb_consumers 36023721 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 117654 # number of nop insts executed
> system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 4958494 # Number of branches executed
> system.cpu0.iew.exec_stores 5526390 # Number of stores executed
> system.cpu0.iew.exec_rate 0.544297 # Inst execution rate
> system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 18655901 # num instructions producing a value
> system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value
929,930c959,960
< system.cpu0.iew.wb_rate 0.508087 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.520292 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back
932,937c962,967
< system.cpu0.commit.commitSquashedInsts 6624150 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 688548 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 263048 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 42066039 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.760422 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.715065 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle
939,947c969,977
< system.cpu0.commit.committed_per_cycle::0 29990291 71.29% 71.29% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 5984334 14.23% 85.52% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 1979513 4.71% 90.23% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 1007903 2.40% 92.62% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 802639 1.91% 94.53% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 528288 1.26% 95.79% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 397543 0.95% 96.73% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 220589 0.52% 97.25% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1154939 2.75% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle
951,953c981,983
< system.cpu0.commit.committed_per_cycle::total 42066039 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 24262669 # Number of instructions committed
< system.cpu0.commit.committedOps 31987958 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 24264310 # Number of instructions committed
> system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed
955,958c985,988
< system.cpu0.commit.refs 11692115 # Number of memory references committed
< system.cpu0.commit.loads 6419212 # Number of loads committed
< system.cpu0.commit.membars 234468 # Number of memory barriers committed
< system.cpu0.commit.branches 4346825 # Number of branches committed
---
> system.cpu0.commit.refs 11698867 # Number of memory references committed
> system.cpu0.commit.loads 6423036 # Number of loads committed
> system.cpu0.commit.membars 234373 # Number of memory barriers committed
> system.cpu0.commit.branches 4346960 # Number of branches committed
960,962c990,992
< system.cpu0.commit.int_insts 28256367 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 500017 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1154939 # number cycles where commit BW limit reached
---
> system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 499893 # Number of function calls committed.
> system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached
964,1027c994,1057
< system.cpu0.rob.rob_reads 78638973 # The number of ROB reads
< system.cpu0.rob.rob_writes 78294863 # The number of ROB writes
< system.cpu0.timesIdled 365151 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 26338646 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 5137152930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 24181927 # Number of Instructions Simulated
< system.cpu0.committedOps 31907216 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 24181927 # Number of Instructions Simulated
< system.cpu0.cpi 2.871433 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.871433 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.348258 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.348258 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 176324047 # number of integer regfile reads
< system.cpu0.int_regfile_writes 35061690 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 912 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 47470625 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 527597 # number of misc regfile writes
< system.cpu0.icache.replacements 404775 # number of replacements
< system.cpu0.icache.tagsinuse 511.602715 # Cycle average of tags in use
< system.cpu0.icache.total_refs 3985323 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 405287 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 9.833335 # Average number of references to valid blocks.
< system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.occ_blocks::cpu0.inst 511.602715 # Average occupied blocks per requestor
< system.cpu0.icache.occ_percent::cpu0.inst 0.999224 # Average percentage of cache occupancy
< system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 3985323 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 3985323 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 3985323 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 3985323 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 3985323 # number of overall hits
< system.cpu0.icache.overall_hits::total 3985323 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 438012 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 438012 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 438012 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 438012 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 438012 # number of overall misses
< system.cpu0.icache.overall_misses::total 438012 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5943655997 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 5943655997 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 5943655997 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 5943655997 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 5943655997 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 5943655997 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 4423335 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 4423335 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 4423335 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 4423335 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 4423335 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 4423335 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099023 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.099023 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099023 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.099023 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099023 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.099023 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13569.619090 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13569.619090 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13569.619090 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13569.619090 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 2262 # number of cycles access was blocked
---
> system.cpu0.rob.rob_reads 77875275 # The number of ROB reads
> system.cpu0.rob.rob_writes 77410136 # The number of ROB writes
> system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 24183568 # Number of Instructions Simulated
> system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated
> system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads
> system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 906 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes
> system.cpu0.icache.replacements 399233 # number of replacements
> system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use
> system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks.
> system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor
> system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy
> system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits
> system.cpu0.icache.overall_hits::total 3861943 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses
> system.cpu0.icache.overall_misses::total 430668 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 4292611 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 4292611 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100328 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.100328 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100328 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.100328 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100328 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.100328 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked
1029c1059
< system.cpu0.icache.blocked::no_mshrs 131 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked
1031c1061
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.267176 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked
1035,1068c1065,1098
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32710 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 32710 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 32710 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 32710 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 32710 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 32710 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405302 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 405302 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 405302 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 405302 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 405302 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 405302 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4852452498 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 4852452498 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4852452498 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 4852452498 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4852452498 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 4852452498 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7399000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7399000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7399000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 7399000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091628 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.091628 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.091628 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11972.436598 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 30901 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 30901 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399767 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 399767 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 399767 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 399767 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 399767 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 399767 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4790784994 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 4790784994 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4790784994 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency
1074,1160c1104,1190
< system.cpu0.dcache.replacements 274922 # number of replacements
< system.cpu0.dcache.tagsinuse 477.004191 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 9558639 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 275434 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 34.703918 # Average number of references to valid blocks.
< system.cpu0.dcache.warmup_cycle 36505000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.occ_blocks::cpu0.data 477.004191 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.931649 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.931649 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 5930824 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 5930824 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3236437 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3236437 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174250 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 174250 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171562 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 171562 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 9167261 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 9167261 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 9167261 # number of overall hits
< system.cpu0.dcache.overall_hits::total 9167261 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 390293 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 390293 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1580955 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1580955 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7756 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 7756 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 1971248 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1971248 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1971248 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1971248 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5368045500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5368045500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61391771868 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 61391771868 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88103500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 88103500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50615000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 50615000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 66759817368 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 66759817368 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 66759817368 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 66759817368 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 6321117 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 6321117 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4817392 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4817392 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183153 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 183153 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179318 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 179318 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 11138509 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 11138509 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 11138509 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 11138509 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061744 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.061744 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328177 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.328177 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048610 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048610 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043253 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043253 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176976 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.176976 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176976 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.176976 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13753.886183 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13753.886183 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38832.080526 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 38832.080526 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9895.933955 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9895.933955 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6525.915420 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6525.915420 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 33866.777477 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 33866.777477 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 7897 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 2466 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 585 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 72 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.499145 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 34.250000 # average number of cycles each access was blocked
---
> system.cpu0.dcache.replacements 274937 # number of replacements
> system.cpu0.dcache.tagsinuse 481.181813 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 9516256 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 275449 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 34.548160 # Average number of references to valid blocks.
> system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 171542 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 9125541 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 9125541 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 9125541 # number of overall hits
> system.cpu0.dcache.overall_hits::total 9125541 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 390766 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 390766 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1582021 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1582021 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8872 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 8872 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7743 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 7743 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1972787 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1972787 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1972787 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1972787 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5377265000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5377265000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60881411847 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 60881411847 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88222500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 88222500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50475500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 50475500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 66258676847 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 66258676847 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 66258676847 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 66258676847 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 6277949 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182538 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 182538 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179285 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 179285 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 11098328 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 11098328 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 11098328 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 11098328 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062244 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.062244 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328194 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.328194 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048604 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048604 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043188 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043188 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177755 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.177755 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177755 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.177755 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13760.831290 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 8283 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 3369 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 596 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.897651 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 41.085366 # average number of cycles each access was blocked
1163,1232c1193,1258
< system.cpu0.dcache.writebacks::writebacks 255626 # number of writebacks
< system.cpu0.dcache.writebacks::total 255626 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201523 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 201523 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449784 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1449784 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651307 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1651307 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651307 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1651307 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188770 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 188770 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131171 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 131171 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8435 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8435 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7755 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 7755 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 319941 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 319941 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 319941 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 319941 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2338858500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2338858500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4087753491 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4087753491 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66408500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66408500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 35107000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 35107000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426611991 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 6426611991 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426611991 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 6426611991 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431962000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431962000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199718891 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199718891 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631680891 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631680891 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029863 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029863 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027229 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027229 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046054 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046054 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043247 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043247 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12389.990465 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12389.990465 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31163.545990 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31163.545990 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7872.969769 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7872.969769 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4527.014829 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4527.014829 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
< system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks
> system.cpu0.dcache.writebacks::total 255577 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency
1242,1245c1268,1271
< system.cpu1.dtb.read_hits 43093620 # DTB read hits
< system.cpu1.dtb.read_misses 44212 # DTB read misses
< system.cpu1.dtb.write_hits 7019560 # DTB write hits
< system.cpu1.dtb.write_misses 11765 # DTB write misses
---
> system.cpu1.dtb.read_hits 43030291 # DTB read hits
> system.cpu1.dtb.read_misses 42638 # DTB read misses
> system.cpu1.dtb.write_hits 6991861 # DTB write hits
> system.cpu1.dtb.write_misses 11867 # DTB write misses
1250,1252c1276,1278
< system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 3591 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch
1254,1256c1280,1282
< system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 43137832 # DTB read accesses
< system.cpu1.dtb.write_accesses 7031325 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 43072929 # DTB read accesses
> system.cpu1.dtb.write_accesses 7003728 # DTB write accesses
1258,1262c1284,1288
< system.cpu1.dtb.hits 50113180 # DTB hits
< system.cpu1.dtb.misses 55977 # DTB misses
< system.cpu1.dtb.accesses 50169157 # DTB accesses
< system.cpu1.itb.inst_hits 7945263 # ITB inst hits
< system.cpu1.itb.inst_misses 6054 # ITB inst misses
---
> system.cpu1.dtb.hits 50022152 # DTB hits
> system.cpu1.dtb.misses 54505 # DTB misses
> system.cpu1.dtb.accesses 50076657 # DTB accesses
> system.cpu1.itb.inst_hits 7786412 # ITB inst hits
> system.cpu1.itb.inst_misses 5635 # ITB inst misses
1271c1297
< system.cpu1.itb.flush_entries 1580 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB
1275c1301
< system.cpu1.itb.perms_faults 1618 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions
1278,1282c1304,1308
< system.cpu1.itb.inst_accesses 7951317 # ITB inst accesses
< system.cpu1.itb.hits 7945263 # DTB hits
< system.cpu1.itb.misses 6054 # DTB misses
< system.cpu1.itb.accesses 7951317 # DTB accesses
< system.cpu1.numCycles 409430571 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses
> system.cpu1.itb.hits 7786412 # DTB hits
> system.cpu1.itb.misses 5635 # DTB misses
> system.cpu1.itb.accesses 7792047 # DTB accesses
> system.cpu1.numCycles 409024249 # number of cpu cycles simulated
1285,1289c1311,1315
< system.cpu1.BPredUnit.lookups 9152257 # Number of BP lookups
< system.cpu1.BPredUnit.condPredicted 7432560 # Number of conditional branches predicted
< system.cpu1.BPredUnit.condIncorrect 466867 # Number of conditional branches incorrect
< system.cpu1.BPredUnit.BTBLookups 6195424 # Number of BTB lookups
< system.cpu1.BPredUnit.BTBHits 5148293 # Number of BTB hits
---
> system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups
> system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted
> system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect
> system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups
> system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits
1291,1310c1317,1336
< system.cpu1.BPredUnit.usedRAS 835215 # Number of times the RAS was used to get a target.
< system.cpu1.BPredUnit.RASInCorrect 50625 # Number of incorrect RAS predictions.
< system.cpu1.fetch.icacheStallCycles 19713770 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 62254744 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 9152257 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 5983508 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 13632356 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 3573599 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 74747 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.BlockedCycles 78115877 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 5836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 48120 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 142516 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 7943235 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 563949 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 3459 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 114180028 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.668662 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.999663 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target.
> system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions.
> system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total)
1312,1320c1338,1346
< system.cpu1.fetch.rateDist::0 100555609 88.07% 88.07% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 838988 0.73% 88.80% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 1011000 0.89% 89.69% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 1744900 1.53% 91.22% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 1443541 1.26% 92.48% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 605100 0.53% 93.01% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 1974563 1.73% 94.74% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 445551 0.39% 95.13% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 5560776 4.87% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total)
1324,1369c1350,1395
< system.cpu1.fetch.rateDist::total 114180028 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.022354 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.152052 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 21120325 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 77740288 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 12430171 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 543608 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 2345636 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 1176073 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 102892 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 72257305 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 341492 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 2345636 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 22356190 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 32102348 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 41268894 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 11643477 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 4463483 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 68190005 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 19565 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 695237 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 3171764 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.FullRegisterEvents 33722 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 71496605 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 312933263 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 312874076 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 59187 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 50205657 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 21290948 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 480351 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 419670 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 8129610 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 13049293 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 8227563 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 1078580 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 1518105 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 62664777 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 1204533 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 89464326 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 109059 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 14241211 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 38124625 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 284346 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 114180028 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.783537 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.520062 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle
1371,1379c1397,1405
< system.cpu1.iq.issued_per_cycle::0 83489742 73.12% 73.12% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 8670086 7.59% 80.71% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 4385231 3.84% 84.56% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 3749968 3.28% 87.84% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 10493751 9.19% 97.03% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 1975559 1.73% 98.76% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 1067200 0.93% 99.69% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 270053 0.24% 99.93% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 78438 0.07% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle
1383c1409
< system.cpu1.iq.issued_per_cycle::total 114180028 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle
1385,1415c1411,1441
< system.cpu1.iq.fu_full::IntAlu 28685 0.36% 0.36% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 990 0.01% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 7576734 95.92% 96.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 292663 3.71% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available
1419,1449c1445,1475
< system.cpu1.iq.FU_type_0::IntAlu 37676817 42.11% 42.46% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 61442 0.07% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.54% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.54% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.54% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.54% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 44006207 49.19% 91.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 7404070 8.28% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued
1452,1464c1478,1490
< system.cpu1.iq.FU_type_0::total 89464326 # Type of FU issued
< system.cpu1.iq.rate 0.218509 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 7899072 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.088293 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 301157769 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 78119517 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 54662771 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 14827 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 8100 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 97041573 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 7763 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 356788 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued
> system.cpu1.iq.rate 0.217987 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores
1466,1469c1492,1495
< system.cpu1.iew.lsq.thread0.squashedLoads 3051550 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 4387 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 17666 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 1202172 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed
1472,1473c1498,1499
< system.cpu1.iew.lsq.thread0.rescheduledLoads 31965367 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 692896 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked
1475,1491c1501,1517
< system.cpu1.iew.iewSquashCycles 2345636 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 24201399 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 366318 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 63975423 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 133542 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 13049293 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 8227563 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 893848 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 67557 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 17666 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 244185 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 171619 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 415804 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 87650825 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 43476570 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 1813501 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute
1493,1501c1519,1527
< system.cpu1.iew.exec_nop 106113 # number of nop insts executed
< system.cpu1.iew.exec_refs 50801692 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 7123929 # Number of branches executed
< system.cpu1.iew.exec_stores 7325122 # Number of stores executed
< system.cpu1.iew.exec_rate 0.214080 # Inst execution rate
< system.cpu1.iew.wb_sent 86821194 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 54669578 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 30455976 # num instructions producing a value
< system.cpu1.iew.wb_consumers 54432612 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 104288 # number of nop insts executed
> system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 7088545 # Number of branches executed
> system.cpu1.iew.exec_stores 7297390 # Number of stores executed
> system.cpu1.iew.exec_rate 0.213684 # Inst execution rate
> system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 30364436 # num instructions producing a value
> system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value
1503,1504c1529,1530
< system.cpu1.iew.wb_rate 0.133526 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.559517 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back
1506,1511c1532,1537
< system.cpu1.commit.commitSquashedInsts 14216299 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 920187 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 365862 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 111882823 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.440904 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.409715 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle
1513,1521c1539,1547
< system.cpu1.commit.committed_per_cycle::0 94662436 84.61% 84.61% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 8450873 7.55% 92.16% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 2228797 1.99% 94.15% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 1285384 1.15% 95.30% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1281795 1.15% 96.45% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 596967 0.53% 96.98% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 1010034 0.90% 97.88% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 539540 0.48% 98.37% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 1826997 1.63% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle
1525,1527c1551,1553
< system.cpu1.commit.committed_per_cycle::total 111882823 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 38951499 # Number of instructions committed
< system.cpu1.commit.committedOps 49329594 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 38958201 # Number of instructions committed
> system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed
1529,1532c1555,1558
< system.cpu1.commit.refs 17023134 # Number of memory references committed
< system.cpu1.commit.loads 9997743 # Number of loads committed
< system.cpu1.commit.membars 202380 # Number of memory barriers committed
< system.cpu1.commit.branches 6138522 # Number of branches committed
---
> system.cpu1.commit.refs 17027012 # Number of memory references committed
> system.cpu1.commit.loads 10000155 # Number of loads committed
> system.cpu1.commit.membars 202531 # Number of memory barriers committed
> system.cpu1.commit.branches 6139960 # Number of branches committed
1534,1536c1560,1562
< system.cpu1.commit.int_insts 43719778 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 556453 # Number of function calls committed.
< system.cpu1.commit.bw_lim_events 1826997 # number cycles where commit BW limit reached
---
> system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 556605 # Number of function calls committed.
> system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached
1538,1601c1564,1627
< system.cpu1.rob.rob_reads 172487010 # The number of ROB reads
< system.cpu1.rob.rob_writes 129525616 # The number of ROB writes
< system.cpu1.timesIdled 1423460 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 295250543 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 4796554837 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 38881860 # Number of Instructions Simulated
< system.cpu1.committedOps 49259955 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 38881860 # Number of Instructions Simulated
< system.cpu1.cpi 10.530118 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 10.530118 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.094966 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.094966 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 392568937 # number of integer regfile reads
< system.cpu1.int_regfile_writes 56802865 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 4926 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 81929191 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 429868 # number of misc regfile writes
< system.cpu1.icache.replacements 620724 # number of replacements
< system.cpu1.icache.tagsinuse 498.809985 # Cycle average of tags in use
< system.cpu1.icache.total_refs 7273497 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 621236 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 11.708106 # Average number of references to valid blocks.
< system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.occ_blocks::cpu1.inst 498.809985 # Average occupied blocks per requestor
< system.cpu1.icache.occ_percent::cpu1.inst 0.974238 # Average percentage of cache occupancy
< system.cpu1.icache.occ_percent::total 0.974238 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 7273497 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 7273497 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 7273497 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 7273497 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 7273497 # number of overall hits
< system.cpu1.icache.overall_hits::total 7273497 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 669686 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 669686 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 669686 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 669686 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 669686 # number of overall misses
< system.cpu1.icache.overall_misses::total 669686 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8966780496 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 8966780496 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 8966780496 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 8966780496 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 8966780496 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 8966780496 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 7943183 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 7943183 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 7943183 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 7943183 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 7943183 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 7943183 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084310 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.084310 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084310 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.084310 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084310 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.084310 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13389.529565 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13389.529565 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13389.529565 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13389.529565 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 2782 # number of cycles access was blocked
---
> system.cpu1.rob.rob_reads 171645222 # The number of ROB reads
> system.cpu1.rob.rob_writes 128401309 # The number of ROB writes
> system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 38888562 # Number of Instructions Simulated
> system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated
> system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads
> system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes
> system.cpu1.icache.replacements 614989 # number of replacements
> system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use
> system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks.
> system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor
> system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy
> system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits
> system.cpu1.icache.overall_hits::total 7122851 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses
> system.cpu1.icache.overall_misses::total 661583 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked
1603c1629
< system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked
1605c1631
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.266667 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked
1609,1642c1635,1668
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48404 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 48404 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 48404 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 48404 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 48404 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 48404 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 621282 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 621282 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 621282 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 621282 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 621282 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 621282 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328304997 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328304997 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328304997 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 7328304997 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328304997 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 7328304997 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078216 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.078216 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.078216 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11795.456809 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46050 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 46050 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 46050 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 46050 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 46050 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 46050 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615533 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 615533 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 615533 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 615533 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 615533 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 615533 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7269169496 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 7269169496 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7269169496 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 7269169496 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7269169496 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 7269169496 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079072 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.079072 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.079072 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency
1648,1734c1674,1760
< system.cpu1.dcache.replacements 363973 # number of replacements
< system.cpu1.dcache.tagsinuse 487.193831 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 13149320 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 364327 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 36.092082 # Average number of references to valid blocks.
< system.cpu1.dcache.warmup_cycle 70722416000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.occ_blocks::cpu1.data 487.193831 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.951550 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.951550 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 8614465 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 8614465 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 4290599 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 4290599 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105175 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 105175 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100810 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 100810 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 12905064 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 12905064 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 12905064 # number of overall hits
< system.cpu1.dcache.overall_hits::total 12905064 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 401162 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 401162 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1564756 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1564756 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14285 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 14285 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10913 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 10913 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 1965918 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 1965918 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 1965918 # number of overall misses
< system.cpu1.dcache.overall_misses::total 1965918 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6004176000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 6004176000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64721170014 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 64721170014 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132767500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 132767500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58656500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 58656500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 70725346014 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 70725346014 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 70725346014 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 70725346014 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 9015627 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 9015627 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 5855355 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 5855355 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119460 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 119460 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111723 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 111723 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 14870982 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 14870982 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 14870982 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 14870982 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044496 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.044496 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267235 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.267235 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119580 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119580 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097679 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097679 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132198 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.132198 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132198 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.132198 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14966.960978 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14966.960978 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41361.828946 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 41361.828946 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9294.189709 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9294.189709 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5374.919820 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5374.919820 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 35975.735516 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 35975.735516 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 27876 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 16218 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 3195 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 164 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.724883 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 98.890244 # average number of cycles each access was blocked
---
> system.cpu1.dcache.replacements 363437 # number of replacements
> system.cpu1.dcache.tagsinuse 485.666262 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 13086846 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 363802 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 35.972441 # Average number of references to valid blocks.
> system.cpu1.dcache.warmup_cycle 70623957000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.occ_blocks::cpu1.data 485.666262 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.948567 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.948567 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 8551806 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 8551806 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 4291461 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 4291461 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103521 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 103521 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100890 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 100890 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 12843267 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 12843267 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 12843267 # number of overall hits
> system.cpu1.dcache.overall_hits::total 12843267 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 401802 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 401802 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1565358 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1565358 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14225 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 14225 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10942 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 10942 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 1967160 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 1967160 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 1967160 # number of overall misses
> system.cpu1.dcache.overall_misses::total 1967160 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026246000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 6026246000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64613580018 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 64613580018 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131651000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 131651000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58881000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 58881000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 70639826018 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 70639826018 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 70639826018 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 70639826018 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 8953608 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 8953608 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 5856819 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 5856819 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 117746 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 117746 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111832 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 111832 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 14810427 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 14810427 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 14810427 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120811 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097843 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097843 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132823 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.132823 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132823 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.132823 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 3227 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.785559 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 89.315476 # average number of cycles each access was blocked
1737,1802c1763,1828
< system.cpu1.dcache.writebacks::writebacks 328753 # number of writebacks
< system.cpu1.dcache.writebacks::total 328753 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169362 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 169362 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401575 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 1401575 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1448 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1448 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570937 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1570937 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570937 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1570937 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231800 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 231800 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163181 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 163181 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12837 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12837 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10908 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 10908 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 394981 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 394981 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 394981 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 394981 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870952500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870952500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5312418211 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5312418211 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91073000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91073000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36840500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36840500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8183370711 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 8183370711 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8183370711 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 8183370711 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263287500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263287500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26961622519 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26961622519 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196224910019 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196224910019 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025711 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025711 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027869 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027869 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107459 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107459 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097634 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097634 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.026561 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.026561 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12385.472390 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12385.472390 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32555.372323 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32555.372323 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7094.570382 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7094.570382 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3377.383572 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3377.383572 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks
> system.cpu1.dcache.writebacks::total 328383 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231383 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 231383 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163131 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 163131 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10936 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 10936 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 394514 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 394514 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 394514 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 394514 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870368000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870368000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5301094210 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5301094210 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90117500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90117500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37009000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37009000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8171462210 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 8171462210 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8171462210 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 8171462210 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263515000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263515000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26947906394 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26947906394 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196211421394 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.026638 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.026638 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency
1824,1827c1850,1853
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1082331782222 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1082331782222 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles
1834c1860
< system.cpu0.kern.inst.quiesce 43796 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed
1836c1862
< system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed