7,11c7,11
< host_inst_rate 63716 # Simulator instruction rate (inst/s)
< host_op_rate 82290 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2641493756 # Simulator tick rate (ticks/s)
< host_mem_usage 388068 # Number of bytes of host memory used
< host_seconds 973.25 # Real time elapsed on the host
---
> host_inst_rate 53678 # Simulator instruction rate (inst/s)
> host_op_rate 69325 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2225327298 # Simulator tick rate (ticks/s)
> host_mem_usage 390932 # Number of bytes of host memory used
> host_seconds 1155.26 # Real time elapsed on the host
14,32c14,90
< system.physmem.bytes_read 131429540 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 1199424 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 10175696 # Number of bytes written to this memory
< system.physmem.num_reads 15128117 # Number of read requests responded to by this memory
< system.physmem.num_writes 868949 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 51123310 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 466551 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 3958130 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 55081440 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
< system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
< system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
< system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
> system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory
> system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s)
213a272
> system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses
215a275
> system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses
217a278
> system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses
219a281
> system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses
227a290
> system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses
235a299
> system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses
243a308
> system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency
245a311
> system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency
247a314
> system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency
249a317
> system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency
257a326
> system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency
265a335
> system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency
383a454
> system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses
385a457
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses
387a460
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses
389a463
> system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses
397a472
> system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses
405a481
> system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses
413a490
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency
415a493
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency
417a496
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency
419a499
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency
427a508
> system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency
435a517
> system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency
439a522
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
441a525
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
445a530
> system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
804a890
> system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses
805a892
> system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses
806a894
> system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses
807a896
> system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency
808a898
> system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency
809a900
> system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency
842a934
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses
843a936
> system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses
844a938
> system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses
845a940
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency
846a942
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency
847a944
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency
848a946
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
849a948
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
908a1008
> system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses
909a1010
> system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses
910a1012
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses
911a1014
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses
912a1016
> system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses
913a1018
> system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses
914a1020
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency
915a1022
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency
916a1024
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency
917a1026
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency
918a1028
> system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency
919a1030
> system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency
970a1082
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses
971a1084
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses
972a1086
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses
973a1088
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses
974a1090
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses
975a1092
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses
976a1094
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency
977a1096
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency
978a1098
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency
979a1100
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency
980a1102
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency
981a1104
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency
982a1106
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
983a1108
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
984a1110
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1337a1464
> system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses
1338a1466
> system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses
1339a1468
> system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses
1340a1470
> system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency
1341a1472
> system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency
1342a1474
> system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency
1375a1508
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses
1376a1510
> system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses
1377a1512
> system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses
1378a1514
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency
1379a1516
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency
1380a1518
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency
1381a1520
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1382a1522
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1441a1582
> system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses
1442a1584
> system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses
1443a1586
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses
1444a1588
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses
1445a1590
> system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses
1446a1592
> system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses
1447a1594
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency
1448a1596
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency
1449a1598
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency
1450a1600
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency
1451a1602
> system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency
1452a1604
> system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency
1505a1658
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses
1506a1660
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses
1507a1662
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses
1508a1664
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses
1509a1666
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses
1510a1668
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses
1511a1670
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency
1512a1672
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency
1513a1674
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency
1514a1676
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency
1515a1678
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1516a1680
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency
1517a1682
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency
1518a1684
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1519a1686
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1520a1688
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1540a1709
> system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1541a1711
> system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< host_inst_rate 63716 # Simulator instruction rate (inst/s)
< host_op_rate 82290 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2641493756 # Simulator tick rate (ticks/s)
< host_mem_usage 388068 # Number of bytes of host memory used
< host_seconds 973.25 # Real time elapsed on the host
---
> host_inst_rate 53678 # Simulator instruction rate (inst/s)
> host_op_rate 69325 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2225327298 # Simulator tick rate (ticks/s)
> host_mem_usage 390932 # Number of bytes of host memory used
> host_seconds 1155.26 # Real time elapsed on the host
14,32c14,90
< system.physmem.bytes_read 131429540 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 1199424 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 10175696 # Number of bytes written to this memory
< system.physmem.num_reads 15128117 # Number of read requests responded to by this memory
< system.physmem.num_writes 868949 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 51123310 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 466551 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 3958130 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 55081440 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
< system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
< system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
< system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
> system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory
> system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s)
213a272
> system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses
215a275
> system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses
217a278
> system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses
219a281
> system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses
227a290
> system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses
235a299
> system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses
243a308
> system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency
245a311
> system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency
247a314
> system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency
249a317
> system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency
257a326
> system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency
265a335
> system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency
383a454
> system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses
385a457
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses
387a460
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses
389a463
> system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses
397a472
> system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses
405a481
> system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses
413a490
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency
415a493
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency
417a496
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency
419a499
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency
427a508
> system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency
435a517
> system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency
439a522
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
441a525
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
445a530
> system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
804a890
> system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses
805a892
> system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses
806a894
> system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses
807a896
> system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency
808a898
> system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency
809a900
> system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency
842a934
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses
843a936
> system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses
844a938
> system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses
845a940
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency
846a942
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency
847a944
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency
848a946
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
849a948
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
908a1008
> system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses
909a1010
> system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses
910a1012
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses
911a1014
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses
912a1016
> system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses
913a1018
> system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses
914a1020
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency
915a1022
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency
916a1024
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency
917a1026
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency
918a1028
> system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency
919a1030
> system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency
970a1082
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses
971a1084
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses
972a1086
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses
973a1088
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses
974a1090
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses
975a1092
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses
976a1094
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency
977a1096
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency
978a1098
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency
979a1100
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency
980a1102
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency
981a1104
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency
982a1106
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
983a1108
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
984a1110
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1337a1464
> system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses
1338a1466
> system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses
1339a1468
> system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses
1340a1470
> system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency
1341a1472
> system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency
1342a1474
> system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency
1375a1508
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses
1376a1510
> system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses
1377a1512
> system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses
1378a1514
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency
1379a1516
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency
1380a1518
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency
1381a1520
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1382a1522
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1441a1582
> system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses
1442a1584
> system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses
1443a1586
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses
1444a1588
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses
1445a1590
> system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses
1446a1592
> system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses
1447a1594
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency
1448a1596
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency
1449a1598
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency
1450a1600
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency
1451a1602
> system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency
1452a1604
> system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency
1505a1658
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses
1506a1660
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses
1507a1662
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses
1508a1664
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses
1509a1666
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses
1510a1668
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses
1511a1670
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency
1512a1672
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency
1513a1674
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency
1514a1676
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency
1515a1678
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1516a1680
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency
1517a1682
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency
1518a1684
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1519a1686
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1520a1688
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1540a1709
> system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1541a1711
> system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency