3,5c3,5
< sim_seconds 2.825951 # Number of seconds simulated
< sim_ticks 2825951018000 # Number of ticks simulated
< final_tick 2825951018000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.825960 # Number of seconds simulated
> sim_ticks 2825959731500 # Number of ticks simulated
> final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 126581 # Simulator instruction rate (inst/s)
< host_op_rate 153564 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2973571752 # Simulator tick rate (ticks/s)
< host_mem_usage 617520 # Number of bytes of host memory used
< host_seconds 950.36 # Real time elapsed on the host
< sim_insts 120297223 # Number of instructions simulated
< sim_ops 145940268 # Number of ops (including micro ops) simulated
---
> host_inst_rate 71367 # Simulator instruction rate (inst/s)
> host_op_rate 86573 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1679006506 # Simulator tick rate (ticks/s)
> host_mem_usage 618544 # Number of bytes of host memory used
> host_seconds 1683.11 # Real time elapsed on the host
> sim_insts 120118276 # Number of instructions simulated
> sim_ops 145712235 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::cpu0.inst 1286144 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1281192 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8384576 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory
23,25c23,25
< system.physmem.bytes_read::cpu1.inst 188912 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 582932 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 428544 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 644308 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 521472 # Number of bytes read from this memory
27,31c27,31
< system.physmem.bytes_read::total 12155436 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1286144 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 188912 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1475056 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8692480 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12495724 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1306176 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 181104 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1487280 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8956736 # Number of bytes written to this memory
34,35c34,35
< system.physmem.bytes_written::total 8710044 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8974300 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
37,40c37,40
< system.physmem.num_reads::cpu0.inst 22343 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 20539 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 131009 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 22656 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 21172 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 133087 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory
42,44c42,44
< system.physmem.num_reads::cpu1.inst 3020 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 9129 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 6696 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 2898 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 10088 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 8148 # Number of read requests responded to by this memory
46,47c46,47
< system.physmem.num_reads::total 192785 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 135820 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 198102 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 139949 # Number of write requests responded to by this memory
50,51c50,51
< system.physmem.num_writes::total 140211 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 144340 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s)
53,56c53,56
< system.physmem.bw_read::cpu0.inst 455119 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 453367 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 2966993 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 462206 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 467701 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 3014044 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 159 # Total read bandwidth from this memory (bytes/s)
58,60c58,60
< system.physmem.bw_read::cpu1.inst 66849 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 206278 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 151646 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 64086 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 227996 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 184529 # Total read bandwidth from this memory (bytes/s)
62,66c62,66
< system.physmem.bw_read::total 4301361 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 455119 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 66849 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 521968 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3075949 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4421763 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 462206 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 64086 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 526292 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3169449 # Write bandwidth from this memory (bytes/s)
69,71c69,71
< system.physmem.bw_write::total 3082164 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3075949 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3175665 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3169449 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s)
73,76c73,76
< system.physmem.bw_total::cpu0.inst 455119 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 459568 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 2966993 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 462206 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 473902 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 3014044 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 159 # Total bandwidth to/from this memory (bytes/s)
78,80c78,80
< system.physmem.bw_total::cpu1.inst 66849 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 206292 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 151646 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu1.inst 64086 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 228010 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 184529 # Total bandwidth to/from this memory (bytes/s)
82,92c82,92
< system.physmem.bw_total::total 7383525 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 192786 # Number of read requests accepted
< system.physmem.writeReqs 140211 # Number of write requests accepted
< system.physmem.readBursts 192786 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 140211 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12328960 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8722752 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12155500 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8710044 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 7597427 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 198102 # Number of read requests accepted
> system.physmem.writeReqs 144340 # Number of write requests accepted
> system.physmem.readBursts 198102 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 144340 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12669056 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8986944 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12495724 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8974300 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue
95,126c95,126
< system.physmem.perBankRdBursts::0 11498 # Per bank write bursts
< system.physmem.perBankRdBursts::1 11843 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12508 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12790 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14191 # Per bank write bursts
< system.physmem.perBankRdBursts::5 11869 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11798 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11857 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12385 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12638 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11524 # Per bank write bursts
< system.physmem.perBankRdBursts::11 10795 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11419 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12202 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11695 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11628 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8335 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8752 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9292 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9229 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7962 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8394 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8300 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8278 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8796 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9162 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8546 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8147 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8256 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8410 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8295 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8139 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 12421 # Per bank write bursts
> system.physmem.perBankRdBursts::1 12320 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12949 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12687 # Per bank write bursts
> system.physmem.perBankRdBursts::4 14539 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12136 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12666 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12482 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12195 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12078 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11738 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11022 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11908 # Per bank write bursts
> system.physmem.perBankRdBursts::13 13049 # Per bank write bursts
> system.physmem.perBankRdBursts::14 12095 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11669 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9112 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9127 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9607 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9172 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8420 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8729 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8984 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8803 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8716 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8606 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8527 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8118 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8733 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9183 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8560 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8024 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
< system.physmem.totGap 2825950731000 # Total gap between requests
---
> system.physmem.numWrRetry 19 # Number of times write queue was full causing retry
> system.physmem.totGap 2825959428000 # Total gap between requests
136c136
< system.physmem.readPktSize::6 189120 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 194436 # Read request sizes (log2)
143,163c143,163
< system.physmem.writePktSize::6 135820 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 58633 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 71115 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 15338 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 12619 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8378 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7227 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 6243 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 5114 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 4480 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1398 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 907 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 653 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 279 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 139949 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 60343 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 72005 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 15875 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12985 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 8721 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7504 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 6567 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 4768 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1542 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 975 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 736 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 313 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
191,257c191,257
< system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3577 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4774 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5406 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5763 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6710 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7308 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8419 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8358 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9796 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10601 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9066 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 10699 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8900 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7787 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 704 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 211 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 96 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 47 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 88838 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 236.966703 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 133.563892 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 301.532977 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 48504 54.60% 54.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17119 19.27% 73.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5692 6.41% 80.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3330 3.75% 84.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2666 3.00% 87.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1452 1.63% 88.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 904 1.02% 89.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1002 1.13% 90.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8169 9.20% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 88838 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6725 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.644610 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 576.008815 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6723 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3720 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4868 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5700 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6922 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8592 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8610 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 10123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 10779 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 9327 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9570 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 11050 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 9220 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 8388 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7975 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 747 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 571 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 421 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 41 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 92433 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 234.287927 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 132.256290 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 299.423161 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 50967 55.14% 55.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17630 19.07% 74.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5955 6.44% 80.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3343 3.62% 84.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2739 2.96% 87.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1518 1.64% 88.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 933 1.01% 89.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1042 1.13% 91.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8306 8.99% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 92433 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6998 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.287082 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 556.369682 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6996 99.97% 99.97% # Reads before turning the bus around for writes
259,301c259,300
< system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6725 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6725 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.266617 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.732165 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 12.286650 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5583 83.02% 83.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 392 5.83% 88.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 83 1.23% 90.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 55 0.82% 90.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 273 4.06% 94.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 27 0.40% 95.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 22 0.33% 95.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 18 0.27% 95.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 21 0.31% 96.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 12 0.18% 96.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 9 0.13% 96.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 9 0.13% 96.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 148 2.20% 98.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 9 0.13% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 7 0.10% 99.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 12 0.18% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 3 0.04% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.01% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 2 0.03% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 4 0.06% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.01% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 11 0.16% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 3 0.04% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6725 # Writes before turning the bus around for reads
< system.physmem.totQLat 6328126220 # Total ticks spent queuing
< system.physmem.totMemAccLat 9940126220 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 963200000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 32849.49 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6998 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6998 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.065876 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.638507 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.720707 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5824 83.22% 83.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 388 5.54% 88.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 101 1.44% 90.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 68 0.97% 91.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 286 4.09% 95.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 30 0.43% 95.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 22 0.31% 96.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 18 0.26% 96.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 13 0.19% 96.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 6 0.09% 96.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 8 0.11% 96.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 11 0.16% 96.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 167 2.39% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 2 0.03% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 5 0.07% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 8 0.11% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 4 0.06% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.03% 99.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 4 0.06% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 3 0.04% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.01% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.01% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 9 0.13% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6998 # Writes before turning the bus around for reads
> system.physmem.totQLat 6678126737 # Total ticks spent queuing
> system.physmem.totMemAccLat 10389764237 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 989770000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 33735.75 # Average queueing delay per DRAM burst
303,307c302,306
< system.physmem.avgMemAccLat 51599.49 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.36 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.09 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.08 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 52485.75 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s
310c309
< system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
---
> system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
312,330c311,329
< system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 21.86 # Average write queue length when enqueuing
< system.physmem.readRowHits 160949 # Number of row buffer hits during reads
< system.physmem.writeRowHits 79145 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.55 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 58.06 # Row buffer hit rate for writes
< system.physmem.avgGap 8486414.99 # Average gap between requests
< system.physmem.pageHitRate 72.99 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 340562880 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 185823000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 767153400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 444152160 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 79601761125 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1625743658250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1891660385775 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.389284 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2704476978140 # Time in different power states
< system.physmem_0.memoryStateTime::REF 94364660000 # Time in different power states
---
> system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing
> system.physmem.readRowHits 165316 # Number of row buffer hits during reads
> system.physmem.writeRowHits 80625 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes
> system.physmem.avgGap 8252373.91 # Average gap between requests
> system.physmem.pageHitRate 72.68 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 362040840 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 197542125 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 797160000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 466261920 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 79687786095 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1625672869500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1891761444000 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.423201 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2704357113137 # Time in different power states
> system.physmem_0.memoryStateTime::REF 94364920000 # Time in different power states
332c331
< system.physmem_0.memoryStateTime::ACT 27109359860 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 27235374363 # Time in different power states
334,344c333,343
< system.physmem_1.actEnergy 331052400 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 180633750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 735430800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 439026480 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 79228268055 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1626071283750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1891562970195 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.354813 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2705022466825 # Time in different power states
< system.physmem_1.memoryStateTime::REF 94364660000 # Time in different power states
---
> system.physmem_1.actEnergy 336752640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 183744000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 746873400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 443666160 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 79354368585 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.369090 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states
> system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states
346c345
< system.physmem_1.memoryStateTime::ACT 26562494425 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states
372,376c371,375
< system.cpu0.branchPred.lookups 23820996 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 15588859 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 920395 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 14518297 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 9504336 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 53057105 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 933540 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 32092107 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 13945777 # Number of BTB hits
378,384c377,383
< system.cpu0.branchPred.BTBHitPct 65.464538 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 3840995 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 33136 # Number of incorrect RAS predictions.
< system.cpu0.branchPred.indirectLookups 1356781 # Number of indirect predictor lookups.
< system.cpu0.branchPred.indirectHits 1203053 # Number of indirect target hits.
< system.cpu0.branchPred.indirectMisses 153728 # Number of indirect misses.
< system.cpu0.branchPredindirectMispredicted 48358 # Number of mispredicted indirect branches.
---
> system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions.
> system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups.
> system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits.
> system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses.
> system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches.
415,428c414,428
< system.cpu0.dtb.walker.walks 66654 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 66654 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25108 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18968 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 22578 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 44076 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 460.137036 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 2988.406264 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-8191 42948 97.44% 97.44% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::8192-16383 855 1.94% 99.38% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::16384-24575 123 0.28% 99.66% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::24576-32767 110 0.25% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency
---
> system.cpu0.dtb.walker.walks 67255 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-8191 43255 97.44% 97.44% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::8192-16383 874 1.97% 99.41% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::16384-24575 114 0.26% 99.66% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::24576-32767 99 0.22% 99.89% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::32768-40959 12 0.03% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency
433,463c433,464
< system.cpu0.dtb.walker.walkWaitTime::total 44076 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 16898 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 11121.375311 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 9757.603879 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 6791.562531 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-16383 15594 92.28% 92.28% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1190 7.04% 99.33% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-49151 80 0.47% 99.80% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::49152-65535 11 0.07% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-114687 8 0.05% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 16898 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 90055870948 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.547875 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.509370 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 89997968948 99.94% 99.94% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 40556500 0.05% 99.98% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 7037000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 4893500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 1776500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 1132500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 1239500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 1264500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::16-17 2000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 90055870948 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 5227 78.38% 78.38% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1442 21.62% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6669 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66654 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkWaitTime::total 44392 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 17098 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 11190.109954 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 9724.852754 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 7829.867535 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-16383 15731 92.00% 92.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1253 7.33% 99.33% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-49151 72 0.42% 99.75% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.04% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::147456-163839 16 0.09% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 17098 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 81474776356 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.525392 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.513017 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 81416314856 99.93% 99.93% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 41234500 0.05% 99.98% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 7083500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 4738000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 1423000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 1004000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 1185500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 1778000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 81474776356 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 5261 77.38% 77.38% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.62% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 6799 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67255 # Table walker requests started/completed, data/inst
465,466c466,467
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66654 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6669 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67255 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6799 # Table walker requests started/completed, data/inst
468,469c469,470
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6669 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 73323 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6799 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 74054 # Table walker requests started/completed, data/inst
472,475c473,476
< system.cpu0.dtb.read_hits 17666854 # DTB read hits
< system.cpu0.dtb.read_misses 56136 # DTB read misses
< system.cpu0.dtb.write_hits 14559303 # DTB write hits
< system.cpu0.dtb.write_misses 10518 # DTB write misses
---
> system.cpu0.dtb.read_hits 23647306 # DTB read hits
> system.cpu0.dtb.read_misses 56401 # DTB read misses
> system.cpu0.dtb.write_hits 17573284 # DTB write hits
> system.cpu0.dtb.write_misses 10854 # DTB write misses
480,482c481,483
< system.cpu0.dtb.flush_entries 3504 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 2262 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch
484,486c485,487
< system.cpu0.dtb.perms_faults 861 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 17722990 # DTB read accesses
< system.cpu0.dtb.write_accesses 14569821 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 23703707 # DTB read accesses
> system.cpu0.dtb.write_accesses 17584138 # DTB write accesses
488,490c489,491
< system.cpu0.dtb.hits 32226157 # DTB hits
< system.cpu0.dtb.misses 66654 # DTB misses
< system.cpu0.dtb.accesses 32292811 # DTB accesses
---
> system.cpu0.dtb.hits 41220590 # DTB hits
> system.cpu0.dtb.misses 67255 # DTB misses
> system.cpu0.dtb.accesses 41287845 # DTB accesses
520,549c521,547
< system.cpu0.itb.walker.walks 10841 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 10841 # Table walker walks initiated with short descriptors
< system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3909 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5864 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 1068 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 421.927760 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 2234.177799 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-4095 9414 96.33% 96.33% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::8192-12287 108 1.11% 99.08% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.60% 99.68% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.76% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::20480-24575 12 0.12% 99.89% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 12199.451303 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 11419.234768 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 4654.618910 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-8191 570 15.64% 15.64% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::8192-16383 2859 78.44% 94.07% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-24575 148 4.06% 98.13% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.31% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.60% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walks 10944 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors
> system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-4095 9496 96.09% 96.09% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::4096-8191 178 1.80% 97.90% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::8192-12287 126 1.28% 99.17% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.62% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.70% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.23% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 9882 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 3633 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 11938.893476 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 11121.754202 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 4829.169649 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-8191 620 17.07% 17.07% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::8192-16383 2792 76.85% 93.92% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.83% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.24% 99.06% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-40959 33 0.91% 99.97% # Table walker service (enqueue to completion) latency
551,562c549,560
< system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 21336382212 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.847765 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.359386 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 3249113500 15.23% 15.23% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 18086389212 84.77% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 793000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 86500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 21336382212 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 2247 87.19% 87.19% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::1M 330 12.81% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 2577 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkCompletionTime::total 3633 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 21344293712 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.816978 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.386812 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 3907509500 18.31% 18.31% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 17435777712 81.69% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 987000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 19500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 21344293712 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 2239 87.09% 87.09% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::1M 332 12.91% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated
564,565c562,563
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10841 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10841 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10944 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10944 # Table walker requests started/completed, data/inst
567,571c565,569
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2577 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2577 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 13418 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 37363257 # ITB inst hits
< system.cpu0.itb.inst_misses 10841 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 13515 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 72708872 # ITB inst hits
> system.cpu0.itb.inst_misses 10944 # ITB inst misses
580c578
< system.cpu0.itb.flush_entries 2348 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2345 # Number of entries that have been flushed from TLB
584c582
< system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions
587,591c585,589
< system.cpu0.itb.inst_accesses 37374098 # ITB inst accesses
< system.cpu0.itb.hits 37363257 # DTB hits
< system.cpu0.itb.misses 10841 # DTB misses
< system.cpu0.itb.accesses 37374098 # DTB accesses
< system.cpu0.numCycles 130634754 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses
> system.cpu0.itb.hits 72708872 # DTB hits
> system.cpu0.itb.misses 10944 # DTB misses
> system.cpu0.itb.accesses 72719816 # DTB accesses
> system.cpu0.numCycles 202299816 # number of cpu cycles simulated
594,610c592,608
< system.cpu0.fetch.icacheStallCycles 18759180 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 111594210 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 23820996 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 14548384 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 105958075 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 2723782 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 147803 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 57411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 403538 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 420731 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 91570 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 37362977 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 256682 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 5313 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 127200199 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 1.057439 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.258294 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 5690816 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 148557 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 57787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 411894 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 415808 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 91444 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 72708572 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 259286 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 5400 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 198828221 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 1.203592 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.307832 # Number of instructions fetched each cycle (Total)
612,615c610,613
< system.cpu0.fetch.rateDist::0 65301995 51.34% 51.34% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 21243041 16.70% 68.04% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 8702131 6.84% 74.88% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 31953032 25.12% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 93975229 47.26% 47.26% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 30343697 15.26% 62.53% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 14563448 7.32% 69.85% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 59945847 30.15% 100.00% # Number of instructions fetched each cycle (Total)
619,665c617,663
< system.cpu0.fetch.rateDist::total 127200199 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.182348 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.854246 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 19580299 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 60730761 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 40895062 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 4960019 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1034058 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 3027631 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 331959 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 109730420 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 3757258 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 1034058 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 25213970 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 12473804 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 37385885 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 40084231 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 11008251 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 104776923 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 1005898 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 1454281 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 163264 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 59868 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 6802738 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 108917617 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 478329249 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 119800886 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 97884799 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 11032807 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1224750 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 1083467 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 12359769 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 18590109 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 16025944 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1692928 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 2223672 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 101900058 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1687234 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 100089682 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 451563 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 8991464 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 21250511 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 118873 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 127200199 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.786867 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.029325 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 198828221 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.262270 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.967832 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 25603497 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 106945433 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 58799621 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 4964058 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 2515612 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 3059417 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 333874 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 154225745 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 3810952 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 2515612 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 34211381 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 12457896 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 83569478 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 55018547 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 11055307 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 137550697 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 1033071 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 1452205 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 164556 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 58179 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 6849429 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 141656181 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 634615161 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 152645231 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 9369 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 130468277 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 11187893 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 2697265 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 2555549 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 22573870 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 24578234 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 19061004 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1697434 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 2322680 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 134618116 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1713414 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 132756465 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 452944 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 10581179 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 21721412 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 120083 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 198828221 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.667694 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 0.963230 # Number of insts issued each cycle
667,672c665,670
< system.cpu0.iq.issued_per_cycle::0 71273767 56.03% 56.03% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 23216726 18.25% 74.28% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 22358125 17.58% 91.86% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 9249672 7.27% 99.13% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1101855 0.87% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 122137220 61.43% 61.43% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 33612355 16.91% 78.33% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 31219254 15.70% 94.04% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 10732023 5.40% 99.43% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1127312 0.57% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle
679c677
< system.cpu0.iq.issued_per_cycle::total 127200199 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 198828221 # Number of insts issued each cycle
681,711c679,709
< system.cpu0.iq.fu_full::IntAlu 9294441 40.55% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 68 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 5565368 24.28% 64.83% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 8061478 35.17% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 10787922 43.88% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 67 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.88% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 5632694 22.91% 66.78% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 8166758 33.22% 100.00% # attempts to use FU when none available
715,745c713,743
< system.cpu0.iq.FU_type_0::IntAlu 66026932 65.97% 65.97% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 92216 0.09% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 8071 0.01% 66.07% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 18353253 18.34% 84.41% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 15606936 15.59% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 89674441 67.55% 67.55% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 111153 0.08% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 8107 0.01% 67.64% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 24338377 18.33% 85.97% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 18622113 14.03% 100.00% # Type of FU issued
748,760c746,758
< system.cpu0.iq.FU_type_0::total 100089682 # Type of FU issued
< system.cpu0.iq.rate 0.766180 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 22921355 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.229008 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 350720067 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 112586232 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 98062666 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 32413 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 11362 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 9718 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 122987773 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 20991 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 362703 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 132756465 # Type of FU issued
> system.cpu0.iq.rate 0.656236 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 24587441 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.185207 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 489349072 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 146920725 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 129226985 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 32463 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 11252 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 157320500 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 21133 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 365431 # Number of loads that had data forwarded from stores
762,765c760,763
< system.cpu0.iew.lsq.thread0.squashedLoads 1887830 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 18911 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 876012 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1915604 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 19339 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 897405 # Number of stores squashed
768,769c766,767
< system.cpu0.iew.lsq.thread0.rescheduledLoads 109448 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 364606 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 120966 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 361642 # Number of times an access to memory failed due to the cache being blocked
771,774c769,772
< system.cpu0.iew.iewSquashCycles 1034058 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 1622257 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 187065 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 103740401 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 2515612 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 1602789 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 184527 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 136483987 # Number of instructions dispatched to IQ
776,787c774,785
< system.cpu0.iew.iewDispLoadInsts 18590109 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 16025944 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 873149 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 28190 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 135133 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 18911 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 251727 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 397563 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 649290 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 99070135 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 17913102 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 953014 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 24578234 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 19061004 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 875924 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 28511 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 132116 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 19339 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 261904 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 398193 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 660097 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 131724041 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 23895876 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 965291 # Number of squashed instructions skipped in execute
789,805c787,803
< system.cpu0.iew.exec_nop 153109 # number of nop insts executed
< system.cpu0.iew.exec_refs 33359413 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 16770669 # Number of branches executed
< system.cpu0.iew.exec_stores 15446311 # Number of stores executed
< system.cpu0.iew.exec_rate 0.758375 # Inst execution rate
< system.cpu0.iew.wb_sent 98522156 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 98072384 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 51087973 # num instructions producing a value
< system.cpu0.iew.wb_consumers 84406715 # num instructions consuming a value
< system.cpu0.iew.wb_rate 0.750737 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.605260 # average fanout of values written-back
< system.cpu0.commit.commitSquashedInsts 7992419 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 1568361 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 592562 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 125525573 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.754570 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.472389 # Number of insts commited each cycle
---
> system.cpu0.iew.exec_nop 152457 # number of nop insts executed
> system.cpu0.iew.exec_refs 42356949 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 25556056 # Number of branches executed
> system.cpu0.iew.exec_stores 18461073 # Number of stores executed
> system.cpu0.iew.exec_rate 0.651133 # Inst execution rate
> system.cpu0.iew.wb_sent 131168007 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 129236702 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 65950850 # num instructions producing a value
> system.cpu0.iew.wb_consumers 106665798 # num instructions consuming a value
> system.cpu0.iew.wb_rate 0.638837 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.618294 # average fanout of values written-back
> system.cpu0.commit.commitSquashedInsts 9550008 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 1593331 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 603744 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 195669003 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.643292 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.341136 # Number of insts commited each cycle
807,815c805,813
< system.cpu0.commit.committed_per_cycle::0 81342054 64.80% 64.80% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 24610935 19.61% 84.41% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 8228457 6.56% 90.96% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 3212332 2.56% 93.52% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 3423017 2.73% 96.25% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 1492381 1.19% 97.44% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 1160319 0.92% 98.36% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 551485 0.44% 98.80% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1504593 1.20% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 135299612 69.15% 69.15% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 33411311 17.08% 86.22% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 12639941 6.46% 92.68% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 3246105 1.66% 94.34% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 4896411 2.50% 96.84% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 2789558 1.43% 98.27% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 1311154 0.67% 98.94% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 556760 0.28% 99.22% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1518151 0.78% 100.00% # Number of insts commited each cycle
819,821c817,819
< system.cpu0.commit.committed_per_cycle::total 125525573 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 78721743 # Number of instructions committed
< system.cpu0.commit.committedOps 94717871 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 195669003 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 103938440 # Number of instructions committed
> system.cpu0.commit.committedOps 125872394 # Number of ops (including micro ops) committed
823,826c821,824
< system.cpu0.commit.refs 31852210 # Number of memory references committed
< system.cpu0.commit.loads 16702278 # Number of loads committed
< system.cpu0.commit.membars 645830 # Number of memory barriers committed
< system.cpu0.commit.branches 16170329 # Number of branches committed
---
> system.cpu0.commit.refs 40826228 # Number of memory references committed
> system.cpu0.commit.loads 22662629 # Number of loads committed
> system.cpu0.commit.membars 647252 # Number of memory barriers committed
> system.cpu0.commit.branches 24954847 # Number of branches committed
828,829c826,827
< system.cpu0.commit.int_insts 81695650 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 1925626 # Number of function calls committed.
---
> system.cpu0.commit.int_insts 109891295 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 4835454 # Number of function calls committed.
831,861c829,859
< system.cpu0.commit.op_class_0::IntAlu 62767692 66.27% 66.27% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 89898 0.09% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 8071 0.01% 66.37% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.37% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.37% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.37% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 16702278 17.63% 84.01% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 15149932 15.99% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 84929206 67.47% 67.47% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 108853 0.09% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 8107 0.01% 67.57% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 22662629 18.00% 85.57% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 18163599 14.43% 100.00% # Class of committed instruction
864,879c862,877
< system.cpu0.commit.op_class_0::total 94717871 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1504593 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 222549197 # The number of ROB reads
< system.cpu0.rob.rob_writes 207085893 # The number of ROB writes
< system.cpu0.timesIdled 123342 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 3434555 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 5521267593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 78599691 # Number of Instructions Simulated
< system.cpu0.committedOps 94595819 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.662026 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.662026 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.601675 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.601675 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 110021691 # number of integer regfile reads
< system.cpu0.int_regfile_writes 59386115 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 8176 # number of floating regfile reads
---
> system.cpu0.commit.op_class_0::total 125872394 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1518151 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 306287204 # The number of ROB reads
> system.cpu0.rob.rob_writes 273994781 # The number of ROB writes
> system.cpu0.timesIdled 123974 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 3471595 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 5449619957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 103816388 # Number of Instructions Simulated
> system.cpu0.committedOps 125750342 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.948631 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.948631 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.513181 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.513181 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads
> system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads
881,889c879,887
< system.cpu0.cc_regfile_reads 349047979 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 40883845 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 177564457 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 1222085 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 709600 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 499.965510 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 28702051 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 710112 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 40.419048 # Average number of references to valid blocks.
---
> system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 274171027 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 709828 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks.
891,893c889,891
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.965510 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.976495 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.976495 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy
895,897c893,895
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
899,978c897,976
< system.cpu0.dcache.tags.tag_accesses 63247390 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 63247390 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 15498209 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 15498209 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 11982969 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 11982969 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307264 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 307264 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362251 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 362251 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360359 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 360359 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 27481178 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 27481178 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 27788442 # number of overall hits
< system.cpu0.dcache.overall_hits::total 27788442 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 646938 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 646938 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1889976 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1889976 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147980 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 147980 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25182 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 25182 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20295 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 20295 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2536914 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2536914 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2684894 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2684894 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8613079000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 8613079000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29673912872 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 29673912872 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399362500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 399362500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 493278500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 493278500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 493500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 493500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 38286991872 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 38286991872 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 38286991872 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 38286991872 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 16145147 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 16145147 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 13872945 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 13872945 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455244 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 455244 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387433 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 387433 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 380654 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 380654 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 30018092 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 30018092 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 30473336 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 30473336 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040070 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.040070 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136235 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.136235 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325056 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325056 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064997 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064997 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053316 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053316 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084513 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.084513 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088106 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.088106 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13313.608105 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13313.608105 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15700.682375 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 15700.682375 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15859.046144 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15859.046144 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24305.420054 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24305.420054 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361109 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 361109 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 36442971 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 36442971 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 36751498 # number of overall hits
> system.cpu0.dcache.overall_hits::total 36751498 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 646522 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 646522 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1887777 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1887777 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147802 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 147802 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25065 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 25065 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20108 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 20108 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 2534299 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 2534299 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 2682101 # number of overall misses
> system.cpu0.dcache.overall_misses::total 2682101 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8646662000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 8646662000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29876871349 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 29876871349 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399690500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 399690500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484891000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 484891000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 240000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 240000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 38523533349 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 38523533349 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 38523533349 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 38523533349 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 22101371 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 22101371 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 16875899 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 16875899 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456329 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 456329 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388131 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 388131 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381217 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 381217 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 38977270 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 38977270 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 39433599 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 39433599 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029253 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.029253 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111862 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.111862 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323894 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323894 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064579 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064579 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052747 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052747 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065020 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.065020 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068016 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.068016 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13374.118746 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13374.118746 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15826.483398 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 15826.483398 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15946.159984 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15946.159984 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24114.332604 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24114.332604 # average StoreCondReq miss latency
981,1066c979,1064
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15091.954978 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 15091.954978 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14260.150260 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 14260.150260 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 1062 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 4223116 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 45 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 202030 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.600000 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 20.903410 # average number of cycles each access was blocked
< system.cpu0.dcache.writebacks::writebacks 709603 # number of writebacks
< system.cpu0.dcache.writebacks::total 709603 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260771 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 260771 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1564893 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1564893 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18568 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18568 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1825664 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1825664 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1825664 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1825664 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386167 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 386167 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325083 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 325083 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102058 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 102058 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6614 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6614 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20295 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 20295 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 711250 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 711250 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 813308 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 813308 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20340 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19033 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39373 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4553087000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4553087000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6070046902 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6070046902 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1659761500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1659761500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103454000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103454000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 472996500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 472996500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10623133902 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 10623133902 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12282895402 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 12282895402 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534665000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534665000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534665000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534665000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023918 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023918 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023433 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023433 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224183 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224183 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017071 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053316 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053316 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023694 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.023694 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026689 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.026689 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11790.461122 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11790.461122 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18672.298773 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18672.298773 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16262.924024 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16262.924024 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15641.669187 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15641.669187 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23306.060606 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23306.060606 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15200.863572 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 15200.863572 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14363.192642 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 14363.192642 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 1028 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 4276317 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 201917 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.416667 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 21.178588 # average number of cycles each access was blocked
> system.cpu0.dcache.writebacks::writebacks 709828 # number of writebacks
> system.cpu0.dcache.writebacks::total 709828 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 259036 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 259036 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563852 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1563852 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18553 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18553 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822888 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1822888 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822888 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1822888 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387486 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 387486 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323925 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 323925 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101400 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 101400 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6512 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6512 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20108 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 20108 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 711411 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 711411 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 812811 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 812811 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31771 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60221 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4570691500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4570691500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6113916381 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6113916381 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664414000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664414000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102380000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102380000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464790000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464790000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 233000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 233000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10684607881 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10684607881 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12349021881 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 12349021881 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621026500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621026500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621026500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621026500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017532 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017532 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019195 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019195 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222208 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222208 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016778 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016778 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052747 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052747 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018252 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.018252 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020612 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.020612 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11795.759073 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11795.759073 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18874.481380 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18874.481380 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16414.339250 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16414.339250 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15721.744472 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15721.744472 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23114.680724 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23114.680724 # average StoreCondReq mshr miss latency
1069,1085c1067,1083
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14935.864889 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14935.864889 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15102.390979 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15102.390979 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222943.215339 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222943.215339 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115171.945242 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115171.945242 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.replacements 1244973 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.762786 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 36061117 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1245485 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 28.953474 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6512698000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762786 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.replacements 1253795 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy
1087,1089c1085,1087
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id
1091,1148c1089,1146
< system.cpu0.icache.tags.tag_accesses 75964361 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 75964361 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 36061117 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 36061117 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 36061117 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 36061117 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 36061117 # number of overall hits
< system.cpu0.icache.overall_hits::total 36061117 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1298298 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1298298 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1298298 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1298298 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1298298 # number of overall misses
< system.cpu0.icache.overall_misses::total 1298298 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13095750432 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 13095750432 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 13095750432 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 13095750432 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 13095750432 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 13095750432 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 37359415 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 37359415 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 37359415 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 37359415 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 37359415 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 37359415 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034752 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.034752 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034752 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.034752 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034752 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.034752 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10086.860206 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10086.860206 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10086.860206 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10086.860206 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 1564537 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 822 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 111550 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.025433 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 74.727273 # average number of cycles each access was blocked
< system.cpu0.icache.writebacks::writebacks 1244973 # number of writebacks
< system.cpu0.icache.writebacks::total 1244973 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52766 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 52766 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 52766 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 52766 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 52766 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 52766 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1245532 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1245532 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1245532 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1245532 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1245532 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1245532 # number of overall MSHR misses
---
> system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits
> system.cpu0.icache.overall_hits::total 71396857 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1308156 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1308156 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1308156 # number of overall misses
> system.cpu0.icache.overall_misses::total 1308156 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13216802476 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 13216802476 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 13216802476 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 13216802476 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 13216802476 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 13216802476 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 72705013 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 72705013 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 72705013 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 72705013 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 72705013 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 72705013 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017993 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.017993 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017993 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.017993 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017993 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.017993 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10103.384058 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10103.384058 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10103.384058 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10103.384058 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 1586454 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 112621 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.086662 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked
> system.cpu0.icache.writebacks::writebacks 1253795 # number of writebacks
> system.cpu0.icache.writebacks::total 1253795 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53805 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 53805 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 53805 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 53805 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 53805 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 53805 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1254351 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1254351 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1254351 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1254351 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1254351 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1254351 # number of overall MSHR misses
1153,1158c1151,1156
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11887458427 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 11887458427 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11887458427 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 11887458427 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11887458427 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 11887458427 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11994065954 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 11994065954 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11994065954 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 11994065954 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11994065954 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 11994065954 # number of overall MSHR miss cycles
1163,1174c1161,1172
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033339 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.033339 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.033339 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9544.081105 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9561.969460 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency
1179,1181c1177,1179
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836444 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1838932 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 2249 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue
1184,1189c1182,1187
< system.cpu0.l2cache.prefetcher.pfSpanPage 237260 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 275777 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16077.094616 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 3264993 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 291873 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 11.186348 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 276743 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks.
1191,1204c1189,1202
< system.cpu0.l2cache.tags.occ_blocks::writebacks 14642.260262 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 14.030425 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.082237 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1420.721692 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.893693 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000856 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086714 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.981268 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1015 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15073 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 314 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.382075 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1413.670732 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.895209 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000987 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000084 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086284 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.982564 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 303 # Occupied blocks per task id
1206,1208c1204,1207
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 282 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 295 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
1210,1246c1209,1245
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 477 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4659 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6956 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2859 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061951 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919983 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 66024498 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 66024498 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55983 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13286 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 69269 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 482066 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 482066 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 1441412 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 1441412 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221318 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 221318 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1193309 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1193309 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398313 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 398313 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55983 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13286 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1193309 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 619631 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1882209 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55983 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13286 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1193309 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 619631 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1882209 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 409 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 145 # number of ReadReq misses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 469 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 481730 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 481730 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 1450652 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 1450652 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221301 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 221301 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1201423 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1201423 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398814 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 398814 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55484 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13243 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1201423 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 620115 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1890265 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55484 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13243 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1201423 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 620115 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1890265 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 413 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses
1248,1328c1247,1327
< system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
< system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55455 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 55455 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20295 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 20295 # number of SCUpgradeReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48487 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 48487 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 52186 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 52186 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96414 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 96414 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 409 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 145 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 52186 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 144901 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 197641 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 409 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 145 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 52186 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 144901 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 197641 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11428500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3458500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 14887000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 116593500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 116593500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 25461000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 25461000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 459500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 459500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2707524000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2707524000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2738746000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2738746000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2927576997 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2927576997 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11428500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3458500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2738746000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 5635100997 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 8388733997 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11428500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3458500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2738746000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 5635100997 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 8388733997 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 56392 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13431 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 69823 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482067 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 482067 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 1441412 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 1441412 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55456 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 55456 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20295 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 20295 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269805 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 269805 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1245495 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1245495 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 494727 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 494727 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 56392 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13431 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1245495 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 764532 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 2079850 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 56392 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13431 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1245495 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 764532 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 2079850 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010796 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.007934 # miss rate for ReadReq accesses
< system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses
< system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54992 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 54992 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20107 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 20107 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47807 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 47807 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 52895 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 52895 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96473 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 96473 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 413 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 141 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 52895 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 144280 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 197729 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 413 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 141 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 52895 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 144280 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 197729 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11587500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3409000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 14996500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 108889500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 108889500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 23948500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 23948500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 220499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 220499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2771311500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2771311500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2784395500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2784395500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2944676496 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2944676496 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11587500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3409000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2784395500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 5715987996 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 8515379996 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11587500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3409000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2784395500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 5715987996 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 8515379996 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55897 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13384 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 69281 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481730 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 481730 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 1450652 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 1450652 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54994 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 54994 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20107 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 20107 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269108 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 269108 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1254318 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1254318 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 495287 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 495287 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55897 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13384 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1254318 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 764395 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 2087994 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55897 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13384 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1254318 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 764395 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 2087994 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010535 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.007996 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999964 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999964 # miss rate for UpgradeReq accesses
1331,1372c1330,1373
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.179711 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179711 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041900 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041900 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.194883 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.194883 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010796 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041900 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189529 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.095027 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010796 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041900 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189529 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.095027 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23851.724138 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26871.841155 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2102.488504 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2102.488504 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1254.545455 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1254.545455 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55840.204591 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55840.204591 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52480.473690 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52480.473690 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30364.646182 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30364.646182 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23851.724138 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52480.473690 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38889.317513 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 42444.300510 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23851.724138 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52480.473690 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38889.317513 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 42444.300510 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked
---
> system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.177650 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.177650 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042170 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042170 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.194782 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.194782 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010535 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042170 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.188751 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.094698 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010535 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042170 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.188751 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.094698 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24177.304965 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27069.494585 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1980.097105 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1980.097105 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1191.052867 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1191.052867 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 220499 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 220499 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57968.738888 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57968.738888 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52640.051045 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52640.051045 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30523.322546 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30523.322546 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 43065.913427 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 43065.913427 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked
1374c1375
< system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
1376c1377
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.666667 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1378,1420c1379,1425
< system.cpu0.l2cache.unused_prefetches 10565 # number of HardPF blocks evicted w/o reference
< system.cpu0.l2cache.writebacks::writebacks 229088 # number of writebacks
< system.cpu0.l2cache.writebacks::total 229088 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5680 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 5680 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 39 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 39 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 771 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 771 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 39 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6451 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 6490 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 39 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6451 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 6490 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 409 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 145 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 554 # number of ReadReq MSHR misses
< system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
< system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 255939 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 255939 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55455 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55455 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20295 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20295 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42807 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 42807 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 52147 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 52147 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95643 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95643 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 409 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 145 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 52147 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138450 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 191151 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 409 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 145 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 52147 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138450 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 255939 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 447090 # number of overall MSHR misses
---
> system.cpu0.l2cache.unused_prefetches 10266 # number of HardPF blocks evicted w/o reference
> system.cpu0.l2cache.writebacks::writebacks 229575 # number of writebacks
> system.cpu0.l2cache.writebacks::total 229575 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5846 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 5846 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 35 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 35 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 765 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 765 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 35 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6611 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 6647 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 35 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6611 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 6647 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 412 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 141 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 553 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 257570 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54992 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54992 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20107 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20107 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41961 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41961 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 52860 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 52860 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95708 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95708 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 412 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 141 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 52860 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137669 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 191082 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 412 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 141 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 52860 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137669 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 448652 # number of overall MSHR misses
1422,1425c1427,1430
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23343 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19033 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34774 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable
1427,1456c1432,1461
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42376 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2588500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11563000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15061119493 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15061119493 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1081830000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1081830000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 319630999 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 319630999 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 381500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 381500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1771002000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1771002000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2424780500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2424780500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2310424997 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2310424997 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2588500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2424780500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4081426997 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 6517770497 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2588500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2424780500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4081426997 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15061119493 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 21578889990 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63224 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2563000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11669500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15404483231 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1067197500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1067197500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 312794500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 312794500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 178499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 178499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1799957000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1799957000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2466178500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2466178500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2327314996 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2327314996 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2563000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2466178500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4127271996 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 6605119996 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2563000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2466178500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4127271996 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 22009603227 # number of overall MSHR miss cycles
1458,1459c1463,1464
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4371667500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4618288500 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366568000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613189000 # number of ReadReq MSHR uncacheable cycles
1461,1467c1466,1470
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4371667500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4618288500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
< system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366568000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613189000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007982 # mshr miss rate for ReadReq accesses
1470,1471c1473,1474
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999964 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999964 # mshr miss rate for UpgradeReq accesses
1474,1488c1477,1493
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158659 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158659 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041868 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193325 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193325 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091906 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155926 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155926 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042142 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193237 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193237 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091515 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for overall accesses
1490,1518c1495,1523
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214963 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20871.841155 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58846.520042 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19508.249932 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19508.249932 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15749.248534 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15749.248534 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41371.784988 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41371.784988 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46498.945289 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24156.760003 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24156.760003 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34097.496205 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48265.203852 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214872 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21102.169982 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59806.977641 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19406.413660 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.413660 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15556.497737 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15556.497737 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178499 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178499 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42895.951002 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42895.951002 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46654.909194 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24316.828228 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24316.828228 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34566.939827 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49057.182910 # average overall mshr miss latency
1520,1521c1525,1526
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214929.572271 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197844.685773 # average ReadReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200389.285827 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190176.252372 # average ReadReq mshr uncacheable latency
1523,1562c1528,1567
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111032.115917 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108983.587408 # average overall mshr uncacheable latency
< system.cpu0.toL2Bus.snoop_filter.tot_requests 4059553 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2049525 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31130 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 322631 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318742 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3889 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 102054 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1891052 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 19033 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 19033 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 711408 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 1472505 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 201922 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 326386 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 87454 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42857 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 113442 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 288333 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 284690 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1245532 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576445 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 3297 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3742005 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2570285 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29068 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119436 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 6460794 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159437936 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98528220 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53724 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 225568 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 258245448 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 1026066 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 3122672 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.120692 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.329569 # Request fanout histogram
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency
> system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 86629 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42593 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 112544 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 287566 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 284127 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1254351 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576083 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 3239 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3768469 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2609794 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29242 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119275 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 6526780 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160567216 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98579420 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53536 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 259423760 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 1028398 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 3154188 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.120549 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.330082 # Request fanout histogram
1564,1566c1569,1571
< system.cpu0.toL2Bus.snoop_fanout::0 2749681 88.06% 88.06% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 369102 11.82% 99.88% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 3889 0.12% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 2778586 88.09% 88.09% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 370970 11.76% 99.85% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 4632 0.15% 100.00% # Request fanout histogram
1570,1571c1575,1576
< system.cpu0.toL2Bus.snoop_fanout::total 3122672 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 4044815993 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 3154188 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 4077816986 # Layer occupancy (ticks)
1573c1578
< system.cpu0.toL2Bus.snoopLayer0.occupancy 114413841 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 113410626 # Layer occupancy (ticks)
1575c1580
< system.cpu0.toL2Bus.respLayer0.occupancy 1871838919 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1885067918 # Layer occupancy (ticks)
1577c1582
< system.cpu0.toL2Bus.respLayer1.occupancy 1215906771 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1231542700 # Layer occupancy (ticks)
1579c1584
< system.cpu0.toL2Bus.respLayer2.occupancy 15648976 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 15872970 # Layer occupancy (ticks)
1581c1586
< system.cpu0.toL2Bus.respLayer3.occupancy 63082921 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 63417420 # Layer occupancy (ticks)
1583,1587c1588,1592
< system.cpu1.branchPred.lookups 34009026 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 11598982 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 286954 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 18822923 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 6035110 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 4689327 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 2779312 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 269179 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 2466051 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 1570212 # Number of BTB hits
1589,1595c1594,1600
< system.cpu1.branchPred.BTBHitPct 32.062555 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 12529712 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 7339 # Number of incorrect RAS predictions.
< system.cpu1.branchPred.indirectLookups 9024222 # Number of indirect predictor lookups.
< system.cpu1.branchPred.indirectHits 8987643 # Number of indirect target hits.
< system.cpu1.branchPred.indirectMisses 36579 # Number of indirect misses.
< system.cpu1.branchPredindirectMispredicted 11117 # Number of mispredicted indirect branches.
---
> system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions.
> system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups.
> system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits.
> system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses.
> system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches.
1625,1658c1630,1664
< system.cpu1.dtb.walker.walks 22019 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 22019 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8988 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5922 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 7109 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 14910 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 597.183099 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 3274.563107 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-4095 14271 95.71% 95.71% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::4096-8191 175 1.17% 96.89% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::8192-12287 226 1.52% 98.40% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.65% 99.05% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::16384-20479 36 0.24% 99.30% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::20480-24575 18 0.12% 99.42% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.48% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.42% 99.90% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::32768-36863 6 0.04% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::53248-57343 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 14910 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 5586 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 11231.919083 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 9899.070869 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 6145.006909 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-8191 1859 33.28% 33.28% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3110 55.67% 88.95% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-24575 395 7.07% 96.03% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::24576-32767 162 2.90% 98.93% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-40959 30 0.54% 99.46% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.98% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walks 21410 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-4095 13903 95.52% 95.52% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::4096-8191 193 1.33% 96.85% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::8192-12287 240 1.65% 98.50% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.67% 99.16% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::16384-20479 26 0.18% 99.34% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::20480-24575 15 0.10% 99.44% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.47% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.03% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::45056-49151 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 14555 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 5693 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 11275.601616 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 9954.937359 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 6246.075100 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-8191 1927 33.85% 33.85% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3145 55.24% 89.09% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-24575 429 7.54% 96.63% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::24576-32767 137 2.41% 99.03% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-40959 17 0.30% 99.33% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::40960-49151 31 0.54% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
1660,1684c1666,1683
< system.cpu1.dtb.walker.walkCompletionTime::total 5586 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 72596800264 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.178979 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.387926 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 59651088264 82.17% 82.17% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 12923549000 17.80% 99.97% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2 13278500 0.02% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::3 4124000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4 1159000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::5 892500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6 1267000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::7 399000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8 261000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::9 175000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::10 102500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::11 47000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12 179500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::13 63000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14 38500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::15 176500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 72596800264 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 1935 74.77% 74.77% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 653 25.23% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22019 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkCompletionTime::total 5693 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 72606451764 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.284045 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.454557 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0-1 72584974764 99.97% 99.97% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2-3 16673000 0.02% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4-5 2243500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6-7 1638500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8-9 418000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::10-11 173000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14-15 118000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::16-17 30000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 72606451764 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1957 73.85% 73.85% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 693 26.15% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 2650 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21410 # Table walker requests started/completed, data/inst
1686,1687c1685,1686
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22019 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21410 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2650 # Table walker requests started/completed, data/inst
1689,1690c1688,1689
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 24607 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2650 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 24060 # Table walker requests started/completed, data/inst
1693,1696c1692,1695
< system.cpu1.dtb.read_hits 10217146 # DTB read hits
< system.cpu1.dtb.read_misses 19031 # DTB read misses
< system.cpu1.dtb.write_hits 6545704 # DTB write hits
< system.cpu1.dtb.write_misses 2988 # DTB write misses
---
> system.cpu1.dtb.read_hits 4195760 # DTB read hits
> system.cpu1.dtb.read_misses 18440 # DTB read misses
> system.cpu1.dtb.write_hits 3493575 # DTB write hits
> system.cpu1.dtb.write_misses 2970 # DTB write misses
1701,1703c1700,1702
< system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 2051 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch
1705,1707c1704,1706
< system.cpu1.dtb.perms_faults 389 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 10236177 # DTB read accesses
< system.cpu1.dtb.write_accesses 6548692 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 4214200 # DTB read accesses
> system.cpu1.dtb.write_accesses 3496545 # DTB write accesses
1709,1711c1708,1710
< system.cpu1.dtb.hits 16762850 # DTB hits
< system.cpu1.dtb.misses 22019 # DTB misses
< system.cpu1.dtb.accesses 16784869 # DTB accesses
---
> system.cpu1.dtb.hits 7689335 # DTB hits
> system.cpu1.dtb.misses 21410 # DTB misses
> system.cpu1.dtb.accesses 7710745 # DTB accesses
1741,1744c1740,1743
< system.cpu1.itb.walker.walks 6065 # Table walker walks requested
< system.cpu1.itb.walker.walksShort 6065 # Table walker walks initiated with short descriptors
< system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2849 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2599 # Level at which table walker walks with short descriptors terminate
---
> system.cpu1.itb.walker.walks 5994 # Table walker walks requested
> system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors
> system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate
1746,1755c1745,1754
< system.cpu1.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 300.018355 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 2054.443929 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-4095 5317 97.60% 97.60% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.05% 98.64% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::8192-12287 30 0.55% 99.19% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::12288-16383 22 0.40% 99.60% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::16384-20479 8 0.15% 99.74% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.82% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency
---
> system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-4095 5231 97.28% 97.28% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::4096-8191 63 1.17% 98.46% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::8192-12287 36 0.67% 99.13% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::12288-16383 24 0.45% 99.57% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.13% 99.70% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.78% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::24576-28671 7 0.13% 99.91% # Table walker wait (enqueue to first request) latency
1758,1770c1757,1769
< system.cpu1.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 1777 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 11882.104671 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 10854.352895 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5876.427895 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-8191 298 16.77% 16.77% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-16383 1356 76.31% 93.08% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-24575 64 3.60% 96.68% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.41% 98.09% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-40959 23 1.29% 99.38% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.61% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.77% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::57344-65535 3 0.17% 99.94% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkWaitTime::total 5377 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 1782 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 11592.031425 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 10629.889069 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5561.428024 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-8191 316 17.73% 17.73% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-16383 1349 75.70% 93.43% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-24575 63 3.54% 96.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.40% 98.37% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::32768-40959 19 1.07% 99.44% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.17% 99.61% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.11% 99.94% # Table walker service (enqueue to completion) latency
1772,1783c1771,1781
< system.cpu1.itb.walker.walkCompletionTime::total 1777 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 16742440916 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.881191 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.323702 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 1989886764 11.89% 11.89% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 14751845152 88.11% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 691000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::3 18000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 16742440916 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 988 85.17% 85.17% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::1M 172 14.83% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 1160 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walkCompletionTime::total 1782 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 16752128416 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.862615 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.344368 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 2302152764 13.74% 13.74% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 14449314652 86.25% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 661000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 16752128416 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 990 84.98% 84.98% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::1M 175 15.02% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated
1785,1786c1783,1784
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6065 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6065 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5994 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5994 # Table walker requests started/completed, data/inst
1788,1792c1786,1790
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1160 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1160 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 7225 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 43720811 # ITB inst hits
< system.cpu1.itb.inst_misses 6065 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 7159 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 8253439 # ITB inst hits
> system.cpu1.itb.inst_misses 5994 # ITB inst misses
1801c1799
< system.cpu1.itb.flush_entries 1192 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1194 # Number of entries that have been flushed from TLB
1805c1803
< system.cpu1.itb.perms_faults 560 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions
1808,1812c1806,1810
< system.cpu1.itb.inst_accesses 43726876 # ITB inst accesses
< system.cpu1.itb.hits 43720811 # DTB hits
< system.cpu1.itb.misses 6065 # DTB misses
< system.cpu1.itb.accesses 43726876 # DTB accesses
< system.cpu1.numCycles 106544770 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses
> system.cpu1.itb.hits 8253439 # DTB hits
> system.cpu1.itb.misses 5994 # DTB misses
> system.cpu1.itb.accesses 8259433 # DTB accesses
> system.cpu1.numCycles 34887121 # number of cpu cycles simulated
1815,1831c1813,1829
< system.cpu1.fetch.icacheStallCycles 10285169 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 109329590 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 34009026 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 27552465 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 93003678 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 3760962 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 80448 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 30144 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 178688 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 297988 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 23992 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 43719656 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 111494 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 2187 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 105780588 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.280193 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.339076 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 780426 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 78816 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 28892 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 168872 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 301988 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 23027 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 8252257 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 107887 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 34136181 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.885084 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.219625 # Number of instructions fetched each cycle (Total)
1833,1836c1831,1834
< system.cpu1.fetch.rateDist::0 48754447 46.09% 46.09% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 14049982 13.28% 59.37% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 7558912 7.15% 66.52% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 35417247 33.48% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 20248194 59.32% 59.32% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 4889749 14.32% 73.64% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 1671087 4.90% 78.54% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 7327151 21.46% 100.00% # Number of instructions fetched each cycle (Total)
1840,1886c1838,1884
< system.cpu1.fetch.rateDist::total 105780588 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.319199 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 1.026138 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 13239589 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 62906745 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 26778529 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 1104926 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 1750799 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 750846 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 132411 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 68206477 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 1115402 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 1750799 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 17653779 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 2374666 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 57902702 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 23447751 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 2650891 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 55293666 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 220143 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 265669 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 37332 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 18647 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 1622767 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 55225885 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 261143833 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 58792741 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 1698 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 52650074 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 2575811 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 1881943 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 1808403 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 13140602 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 10477180 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 6893389 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 629902 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 660425 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 54420167 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 587049 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 54175023 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 95968 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 3662766 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 5235414 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 44205 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 105780588 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.512145 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 0.849831 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 34136181 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.134414 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.711489 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 7136711 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 16890873 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 8747772 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 1097057 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 263768 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 709532 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 129045 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 23428697 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 1046505 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 263768 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 8558773 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 2377328 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 11841982 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 8401624 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 2692706 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 22261726 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 187544 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 264330 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 36982 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 15461 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 1675349 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 22265644 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 103654423 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 25648399 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 19867778 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 2397866 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 407377 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 334219 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 2894111 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 4447920 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 3797613 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 625649 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 631175 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 21446441 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 559995 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 21251983 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 91992 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 2044542 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 4727165 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 43295 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 34136181 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.622565 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 0.949324 # Number of insts issued each cycle
1888,1893c1886,1891
< system.cpu1.iq.issued_per_cycle::0 72358023 68.40% 68.40% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 16614078 15.71% 84.11% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 13151335 12.43% 96.54% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 3370344 3.19% 99.73% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 286797 0.27% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 11 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 21624116 63.35% 63.35% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 6146372 18.01% 81.35% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 4248735 12.45% 93.80% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 1859698 5.45% 99.25% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 257253 0.75% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle
1900c1898
< system.cpu1.iq.issued_per_cycle::total 105780588 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 34136181 # Number of insts issued each cycle
1902,1932c1900,1930
< system.cpu1.iq.fu_full::IntAlu 2941757 45.24% 45.24% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 670 0.01% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.26% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 1685952 25.93% 71.19% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 1873492 28.81% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 1435935 29.89% 29.89% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 668 0.01% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.90% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 1614233 33.60% 63.50% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 1753849 36.50% 100.00% # attempts to use FU when none available
1936,1966c1934,1964
< system.cpu1.iq.FU_type_0::IntAlu 36944686 68.20% 68.20% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 46486 0.09% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 3329 0.01% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 10429510 19.25% 87.54% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 6750946 12.46% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 13143313 61.85% 61.85% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 28154 0.13% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 3291 0.02% 61.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 4401591 20.71% 82.70% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 3675568 17.30% 100.00% # Type of FU issued
1969,1977c1967,1975
< system.cpu1.iq.FU_type_0::total 54175023 # Type of FU issued
< system.cpu1.iq.rate 0.508472 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 6501871 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.120016 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 220722500 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 58678222 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 52198206 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 5973 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 2102 # Number of floating instruction queue writes
---
> system.cpu1.iq.FU_type_0::total 21251983 # Type of FU issued
> system.cpu1.iq.rate 0.609164 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 4804685 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.226082 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 81530573 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 24059081 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 20789563 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 6251 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 2056 # Number of floating instruction queue writes
1979,1981c1977,1979
< system.cpu1.iq.int_alu_accesses 60672989 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 3839 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 91219 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.int_alu_accesses 26052476 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 4126 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 87608 # Number of loads that had data forwarded from stores
1983,1986c1981,1984
< system.cpu1.iew.lsq.thread0.squashedLoads 444760 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 748 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 10369 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 281379 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 411817 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 594 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 10183 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 255647 # Number of stores squashed
1989,1990c1987,1988
< system.cpu1.iew.lsq.thread0.rescheduledLoads 52226 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 78419 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 40342 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 77877 # Number of times an access to memory failed due to the cache being blocked
1992,1995c1990,1993
< system.cpu1.iew.iewSquashCycles 1750799 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 547306 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 107318 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 55048106 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 263768 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 542908 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 100291 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 22047493 # Number of instructions dispatched to IQ
1997,2008c1995,2006
< system.cpu1.iew.iewDispLoadInsts 10477180 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 6893389 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 299581 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 8072 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 92519 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 10369 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 45476 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 168250 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 53925594 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 10330118 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 227431 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 4447920 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 3797613 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 296998 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 7633 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 86238 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 10183 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 34861 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 119032 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 153893 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 21020629 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 4306114 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 209967 # Number of squashed instructions skipped in execute
2010,2026c2008,2024
< system.cpu1.iew.exec_nop 40890 # number of nop insts executed
< system.cpu1.iew.exec_refs 17028825 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 11888375 # Number of branches executed
< system.cpu1.iew.exec_stores 6698707 # Number of stores executed
< system.cpu1.iew.exec_rate 0.506131 # Inst execution rate
< system.cpu1.iew.wb_sent 53782194 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 52199995 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 25393405 # num instructions producing a value
< system.cpu1.iew.wb_consumers 38775074 # num instructions consuming a value
< system.cpu1.iew.wb_rate 0.489935 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.654890 # average fanout of values written-back
< system.cpu1.commit.commitSquashedInsts 3417074 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 542844 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 157272 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 103878319 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.494591 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.150147 # Number of insts commited each cycle
---
> system.cpu1.iew.exec_nop 41057 # number of nop insts executed
> system.cpu1.iew.exec_refs 7931495 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 3060021 # Number of branches executed
> system.cpu1.iew.exec_stores 3625381 # Number of stores executed
> system.cpu1.iew.exec_rate 0.602533 # Inst execution rate
> system.cpu1.iew.wb_sent 20889464 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 20791352 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 10424214 # num instructions producing a value
> system.cpu1.iew.wb_consumers 16342751 # num instructions consuming a value
> system.cpu1.iew.wb_rate 0.595961 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.637849 # average fanout of values written-back
> system.cpu1.commit.commitSquashedInsts 1830942 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 516700 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 142734 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 33726190 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.592855 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.351829 # Number of insts commited each cycle
2028,2036c2026,2034
< system.cpu1.commit.committed_per_cycle::0 77963106 75.05% 75.05% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 14542376 14.00% 89.05% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 6113605 5.89% 94.94% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 710011 0.68% 95.62% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1999110 1.92% 97.55% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 1749013 1.68% 99.23% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 272868 0.26% 99.49% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 126868 0.12% 99.61% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 401362 0.39% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 24181138 71.70% 71.70% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 5602280 16.61% 88.31% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 1689893 5.01% 93.32% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 666101 1.98% 95.30% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 523339 1.55% 96.85% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 342031 1.01% 97.86% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 220744 0.65% 98.52% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 118908 0.35% 98.87% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 381756 1.13% 100.00% # Number of insts commited each cycle
2040,2042c2038,2040
< system.cpu1.commit.committed_per_cycle::total 103878319 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 41730387 # Number of instructions committed
< system.cpu1.commit.committedOps 51377304 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 33726190 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 16334743 # Number of instructions committed
> system.cpu1.commit.committedOps 19994748 # Number of ops (including micro ops) committed
2044,2047c2042,2045
< system.cpu1.commit.refs 16644430 # Number of memory references committed
< system.cpu1.commit.loads 10032420 # Number of loads committed
< system.cpu1.commit.membars 210881 # Number of memory barriers committed
< system.cpu1.commit.branches 11730295 # Number of branches committed
---
> system.cpu1.commit.refs 7578069 # Number of memory references committed
> system.cpu1.commit.loads 4036103 # Number of loads committed
> system.cpu1.commit.membars 208295 # Number of memory barriers committed
> system.cpu1.commit.branches 2905369 # Number of branches committed
2049,2050c2047,2048
< system.cpu1.commit.int_insts 46164743 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 3380868 # Number of function calls committed.
---
> system.cpu1.commit.int_insts 17763800 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 462325 # Number of function calls committed.
2052,2082c2050,2080
< system.cpu1.commit.op_class_0::IntAlu 34684147 67.51% 67.51% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 45398 0.09% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 3329 0.01% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 10032420 19.53% 87.13% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 6612010 12.87% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 12386323 61.95% 61.95% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 27065 0.14% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 3291 0.02% 62.10% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 4036103 20.19% 82.29% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 3541966 17.71% 100.00% # Class of committed instruction
2085,2100c2083,2098
< system.cpu1.commit.op_class_0::total 51377304 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 401362 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 138158228 # The number of ROB reads
< system.cpu1.rob.rob_writes 111482281 # The number of ROB writes
< system.cpu1.timesIdled 55620 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 764182 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 5544797786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 41697532 # Number of Instructions Simulated
< system.cpu1.committedOps 51344449 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 2.555182 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 2.555182 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.391362 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.391362 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 56568285 # number of integer regfile reads
< system.cpu1.int_regfile_writes 35909809 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 1388 # number of floating regfile reads
---
> system.cpu1.commit.op_class_0::total 19994748 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 381756 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 54190677 # The number of ROB reads
> system.cpu1.rob.rob_writes 44052640 # The number of ROB writes
> system.cpu1.timesIdled 55343 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 750940 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 5616474700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 16301888 # Number of Instructions Simulated
> system.cpu1.committedOps 19961893 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 2.140066 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 2.140066 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.467275 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.467275 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads
> system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads
2102,2198c2100,2196
< system.cpu1.cc_regfile_reads 192177585 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 15728126 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 146901400 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 390692 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 191412 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 467.958660 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 15830019 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 191751 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 82.555079 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 89229031500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.958660 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913982 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.913982 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 33166441 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 33166441 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 9618480 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 9618480 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 5953541 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 5953541 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50151 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 50151 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79497 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 79497 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71560 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 71560 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 15572021 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 15572021 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 15622172 # number of overall hits
< system.cpu1.dcache.overall_hits::total 15622172 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 219751 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 219751 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 400027 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 400027 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30362 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 30362 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18466 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 18466 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23631 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23631 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 619778 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 619778 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 650140 # number of overall misses
< system.cpu1.dcache.overall_misses::total 650140 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3494026000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 3494026000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9769416956 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 9769416956 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360558000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 360558000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 577732000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 577732000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 853500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 853500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 13263442956 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 13263442956 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 13263442956 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 13263442956 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 9838231 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 9838231 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 6353568 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 6353568 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80513 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 80513 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97963 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 97963 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95191 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 95191 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 16191799 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 16191799 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 16272312 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 16272312 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022336 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.022336 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062961 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.062961 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377107 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377107 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188500 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188500 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248248 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248248 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038277 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.038277 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039954 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.039954 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15899.932196 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15899.932196 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24421.893912 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 24421.893912 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19525.506336 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19525.506336 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24448.055520 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24448.055520 # average StoreCondReq miss latency
---
> system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 50047969 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 189214 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70537 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 70537 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 6546274 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 6546274 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 6595167 # number of overall hits
> system.cpu1.dcache.overall_hits::total 6595167 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 215923 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 215923 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 399880 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 399880 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30250 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 30250 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18610 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 18610 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23458 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23458 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 615803 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 615803 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 646053 # number of overall misses
> system.cpu1.dcache.overall_misses::total 646053 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3499498000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3499498000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10163021954 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 10163021954 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366635500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 366635500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572131000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 572131000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1270000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1270000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 13662519954 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 13662519954 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 13662519954 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 13662519954 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 3846750 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3846750 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 3315327 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 3315327 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79143 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 79143 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96738 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 96738 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93995 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 93995 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 7162077 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 7162077 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 7241220 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 7241220 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056131 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.056131 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120616 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.120616 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382220 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382220 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192375 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192375 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249566 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249566 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085981 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.085981 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089219 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.089219 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16207.157181 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16207.157181 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25415.179439 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 25415.179439 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19700.994089 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19700.994089 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24389.589905 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24389.589905 # average StoreCondReq miss latency
2201,2286c2199,2284
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21400.312622 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 21400.312622 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20400.902815 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 20400.902815 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 1422803 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 40164 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.633333 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 35.424833 # average number of cycles each access was blocked
< system.cpu1.dcache.writebacks::writebacks 191413 # number of writebacks
< system.cpu1.dcache.writebacks::total 191413 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80045 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 80045 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309351 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 309351 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13126 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13126 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 389396 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 389396 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 389396 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 389396 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139706 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 139706 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90676 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 90676 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28955 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 28955 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5340 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5340 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23631 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23631 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 230382 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 230382 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 259337 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 259337 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14528 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14528 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11864 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26392 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1929657000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1929657000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2407624467 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2407624467 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488405000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488405000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91592000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91592000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 554116000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 554116000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 838500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 838500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4337281467 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4337281467 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4825686467 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4825686467 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2529035000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2529035000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2529035000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2529035000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014200 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014272 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014272 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359631 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359631 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054510 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054510 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248248 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248248 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014228 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.014228 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015937 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.015937 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13812.270053 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13812.270053 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26551.948333 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26551.948333 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16867.725781 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16867.725781 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17152.059925 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17152.059925 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23448.690280 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23448.690280 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22186.510871 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 22186.510871 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21147.676667 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 21147.676667 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 397 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 1522509 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 39 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 40277 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10.179487 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 37.800953 # average number of cycles each access was blocked
> system.cpu1.dcache.writebacks::writebacks 189214 # number of writebacks
> system.cpu1.dcache.writebacks::total 189214 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79118 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 79118 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 308913 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 308913 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13245 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13245 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 388031 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 388031 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 388031 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 388031 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136805 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 136805 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90967 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 90967 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28906 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 28906 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5365 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5365 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23458 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23458 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 227772 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 227772 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 256678 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 256678 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3078 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5513 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1918091000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1918091000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2479606465 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2479606465 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 495967500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 495967500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96498000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96498000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548698000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548698000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1245000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1245000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4397697465 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4397697465 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4893664965 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4893664965 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 441985000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 441985000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 441985000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 441985000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035564 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035564 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027438 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365238 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365238 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055459 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055459 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249566 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249566 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031803 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031803 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14020.620591 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14020.620591 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.307573 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.307573 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17157.942988 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17157.942988 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17986.579683 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17986.579683 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23390.655640 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23390.655640 # average StoreCondReq mshr miss latency
2289,2303c2287,2301
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18826.477186 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18826.477186 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18607.782411 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18607.782411 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174080.052313 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174080.052313 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95825.818430 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95825.818430 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.replacements 601488 # number of replacements
< system.cpu1.icache.tags.tagsinuse 499.448304 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 43094812 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 602000 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 71.586066 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 79058224000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448304 # Average occupied blocks per requestor
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.replacements 585593 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor
2307,2308c2305,2306
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
2310,2367c2308,2365
< system.cpu1.icache.tags.tag_accesses 88040802 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 88040802 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 43094812 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 43094812 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 43094812 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 43094812 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 43094812 # number of overall hits
< system.cpu1.icache.overall_hits::total 43094812 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 624586 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 624586 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 624586 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 624586 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 624586 # number of overall misses
< system.cpu1.icache.overall_misses::total 624586 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5619455793 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 5619455793 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 5619455793 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 5619455793 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 5619455793 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 5619455793 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 43719398 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 43719398 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 43719398 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 43719398 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 43719398 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 43719398 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014286 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.014286 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014286 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.014286 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014286 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.014286 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8997.088941 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8997.088941 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8997.088941 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8997.088941 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 497106 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 2 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 41763 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.903024 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked
< system.cpu1.icache.writebacks::writebacks 601488 # number of writebacks
< system.cpu1.icache.writebacks::total 601488 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22580 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 22580 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 22580 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 22580 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 22580 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 22580 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 602006 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 602006 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 602006 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 602006 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 602006 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 602006 # number of overall MSHR misses
---
> system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 7643805 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 7643805 # number of overall hits
> system.cpu1.icache.overall_hits::total 7643805 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 608184 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 608184 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 608184 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 608184 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 608184 # number of overall misses
> system.cpu1.icache.overall_misses::total 608184 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5475305711 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 5475305711 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 5475305711 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 5475305711 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 5475305711 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 5475305711 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 8251989 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 8251989 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 8251989 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 8251989 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 8251989 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 8251989 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073702 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.073702 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073702 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.073702 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073702 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.073702 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9002.712520 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 9002.712520 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 9002.712520 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 9002.712520 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 487413 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 41153 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.843924 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu1.icache.writebacks::writebacks 585593 # number of writebacks
> system.cpu1.icache.writebacks::total 585593 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22069 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 22069 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 22069 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 22069 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 22069 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 22069 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586115 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 586115 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 586115 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 586115 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 586115 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 586115 # number of overall MSHR misses
2372,2400c2370,2398
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5157000587 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5157000587 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5157000587 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5157000587 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5157000587 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5157000587 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9463000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9463000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9463000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 9463000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013770 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.013770 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.013770 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8566.360779 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92774.509804 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92774.509804 # average overall mshr uncacheable latency
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 196563 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 197115 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 493 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5018314097 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5018314097 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5018314097 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5018314097 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5018314097 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5018314097 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9229000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9229000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9229000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 9229000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071027 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.071027 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.071027 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8561.995678 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue
2403,2408c2401,2406
< system.cpu1.l2cache.prefetcher.pfSpanPage 59469 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 47848 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15152.810983 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 1369588 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 62482 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 21.919721 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 51951 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 66549 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 19.998678 # Average number of references to valid blocks.
2410,2415c2408,2413
< system.cpu1.l2cache.tags.occ_blocks::writebacks 14657.752176 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.247040 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.961226 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 482.850541 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.894638 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000564 # Average percentage of cache occupancy
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 14780.960176 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.872611 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.970486 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 470.415625 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.902158 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000969 # Average percentage of cache occupancy
2417,2425c2415,2423
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.029471 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.924854 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1015 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13588 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 873 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 127 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028712 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.932020 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13541 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 11 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 870 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 142 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
2427,2540c2425,2538
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8865 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4269 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.061951 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001892 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.829346 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 27297276 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 27297276 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17323 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6382 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 23705 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 116494 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 116494 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 663845 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 663845 # number of WritebackClean hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27330 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 27330 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 585501 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 585501 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 105069 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 105069 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17323 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6382 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 585501 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 132399 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 741605 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17323 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6382 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 585501 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 132399 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 741605 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 251 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 687 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29837 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29837 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23628 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 23628 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34183 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 34183 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16502 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 16502 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68911 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 68911 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 251 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 16502 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 103094 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 120283 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 251 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 16502 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 103094 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 120283 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9535000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5307000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 14842000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65279500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 65279500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 35645500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 35645500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 815499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 815499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382048000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1382048000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 678918000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 678918000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1543279999 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1543279999 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9535000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5307000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 678918000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 2925327999 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 3619087999 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9535000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5307000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 678918000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 2925327999 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 3619087999 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17759 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6633 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 116494 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 116494 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 663845 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 663845 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29837 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 29837 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23628 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23628 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61513 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 61513 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 602003 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 602003 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 173980 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 173980 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17759 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6633 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 602003 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 235493 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 861888 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17759 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6633 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 602003 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 235493 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 861888 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037841 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.028165 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4388 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 115107 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 115107 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 647294 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 647294 # number of WritebackClean hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27150 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 27150 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570057 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 570057 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101740 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 101740 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16755 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6229 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 570057 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 128890 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 721931 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16755 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6229 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 570057 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 128890 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 721931 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 448 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 691 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29892 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29892 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23453 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 23453 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34596 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 34596 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16047 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 16047 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69320 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 69320 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 448 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 16047 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 103916 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 120654 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 448 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 16047 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 103916 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 120654 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9860500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5063000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 14923500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63584500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 63584500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 34923000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 34923000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1206498 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1206498 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1459821998 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1459821998 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658205000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658205000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1571289999 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1571289999 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9860500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5063000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658205000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3031111997 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3704240497 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9860500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5063000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658205000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3031111997 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3704240497 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17203 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6472 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 23675 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 115107 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 115107 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 647294 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 647294 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29892 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 29892 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23453 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23453 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61746 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 61746 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 586104 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 586104 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171060 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 171060 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17203 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6472 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 586104 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 232806 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 842585 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17203 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6472 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 586104 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 232806 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 842585 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037546 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.029187 # miss rate for ReadReq accesses
2547,2588c2545,2586
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555704 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555704 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027412 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027412 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.396086 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.396086 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037841 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027412 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.437779 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.139558 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037841 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027412 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.437779 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.139558 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21143.426295 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21604.075691 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2187.870764 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2187.870764 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1508.612663 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1508.612663 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 271833 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 271833 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40430.857444 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40430.857444 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41141.558599 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41141.558599 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22395.263441 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22395.263441 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21143.426295 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41141.558599 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28375.346761 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 30088.108868 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21143.426295 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41141.558599 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28375.346761 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 30088.108868 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560295 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560295 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027379 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027379 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405238 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405238 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037546 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027379 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446363 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.143195 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037546 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027379 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446363 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.143195 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.390947 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21596.960926 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2127.141041 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2127.141041 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1489.063233 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1489.063233 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 241299.600000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 241299.600000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42196.265406 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42196.265406 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41017.324110 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41017.324110 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22667.195600 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22667.195600 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 30701.348459 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 30701.348459 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked
2590c2588
< system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked
2592c2590
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 25.666667 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked
2594,2636c2592,2634
< system.cpu1.l2cache.unused_prefetches 878 # number of HardPF blocks evicted w/o reference
< system.cpu1.l2cache.writebacks::writebacks 32705 # number of writebacks
< system.cpu1.l2cache.writebacks::total 32705 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 447 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 447 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 70 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 70 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 517 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 526 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 517 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 526 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 436 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 251 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25391 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 25391 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29837 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29837 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23628 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23628 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33736 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 33736 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16493 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16493 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68841 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68841 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 436 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 251 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16493 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102577 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 119757 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 436 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 251 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16493 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102577 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25391 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 145148 # number of overall MSHR misses
---
> system.cpu1.l2cache.unused_prefetches 821 # number of HardPF blocks evicted w/o reference
> system.cpu1.l2cache.writebacks::writebacks 37285 # number of writebacks
> system.cpu1.l2cache.writebacks::total 37285 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 573 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 573 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 647 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 651 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 647 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 651 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 448 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 691 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 27204 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29892 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29892 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23453 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23453 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34023 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 34023 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16043 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16043 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69246 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69246 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 448 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16043 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103269 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 120003 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 448 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16043 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103269 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 147207 # number of overall MSHR misses
2638,2641c2636,2639
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14528 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14630 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11864 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3180 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable
2643,2681c2641,2679
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26494 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3801000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10720000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1003077137 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 504358500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 504358500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 376609000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 376609000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 725499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 725499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1128947000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1128947000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 579803500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 579803500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1128190999 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1128190999 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3801000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 579803500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2257137999 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 2847661499 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3801000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 579803500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2257137999 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 3850738636 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8698000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412762500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2421460500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8698000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412762500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2421460500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028165 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5615 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3605000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10777500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1221222561 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 499462500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 499462500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 372532500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 372532500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1056498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1056498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1184971500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1184971500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 561881000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 561881000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1153728499 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1153728499 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3605000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 561881000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2338699999 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 2911358499 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3605000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 561881000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2338699999 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4132581060 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8464000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417313000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 425777000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8464000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417313000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 425777000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029187 # mshr miss rate for ReadReq accesses
2690,2704c2688,2702
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548437 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548437 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027397 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.395683 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.395683 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138947 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551015 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551015 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027372 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404805 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404805 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142422 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for overall accesses
2706,2778c2704,2776
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168407 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15604.075691 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39505.223780 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16903.793947 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16903.793947 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15939.097681 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15939.097681 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 241833 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 241833 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33464.162912 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33464.162912 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35154.520099 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16388.358667 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16388.358667 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23778.664287 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26529.739549 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166076.713932 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165513.362953 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91420.222037 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91396.561486 # average overall mshr uncacheable latency
< system.cpu1.toL2Bus.snoop_filter.tot_requests 1693819 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 856333 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 183235 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 181854 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1381 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 43509 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 857970 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 11864 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 11864 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 150213 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 676407 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 108999 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 30864 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 72606 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41945 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 86317 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 68814 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 66024 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 602006 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 255355 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 206 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1805701 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 897982 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14680 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38591 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2756954 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 77025056 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30176714 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26532 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71036 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 107299338 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 403916 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1269906 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.163115 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.372403 # Request fanout histogram
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174709 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15596.960926 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44891.286612 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16708.902047 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16708.902047 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15884.215239 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15884.215239 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 211299.600000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 211299.600000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34828.542457 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34828.542457 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35023.437013 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16661.301721 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16661.301721 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24260.714307 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28073.264587 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135579.272255 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133892.138365 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency
> system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 71200 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41639 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 86222 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 68548 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 66385 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586115 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 251518 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 256 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1758016 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 847991 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14492 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37672 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2658171 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74990240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29751886 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68812 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 104836826 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 408149 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1234265 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.169046 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.379975 # Request fanout histogram
2780,2782c2778,2780
< system.cpu1.toL2Bus.snoop_fanout::0 1064146 83.80% 83.80% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 204379 16.09% 99.89% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 1381 0.11% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 1028032 83.29% 83.29% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 203819 16.51% 99.80% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 2414 0.20% 100.00% # Request fanout histogram
2786,2787c2784,2785
< system.cpu1.toL2Bus.snoop_fanout::total 1269906 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1668457495 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1234265 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1616622989 # Layer occupancy (ticks)
2789c2787
< system.cpu1.toL2Bus.snoopLayer0.occupancy 80964876 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 80296887 # Layer occupancy (ticks)
2791c2789
< system.cpu1.toL2Bus.respLayer0.occupancy 903243234 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks)
2793c2791
< system.cpu1.toL2Bus.respLayer1.occupancy 401728937 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks)
2795c2793
< system.cpu1.toL2Bus.respLayer2.occupancy 8056980 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks)
2797c2795
< system.cpu1.toL2Bus.respLayer3.occupancy 20851461 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks)
2799,2800c2797,2798
< system.iobus.trans_dist::ReadReq 31007 # Transaction distribution
< system.iobus.trans_dist::ReadResp 31007 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
> system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
2823,2825c2821,2823
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 180856 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes)
2846,2849c2844,2847
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2484002 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 40382501 # Layer occupancy (ticks)
2853c2851
< system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks)
2855c2853
< system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
2857c2855
< system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks)
2859c2857
< system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
2861c2859
< system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 582000 # Layer occupancy (ticks)
2863c2861
< system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks)
2865c2863
< system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2867c2865
< system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2873c2871
< system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
2881c2879
< system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
2883c2881
< system.iobus.reqLayer23.occupancy 6116000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6099000 # Layer occupancy (ticks)
2885c2883
< system.iobus.reqLayer24.occupancy 33795000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks)
2887c2885
< system.iobus.reqLayer25.occupancy 187654365 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks)
2891c2889
< system.iobus.respLayer3.occupancy 36766000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2893,2894c2891,2892
< system.iocache.tags.replacements 36453 # number of replacements
< system.iocache.tags.tagsinuse 14.555427 # Cycle average of tags in use
---
> system.iocache.tags.replacements 36458 # number of replacements
> system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use
2896c2894
< system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2898,2901c2896,2899
< system.iocache.tags.warmup_cycle 255133996000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.555427 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.909714 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.909714 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy
2905,2908c2903,2906
< system.iocache.tags.tag_accesses 328239 # Number of tag accesses
< system.iocache.tags.data_accesses 328239 # Number of data accesses
< system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 247 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 328284 # Number of tag accesses
> system.iocache.tags.data_accesses 328284 # Number of data accesses
> system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2911,2924c2909,2922
< system.iocache.demand_misses::realview.ide 36471 # number of demand (read+write) misses
< system.iocache.demand_misses::total 36471 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 36471 # number of overall misses
< system.iocache.overall_misses::total 36471 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ide 32034877 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 32034877 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4302643488 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4302643488 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4334678365 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4334678365 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4334678365 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4334678365 # number of overall miss cycles
< system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36476 # number of overall misses
> system.iocache.overall_misses::total 36476 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ide 32586377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 32586377 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4303595229 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4303595229 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4336181606 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4336181606 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4336181606 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4336181606 # number of overall miss cycles
> system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2927,2930c2925,2928
< system.iocache.demand_accesses::realview.ide 36471 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 36471 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 36471 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 36471 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
2939,2946c2937,2944
< system.iocache.ReadReq_avg_miss_latency::realview.ide 129695.858300 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 129695.858300 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118778.806537 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118778.806537 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 118852.742316 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 118852.742316 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 129311.019841 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 129311.019841 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.080306 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118805.080306 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 118877.662189 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 118877.662189 # average overall miss latency
2955,2956c2953,2954
< system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
2959,2970c2957,2968
< system.iocache.demand_mshr_misses::realview.ide 36471 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 36471 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 36471 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 36471 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 19684877 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 19684877 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489128459 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2489128459 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2508813336 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2508813336 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2508813336 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2508813336 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 19986377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 19986377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490041664 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2490041664 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2510028041 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2510028041 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2510028041 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2510028041 # number of overall MSHR miss cycles
2979,2991c2977,2989
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79695.858300 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 79695.858300 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68714.897830 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68714.897830 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency
< system.l2c.tags.replacements 126939 # number of replacements
< system.l2c.tags.tagsinuse 63214.740893 # Cycle average of tags in use
< system.l2c.tags.total_refs 439035 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 190800 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.301022 # Average number of references to valid blocks.
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency
> system.l2c.tags.replacements 132778 # number of replacements
> system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use
> system.l2c.tags.total_refs 444088 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks.
2993,3005c2991,3003
< system.l2c.tags.occ_blocks::writebacks 13659.794415 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.383881 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061858 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 8032.623601 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 2877.626716 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34705.867730 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.664427 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910014 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1967.326736 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 460.362743 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1490.118772 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.208432 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000235 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065836 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 8064.380543 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 2772.729395 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33768.581689 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.679196 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910017 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1783.108864 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 674.072360 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2431.451744 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.208824 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000250 # Average percentage of cache occupancy
3007,3010c3005,3008
< system.l2c.tags.occ_percent::cpu0.inst 0.122568 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.043909 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.529570 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000056 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.inst 0.123053 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.042308 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.515268 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy
3012,3024c3010,3021
< system.l2c.tags.occ_percent::cpu1.inst 0.030019 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.007025 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022737 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.964580 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 29285 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 34558 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 5757 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 23342 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
---
> system.l2c.tags.occ_percent::cpu1.inst 0.027208 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.010286 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.037101 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.964414 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 29279 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 34582 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 180 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 5628 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 23471 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id
3026,3088c3023,3085
< system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 6476 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 27436 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.446854 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000275 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.527313 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6030021 # Number of tag accesses
< system.l2c.tags.data_accesses 6030021 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 261794 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 261794 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 32586 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 2322 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 34908 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 2057 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 1031 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 3088 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 3923 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1723 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5646 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 188 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 73 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 32795 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 46613 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46486 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 68 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 36 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 13556 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 9028 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5103 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 153946 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 188 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 73 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 32795 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 50536 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 46486 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 13556 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 10751 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 5103 # number of demand (read+write) hits
< system.l2c.demand_hits::total 159592 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 188 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 73 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 32795 # number of overall hits
< system.l2c.overall_hits::cpu0.data 50536 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 46486 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 13556 # number of overall hits
< system.l2c.overall_hits::cpu1.data 10751 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 5103 # number of overall hits
< system.l2c.overall_hits::total 159592 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 9262 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3049 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 12311 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 797 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1327 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 2124 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11181 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 8169 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 19350 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses
---
> system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6131058 # Number of tag accesses
> system.l2c.tags.data_accesses 6131058 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4036 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 163 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 33190 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 46982 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46066 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 73 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 13227 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 9835 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5456 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 155096 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 163 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 33190 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 51018 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 46066 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 73 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 13227 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 11214 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 5456 # number of demand (read+write) hits
> system.l2c.demand_hits::total 160511 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 163 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 33190 # number of overall hits
> system.l2c.overall_hits::cpu0.data 51018 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 46066 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 73 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 13227 # number of overall hits
> system.l2c.overall_hits::cpu1.data 11214 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 5456 # number of overall hits
> system.l2c.overall_hits::total 160511 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 8984 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 2771 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 11755 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1290 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11642 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 8933 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 20575 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses
3090,3093c3087,3090
< system.l2c.ReadSharedReq_misses::cpu0.inst 19352 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 9056 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131166 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 5 # number of ReadSharedReq misses
---
> system.l2c.ReadSharedReq_misses::cpu0.inst 19670 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 9220 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses
3095,3099c3092,3096
< system.l2c.ReadSharedReq_misses::cpu1.inst 2936 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 955 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6696 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 170195 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses
---
> system.l2c.ReadSharedReq_misses::cpu1.inst 2815 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 1145 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 174280 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses
3101,3104c3098,3101
< system.l2c.demand_misses::cpu0.inst 19352 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 20237 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 131166 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 19670 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 20862 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses
3106,3110c3103,3107
< system.l2c.demand_misses::cpu1.inst 2936 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 9124 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 6696 # number of demand (read+write) misses
< system.l2c.demand_misses::total 189545 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses
---
> system.l2c.demand_misses::cpu1.inst 2815 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 10078 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) misses
> system.l2c.demand_misses::total 194855 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses
3112,3115c3109,3112
< system.l2c.overall_misses::cpu0.inst 19352 # number of overall misses
< system.l2c.overall_misses::cpu0.data 20237 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 131166 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 19670 # number of overall misses
> system.l2c.overall_misses::cpu0.data 20862 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 133244 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses
3117,3130c3114,3127
< system.l2c.overall_misses::cpu1.inst 2936 # number of overall misses
< system.l2c.overall_misses::cpu1.data 9124 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 6696 # number of overall misses
< system.l2c.overall_misses::total 189545 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 10685000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 2955500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 13640500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1570500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1260500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 2831000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1150734500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 687988500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1838723000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2363000 # number of ReadSharedReq miss cycles
---
> system.l2c.overall_misses::cpu1.inst 2815 # number of overall misses
> system.l2c.overall_misses::cpu1.data 10078 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 8148 # number of overall misses
> system.l2c.overall_misses::total 194855 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 8725000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 2891500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 11616500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1430000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1143000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 2573000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1196035499 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 747656500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 1943691999 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2599000 # number of ReadSharedReq miss cycles
3132,3141c3129,3138
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1607400500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 824224000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 522500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 83500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 250906500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 89245500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 17878713282 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 2363000 # number of demand (read+write) miss cycles
---
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1635002000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 838941000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 652000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 97500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 242297000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 106324000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 18502691507 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 2599000 # number of demand (read+write) miss cycles
3143,3152c3140,3149
< system.l2c.demand_miss_latency::cpu0.inst 1607400500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1974958500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 522500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 250906500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 777234000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 19717436282 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 2363000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 1635002000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 2034976499 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 652000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 97500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 242297000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 853980500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 20446383506 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 2599000 # number of overall miss cycles
3154,3258c3151,3255
< system.l2c.overall_miss_latency::cpu0.inst 1607400500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1974958500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 522500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 250906500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 777234000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 19717436282 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 261794 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 261794 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 41848 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5371 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 47219 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 2854 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 2358 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 5212 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 15104 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 9892 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 24996 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 213 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 76 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 52147 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 55669 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177652 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 73 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 16492 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 9983 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11799 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 324141 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 213 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 52147 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 70773 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177652 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 73 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 16492 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 19875 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11799 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 349137 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 213 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 52147 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 70773 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177652 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 73 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 16492 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 19875 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11799 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 349137 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.221325 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.567678 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.260721 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.279257 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.562765 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.407521 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.740267 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.825819 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.774124 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.039474 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.371105 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162676 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.027027 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.178026 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.095663 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.525065 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.039474 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.371105 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.285942 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.027027 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.178026 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.459069 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.542896 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.039474 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.371105 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.285942 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.027027 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.178026 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.459069 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.542896 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1153.638523 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 969.334208 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1107.992852 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1970.514429 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 949.886963 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1332.862524 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102918.746087 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84219.427102 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 95024.444444 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 94520 # average ReadSharedReq miss latency
---
> system.l2c.overall_miss_latency::cpu0.inst 1635002000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 2034976499 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 652000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 97500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 242297000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 853980500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 20446383506 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 266860 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 266860 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 41414 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5457 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 46871 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 2664 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 2223 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 4887 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15678 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 10312 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 25990 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 190 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 52860 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 56202 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179310 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 80 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 16042 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 10980 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 13604 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 329376 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 190 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 52860 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 71880 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179310 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 80 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 16042 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 21292 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13604 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 355366 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 190 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 52860 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 71880 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179310 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 80 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 16042 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 21292 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13604 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 355366 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.216931 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.507788 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.250795 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.245871 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.580297 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.397995 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.742569 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.866272 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.791651 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.038462 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.372115 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.164051 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.033333 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.175477 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.104281 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.529122 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.038462 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.372115 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.290234 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.033333 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.175477 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.473323 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.548322 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.038462 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.372115 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.290234 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.033333 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.175477 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.473323 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.548322 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 971.170971 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1043.486106 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 988.217780 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2183.206107 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 886.046512 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1322.879177 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102734.538653 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83696.014777 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 94468.626926 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average ReadSharedReq miss latency
3260,3269c3257,3266
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83061.208144 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91014.134276 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 104500 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85458.617166 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93450.785340 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 105048.404959 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 94520 # average overall miss latency
---
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83121.606507 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90991.431670 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 97500 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86073.534636 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92859.388646 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 106166.464924 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency
3271,3280c3268,3277
< system.l2c.demand_avg_miss_latency::cpu0.inst 83061.208144 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 97591.466126 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 85458.617166 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 85185.664182 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 104025.093155 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 94520 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 104931.274568 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency
3282,3291c3279,3288
< system.l2c.overall_avg_miss_latency::cpu0.inst 83061.208144 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 97591.466126 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 85458.617166 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 85185.664182 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 104025.093155 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 838 # number of cycles access was blocked
---
> system.l2c.overall_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 104931.274568 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 21 # number of cycles access was blocked
3293c3290
< system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked
3295c3292
< system.l2c.avg_blocked_cycles::no_mshrs 104.750000 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
3297,3319c3294,3316
< system.l2c.writebacks::writebacks 99614 # number of writebacks
< system.l2c.writebacks::total 99614 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 7 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3468 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3468 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 9262 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 3049 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 12311 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 797 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1327 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 2124 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11181 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 8169 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 19350 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadSharedReq MSHR misses
---
> system.l2c.writebacks::writebacks 103743 # number of writebacks
> system.l2c.writebacks::total 103743 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 3708 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 3708 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8984 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 2771 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 11755 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1290 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1945 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11642 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 8933 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 20575 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses
3321,3324c3318,3321
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19350 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9056 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadSharedReq MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19662 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9220 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses
3326,3330c3323,3327
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2929 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 955 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 170186 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2807 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1145 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 174264 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses
3332,3335c3329,3332
< system.l2c.demand_mshr_misses::cpu0.inst 19350 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 20237 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 19662 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 20862 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses
3337,3341c3334,3338
< system.l2c.demand_mshr_misses::cpu1.inst 2929 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 9124 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 189536 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.inst 2807 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 10078 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 194839 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses
3343,3346c3340,3343
< system.l2c.overall_mshr_misses::cpu0.inst 19350 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 20237 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 19662 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 20862 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses
3348,3351c3345,3348
< system.l2c.overall_mshr_misses::cpu1.inst 2929 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 9124 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 189536 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu1.inst 2807 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 10078 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 194839 # number of overall MSHR misses
3353c3350
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable
3355,3359c3352,3356
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14525 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 37970 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 30897 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 37951 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 30885 # number of WriteReq MSHR uncacheable
3361c3358
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses
3363,3374c3360,3371
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26389 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 68867 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 221469500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 70279500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 291749000 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20549499 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32977500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 53526999 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1038924500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606298001 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 1645222501 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5510 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 68836 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213623000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63075000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 276698000 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16864000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32149500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 49013500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1079614502 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 658325502 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 1737940004 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of ReadSharedReq MSHR miss cycles
3376,3385c3373,3382
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1413871007 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 733663501 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 472500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 221234502 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 79695500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 16176437301 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1437895505 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 746740501 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 582000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 87500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 213731003 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 94873501 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 16759063028 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of demand (read+write) MSHR miss cycles
3387,3396c3384,3393
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1413871007 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 1772588001 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 472500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 221234502 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 685993501 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 17821659802 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1437895505 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 1826355003 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 582000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 87500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 213731003 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 753199003 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 18497003032 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of overall MSHR miss cycles
3398,3406c3395,3403
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1413871007 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 1772588001 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 472500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 221234502 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 685993501 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 17821659802 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1437895505 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 1826355003 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 582000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 87500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 213731003 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 753199003 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 18497003032 # number of overall MSHR miss cycles
3408,3411c3405,3408
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4005508001 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6861000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2151256501 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 6356192002 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5794669001 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6627000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 361914000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6355776501 # number of ReadReq MSHR uncacheable cycles
3413,3416c3410,3413
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005508001 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6861000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2151256501 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 6356192002 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5794669001 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6627000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 361914000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6355776501 # number of overall MSHR uncacheable cycles
3419,3470c3416,3467
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.221325 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.567678 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.260721 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.279257 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.562765 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.407521 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.740267 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.825819 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.774124 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162676 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.095663 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.525037 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.285942 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.459069 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.542870 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.285942 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.459069 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.542870 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23911.628158 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23050.016399 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23698.237349 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25783.562108 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24851.168048 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25201.035311 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92918.746087 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74219.366018 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 85024.418656 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average ReadSharedReq mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.216931 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.507788 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.250795 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.245871 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.580297 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.397995 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742569 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866272 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.791651 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.164051 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.104281 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.529073 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.548277 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.548277 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23778.161175 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22762.540599 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23538.749468 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25746.564885 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24922.093023 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25199.742931 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92734.453015 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73695.903056 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 84468.529964 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average ReadSharedReq mshr miss latency
3472,3481c3469,3478
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81014.079174 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83450.785340 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95051.515994 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency
---
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80991.377549 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82858.952838 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96170.540261 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency
3483,3492c3480,3489
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency
3494,3502c3491,3499
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency
3504,3507c3501,3504
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196927.630334 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148107.160138 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167400.368765 # average ReadReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182388.624878 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117695.609756 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167473.228663 # average ReadReq mshr uncacheable latency
3509,3515c3506,3512
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101732.354685 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81520.955739 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 92296.629765 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 514606 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 294659 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96223.393849 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3519,3526c3516,3523
< system.membus.trans_dist::ReadReq 37970 # Transaction distribution
< system.membus.trans_dist::ReadResp 208402 # Transaction distribution
< system.membus.trans_dist::WriteReq 30897 # Transaction distribution
< system.membus.trans_dist::WriteResp 30897 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 135820 # Transaction distribution
< system.membus.trans_dist::CleanEvict 15995 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 76425 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 40810 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 37951 # Transaction distribution
> system.membus.trans_dist::ReadResp 212466 # Transaction distribution
> system.membus.trans_dist::WriteReq 30885 # Transaction distribution
> system.membus.trans_dist::WriteResp 30885 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution
> system.membus.trans_dist::CleanEvict 17155 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution
3528,3531c3525,3528
< system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
< system.membus.trans_dist::ReadExReq 38865 # Transaction distribution
< system.membus.trans_dist::ReadExResp 19252 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 170433 # Transaction distribution
---
> system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
> system.membus.trans_dist::ReadExReq 40333 # Transaction distribution
> system.membus.trans_dist::ReadExResp 20490 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 174516 # Transaction distribution
3535,3540c3532,3537
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13670 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 646867 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 768487 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 841426 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13608 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661161 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 782719 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 855668 # Packet count per connected master and slave (bytes)
3543,3545c3540,3542
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27340 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18547336 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 18737758 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27216 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19151816 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 19342114 # Cumulative packet size per connected master and slave (bytes)
3548,3552c3545,3549
< system.membus.pkt_size::total 21055902 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 122883 # Total snoops (count)
< system.membus.snoop_fanout::samples 431628 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.011899 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.108432 # Request fanout histogram
---
> system.membus.pkt_size::total 21660258 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 122014 # Total snoops (count)
> system.membus.snoop_fanout::samples 435296 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.011884 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.108364 # Request fanout histogram
3554,3555c3551,3552
< system.membus.snoop_fanout::0 426492 98.81% 98.81% # Request fanout histogram
< system.membus.snoop_fanout::1 5136 1.19% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 430123 98.81% 98.81% # Request fanout histogram
> system.membus.snoop_fanout::1 5173 1.19% 100.00% # Request fanout histogram
3560,3561c3557,3558
< system.membus.snoop_fanout::total 431628 # Request fanout histogram
< system.membus.reqLayer0.occupancy 81611500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 435296 # Request fanout histogram
> system.membus.reqLayer0.occupancy 81593499 # Layer occupancy (ticks)
3565c3562
< system.membus.reqLayer2.occupancy 11561000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks)
3567c3564
< system.membus.reqLayer5.occupancy 995379161 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks)
3569c3566
< system.membus.respLayer2.occupancy 1093943847 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks)
3571c3568
< system.membus.respLayer3.occupancy 1316877 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks)
3614,3644c3611,3641
< system.toL2Bus.snoop_filter.tot_requests 1005681 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 545297 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 156423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 20020 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 19070 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 950 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 37973 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 482978 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30897 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30897 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 361408 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 120637 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 111235 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 43898 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 155133 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 50623 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 50623 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 445008 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 4567 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1196695 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 348487 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1545182 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34087104 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5287070 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 39374174 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 380983 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 851193 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.382254 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.488230 # Request fanout histogram
---
> system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 153354 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 51065 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 51065 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 447881 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 4599 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241884 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315944 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1557828 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34423168 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674082 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 40097250 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 382843 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 858573 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.374933 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.486434 # Request fanout histogram
3646,3648c3643,3645
< system.toL2Bus.snoop_fanout::0 526771 61.89% 61.89% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 323472 38.00% 99.89% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 950 0.11% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 537636 62.62% 62.62% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 319967 37.27% 99.89% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 970 0.11% 100.00% # Request fanout histogram
3652,3653c3649,3650
< system.toL2Bus.snoop_fanout::total 851193 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 876200249 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 858573 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 885446562 # Layer occupancy (ticks)
3655c3652
< system.toL2Bus.snoopLayer0.occupancy 348123 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
3657c3654
< system.toL2Bus.respLayer0.occupancy 630764010 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 647873032 # Layer occupancy (ticks)
3659c3656
< system.toL2Bus.respLayer1.occupancy 246030993 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 232753441 # Layer occupancy (ticks)
3662c3659
< system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed
3664c3661
< system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 2763 # number of quiesce instructions executed