Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

Deleted Added

sdiff udiff text old ( 11281:953f7d1cc9e3 ) new ( 11336:b318499f676c )

full compact

3,5c3,5
< sim_seconds 2.827515 # Number of seconds simulated
< sim_ticks 2827514981500 # Number of ticks simulated
< final_tick 2827514981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.827476 # Number of seconds simulated
> sim_ticks 2827475548000 # Number of ticks simulated
> final_tick 2827475548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 72486 # Simulator instruction rate (inst/s)
< host_op_rate 87933 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1706351372 # Simulator tick rate (ticks/s)
< host_mem_usage 605296 # Number of bytes of host memory used
< host_seconds 1657.05 # Real time elapsed on the host
< sim_insts 120112531 # Number of instructions simulated
< sim_ops 145708890 # Number of ops (including micro ops) simulated
---
> host_inst_rate 107187 # Simulator instruction rate (inst/s)
> host_op_rate 130034 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2524753544 # Simulator tick rate (ticks/s)
> host_mem_usage 623308 # Number of bytes of host memory used
> host_seconds 1119.90 # Real time elapsed on the host
> sim_insts 120039450 # Number of instructions simulated
> sim_ops 145624845 # Number of ops (including micro ops) simulated
16,25c16,24
< system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 1298880 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1333736 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8603840 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 183536 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 661460 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 448448 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 1298560 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1281000 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8477568 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 174256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 561876 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 361024 # Number of bytes read from this memory
27,31c26,30
< system.physmem.bytes_read::total 12533612 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1298880 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 183536 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1482416 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8896000 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12157612 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1298560 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 174256 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1472816 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8578432 # Number of bytes written to this memory
34,44c33,42
< system.physmem.bytes_written::total 8913564 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 22542 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 21360 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 134435 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 2936 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 10356 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 7007 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8595996 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 22537 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 20536 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 132462 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 2791 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8800 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 5641 # Number of read requests responded to by this memory
46,47c44,45
< system.physmem.num_reads::total 198694 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 139000 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 192819 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 134038 # Number of write requests responded to by this memory
50,60c48,57
< system.physmem.num_writes::total 143391 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 724 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 459372 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 471699 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 3042898 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 64911 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 233937 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 158601 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 138429 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 459265 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 453054 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2998282 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 61630 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 198720 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 127684 # Total read bandwidth from this memory (bytes/s)
62,66c59,63
< system.physmem.bw_read::total 4432731 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 459372 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 64911 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 524282 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3146226 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4299812 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 459265 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 61630 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 520894 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3033954 # Write bandwidth from this memory (bytes/s)
69,80c66,76
< system.physmem.bw_write::total 3152437 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3146226 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 724 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 459372 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 477897 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 3042898 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 64911 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 233951 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 158601 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3040166 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3033954 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 459265 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 459252 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2998282 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 61630 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 198734 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 127684 # Total bandwidth to/from this memory (bytes/s)
82,92c78,88
< system.physmem.bw_total::total 7585168 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 198695 # Number of read requests accepted
< system.physmem.writeReqs 143391 # Number of write requests accepted
< system.physmem.readBursts 198695 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 143391 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12706944 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8926464 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12533676 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8913564 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 7339978 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 192820 # Number of read requests accepted
> system.physmem.writeReqs 138429 # Number of write requests accepted
> system.physmem.readBursts 192820 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 138429 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12329536 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8609152 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12157676 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8595996 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue
94,126c90,122
< system.physmem.neitherReadNorWriteReqs 66310 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12511 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12409 # Per bank write bursts
< system.physmem.perBankRdBursts::2 13005 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12914 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14688 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12279 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12659 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12545 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12216 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11968 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11724 # Per bank write bursts
< system.physmem.perBankRdBursts::11 10899 # Per bank write bursts
< system.physmem.perBankRdBursts::12 12000 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12901 # Per bank write bursts
< system.physmem.perBankRdBursts::14 12154 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11674 # Per bank write bursts
< system.physmem.perBankWrBursts::0 9120 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9128 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9608 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9301 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8579 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8797 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8898 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8634 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8555 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8430 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8386 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7930 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8700 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8975 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8498 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7937 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 11576 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11126 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12008 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12324 # Per bank write bursts
> system.physmem.perBankRdBursts::4 14472 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12248 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12234 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12314 # Per bank write bursts
> system.physmem.perBankRdBursts::8 11863 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12111 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11927 # Per bank write bursts
> system.physmem.perBankRdBursts::11 10878 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11632 # Per bank write bursts
> system.physmem.perBankRdBursts::13 12420 # Per bank write bursts
> system.physmem.perBankRdBursts::14 12142 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11374 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8212 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8081 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8787 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8816 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8301 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8710 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8720 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8560 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8226 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8556 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8511 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8034 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8394 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8529 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8449 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7632 # Per bank write bursts
128,129c124,125
< system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
< system.physmem.totGap 2827514698000 # Total gap between requests
---
> system.physmem.numWrRetry 14 # Number of times write queue was full causing retry
> system.physmem.totGap 2827475264500 # Total gap between requests
136c132
< system.physmem.readPktSize::6 195029 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 189154 # Read request sizes (log2)
143,156c139,152
< system.physmem.writePktSize::6 139000 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 63536 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 75209 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 13408 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 10355 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8590 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7482 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 6561 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 5366 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 4742 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1364 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 854 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 595 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 246 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 134038 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 61526 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 73950 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 12963 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 10011 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 8224 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7155 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 6169 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 5077 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 4439 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1284 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 803 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 555 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 257 # What read queue length does an incoming req see
158,159c154,155
< system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
191,234c187,230
< system.physmem.wrQLenPdf::15 2872 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3412 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4292 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4676 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6270 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7487 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7498 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8782 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9419 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 11226 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9482 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9504 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 10926 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 9080 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8303 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7724 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 722 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 447 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 143 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 107 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 60 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 56 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 29 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2604 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3606 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4862 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4513 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5668 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5623 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6871 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7749 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8539 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8810 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9497 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 11730 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 9218 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 8443 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7994 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1311 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 337 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 271 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 214 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 100 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 75 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see
236,305c232,301
< system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 91952 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 235.267792 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 133.235046 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 298.839280 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 50134 54.52% 54.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17916 19.48% 74.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5936 6.46% 80.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3412 3.71% 84.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2785 3.03% 87.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1606 1.75% 88.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 997 1.08% 90.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 910 0.99% 91.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8256 8.98% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 91952 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6854 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.967610 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 561.585770 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6852 99.97% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6854 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6854 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.349577 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.863128 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.733584 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5532 80.71% 80.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 528 7.70% 88.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 124 1.81% 90.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 151 2.20% 92.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 37 0.54% 92.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 137 2.00% 94.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 51 0.74% 95.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 13 0.19% 95.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 30 0.44% 96.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 17 0.25% 96.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 5 0.07% 96.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 10 0.15% 96.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 152 2.22% 99.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 5 0.07% 99.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 2 0.03% 99.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 27 0.39% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 1 0.01% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 3 0.04% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.01% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.01% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.01% 99.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 13 0.19% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6854 # Writes before turning the bus around for reads
< system.physmem.totQLat 6593126991 # Total ticks spent queuing
< system.physmem.totMemAccLat 10315864491 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 992730000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 33207.05 # Average queueing delay per DRAM burst
< system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
< system.physmem.avgMemAccLat 51957.05 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s
---
> system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 86851 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 241.087472 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 135.747966 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 303.663203 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 46826 53.92% 53.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16666 19.19% 73.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5740 6.61% 79.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3326 3.83% 83.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2736 3.15% 86.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1522 1.75% 88.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 967 1.11% 89.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 891 1.03% 90.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8177 9.41% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 86851 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6471 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 29.771133 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 578.111149 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6469 99.97% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6471 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6471 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.787823 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.938766 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 13.675923 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5299 81.89% 81.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 491 7.59% 89.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 106 1.64% 91.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 48 0.74% 91.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 55 0.85% 92.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 30 0.46% 93.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 47 0.73% 93.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 20 0.31% 94.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 127 1.96% 96.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 8 0.12% 96.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 7 0.11% 96.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 12 0.19% 96.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 76 1.17% 97.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 3 0.05% 97.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.06% 97.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 25 0.39% 98.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 78 1.21% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.02% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 4 0.06% 99.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.02% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.02% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 8 0.12% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6471 # Writes before turning the bus around for reads
> system.physmem.totQLat 6248738813 # Total ticks spent queuing
> system.physmem.totMemAccLat 9860907563 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 963245000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 32435.71 # Average queueing delay per DRAM burst
> system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 51185.61 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.36 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.04 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
308c304
< system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
---
> system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
311,328c307,324
< system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing
< system.physmem.readRowHits 165438 # Number of row buffer hits during reads
< system.physmem.writeRowHits 80631 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 57.80 # Row buffer hit rate for writes
< system.physmem.avgGap 8265508.38 # Average gap between requests
< system.physmem.pageHitRate 72.79 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 362418840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 197748375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 803470200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 466981200 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 80961093990 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1625490282750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1892961490875 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.478934 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2704041495487 # Time in different power states
< system.physmem_0.memoryStateTime::REF 94416920000 # Time in different power states
---
> system.physmem.avgWrQLen 25.73 # Average write queue length when enqueuing
> system.physmem.readRowHits 160837 # Number of row buffer hits during reads
> system.physmem.writeRowHits 79479 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes
> system.physmem.avgGap 8535800.15 # Average gap between requests
> system.physmem.pageHitRate 73.45 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 333433800 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 181933125 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 766755600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 441851760 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 184676952720 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 80138844765 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1626188195250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1892727967020 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.405562 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2705208494482 # Time in different power states
> system.physmem_0.memoryStateTime::REF 94415360000 # Time in different power states
330c326
< system.physmem_0.memoryStateTime::ACT 29056546513 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 27851611768 # Time in different power states
332,342c328,338
< system.physmem_1.actEnergy 332738280 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 181553625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 745180800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 436823280 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 80279403345 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1626088257000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1892743451850 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.401821 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2705042490853 # Time in different power states
< system.physmem_1.memoryStateTime::REF 94416920000 # Time in different power states
---
> system.physmem_1.actEnergy 323159760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 176327250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 735906600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 429824880 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 184676952720 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 80034809220 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1626279454500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1892656434930 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.380263 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2705361200169 # Time in different power states
> system.physmem_1.memoryStateTime::REF 94415360000 # Time in different power states
344c340
< system.physmem_1.memoryStateTime::ACT 28055246647 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 27698906081 # Time in different power states
370,374c366,370
< system.cpu0.branchPred.lookups 53824650 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 24914718 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 1030270 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 32581460 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 24224214 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 53905391 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 24966840 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 1032917 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 32635895 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 24264793 # Number of BTB hits
376,378c372,374
< system.cpu0.branchPred.BTBHitPct 74.349688 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 15556762 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 33886 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 74.350016 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 15570273 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 33772 # Number of incorrect RAS predictions.
409,423c405,419
< system.cpu0.dtb.walker.walks 72482 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 72482 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26840 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21370 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 24272 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 48210 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 483.737814 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 3068.363590 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-8191 46935 97.36% 97.36% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::8192-16383 960 1.99% 99.35% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::16384-24575 127 0.26% 99.61% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::24576-32767 144 0.30% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.02% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::40960-49151 24 0.05% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
---
> system.cpu0.dtb.walker.walks 72512 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 72512 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26965 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21131 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 24416 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 48096 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 467.596058 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 2968.857131 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-8191 46825 97.36% 97.36% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::8192-16383 988 2.05% 99.41% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::16384-24575 122 0.25% 99.67% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::24576-32767 128 0.27% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
430,450c426,447
< system.cpu0.dtb.walker.walkWaitTime::total 48210 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 19223 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 10866.878219 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 9427.660612 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 7974.318697 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-32767 19122 99.47% 99.47% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-65535 77 0.40% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 19223 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 87324939152 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.584645 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.504578 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 87261759152 99.93% 99.93% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 45052000 0.05% 99.98% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 7883000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 5458000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 1586500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 936000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 1172500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 1091000 0.00% 100.00% # Table walker pending requests distribution
---
> system.cpu0.dtb.walker.walkWaitTime::total 48096 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 18855 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 10765.367277 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 9357.714559 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 7448.182030 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-32767 18771 99.55% 99.55% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-65535 62 0.33% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.11% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 18855 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 82990542356 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.627007 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.496515 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 82928307856 99.93% 99.93% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 44597000 0.05% 99.98% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 7454000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 4958000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 1796000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 1081000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 1137000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 1210500 0.00% 100.00% # Table walker pending requests distribution
452,456c449,453
< system.cpu0.dtb.walker.walksPending::total 87324939152 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 5998 77.94% 77.94% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1698 22.06% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 7696 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72482 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walksPending::total 82990542356 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 5809 78.88% 78.88% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1555 21.12% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 7364 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72512 # Table walker requests started/completed, data/inst
458,459c455,456
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72482 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7696 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72512 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7364 # Table walker requests started/completed, data/inst
461,462c458,459
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7696 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 80178 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7364 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 79876 # Table walker requests started/completed, data/inst
465,468c462,465
< system.cpu0.dtb.read_hits 24348850 # DTB read hits
< system.cpu0.dtb.read_misses 61646 # DTB read misses
< system.cpu0.dtb.write_hits 18136813 # DTB write hits
< system.cpu0.dtb.write_misses 10836 # DTB write misses
---
> system.cpu0.dtb.read_hits 24390364 # DTB read hits
> system.cpu0.dtb.read_misses 61238 # DTB read misses
> system.cpu0.dtb.write_hits 18168033 # DTB write hits
> system.cpu0.dtb.write_misses 11274 # DTB write misses
473,475c470,472
< system.cpu0.dtb.flush_entries 3858 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 293 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 2461 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3796 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 307 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 2501 # Number of TLB faults due to prefetch
477,479c474,476
< system.cpu0.dtb.perms_faults 958 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 24410496 # DTB read accesses
< system.cpu0.dtb.write_accesses 18147649 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 1008 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 24451602 # DTB read accesses
> system.cpu0.dtb.write_accesses 18179307 # DTB write accesses
481,483c478,480
< system.cpu0.dtb.hits 42485663 # DTB hits
< system.cpu0.dtb.misses 72482 # DTB misses
< system.cpu0.dtb.accesses 42558145 # DTB accesses
---
> system.cpu0.dtb.hits 42558397 # DTB hits
> system.cpu0.dtb.misses 72512 # DTB misses
> system.cpu0.dtb.accesses 42630909 # DTB accesses
513,540c510,537
< system.cpu0.itb.walker.walks 11063 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 11063 # Table walker walks initiated with short descriptors
< system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4358 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6586 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 119 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 10944 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 511.878655 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 2393.914880 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-4095 10440 95.39% 95.39% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::4096-8191 166 1.52% 96.91% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::8192-12287 245 2.24% 99.15% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::12288-16383 55 0.50% 99.65% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::16384-20479 14 0.13% 99.78% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::20480-24575 14 0.13% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 10944 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 3006 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 12466.400532 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 11507.410615 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 5482.679017 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-16383 2781 92.51% 92.51% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-32767 206 6.85% 99.37% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.57% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walks 10837 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 10837 # Table walker walks initiated with short descriptors
> system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4138 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6571 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 128 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 10709 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 537.118312 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 2502.473477 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-4095 10215 95.39% 95.39% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::4096-8191 152 1.42% 96.81% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::8192-12287 230 2.15% 98.95% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::12288-16383 65 0.61% 99.56% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.12% 99.68% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::20480-24575 22 0.21% 99.89% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 10709 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 3004 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 12684.087883 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 11728.240532 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 5609.984659 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-16383 2772 92.28% 92.28% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-32767 204 6.79% 99.07% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-49151 24 0.80% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.10% 99.97% # Table walker service (enqueue to completion) latency
542,553c539,550
< system.cpu0.itb.walker.walkCompletionTime::total 3006 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 18373803416 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.969102 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.173359 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 568612000 3.09% 3.09% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 17804392916 96.90% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 690500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 108000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 18373803416 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 2539 87.95% 87.95% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::1M 348 12.05% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 2887 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkCompletionTime::total 3004 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 18565989416 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.960744 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.194475 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 729735500 3.93% 3.93% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 17835412416 96.06% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 771500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 18565989416 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 2530 87.97% 87.97% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::1M 346 12.03% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 2876 # Table walker page sizes translated
555,556c552,553
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11063 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11063 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10837 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10837 # Table walker requests started/completed, data/inst
558,562c555,559
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2887 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2887 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 13950 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 74042794 # ITB inst hits
< system.cpu0.itb.inst_misses 11063 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2876 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2876 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 13713 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 74149475 # ITB inst hits
> system.cpu0.itb.inst_misses 10837 # ITB inst misses
571c568
< system.cpu0.itb.flush_entries 2625 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2616 # Number of entries that have been flushed from TLB
575c572
< system.cpu0.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions
578,582c575,579
< system.cpu0.itb.inst_accesses 74053857 # ITB inst accesses
< system.cpu0.itb.hits 74042794 # DTB hits
< system.cpu0.itb.misses 11063 # DTB misses
< system.cpu0.itb.accesses 74053857 # DTB accesses
< system.cpu0.numCycles 211047403 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 74160312 # ITB inst accesses
> system.cpu0.itb.hits 74149475 # DTB hits
> system.cpu0.itb.misses 10837 # DTB misses
> system.cpu0.itb.accesses 74160312 # DTB accesses
> system.cpu0.numCycles 211083313 # number of cpu cycles simulated
585,601c582,598
< system.cpu0.fetch.icacheStallCycles 21173136 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 200001666 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 53824650 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 39780976 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 180559136 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 5880452 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 163694 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 71518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 416219 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 467581 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 105314 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 74043107 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 284080 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 205896824 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 1.187509 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.306152 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 21223431 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 200300307 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 53905391 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 39835066 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 180535577 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 5889142 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 161904 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 68557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 388699 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 473615 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 104901 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 74149781 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 285289 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 4990 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 205901255 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 1.189189 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.306256 # Number of instructions fetched each cycle (Total)
603,606c600,603
< system.cpu0.fetch.rateDist::0 98736671 47.95% 47.95% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 31028549 15.07% 63.02% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 14918972 7.25% 70.27% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 61212632 29.73% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 98579580 47.88% 47.88% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 31081229 15.10% 62.97% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 14947160 7.26% 70.23% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 61293286 29.77% 100.00% # Number of instructions fetched each cycle (Total)
610,656c607,653
< system.cpu0.fetch.rateDist::total 205896824 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.255036 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.947662 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 26444854 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 111284081 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 60438396 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 5147375 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 2582118 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 3181251 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 362597 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 158450982 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 4186687 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 2582118 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 35356822 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 13355442 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 85192856 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 56532551 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 12877035 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 141523079 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 1131567 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 1510730 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 170563 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 62525 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 8538727 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 145648252 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 652695637 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 157341344 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 11002 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 133402169 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 12246080 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 2729481 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 2582524 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 22941481 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 25362929 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 19747073 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1756360 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 2710793 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 138386443 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1765013 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 136262498 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 514521 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 11554986 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 23816746 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 127231 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 205896824 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.661800 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 0.962021 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 205901255 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.255375 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.948916 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 26485725 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 111121300 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 60553458 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 5155672 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 2585100 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 3186918 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 364053 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 158727281 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 4198172 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 2585100 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 35410452 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 13324080 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 85173312 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 56642777 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 12765534 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 141784227 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 1134861 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 1512506 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 171242 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 63990 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 8419059 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 145923157 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 653859214 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 157615965 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 11018 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 133662052 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 12261102 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 2732054 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 2584956 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 22955704 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 25402528 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 19781437 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1763657 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 2641114 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 138643116 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1767872 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 136516412 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 515589 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 11570507 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 23858027 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 127265 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 205901255 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.663019 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 0.962571 # Number of insts issued each cycle
658,663c655,660
< system.cpu0.iq.issued_per_cycle::0 127277158 61.82% 61.82% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 34398562 16.71% 78.52% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 31970025 15.53% 94.05% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 11080468 5.38% 99.43% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1170573 0.57% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 38 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 127147396 61.75% 61.75% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 34442708 16.73% 78.48% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 32032196 15.56% 94.04% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 11106549 5.39% 99.43% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1172365 0.57% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 41 0.00% 100.00% # Number of insts issued each cycle
670c667
< system.cpu0.iq.issued_per_cycle::total 205896824 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 205901255 # Number of insts issued each cycle
672,702c669,699
< system.cpu0.iq.fu_full::IntAlu 11103787 43.69% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 71 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 5926512 23.32% 67.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 8382229 32.98% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 11130379 43.68% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 74 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.68% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 5931854 23.28% 66.95% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 8421894 33.05% 100.00% # attempts to use FU when none available
706,707c703,704
< system.cpu0.iq.FU_type_0::IntAlu 91815128 67.38% 67.38% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 112435 0.08% 67.47% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 91995657 67.39% 67.39% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 112676 0.08% 67.47% # Type of FU issued
709c706
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.47% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 67.47% # Type of FU issued
731,736c728,733
< system.cpu0.iq.FU_type_0::SimdFloatMisc 8235 0.01% 67.47% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 25085333 18.41% 85.88% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 19239052 14.12% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::SimdFloatMisc 8005 0.01% 67.48% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.48% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.48% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.48% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 25126496 18.41% 85.88% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 19271262 14.12% 100.00% # Type of FU issued
739,751c736,748
< system.cpu0.iq.FU_type_0::total 136262498 # Type of FU issued
< system.cpu0.iq.rate 0.645649 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 25412599 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.186497 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 504310819 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 151713950 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 132552939 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 38121 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 13270 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 11439 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 161648054 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 24728 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 380758 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 136516412 # Type of FU issued
> system.cpu0.iq.rate 0.646742 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 25484201 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.186675 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 504896258 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 151989102 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 132800903 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 37611 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 13286 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 11444 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 161974001 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 24297 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 381848 # Number of loads that had data forwarded from stores
753,756c750,753
< system.cpu0.iew.lsq.thread0.squashedLoads 2120893 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2730 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 20852 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 1081680 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 2124335 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2693 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 20966 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 1085688 # Number of stores squashed
759,760c756,757
< system.cpu0.iew.lsq.thread0.rescheduledLoads 121274 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 393141 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 122039 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 394742 # Number of times an access to memory failed due to the cache being blocked
762,765c759,762
< system.cpu0.iew.iewSquashCycles 2582118 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 1967503 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 225282 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 140361265 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 2585100 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 1946406 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 232120 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 140620014 # Number of instructions dispatched to IQ
767,778c764,775
< system.cpu0.iew.iewDispLoadInsts 25362929 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 19747073 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 903285 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 28583 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 172530 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 20852 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 314241 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 420118 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 734359 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 135106830 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 24606381 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 1083325 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 25402528 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 19781437 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 904543 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 28856 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 178897 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 20966 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 314635 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 420768 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 735403 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 135358106 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 24646455 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 1085945 # Number of squashed instructions skipped in execute
780,796c777,793
< system.cpu0.iew.exec_nop 209809 # number of nop insts executed
< system.cpu0.iew.exec_refs 43646202 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 26044471 # Number of branches executed
< system.cpu0.iew.exec_stores 19039821 # Number of stores executed
< system.cpu0.iew.exec_rate 0.640173 # Inst execution rate
< system.cpu0.iew.wb_sent 134503420 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 132564378 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 67577240 # num instructions producing a value
< system.cpu0.iew.wb_consumers 109379746 # num instructions consuming a value
< system.cpu0.iew.wb_rate 0.628126 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.617822 # average fanout of values written-back
< system.cpu0.commit.commitSquashedInsts 10448394 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 1637782 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 672162 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 202592939 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.635502 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.338703 # Number of insts commited each cycle
---
> system.cpu0.iew.exec_nop 209026 # number of nop insts executed
> system.cpu0.iew.exec_refs 43717751 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 26098625 # Number of branches executed
> system.cpu0.iew.exec_stores 19071296 # Number of stores executed
> system.cpu0.iew.exec_rate 0.641254 # Inst execution rate
> system.cpu0.iew.wb_sent 134752568 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 132812347 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 67711784 # num instructions producing a value
> system.cpu0.iew.wb_consumers 109592899 # num instructions consuming a value
> system.cpu0.iew.wb_rate 0.629194 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.617848 # average fanout of values written-back
> system.cpu0.commit.commitSquashedInsts 10460496 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 1640607 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 673446 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 202593421 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.636705 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.338464 # Number of insts commited each cycle
798,806c795,803
< system.cpu0.commit.committed_per_cycle::0 141057849 69.63% 69.63% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 33954375 16.76% 86.39% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 12905235 6.37% 92.76% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 3389250 1.67% 94.43% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 4963565 2.45% 96.88% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 2666475 1.32% 98.20% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 1522321 0.75% 98.95% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 575799 0.28% 99.23% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1558070 0.77% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 140886474 69.54% 69.54% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 34073921 16.82% 86.36% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 12920125 6.38% 92.74% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 3397713 1.68% 94.41% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 4982698 2.46% 96.87% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 2731294 1.35% 98.22% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 1467251 0.72% 98.95% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 577318 0.28% 99.23% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1556627 0.77% 100.00% # Number of insts commited each cycle
810,812c807,809
< system.cpu0.commit.committed_per_cycle::total 202592939 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 106280740 # Number of instructions committed
< system.cpu0.commit.committedOps 128748309 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 202593421 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 106498180 # Number of instructions committed
> system.cpu0.commit.committedOps 128992320 # Number of ops (including micro ops) committed
814,817c811,814
< system.cpu0.commit.refs 41907429 # Number of memory references committed
< system.cpu0.commit.loads 23242036 # Number of loads committed
< system.cpu0.commit.membars 664627 # Number of memory barriers committed
< system.cpu0.commit.branches 25370057 # Number of branches committed
---
> system.cpu0.commit.refs 41973942 # Number of memory references committed
> system.cpu0.commit.loads 23278193 # Number of loads committed
> system.cpu0.commit.membars 666414 # Number of memory barriers committed
> system.cpu0.commit.branches 25425121 # Number of branches committed
819,820c816,817
< system.cpu0.commit.int_insts 112383608 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 4877012 # Number of function calls committed.
---
> system.cpu0.commit.int_insts 112579800 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 4882067 # Number of function calls committed.
822,852c819,849
< system.cpu0.commit.op_class_0::IntAlu 86722676 67.36% 67.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 109969 0.09% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 8235 0.01% 67.45% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 23242036 18.05% 85.50% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 18665393 14.50% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 86900184 67.37% 67.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 110189 0.09% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.45% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 8005 0.01% 67.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 23278193 18.05% 85.51% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 18695749 14.49% 100.00% # Class of committed instruction
855,880c852,877
< system.cpu0.commit.op_class_0::total 128748309 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1558070 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 316922543 # The number of ROB reads
< system.cpu0.rob.rob_writes 281696540 # The number of ROB writes
< system.cpu0.timesIdled 138499 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 5150579 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 5443982755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 106128897 # Number of Instructions Simulated
< system.cpu0.committedOps 128596466 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.988595 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.988595 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.502868 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.502868 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 146588252 # number of integer regfile reads
< system.cpu0.int_regfile_writes 83723999 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 9570 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes
< system.cpu0.cc_regfile_reads 476941595 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 51071402 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 282603834 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 1261450 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 749987 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 496.992457 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 38690178 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 750499 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 51.552604 # Average number of references to valid blocks.
---
> system.cpu0.commit.op_class_0::total 128992320 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1556627 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 317161742 # The number of ROB reads
> system.cpu0.rob.rob_writes 282212626 # The number of ROB writes
> system.cpu0.timesIdled 140171 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 5182058 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 5443868094 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 106346337 # Number of Instructions Simulated
> system.cpu0.committedOps 128840477 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.984867 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.984867 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.503812 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.503812 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 146850094 # number of integer regfile reads
> system.cpu0.int_regfile_writes 83860337 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 9519 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 2721 # number of floating regfile writes
> system.cpu0.cc_regfile_reads 477816426 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 51195786 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 282652550 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 1263043 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 752117 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 499.742963 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 38755611 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 752629 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 51.493646 # Average number of references to valid blocks.
882,884c879,881
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.992457 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970688 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.970688 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.742963 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.976060 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.976060 # Average percentage of cache occupancy
886,888c883,885
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
890,969c887,966
< system.cpu0.dcache.tags.tag_accesses 83515372 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 83515372 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 22054482 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 22054482 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 15385393 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 15385393 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316703 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 316703 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371938 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 371938 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370232 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 370232 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 37439875 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 37439875 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 37756578 # number of overall hits
< system.cpu0.dcache.overall_hits::total 37756578 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 687176 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 687176 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1969830 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1969830 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153892 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 153892 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25692 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 25692 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20263 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 20263 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2657006 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2657006 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2810898 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2810898 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 10005125000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 10005125000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36953361360 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 36953361360 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 414445500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 414445500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 533612500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 533612500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 572000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 572000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 46958486360 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 46958486360 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 46958486360 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 46958486360 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 22741658 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 22741658 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 17355223 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 17355223 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470595 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 470595 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397630 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 397630 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390495 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 390495 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 40096881 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 40096881 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 40567476 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 40567476 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030217 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.030217 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113501 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.113501 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327016 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327016 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064613 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064613 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051891 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051891 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066265 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.066265 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069289 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.069289 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14559.770714 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 14559.770714 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18759.670307 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 18759.670307 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16131.305465 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16131.305465 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26334.328579 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26334.328579 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 83654415 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 83654415 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 22092656 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 22092656 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 15410060 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 15410060 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316535 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 316535 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 372009 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 372009 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370743 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 370743 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 37502716 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 37502716 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 37819251 # number of overall hits
> system.cpu0.dcache.overall_hits::total 37819251 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 687238 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 687238 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1974372 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1974372 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 154018 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 154018 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26141 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 26141 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20265 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 20265 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 2661610 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 2661610 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 2815628 # number of overall misses
> system.cpu0.dcache.overall_misses::total 2815628 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9986915000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 9986915000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36507657372 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 36507657372 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 419065500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 419065500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 536371000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 536371000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 741000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 741000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 46494572372 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 46494572372 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 46494572372 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 46494572372 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 22779894 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 22779894 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 17384432 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 17384432 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470553 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 470553 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 398150 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 398150 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391008 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 391008 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 40164326 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 40164326 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 40634879 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 40634879 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030169 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.030169 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113571 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.113571 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327313 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327313 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065656 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065656 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051828 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051828 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066268 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.066268 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069291 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.069291 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14531.959816 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 14531.959816 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18490.769405 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 18490.769405 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16030.966681 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16030.966681 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26467.850975 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26467.850975 # average StoreCondReq miss latency
972,981c969,978
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17673.458908 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 17673.458908 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16705.866367 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 16705.866367 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 5691402 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 46 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 211704 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.891304 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 26.883772 # average number of cycles each access was blocked
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17468.589452 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 17468.589452 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16513.038076 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 16513.038076 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 1294 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 5611564 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 45 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 212264 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.755556 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 26.436720 # average number of cycles each access was blocked
984,1061c981,1058
< system.cpu0.dcache.writebacks::writebacks 749987 # number of writebacks
< system.cpu0.dcache.writebacks::total 749987 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277260 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 277260 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634141 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1634141 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19045 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19045 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1911401 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1911401 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1911401 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1911401 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 409916 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 409916 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335689 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 335689 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107270 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 107270 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6647 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6647 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20263 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 20263 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 745605 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 745605 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 852875 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 852875 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31809 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31809 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60302 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60302 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149096500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149096500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7778892390 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7778892390 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1793614000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1793614000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108165500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108165500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513361500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513361500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 560000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 560000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12927988890 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 12927988890 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14721602890 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 14721602890 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6623643500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6623643500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395209000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395209000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12018852500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12018852500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018025 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018025 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019342 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019342 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227945 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227945 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016717 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051891 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051891 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018595 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.018595 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021024 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.021024 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.345495 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.345495 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23172.914185 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23172.914185 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16720.555607 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16720.555607 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16272.829848 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16272.829848 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25334.920792 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25334.920792 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 752119 # number of writebacks
> system.cpu0.dcache.writebacks::total 752119 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276058 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 276058 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1637615 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1637615 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19358 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19358 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1913673 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1913673 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1913673 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1913673 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 411180 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 411180 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336757 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 336757 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107638 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 107638 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6783 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6783 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20265 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 20265 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 747937 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 747937 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 855575 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 855575 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31813 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31813 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28497 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28497 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60310 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60310 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5148866500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5148866500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7661006402 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7661006402 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1794118000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1794118000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 109526500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109526500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 516121000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 516121000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 726000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 726000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12809872902 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 12809872902 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14603990902 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 14603990902 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6624175500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6624175500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395535000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395535000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12019710500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12019710500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018050 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018050 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019371 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019371 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228748 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228748 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017036 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017036 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051828 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051828 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018622 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.018622 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021055 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.021055 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.171555 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.171555 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22749.360524 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22749.360524 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16668.072614 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16668.072614 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16147.206251 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.206251 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25468.591167 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25468.591167 # average StoreCondReq mshr miss latency
1064,1073c1061,1070
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17338.924618 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17338.924618 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17261.149512 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17261.149512 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208231.742589 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208231.742589 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189352.086477 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189352.086477 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199311.009585 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199311.009585 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17126.941042 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17126.941042 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17069.211819 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17069.211819 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208222.283343 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208222.283343 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189336.947749 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189336.947749 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199298.797878 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199298.797878 # average overall mshr uncacheable latency
1075,1081c1072,1078
< system.cpu0.icache.tags.replacements 1312325 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.728748 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 72670068 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1312837 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 55.353458 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 8207375500 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728748 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.replacements 1314552 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.728712 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 72774275 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1315064 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 55.338961 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 8206989500 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728712 # Average occupied blocks per requestor
1086,1087c1083,1084
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 135 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id
1089,1132c1086,1129
< system.cpu0.icache.tags.tag_accesses 149391678 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 149391678 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 72670068 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 72670068 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 72670068 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 72670068 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 72670068 # number of overall hits
< system.cpu0.icache.overall_hits::total 72670068 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1369337 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1369337 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1369337 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1369337 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1369337 # number of overall misses
< system.cpu0.icache.overall_misses::total 1369337 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14942606327 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 14942606327 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 14942606327 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 14942606327 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 14942606327 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 14942606327 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 74039405 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 74039405 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 74039405 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 74039405 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 74039405 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 74039405 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018495 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.018495 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018495 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.018495 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018495 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.018495 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10912.292830 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10912.292830 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10912.292830 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10912.292830 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10912.292830 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10912.292830 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 2029991 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 126413 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.058404 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked
---
> system.cpu0.icache.tags.tag_accesses 149607293 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 149607293 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 72774275 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 72774275 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 72774275 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 72774275 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 72774275 # number of overall hits
> system.cpu0.icache.overall_hits::total 72774275 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1371825 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1371825 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1371825 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1371825 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1371825 # number of overall misses
> system.cpu0.icache.overall_misses::total 1371825 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14990660882 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 14990660882 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 14990660882 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 14990660882 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 14990660882 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 14990660882 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 74146100 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 74146100 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 74146100 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 74146100 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 74146100 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 74146100 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018502 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.018502 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018502 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.018502 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018502 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.018502 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10927.531487 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10927.531487 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10927.531487 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10927.531487 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10927.531487 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10927.531487 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 2029638 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 1805 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 126916 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.991979 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 112.812500 # average number of cycles each access was blocked
1135,1148c1132,1145
< system.cpu0.icache.writebacks::writebacks 1312325 # number of writebacks
< system.cpu0.icache.writebacks::total 1312325 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56467 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 56467 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 56467 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 56467 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 56467 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 56467 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1312870 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1312870 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1312870 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1312870 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1312870 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1312870 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 1314552 # number of writebacks
> system.cpu0.icache.writebacks::total 1314552 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56730 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 56730 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 56730 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 56730 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 56730 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 56730 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1315095 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1315095 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1315095 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1315095 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1315095 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1315095 # number of overall MSHR misses
1153,1158c1150,1155
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13422835685 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 13422835685 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13422835685 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 13422835685 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13422835685 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 13422835685 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13463982231 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 13463982231 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13463982231 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 13463982231 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13463982231 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 13463982231 # number of overall MSHR miss cycles
1163,1174c1160,1171
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017732 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.017732 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.017732 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10224.040221 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017737 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017737 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017737 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.017737 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017737 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.017737 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10238.030128 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10238.030128 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10238.030128 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10238.030128 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10238.030128 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10238.030128 # average overall mshr miss latency
1180,1182c1177,1179
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1922264 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1925121 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 2600 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1929258 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1932095 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 2584 # number of redundant prefetches already in prefetch queue
1185,1190c1182,1187
< system.cpu0.l2cache.prefetcher.pfSpanPage 245295 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 283525 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16106.133558 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 3424599 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 299662 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 11.428206 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 247841 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 284507 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16086.849244 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 3431968 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 300678 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 11.414097 # Average number of references to valid blocks.
1192,1304c1189,1301
< system.cpu0.l2cache.tags.occ_blocks::writebacks 14666.612197 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.987362 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.024801 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1424.509198 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.895179 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000854 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086945 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.983040 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 969 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15162 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 307 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 430 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 205 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 496 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4568 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7930 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2049 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059143 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925415 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 69529329 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 69529329 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 59791 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14320 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 74111 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 505100 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 505100 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 1523954 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 1523954 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205881 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 205881 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1258248 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1258248 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 426377 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 426377 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 59791 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14320 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1258248 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 632258 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1964617 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 59791 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14320 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1258248 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 632258 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1964617 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 340 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 103 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 443 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55446 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 55446 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20261 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 20261 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 74580 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 74580 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 54597 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 54597 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97319 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 97319 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 340 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 103 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 54597 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 171899 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 226939 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 340 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 103 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 54597 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 171899 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 226939 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 12449000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2707500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 15156500 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 180664000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 180664000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 42645500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 42645500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 540498 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 540498 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 4119133500 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 4119133500 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3780116498 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3780116498 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3430160498 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3430160498 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 12449000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2707500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3780116498 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 7549293998 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 11344566996 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 12449000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2707500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3780116498 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 7549293998 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 11344566996 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60131 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14423 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 74554 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 505100 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 505100 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 1523954 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 1523954 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55447 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 55447 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 14687.998077 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 10.848877 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.803869 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1387.198421 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.896484 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000662 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000049 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.084668 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.981863 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 953 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15209 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 34 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 301 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 417 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 201 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 502 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4642 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7971 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1960 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058167 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928284 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 69690071 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 69690071 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60554 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14268 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 74822 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 506171 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 506171 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 1527085 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 1527085 # number of WritebackClean hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205394 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 205394 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1259556 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1259556 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 427820 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 427820 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60554 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14268 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1259556 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 633214 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1967592 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60554 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14268 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1259556 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 633214 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1967592 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 344 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 106 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 450 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56106 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 56106 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20260 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 20260 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 75462 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 75462 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55517 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 55517 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97649 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 97649 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 344 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 106 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 55517 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 173111 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 229078 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 344 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 106 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 55517 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 173111 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 229078 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11458500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2915500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 14374000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 181260500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 181260500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 44478000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 44478000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 700997 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 700997 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3994943500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 3994943500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3810249498 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3810249498 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3419507493 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3419507493 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11458500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2915500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3810249498 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 7414450993 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 11239074491 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11458500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2915500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3810249498 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 7414450993 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 11239074491 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60898 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14374 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 75272 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506171 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 506171 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 1527085 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 1527085 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56106 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 56106 # number of UpgradeReq accesses(hits+misses)
1307,1331c1304,1328
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280461 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 280461 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1312845 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1312845 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 523696 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 523696 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60131 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14423 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1312845 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 804157 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 2191556 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60131 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14423 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1312845 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 804157 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 2191556 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005654 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.007141 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.005942 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280856 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 280856 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1315073 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1315073 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 525469 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 525469 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60898 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14374 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1315073 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 806325 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 2196670 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60898 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14374 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1315073 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 806325 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 2196670 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005649 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.007374 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.005978 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999951 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999951 # miss rate for SCUpgradeReq accesses
1334,1374c1331,1371
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.265919 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.265919 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041587 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041587 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.185831 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.185831 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005654 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.007141 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041587 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.213763 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.103552 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005654 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.007141 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041587 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.213763 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.103552 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36614.705882 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26286.407767 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34213.318284 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3258.377520 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3258.377520 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2104.807265 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2104.807265 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 270249 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 270249 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55231.074014 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55231.074014 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69236.707108 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69236.707108 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35246.565398 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35246.565398 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36614.705882 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26286.407767 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69236.707108 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43917.032665 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 49989.499363 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36614.705882 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26286.407767 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69236.707108 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43917.032665 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 49989.499363 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.268686 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.268686 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042216 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042216 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.185832 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.185832 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005649 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.007374 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042216 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.214691 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.104284 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005649 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.007374 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042216 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.214691 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.104284 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33309.593023 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27504.716981 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31942.222222 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3230.679428 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3230.679428 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2195.360316 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2195.360316 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 175249.250000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 175249.250000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52939.804140 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52939.804140 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68632.121656 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68632.121656 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35018.356491 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35018.356491 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33309.593023 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27504.716981 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68632.121656 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42830.617309 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 49062.216760 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33309.593023 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27504.716981 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68632.121656 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42830.617309 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 49062.216760 # average overall miss latency
1383,1385c1380,1382
< system.cpu0.l2cache.writebacks::writebacks 233393 # number of writebacks
< system.cpu0.l2cache.writebacks::total 233393 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
---
> system.cpu0.l2cache.writebacks::writebacks 234505 # number of writebacks
> system.cpu0.l2cache.writebacks::total 234505 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
1387,1428c1384,1425
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 33060 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 33060 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 43 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 43 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 786 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 786 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 43 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33846 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 33890 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 43 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33846 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 33890 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 339 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 103 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 260432 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 260432 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55446 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55446 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20261 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20261 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41520 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 41520 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 54554 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 54554 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96533 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96533 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 339 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 103 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 54554 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138053 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 193049 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 339 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 103 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 54554 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138053 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 260432 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 453481 # number of overall MSHR misses
---
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 33047 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 33047 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 39 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 39 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 815 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 815 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 39 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33862 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 33902 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 39 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33862 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 33902 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 105 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 449 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 263045 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 263045 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56106 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56106 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20260 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20260 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42415 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 42415 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55478 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55478 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96834 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96834 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 344 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 105 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55478 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139249 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 195176 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 344 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 105 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55478 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139249 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 263045 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 458221 # number of overall MSHR misses
1430,1433c1427,1430
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31809 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34813 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31813 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34817 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28497 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28497 # number of WriteReq MSHR uncacheable
1435,1464c1432,1461
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60302 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63306 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10399500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2089500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12489000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 22074812822 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 22074812822 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1462138500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1462138500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 360190499 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 360190499 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 468498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 468498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2502746000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2502746000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3450718498 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3450718498 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2793545998 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2793545998 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10399500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2089500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3450718498 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5296291998 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 8759499496 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10399500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2089500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3450718498 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5296291998 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 22074812822 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 30834312318 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60310 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63314 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9394500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2264500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11659000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21677740222 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21677740222 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1466066000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1466066000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 362872998 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 362872998 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 610997 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 610997 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2406611500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2406611500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3475237498 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3475237498 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2779907993 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2779907993 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9394500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2264500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3475237498 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5186519493 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 8673415991 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9394500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2264500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3475237498 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5186519493 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21677740222 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 30351156213 # number of overall MSHR miss cycles
1466,1469c1463,1466
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6368846000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6766966500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5178267462 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178267462 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369324000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6767444500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5178555462 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178555462 # number of WriteReq MSHR uncacheable cycles
1471,1475c1468,1472
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547113462 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945233962 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.005929 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547879462 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945999962 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005649 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007305 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.005965 # mshr miss rate for ReadReq accesses
1478,1481c1475,1478
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999951 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999951 # mshr miss rate for SCUpgradeReq accesses
1484,1498c1481,1495
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148042 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148042 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041554 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184330 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184330 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171674 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088088 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171674 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151020 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151020 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042186 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184281 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184281 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005649 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.007305 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172696 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088851 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005649 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.007305 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172696 # mshr miss rate for overall accesses
1500,1528c1497,1525
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.206922 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28255.656109 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84762.290433 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26370.495617 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26370.495617 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17777.528207 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17777.528207 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 234249 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234249 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60278.082852 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60278.082852 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63253.262785 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28938.767033 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28938.767033 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45374.487804 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67994.717128 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208598 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27309.593023 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25966.592428 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82410.767063 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82410.767063 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26130.289096 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26130.289096 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17910.809378 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17910.809378 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 152749.250000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 152749.250000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56739.632206 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56739.632206 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62641.722809 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62641.722809 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28707.974399 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28707.974399 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27309.593023 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62641.722809 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37246.367967 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44438.947365 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27309.593023 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62641.722809 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37246.367967 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82410.767063 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66236.938536 # average overall mshr miss latency
1530,1533c1527,1530
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200221.509636 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194380.446959 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181738.232619 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181738.232619 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200211.360136 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194371.844214 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181722.829140 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181722.829140 # average WriteReq mshr uncacheable latency
1535,1536c1532,1533
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191488.067759 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188690.392096 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191475.368297 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188678.648672 # average overall mshr uncacheable latency
1538,1575c1535,1572
< system.cpu0.toL2Bus.snoop_filter.tot_requests 4279317 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162325 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 327449 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 323077 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 121937 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 2006842 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 739077 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 1523954 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 209281 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 317808 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 85654 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42585 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 113145 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 298662 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 295385 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312870 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595361 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 3427 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3918545 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2723305 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 31953 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 129711 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 6803514 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166426752 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103211806 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 57692 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 240524 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 269936774 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 1020233 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 3250109 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.119815 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.328862 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 4287266 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2165878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33429 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 330817 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 325927 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4890 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 121349 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 2010442 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28497 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28497 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 741210 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 1560498 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 209521 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 320891 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 86097 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42565 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 113963 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 298891 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 295589 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1315095 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595916 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 3396 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3950726 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739036 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 31654 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130125 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 6851541 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 168343936 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103984190 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 57496 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 243592 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 272629214 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 1021824 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 3257313 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.120341 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.329941 # Request fanout histogram
1577,1579c1574,1576
< system.cpu0.toL2Bus.snoop_fanout::0 2865068 88.15% 88.15% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 380669 11.71% 99.87% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 4372 0.13% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 2870216 88.12% 88.12% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 382207 11.73% 99.85% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 4890 0.15% 100.00% # Request fanout histogram
1583,1584c1580,1581
< system.cpu0.toL2Bus.snoop_fanout::total 3250109 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 4279335949 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 3257313 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 4288108443 # Layer occupancy (ticks)
1586c1583
< system.cpu0.toL2Bus.snoopLayer0.occupancy 113715191 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 113808525 # Layer occupancy (ticks)
1588c1585
< system.cpu0.toL2Bus.respLayer0.occupancy 1972888832 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1976208867 # Layer occupancy (ticks)
1590c1587
< system.cpu0.toL2Bus.respLayer1.occupancy 1291542228 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1295252494 # Layer occupancy (ticks)
1592c1589
< system.cpu0.toL2Bus.respLayer2.occupancy 17537485 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 17289481 # Layer occupancy (ticks)
1594c1591
< system.cpu0.toL2Bus.respLayer3.occupancy 69622914 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 69274405 # Layer occupancy (ticks)
1596,1600c1593,1597
< system.cpu1.branchPred.lookups 4034173 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 2335207 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 244345 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 2038897 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 1508183 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 3960492 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 2278371 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 239603 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 1992874 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 1474633 # Number of BTB hits
1602,1604c1599,1601
< system.cpu1.branchPred.BTBHitPct 73.970534 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 793679 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 5620 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 73.995295 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 786361 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 6053 # Number of incorrect RAS predictions.
1634,1677c1631,1674
< system.cpu1.dtb.walker.walks 15746 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 15746 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8388 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3065 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 4293 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 11453 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 595.826421 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 3233.762475 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-4095 10927 95.41% 95.41% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::4096-8191 176 1.54% 96.94% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::8192-12287 209 1.82% 98.77% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::12288-16383 35 0.31% 99.07% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.19% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.39% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::24576-28671 3 0.03% 99.42% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::28672-32767 42 0.37% 99.78% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::32768-36863 20 0.17% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 11453 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 3271 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 11706.970345 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 10400.215389 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 7344.366479 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-16383 2791 85.33% 85.33% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-32767 443 13.54% 98.87% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-49151 31 0.95% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.09% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 3271 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 78450006060 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.184600 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.390418 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 63997466940 81.58% 81.58% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 14437247120 18.40% 99.98% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2 10341500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::3 2133500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4 875500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::5 457000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6 962000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::7 87500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8 30500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::9 79000 0.00% 100.00% # Table walker pending requests distribution
---
> system.cpu1.dtb.walker.walks 15222 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 15222 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 7935 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3046 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 4241 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 10981 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 629.359803 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 3543.870184 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-8191 10629 96.79% 96.79% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::8192-16383 248 2.26% 99.05% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::16384-24575 28 0.25% 99.31% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::24576-32767 51 0.46% 99.77% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::32768-40959 21 0.19% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::81920-90111 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::90112-98303 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 10981 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 11717.562048 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 10260.840497 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 8597.667676 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-16383 2739 86.05% 86.05% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-32767 395 12.41% 98.46% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-49151 36 1.13% 99.59% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.09% 99.69% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::81920-98303 1 0.03% 99.72% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::98304-114687 6 0.19% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-147455 2 0.06% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 78410323560 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.145148 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.354804 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 67057915756 85.52% 85.52% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::1 11337246804 14.46% 99.98% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2 10462000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::3 1830000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4 951000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::5 350500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6 990500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::7 120500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8 94000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::9 139000 0.00% 100.00% # Table walker pending requests distribution
1679,1688c1676,1685
< system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12 54000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::13 17000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14 17500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::15 175000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 78450006060 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 1233 71.11% 71.11% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 501 28.89% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 1734 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15746 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walksPending::11 14500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12 22500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::13 12000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14 7500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::15 153000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 78410323560 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1233 73.13% 73.13% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 453 26.87% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 1686 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15222 # Table walker requests started/completed, data/inst
1690,1691c1687,1688
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15746 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1734 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15222 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1686 # Table walker requests started/completed, data/inst
1693,1694c1690,1691
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1734 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 17480 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1686 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 16908 # Table walker requests started/completed, data/inst
1697,1700c1694,1697
< system.cpu1.dtb.read_hits 3564995 # DTB read hits
< system.cpu1.dtb.read_misses 13832 # DTB read misses
< system.cpu1.dtb.write_hits 3032176 # DTB write hits
< system.cpu1.dtb.write_misses 1914 # DTB write misses
---
> system.cpu1.dtb.read_hits 3499603 # DTB read hits
> system.cpu1.dtb.read_misses 13349 # DTB read misses
> system.cpu1.dtb.write_hits 2989645 # DTB write hits
> system.cpu1.dtb.write_misses 1873 # DTB write misses
1705,1707c1702,1704
< system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 34 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 1646 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 45 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 267 # Number of TLB faults due to prefetch
1709,1711c1706,1708
< system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 3578827 # DTB read accesses
< system.cpu1.dtb.write_accesses 3034090 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 3512952 # DTB read accesses
> system.cpu1.dtb.write_accesses 2991518 # DTB write accesses
1713,1715c1710,1712
< system.cpu1.dtb.hits 6597171 # DTB hits
< system.cpu1.dtb.misses 15746 # DTB misses
< system.cpu1.dtb.accesses 6612917 # DTB accesses
---
> system.cpu1.dtb.hits 6489248 # DTB hits
> system.cpu1.dtb.misses 15222 # DTB misses
> system.cpu1.dtb.accesses 6504470 # DTB accesses
1745,1784c1742,1782
< system.cpu1.itb.walker.walks 6257 # Table walker walks requested
< system.cpu1.itb.walker.walksShort 6257 # Table walker walks initiated with short descriptors
< system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3920 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2276 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksSquashedBefore 61 # Table walks squashed before starting
< system.cpu1.itb.walker.walkWaitTime::samples 6196 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 206.181407 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 1542.947362 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-4095 6076 98.06% 98.06% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::4096-8191 60 0.97% 99.03% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::8192-12287 39 0.63% 99.66% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.11% 99.77% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.08% 99.85% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.06% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 6196 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 896 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 11471.540179 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 10591.082273 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5713.555798 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-8191 197 21.99% 21.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-16383 650 72.54% 94.53% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-24575 13 1.45% 95.98% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-32767 24 2.68% 98.66% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.56% 99.22% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.22% 99.44% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.45% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.11% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 896 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 13992892620 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.945402 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.227238 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 764122764 5.46% 5.46% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 13228629356 94.54% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 140500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 13992892620 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 692 82.87% 82.87% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::1M 143 17.13% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 835 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 6092 # Table walker walks requested
> system.cpu1.itb.walker.walksShort 6092 # Table walker walks initiated with short descriptors
> system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3792 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2256 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksSquashedBefore 44 # Table walks squashed before starting
> system.cpu1.itb.walker.walkWaitTime::samples 6048 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 194.031085 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 1498.555311 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-4095 5941 98.23% 98.23% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::4096-8191 54 0.89% 99.12% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.58% 99.70% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.12% 99.82% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::16384-20479 3 0.05% 99.87% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 6048 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 878 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 11682.801822 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 10808.720287 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5784.559551 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-8191 174 19.82% 19.82% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-16383 650 74.03% 93.85% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-24575 15 1.71% 95.56% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-32767 28 3.19% 98.75% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.57% 99.32% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.34% 99.66% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.11% 99.77% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.11% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.11% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 878 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 13953243120 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.946198 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.225667 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 750840264 5.38% 5.38% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 13202275856 94.62% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 127000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 13953243120 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 691 82.85% 82.85% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::1M 143 17.15% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 834 # Table walker page sizes translated
1786,1787c1784,1785
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6257 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6257 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6092 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6092 # Table walker requests started/completed, data/inst
1789,1793c1787,1791
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 835 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 835 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 7092 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 7247489 # ITB inst hits
< system.cpu1.itb.inst_misses 6257 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 834 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 834 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 6926 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 7131526 # ITB inst hits
> system.cpu1.itb.inst_misses 6092 # ITB inst misses
1802c1800
< system.cpu1.itb.flush_entries 899 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 898 # Number of entries that have been flushed from TLB
1806c1804
< system.cpu1.itb.perms_faults 342 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 335 # Number of TLB faults due to permissions restrictions
1809,1813c1807,1811
< system.cpu1.itb.inst_accesses 7253746 # ITB inst accesses
< system.cpu1.itb.hits 7247489 # DTB hits
< system.cpu1.itb.misses 6257 # DTB misses
< system.cpu1.itb.accesses 7253746 # DTB accesses
< system.cpu1.numCycles 32825676 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 7137618 # ITB inst accesses
> system.cpu1.itb.hits 7131526 # DTB hits
> system.cpu1.itb.misses 6092 # DTB misses
> system.cpu1.itb.accesses 7137618 # DTB accesses
> system.cpu1.numCycles 32153663 # number of cpu cycles simulated
1816,1832c1814,1830
< system.cpu1.fetch.icacheStallCycles 8001289 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 21471337 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 4034173 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 2301862 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 23036367 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 699414 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 85773 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 29291 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 185520 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 275269 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 17468 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 7247139 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 103562 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 31980684 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.819942 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.194084 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 7900141 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 21121078 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 3960492 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 2260994 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 22525520 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 690384 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 85873 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 36828 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 183368 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 268596 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 16764 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 7131220 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 101425 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 2175 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 31362282 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.823323 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.195698 # Number of instructions fetched each cycle (Total)
1834,1837c1832,1835
< system.cpu1.fetch.rateDist::0 19847655 62.06% 62.06% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 4393311 13.74% 75.80% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 1390148 4.35% 80.15% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 6349570 19.85% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 19419839 61.92% 61.92% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 4322960 13.78% 75.70% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 1360110 4.34% 80.04% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 6259373 19.96% 100.00% # Number of instructions fetched each cycle (Total)
1841,1867c1839,1865
< system.cpu1.fetch.rateDist::total 31980684 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.122897 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.654102 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 6559156 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 16660335 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 7594258 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 935690 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 231245 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 620374 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 121000 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 20120105 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 926045 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 231245 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 7803762 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 2337008 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 11658570 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 7267589 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 2682510 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 19097640 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 153089 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 210195 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 28229 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 13307 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 1810658 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 18872486 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 89304984 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 22006430 # Number of integer rename lookups
---
> system.cpu1.fetch.rateDist::total 31362282 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.123174 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.656879 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 6476013 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 16288433 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 7449358 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 919688 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 228790 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 612596 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 118905 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 19752784 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 909327 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 228790 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 7703782 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 2255288 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 11537440 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 7124756 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 2512226 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 18734047 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 149896 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 201471 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 27483 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 12915 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 1654980 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 18476585 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 87682069 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 21592076 # Number of integer rename lookups
1869,1887c1867,1885
< system.cpu1.rename.CommittedMaps 16903103 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 1969383 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 373801 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 306197 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 2490350 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 3798024 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 3334408 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 558239 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 459403 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 18396455 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 514218 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 18243143 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 80370 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 1798248 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 4138161 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 41963 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 31980684 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.570443 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 0.921832 # Number of insts issued each cycle
---
> system.cpu1.rename.CommittedMaps 16547143 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1929442 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 373208 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 305811 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 2461191 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 3733224 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 3288117 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 552829 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 458093 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 18036557 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 513632 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 17896075 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 81001 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 1765820 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 4051574 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 42199 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 31362282 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.570624 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 0.921463 # Number of insts issued each cycle
1889,1894c1887,1892
< system.cpu1.iq.issued_per_cycle::0 21156406 66.15% 66.15% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 5430198 16.98% 83.13% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 3595564 11.24% 94.38% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 1572256 4.92% 99.29% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 226251 0.71% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 20726941 66.09% 66.09% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 5363186 17.10% 83.19% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 3506961 11.18% 94.37% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 1541817 4.92% 99.29% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 223369 0.71% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle
1901c1899
< system.cpu1.iq.issued_per_cycle::total 31980684 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 31362282 # Number of insts issued each cycle
1903,1933c1901,1931
< system.cpu1.iq.fu_full::IntAlu 1148262 27.95% 27.95% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 668 0.02% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.97% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 1340987 32.64% 60.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 1618003 39.39% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 1114950 27.66% 27.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 668 0.02% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 1322557 32.82% 60.50% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 1592153 39.50% 100.00% # attempts to use FU when none available
1937,1967c1935,1965
< system.cpu1.iq.FU_type_0::IntAlu 11255159 61.70% 61.70% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 26433 0.14% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 3176 0.02% 61.86% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 3744432 20.53% 82.38% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 3213919 17.62% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 11018686 61.57% 61.57% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 25379 0.14% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.71% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 3144 0.02% 61.73% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.73% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.73% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.73% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 3679682 20.56% 82.29% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 3169160 17.71% 100.00% # Type of FU issued
1970,1976c1968,1974
< system.cpu1.iq.FU_type_0::total 18243143 # Type of FU issued
< system.cpu1.iq.rate 0.555758 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 4107920 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.225176 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 72655260 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 20717149 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 17851675 # Number of integer instruction queue wakeup accesses
---
> system.cpu1.iq.FU_type_0::total 17896075 # Type of FU issued
> system.cpu1.iq.rate 0.556580 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 4030328 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.225207 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 71265761 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 20324002 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 17511405 # Number of integer instruction queue wakeup accesses
1980c1978
< system.cpu1.iq.int_alu_accesses 22351039 # Number of integer alu accesses
---
> system.cpu1.iq.int_alu_accesses 21926379 # Number of integer alu accesses
1982c1980
< system.cpu1.iew.lsq.thread0.forwLoads 72767 # Number of loads that had data forwarded from stores
---
> system.cpu1.iew.lsq.thread0.forwLoads 71343 # Number of loads that had data forwarded from stores
1984,1987c1982,1985
< system.cpu1.iew.lsq.thread0.squashedLoads 344909 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 550 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 8264 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 279088 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 337548 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 8028 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 276059 # Number of stores squashed
1990,1991c1988,1989
< system.cpu1.iew.lsq.thread0.rescheduledLoads 35940 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 54533 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 35249 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 51219 # Number of times an access to memory failed due to the cache being blocked
1993,1996c1991,1994
< system.cpu1.iew.iewSquashCycles 231245 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 541574 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 157299 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 18927437 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 228790 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 526676 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 150264 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 18566765 # Number of instructions dispatched to IQ
1998,2009c1996,2007
< system.cpu1.iew.iewDispLoadInsts 3798024 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 3334408 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 272337 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 6587 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 145035 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 8264 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 30633 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 103644 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 134277 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 18042171 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 3670535 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 185229 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 3733224 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 3288117 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 271755 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 6489 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 137973 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 8028 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 29675 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 101337 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 131012 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 17697567 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 3606675 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 183289 # Number of squashed instructions skipped in execute
2011,2027c2009,2025
< system.cpu1.iew.exec_nop 16764 # number of nop insts executed
< system.cpu1.iew.exec_refs 6830795 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 2603132 # Number of branches executed
< system.cpu1.iew.exec_stores 3160260 # Number of stores executed
< system.cpu1.iew.exec_rate 0.549636 # Inst execution rate
< system.cpu1.iew.wb_sent 17938795 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 17851675 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 8886835 # num instructions producing a value
< system.cpu1.iew.wb_consumers 13789507 # num instructions consuming a value
< system.cpu1.iew.wb_rate 0.543833 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.644464 # average fanout of values written-back
< system.cpu1.commit.commitSquashedInsts 1628624 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 472255 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 125883 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 31615084 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.541371 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.295044 # Number of insts commited each cycle
---
> system.cpu1.iew.exec_nop 16576 # number of nop insts executed
> system.cpu1.iew.exec_refs 6722071 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 2541515 # Number of branches executed
> system.cpu1.iew.exec_stores 3115396 # Number of stores executed
> system.cpu1.iew.exec_rate 0.550406 # Inst execution rate
> system.cpu1.iew.wb_sent 17598968 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 17511405 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 8692607 # num instructions producing a value
> system.cpu1.iew.wb_consumers 13471004 # num instructions consuming a value
> system.cpu1.iew.wb_rate 0.544616 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.645283 # average fanout of values written-back
> system.cpu1.commit.commitSquashedInsts 1597357 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 471433 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 123201 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 31002866 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.541480 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.295585 # Number of insts commited each cycle
2029,2037c2027,2035
< system.cpu1.commit.committed_per_cycle::0 23337715 73.82% 73.82% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 4942860 15.63% 89.45% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 1433345 4.53% 93.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 542164 1.71% 95.70% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 455708 1.44% 97.14% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 302171 0.96% 98.10% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 181914 0.58% 98.67% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 99381 0.31% 98.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 319826 1.01% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 22873291 73.78% 73.78% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 4864873 15.69% 89.47% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 1409236 4.55% 94.02% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 529319 1.71% 95.72% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 438451 1.41% 97.14% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 294402 0.95% 98.09% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 179192 0.58% 98.66% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 97652 0.31% 98.98% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 316450 1.02% 100.00% # Number of insts commited each cycle
2041,2043c2039,2041
< system.cpu1.commit.committed_per_cycle::total 31615084 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 13986698 # Number of instructions committed
< system.cpu1.commit.committedOps 17115488 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 31002866 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 13696177 # Number of instructions committed
> system.cpu1.commit.committedOps 16787432 # Number of ops (including micro ops) committed
2045,2048c2043,2046
< system.cpu1.commit.refs 6508435 # Number of memory references committed
< system.cpu1.commit.loads 3453115 # Number of loads committed
< system.cpu1.commit.membars 191139 # Number of memory barriers committed
< system.cpu1.commit.branches 2479082 # Number of branches committed
---
> system.cpu1.commit.refs 6407734 # Number of memory references committed
> system.cpu1.commit.loads 3395676 # Number of loads committed
> system.cpu1.commit.membars 190902 # Number of memory barriers committed
> system.cpu1.commit.branches 2419020 # Number of branches committed
2050,2051c2048,2049
< system.cpu1.commit.int_insts 15267561 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 414980 # Number of function calls committed.
---
> system.cpu1.commit.int_insts 14992163 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 410100 # Number of function calls committed.
2053,2083c2051,2081
< system.cpu1.commit.op_class_0::IntAlu 10578262 61.81% 61.81% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 25615 0.15% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 3176 0.02% 61.97% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.97% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.97% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.97% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 3453115 20.18% 82.15% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 3055320 17.85% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 10351952 61.66% 61.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 24602 0.15% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 3144 0.02% 61.83% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.83% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.83% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.83% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 3395676 20.23% 82.06% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 3012058 17.94% 100.00% # Class of committed instruction
2086,2197c2084,2195
< system.cpu1.commit.op_class_0::total 17115488 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 319826 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 49145756 # The number of ROB reads
< system.cpu1.rob.rob_writes 37850174 # The number of ROB writes
< system.cpu1.timesIdled 55034 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 844992 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 5621633430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 13983634 # Number of Instructions Simulated
< system.cpu1.committedOps 17112424 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 2.347435 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 2.347435 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.425997 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.425997 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 20215691 # number of integer regfile reads
< system.cpu1.int_regfile_writes 11658166 # number of integer regfile writes
< system.cpu1.cc_regfile_reads 64782198 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 5550427 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 46731168 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 350339 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 150744 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 471.669505 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 5845075 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 151083 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 38.687840 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 104824569000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.669505 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921230 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.921230 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 328 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 12896760 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 12896760 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 3092594 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 3092594 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 2524465 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 2524465 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42426 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 42426 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70168 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 70168 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61430 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 61430 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 5617059 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 5617059 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 5659485 # number of overall hits
< system.cpu1.dcache.overall_hits::total 5659485 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 178952 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 178952 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 316827 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 316827 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23604 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 23604 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17348 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 17348 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23299 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23299 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 495779 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 495779 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 519383 # number of overall misses
< system.cpu1.dcache.overall_misses::total 519383 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3441746500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 3441746500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11862734947 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 11862734947 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362002500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 362002500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 631001500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 631001500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1169000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1169000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 15304481447 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 15304481447 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 15304481447 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 15304481447 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 3271546 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3271546 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 2841292 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 2841292 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66030 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 66030 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87516 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 87516 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84729 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 84729 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 6112838 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 6112838 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 6178868 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 6178868 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054700 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.054700 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111508 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.111508 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.357474 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.357474 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.198227 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.198227 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274983 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274983 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081105 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.081105 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084058 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.084058 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19232.791475 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 19232.791475 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37442.310621 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 37442.310621 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20867.102836 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20867.102836 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27082.771793 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27082.771793 # average StoreCondReq miss latency
---
> system.cpu1.commit.op_class_0::total 16787432 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 316450 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 48173976 # The number of ROB reads
> system.cpu1.rob.rob_writes 37125010 # The number of ROB writes
> system.cpu1.timesIdled 52987 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 791381 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 5622225995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 13693113 # Number of Instructions Simulated
> system.cpu1.committedOps 16784368 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 2.348163 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 2.348163 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.425865 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.425865 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 19830637 # number of integer regfile reads
> system.cpu1.int_regfile_writes 11457060 # number of integer regfile writes
> system.cpu1.cc_regfile_reads 63567667 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 5386626 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 46959699 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 351107 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 146387 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 464.874328 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 5757831 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 146736 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 39.239389 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 89642414500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 464.874328 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.907958 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.907958 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 12687956 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 12687956 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 3034292 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3034292 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 2492465 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 2492465 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42455 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 42455 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70401 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 70401 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61757 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 61757 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 5526757 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 5526757 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 5569212 # number of overall hits
> system.cpu1.dcache.overall_hits::total 5569212 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 176347 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 176347 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 307156 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 307156 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23291 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 23291 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17298 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 17298 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23328 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23328 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 483503 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 483503 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 506794 # number of overall misses
> system.cpu1.dcache.overall_misses::total 506794 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277543500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3277543500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10809748445 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 10809748445 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 356539500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 356539500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 632211000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 632211000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1062000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1062000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 14087291945 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 14087291945 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 14087291945 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 14087291945 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 3210639 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3210639 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 2799621 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 2799621 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65746 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 65746 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87699 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 87699 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85085 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 85085 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 6010260 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 6010260 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 6076006 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 6076006 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054926 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.054926 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.109713 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.109713 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.354257 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.354257 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197243 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197243 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274173 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274173 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.080446 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.080446 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.083409 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.083409 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18585.762729 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 18585.762729 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35193.023887 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 35193.023887 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20611.602497 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20611.602497 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27100.951646 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27100.951646 # average StoreCondReq miss latency
2200,2209c2198,2207
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30869.563751 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 30869.563751 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29466.658414 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 29466.658414 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 1808008 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 30216 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.548387 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 59.836113 # average number of cycles each access was blocked
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29135.893562 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 29135.893562 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27796.879886 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 27796.879886 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 1608332 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 29276 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.735294 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 54.936877 # average number of cycles each access was blocked
2212,2289c2210,2287
< system.cpu1.dcache.writebacks::writebacks 150744 # number of writebacks
< system.cpu1.dcache.writebacks::total 150744 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62223 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 62223 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 237836 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 237836 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12586 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12586 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 300059 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 300059 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 300059 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 300059 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116729 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 116729 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78991 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 78991 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22881 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 22881 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4762 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4762 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23299 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23299 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 195720 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 195720 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 218601 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 218601 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3069 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3069 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5480 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5480 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1778715000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1778715000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2939877456 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2939877456 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 425185000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 425185000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98534500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98534500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 607713500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 607713500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1158000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1158000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4718592456 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4718592456 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5143777456 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5143777456 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 437774500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 437774500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 301405500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 301405500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 739180000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 739180000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035680 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035680 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027801 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027801 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.346524 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.346524 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054413 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054413 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274983 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274983 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035379 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.035379 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15237.987133 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15237.987133 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37217.878695 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 37217.878695 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18582.448320 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18582.448320 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 20691.831163 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 20691.831163 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26083.243916 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26083.243916 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 146387 # number of writebacks
> system.cpu1.dcache.writebacks::total 146387 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 61765 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 61765 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 230665 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 230665 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12462 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12462 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 292430 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 292430 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 292430 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 292430 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 114582 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 114582 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 76491 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 76491 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22561 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 22561 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4836 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4836 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23328 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23328 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 191073 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 191073 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 213634 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 213634 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3393 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3393 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2735 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2735 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6128 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6128 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1708391000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1708391000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2716718455 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2716718455 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 399807500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 399807500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95324000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95324000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 608894000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 608894000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1051000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1051000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4425109455 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4425109455 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4824916955 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4824916955 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 456207000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 456207000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 319373000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 319373000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 775580000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 775580000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035688 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035688 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027322 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027322 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.343154 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.343154 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055143 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055143 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274173 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274173 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031791 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031791 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035160 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035160 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14909.767677 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14909.767677 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35516.837994 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35516.837994 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17721.178139 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17721.178139 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19711.331679 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19711.331679 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26101.423182 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26101.423182 # average StoreCondReq mshr miss latency
2292,2301c2290,2299
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24108.892581 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24108.892581 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23530.438818 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23530.438818 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142644.020854 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142644.020854 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125012.650353 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125012.650353 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134886.861314 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134886.861314 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23159.260885 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23159.260885 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22584.967538 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22584.967538 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134455.349248 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134455.349248 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116772.577697 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 116772.577697 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126563.315927 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126563.315927 # average overall mshr uncacheable latency
2303,2311c2301,2309
< system.cpu1.icache.tags.replacements 551908 # number of replacements
< system.cpu1.icache.tags.tagsinuse 499.384443 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 6675021 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 552420 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 12.083236 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 79408503500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.384443 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975360 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.975360 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 545035 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.387406 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 6566366 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 545547 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 12.036298 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 79388435000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.387406 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975366 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.975366 # Average percentage of cache occupancy
2317,2360c2315,2358
< system.cpu1.icache.tags.tag_accesses 15046317 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 15046317 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 6675021 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 6675021 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 6675021 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 6675021 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 6675021 # number of overall hits
< system.cpu1.icache.overall_hits::total 6675021 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 571924 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 571924 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 571924 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 571924 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 571924 # number of overall misses
< system.cpu1.icache.overall_misses::total 571924 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5247903529 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 5247903529 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 5247903529 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 5247903529 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 5247903529 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 5247903529 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 7246945 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 7246945 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 7246945 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 7246945 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 7246945 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 7246945 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078919 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.078919 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078919 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.078919 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078919 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.078919 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9175.875692 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9175.875692 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9175.875692 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9175.875692 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9175.875692 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9175.875692 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 518390 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 40965 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.654461 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 146 # average number of cycles each access was blocked
---
> system.cpu1.icache.tags.tag_accesses 14807594 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 14807594 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 6566366 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 6566366 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 6566366 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 6566366 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 6566366 # number of overall hits
> system.cpu1.icache.overall_hits::total 6566366 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 564657 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 564657 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 564657 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 564657 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 564657 # number of overall misses
> system.cpu1.icache.overall_misses::total 564657 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5140866064 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 5140866064 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 5140866064 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 5140866064 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 5140866064 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 5140866064 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 7131023 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 7131023 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 7131023 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 7131023 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 7131023 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 7131023 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.079183 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.079183 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.079183 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.079183 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.079183 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.079183 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9104.405088 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 9104.405088 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9104.405088 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 9104.405088 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9104.405088 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 9104.405088 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 492404 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 97 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 39695 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.404686 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets 97 # average number of cycles each access was blocked
2363,2376c2361,2374
< system.cpu1.icache.writebacks::writebacks 551908 # number of writebacks
< system.cpu1.icache.writebacks::total 551908 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19497 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 19497 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 19497 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 19497 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 19497 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 19497 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 552427 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 552427 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 552427 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 552427 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 552427 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 552427 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 545035 # number of writebacks
> system.cpu1.icache.writebacks::total 545035 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19109 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 19109 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 19109 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 19109 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 19109 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 19109 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 545548 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 545548 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 545548 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 545548 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 545548 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 545548 # number of overall MSHR misses
2381,2406c2379,2404
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4796273338 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4796273338 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4796273338 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4796273338 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4796273338 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4796273338 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14117999 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14117999 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14117999 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 14117999 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076229 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.076229 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.076229 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8682.184864 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4699860850 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 4699860850 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4699860850 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 4699860850 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4699860850 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 4699860850 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13703500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13703500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13703500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 13703500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076503 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076503 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076503 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.076503 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076503 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.076503 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8614.935533 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8614.935533 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8614.935533 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8614.935533 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8614.935533 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8614.935533 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133043.689320 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133043.689320 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133043.689320 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133043.689320 # average overall mshr uncacheable latency
2408,2410c2406,2408
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 114901 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 115599 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 633 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 104122 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 104721 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 542 # number of redundant prefetches already in prefetch queue
2413,2418c2411,2416
< system.cpu1.l2cache.prefetcher.pfSpanPage 47913 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 38341 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15301.887572 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 1226523 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 53480 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 22.934237 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 47159 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 31230 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15089.646508 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 1211194 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 46334 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 26.140502 # Average number of references to valid blocks.
2420,2431c2418,2429
< system.cpu1.l2cache.tags.occ_blocks::writebacks 14854.525753 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 7.568708 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.883063 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 435.910048 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.906648 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000462 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000237 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026606 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.933953 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 923 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14155 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 14617.935135 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.988168 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.811204 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 457.912000 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.892208 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000610 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000233 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027949 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.920999 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 989 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14057 # Occupied blocks per task id
2433,2435c2431,2433
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 616 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 639 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 339 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
2437,2546c2435,2548
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 33 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 802 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2695 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10658 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056335 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.863953 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 24288275 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 24288275 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12056 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6824 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 18880 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 92484 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 92484 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 598066 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 598066 # number of WritebackClean hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16973 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 16973 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 541415 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 541415 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 78226 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 78226 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12056 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6824 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 541415 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 95199 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 655494 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12056 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6824 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 541415 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 95199 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 655494 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 455 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 292 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 747 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29477 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29477 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23299 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 23299 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33181 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 33181 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 11002 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 11002 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66142 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 66142 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 455 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 292 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 11002 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 99323 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 111072 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 455 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 292 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 11002 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 99323 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 111072 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10030500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5845500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 15876000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63278000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 63278000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 61670500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 61670500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1141500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1141500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1906360500 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1906360500 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658538999 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658538999 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1560865998 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1560865998 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10030500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5845500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658538999 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3467226498 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 4141641497 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10030500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5845500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658538999 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3467226498 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 4141641497 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12511 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7116 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 19627 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 92484 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 92484 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 598066 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 598066 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29477 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 29477 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23299 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23299 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50154 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 50154 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 552417 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 552417 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 144368 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 144368 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12511 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7116 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 552417 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 194522 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 766566 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12511 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7116 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 552417 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 194522 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 766566 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036368 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.041034 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.038060 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 795 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2682 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10580 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060364 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.857971 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 23905593 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 23905593 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 11685 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6708 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 18393 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 90174 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 90174 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 589051 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 589051 # number of WritebackClean hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16477 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 16477 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 535495 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 535495 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77565 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 77565 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 11685 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6708 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 535495 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 94042 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 647930 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 11685 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6708 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 535495 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 94042 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 647930 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 432 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 295 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 727 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28730 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 28730 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23326 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 23326 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 31913 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 31913 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10053 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 10053 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 64409 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 64409 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 432 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 295 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 10053 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 96322 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 107102 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 432 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 295 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 10053 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 96322 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 107102 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9521500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5794000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 15315500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 61496500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 61496500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 62755500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 62755500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1034500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1034500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1713894999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1713894999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 608578499 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 608578499 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1469826997 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1469826997 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9521500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5794000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 608578499 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3183721996 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3807615995 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9521500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5794000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 608578499 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3183721996 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3807615995 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12117 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7003 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 19120 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 90174 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 90174 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 589051 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 589051 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28730 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 28730 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23326 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23326 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 48390 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 48390 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 545548 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 545548 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141974 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 141974 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12117 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7003 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 545548 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 190364 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 755032 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12117 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7003 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 545548 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 190364 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 755032 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.035652 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.042125 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.038023 # miss rate for ReadReq accesses
2551,2592c2553,2596
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.661582 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.661582 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.019916 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019916 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.458149 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.458149 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036368 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.041034 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.019916 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.510600 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.144896 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036368 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.041034 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019916 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.510600 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.144896 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22045.054945 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20018.835616 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21253.012048 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2146.690640 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2146.690640 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2646.916177 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2646.916177 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 57453.376933 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 57453.376933 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59856.298764 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59856.298764 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23598.711832 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23598.711832 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22045.054945 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20018.835616 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59856.298764 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34908.596176 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 37287.898813 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22045.054945 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20018.835616 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59856.298764 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34908.596176 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 37287.898813 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 52 # number of cycles access was blocked
---
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.659496 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.659496 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018427 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018427 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.453668 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.453668 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.035652 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.042125 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018427 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.505989 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.141851 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.035652 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.042125 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018427 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.505989 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.141851 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22040.509259 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19640.677966 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21066.712517 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2140.497738 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2140.497738 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2690.366972 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2690.366972 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 517250 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 517250 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53705.229812 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53705.229812 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60537.003780 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60537.003780 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22820.211415 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22820.211415 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22040.509259 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19640.677966 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60537.003780 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33052.905837 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 35551.306185 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22040.509259 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19640.677966 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60537.003780 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33052.905837 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 35551.306185 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked
2594c2598
< system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
2596c2600
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 61.800000 # average number of cycles each access was blocked
2600,2601c2604,2605
< system.cpu1.l2cache.writebacks::writebacks 31325 # number of writebacks
< system.cpu1.l2cache.writebacks::total 31325 # number of writebacks
---
> system.cpu1.l2cache.writebacks::writebacks 25194 # number of writebacks
> system.cpu1.l2cache.writebacks::total 25194 # number of writebacks
2603,2610c2607,2614
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 17 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1215 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 1215 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 35 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits
---
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 18 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1004 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 1004 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 30 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits
2612,2615c2616,2619
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 17 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1250 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 1273 # number of demand (read+write) MSHR hits
---
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 18 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1034 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 1055 # number of demand (read+write) MSHR hits
2617,2646c2621,2652
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 17 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1250 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 1273 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 454 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 275 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 729 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 21206 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 21206 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29477 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29477 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23299 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23299 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31966 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 31966 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10997 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10997 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 66107 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 66107 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 454 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 275 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10997 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 98073 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 109799 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 454 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 275 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10997 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 98073 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 21206 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 131005 # number of overall MSHR misses
---
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 18 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1034 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 1055 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 431 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 708 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18894 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 18894 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28730 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28730 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23326 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23326 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 30909 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 30909 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10051 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10051 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 64379 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 64379 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 431 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10051 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95288 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 106047 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 431 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10051 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95288 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18894 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 124941 # number of overall MSHR misses
2648,2651c2654,2657
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3069 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3393 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3496 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2735 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2735 # number of WriteReq MSHR uncacheable
2653,2693c2659,2699
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5480 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5583 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7288000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3982000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11270000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1346298482 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1346298482 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 600399000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 600399000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 432262000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 432262000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1075500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1075500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1610738500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1610738500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 592445999 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 592445999 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1162092498 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1162092498 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7288000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3982000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 592445999 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2772830998 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 3376546997 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7288000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3982000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 592445999 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2772830998 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1346298482 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4722845479 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13345000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 413019000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 426364000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 283076496 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 283076496 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13345000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 696095496 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 709440496 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036288 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.038645 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.037143 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 6128 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 6231 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6917000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3905000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10822000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1067670505 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1067670505 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 582110500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 582110500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 433237000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 433237000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 968500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 968500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1451048500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1451048500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 548233499 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 548233499 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1082241497 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1082241497 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6917000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3905000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 548233499 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2533289997 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 3092345496 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6917000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3905000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 548233499 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2533289997 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1067670505 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4160016001 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12931000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 428763500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 441694500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 298620996 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 298620996 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12931000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 727384496 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 740315496 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035570 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.039554 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.037029 # mshr miss rate for ReadReq accesses
2700,2714c2706,2722
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637357 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637357 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019907 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457906 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457906 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036288 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.038645 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.504174 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.143235 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036288 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.038645 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.504174 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638748 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638748 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018424 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018424 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.453456 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.453456 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035570 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.039554 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018424 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500557 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140454 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035570 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.039554 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018424 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500557 # mshr miss rate for overall accesses
2716,2752c2724,2760
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170899 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15459.533608 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63486.677450 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20368.388913 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20368.388913 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18552.813425 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18552.813425 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50389.116561 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50389.116561 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53873.419933 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17578.962863 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17578.962863 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30752.074217 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36050.879577 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134577.712610 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134414.880202 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117410.408959 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117410.408959 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127024.725547 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127071.555794 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.165478 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15285.310734 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56508.442098 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56508.442098 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20261.416638 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20261.416638 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18573.137272 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18573.137272 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 484250 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 484250 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46945.824841 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46945.824841 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54545.169535 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16810.473866 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16810.473866 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26585.614107 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29160.141220 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26585.614107 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56508.442098 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33295.843646 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125543.689320 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126367.079281 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126342.820366 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109185.007678 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 109185.007678 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125543.689320 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118698.514360 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 118811.666827 # average overall mshr uncacheable latency
2754,2791c2762,2800
< system.cpu1.toL2Bus.snoop_filter.tot_requests 1510050 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 763127 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12108 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 172945 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 171137 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1808 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 26162 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 760461 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 125070 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 598066 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 92914 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 26023 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 70036 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41455 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 85358 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 57012 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 54811 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 552427 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 220569 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 25 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1646728 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729194 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15588 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27029 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2418539 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70023728 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24695290 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28464 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50044 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 94797526 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 371473 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1121639 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.173444 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.382865 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 1486808 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 750931 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12198 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 171006 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 168745 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2261 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 25827 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 751423 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2735 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2735 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 116660 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 601248 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 88861 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 22992 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 70535 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41533 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 84868 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 55768 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 52923 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 545548 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 220317 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 68 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1636337 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718931 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15307 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 26144 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2396719 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 69798960 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24301530 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28012 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48468 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 94176970 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 362810 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1100696 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.175235 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.385533 # Request fanout histogram
2793,2795c2802,2804
< system.cpu1.toL2Bus.snoop_fanout::0 928905 82.82% 82.82% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 190926 17.02% 99.84% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 1808 0.16% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 910077 82.68% 82.68% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 188358 17.11% 99.79% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 2261 0.21% 100.00% # Request fanout histogram
2799,2800c2808,2809
< system.cpu1.toL2Bus.snoop_fanout::total 1121639 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1469339490 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1100696 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1446777487 # Layer occupancy (ticks)
2802c2811
< system.cpu1.toL2Bus.snoopLayer0.occupancy 79587436 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 80382983 # Layer occupancy (ticks)
2804c2813
< system.cpu1.toL2Bus.respLayer0.occupancy 828867751 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 818547754 # Layer occupancy (ticks)
2806c2815
< system.cpu1.toL2Bus.respLayer1.occupancy 323642126 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 317524641 # Layer occupancy (ticks)
2808c2817
< system.cpu1.toL2Bus.respLayer2.occupancy 8481980 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 8315477 # Layer occupancy (ticks)
2810c2819
< system.cpu1.toL2Bus.respLayer3.occupancy 14527980 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 14039475 # Layer occupancy (ticks)
2862c2871
< system.iobus.reqLayer0.occupancy 40431500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 40401000 # Layer occupancy (ticks)
2864c2873
< system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 111000 # Layer occupancy (ticks)
2866c2875
< system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks)
2870c2879
< system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
2872c2881
< system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
2874c2883
< system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 591500 # Layer occupancy (ticks)
2876c2885
< system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks)
2878c2887
< system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2884c2893
< system.iobus.reqLayer16.occupancy 49500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks)
2888c2897
< system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
2894c2903
< system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2896c2905
< system.iobus.reqLayer23.occupancy 6146000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks)
2898c2907
< system.iobus.reqLayer24.occupancy 34110000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 34127000 # Layer occupancy (ticks)
2900c2909
< system.iobus.reqLayer25.occupancy 186335542 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187100472 # Layer occupancy (ticks)
2907c2916
< system.iocache.tags.tagsinuse 14.549511 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.549835 # Cycle average of tags in use
2911,2914c2920,2923
< system.iocache.tags.warmup_cycle 256320229000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.549511 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.909344 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.909344 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 256259438000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.549835 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.909365 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.909365 # Average percentage of cache occupancy
2928,2935c2937,2944
< system.iocache.ReadReq_miss_latency::realview.ide 32965876 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 32965876 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4737835666 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4737835666 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 32965876 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 32965876 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 32965876 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 32965876 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 32651377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 32651377 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4576002095 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4576002095 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 32651377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 32651377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 32651377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 32651377 # number of overall miss cycles
2952,2960c2961,2969
< system.iocache.ReadReq_avg_miss_latency::realview.ide 130816.968254 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 130816.968254 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130792.724879 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 130792.724879 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 130816.968254 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 130816.968254 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 713 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 129568.956349 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 129568.956349 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126325.146174 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 126325.146174 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 129568.956349 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 129568.956349 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 129568.956349 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 129568.956349 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2962c2971
< system.iocache.blocked::no_mshrs 91 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2964c2973
< system.iocache.avg_blocked_cycles::no_mshrs 7.835165 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2978,2985c2987,2994
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 20365876 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 20365876 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2926635666 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2926635666 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 20365876 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 20365876 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 20365876 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 20365876 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 20051377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 20051377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763118347 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2763118347 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 20051377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 20051377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 20051377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 20051377 # number of overall MSHR miss cycles
2994,3001c3003,3010
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80816.968254 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 80816.968254 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80792.724879 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80792.724879 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79568.956349 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 79568.956349 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76278.664615 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76278.664615 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 79568.956349 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 79568.956349 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 79568.956349 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 79568.956349 # average overall mshr miss latency
3003,3007c3012,3016
< system.l2c.tags.replacements 131293 # number of replacements
< system.l2c.tags.tagsinuse 63152.978828 # Cycle average of tags in use
< system.l2c.tags.total_refs 442353 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 195350 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.264413 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 124416 # number of replacements
> system.l2c.tags.tagsinuse 63285.129344 # Cycle average of tags in use
> system.l2c.tags.total_refs 440296 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 188523 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.335503 # Average number of references to valid blocks.
3009,3037c3018,3045
< system.l2c.tags.occ_blocks::writebacks 13838.997413 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.349981 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 1.060621 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 8045.868087 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 2735.320064 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33659.346102 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.413836 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909660 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1799.024775 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 856.706825 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2190.981465 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.211166 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.122770 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.041738 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.513601 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.027451 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.013072 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033432 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.963638 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 30319 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 33712 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 6038 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 24164 # Occupied blocks per task id
---
> system.l2c.tags.occ_blocks::writebacks 13134.904875 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.362165 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 2.695219 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 8133.848343 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 2874.315443 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35508.928641 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.483607 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1685.782920 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 491.980320 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1432.827811 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.200423 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000234 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000041 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.124113 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.043859 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.541823 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.025723 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.007507 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.021863 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.965654 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 30961 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 33119 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 318 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 6018 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 24625 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
3040,3065c3048,3073
< system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 622 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 4436 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 28625 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.462631 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000397 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.514404 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6100734 # Number of tag accesses
< system.l2c.tags.data_accesses 6100734 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 264718 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 264718 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 32582 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 2383 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 34965 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 2172 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 943 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 3115 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4024 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1119 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5143 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 183 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 74 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 34982 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 48772 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46702 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 30 # number of ReadSharedReq hits
---
> system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 608 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 4362 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 28117 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.472427 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.505356 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6003066 # Number of tag accesses
> system.l2c.tags.data_accesses 6003066 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 259699 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 259699 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 32958 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 1822 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 34780 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 2116 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 991 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 3107 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4295 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1377 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5672 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 80 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 35927 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 48996 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47632 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 35 # number of ReadSharedReq hits
3067,3076c3075,3084
< system.l2c.ReadSharedReq_hits::cpu1.inst 8142 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 6412 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3079 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 148391 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 34982 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 52796 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 46702 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 30 # number of demand (read+write) hits
---
> system.l2c.ReadSharedReq_hits::cpu1.inst 7348 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 5260 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 2775 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 148252 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 35927 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 53291 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 47632 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 35 # number of demand (read+write) hits
3078,3087c3086,3095
< system.l2c.demand_hits::cpu1.inst 8142 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 7531 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 3079 # number of demand (read+write) hits
< system.l2c.demand_hits::total 153534 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 183 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 34982 # number of overall hits
< system.l2c.overall_hits::cpu0.data 52796 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 46702 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 30 # number of overall hits
---
> system.l2c.demand_hits::cpu1.inst 7348 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 6637 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 2775 # number of demand (read+write) hits
> system.l2c.demand_hits::total 153924 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 35927 # number of overall hits
> system.l2c.overall_hits::cpu0.data 53291 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 47632 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 35 # number of overall hits
3089,3305c3097,3301
< system.l2c.overall_hits::cpu1.inst 8142 # number of overall hits
< system.l2c.overall_hits::cpu1.data 7531 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 3079 # number of overall hits
< system.l2c.overall_hits::total 153534 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 9630 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 11930 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 789 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1228 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 2017 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11769 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 9002 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 20771 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 32 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 19572 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 9277 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134592 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 2853 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 1343 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 7007 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 174687 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 32 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 19572 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 21046 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 134592 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 2853 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 10345 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 7007 # number of demand (read+write) misses
< system.l2c.demand_misses::total 195458 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 32 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 19572 # number of overall misses
< system.l2c.overall_misses::cpu0.data 21046 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 134592 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 2853 # number of overall misses
< system.l2c.overall_misses::cpu1.data 10345 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 7007 # number of overall misses
< system.l2c.overall_misses::total 195458 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 24914000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 5940500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 30854500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4111000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2758000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 6869000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1778582000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 1203023000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 2981605000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4841000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2598359001 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 1294263000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21242920310 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 929500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 133000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 386572500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 186522500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1271879384 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 26986808195 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 4841000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 2598359001 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 3072845000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21242920310 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 929500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 386572500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1389545500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1271879384 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 29968413195 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 4841000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 2598359001 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 3072845000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21242920310 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 929500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 386572500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1389545500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1271879384 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 29968413195 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 264718 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 264718 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 42212 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 4683 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 46895 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 2961 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 2171 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 5132 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 15793 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 10121 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 25914 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 215 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 77 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 54554 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 58049 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 181294 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 37 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 16 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 10995 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 7755 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10086 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 323078 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 215 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 54554 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 73842 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 181294 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 37 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 16 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 10995 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 17876 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10086 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 348992 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 215 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 54554 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 73842 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 181294 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 37 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 16 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 10995 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 17876 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10086 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 348992 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.228134 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.491138 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.254398 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.266464 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.565638 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.393024 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.745204 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.889438 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.801536 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148837 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.038961 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.358764 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.159813 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.742396 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.189189 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.062500 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.259482 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173179 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.694725 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.540696 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.148837 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.038961 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.358764 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.285014 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.742396 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.189189 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.062500 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.259482 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.578709 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.694725 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.560064 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.148837 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.038961 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.358764 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.285014 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.742396 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.189189 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.062500 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.259482 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.578709 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.694725 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.560064 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2587.123572 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2582.826087 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2586.295054 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5210.392902 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2245.928339 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3405.552801 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151124.309627 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133639.524550 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 143546.531221 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 151281.250000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132758.992489 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139513.096906 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132785.714286 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135496.845426 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138884.959047 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 154486.642939 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 151281.250000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 132758.992489 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 146006.129431 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132785.714286 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 135496.845426 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 134320.492992 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 153324.055270 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 151281.250000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 132758.992489 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 146006.129431 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132785.714286 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 135496.845426 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 134320.492992 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 153324.055270 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 244 # number of cycles access was blocked
---
> system.l2c.overall_hits::cpu1.inst 7348 # number of overall hits
> system.l2c.overall_hits::cpu1.data 6637 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 2775 # number of overall hits
> system.l2c.overall_hits::total 153924 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 9722 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 2335 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 12057 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 856 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1275 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 2131 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11049 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 7844 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 18893 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 19551 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 9160 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132619 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 2702 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 942 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5641 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 170652 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 19551 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 20209 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 132619 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 2702 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8786 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 5641 # number of demand (read+write) misses
> system.l2c.demand_misses::total 189545 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 19551 # number of overall misses
> system.l2c.overall_misses::cpu0.data 20209 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 132619 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 2702 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8786 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 5641 # number of overall misses
> system.l2c.overall_misses::total 189545 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 26536500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 4336000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 30872500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 5860500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2953500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 8814000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1676214000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1047435000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 2723649000 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3711000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 521000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2599690001 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 1274805500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20824441779 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 838500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 362692000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 133047500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 997218792 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 26196966072 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 3711000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 521000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 2599690001 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 2951019500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20824441779 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 838500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 362692000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1180482500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 997218792 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 28920615072 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 3711000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 521000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 2599690001 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 2951019500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20824441779 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 838500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 362692000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1180482500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 997218792 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 28920615072 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 259699 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 259699 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 42680 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 4157 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 46837 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 2972 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 2266 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 5238 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15344 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 9221 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 24565 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 211 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 84 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 55478 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 58156 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180251 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 41 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 15 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 10050 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 6202 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8416 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 318904 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 211 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 84 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 55478 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 73500 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180251 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 15 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 10050 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 15423 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8416 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 343469 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 211 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 84 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 55478 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 73500 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180251 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 15 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 10050 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 15423 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8416 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 343469 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.227788 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.561703 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.257425 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.288022 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.562665 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.406835 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.720086 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.850667 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.769102 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.127962 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.047619 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.352410 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.157507 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735746 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.146341 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.268856 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.151886 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.670271 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.535120 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.127962 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.047619 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.352410 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.274952 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735746 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.146341 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.268856 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.569669 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.670271 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.551855 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.127962 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.047619 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.352410 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.274952 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735746 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.146341 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.268856 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.569669 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.670271 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.551855 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2729.530961 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1856.959315 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2560.545741 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6846.378505 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2316.470588 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 4136.086344 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151707.303828 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133533.273840 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 144161.805960 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137444.444444 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 130250 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132969.669122 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139170.906114 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157024.572490 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139750 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134230.940044 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141239.384289 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176780.498493 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 153511.040433 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137444.444444 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 130250 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 132969.669122 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 146025.013608 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157024.572490 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139750 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 134230.940044 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 134359.492374 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 176780.498493 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 152579.150450 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137444.444444 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 130250 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 132969.669122 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 146025.013608 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157024.572490 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139750 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 134230.940044 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 134359.492374 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 176780.498493 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 152579.150450 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 320 # number of cycles access was blocked
3307c3303
< system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked
3309c3305
< system.l2c.avg_blocked_cycles::no_mshrs 81.333333 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
3313,3367c3309,3360
< system.l2c.writebacks::writebacks 102794 # number of writebacks
< system.l2c.writebacks::total 102794 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 23 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 23 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 23 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 31 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3318 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3318 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 9630 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 2300 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 11930 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 789 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1228 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 2017 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11769 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 9002 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 20771 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 32 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19549 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9277 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134592 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2845 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1343 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 7007 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 174656 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 32 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 19549 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 21046 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134592 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 2845 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 10345 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 7007 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 195427 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 32 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 19549 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 21046 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134592 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 2845 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 10345 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 7007 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 195427 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 97832 # number of writebacks
> system.l2c.writebacks::total 97832 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 7 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 2 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 2993 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 2993 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 9722 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 2335 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 12057 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 856 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1275 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 2131 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11049 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 7844 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 18893 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 4 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19544 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9160 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132619 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2700 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5641 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 170643 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 19544 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 20209 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132619 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 6 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 2700 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8786 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5641 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 189536 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 19544 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 20209 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132619 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 6 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 2700 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8786 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5641 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 189536 # number of overall MSHR misses
3369c3362
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31809 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31813 # number of ReadReq MSHR uncacheable
3371,3375c3364,3368
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3066 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 37982 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 30904 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3390 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 38310 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28497 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2735 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 31232 # number of WriteReq MSHR uncacheable
3377c3370
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60302 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60310 # number of overall MSHR uncacheable misses
3379,3422c3372,3412
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5477 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 68886 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 726468500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172914500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 899383000 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 61180001 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 94048000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 155228001 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1660892000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1113003000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 2773895000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 4521000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 358000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2400281501 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1201493000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19897000310 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 859500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 357493000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 173092500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1201809384 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 25237031195 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4521000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 358000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 2400281501 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2862385000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19897000310 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 859500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 357493000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 1286095500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1201809384 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 28010926195 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4521000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 358000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 2400281501 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2862385000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19897000310 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 859500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 357493000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 1286095500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1201809384 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 28010926195 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6125 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 69542 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 706982000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 168762500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 875744500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 63871998 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 94072500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 157944498 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1565721015 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 968993503 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 2534714518 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3441000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 481000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2403579538 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1183199515 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19498197011 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 778500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 335513027 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 123623012 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 940802327 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 24489614930 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3441000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 481000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 2403579538 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2748920530 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19498197011 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 778500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 335513027 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1092616515 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 940802327 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 27024329448 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3441000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 481000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 2403579538 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2748920530 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19498197011 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 778500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 335513027 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1092616515 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 940802327 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 27024329448 # number of overall MSHR miss cycles
3424,3430c3414,3420
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5796274000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11490000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 357780500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 6509592500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4693778538 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 242067504 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4935846042 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5796653509 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11076000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 367690504 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6519468013 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4693986539 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 252107506 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4946094045 # number of WriteReq MSHR uncacheable cycles
3432,3435c3422,3425
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10490052538 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11490000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 599848004 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 11445438542 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10490640048 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11076000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 619798010 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 11465562058 # number of overall MSHR uncacheable cycles
3438,3521c3428,3505
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.228134 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.491138 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.254398 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.266464 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.565638 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393024 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.745204 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.889438 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.801536 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148837 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.038961 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.358342 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.159813 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742396 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.189189 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.062500 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.258754 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173179 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.694725 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.540600 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148837 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.038961 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.358342 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.285014 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742396 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189189 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.062500 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.258754 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.578709 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.694725 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.559976 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148837 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.038961 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.358342 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.285014 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742396 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189189 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.062500 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.258754 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.578709 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.694725 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.559976 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75438.058152 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75180.217391 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75388.348701 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77541.192649 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76586.319218 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76959.841844 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141124.309627 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123639.524550 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 133546.531221 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122782.827817 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129513.096906 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128884.959047 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144495.643980 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122782.827817 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136006.129431 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.492992 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 143331.915216 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122782.827817 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136006.129431 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.492992 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 143331.915216 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.227788 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.561703 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.257425 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.288022 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.562665 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.406835 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.720086 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850667 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.769102 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.127962 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.047619 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.352284 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.157507 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735746 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.146341 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.268657 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151886 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.670271 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.535092 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127962 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.047619 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.352284 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.274952 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735746 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.146341 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.268657 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.569669 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.670271 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.551829 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127962 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.047619 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.352284 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.274952 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735746 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.146341 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.268657 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.569669 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.670271 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.551829 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72719.810739 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72275.160600 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72633.698267 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74616.820093 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73782.352941 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74117.549507 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141707.033668 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123533.082993 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 134161.568729 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127444.444444 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 120250 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122982.989050 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129170.252729 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147024.159517 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129750 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124264.084074 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131234.619958 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166779.352420 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143513.738800 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127444.444444 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 120250 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122982.989050 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136024.569746 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147024.159517 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129750 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124264.084074 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124358.811177 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166779.352420 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 142581.511945 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127444.444444 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 120250 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122982.989050 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136024.569746 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147024.159517 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129750 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124264.084074 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124358.811177 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166779.352420 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 142581.511945 # average overall mshr miss latency
3523,3529c3507,3513
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182221.195259 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116692.922374 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171386.248749 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164734.444881 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100401.287433 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159715.442726 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182210.213089 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107533.980583 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108463.275516 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170176.664396 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164718.620872 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 92178.247166 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158366.228388 # average WriteReq mshr uncacheable latency
3531,3534c3515,3518
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173958.617260 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109521.271499 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 166150.430305 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173945.283502 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107533.980583 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101191.511837 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 164872.480774 # average overall mshr uncacheable latency
3536,3548c3520,3532
< system.membus.trans_dist::ReadReq 37982 # Transaction distribution
< system.membus.trans_dist::ReadResp 212889 # Transaction distribution
< system.membus.trans_dist::WriteReq 30904 # Transaction distribution
< system.membus.trans_dist::WriteResp 30904 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 139000 # Transaction distribution
< system.membus.trans_dist::CleanEvict 16061 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 72768 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 40424 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 14027 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
< system.membus.trans_dist::ReadExReq 40474 # Transaction distribution
< system.membus.trans_dist::ReadExResp 20691 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 174908 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 38310 # Transaction distribution
> system.membus.trans_dist::ReadResp 209204 # Transaction distribution
> system.membus.trans_dist::WriteReq 31232 # Transaction distribution
> system.membus.trans_dist::WriteResp 31232 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 134038 # Transaction distribution
> system.membus.trans_dist::CleanEvict 15311 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 73680 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 40459 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
> system.membus.trans_dist::ReadExReq 38317 # Transaction distribution
> system.membus.trans_dist::ReadExResp 18829 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 170895 # Transaction distribution
3550d3533
< system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
3553,3558c3536,3541
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 672318 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 793976 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 902910 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14998 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641245 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 764215 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 837164 # Packet count per connected master and slave (bytes)
3561,3563c3544,3546
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19129032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 19319536 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29996 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18435464 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18628592 # Cumulative packet size per connected master and slave (bytes)
3566,3568c3549,3551
< system.membus.pkt_size::total 21637680 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 119522 # Total snoops (count)
< system.membus.snoop_fanout::samples 588990 # Request fanout histogram
---
> system.membus.pkt_size::total 20946736 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 119950 # Total snoops (count)
> system.membus.snoop_fanout::samples 578486 # Request fanout histogram
3573c3556
< system.membus.snoop_fanout::1 588990 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 578486 100.00% 100.00% # Request fanout histogram
3578,3579c3561,3562
< system.membus.snoop_fanout::total 588990 # Request fanout histogram
< system.membus.reqLayer0.occupancy 81993500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 578486 # Request fanout histogram
> system.membus.reqLayer0.occupancy 82005000 # Layer occupancy (ticks)
3583c3566
< system.membus.reqLayer2.occupancy 11365991 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 12415490 # Layer occupancy (ticks)
3585c3568
< system.membus.reqLayer5.occupancy 1011151356 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 979073321 # Layer occupancy (ticks)
3587c3570
< system.membus.respLayer2.occupancy 1153249220 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1095686984 # Layer occupancy (ticks)
3589c3572
< system.membus.respLayer3.occupancy 64060493 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1343381 # Layer occupancy (ticks)
3632,3651c3615,3634
< system.toL2Bus.snoop_filter.tot_requests 995943 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 537996 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 143832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 21510 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 20627 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 883 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 37985 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 476927 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 403719 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 92623 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 107653 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 43539 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 151192 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 50791 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 50791 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 438958 # Transaction distribution
---
> system.toL2Bus.snoop_filter.tot_requests 986513 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 532898 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 144750 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 20257 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 19380 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 877 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 38313 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 474331 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 31232 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 31232 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 393751 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 116065 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 108396 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 43566 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 151962 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 49800 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 49800 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 436034 # Transaction distribution
3653,3662c3636,3645
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1238290 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 270024 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1508314 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35030546 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4521886 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 39552432 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 444179 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 913848 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.335282 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.474132 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1264986 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 256361 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1521347 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35072434 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3807934 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 38880368 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 439648 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 904500 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.339928 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.475727 # Request fanout histogram
3664,3666c3647,3649
< system.toL2Bus.snoop_fanout::0 608334 66.57% 66.57% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 304631 33.33% 99.90% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 883 0.10% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 597912 66.10% 66.10% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 305711 33.80% 99.90% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 877 0.10% 100.00% # Request fanout histogram
3670,3671c3653,3654
< system.toL2Bus.snoop_fanout::total 913848 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 880459353 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 904500 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 870687772 # Layer occupancy (ticks)
3673c3656
< system.toL2Bus.snoopLayer0.occupancy 356618 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
3675c3658
< system.toL2Bus.respLayer0.occupancy 654259891 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 657373534 # Layer occupancy (ticks)
3677c3660
< system.toL2Bus.respLayer1.occupancy 211427270 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 203531555 # Layer occupancy (ticks)
3680c3663
< system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed
3682c3665
< system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 2705 # number of quiesce instructions executed