3,5c3,5
< sim_seconds 2.625395 # Number of seconds simulated
< sim_ticks 2625394935000 # Number of ticks simulated
< final_tick 2625394935000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.825406 # Number of seconds simulated
> sim_ticks 2825405893500 # Number of ticks simulated
> final_tick 2825405893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 71798 # Simulator instruction rate (inst/s)
< host_op_rate 87106 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1566670818 # Simulator tick rate (ticks/s)
< host_mem_usage 647044 # Number of bytes of host memory used
< host_seconds 1675.78 # Real time elapsed on the host
< sim_insts 120317196 # Number of instructions simulated
< sim_ops 145970023 # Number of ops (including micro ops) simulated
---
> host_inst_rate 89977 # Simulator instruction rate (inst/s)
> host_op_rate 109159 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2115602490 # Simulator tick rate (ticks/s)
> host_mem_usage 657340 # Number of bytes of host memory used
> host_seconds 1335.51 # Real time elapsed on the host
> sim_insts 120165205 # Number of instructions simulated
> sim_ops 145782922 # Number of ops (including micro ops) simulated
17,25c17,25
< system.physmem.bytes_read::cpu0.itb.walker 448 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 1152320 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1224232 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8325184 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 318816 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 736276 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 690624 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 1275648 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1290856 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427776 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 182944 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 606480 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 427776 # Number of bytes read from this memory
27,31c27,31
< system.physmem.bytes_read::total 12451228 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1152320 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 318816 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1471136 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9003520 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12214872 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1275648 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 182944 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1458592 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8756928 # Number of bytes written to this memory
34c34
< system.physmem.bytes_written::total 9021084 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8774492 # Number of bytes written to this memory
36,44c36,44
< system.physmem.num_reads::cpu0.itb.walker 7 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 20252 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 19649 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 130081 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 5049 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 11525 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 10791 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 22179 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 20690 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 131684 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 2926 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 9496 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 6684 # Number of read requests responded to by this memory
46,47c46,47
< system.physmem.num_reads::total 197406 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 140680 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 193712 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 136827 # Number of write requests responded to by this memory
50,92c50,92
< system.physmem.num_writes::total 145071 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 171 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 438913 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 466304 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 3171022 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 121435 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 280444 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 263055 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4742611 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 438913 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 121435 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 560348 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3429396 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3436086 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3429396 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 171 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 438913 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 472979 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 3171022 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 121435 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 280459 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 263055 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 8178698 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 197407 # Number of read requests accepted
< system.physmem.writeReqs 145071 # Number of write requests accepted
< system.physmem.readBursts 197407 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 145071 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12624448 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9033728 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12451292 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 9021084 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_writes::total 141218 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 451492 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 456875 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2982855 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 204 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 64750 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 214652 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 151403 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4323227 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 451492 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 64750 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 516242 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3099352 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 6202 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3105569 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3099352 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 451492 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 463077 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2982855 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 204 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 64750 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 214667 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 151403 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7428796 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 193713 # Number of read requests accepted
> system.physmem.writeReqs 141218 # Number of write requests accepted
> system.physmem.readBursts 193713 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 141218 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12387136 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8786752 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12214936 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8774492 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue
94,119c94,119
< system.physmem.neitherReadNorWriteReqs 50333 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12702 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12398 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12869 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12803 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14881 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12147 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12755 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12276 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11968 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12044 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11861 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11195 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11579 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12354 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11791 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11634 # Per bank write bursts
< system.physmem.perBankWrBursts::0 9169 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9145 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9512 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9193 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8772 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8759 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9221 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8821 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8638 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 49946 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 12421 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11965 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12291 # Per bank write bursts
> system.physmem.perBankRdBursts::3 13088 # Per bank write bursts
> system.physmem.perBankRdBursts::4 14558 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12211 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11940 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12041 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12092 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12171 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11769 # Per bank write bursts
> system.physmem.perBankRdBursts::11 10768 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11340 # Per bank write bursts
> system.physmem.perBankRdBursts::13 12292 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11321 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11281 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9078 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8838 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9120 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9597 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8379 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8806 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8536 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8489 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8658 # Per bank write bursts
121,126c121,126
< system.physmem.perBankWrBursts::10 8601 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8338 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8547 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8875 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8631 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8251 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 8573 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8021 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8348 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8584 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7909 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7678 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
< system.physmem.totGap 2625394672500 # Total gap between requests
---
> system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
> system.physmem.totGap 2825405630500 # Total gap between requests
132c132
< system.physmem.readPktSize::2 551 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 550 # Read request sizes (log2)
136c136
< system.physmem.readPktSize::6 193742 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 190049 # Read request sizes (log2)
143,163c143,163
< system.physmem.writePktSize::6 140680 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 60453 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 70781 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 16881 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 12152 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8838 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7520 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 6581 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 5428 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 4952 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1308 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 972 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 775 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 324 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 266 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 136827 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 58643 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 71509 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 15316 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12788 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 8414 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7274 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 6278 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 5174 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 4590 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1392 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 933 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 285 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 252 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
191,223c191,223
< system.physmem.wrQLenPdf::15 2665 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4593 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5057 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5456 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6711 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8346 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8856 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 10182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9756 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9902 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 11207 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 9191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8461 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 456 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 274 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2640 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4486 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5017 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5977 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8098 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8572 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9894 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9480 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9411 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8905 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 10669 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 8786 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 8210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7795 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 707 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 426 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 426 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 219 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
225,257c225,257
< system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 90794 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 238.541225 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 134.856216 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 301.373578 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 48956 53.92% 53.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17750 19.55% 73.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6013 6.62% 80.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3452 3.80% 83.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2808 3.09% 86.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1564 1.72% 88.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 893 0.98% 89.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 995 1.10% 90.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8363 9.21% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 90794 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 7077 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 27.872686 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 551.008017 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 7075 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 124 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 87370 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 242.346618 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 136.604135 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 304.406981 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 46631 53.37% 53.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17108 19.58% 72.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5841 6.69% 79.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3374 3.86% 83.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2711 3.10% 86.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1534 1.76% 88.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 893 1.02% 89.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1014 1.16% 90.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8264 9.46% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 87370 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6825 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.358242 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 561.081040 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6823 99.97% 99.97% # Reads before turning the bus around for writes
260,298c260,299
< system.physmem.rdPerTurnAround::total 7077 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 7077 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.945175 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.553311 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.579174 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5904 83.43% 83.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 368 5.20% 88.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 217 3.07% 91.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 59 0.83% 92.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 82 1.16% 93.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 159 2.25% 95.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 25 0.35% 96.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 12 0.17% 96.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 13 0.18% 96.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 11 0.16% 96.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 10 0.14% 96.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 6 0.08% 97.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 165 2.33% 99.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 6 0.08% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 3 0.04% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 6 0.08% 99.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 1 0.01% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 10 0.14% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 5 0.07% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 7077 # Writes before turning the bus around for reads
< system.physmem.totQLat 6986626052 # Total ticks spent queuing
< system.physmem.totMemAccLat 10685194802 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 986285000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 35418.90 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6825 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6825 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.116190 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.646323 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 12.038338 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5646 82.73% 82.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 406 5.95% 88.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 199 2.92% 91.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 55 0.81% 92.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 78 1.14% 93.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 151 2.21% 95.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 25 0.37% 96.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 11 0.16% 96.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 15 0.22% 96.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 9 0.13% 96.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 8 0.12% 96.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 6 0.09% 96.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 163 2.39% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 7 0.10% 99.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 2 0.03% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 8 0.12% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.03% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 2 0.03% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.01% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 2 0.03% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 16 0.23% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6825 # Writes before turning the bus around for reads
> system.physmem.totQLat 6500326386 # Total ticks spent queuing
> system.physmem.totMemAccLat 10129370136 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 967745000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 33584.91 # Average queueing delay per DRAM burst
300,304c301,305
< system.physmem.avgMemAccLat 54168.90 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.81 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.44 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.74 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 52334.91 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s
307,327c308,328
< system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.34 # Average write queue length when enqueuing
< system.physmem.readRowHits 164764 # Number of row buffer hits during reads
< system.physmem.writeRowHits 82850 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 58.69 # Row buffer hit rate for writes
< system.physmem.avgGap 7665878.31 # Average gap between requests
< system.physmem.pageHitRate 73.17 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 357081480 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 194836125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 802081800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 470396160 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 75099546585 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1509358032750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1757759761380 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.522942 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2510844795677 # Time in different power states
< system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states
---
> system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 27.47 # Average write queue length when enqueuing
> system.physmem.readRowHits 161846 # Number of row buffer hits during reads
> system.physmem.writeRowHits 81625 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 59.44 # Row buffer hit rate for writes
> system.physmem.avgGap 8435784.18 # Average gap between requests
> system.physmem.pageHitRate 73.58 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 343821240 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 187600875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 784017000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 459062640 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 79593993450 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1625423449500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1891333620465 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.402761 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2703936458200 # Time in different power states
> system.physmem_0.memoryStateTime::REF 94346460000 # Time in different power states
329c330
< system.physmem_0.memoryStateTime::ACT 26879018073 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 27121665550 # Time in different power states
331,341c332,342
< system.physmem_1.actEnergy 329321160 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 179689125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 736515000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 444268800 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 74435410800 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1509940608000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1757543599365 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.440607 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2511823665901 # Time in different power states
< system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states
---
> system.physmem_1.actEnergy 316695960 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 172800375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 725657400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 430596000 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 78590048175 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1626304103250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1891081576920 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.313555 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2705408031049 # Time in different power states
> system.physmem_1.memoryStateTime::REF 94346460000 # Time in different power states
343c344
< system.physmem_1.memoryStateTime::ACT 25903669599 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 25651382451 # Time in different power states
354,362c355,363
< system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s)
---
> system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
369,373c370,374
< system.cpu0.branchPred.lookups 51763361 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 23412597 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 921572 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 31250401 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 23297364 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 24021626 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 15717395 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 977579 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 14633586 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 10784998 # Number of BTB hits
375,377c376,378
< system.cpu0.branchPred.BTBHitPct 74.550608 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 15315613 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 29376 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 73.700308 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 3879887 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 32532 # Number of incorrect RAS predictions.
408,454c409,453
< system.cpu0.dtb.walker.walks 63347 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 63347 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24259 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18763 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 20325 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 43022 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 472.792990 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 2838.942862 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-8191 41882 97.35% 97.35% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::8192-16383 877 2.04% 99.39% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::16384-24575 115 0.27% 99.66% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::24576-32767 113 0.26% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::40960-49151 23 0.05% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 43022 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 16160 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 9833.168317 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 8304.443400 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 6846.428458 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-16383 15169 93.87% 93.87% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::16384-32767 911 5.64% 99.50% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-49151 54 0.33% 99.84% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.02% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-114687 20 0.12% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 16160 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 95658285656 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.461466 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.505385 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 95607533656 99.95% 99.95% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 37952000 0.04% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 6012000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 3722000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 1321500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 760000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 604000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 360500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::16-17 20000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 95658285656 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.00% 77.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1546 23.00% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6722 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 63347 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walks 65547 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 65547 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26411 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18806 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 20330 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 45217 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 420.151713 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 2682.973536 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-8191 44150 97.64% 97.64% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::8192-16383 821 1.82% 99.46% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::16384-24575 92 0.20% 99.66% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::24576-32767 122 0.27% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::32768-40959 7 0.02% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::40960-49151 22 0.05% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 45217 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 15532 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 9209.084471 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 7773.401889 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 5863.053322 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-16383 14685 94.55% 94.55% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::16384-32767 794 5.11% 99.66% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.30% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 15532 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 89510783948 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.549501 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.505567 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 89461994948 99.95% 99.95% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 35577000 0.04% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 6153500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 3637000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 1264000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 750500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 798000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 605000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::16-17 4000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 89510783948 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 5141 79.20% 79.20% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1350 20.80% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 6491 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65547 # Table walker requests started/completed, data/inst
456,457c455,456
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 63347 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6722 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65547 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6491 # Table walker requests started/completed, data/inst
459,460c458,459
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6722 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 70069 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6491 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 72038 # Table walker requests started/completed, data/inst
463,466c462,465
< system.cpu0.dtb.read_hits 22737235 # DTB read hits
< system.cpu0.dtb.read_misses 54172 # DTB read misses
< system.cpu0.dtb.write_hits 16921500 # DTB write hits
< system.cpu0.dtb.write_misses 9175 # DTB write misses
---
> system.cpu0.dtb.read_hits 17771522 # DTB read hits
> system.cpu0.dtb.read_misses 55962 # DTB read misses
> system.cpu0.dtb.write_hits 14661221 # DTB write hits
> system.cpu0.dtb.write_misses 9585 # DTB write misses
471,473c470,472
< system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 141 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 1882 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 322 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 2338 # Number of TLB faults due to prefetch
475,477c474,476
< system.cpu0.dtb.perms_faults 854 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 22791407 # DTB read accesses
< system.cpu0.dtb.write_accesses 16930675 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 17827484 # DTB read accesses
> system.cpu0.dtb.write_accesses 14670806 # DTB write accesses
479,481c478,480
< system.cpu0.dtb.hits 39658735 # DTB hits
< system.cpu0.dtb.misses 63347 # DTB misses
< system.cpu0.dtb.accesses 39722082 # DTB accesses
---
> system.cpu0.dtb.hits 32432743 # DTB hits
> system.cpu0.dtb.misses 65547 # DTB misses
> system.cpu0.dtb.accesses 32498290 # DTB accesses
511,557c510,551
< system.cpu0.itb.walker.walks 10275 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 10275 # Table walker walks initiated with short descriptors
< system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6085 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 114 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 10161 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 480.267690 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 2390.213266 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-4095 9738 95.84% 95.84% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::4096-8191 133 1.31% 97.15% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::8192-12287 215 2.12% 99.26% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::12288-16383 37 0.36% 99.63% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.71% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.86% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 10161 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 11438.934123 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 10140.740913 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 6204.580963 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-8191 871 32.24% 32.24% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::8192-16383 1681 62.21% 94.45% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-24575 53 1.96% 96.41% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.15% 99.56% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 22643799124 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.979659 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.141451 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 461404000 2.04% 2.04% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 22181693124 97.96% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 593000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 109000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 22643799124 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 2268 87.64% 87.64% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::1M 320 12.36% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walks 10460 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 10460 # Table walker walks initiated with short descriptors
> system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4240 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6125 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 95 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 10365 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 435.745297 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 2168.024140 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-4095 9957 96.06% 96.06% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.42% 97.48% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::8192-12287 193 1.86% 99.34% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::12288-16383 32 0.31% 99.65% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.76% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::20480-24575 17 0.16% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 10365 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 2678 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 10848.207618 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 9582.239797 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 5620.252827 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-8191 1037 38.72% 38.72% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::8192-16383 1516 56.61% 95.33% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-24575 52 1.94% 97.27% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::24576-32767 65 2.43% 99.70% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 2678 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 20779406712 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.976236 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.152563 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 494503000 2.38% 2.38% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 20284294712 97.62% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 517000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 92000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 20779406712 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 2260 87.50% 87.50% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::1M 323 12.50% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 2583 # Table walker page sizes translated
559,560c553,554
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10275 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10275 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10460 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10460 # Table walker requests started/completed, data/inst
562,566c556,560
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 12863 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 70928349 # ITB inst hits
< system.cpu0.itb.inst_misses 10275 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2583 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2583 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 13043 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 37759439 # ITB inst hits
> system.cpu0.itb.inst_misses 10460 # ITB inst misses
575c569
< system.cpu0.itb.flush_entries 2365 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2357 # Number of entries that have been flushed from TLB
579c573
< system.cpu0.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 1912 # Number of TLB faults due to permissions restrictions
582,586c576,580
< system.cpu0.itb.inst_accesses 70938624 # ITB inst accesses
< system.cpu0.itb.hits 70928349 # DTB hits
< system.cpu0.itb.misses 10275 # DTB misses
< system.cpu0.itb.accesses 70938624 # DTB accesses
< system.cpu0.numCycles 192976868 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 37769899 # ITB inst accesses
> system.cpu0.itb.hits 37759439 # DTB hits
> system.cpu0.itb.misses 10460 # DTB misses
> system.cpu0.itb.accesses 37769899 # DTB accesses
> system.cpu0.numCycles 130135672 # number of cpu cycles simulated
589,605c583,599
< system.cpu0.fetch.icacheStallCycles 19363908 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 190332929 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 51763361 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 38612977 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 166709106 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 5608958 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 145099 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 54692 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 348676 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 420281 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 85262 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 70928958 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 257958 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 4691 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 189931503 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 1.225932 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.310916 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 18741348 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 112674064 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 24021626 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 14664885 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 105564363 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 2824766 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 148935 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 59402 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 359448 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 427042 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 91226 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 37760092 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 271445 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 4846 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 126804147 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 1.071967 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.260919 # Number of instructions fetched each cycle (Total)
607,610c601,604
< system.cpu0.fetch.rateDist::0 88125904 46.40% 46.40% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 29232702 15.39% 61.79% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 14108338 7.43% 69.22% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 58464559 30.78% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 64261882 50.68% 50.68% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 21462384 16.93% 67.60% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 8772204 6.92% 74.52% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 32307677 25.48% 100.00% # Number of instructions fetched each cycle (Total)
614,660c608,654
< system.cpu0.fetch.rateDist::total 189931503 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.268236 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.986299 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 24608865 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 101406874 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 56677604 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 4757932 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 2480228 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 2944179 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 328448 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 148845488 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 3759445 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 2480228 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 33020653 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 11928133 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 79389996 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 52895431 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 10217062 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 132354164 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 1007004 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 1382043 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 149840 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 52195 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 6188026 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 135879963 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 611395498 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 146969281 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 9373 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 124973310 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 10906650 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 2656416 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 2518561 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 22027855 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 23660512 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 18424443 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1639164 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 2432445 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 129487187 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1661777 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 127665829 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 454854 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 10484678 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 21309646 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 116701 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 189931503 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.672168 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 0.963951 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 126804147 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.184589 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.865820 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 19721438 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 59617090 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 41434685 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 4962697 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 1068237 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 3055964 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 348356 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 110795648 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 3978318 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 1068237 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 25470078 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 12211623 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 36823403 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 40512045 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 10718761 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 105720614 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 1057290 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 1452767 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 161700 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 58122 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 6514709 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 109806374 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 482725120 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 121004760 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 9383 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 98259136 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 11547235 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1229554 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 1088238 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 12335468 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 18754417 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 16214275 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1701393 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 2256069 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 102765106 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1695392 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 100794287 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 484302 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 9532947 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 22407435 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 122350 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 126804147 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.794882 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.031887 # Number of insts issued each cycle
662,667c656,661
< system.cpu0.iq.issued_per_cycle::0 116041258 61.10% 61.10% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 32572628 17.15% 78.25% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 29941917 15.76% 94.01% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 10293469 5.42% 99.43% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1082195 0.57% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 70515231 55.61% 55.61% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 23338464 18.41% 74.01% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 22507800 17.75% 91.76% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 9330414 7.36% 99.12% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1112209 0.88% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle
674c668
< system.cpu0.iq.issued_per_cycle::total 189931503 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 126804147 # Number of insts issued each cycle
676,706c670,700
< system.cpu0.iq.fu_full::IntAlu 10298963 43.90% 43.90% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 129 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.91% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 5415712 23.09% 66.99% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 7742693 33.01% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 9354884 40.60% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 74 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 5601126 24.31% 64.90% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 8088042 35.10% 100.00% # attempts to use FU when none available
709,740c703,734
< system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 86175456 67.50% 67.50% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 106512 0.08% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 7179 0.01% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 23410232 18.34% 85.93% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 17964178 14.07% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 66470143 65.95% 65.95% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 93430 0.09% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 8105 0.01% 66.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 18478690 18.33% 84.38% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 15741645 15.62% 100.00% # Type of FU issued
743,755c737,749
< system.cpu0.iq.FU_type_0::total 127665829 # Type of FU issued
< system.cpu0.iq.rate 0.661560 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 23457497 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.183741 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 469142790 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 141641253 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 124187141 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 32722 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 11272 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 151099696 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 21358 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 349091 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 100794287 # Type of FU issued
> system.cpu0.iq.rate 0.774532 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 23044126 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.228625 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 351888789 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 114001116 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 98678663 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 32360 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 9725 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 123815106 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 21034 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 363531 # Number of loads that had data forwarded from stores
757,760c751,754
< system.cpu0.iew.lsq.thread0.squashedLoads 1883461 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2555 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 18950 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 972383 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1999131 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2544 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 19035 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 1014690 # Number of stores squashed
763,764c757,758
< system.cpu0.iew.lsq.thread0.rescheduledLoads 113459 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 340118 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 107294 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 362990 # Number of times an access to memory failed due to the cache being blocked
766,769c760,763
< system.cpu0.iew.iewSquashCycles 2480228 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 1536268 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 176000 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 131320075 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 1068237 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 1634305 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 175316 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 104635112 # Number of instructions dispatched to IQ
771,782c765,776
< system.cpu0.iew.iewDispLoadInsts 23660512 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 18424443 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 851631 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 24928 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 129599 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 18950 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 275039 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 375413 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 650452 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 126634007 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 22982824 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 968597 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 18754417 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 16214275 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 876681 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 26796 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 125236 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 19035 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 291770 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 399939 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 691709 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 99697701 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 18022679 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 1031168 # Number of squashed instructions skipped in execute
784,792c778,786
< system.cpu0.iew.exec_nop 171111 # number of nop insts executed
< system.cpu0.iew.exec_refs 40767921 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 24572908 # Number of branches executed
< system.cpu0.iew.exec_stores 17785097 # Number of stores executed
< system.cpu0.iew.exec_rate 0.656213 # Inst execution rate
< system.cpu0.iew.wb_sent 126104266 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 124196865 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 63208416 # num instructions producing a value
< system.cpu0.iew.wb_consumers 102222094 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 174614 # number of nop insts executed
> system.cpu0.iew.exec_refs 33573838 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 16859604 # Number of branches executed
> system.cpu0.iew.exec_stores 15551159 # Number of stores executed
> system.cpu0.iew.exec_rate 0.766106 # Inst execution rate
> system.cpu0.iew.wb_sent 99140543 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 98688388 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 51348142 # num instructions producing a value
> system.cpu0.iew.wb_consumers 84871692 # num instructions consuming a value
794,795c788,789
< system.cpu0.iew.wb_rate 0.643584 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.618344 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.758350 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.605009 # average fanout of values written-back
797,802c791,796
< system.cpu0.commit.commitSquashedInsts 9488534 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 1545076 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 597321 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 186809549 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.646573 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.344397 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 8492759 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 1573042 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 633433 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 125053157 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.760074 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.473514 # Number of insts commited each cycle
804,812c798,806
< system.cpu0.commit.committed_per_cycle::0 128903317 69.00% 69.00% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 31993486 17.13% 86.13% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 12242174 6.55% 92.68% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 3077822 1.65% 94.33% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 4650551 2.49% 96.82% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 2601023 1.39% 98.21% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 1367878 0.73% 98.94% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 526295 0.28% 99.23% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1447003 0.77% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 80626724 64.47% 64.47% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 24772258 19.81% 84.28% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 8266840 6.61% 90.89% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 3238221 2.59% 93.48% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 3432782 2.75% 96.23% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 1539199 1.23% 97.46% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 1134355 0.91% 98.37% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 546479 0.44% 98.80% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1496299 1.20% 100.00% # Number of insts commited each cycle
816,818c810,812
< system.cpu0.commit.committed_per_cycle::total 186809549 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 99693903 # Number of instructions committed
< system.cpu0.commit.committedOps 120785976 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 125053157 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 78998098 # Number of instructions committed
> system.cpu0.commit.committedOps 95049599 # Number of ops (including micro ops) committed
820,823c814,817
< system.cpu0.commit.refs 39229111 # Number of memory references committed
< system.cpu0.commit.loads 21777051 # Number of loads committed
< system.cpu0.commit.membars 629182 # Number of memory barriers committed
< system.cpu0.commit.branches 23976855 # Number of branches committed
---
> system.cpu0.commit.refs 31954871 # Number of memory references committed
> system.cpu0.commit.loads 16755286 # Number of loads committed
> system.cpu0.commit.membars 647733 # Number of memory barriers committed
> system.cpu0.commit.branches 16226575 # Number of branches committed
825,826c819,820
< system.cpu0.commit.int_insts 105625598 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 4749745 # Number of function calls committed.
---
> system.cpu0.commit.int_insts 81983360 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 1932291 # Number of function calls committed.
828,858c822,852
< system.cpu0.commit.op_class_0::IntAlu 81445291 67.43% 67.43% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 104395 0.09% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 7179 0.01% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 21777051 18.03% 85.55% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 17452060 14.45% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 62995577 66.28% 66.28% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 91046 0.10% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 8105 0.01% 66.38% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 16755286 17.63% 84.01% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 15199585 15.99% 100.00% # Class of committed instruction
861,890c855,884
< system.cpu0.commit.op_class_0::total 120785976 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1447003 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 292572702 # The number of ROB reads
< system.cpu0.rob.rob_writes 263669539 # The number of ROB writes
< system.cpu0.timesIdled 123127 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 3045365 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 5057813082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 99572209 # Number of Instructions Simulated
< system.cpu0.committedOps 120664282 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.938060 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.938060 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.515980 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.515980 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 137228019 # number of integer regfile reads
< system.cpu0.int_regfile_writes 78727155 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 8192 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
< system.cpu0.cc_regfile_reads 446969794 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 47254034 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 263157526 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 1194331 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 673421 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 483.801587 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 36230548 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 673933 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 53.759866 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 274448500 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.801587 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944925 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.944925 # Average percentage of cache occupancy
---
> system.cpu0.commit.op_class_0::total 95049599 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1496299 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 222908078 # The number of ROB reads
> system.cpu0.rob.rob_writes 208834787 # The number of ROB writes
> system.cpu0.timesIdled 129596 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 3331525 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 5520676264 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 78876046 # Number of Instructions Simulated
> system.cpu0.committedOps 94927547 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.649876 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.649876 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.606106 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.606106 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 110754452 # number of integer regfile reads
> system.cpu0.int_regfile_writes 59798186 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 8167 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes
> system.cpu0.cc_regfile_reads 351214590 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 41113323 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 177297499 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 1225193 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 713718 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 494.250179 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 28854841 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 714230 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 40.399929 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 274766500 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.250179 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965332 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.965332 # Average percentage of cache occupancy
892c886
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
894c888
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
896,975c890,969
< system.cpu0.dcache.tags.tag_accesses 78023145 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 78023145 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 20647656 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 20647656 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 14394101 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 14394101 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296444 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 296444 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354739 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 354739 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351671 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 351671 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 35041757 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 35041757 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 35338201 # number of overall hits
< system.cpu0.dcache.overall_hits::total 35338201 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 609728 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 609728 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1806132 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1806132 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141710 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 141710 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24359 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 24359 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21165 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 21165 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2415860 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2415860 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2557570 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2557570 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8120126000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 8120126000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26313440366 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 26313440366 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385463000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 385463000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480627500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 480627500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 430000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 430000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 34433566366 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 34433566366 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 34433566366 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 34433566366 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 21257384 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 21257384 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 16200233 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 16200233 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438154 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 438154 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379098 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 379098 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372836 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 372836 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 37457617 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 37457617 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 37895771 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 37895771 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028683 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.028683 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111488 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.111488 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323425 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323425 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064255 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064255 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056768 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056768 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064496 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.064496 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067490 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.067490 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13317.620316 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13317.620316 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14568.946437 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 14568.946437 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15824.253869 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15824.253869 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22708.599102 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22708.599102 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 63563549 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 63563549 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 15604955 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 15604955 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 12027073 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 12027073 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310316 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 310316 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363058 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 363058 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361354 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 361354 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 27632028 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 27632028 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 27942344 # number of overall hits
> system.cpu0.dcache.overall_hits::total 27942344 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 644494 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 644494 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1893203 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1893203 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147485 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 147485 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25333 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 25333 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20104 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 20104 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 2537697 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 2537697 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 2685182 # number of overall misses
> system.cpu0.dcache.overall_misses::total 2685182 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8536879000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 8536879000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27482436369 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 27482436369 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389618000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 389618000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 450883500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 450883500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 36019315369 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 36019315369 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 36019315369 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 36019315369 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 16249449 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 16249449 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 13920276 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 13920276 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457801 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 457801 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388391 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 388391 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381458 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 381458 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 30169725 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 30169725 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 30627526 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 30627526 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039663 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.039663 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136003 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.136003 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.322160 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.322160 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065226 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065226 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052703 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052703 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084114 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.084114 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087672 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.087672 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13245.862646 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13245.862646 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14516.370600 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 14516.370600 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15379.860261 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15379.860261 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22427.551731 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22427.551731 # average StoreCondReq miss latency
978,987c972,981
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14253.129886 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 14253.129886 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13463.391565 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13463.391565 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 747 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 3913122 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 192454 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.893617 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 20.332765 # average number of cycles each access was blocked
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14193.702152 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 14193.702152 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13414.105773 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13414.105773 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 682 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 4150493 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 202595 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 20.486651 # average number of cycles each access was blocked
990,1067c984,1061
< system.cpu0.dcache.writebacks::writebacks 491417 # number of writebacks
< system.cpu0.dcache.writebacks::total 491417 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 243049 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 243049 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494093 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1494093 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18165 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18165 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1737142 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1737142 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1737142 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1737142 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366679 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 366679 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312039 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 312039 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98387 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 98387 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6194 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6194 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21165 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 21165 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 678718 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 678718 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 777105 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 777105 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29394 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55521 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291687500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291687500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5394914387 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5394914387 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1614083000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614083000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96183500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96183500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459474500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459474500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 418000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 418000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9686601887 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9686601887 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300684887 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 11300684887 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5681056500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5681056500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4312326500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4312326500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9993383000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9993383000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017249 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017249 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019261 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019261 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224549 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224549 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016339 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016339 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056768 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056768 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018120 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.018120 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020506 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.020506 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11704.208586 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11704.208586 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17289.231112 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17289.231112 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16405.449907 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16405.449907 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15528.495318 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15528.495318 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21709.166076 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21709.166076 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 517170 # number of writebacks
> system.cpu0.dcache.writebacks::total 517170 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 254611 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 254611 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1567828 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1567828 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18755 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18755 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822439 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1822439 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822439 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1822439 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 389883 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 389883 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325375 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 325375 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102048 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 102048 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6578 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6578 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20104 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 20104 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 715258 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 715258 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 817306 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 817306 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19086 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39472 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4555035000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4555035000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5512912898 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5512912898 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1660765500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1660765500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101006000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101006000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 430792500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 430792500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 441000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 441000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10067947898 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10067947898 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11728713398 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 11728713398 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4315293000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4315293000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3299266500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3299266500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7614559500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7614559500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023994 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023994 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023374 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023374 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222909 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222909 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052703 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052703 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023708 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.023708 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026685 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.026685 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11683.081848 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11683.081848 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16943.259003 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16943.259003 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16274.356185 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16274.356185 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15355.123138 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15355.123138 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21428.198368 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21428.198368 # average StoreCondReq mshr miss latency
1070,1079c1064,1073
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14271.909522 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14271.909522 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14542.030854 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14542.030854 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193272.657685 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193272.657685 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165052.493589 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165052.493589 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179992.849552 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179992.849552 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14075.966851 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14075.966851 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14350.455518 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14350.455518 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 211679.240655 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211679.240655 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172863.171959 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172863.171959 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 192910.404844 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 192910.404844 # average overall mshr uncacheable latency
1081,1089c1075,1083
< system.cpu0.icache.tags.replacements 1208444 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.748718 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 69666115 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1208956 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 57.625021 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6421480000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748718 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999509 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999509 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 1264231 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.765651 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 36438607 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1264743 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 28.811076 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6439669000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.765651 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999542 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999542 # Average percentage of cache occupancy
1091,1093c1085,1087
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
1095,1138c1089,1132
< system.cpu0.icache.tags.tag_accesses 143059850 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 143059850 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 69666115 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 69666115 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 69666115 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 69666115 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 69666115 # number of overall hits
< system.cpu0.icache.overall_hits::total 69666115 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1259322 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1259322 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1259322 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1259322 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1259322 # number of overall misses
< system.cpu0.icache.overall_misses::total 1259322 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12306647041 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 12306647041 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 12306647041 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 12306647041 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 12306647041 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 12306647041 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 70925437 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 70925437 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 70925437 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 70925437 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 70925437 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 70925437 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017756 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.017756 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017756 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.017756 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017756 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.017756 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9772.438694 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 9772.438694 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 9772.438694 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 9772.438694 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 1459740 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 453 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 110714 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.184782 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 45.300000 # average number of cycles each access was blocked
---
> system.cpu0.icache.tags.tag_accesses 76777836 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 76777836 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 36438607 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 36438607 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 36438607 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 36438607 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 36438607 # number of overall hits
> system.cpu0.icache.overall_hits::total 36438607 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1317920 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1317920 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1317920 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1317920 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1317920 # number of overall misses
> system.cpu0.icache.overall_misses::total 1317920 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13045197783 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 13045197783 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 13045197783 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 13045197783 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 13045197783 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 13045197783 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 37756527 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 37756527 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 37756527 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 37756527 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 37756527 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 37756527 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034906 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.034906 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034906 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.034906 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034906 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.034906 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.322951 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.322951 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 9898.322951 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 9898.322951 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 1585730 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 630 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 117915 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.448077 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 57.272727 # average number of cycles each access was blocked
1141,1152c1135,1146
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50344 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 50344 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 50344 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 50344 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 50344 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 50344 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1208978 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1208978 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1208978 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1208978 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1208978 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1208978 # number of overall MSHR misses
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53136 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 53136 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 53136 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 53136 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 53136 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 53136 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264784 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1264784 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264784 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1264784 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264784 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1264784 # number of overall MSHR misses
1157,1162c1151,1156
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11179466333 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 11179466333 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11179466333 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 11179466333 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11179466333 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 11179466333 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11837775153 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 11837775153 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11837775153 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 11837775153 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11837775153 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 11837775153 # number of overall MSHR miss cycles
1167,1178c1161,1172
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017046 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.017046 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.017046 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9247.038683 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033498 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.033498 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.033498 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9359.523170 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency
1184,1186c1178,1180
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1763942 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1769107 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 4567 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1848695 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1851312 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 2366 # number of redundant prefetches already in prefetch queue
1189,1380c1183,1369
< system.cpu0.l2cache.prefetcher.pfSpanPage 220637 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 266650 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16052.098762 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 3449668 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 282876 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 12.194983 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 9287.877050 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.757624 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.215297 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4106.053527 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1602.376504 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.818760 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.566887 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000840 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.250614 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.097801 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063588 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.979742 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15158 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 321 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 276 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4651 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7186 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2852 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925171 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 63497786 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 63497786 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50315 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12479 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 62794 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 491416 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 491416 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28453 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 28453 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1608 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 1608 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210730 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 210730 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1158323 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1158323 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 372689 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 372689 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50315 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12479 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1158323 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 583419 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1804536 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50315 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12479 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1158323 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 583419 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1804536 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 419 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 174 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 593 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27292 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 27292 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19556 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19556 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45826 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 45826 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 50641 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 50641 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98477 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 98477 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 419 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 174 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 50641 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 144303 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 195537 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 419 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 174 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 50641 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 144303 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 195537 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11008500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4405500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 15414000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502449500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 502449500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396768500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396768500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 399000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 399000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2648910998 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2648910998 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2424883999 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2424883999 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2835688998 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2835688998 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11008500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4405500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2424883999 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 5484599996 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 7924897995 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11008500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4405500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2424883999 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 5484599996 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 7924897995 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50734 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12653 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 63387 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 491416 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 491416 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21164 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 21164 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256556 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 256556 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1208964 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1208964 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 471166 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 471166 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50734 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12653 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1208964 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 727722 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 2000073 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50734 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12653 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1208964 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 727722 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 2000073 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013752 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.009355 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.489587 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.489587 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924022 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924022 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178620 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178620 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041888 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041888 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.209007 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.209007 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013752 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041888 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198294 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.097765 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013752 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041888 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198294 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.097765 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25318.965517 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25993.254637 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18410.138502 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18410.138502 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20288.837186 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20288.837186 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 399000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 399000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57803.670362 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57803.670362 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47883.809542 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47883.809542 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28795.444601 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28795.444601 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 40528.892205 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 40528.892205 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 233112 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 279786 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16110.932478 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 3625969 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 296031 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 12.248612 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 2809841331000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 7402.389300 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.896732 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.359713 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5003.167978 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1996.783797 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1695.334959 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.451806 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000726 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000083 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.305369 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.121874 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.103475 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.983333 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1041 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15195 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 403 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 288 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4805 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7004 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2900 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063538 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927429 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 66593364 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 66593364 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 52693 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12386 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 65079 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 517165 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 517165 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28793 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 28793 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1744 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 1744 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223098 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 223098 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1208893 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1208893 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 400319 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 400319 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 52693 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12386 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1208893 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 623417 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1897389 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 52693 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12386 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1208893 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 623417 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1897389 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 398 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 157 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 555 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26381 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 26381 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18360 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 18360 # number of SCUpgradeReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47293 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 47293 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55856 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 55856 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98075 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 98075 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 398 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 157 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 55856 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 145368 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 201779 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 398 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 157 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 55856 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 145368 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 201779 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10822500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3611000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 14433500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 484495000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 484495000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 371083000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 371083000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 421500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 421500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2673446497 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2673446497 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2697437499 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2697437499 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2928360998 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2928360998 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10822500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3611000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2697437499 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 5601807495 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 8313678494 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10822500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3611000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2697437499 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 5601807495 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 8313678494 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 53091 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12543 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 65634 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 517165 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 517165 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55174 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 55174 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20104 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 20104 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270391 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 270391 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1264749 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1264749 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 498394 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 498394 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 53091 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12543 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1264749 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 768785 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 2099168 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 53091 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12543 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1264749 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 768785 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 2099168 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012517 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.008456 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478142 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478142 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.913251 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.913251 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174906 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174906 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.044164 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.044164 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.196782 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.196782 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012517 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.044164 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189088 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.096123 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012517 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.044164 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189088 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.096123 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23000 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26006.306306 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18365.300785 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18365.300785 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20211.492375 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20211.492375 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56529.433468 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56529.433468 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48292.708017 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48292.708017 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29858.383869 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29858.383869 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23000 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48292.708017 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38535.355064 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 41201.901556 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23000 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48292.708017 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38535.355064 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 41201.901556 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 214 # number of cycles access was blocked
1384c1373
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked
1388,1390c1377,1378
< system.cpu0.l2cache.writebacks::writebacks 193260 # number of writebacks
< system.cpu0.l2cache.writebacks::total 193260 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
---
> system.cpu0.l2cache.writebacks::writebacks 197696 # number of writebacks
> system.cpu0.l2cache.writebacks::total 197696 # number of writebacks
1392,1399c1380,1386
< system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6054 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 6054 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 30 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 30 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 713 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 713 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
---
> system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5476 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 5476 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 32 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 32 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 797 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 797 # number of ReadSharedReq MSHR hits
1401,1404c1388,1390
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6767 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 6799 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
---
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 32 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6273 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 6306 # number of demand (read+write) MSHR hits
1406,1438c1392,1422
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6767 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 6799 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 418 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 591 # number of ReadReq MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8374 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::total 8374 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 232540 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27292 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27292 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19556 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19556 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39772 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 39772 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 50611 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 50611 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97764 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97764 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 418 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50611 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137536 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 188738 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 418 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50611 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137536 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 421278 # number of overall MSHR misses
---
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 32 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6273 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 6306 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 398 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 156 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 554 # number of ReadReq MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8991 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::total 8991 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245693 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 245693 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26381 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26381 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18360 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18360 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41817 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41817 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55824 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55824 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97278 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97278 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 398 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 156 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55824 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139095 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 195473 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 398 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 156 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55824 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139095 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245693 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 441166 # number of overall MSHR misses
1440,1443c1424,1427
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32398 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23390 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19086 # number of WriteReq MSHR uncacheable
1445,1474c1429,1458
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 58525 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3355000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11834500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15228773142 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 539452500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 539452500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 299483497 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 299483497 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 327000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 327000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1648200500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1648200500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2120543999 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2120543999 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2210587998 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2210587998 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3355000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2120543999 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3858788498 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 5991166997 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3355000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2120543999 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3858788498 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 21219940139 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42476 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2662500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11097000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15042795977 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15042795977 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 537912499 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 537912499 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 278663498 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 278663498 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 343500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 343500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1730970000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1730970000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2361388499 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2361388499 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2303131998 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2303131998 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2662500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2361388499 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4034101998 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 6406587497 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2662500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2361388499 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4034101998 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15042795977 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 21449383474 # number of overall MSHR miss cycles
1476,1479c1460,1463
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5445807000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5689149000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4113464958 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4113464958 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4152104000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4395446000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3153204958 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3153204958 # number of WriteReq MSHR uncacheable cycles
1481,1485c1465,1469
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9559271958 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9802613958 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009324 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7305308958 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7548650958 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008441 # mshr miss rate for ReadReq accesses
1490,1510c1474,1492
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489587 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489587 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924022 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924022 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155023 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155023 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041863 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207494 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.207494 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094366 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478142 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478142 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.913251 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.913251 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154654 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154654 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044138 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.195183 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.195183 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093119 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for overall accesses
1512,1540c1494,1522
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210631 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20024.534687 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65488.832640 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19765.957057 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19765.957057 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15314.148957 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15314.148957 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 327000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 327000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41441.227497 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41441.227497 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41898.875719 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22611.472505 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22611.472505 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31743.300220 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50370.397075 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210162 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20030.685921 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61225.985181 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.148175 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20390.148175 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15177.750436 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.750436 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41393.930698 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41393.930698 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42300.596500 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23675.774564 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23675.774564 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32774.794969 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48619.756450 # average overall mshr miss latency
1542,1545c1524,1527
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185269.340682 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175601.858139 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157441.151223 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157441.151223 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203674.286275 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 187919.880291 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165210.361417 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165210.361417 # average WriteReq mshr uncacheable latency
1547,1548c1529,1530
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172173.987464 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167494.471730 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185075.723500 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 177715.673745 # average overall mshr uncacheable latency
1550,1565c1532,1547
< system.cpu0.toL2Bus.trans_dist::ReadReq 116134 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1839025 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 26127 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 864426 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 1492254 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 304971 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 91775 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43512 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 114568 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 284553 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 270414 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1208978 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592867 # Transaction distribution
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 118491 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1915950 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 30902 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 19086 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 881917 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 1558941 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 295049 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 88486 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42808 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 113105 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 298585 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 285519 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1264784 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 601994 # Transaction distribution
1567,1580c1549,1562
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3608808 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2486821 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28899 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112519 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 6237047 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77421632 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82196692 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50612 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202936 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 159871872 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 1179844 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 5097277 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 1.224281 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.417108 # Request fanout histogram
---
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3774932 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2575467 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29033 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 117114 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 6496546 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80991872 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86506920 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50172 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 212364 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 167761328 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 1157195 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 5250259 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 1.213502 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.409779 # Request fanout histogram
1583,1584c1565,1566
< system.cpu0.toL2Bus.snoop_fanout::1 3954053 77.57% 77.57% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 1143224 22.43% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::1 4129320 78.65% 78.65% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 1120939 21.35% 100.00% # Request fanout histogram
1588,1589c1570,1571
< system.cpu0.toL2Bus.snoop_fanout::total 5097277 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 2520550941 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 5250259 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 2631653442 # Layer occupancy (ticks)
1591c1573
< system.cpu0.toL2Bus.snoopLayer0.occupancy 112317000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 114940499 # Layer occupancy (ticks)
1593c1575
< system.cpu0.toL2Bus.respLayer0.occupancy 1816757420 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1900515323 # Layer occupancy (ticks)
1595c1577
< system.cpu0.toL2Bus.respLayer1.occupancy 1173564387 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1221760496 # Layer occupancy (ticks)
1597c1579
< system.cpu0.toL2Bus.respLayer2.occupancy 16253983 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 16493992 # Layer occupancy (ticks)
1599c1581
< system.cpu0.toL2Bus.respLayer3.occupancy 61816936 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 64044457 # Layer occupancy (ticks)
1601,1605c1583,1587
< system.cpu1.branchPred.lookups 6152669 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 3868120 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 360109 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 3337115 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 2452438 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 33870827 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 11547618 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 303923 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 18735544 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 14949091 # Number of BTB hits
1607,1609c1589,1591
< system.cpu1.branchPred.BTBHitPct 73.489766 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 1042883 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 10537 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 79.790002 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 12480037 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 7268 # Number of incorrect RAS predictions.
1639,1670c1621,1653
< system.cpu1.dtb.walker.walks 24322 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 24322 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11233 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 7099 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 17223 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 438.425361 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 2740.461547 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-4095 16689 96.90% 96.90% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::4096-8191 124 0.72% 97.62% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::8192-12287 219 1.27% 98.89% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::12288-16383 86 0.50% 99.39% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.51% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::20480-24575 13 0.08% 99.58% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::24576-28671 39 0.23% 99.81% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::28672-32767 13 0.08% 99.88% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.09% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 17223 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 5609 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 10144.232484 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 8674.966878 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 6379.427582 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-8191 2437 43.45% 43.45% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2571 45.84% 89.29% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-24575 453 8.08% 97.36% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::24576-32767 115 2.05% 99.41% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.05% 99.47% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 99.98% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walks 21101 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 21101 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8660 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5796 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 6645 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 14456 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 508.058937 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 2886.331667 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-4095 13910 96.22% 96.22% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::4096-8191 137 0.95% 97.17% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::8192-12287 242 1.67% 98.84% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::12288-16383 68 0.47% 99.32% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.14% 99.45% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::20480-24575 12 0.08% 99.54% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::24576-28671 37 0.26% 99.79% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::28672-32767 11 0.08% 99.87% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::32768-36863 15 0.10% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 14456 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 5194 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 9424.913362 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 8003.762670 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 6175.333367 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-8191 2569 49.46% 49.46% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2132 41.05% 90.51% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-24575 361 6.95% 97.46% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::24576-32767 99 1.91% 99.36% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.06% 99.42% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::40960-49151 27 0.52% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency
1672,1696c1655,1679
< system.cpu1.dtb.walker.walkCompletionTime::total 5609 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 69613371380 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.373428 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.487046 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 43658416792 62.72% 62.72% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 25935559588 37.26% 99.97% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2 12091000 0.02% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::3 3523500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4 1046500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::5 593000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6 908500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::7 323500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8 151000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::9 143500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::10 80500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::11 88500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12 153000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::13 38000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14 28000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::15 226500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 69613371380 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 1968 73.85% 73.85% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 697 26.15% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2665 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24322 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkCompletionTime::total 5194 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 72058045764 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.162272 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.372420 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 60402096044 83.82% 83.82% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::1 11637981720 16.15% 99.98% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2 11426500 0.02% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::3 2950500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4 950000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::5 753000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6 773000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::7 312500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8 161500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::9 148500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::10 75000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12 134500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::13 51500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14 27000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::15 156500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 72058045764 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.91% 75.91% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 606 24.09% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 2516 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21101 # Table walker requests started/completed, data/inst
1698,1699c1681,1682
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24322 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2665 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21101 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2516 # Table walker requests started/completed, data/inst
1701,1702c1684,1685
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2665 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 26987 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2516 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 23617 # Table walker requests started/completed, data/inst
1705,1708c1688,1691
< system.cpu1.dtb.read_hits 5224196 # DTB read hits
< system.cpu1.dtb.read_misses 21002 # DTB read misses
< system.cpu1.dtb.write_hits 4300766 # DTB write hits
< system.cpu1.dtb.write_misses 3320 # DTB write misses
---
> system.cpu1.dtb.read_hits 10151644 # DTB read hits
> system.cpu1.dtb.read_misses 18305 # DTB read misses
> system.cpu1.dtb.write_hits 6523716 # DTB write hits
> system.cpu1.dtb.write_misses 2796 # DTB write misses
1713,1715c1696,1698
< system.cpu1.dtb.flush_entries 2043 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 67 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 616 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 50 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 456 # Number of TLB faults due to prefetch
1717,1719c1700,1702
< system.cpu1.dtb.perms_faults 364 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 5245198 # DTB read accesses
< system.cpu1.dtb.write_accesses 4304086 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 384 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 10169949 # DTB read accesses
> system.cpu1.dtb.write_accesses 6526512 # DTB write accesses
1721,1723c1704,1706
< system.cpu1.dtb.hits 9524962 # DTB hits
< system.cpu1.dtb.misses 24322 # DTB misses
< system.cpu1.dtb.accesses 9549284 # DTB accesses
---
> system.cpu1.dtb.hits 16675360 # DTB hits
> system.cpu1.dtb.misses 21101 # DTB misses
> system.cpu1.dtb.accesses 16696461 # DTB accesses
1753,1795c1736,1780
< system.cpu1.itb.walker.walks 6842 # Table walker walks requested
< system.cpu1.itb.walker.walksShort 6842 # Table walker walks initiated with short descriptors
< system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4094 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2680 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksSquashedBefore 68 # Table walks squashed before starting
< system.cpu1.itb.walker.walkWaitTime::samples 6774 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 241.142604 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 1918.263476 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-4095 6651 98.18% 98.18% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::4096-8191 49 0.72% 98.91% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.52% 99.42% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::12288-16383 15 0.22% 99.65% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.72% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::20480-24575 10 0.15% 99.87% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.07% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 6774 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 1233 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 11141.524736 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 9875.363796 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 6280.061079 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-8191 357 28.95% 28.95% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-16383 797 64.64% 93.59% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-24575 18 1.46% 95.05% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-32767 48 3.89% 98.95% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.41% 99.35% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.57% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 1233 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 18042065828 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.988332 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.107619 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 210878764 1.17% 1.17% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 17830879064 98.83% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 267500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::3 19000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::4 21500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 18042065828 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 6899 # Table walker walks requested
> system.cpu1.itb.walker.walksShort 6899 # Table walker walks initiated with short descriptors
> system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4113 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2729 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksSquashedBefore 57 # Table walks squashed before starting
> system.cpu1.itb.walker.walkWaitTime::samples 6842 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 198.333821 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 1594.183488 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-4095 6730 98.36% 98.36% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.86% 99.23% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::8192-12287 21 0.31% 99.53% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::12288-16383 14 0.20% 99.74% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 6842 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 1221 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 10738.329238 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 9530.760976 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5854.425690 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-4095 35 2.87% 2.87% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 374 30.63% 33.50% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 40.70% 74.20% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 243 19.90% 94.10% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-20479 3 0.25% 94.35% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::20480-24575 9 0.74% 95.09% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 37 3.03% 98.12% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.31% 99.43% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.16% 99.59% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.25% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 1221 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 11897679120 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.980675 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.137806 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 230157764 1.93% 1.93% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 11667291856 98.06% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 229500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 11897679120 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 997 85.65% 85.65% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::1M 167 14.35% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 1164 # Table walker page sizes translated
1797,1798c1782,1783
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6842 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6842 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6899 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst
1800,1804c1785,1789
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 8007 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 10488200 # ITB inst hits
< system.cpu1.itb.inst_misses 6842 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1164 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1164 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 8063 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 43584522 # ITB inst hits
> system.cpu1.itb.inst_misses 6899 # ITB inst misses
1813c1798
< system.cpu1.itb.flush_entries 1196 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1193 # Number of entries that have been flushed from TLB
1817c1802
< system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 547 # Number of TLB faults due to permissions restrictions
1820,1824c1805,1809
< system.cpu1.itb.inst_accesses 10495042 # ITB inst accesses
< system.cpu1.itb.hits 10488200 # DTB hits
< system.cpu1.itb.misses 6842 # DTB misses
< system.cpu1.itb.accesses 10495042 # DTB accesses
< system.cpu1.numCycles 43023242 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 43591421 # ITB inst accesses
> system.cpu1.itb.hits 43584522 # DTB hits
> system.cpu1.itb.misses 6899 # DTB misses
> system.cpu1.itb.accesses 43591421 # DTB accesses
> system.cpu1.numCycles 105332010 # number of cpu cycles simulated
1827,1843c1812,1828
< system.cpu1.fetch.icacheStallCycles 9545006 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 31536140 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 6152669 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 3495321 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 31308638 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 988880 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 91081 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 40105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 214294 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 338691 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 30719 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 10487595 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 131638 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 2429 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 42062974 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.911933 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.224898 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 10132151 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 108981973 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 33870827 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 27429128 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 92017725 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 3770452 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 88186 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 36483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 195284 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 298638 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 22598 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 43583923 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 117443 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 2417 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 104676291 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.289820 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.339564 # Number of instructions fetched each cycle (Total)
1845,1848c1830,1833
< system.cpu1.fetch.rateDist::0 24350235 57.89% 57.89% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 6287044 14.95% 72.84% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 2205515 5.24% 78.08% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 9220180 21.92% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 47827120 45.69% 45.69% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 14002469 13.38% 59.07% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 7529046 7.19% 66.26% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 35317656 33.74% 100.00% # Number of instructions fetched each cycle (Total)
1852,1898c1837,1883
< system.cpu1.fetch.rateDist::total 42062974 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.143008 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.733002 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 8267663 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 20626897 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 11490517 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 1337775 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 340122 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 874675 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 157334 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 30100708 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 1379443 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 340122 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 10041900 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 2603998 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 14921640 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 11019721 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 3135593 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 28621166 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 281517 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 330506 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 50454 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 20125 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 1923436 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 29030542 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 132294985 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 32813170 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 25609862 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 3420680 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 453393 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 375590 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 3438293 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 5562789 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 4719499 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 701110 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 705314 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 27634808 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 626900 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 27144127 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 143701 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 2955966 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 6891737 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 53840 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 42062974 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.645321 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 0.965357 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 104676291 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.321563 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.034652 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 13137871 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 61997568 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 26684640 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 1104927 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 1751285 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 750757 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 136902 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 67935331 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 1160131 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 1751285 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 17557644 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 2234457 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 57207184 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 23346153 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 2579568 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 55040039 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 231549 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 250107 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 36576 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 14638 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 1569614 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 54888875 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 259969011 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 58535420 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 1673 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 52136282 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 2752593 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 1876398 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 1803595 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 13068910 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 10432997 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 6892596 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 625658 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 847753 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 54148527 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 587967 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 53807238 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 110933 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 3881118 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 5762517 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 48708 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 104676291 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.514035 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 0.850765 # Number of insts issued each cycle
1900,1905c1885,1890
< system.cpu1.iq.issued_per_cycle::0 26343154 62.63% 62.63% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 7337268 17.44% 80.07% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 5660550 13.46% 93.53% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 2402263 5.71% 99.24% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 319725 0.76% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 14 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 71469096 68.28% 68.28% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 16529250 15.79% 84.07% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 13041841 12.46% 96.53% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 3350126 3.20% 99.73% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 285962 0.27% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 16 0.00% 100.00% # Number of insts issued each cycle
1912c1897
< system.cpu1.iq.issued_per_cycle::total 42062974 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 104676291 # Number of insts issued each cycle
1914,1944c1899,1929
< system.cpu1.iq.fu_full::IntAlu 1996325 32.40% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 609 0.01% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.40% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 1885144 30.59% 63.00% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 2280359 37.00% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 2912792 45.01% 45.01% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 674 0.01% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.02% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 1671813 25.83% 70.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 1886405 29.15% 100.00% # attempts to use FU when none available
1947,1978c1932,1963
< system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 17084879 62.94% 62.94% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 34880 0.13% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 4083 0.02% 63.09% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.09% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.09% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.09% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 5473288 20.16% 83.25% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 4546930 16.75% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 36660342 68.13% 68.13% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 45736 0.08% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 3323 0.01% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 10366546 19.27% 87.49% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 6731225 12.51% 100.00% # Type of FU issued
1981,1993c1966,1978
< system.cpu1.iq.FU_type_0::total 27144127 # Type of FU issued
< system.cpu1.iq.rate 0.630918 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 6162437 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.227027 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 102651570 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 31226183 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 26510239 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 5796 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 33302783 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 3714 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 106694 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 53807238 # Type of FU issued
> system.cpu1.iq.rate 0.510835 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 6471684 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.120275 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 218867204 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 58625584 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 51813824 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 6180 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 2068 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 60274803 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 4053 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 90118 # Number of loads that had data forwarded from stores
1995,1998c1980,1983
< system.cpu1.iew.lsq.thread0.squashedLoads 599497 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 782 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 10594 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 400513 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 483730 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 10069 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 351136 # Number of stores squashed
2001,2002c1986,1987
< system.cpu1.iew.lsq.thread0.rescheduledLoads 46755 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 99859 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 51537 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 78201 # Number of times an access to memory failed due to the cache being blocked
2004,2007c1989,1992
< system.cpu1.iew.iewSquashCycles 340122 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 663664 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 112730 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 28316728 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 1751285 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 538520 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 104583 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 54788620 # Number of instructions dispatched to IQ
2009,2020c1994,2005
< system.cpu1.iew.iewDispLoadInsts 5562789 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 4719499 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 329074 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 12650 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 90576 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 10594 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 71921 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 150578 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 222499 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 26808358 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 5342958 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 311471 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 10432997 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 6892596 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 301008 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 9394 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 87795 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 10069 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 55171 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 126265 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 181436 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 53538867 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 10265396 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 247288 # Number of squashed instructions skipped in execute
2022,2030c2007,2015
< system.cpu1.iew.exec_nop 55020 # number of nop insts executed
< system.cpu1.iew.exec_refs 9813397 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 4108906 # Number of branches executed
< system.cpu1.iew.exec_stores 4470439 # Number of stores executed
< system.cpu1.iew.exec_rate 0.623113 # Inst execution rate
< system.cpu1.iew.wb_sent 26632744 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 26512023 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 13415515 # num instructions producing a value
< system.cpu1.iew.wb_consumers 21195279 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 52126 # number of nop insts executed
> system.cpu1.iew.exec_refs 16932944 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 11793778 # Number of branches executed
> system.cpu1.iew.exec_stores 6667548 # Number of stores executed
> system.cpu1.iew.exec_rate 0.508287 # Inst execution rate
> system.cpu1.iew.wb_sent 53390597 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 51815609 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 25160275 # num instructions producing a value
> system.cpu1.iew.wb_consumers 38370093 # num instructions consuming a value
2032,2033c2017,2018
< system.cpu1.iew.wb_rate 0.616226 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.632948 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.491927 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.655726 # average fanout of values written-back
2035,2040c2020,2025
< system.cpu1.commit.commitSquashedInsts 2659330 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 573060 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 205791 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 41503303 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.610529 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.356545 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 3631838 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 539259 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 169982 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 102749355 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.495266 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.156980 # Number of insts commited each cycle
2042,2050c2027,2035
< system.cpu1.commit.committed_per_cycle::0 29410485 70.86% 70.86% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 7042051 16.97% 87.83% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 2116509 5.10% 92.93% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 864843 2.08% 95.01% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 769424 1.85% 96.87% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 435639 1.05% 97.92% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 276731 0.67% 98.58% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 147889 0.36% 98.94% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 439732 1.06% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 77230128 75.16% 75.16% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 14246960 13.87% 89.03% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 6071957 5.91% 94.94% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 703815 0.68% 95.62% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1976351 1.92% 97.55% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 1539288 1.50% 99.05% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 468880 0.46% 99.50% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 125021 0.12% 99.62% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 386955 0.38% 100.00% # Number of insts commited each cycle
2054,2056c2039,2041
< system.cpu1.commit.committed_per_cycle::total 41503303 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 20778200 # Number of instructions committed
< system.cpu1.commit.committedOps 25338954 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 102749355 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 41322014 # Number of instructions committed
> system.cpu1.commit.committedOps 50888230 # Number of ops (including micro ops) committed
2058,2061c2043,2046
< system.cpu1.commit.refs 9282278 # Number of memory references committed
< system.cpu1.commit.loads 4963292 # Number of loads committed
< system.cpu1.commit.membars 229830 # Number of memory barriers committed
< system.cpu1.commit.branches 3902679 # Number of branches committed
---
> system.cpu1.commit.refs 16490727 # Number of memory references committed
> system.cpu1.commit.loads 9949267 # Number of loads committed
> system.cpu1.commit.membars 209363 # Number of memory barriers committed
> system.cpu1.commit.branches 11627773 # Number of branches committed
2063,2064c2048,2049
< system.cpu1.commit.int_insts 22267919 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 549742 # Number of function calls committed.
---
> system.cpu1.commit.int_insts 45743033 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 3362907 # Number of function calls committed.
2066,2096c2051,2081
< system.cpu1.commit.op_class_0::IntAlu 16018762 63.22% 63.22% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 33831 0.13% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 4083 0.02% 63.37% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.37% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.37% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.37% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 4963292 19.59% 82.96% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 4318986 17.04% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 34349326 67.50% 67.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 44854 0.09% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 3323 0.01% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 9949267 19.55% 87.15% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 6541460 12.85% 100.00% # Class of committed instruction
2099,2114c2084,2099
< system.cpu1.commit.op_class_0::total 25338954 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 439732 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 67911551 # The number of ROB reads
< system.cpu1.rob.rob_writes 56552827 # The number of ROB writes
< system.cpu1.timesIdled 67532 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 960268 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 5207215501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 20744987 # Number of Instructions Simulated
< system.cpu1.committedOps 25305741 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 2.073910 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 2.073910 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.482181 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.482181 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 29917814 # number of integer regfile reads
< system.cpu1.int_regfile_writes 16874088 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 1382 # number of floating regfile reads
---
> system.cpu1.commit.op_class_0::total 50888230 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 386955 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 136861200 # The number of ROB reads
> system.cpu1.rob.rob_writes 110963404 # The number of ROB writes
> system.cpu1.timesIdled 59136 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 655719 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 5544933026 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 41289159 # Number of Instructions Simulated
> system.cpu1.committedOps 50855375 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 2.551082 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 2.551082 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.391991 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.391991 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 56164709 # number of integer regfile reads
> system.cpu1.int_regfile_writes 35664798 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 1398 # number of floating regfile reads
2116,2212c2101,2197
< system.cpu1.cc_regfile_reads 95785070 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 9455596 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 60806398 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 422782 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 228231 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 478.409113 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 8403253 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 228545 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 36.768483 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 103444079500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.409113 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934393 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.934393 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 18586968 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 18586968 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 4548259 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 4548259 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3563356 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3563356 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63759 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 63759 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87271 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 87271 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79516 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 79516 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 8111615 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 8111615 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 8175374 # number of overall hits
< system.cpu1.dcache.overall_hits::total 8175374 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 254647 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 254647 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 480567 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 480567 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35928 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 35928 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19211 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 19211 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23462 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23462 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 735214 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 735214 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 771142 # number of overall misses
< system.cpu1.dcache.overall_misses::total 771142 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4017153000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 4017153000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11025282924 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 11025282924 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 376163500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 376163500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545526500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 545526500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 528500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 528500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 15042435924 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 15042435924 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 15042435924 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 15042435924 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 4802906 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 4802906 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 4043923 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4043923 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99687 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 99687 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106482 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 106482 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102978 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 102978 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 8846829 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 8846829 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 8946516 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 8946516 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.053019 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.053019 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118837 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.118837 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.360408 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.360408 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.180415 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180415 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227835 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227835 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083105 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.083105 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086195 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.086195 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15775.379250 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15775.379250 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22942.238905 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 22942.238905 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19580.630889 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19580.630889 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23251.491774 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23251.491774 # average StoreCondReq miss latency
---
> system.cpu1.cc_regfile_reads 190801964 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 15538939 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 145958777 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 388038 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 188683 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 469.137779 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 15712566 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 189037 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 83.118998 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 93446032500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.137779 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916285 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.916285 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 32914145 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 32914145 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 9558582 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 9558582 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 5897409 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 5897409 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49196 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 49196 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78850 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 78850 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70461 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 70461 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 15455991 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 15455991 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 15505187 # number of overall hits
> system.cpu1.dcache.overall_hits::total 15505187 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 218229 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 218229 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 396239 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 396239 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29850 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 29850 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18125 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 18125 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23674 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23674 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 614468 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 614468 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 644318 # number of overall misses
> system.cpu1.dcache.overall_misses::total 644318 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3487669000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3487669000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9663134455 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 9663134455 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 358154500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 358154500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554726500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 554726500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 887500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 887500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 13150803455 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 13150803455 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 13150803455 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 13150803455 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 9776811 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 9776811 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 6293648 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 6293648 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79046 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 79046 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96975 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 96975 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94135 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 94135 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 16070459 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 16070459 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 16149505 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 16149505 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022321 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.022321 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062959 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.062959 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377628 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377628 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186904 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186904 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.251490 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.251490 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038236 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.038236 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039897 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.039897 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15981.693542 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15981.693542 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24387.136185 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 24387.136185 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19760.248276 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19760.248276 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23431.887303 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.887303 # average StoreCondReq miss latency
2215,2224c2200,2209
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20459.942172 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20459.942172 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19506.700354 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 19506.700354 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 359 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 1638919 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 40 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 49248 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.975000 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 33.278895 # average number of cycles each access was blocked
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21401.933795 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 21401.933795 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20410.423820 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 20410.423820 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 1417697 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 39735 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 35.678797 # average number of cycles each access was blocked
2227,2304c2212,2289
< system.cpu1.dcache.writebacks::writebacks 137260 # number of writebacks
< system.cpu1.dcache.writebacks::total 137260 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91413 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 91413 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375801 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 375801 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13808 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13808 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 467214 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 467214 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 467214 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 467214 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163234 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 163234 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104766 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 104766 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32551 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 32551 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5403 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5403 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23462 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23462 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 268000 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 268000 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 300551 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 300551 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5603 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10511 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2247760000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247760000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2639771935 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2639771935 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 542309000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 542309000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 101732500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 101732500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522075500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522075500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 517500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 517500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4887531935 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4887531935 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5429840935 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5429840935 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 989470000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 989470000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857954500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857954500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1847424500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1847424500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033987 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033987 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025907 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025907 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.326532 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.326532 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050741 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050741 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227835 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227835 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030293 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.030293 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033594 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033594 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.170430 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.170430 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25196.838049 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25196.838049 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16660.286934 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16660.286934 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18828.891357 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18828.891357 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22251.960617 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22251.960617 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 116769 # number of writebacks
> system.cpu1.dcache.writebacks::total 116769 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80049 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 80049 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306072 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 306072 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13108 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13108 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 386121 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 386121 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 386121 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 386121 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 138180 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 138180 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90167 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 90167 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28614 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 28614 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5017 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5017 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23674 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23674 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 228347 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 228347 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 256961 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 256961 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14486 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26301 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1915104500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1915104500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2355138466 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2355138466 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 482351500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 482351500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90011000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90011000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531068500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531068500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 871500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 871500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4270242966 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4270242966 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4752594466 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4752594466 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2349248500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2349248500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1864740000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1864740000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4213988500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4213988500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014133 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014133 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014327 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014327 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361992 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361992 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051735 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051735 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.251490 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.251490 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014209 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015911 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.015911 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.491243 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.491243 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26119.738552 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26119.738552 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16857.185294 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16857.185294 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17941.199920 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17941.199920 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22432.563149 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22432.563149 # average StoreCondReq mshr miss latency
2307,2316c2292,2301
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18237.059459 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18237.059459 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18066.288034 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18066.288034 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176596.466179 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176596.466179 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174807.355338 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174807.355338 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175761.059842 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 175761.059842 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18700.674701 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18700.674701 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18495.392165 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18495.392165 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162173.719453 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162173.719453 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157828.184511 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157828.184511 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160221.607543 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160221.607543 # average overall mshr uncacheable latency
2318,2326c2303,2311
< system.cpu1.icache.tags.replacements 661426 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.525577 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 9800007 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 661938 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 14.805023 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 78861824000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.525577 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973683 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.973683 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 603214 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.475238 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 42957427 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 603726 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 71.153846 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 78885354000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.475238 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975538 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.975538 # Average percentage of cache occupancy
2328,2329c2313,2314
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
2331,2371c2316,2356
< system.cpu1.icache.tags.tag_accesses 21636569 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 21636569 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 9800007 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 9800007 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 9800007 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 9800007 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 9800007 # number of overall hits
< system.cpu1.icache.overall_hits::total 9800007 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 687303 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 687303 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 687303 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 687303 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 687303 # number of overall misses
< system.cpu1.icache.overall_misses::total 687303 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6263235013 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 6263235013 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 6263235013 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 6263235013 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 6263235013 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 6263235013 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 10487310 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 10487310 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 10487310 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 10487310 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 10487310 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 10487310 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065537 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.065537 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065537 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.065537 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065537 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.065537 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9112.771242 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9112.771242 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9112.771242 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9112.771242 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 638996 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 564 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 53890 # number of cycles access was blocked
---
> system.cpu1.icache.tags.tag_accesses 87771063 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 87771063 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 42957427 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 42957427 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 42957427 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 42957427 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 42957427 # number of overall hits
> system.cpu1.icache.overall_hits::total 42957427 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 626240 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 626240 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 626240 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 626240 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 626240 # number of overall misses
> system.cpu1.icache.overall_misses::total 626240 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5487739407 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 5487739407 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 5487739407 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 5487739407 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 5487739407 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 5487739407 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 43583667 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 43583667 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 43583667 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 43583667 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 43583667 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 43583667 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014369 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.014369 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014369 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.014369 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014369 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.014369 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8762.997265 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8762.997265 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8762.997265 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8762.997265 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 503899 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 46132 # number of cycles access was blocked
2373,2374c2358,2359
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.857413 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 564 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.922982 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets 26 # average number of cycles each access was blocked
2377,2388c2362,2373
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 25354 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 25354 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 25354 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 25354 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 25354 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 25354 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 661949 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 661949 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 661949 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 661949 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 661949 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 661949 # number of overall MSHR misses
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22511 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 22511 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 22511 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 22511 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 22511 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 22511 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 603729 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 603729 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 603729 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 603729 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 603729 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 603729 # number of overall MSHR misses
2393,2418c2378,2403
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5721508360 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5721508360 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5721508360 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5721508360 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5721508360 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5721508360 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8594000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8594000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8594000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 8594000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063119 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.063119 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.063119 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8643.427757 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 84254.901961 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 84254.901961 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5031797233 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5031797233 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5031797233 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5031797233 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5031797233 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5031797233 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9110000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9110000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9110000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 9110000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013852 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.013852 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.013852 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8334.529620 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89313.725490 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89313.725490 # average overall mshr uncacheable latency
2420,2422c2405,2407
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 269622 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 270613 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 884 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 189065 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 189671 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 541 # number of redundant prefetches already in prefetch queue
2425,2430c2410,2415
< system.cpu1.l2cache.prefetcher.pfSpanPage 67787 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 66660 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15577.889137 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 1655246 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 81265 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 20.368498 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 56769 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 48663 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15171.630527 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 1474911 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 63236 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 23.323914 # Average number of references to valid blocks.
2432,2489c2417,2474
< system.cpu1.l2cache.tags.occ_blocks::writebacks 6747.638156 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.637913 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.167789 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4673.355619 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2625.058292 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1517.031368 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.411843 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000771 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000132 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285239 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.160221 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.092592 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.950799 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1291 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13290 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 868 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8605 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4215 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078796 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811157 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 30536660 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 30536660 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19077 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7323 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 26400 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 137259 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 137259 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2433 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 2433 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1103 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 1103 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38090 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 38090 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 639615 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 639615 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 127678 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 127678 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19077 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7323 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 639615 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 165768 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 831783 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19077 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7323 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 639615 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 165768 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 831783 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 286 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 8232.224686 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.332834 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.684874 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3831.793838 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2451.411988 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 641.182307 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.502455 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000692 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000225 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233874 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.149622 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.039135 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.926003 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1118 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 35 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13420 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 930 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 167 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8633 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4319 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068237 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002136 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819092 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 27275895 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 27275895 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 15350 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7200 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 22550 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 116768 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 116768 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1559 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1559 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 954 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 954 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27353 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 27353 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 586865 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 586865 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101704 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 101704 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 15350 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7200 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 586865 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 129057 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 738472 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 15350 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7200 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 586865 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 129057 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 738472 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 400 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 278 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 678 # number of ReadReq misses
2492,2618c2477,2597
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29127 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29127 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22358 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22358 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35752 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 35752 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22316 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 22316 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73485 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 73485 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 431 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 286 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 22316 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 109237 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 132270 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 431 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 286 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 22316 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 109237 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 132270 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9445500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5864000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 15309500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555921000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 555921000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449033000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449033000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 501000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 501000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1528833498 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1528833498 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 894673000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 894673000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1746677998 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1746677998 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9445500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5864000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 894673000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3275511496 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 4185493996 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9445500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5864000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 894673000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3275511496 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 4185493996 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19508 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7609 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 27117 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 137260 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 137260 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31560 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 31560 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23461 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23461 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73842 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 73842 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 661931 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 661931 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 201163 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 201163 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19508 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7609 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 661931 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 275005 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 964053 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19508 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7609 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 661931 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 275005 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 964053 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037587 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.026441 # miss rate for ReadReq accesses
< system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses
< system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.922909 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.922909 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952986 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952986 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484169 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484169 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.033713 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.033713 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.365301 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.365301 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037587 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033713 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.397218 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.137202 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037587 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033713 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.397218 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.137202 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20503.496503 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21352.161785 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19086.105675 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19086.105675 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20083.773146 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20083.773146 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 501000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 501000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42762.181081 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42762.181081 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40091.100556 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40091.100556 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23769.177356 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23769.177356 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 31643.562380 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 31643.562380 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked
---
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28175 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 28175 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22720 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22720 # number of SCUpgradeReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33751 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 33751 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16862 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 16862 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70088 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 70088 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 400 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 278 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 16862 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 103839 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 121379 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 400 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 278 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 16862 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 103839 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 121379 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8778500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5791500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 14570000 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536726500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 536726500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 459045500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 459045500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 847500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 847500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1378926000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1378926000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 607258000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 607258000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1556092998 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1556092998 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8778500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5791500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 607258000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 2935018998 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3556846998 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8778500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5791500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 607258000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 2935018998 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3556846998 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 15750 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7478 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 23228 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 116769 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 116769 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29734 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 29734 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23674 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23674 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61104 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 61104 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 603727 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 603727 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171792 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 171792 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 15750 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7478 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 603727 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 232896 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 859851 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 15750 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7478 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 603727 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 232896 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 859851 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037176 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.029189 # miss rate for ReadReq accesses
> system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses
> system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.947568 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947568 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.959703 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.959703 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.552353 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.552353 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027930 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027930 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.407982 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.407982 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037176 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027930 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.445860 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.141163 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037176 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027930 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.445860 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.141163 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20832.733813 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21489.675516 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19049.742680 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19049.742680 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20204.467430 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20204.467430 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40855.856123 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40855.856123 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36013.402918 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36013.402918 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22201.988900 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22201.988900 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20832.733813 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36013.402918 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28265.093058 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 29303.643942 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20832.733813 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36013.402918 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28265.093058 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 29303.643942 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked
2622c2601
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.800000 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 22.800000 # average number of cycles each access was blocked
2626,2646c2605,2625
< system.cpu1.l2cache.writebacks::writebacks 39050 # number of writebacks
< system.cpu1.l2cache.writebacks::total 39050 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 854 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 854 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 14 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 144 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 998 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 1025 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 998 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 1025 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 431 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 273 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 704 # number of ReadReq MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 30215 # number of writebacks
> system.cpu1.l2cache.writebacks::total 30215 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 420 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 420 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 76 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 76 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 496 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 516 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 496 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 516 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 400 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 264 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 664 # number of ReadReq MSHR misses
2649,2675c2628,2652
< system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3034 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::total 3034 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 37433 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29127 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29127 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22358 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22358 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34898 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 34898 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 22302 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 22302 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73341 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73341 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 431 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 273 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22302 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108239 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 131245 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 431 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 273 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22302 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108239 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 168678 # number of overall MSHR misses
---
> system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2169 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::total 2169 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23681 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 23681 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28175 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28175 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22720 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22720 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33331 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 33331 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16856 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16856 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70012 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70012 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 400 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 264 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16856 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103343 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 120863 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 400 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 264 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16856 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103343 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23681 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 144544 # number of overall MSHR misses
2677,2680c2654,2657
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5705 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14588 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable
2682,2724c2659,2701
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10613 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4063500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10923000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619868588 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619868588 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 495927500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 495927500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 345361500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 345361500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 435000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 435000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1215520500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1215520500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 760109500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 760109500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1300287998 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300287998 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4063500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 760109500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2515808498 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 3286840998 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4063500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 760109500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2515808498 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619868588 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4906709586 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7829000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 944359000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 952188000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 821025498 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 821025498 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7829000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1765384498 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1773213498 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025962 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses
< system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26403 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4031500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10410000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1037990412 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1037990412 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 463119500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 463119500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 352921500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 352921500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 751500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 751500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1120597500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1120597500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 506014500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 506014500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1134157998 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1134157998 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4031500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 506014500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2254755498 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 2771179998 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4031500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 506014500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2254755498 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1037990412 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 3809170410 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8345000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2233165500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2241510500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1776007998 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1776007998 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8345000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4009173498 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4017518498 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028586 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses
> system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses
2729,2749c2706,2724
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.922909 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.922909 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952986 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952986 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.472604 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.472604 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033692 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364585 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364585 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136139 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947568 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947568 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.959703 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959703 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.545480 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.545480 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027920 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.407539 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.407539 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140563 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for overall accesses
2751,2787c2726,2762
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174968 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15515.625000 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43273.811557 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17026.384454 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.384454 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15446.887020 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15446.887020 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 435000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 435000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34830.663648 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34830.663648 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34082.571070 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17729.346450 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17729.346450 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25043.552120 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29089.208942 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168545.243619 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166904.119194 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167283.108802 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 167283.108802 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 167955.903149 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167079.383586 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168104 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15677.710843 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43832.203539 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16437.249335 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16437.249335 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15533.516725 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15533.516725 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33620.278419 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33620.278419 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30019.844566 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16199.480061 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16199.480061 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22928.274145 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26353.016452 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154160.258180 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153654.407732 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150318.070080 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150318.070080 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152434.260979 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 152161.439912 # average overall mshr uncacheable latency
2789,2798c2764,2773
< system.cpu1.toL2Bus.trans_dist::ReadReq 70770 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 942311 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 4908 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 510267 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 868505 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 48336 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 75730 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43006 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 89941 # Transaction distribution
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 67801 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 858839 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 11815 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 481520 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 790490 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 28803 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 75635 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42021 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 86708 # Transaction distribution
2800,2804c2775,2779
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 96740 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 79738 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 661949 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 536905 # Transaction distribution
---
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 83417 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 65666 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 603729 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 520017 # Transaction distribution
2806,2819c2781,2794
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1973224 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 988189 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17063 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42721 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 3021197 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42365216 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29405313 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30436 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78032 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 71878997 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 1156869 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 2994555 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 1.368102 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.482289 # Request fanout histogram
---
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1799792 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 888351 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17049 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 36002 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2741194 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38640160 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25264094 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29912 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 63000 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 63997166 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 1119232 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 2773999 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 1.384160 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.486396 # Request fanout histogram
2822,2823c2797,2798
< system.cpu1.toL2Bus.snoop_fanout::1 1892252 63.19% 63.19% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 1102303 36.81% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::1 1708339 61.58% 61.58% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 1065660 38.42% 100.00% # Request fanout histogram
2827,2828c2802,2803
< system.cpu1.toL2Bus.snoop_fanout::total 2994555 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1102178989 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 2773999 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 991762490 # Layer occupancy (ticks)
2830c2805
< system.cpu1.toL2Bus.snoopLayer0.occupancy 87567999 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 81878499 # Layer occupancy (ticks)
2832c2807
< system.cpu1.toL2Bus.respLayer0.occupancy 993110829 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 905763364 # Layer occupancy (ticks)
2834c2809
< system.cpu1.toL2Bus.respLayer1.occupancy 449674318 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 398007900 # Layer occupancy (ticks)
2836c2811
< system.cpu1.toL2Bus.respLayer2.occupancy 9464978 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 9580481 # Layer occupancy (ticks)
2838c2813
< system.cpu1.toL2Bus.respLayer3.occupancy 23224976 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 20262978 # Layer occupancy (ticks)
2840,2841c2815,2816
< system.iobus.trans_dist::ReadReq 31011 # Transaction distribution
< system.iobus.trans_dist::ReadResp 31011 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
> system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
2849c2824
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2865c2840
< system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes)
2868c2843
< system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes)
2874c2849
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2890c2865
< system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2893c2868
< system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes)
2904c2879
< system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
2938c2913
< system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks)
2943c2918
< system.iocache.tags.tagsinuse 14.446879 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.557293 # Cycle average of tags in use
2947,2950c2922,2925
< system.iocache.tags.warmup_cycle 254837974000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.446879 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.902930 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.902930 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 254755320000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.557293 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.909831 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.909831 # Average percentage of cache occupancy
2964,2971c2939,2946
< system.iocache.ReadReq_miss_latency::realview.ide 32277877 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 32277877 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4275018561 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4275018561 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 32277877 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 32277877 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 32277877 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 32277877 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 32401877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 32401877 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4274240561 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4274240561 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 32401877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 32401877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 32401877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 32401877 # number of overall miss cycles
2988,2995c2963,2970
< system.iocache.ReadReq_avg_miss_latency::realview.ide 128086.813492 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 128086.813492 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118016.192607 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118016.192607 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 128086.813492 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 128086.813492 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 128578.876984 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 128578.876984 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117994.715134 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 117994.715134 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 128578.876984 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 128578.876984 # average overall miss latency
3014,3021c2989,2996
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 19677877 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 19677877 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463818561 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2463818561 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 19677877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 19677877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 19677877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 19677877 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 19801877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 19801877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463040561 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2463040561 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 19801877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 19801877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 19801877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 19801877 # number of overall MSHR miss cycles
3030,3037c3005,3012
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78086.813492 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 78086.813492 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68016.192607 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68016.192607 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78578.876984 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 78578.876984 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67994.715134 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67994.715134 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency
3039,3043c3014,3018
< system.l2c.tags.replacements 136014 # number of replacements
< system.l2c.tags.tagsinuse 64041.678257 # Cycle average of tags in use
< system.l2c.tags.total_refs 410908 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 200324 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.051217 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 130408 # number of replacements
> system.l2c.tags.tagsinuse 64065.129893 # Cycle average of tags in use
> system.l2c.tags.total_refs 410009 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 194847 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.104261 # Average number of references to valid blocks.
3045,3138c3020,3112
< system.l2c.tags.occ_blocks::writebacks 12985.002975 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.737581 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 3.016987 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 6471.116722 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 1893.814522 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32628.788989 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.896219 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 1.746917 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 3305.203826 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 1817.254812 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4915.098707 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.198135 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.098741 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.028897 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.497876 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000027 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.050433 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.027729 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.074998 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.977198 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 30547 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 33736 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 6158 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 24257 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 28206 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.466110 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.514771 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 5562101 # Number of tag accesses
< system.l2c.tags.data_accesses 5562101 # Number of data accesses
< system.l2c.Writeback_hits::writebacks 232311 # number of Writeback hits
< system.l2c.Writeback_hits::total 232311 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 2454 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 792 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 3246 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 65 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 3756 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1862 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5618 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 89 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 33340 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 45362 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 43171 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 54 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 50 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 17322 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 11995 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 7539 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 159106 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 33340 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 49118 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 43171 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 54 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 17322 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 13857 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 7539 # number of demand (read+write) hits
< system.l2c.demand_hits::total 164724 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 33340 # number of overall hits
< system.l2c.overall_hits::cpu0.data 49118 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 43171 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 54 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 17322 # number of overall hits
< system.l2c.overall_hits::cpu1.data 13857 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 7539 # number of overall hits
< system.l2c.overall_hits::total 164724 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 8230 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3781 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 12011 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 840 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1988 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11269 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 9058 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 20327 # number of ReadExReq misses
---
> system.l2c.tags.occ_blocks::writebacks 11642.697009 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.974901 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.090106 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 8094.672337 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 2978.207969 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37076.471677 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.445472 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909924 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1874.720720 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 683.354796 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1693.584982 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.177653 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000213 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.123515 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.045444 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565742 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.028606 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.010427 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025842 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.977556 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 31097 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 33320 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 200 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 5745 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 25152 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 514 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 6128 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 26654 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.474503 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.508423 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 5488101 # Number of tag accesses
> system.l2c.tags.data_accesses 5488101 # Number of data accesses
> system.l2c.Writeback_hits::writebacks 227912 # number of Writeback hits
> system.l2c.Writeback_hits::total 227912 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 2549 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 581 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 3130 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 167 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 333 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 3885 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1531 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5416 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 182 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 78 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 36625 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 47695 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45738 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 45 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 34 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 14003 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 9344 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4694 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 158438 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 182 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 36625 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 51580 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 45738 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 45 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 14003 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 10875 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 4694 # number of demand (read+write) hits
> system.l2c.demand_hits::total 163854 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 182 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 36625 # number of overall hits
> system.l2c.overall_hits::cpu0.data 51580 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 45738 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 45 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 14003 # number of overall hits
> system.l2c.overall_hits::cpu1.data 10875 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 4694 # number of overall hits
> system.l2c.overall_hits::total 163854 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 8869 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 2831 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 11700 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 686 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1243 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1929 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11279 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 8332 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 19611 # number of ReadExReq misses
3140,3149c3114,3123
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 7 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 17264 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 8071 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 10 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 4969 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 2483 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 173860 # number of ReadSharedReq misses
---
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 19189 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 9101 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131841 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 9 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 2845 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 1165 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6684 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 170863 # number of ReadSharedReq misses
3151,3160c3125,3134
< system.l2c.demand_misses::cpu0.itb.walker 7 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 17264 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 19340 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 4969 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 11541 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) misses
< system.l2c.demand_misses::total 194187 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 19189 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 20380 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 131841 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 2845 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 9497 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 6684 # number of demand (read+write) misses
> system.l2c.demand_misses::total 190474 # number of demand (read+write) misses
3162,3342c3136,3316
< system.l2c.overall_misses::cpu0.itb.walker 7 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 17264 # number of overall misses
< system.l2c.overall_misses::cpu0.data 19340 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 130238 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 4969 # number of overall misses
< system.l2c.overall_misses::cpu1.data 11541 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 10791 # number of overall misses
< system.l2c.overall_misses::total 194187 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 7636500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 4088000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 11724500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1275500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 739500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 2015000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1086401000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 758222000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1844623000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2203000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 699000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1415731001 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 721065000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 855000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 165500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 421639500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 224776000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 18692667834 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 2203000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 699000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1415731001 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1807466000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 855000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 165500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 421639500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 982998000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 20537290834 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 2203000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 699000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1415731001 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1807466000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 855000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 165500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 421639500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 982998000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 20537290834 # number of overall miss cycles
< system.l2c.Writeback_accesses::writebacks 232311 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 232311 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 10684 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 4573 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 15257 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 1087 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1213 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2300 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 15025 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 10920 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 25945 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 209 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 96 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 50604 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 53433 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 173409 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 64 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 52 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 22291 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 14478 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 18330 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 332966 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 209 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 96 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 50604 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 68458 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173409 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 64 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 52 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 22291 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 25398 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18330 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 358911 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 209 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 96 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 50604 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 68458 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173409 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 64 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 52 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 22291 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 25398 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18330 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 358911 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.770311 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.826810 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.787245 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772769 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.946414 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.864348 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.750017 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.829487 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.783465 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.072917 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.341159 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.151049 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.038462 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.222915 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171502 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.522155 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.072917 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.341159 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.282509 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.038462 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.222915 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.454406 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.541045 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.072917 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.341159 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.282509 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.038462 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.222915 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.454406 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.541045 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 927.885784 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1081.195451 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 976.146865 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1518.452381 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 644.163763 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1013.581489 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96406.158488 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83707.440936 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 90747.429527 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88120 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 99857.142857 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82004.807750 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89340.230455 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 85500 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 82750 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84853.994768 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90525.976641 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 107515.632313 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 105760.379603 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 105760.379603 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 1319 # number of cycles access was blocked
---
> system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 19189 # number of overall misses
> system.l2c.overall_misses::cpu0.data 20380 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 131841 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 2845 # number of overall misses
> system.l2c.overall_misses::cpu1.data 9497 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 6684 # number of overall misses
> system.l2c.overall_misses::total 190474 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 8584000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 2028000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 10612000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1081500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1017000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 2098500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1148001500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 689593000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 1837594500 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2446500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 248000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1585577501 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 820774000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14236289443 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 820000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 310000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 240581000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 107330500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 936970593 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 17931347537 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 2446500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 248000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1585577501 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 1968775500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14236289443 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 820000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 310000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 240581000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 796923500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 936970593 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 19768942037 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 2446500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 248000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1585577501 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 1968775500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14236289443 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 820000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 310000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 240581000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 796923500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 936970593 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 19768942037 # number of overall miss cycles
> system.l2c.Writeback_accesses::writebacks 227912 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 227912 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 11418 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 3412 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 14830 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 853 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1409 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2262 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15164 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 9863 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 25027 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 207 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 81 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 55814 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 56796 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177579 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 54 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 16848 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 10509 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11378 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 329301 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 207 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 81 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 55814 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 71960 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177579 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 54 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 16848 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 20372 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11378 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 354328 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 207 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 81 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 55814 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 71960 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177579 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 54 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 16848 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 20372 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11378 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 354328 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.776756 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829719 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.788941 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.804220 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.882186 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.852785 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.743801 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.844773 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.783594 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.037037 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.343803 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.160240 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.028571 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.168863 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.110857 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.518866 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.037037 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.343803 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.283213 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.028571 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.168863 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.466179 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.537564 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.037037 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.343803 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.283213 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.028571 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.168863 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.466179 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.537564 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 967.865599 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 716.354645 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 907.008547 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1576.530612 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 818.181818 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1087.869362 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101782.205869 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.402304 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 93702.233440 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 97860 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 82666.666667 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82629.501329 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90185.034612 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91111.111111 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 310000 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84562.741652 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92129.184549 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 104945.760855 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 97860 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82666.666667 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 82629.501329 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 96603.312071 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91111.111111 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 310000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 84562.741652 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 83913.183110 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 103788.139258 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 97860 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82666.666667 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 82629.501329 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 96603.312071 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91111.111111 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 310000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 84562.741652 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 83913.183110 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 103788.139258 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
3344c3318
< system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
3346c3320
< system.l2c.avg_blocked_cycles::no_mshrs 62.809524 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
3350,3371c3324,3345
< system.l2c.writebacks::writebacks 104474 # number of writebacks
< system.l2c.writebacks::total 104474 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3557 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3557 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 8230 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 3781 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 12011 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 840 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1148 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1988 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11269 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 9058 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 20327 # number of ReadExReq MSHR misses
---
> system.l2c.writebacks::writebacks 100621 # number of writebacks
> system.l2c.writebacks::total 100621 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 12 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 3122 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 3122 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8869 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 2831 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 11700 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 686 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1243 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1929 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11279 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 8332 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 19611 # number of ReadExReq MSHR misses
3373,3382c3347,3356
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 7 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17259 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8071 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 4959 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2483 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 173845 # number of ReadSharedReq MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19186 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9101 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131841 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2836 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1165 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6684 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 170851 # number of ReadSharedReq MSHR misses
3384,3393c3358,3367
< system.l2c.demand_mshr_misses::cpu0.itb.walker 7 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 17259 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 19340 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 4959 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 11541 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 194172 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 19186 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 20380 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131841 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 2836 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 9497 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6684 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 190462 # number of demand (read+write) MSHR misses
3395,3404c3369,3378
< system.l2c.overall_mshr_misses::cpu0.itb.walker 7 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 17259 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 19340 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 4959 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 11541 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 194172 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 19186 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 20380 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131841 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 2836 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 9497 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6684 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 190462 # number of overall MSHR misses
3406c3380
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable
3408,3412c3382,3386
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5600 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 38100 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 31035 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14482 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 37974 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 30901 # number of WriteReq MSHR uncacheable
3414c3388
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses
3416,3459c3390,3433
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10508 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 69135 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 170692500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 78410000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 249102500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17547003 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23836000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 41383003 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973711000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 667642000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 1641353000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 629000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1242953501 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 640355000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 755000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 145500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 371358500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 199946000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 16953339334 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 629000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1242953501 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 1614066000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 755000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 145500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 371358500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 867588000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 18594692334 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 629000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1242953501 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 1614066000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 755000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 145500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 371358500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 867588000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 18594692334 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26297 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 68875 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 183870501 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 58746000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 242616501 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14335002 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25812000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 40147002 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1035211500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606273000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 1641484500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2196500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 218000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1393418001 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 729764000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12917879443 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 730000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 300000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 211664500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 95680500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 870130593 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 16221981537 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2196500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 218000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1393418001 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 1764975500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12917879443 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 730000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 300000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 211664500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 701953500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 870130593 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 17863466037 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2196500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 218000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1393418001 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 1764975500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12917879443 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 730000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 300000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 211664500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 701953500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 870130593 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 17863466037 # number of overall MSHR miss cycles
3461,3467c3435,3441
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4916712000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5992000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 843515500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 5955489000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3669260542 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 737586502 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4406847044 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3785154000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6508000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1972430500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 5953362000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2828697042 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1575146501 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4403843543 # number of WriteReq MSHR uncacheable cycles
3469,3472c3443,3446
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8585972542 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5992000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1581102002 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 10362336044 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6613851042 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6508000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3547577001 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10357205543 # number of overall MSHR uncacheable cycles
3475,3558c3449,3532
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.770311 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.826810 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.787245 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772769 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.946414 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.864348 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750017 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.829487 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.783465 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.151049 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171502 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.522110 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.541003 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.541003 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20740.279465 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20737.900026 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20739.530430 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20889.289286 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.066202 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20816.399899 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86406.158488 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73707.440936 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 80747.429527 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79340.230455 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80525.976641 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97519.855814 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.776756 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829719 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.788941 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.804220 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.882186 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.852785 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743801 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.844773 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.783594 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.160240 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110857 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.518829 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.283213 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.466179 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.537530 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.283213 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.466179 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.537530 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20731.818807 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20750.971388 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20736.453077 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20896.504373 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.888978 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20812.339036 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91782.205869 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72764.402304 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 83702.233440 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80185.034612 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82129.184549 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 94948.121679 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency
3560,3566c3534,3540
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167269.238620 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150627.767857 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156312.047244 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140439.412944 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150282.498370 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141996.038150 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185674.188168 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136198.763983 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156774.687944 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148207.955674 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133317.520186 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142514.596388 # average WriteReq mshr uncacheable latency
3568,3571c3542,3545
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154643.694134 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150466.501903 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 149885.528951 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167558.042207 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134904.247671 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 150376.849989 # average overall mshr uncacheable latency
3573,3585c3547,3558
< system.membus.trans_dist::ReadReq 38100 # Transaction distribution
< system.membus.trans_dist::ReadResp 212196 # Transaction distribution
< system.membus.trans_dist::WriteReq 31035 # Transaction distribution
< system.membus.trans_dist::WriteResp 31035 # Transaction distribution
< system.membus.trans_dist::Writeback 140680 # Transaction distribution
< system.membus.trans_dist::CleanEvict 16716 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 41581 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 14111 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
< system.membus.trans_dist::ReadExReq 40212 # Transaction distribution
< system.membus.trans_dist::ReadExResp 20215 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 174097 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 37974 # Transaction distribution
> system.membus.trans_dist::ReadResp 209076 # Transaction distribution
> system.membus.trans_dist::WriteReq 30901 # Transaction distribution
> system.membus.trans_dist::WriteResp 30901 # Transaction distribution
> system.membus.trans_dist::Writeback 136827 # Transaction distribution
> system.membus.trans_dist::CleanEvict 16300 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 76178 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 40718 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 13724 # Transaction distribution
> system.membus.trans_dist::ReadExReq 39427 # Transaction distribution
> system.membus.trans_dist::ReadExResp 19516 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 171103 # Transaction distribution
3588c3561
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes)
3590,3592c3563,3565
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14206 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 677829 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 799987 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663947 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 785587 # Packet count per connected master and slave (bytes)
3595,3596c3568,3569
< system.membus.pkt_count::total 908921 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 894521 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
3598,3600c3571,3573
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28412 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19154168 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 19345693 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18671220 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18861706 # Cumulative packet size per connected master and slave (bytes)
3603,3605c3576,3578
< system.membus.pkt_size::total 21663837 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 125106 # Total snoops (count)
< system.membus.snoop_fanout::samples 595969 # Request fanout histogram
---
> system.membus.pkt_size::total 21179850 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 123655 # Total snoops (count)
> system.membus.snoop_fanout::samples 585907 # Request fanout histogram
3610c3583
< system.membus.snoop_fanout::1 595969 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 585907 100.00% 100.00% # Request fanout histogram
3615,3616c3588,3589
< system.membus.snoop_fanout::total 595969 # Request fanout histogram
< system.membus.reqLayer0.occupancy 81639500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 585907 # Request fanout histogram
> system.membus.reqLayer0.occupancy 81623000 # Layer occupancy (ticks)
3620c3593
< system.membus.reqLayer2.occupancy 11797490 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11432490 # Layer occupancy (ticks)
3622c3595
< system.membus.reqLayer5.occupancy 1030129184 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 989982724 # Layer occupancy (ticks)
3624c3597
< system.membus.respLayer2.occupancy 1147298884 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1127040159 # Layer occupancy (ticks)
3626c3599
< system.membus.respLayer3.occupancy 64422049 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 64467297 # Layer occupancy (ticks)
3659,3672c3632,3645
< system.toL2Bus.trans_dist::ReadReq 38103 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 495292 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 373006 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 88968 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 80200 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 41893 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 122093 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 50895 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 50895 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 457205 # Transaction distribution
---
> system.toL2Bus.trans_dist::ReadReq 37978 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 489550 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30901 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 364752 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 88216 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 79213 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 41051 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 120264 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 50507 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 50507 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 451588 # Transaction distribution
3674,3683c3647,3656
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082088 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 352339 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1434427 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31351112 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6763093 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 38114205 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 462700 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 1239270 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.168619 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.374415 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1086474 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 331144 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1417618 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32384412 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5153902 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 37538314 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 454329 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 1220605 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.166616 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.372633 # Request fanout histogram
3686,3687c3659,3660
< system.toL2Bus.snoop_fanout::1 1030306 83.14% 83.14% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 208964 16.86% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 1017233 83.34% 83.34% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 203372 16.66% 100.00% # Request fanout histogram
3691,3692c3664,3665
< system.toL2Bus.snoop_fanout::total 1239270 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 822017005 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 1220605 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 824158889 # Layer occupancy (ticks)
3696c3669
< system.toL2Bus.respLayer0.occupancy 615196241 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 620803562 # Layer occupancy (ticks)
3698c3671
< system.toL2Bus.respLayer1.occupancy 261600624 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 245897316 # Layer occupancy (ticks)
3701c3674
< system.cpu0.kern.inst.quiesce 2069 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed
3703c3676
< system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 2769 # number of quiesce instructions executed