3,5c3,5
< sim_seconds 2.625396 # Number of seconds simulated
< sim_ticks 2625395606000 # Number of ticks simulated
< final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.625378 # Number of seconds simulated
> sim_ticks 2625378187500 # Number of ticks simulated
> final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 93034 # Simulator instruction rate (inst/s)
< host_op_rate 112875 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2029681489 # Simulator tick rate (ticks/s)
< host_mem_usage 651304 # Number of bytes of host memory used
< host_seconds 1293.50 # Real time elapsed on the host
< sim_insts 120339436 # Number of instructions simulated
< sim_ops 146004136 # Number of ops (including micro ops) simulated
---
> host_inst_rate 94574 # Simulator instruction rate (inst/s)
> host_op_rate 114754 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2065319127 # Simulator tick rate (ticks/s)
> host_mem_usage 650700 # Number of bytes of host memory used
> host_seconds 1271.17 # Real time elapsed on the host
> sim_insts 120220550 # Number of instructions simulated
> sim_ops 145872273 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::cpu0.inst 1180896 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1238652 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8338496 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1156128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1193576 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8234944 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
23,25c23,25
< system.physmem.bytes_read::cpu1.inst 327120 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 750304 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 683328 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu1.inst 336832 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 657616 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 605504 # Number of bytes read from this memory
27,32c27,32
< system.physmem.bytes_read::total 12522572 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1180896 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 327120 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1508016 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8921792 # Number of bytes written to this memory
< system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12188376 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1156128 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 336832 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1492960 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8634432 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
34,35c34,35
< system.physmem.bytes_written::total 8939536 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8651996 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
37,40c37,40
< system.physmem.num_reads::cpu0.inst 20697 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 19879 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 130289 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 20310 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 19170 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 128671 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
42,44c42,44
< system.physmem.num_reads::cpu1.inst 5178 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 11747 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 10677 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 5329 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 10295 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 9461 # Number of read requests responded to by this memory
46,48c46,48
< system.physmem.num_reads::total 198526 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 139403 # Number of write requests responded to by this memory
< system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 193295 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 134913 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
50,51c50,51
< system.physmem.num_writes::total 143839 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 683 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 139304 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 658 # Total read bandwidth from this memory (bytes/s)
53,56c53,56
< system.physmem.bw_read::cpu0.inst 449797 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 471796 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 3176091 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 440366 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 454630 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 3136670 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 268 # Total read bandwidth from this memory (bytes/s)
58,60c58,60
< system.physmem.bw_read::cpu1.inst 124598 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 285787 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 260276 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 128298 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 250484 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 230635 # Total read bandwidth from this memory (bytes/s)
62,67c62,67
< system.physmem.bw_read::total 4769785 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 449797 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 124598 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 574396 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3398266 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 6743 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4642522 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 440366 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 128298 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 568665 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3288834 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s)
69,71c69,71
< system.physmem.bw_write::total 3405024 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3398266 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 683 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3295524 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3288834 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 658 # Total bandwidth to/from this memory (bytes/s)
73,76c73,76
< system.physmem.bw_total::cpu0.inst 449797 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 478540 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 3176091 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 440366 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 461305 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 3136670 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 268 # Total bandwidth to/from this memory (bytes/s)
78,80c78,80
< system.physmem.bw_total::cpu1.inst 124598 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 285802 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 260276 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu1.inst 128298 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 250500 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 230635 # Total bandwidth to/from this memory (bytes/s)
82,126c82,126
< system.physmem.bw_total::total 8174809 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 198527 # Number of read requests accepted
< system.physmem.writeReqs 180063 # Number of write requests accepted
< system.physmem.readBursts 198527 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 180063 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12696000 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue
< system.physmem.bytesWritten 10018560 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12522636 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 11257872 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 23492 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 14407 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12827 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12491 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12947 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12890 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14947 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12185 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12844 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12385 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12025 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12120 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11888 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11181 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11694 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12452 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11831 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11668 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10196 # Per bank write bursts
< system.physmem.perBankWrBursts::1 10156 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10450 # Per bank write bursts
< system.physmem.perBankWrBursts::3 10103 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9839 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9619 # Per bank write bursts
< system.physmem.perBankWrBursts::6 10216 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9774 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9494 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9611 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9445 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9199 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9616 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9900 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9667 # Per bank write bursts
< system.physmem.perBankWrBursts::15 9255 # Per bank write bursts
---
> system.physmem.bw_total::total 7938046 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 193296 # Number of read requests accepted
> system.physmem.writeReqs 175528 # Number of write requests accepted
> system.physmem.readBursts 193296 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 175528 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12362624 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9724800 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12188440 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10970332 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 23562 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 14506 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 12287 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11514 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12472 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12180 # Per bank write bursts
> system.physmem.perBankRdBursts::4 14590 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12444 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12518 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12466 # Per bank write bursts
> system.physmem.perBankRdBursts::8 11679 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12089 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11915 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11053 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11299 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11450 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11880 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11330 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9713 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9189 # Per bank write bursts
> system.physmem.perBankWrBursts::2 10054 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9647 # Per bank write bursts
> system.physmem.perBankWrBursts::4 9435 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9608 # Per bank write bursts
> system.physmem.perBankWrBursts::6 10036 # Per bank write bursts
> system.physmem.perBankWrBursts::7 9866 # Per bank write bursts
> system.physmem.perBankWrBursts::8 9192 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9471 # Per bank write bursts
> system.physmem.perBankWrBursts::10 9539 # Per bank write bursts
> system.physmem.perBankWrBursts::11 9209 # Per bank write bursts
> system.physmem.perBankWrBursts::12 9294 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9108 # Per bank write bursts
> system.physmem.perBankWrBursts::14 9699 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8890 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 63 # Number of times write queue was full causing retry
< system.physmem.totGap 2625395343000 # Total gap between requests
---
> system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
> system.physmem.totGap 2625377925000 # Total gap between requests
132c132
< system.physmem.readPktSize::2 559 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 550 # Read request sizes (log2)
134c134
< system.physmem.readPktSize::4 3083 # Read request sizes (log2)
---
> system.physmem.readPktSize::4 3082 # Read request sizes (log2)
136c136
< system.physmem.readPktSize::6 194857 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 189636 # Read request sizes (log2)
139c139
< system.physmem.writePktSize::2 4436 # Write request sizes (log2)
---
> system.physmem.writePktSize::2 4391 # Write request sizes (log2)
143,163c143,163
< system.physmem.writePktSize::6 175627 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 60901 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 71603 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 16635 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 12571 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8573 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7706 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 6473 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 4946 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1315 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 955 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 741 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 319 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 264 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 171137 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 58646 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 70721 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 16311 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12182 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 8246 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7467 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 6266 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 5177 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 4683 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1253 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 923 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 715 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 309 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
191,257c191,257
< system.physmem.wrQLenPdf::15 2178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2364 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 3392 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4260 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4830 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5632 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6761 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7304 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 7856 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9461 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8415 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9026 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 11942 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 9626 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8927 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 8140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1572 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1432 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1535 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 2344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1780 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 2392 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1761 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1974 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1723 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1757 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1763 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1494 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1375 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 811 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 446 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 449 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 224 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 91717 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 247.658515 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 138.206739 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 311.047088 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 48645 53.04% 53.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18050 19.68% 72.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5879 6.41% 79.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3418 3.73% 82.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2896 3.16% 86.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1497 1.63% 87.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 939 1.02% 88.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1042 1.14% 89.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9351 10.20% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 91717 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6649 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 29.834862 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 569.193500 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6647 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2100 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2340 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 3256 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4036 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5294 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5941 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6575 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7082 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7445 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7962 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8621 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 11356 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 9282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 8943 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 8063 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1588 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1372 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2519 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2445 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1674 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2563 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1837 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1717 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1608 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1995 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1362 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1075 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 796 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 429 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 337 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 87477 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 252.493341 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 140.519371 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 314.341475 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 45925 52.50% 52.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16983 19.41% 71.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5819 6.65% 78.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3357 3.84% 82.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2775 3.17% 85.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1460 1.67% 87.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 948 1.08% 88.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 995 1.14% 89.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9215 10.53% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 87477 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6395 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 30.205629 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 580.308341 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6393 99.97% 99.97% # Reads before turning the bus around for writes
260,300c260,297
< system.physmem.rdPerTurnAround::total 6649 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6649 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 23.543390 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.659302 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 38.965105 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-31 6283 94.50% 94.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-47 92 1.38% 95.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-63 34 0.51% 96.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-95 28 0.42% 96.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-111 36 0.54% 97.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-127 35 0.53% 98.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-143 13 0.20% 98.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-159 17 0.26% 98.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-175 4 0.06% 98.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-191 17 0.26% 98.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-207 15 0.23% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-223 12 0.18% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-271 5 0.08% 99.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-287 5 0.08% 99.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-303 1 0.02% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::304-319 2 0.03% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::320-335 5 0.08% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::336-351 4 0.06% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::352-367 13 0.20% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::368-383 1 0.02% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::416-431 2 0.03% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::496-511 1 0.02% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-527 3 0.05% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::544-559 1 0.02% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::672-687 2 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::688-703 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::704-719 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6649 # Writes before turning the bus around for reads
< system.physmem.totQLat 7005041065 # Total ticks spent queuing
< system.physmem.totMemAccLat 10724572315 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 991875000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 35312.12 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6395 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6395 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 23.760751 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.753987 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 37.694415 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 6028 94.26% 94.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 95 1.49% 95.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 28 0.44% 96.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 10 0.16% 96.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 24 0.38% 96.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 40 0.63% 97.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 30 0.47% 97.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 13 0.20% 98.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 18 0.28% 98.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 5 0.08% 98.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 23 0.36% 98.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 21 0.33% 99.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 7 0.11% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 3 0.05% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 2 0.03% 99.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 5 0.08% 99.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 3 0.05% 99.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 2 0.03% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 3 0.05% 99.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 7 0.11% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 6 0.09% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 11 0.17% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 1 0.02% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 2 0.03% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 2 0.03% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 3 0.05% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::688-703 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6395 # Writes before turning the bus around for reads
> system.physmem.totQLat 6824061250 # Total ticks spent queuing
> system.physmem.totMemAccLat 10445923750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 965830000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 35327.45 # Average queueing delay per DRAM burst
302,306c299,303
< system.physmem.avgMemAccLat 54062.12 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.84 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.77 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.29 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 54077.45 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.71 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.70 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.64 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.18 # Average system write bandwidth in MiByte/s
311,329c308,326
< system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 27.13 # Average write queue length when enqueuing
< system.physmem.readRowHits 165504 # Number of row buffer hits during reads
< system.physmem.writeRowHits 97693 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 62.40 # Row buffer hit rate for writes
< system.physmem.avgGap 6934666.38 # Average gap between requests
< system.physmem.pageHitRate 74.15 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 361050480 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 197001750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 807424800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 520687440 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 75248496990 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1509227374500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1757839822440 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.553437 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2510629171267 # Time in different power states
< system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states
---
> system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 27.24 # Average write queue length when enqueuing
> system.physmem.readRowHits 161531 # Number of row buffer hits during reads
> system.physmem.writeRowHits 96107 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes
> system.physmem.avgGap 7118240.48 # Average gap between requests
> system.physmem.pageHitRate 74.65 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 340124400 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 185583750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 783673800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 502511040 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 74898468540 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1509525073500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1757712204390 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.508799 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2511124862587 # Time in different power states
> system.physmem_0.memoryStateTime::REF 87667060000 # Time in different power states
331c328
< system.physmem_0.memoryStateTime::ACT 27094642483 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 26583898663 # Time in different power states
333,343c330,340
< system.physmem_1.actEnergy 332330040 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 181330875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 739892400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 493691760 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 74790166545 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1509629418750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1757644616850 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.479084 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2511304272827 # Time in different power states
< system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states
---
> system.physmem_1.actEnergy 321201720 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 175258875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 723013200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 482124960 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 74441693340 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1509925753500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1757545814955 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.445422 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2511799542258 # Time in different power states
> system.physmem_1.memoryStateTime::REF 87667060000 # Time in different power states
345c342
< system.physmem_1.memoryStateTime::ACT 26423733173 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 25911565742 # Time in different power states
371,375c368,372
< system.cpu0.branchPred.lookups 51768532 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 23412360 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 919881 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 31255966 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 23302169 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 22612465 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 14651481 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 907853 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 13732961 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 10133003 # Number of BTB hits
377,379c374,376
< system.cpu0.branchPred.BTBHitPct 74.552708 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 15318582 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 29481 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 73.786003 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 3723828 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 29274 # Number of incorrect RAS predictions.
410,462c407,453
< system.cpu0.dtb.walker.walks 62660 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 62660 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24194 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18908 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 19558 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 43102 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 433.564568 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 2585.553866 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-4095 41662 96.66% 96.66% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::4096-8191 436 1.01% 97.67% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::8192-12287 432 1.00% 98.67% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::12288-16383 320 0.74% 99.42% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::16384-20479 76 0.18% 99.59% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::20480-24575 60 0.14% 99.73% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::24576-28671 79 0.18% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::28672-32767 9 0.02% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::32768-36863 4 0.01% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::40960-45055 16 0.04% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::45056-49151 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::49152-53247 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 43102 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 15681 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 9053.791276 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 7430.926564 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 8773.860990 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-16383 14744 94.02% 94.02% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::16384-32767 873 5.57% 99.59% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-49151 41 0.26% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-212991 10 0.06% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::212992-229375 7 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 15681 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 91363987860 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.449877 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.503999 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 91318747860 99.95% 99.95% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 34013000 0.04% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 5422000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 3241000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 1011500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 587500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 452000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::16-17 12000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 91363987860 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 5167 76.75% 76.75% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1565 23.25% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6732 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62660 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walks 61748 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 61748 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23984 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18764 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 19000 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 42748 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 436.289417 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 2694.039371 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-8191 41732 97.62% 97.62% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::8192-16383 726 1.70% 99.32% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::16384-24575 177 0.41% 99.74% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::24576-32767 77 0.18% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.04% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::49152-57343 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 42748 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 15024 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 8664.869276 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 7136.607726 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 7119.581025 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-16383 14229 94.71% 94.71% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::16384-32767 745 4.96% 99.67% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-49151 26 0.17% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.03% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-147455 16 0.11% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 15024 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 87051634064 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.443285 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.503059 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 87007241564 99.95% 99.95% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 33256500 0.04% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 5843000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 2996500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 874000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 581000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 581000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 249500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::16-17 11000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 87051634064 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 5088 77.48% 77.48% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1479 22.52% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 6567 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61748 # Table walker requests started/completed, data/inst
464,465c455,456
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62660 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6732 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61748 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6567 # Table walker requests started/completed, data/inst
467,468c458,459
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6732 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 69392 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6567 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 68315 # Table walker requests started/completed, data/inst
471,474c462,465
< system.cpu0.dtb.read_hits 22710900 # DTB read hits
< system.cpu0.dtb.read_misses 53664 # DTB read misses
< system.cpu0.dtb.write_hits 16914206 # DTB write hits
< system.cpu0.dtb.write_misses 8996 # DTB write misses
---
> system.cpu0.dtb.read_hits 16748968 # DTB read hits
> system.cpu0.dtb.read_misses 52995 # DTB read misses
> system.cpu0.dtb.write_hits 13907664 # DTB write hits
> system.cpu0.dtb.write_misses 8753 # DTB write misses
479,481c470,472
< system.cpu0.dtb.flush_entries 3521 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 84 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 1885 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3489 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 2047 # Number of TLB faults due to prefetch
483,485c474,476
< system.cpu0.dtb.perms_faults 828 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 22764564 # DTB read accesses
< system.cpu0.dtb.write_accesses 16923202 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 843 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 16801963 # DTB read accesses
> system.cpu0.dtb.write_accesses 13916417 # DTB write accesses
487,489c478,480
< system.cpu0.dtb.hits 39625106 # DTB hits
< system.cpu0.dtb.misses 62660 # DTB misses
< system.cpu0.dtb.accesses 39687766 # DTB accesses
---
> system.cpu0.dtb.hits 30656632 # DTB hits
> system.cpu0.dtb.misses 61748 # DTB misses
> system.cpu0.dtb.accesses 30718380 # DTB accesses
519,549c510,537
< system.cpu0.itb.walker.walks 9923 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 9923 # Table walker walks initiated with short descriptors
< system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3743 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6075 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 105 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 9818 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 399.113872 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 2107.706971 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-4095 9439 96.14% 96.14% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::4096-8191 239 2.43% 98.57% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::8192-12287 79 0.80% 99.38% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::12288-16383 28 0.29% 99.66% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::16384-20479 10 0.10% 99.77% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::20480-24575 11 0.11% 99.88% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::28672-32767 5 0.05% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 9818 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 2687 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 10340.528470 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 8874.826622 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 6037.575177 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-8191 928 34.54% 34.54% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::8192-16383 1618 60.22% 94.75% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-24575 45 1.67% 96.43% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.16% 99.59% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walks 9874 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 9874 # Table walker walks initiated with short descriptors
> system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3715 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6056 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 9771 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 366.390339 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 1951.164851 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-4095 9421 96.42% 96.42% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::4096-8191 224 2.29% 98.71% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::8192-12287 80 0.82% 99.53% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::12288-16383 17 0.17% 99.70% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.84% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::20480-24575 5 0.05% 99.89% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::28672-32767 6 0.06% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 9771 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 2691 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 9965.812709 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 8554.132900 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 5681.325139 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-8191 1024 38.05% 38.05% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::8192-16383 1554 57.75% 95.80% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-24575 43 1.60% 97.40% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::24576-32767 63 2.34% 99.74% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-40959 4 0.15% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
551,562c539,550
< system.cpu0.itb.walker.walkCompletionTime::total 2687 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 18349502828 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.974755 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.157116 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 463854500 2.53% 2.53% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 17885129828 97.47% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 423500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 95000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 18349502828 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 2262 87.61% 87.61% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::1M 320 12.39% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 2582 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkCompletionTime::total 2691 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 18106130328 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.976227 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.152552 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 430953000 2.38% 2.38% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 17674714828 97.62% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 401500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 61000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 18106130328 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 2271 87.75% 87.75% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::1M 317 12.25% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
564,565c552,553
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9923 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9874 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9874 # Table walker requests started/completed, data/inst
567,571c555,559
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2582 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 12505 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 70918524 # ITB inst hits
< system.cpu0.itb.inst_misses 9923 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 12462 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 35678798 # ITB inst hits
> system.cpu0.itb.inst_misses 9874 # ITB inst misses
580c568
< system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2368 # Number of entries that have been flushed from TLB
584c572
< system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 1932 # Number of TLB faults due to permissions restrictions
587,591c575,579
< system.cpu0.itb.inst_accesses 70928447 # ITB inst accesses
< system.cpu0.itb.hits 70918524 # DTB hits
< system.cpu0.itb.misses 9923 # DTB misses
< system.cpu0.itb.accesses 70928447 # DTB accesses
< system.cpu0.numCycles 192710246 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 35688672 # ITB inst accesses
> system.cpu0.itb.hits 35678798 # DTB hits
> system.cpu0.itb.misses 9874 # DTB misses
> system.cpu0.itb.accesses 35688672 # DTB accesses
> system.cpu0.numCycles 121733824 # number of cpu cycles simulated
594,610c582,598
< system.cpu0.fetch.icacheStallCycles 19172907 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 190300440 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 51768532 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 38620751 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 166603353 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 5605830 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 133760 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 54794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 348448 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 420234 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 74628 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 70919147 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 257234 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 4157 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 189611039 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 1.227807 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.311092 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 17621783 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 106366119 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 22612465 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 13856831 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 98711813 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 2650530 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 130938 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 54154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 345087 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 416739 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 73296 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 35679429 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 256075 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 4180 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 118679075 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 1.081251 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.263308 # Number of instructions fetched each cycle (Total)
612,615c600,603
< system.cpu0.fetch.rateDist::0 87830492 46.32% 46.32% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 29214542 15.41% 61.73% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 14106780 7.44% 69.17% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 58459225 30.83% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 59721044 50.32% 50.32% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 20146281 16.98% 67.30% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 8259650 6.96% 74.26% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 30552100 25.74% 100.00% # Number of instructions fetched each cycle (Total)
619,665c607,653
< system.cpu0.fetch.rateDist::total 189611039 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.268634 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.987495 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 24427882 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 101305691 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 56642715 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 4754811 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 2479940 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 2942193 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 327073 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 148781526 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 3762312 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 2479940 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 32842566 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 11912016 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 79322122 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 52855770 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 10198625 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 132285921 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 1008096 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 1377906 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 148604 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 51873 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 6170558 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 135790293 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 611071310 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 146878490 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 9376 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 124889963 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 10900327 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 2656202 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 2518524 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 22032615 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 23644678 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 18416726 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1638849 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 2450280 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 129422072 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1660998 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 127592349 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 453825 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 10488941 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 21267672 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 117222 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 189611039 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.672916 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 0.964306 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 118679075 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.185753 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.873760 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 18470879 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 55646585 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 38814384 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 4744194 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 1003033 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 2910392 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 326287 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 104430369 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 3709386 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 1003033 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 23916141 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 11897059 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 33727750 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 37986661 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 10148431 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 99624170 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 979348 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 1380369 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 148421 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 51935 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 6127142 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 103189966 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 455330287 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 114159594 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 9381 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 92428419 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 10761544 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1188796 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 1051388 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 11830283 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 17680232 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 15386939 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1636462 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 2175060 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 96814528 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1636038 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 95024919 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 451413 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 8911325 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 20849804 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 116309 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 118679075 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.800688 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.033122 # Number of insts issued each cycle
667,672c655,660
< system.cpu0.iq.issued_per_cycle::0 115784330 61.06% 61.06% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 32509497 17.15% 78.21% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 29946391 15.79% 94.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 10293248 5.43% 99.43% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1077539 0.57% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 65546472 55.23% 55.23% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 22156727 18.67% 73.90% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 21116341 17.79% 91.69% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 8802658 7.42% 99.11% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1056849 0.89% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 28 0.00% 100.00% # Number of insts issued each cycle
679c667
< system.cpu0.iq.issued_per_cycle::total 189611039 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 118679075 # Number of insts issued each cycle
681,711c669,699
< system.cpu0.iq.fu_full::IntAlu 10302435 44.02% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 127 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 44.02% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 5400760 23.08% 67.10% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 7700326 32.90% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 8808229 40.49% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 130 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.49% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 5336848 24.53% 65.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 7610455 34.98% 100.00% # attempts to use FU when none available
715,745c703,733
< system.cpu0.iq.FU_type_0::IntAlu 86139109 67.51% 67.51% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 105637 0.08% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 7185 0.01% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.60% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 23381898 18.33% 85.93% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 17956248 14.07% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 62565826 65.84% 65.84% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 87588 0.09% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 7159 0.01% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 17417081 18.33% 84.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 14944992 15.73% 100.00% # Type of FU issued
748,756c736,744
< system.cpu0.iq.FU_type_0::total 127592349 # Type of FU issued
< system.cpu0.iq.rate 0.662094 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 23403648 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.183425 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 468620138 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 141579564 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 124128658 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 33072 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 11274 # Number of floating instruction queue writes
---
> system.cpu0.iq.FU_type_0::total 95024919 # Type of FU issued
> system.cpu0.iq.rate 0.780596 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 21755662 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.228947 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 330903688 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 107369307 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 93061278 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 32300 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 11278 # Number of floating instruction queue writes
758,760c746,748
< system.cpu0.iq.int_alu_accesses 150972031 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 21694 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 349342 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.int_alu_accesses 116757282 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 21027 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 347087 # Number of loads that had data forwarded from stores
762,765c750,753
< system.cpu0.iew.lsq.thread0.squashedLoads 1883137 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2543 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 18891 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 974261 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1857425 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2513 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 18755 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 953252 # Number of stores squashed
768,769c756,757
< system.cpu0.iew.lsq.thread0.rescheduledLoads 112825 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 327783 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 101364 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 327888 # Number of times an access to memory failed due to the cache being blocked
771,774c759,762
< system.cpu0.iew.iewSquashCycles 2479940 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 1553148 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 173644 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 131254258 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 1003033 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 1539075 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 172884 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 98621711 # Number of instructions dispatched to IQ
776,787c764,775
< system.cpu0.iew.iewDispLoadInsts 23644678 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 18416726 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 851019 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 17680232 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 15386939 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 849096 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 24467 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 126834 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 18755 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 265533 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 373430 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 638963 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 94008948 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 16992930 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 954343 # Number of squashed instructions skipped in execute
789,797c777,785
< system.cpu0.iew.exec_nop 171188 # number of nop insts executed
< system.cpu0.iew.exec_refs 40733276 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 24565455 # Number of branches executed
< system.cpu0.iew.exec_stores 17777509 # Number of stores executed
< system.cpu0.iew.exec_rate 0.656753 # Inst execution rate
< system.cpu0.iew.wb_sent 126045909 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 124138382 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 63204033 # num instructions producing a value
< system.cpu0.iew.wb_consumers 102166760 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 171145 # number of nop insts executed
> system.cpu0.iew.exec_refs 31760151 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 15805524 # Number of branches executed
> system.cpu0.iew.exec_stores 14767221 # Number of stores executed
> system.cpu0.iew.exec_rate 0.772250 # Inst execution rate
> system.cpu0.iew.wb_sent 93501427 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 93071002 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 48393961 # num instructions producing a value
> system.cpu0.iew.wb_consumers 79995949 # num instructions consuming a value
799,800c787,788
< system.cpu0.iew.wb_rate 0.644171 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.618636 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.764545 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.604955 # average fanout of values written-back
802,807c790,795
< system.cpu0.commit.commitSquashedInsts 9496881 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 1543776 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 596906 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 186488308 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.647310 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.345681 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 7948634 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 1519729 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 585621 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 117035605 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.766100 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.480781 # Number of insts commited each cycle
809,817c797,805
< system.cpu0.commit.committed_per_cycle::0 128655160 68.99% 68.99% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 31929494 17.12% 86.11% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 12238036 6.56% 92.67% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 3079239 1.65% 94.32% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 4650991 2.49% 96.82% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 2566190 1.38% 98.19% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 1394957 0.75% 98.94% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 526048 0.28% 99.22% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1448193 0.78% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 75174289 64.23% 64.23% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 23319780 19.93% 84.16% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 7849886 6.71% 90.86% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 3044520 2.60% 93.47% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 3180912 2.72% 96.18% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 1406827 1.20% 97.39% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 1102407 0.94% 98.33% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 520278 0.44% 98.77% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1436706 1.23% 100.00% # Number of insts commited each cycle
821,823c809,811
< system.cpu0.commit.committed_per_cycle::total 186488308 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 99634335 # Number of instructions committed
< system.cpu0.commit.committedOps 120715819 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 117035605 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 74499569 # Number of instructions committed
> system.cpu0.commit.committedOps 89660931 # Number of ops (including micro ops) committed
825,828c813,816
< system.cpu0.commit.refs 39204006 # Number of memory references committed
< system.cpu0.commit.loads 21761541 # Number of loads committed
< system.cpu0.commit.membars 628761 # Number of memory barriers committed
< system.cpu0.commit.branches 23967170 # Number of branches committed
---
> system.cpu0.commit.refs 30256494 # Number of memory references committed
> system.cpu0.commit.loads 15822807 # Number of loads committed
> system.cpu0.commit.membars 627513 # Number of memory barriers committed
> system.cpu0.commit.branches 15208996 # Number of branches committed
830,831c818,819
< system.cpu0.commit.int_insts 105564175 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 4749359 # Number of function calls committed.
---
> system.cpu0.commit.int_insts 77458658 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 1847857 # Number of function calls committed.
833,863c821,851
< system.cpu0.commit.op_class_0::IntAlu 81401150 67.43% 67.43% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 103478 0.09% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 7185 0.01% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 21761541 18.03% 85.55% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 17442465 14.45% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 59311896 66.15% 66.15% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 85382 0.10% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 7159 0.01% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 15822807 17.65% 83.90% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 14433687 16.10% 100.00% # Class of committed instruction
866,881c854,869
< system.cpu0.commit.op_class_0::total 120715819 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1448193 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 292184577 # The number of ROB reads
< system.cpu0.rob.rob_writes 263546817 # The number of ROB writes
< system.cpu0.timesIdled 122559 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 3099207 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 5058081346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 99512641 # Number of Instructions Simulated
< system.cpu0.committedOps 120594125 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.936540 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.936540 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.516385 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.516385 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 137143613 # number of integer regfile reads
< system.cpu0.int_regfile_writes 78685231 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 8206 # number of floating regfile reads
---
> system.cpu0.commit.op_class_0::total 89660931 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1436706 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 209187674 # The number of ROB reads
> system.cpu0.rob.rob_writes 196861250 # The number of ROB writes
> system.cpu0.timesIdled 121559 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 3054749 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 5129022957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 74377875 # Number of Instructions Simulated
> system.cpu0.committedOps 89539237 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.636694 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.636694 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.610988 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.610988 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 104549028 # number of integer regfile reads
> system.cpu0.int_regfile_writes 56469550 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 8161 # number of floating regfile reads
883,895c871,883
< system.cpu0.cc_regfile_reads 446712527 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 47224279 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 373664445 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 1193481 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 673244 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 484.859625 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 36215686 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 673756 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 53.751931 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 278115000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.859625 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946991 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.946991 # Average percentage of cache occupancy
---
> system.cpu0.cc_regfile_reads 331224109 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 38421528 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 233358199 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 1191250 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 674914 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 486.328727 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 27281228 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 675426 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 40.391143 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 277646000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.328727 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949861 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.949861 # Average percentage of cache occupancy
897,899c885,887
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
901,980c889,968
< system.cpu0.dcache.tags.tag_accesses 77975696 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 77975696 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 20636575 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 20636575 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 14390339 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 14390339 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296451 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 296451 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354772 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 354772 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351523 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 351523 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 35026914 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 35026914 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 35323365 # number of overall hits
< system.cpu0.dcache.overall_hits::total 35323365 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 606585 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 606585 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1800589 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1800589 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141770 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 141770 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24267 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 24267 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21226 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 21226 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2407174 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2407174 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2548944 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2548944 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8152337496 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 8152337496 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26333386263 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 26333386263 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385690944 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 385690944 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485736540 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 485736540 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 421500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 421500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 34485723759 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 34485723759 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 34485723759 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 34485723759 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 21243160 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 21243160 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 16190928 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 16190928 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438221 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 438221 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379039 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 379039 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372749 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 372749 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 37434088 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 37434088 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 37872309 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 37872309 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028554 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.028554 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111210 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.111210 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323513 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323513 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064022 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064022 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056944 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056944 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064304 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.064304 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067304 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.067304 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13439.728144 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13439.728144 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14624.873451 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 14624.873451 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15893.639263 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15893.639263 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22884.035617 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22884.035617 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 60112887 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 60112887 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 14700771 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 14700771 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 11392924 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 11392924 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295732 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 295732 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354072 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 354072 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350987 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 350987 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 26093695 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 26093695 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 26389427 # number of overall hits
> system.cpu0.dcache.overall_hits::total 26389427 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 607182 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 607182 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1803068 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1803068 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141599 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 141599 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24346 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 24346 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21181 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 21181 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 2410250 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 2410250 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 2551849 # number of overall misses
> system.cpu0.dcache.overall_misses::total 2551849 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8154354688 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 8154354688 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26135736531 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 26135736531 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 384171142 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 384171142 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484170513 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 484170513 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 824000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 824000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 34290091219 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 34290091219 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 34290091219 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 34290091219 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 15307953 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 15307953 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 13195992 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 13195992 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437331 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 437331 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378418 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 378418 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372168 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 372168 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 28503945 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 28503945 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 28941276 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 28941276 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039664 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.039664 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136638 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.136638 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323780 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323780 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064336 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064336 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056912 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056912 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084558 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.084558 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088173 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.088173 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13429.836010 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13429.836010 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14495.147455 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 14495.147455 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15779.641091 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15779.641091 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22858.718332 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22858.718332 # average StoreCondReq miss latency
983,992c971,980
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14326.228083 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 14326.228083 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13529.416009 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13529.416009 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 842 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 3715311 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 190617 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.541667 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 19.490974 # average number of cycles each access was blocked
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 3670700 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 191761 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.162791 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 19.142057 # average number of cycles each access was blocked
995,1066c983,1060
< system.cpu0.dcache.writebacks::writebacks 491598 # number of writebacks
< system.cpu0.dcache.writebacks::total 491598 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 240080 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 240080 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1488537 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1488537 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18067 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18067 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1728617 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1728617 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1728617 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1728617 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366505 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 366505 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312052 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 312052 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98413 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 98413 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6200 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6200 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21226 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 21226 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 678557 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 678557 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 776970 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 776970 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4125978302 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4125978302 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5242118761 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5242118761 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570027702 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570027702 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93210251 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93210251 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452955960 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452955960 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 405000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 405000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9368097063 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9368097063 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10938124765 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 10938124765 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5613897000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5613897000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4260937012 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4260937012 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9874834012 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9874834012 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017253 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019273 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019273 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224574 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224574 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016357 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016357 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056944 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056944 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018127 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.018127 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020516 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.020516 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11257.631689 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11257.631689 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16798.862885 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16798.862885 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15953.458405 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.458405 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15033.911452 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15033.911452 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21339.675869 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21339.675869 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 492000 # number of writebacks
> system.cpu0.dcache.writebacks::total 492000 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239081 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 239081 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1490741 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1490741 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18153 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18153 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1729822 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1729822 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1729822 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1729822 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368101 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 368101 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312327 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 312327 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98325 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 98325 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6193 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21181 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 21181 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 680428 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 680428 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 778753 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 778753 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17965 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34679 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4128121038 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4128121038 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5207818329 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5207818329 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570971031 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570971031 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91940502 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91940502 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 451443987 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 451443987 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 794000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 794000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335939367 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 9335939367 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10906910398 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 10906910398 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3693380750 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3693380750 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2688166013 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2688166013 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6381546763 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6381546763 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023668 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023668 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224830 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224830 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016366 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016366 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056912 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056912 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023871 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.023871 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026908 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.026908 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526 # average StoreCondReq mshr miss latency
1069,1078c1063,1072
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13805.910282 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13805.910282 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14077.924199 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14077.924199 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898 # average overall mshr uncacheable latency
1080,1086c1074,1080
< system.cpu0.icache.tags.replacements 1204763 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.748349 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 69666497 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1205275 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 57.801329 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6415532250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748349 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.replacements 1200530 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.748320 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 34431245 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1201042 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 28.667811 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6414143250 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748320 # Average occupied blocks per requestor
1090,1092c1084,1086
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
1094,1134c1088,1128
< system.cpu0.icache.tags.tag_accesses 143036633 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 143036633 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 69666497 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 69666497 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 69666497 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 69666497 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 69666497 # number of overall hits
< system.cpu0.icache.overall_hits::total 69666497 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1249171 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1249171 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1249171 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1249171 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1249171 # number of overall misses
< system.cpu0.icache.overall_misses::total 1249171 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12316352733 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 12316352733 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 12316352733 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 12316352733 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 12316352733 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 12316352733 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 70915668 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 70915668 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 70915668 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 70915668 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 70915668 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 70915668 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017615 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.017615 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017615 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.017615 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017615 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.017615 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.621087 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.621087 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 9859.621087 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 9859.621087 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 1363430 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 975 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 105819 # number of cycles access was blocked
---
> system.cpu0.icache.tags.tag_accesses 72552920 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 72552920 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 34431245 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 34431245 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 34431245 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 34431245 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 34431245 # number of overall hits
> system.cpu0.icache.overall_hits::total 34431245 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1244682 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1244682 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1244682 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1244682 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1244682 # number of overall misses
> system.cpu0.icache.overall_misses::total 1244682 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12221339030 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 12221339030 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 12221339030 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 12221339030 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 12221339030 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 12221339030 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 35675927 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 35675927 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 35675927 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 35675927 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 35675927 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 35675927 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034889 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.034889 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034889 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.034889 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034889 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.034889 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9818.844516 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 9818.844516 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 9818.844516 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 9818.844516 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 1349229 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 432 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 105227 # number of cycles access was blocked
1136,1137c1130,1131
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.884548 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 88.636364 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.822080 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 39.272727 # average number of cycles each access was blocked
1140,1157c1134,1155
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43872 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 43872 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 43872 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 43872 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 43872 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 43872 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1205299 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1205299 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1205299 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1205299 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1205299 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1205299 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10580120186 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 10580120186 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10580120186 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 10580120186 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10580120186 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 10580120186 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43614 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 43614 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 43614 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 43614 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 43614 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 43614 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201068 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1201068 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201068 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1201068 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201068 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1201068 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses
> system.cpu0.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10504795288 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 10504795288 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10504795288 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 10504795288 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10504795288 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 10504795288 # number of overall MSHR miss cycles
1162,1177c1160,1175
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016996 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.016996 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.016996 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8778.004616 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033666 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.033666 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.033666 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8746.211945 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88419.303131 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88419.303131 # average overall mshr uncacheable latency
1179,1181c1177,1179
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762691 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1767870 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 4580 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1764126 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1768652 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 4013 # number of redundant prefetches already in prefetch queue
1184,1211c1182,1209
< system.cpu0.l2cache.prefetcher.pfSpanPage 220490 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 265715 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16040.758095 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 2094535 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 281946 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 7.428852 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 2609861933500 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 9327.683600 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 17.267794 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.026625 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4039.749605 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1610.171801 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1044.858671 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.569317 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001054 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.246567 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.098277 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063773 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.979050 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1077 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15140 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 37 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 401 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 317 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 220332 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 264213 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16022.712569 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 2093032 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 280442 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 7.463333 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 9357.549400 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.830885 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.990255 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3887.194071 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1642.708300 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1121.439658 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.571139 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.237255 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100263 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068447 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.977949 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15194 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 426 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
1213,1257c1211,1254
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4738 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7052 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2870 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065735 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924072 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 41668980 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 41668980 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50191 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11923 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1155240 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.data 372543 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 1589897 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 491596 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 491596 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28444 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 28444 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1603 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 1603 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210600 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 210600 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50191 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11923 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1155240 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 583143 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1800497 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50191 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11923 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1155240 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 583143 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1800497 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 425 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 170 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 50043 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.data 98477 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 149115 # number of ReadReq misses
< system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
< system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27382 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 27382 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19621 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19621 # number of SCUpgradeReq misses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 450 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7327 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2684 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927368 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 41624222 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 41624222 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49855 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11685 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1152127 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.data 374018 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 1587685 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 491993 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 491993 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28477 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 28477 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1602 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 1602 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210193 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 210193 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49855 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11685 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1152127 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 584211 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1797878 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49855 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11685 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1152127 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 584211 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1797878 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 397 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 143 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 48926 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.data 98504 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 147970 # number of ReadReq misses
> system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
> system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27483 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 27483 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19577 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19577 # number of SCUpgradeReq misses
1260,1305c1257,1302
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45870 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 45870 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 425 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 170 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 50043 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 144347 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 194985 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 425 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 170 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 50043 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 144347 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 194985 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11462248 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4075246 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2454493202 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2862988088 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 5333018784 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502169231 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 502169231 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396029410 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396029410 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 393499 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 393499 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2652639758 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2652639758 # number of ReadExReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11462248 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4075246 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2454493202 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 5515627846 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 7985658542 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11462248 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4075246 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2454493202 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 5515627846 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 7985658542 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50616 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12093 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1205283 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.data 471020 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 1739012 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 491597 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 491597 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55826 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 55826 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21224 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 21224 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46426 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 46426 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 397 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 143 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 48926 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 144930 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 194396 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 397 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 143 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 48926 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 144930 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 194396 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10907493 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3478500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2401346947 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2853426397 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 5269159337 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 505786782 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 505786782 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 394596383 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 394596383 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 773499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 773499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2617489063 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2617489063 # number of ReadExReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10907493 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3478500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2401346947 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 5470915460 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 7886648400 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10907493 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3478500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2401346947 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 5470915460 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 7886648400 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50252 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 11828 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1201053 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.data 472522 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 1735655 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 491995 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 491995 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55960 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 55960 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21179 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 21179 # number of SCUpgradeReq accesses(hits+misses)
1308,1330c1305,1327
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256470 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 256470 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50616 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12093 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1205283 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 727490 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1995482 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50616 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12093 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1205283 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 727490 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1995482 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014058 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.041520 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.209072 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.085747 # miss rate for ReadReq accesses
< system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses
< system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.490488 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.490488 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924472 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924472 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256619 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 256619 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50252 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 11828 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1201053 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 729141 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1992274 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50252 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 11828 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1201053 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 729141 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1992274 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012090 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040736 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.208464 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.085253 # miss rate for ReadReq accesses
> system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses
> system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.491119 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.491119 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924359 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924359 # miss rate for SCUpgradeReq accesses
1333,1368c1330,1365
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178851 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178851 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014058 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041520 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198418 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.097713 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014058 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041520 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198418 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.097713 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23972.035294 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49047.683033 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29072.657453 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35764.468927 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18339.391973 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18339.391973 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20183.956475 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20183.956475 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 196749.500000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 196749.500000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57829.512928 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57829.512928 # average ReadExReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 40955.245491 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 40955.245491 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180914 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180914 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012090 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040736 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198768 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.097575 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012090 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040736 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198768 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.097575 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24325.174825 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49081.203184 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28967.619559 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35609.646124 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18403.623404 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18403.623404 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20156.121112 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20156.121112 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 386749.500000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 386749.500000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56379.810085 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56379.810085 # average ReadExReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 40570.013786 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 40570.013786 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked
1370c1367
< system.cpu0.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked
1372c1369
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.400000 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.428571 # average number of cycles each access was blocked
1376,1377c1373,1374
< system.cpu0.l2cache.writebacks::writebacks 193170 # number of writebacks
< system.cpu0.l2cache.writebacks::total 193170 # number of writebacks
---
> system.cpu0.l2cache.writebacks::writebacks 192333 # number of writebacks
> system.cpu0.l2cache.writebacks::total 192333 # number of writebacks
1380,1384c1377,1381
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 27 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 699 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 728 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6075 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 6075 # number of ReadExReq MSHR hits
---
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 734 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 766 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5918 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 5918 # number of ReadExReq MSHR hits
1387,1389c1384,1386
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 27 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6774 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 6803 # number of demand (read+write) MSHR hits
---
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6652 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 6684 # number of demand (read+write) MSHR hits
1392,1407c1389,1404
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 27 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6774 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 6803 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 424 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 169 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 50016 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97778 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 148387 # number of ReadReq MSHR misses
< system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
< system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 232167 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27382 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27382 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19621 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19621 # number of SCUpgradeReq MSHR misses
---
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6652 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 6684 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 396 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 142 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 48896 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97770 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 147204 # number of ReadReq MSHR misses
> system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
> system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 231819 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27483 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27483 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19577 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19577 # number of SCUpgradeReq MSHR misses
1410,1448c1407,1453
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39795 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 39795 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 424 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 169 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50016 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137573 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 188182 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 424 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 169 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50016 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137573 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 420349 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2961750 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2122401548 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2188318454 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4322363002 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15144909271 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 533487187 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 533487187 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293580560 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293580560 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 321999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 321999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1622773486 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1622773486 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2961750 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2122401548 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3811091940 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 5945136488 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2961750 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2122401548 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3811091940 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 21090045759 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40508 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 40508 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 396 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 142 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48896 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138278 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 187712 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 396 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 142 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48896 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138278 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 419531 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20967 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37681 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2542000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2076482303 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2175990950 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4263319752 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15030655008 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 535907154 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 535907154 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292472580 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292472580 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 643499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 643499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1596975176 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1596975176 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2542000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2076482303 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3772966126 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 5860294928 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2542000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2076482303 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3772966126 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 20890949936 # number of overall MSHR miss cycles
1450,1453c1455,1458
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5378380500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5619905250 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4060847435 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4060847435 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3549350250 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3790875000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2559965955 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2559965955 # number of WriteReq MSHR uncacheable cycles
1455,1463c1460,1468
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9439227935 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9680752685 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.207588 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.085328 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
< system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6109316205 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6350840955 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.206911 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.084812 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses
> system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses
1466,1469c1471,1474
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.490488 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.490488 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924472 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924472 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.491119 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.491119 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924359 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924359 # mshr miss rate for SCUpgradeReq accesses
1472,1482c1477,1487
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155164 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155164 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094304 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157853 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157853 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094220 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for overall accesses
1484,1518c1489,1523
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210650 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22380.478778 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29128.987054 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65232.824954 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19483.134431 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19483.134431 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14962.568676 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.568676 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 160999.500000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 160999.500000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40778.326071 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40778.326071 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31592.482214 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50172.703537 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210579 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485 # average overall mshr uncacheable latency
1520,1547c1525,1552
< system.cpu0.toL2Bus.trans_dist::ReadReq 1908189 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1835262 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 26172 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 26172 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 491597 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 299764 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 91875 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43573 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 114693 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 284602 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 270315 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2416584 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2311982 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27986 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112626 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 4869178 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77186016 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82205272 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48372 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202464 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 159642124 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 659500 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 3123483 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 3.174208 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.379288 # Request fanout histogram
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 1907833 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1820754 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 16714 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 491995 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 299768 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 92116 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43624 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 114864 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 284068 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 270286 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2408123 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2274201 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27655 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 111764 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 4821743 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76915296 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82255660 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 47312 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 201008 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 159419276 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 687931 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 3186793 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 1.203876 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.402878 # Request fanout histogram
1550,1553c1555,1556
< system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::3 2579348 82.58% 82.58% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::4 544135 17.42% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::1 2537081 79.61% 79.61% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 649712 20.39% 100.00% # Request fanout histogram
1555,1558c1558,1561
< system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::total 3123483 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 1823730646 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::total 3186793 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 1807599924 # Layer occupancy (ticks)
1560c1563
< system.cpu0.toL2Bus.snoopLayer0.occupancy 112580498 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 112679999 # Layer occupancy (ticks)
1562c1565
< system.cpu0.toL2Bus.respLayer0.occupancy 1815085939 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1808718407 # Layer occupancy (ticks)
1564c1567
< system.cpu0.toL2Bus.respLayer1.occupancy 1180413157 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1166698241 # Layer occupancy (ticks)
1566c1569
< system.cpu0.toL2Bus.respLayer2.occupancy 15906731 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # Layer occupancy (ticks)
1568c1571
< system.cpu0.toL2Bus.respLayer3.occupancy 62058933 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks)
1570,1574c1573,1577
< system.cpu1.branchPred.lookups 6179090 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 3881916 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 362855 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 3346788 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 2458848 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 35319893 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 12619406 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits
1576,1578c1579,1581
< system.cpu1.branchPred.BTBHitPct 73.468890 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 1048082 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 10606 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 79.617709 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 12648833 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 10709 # Number of incorrect RAS predictions.
1608,1624c1611,1627
< system.cpu1.dtb.walker.walks 24514 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 24514 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11457 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6002 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 7055 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 17459 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 393.464689 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 2513.400268 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-4095 16937 97.01% 97.01% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::4096-8191 156 0.89% 97.90% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::8192-12287 187 1.07% 98.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::12288-16383 85 0.49% 99.46% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::16384-20479 23 0.13% 99.59% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::20480-24575 6 0.03% 99.63% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::24576-28671 44 0.25% 99.88% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::28672-32767 3 0.02% 99.90% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.98% # Table walker wait (enqueue to first request) latency
---
> system.cpu1.dtb.walker.walks 24259 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 24259 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11332 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6025 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 6902 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 17357 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 400.040330 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 2564.899375 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-4095 16829 96.96% 96.96% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::4096-8191 181 1.04% 98.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::8192-12287 173 1.00% 99.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::12288-16383 71 0.41% 99.41% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.16% 99.57% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::20480-24575 5 0.03% 99.60% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::24576-28671 45 0.26% 99.86% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::28672-32767 6 0.03% 99.89% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.97% # Table walker wait (enqueue to first request) latency
1626c1629
< system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
---
> system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1629,1665c1632,1666
< system.cpu1.dtb.walker.walkWaitTime::total 17459 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 5476 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 9377.190285 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 8039.034346 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 5934.391980 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-8191 2488 45.43% 45.43% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2481 45.31% 90.74% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-24575 381 6.96% 97.70% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::24576-32767 96 1.75% 99.45% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-40959 6 0.11% 99.56% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::40960-49151 20 0.37% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 5476 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 69614954880 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.366193 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.484439 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 44157971700 63.43% 63.43% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 25439149180 36.54% 99.97% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2 11249000 0.02% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::3 3199000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4 940000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::5 768000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6 744500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::7 290500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8 107000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::9 122500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::10 85500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::11 64000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12 71500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::13 26500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14 31000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::15 135000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 69614954880 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 1964 73.78% 73.78% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 698 26.22% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2662 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24514 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkWaitTime::total 17357 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 5295 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 9383.568650 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 7860.112601 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 8293.617199 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-32767 5259 99.32% 99.32% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-65535 29 0.55% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.06% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::163840-196607 3 0.06% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 5295 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 69596834880 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.389063 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.490087 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 42554298056 61.14% 61.14% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::1 27024786824 38.83% 99.97% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2 11219000 0.02% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::3 3252000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4 913000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::5 701500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6 719000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::7 299000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8 99500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::9 182000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::10 50000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::11 63500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12 106500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 69596834880 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1939 74.63% 74.63% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 659 25.37% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24259 # Table walker requests started/completed, data/inst
1667,1668c1668,1669
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24514 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2662 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24259 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst
1670,1671c1671,1672
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2662 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 27176 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 26857 # Table walker requests started/completed, data/inst
1674,1677c1675,1678
< system.cpu1.dtb.read_hits 5241297 # DTB read hits
< system.cpu1.dtb.read_misses 21288 # DTB read misses
< system.cpu1.dtb.write_hits 4318497 # DTB write hits
< system.cpu1.dtb.write_misses 3226 # DTB write misses
---
> system.cpu1.dtb.read_hits 11166498 # DTB read hits
> system.cpu1.dtb.read_misses 21069 # DTB read misses
> system.cpu1.dtb.write_hits 7306223 # DTB write hits
> system.cpu1.dtb.write_misses 3190 # DTB write misses
1682,1684c1683,1685
< system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 72 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 621 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 2022 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 70 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 623 # Number of TLB faults due to prefetch
1686,1688c1687,1689
< system.cpu1.dtb.perms_faults 379 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 5262585 # DTB read accesses
< system.cpu1.dtb.write_accesses 4321723 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 374 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 11187567 # DTB read accesses
> system.cpu1.dtb.write_accesses 7309413 # DTB write accesses
1690,1692c1691,1693
< system.cpu1.dtb.hits 9559794 # DTB hits
< system.cpu1.dtb.misses 24514 # DTB misses
< system.cpu1.dtb.accesses 9584308 # DTB accesses
---
> system.cpu1.dtb.hits 18472721 # DTB hits
> system.cpu1.dtb.misses 24259 # DTB misses
> system.cpu1.dtb.accesses 18496980 # DTB accesses
1722,1760c1723,1758
< system.cpu1.itb.walker.walks 6863 # Table walker walks requested
< system.cpu1.itb.walker.walksShort 6863 # Table walker walks initiated with short descriptors
< system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4096 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2697 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksSquashedBefore 70 # Table walks squashed before starting
< system.cpu1.itb.walker.walkWaitTime::samples 6793 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 193.655233 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 1558.039702 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-2047 6647 97.85% 97.85% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::2048-4095 36 0.53% 98.38% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 98.79% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::6144-8191 24 0.35% 99.15% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::8192-10239 16 0.24% 99.38% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::10240-12287 12 0.18% 99.56% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::12288-14335 8 0.12% 99.68% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.07% 99.75% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::16384-18431 3 0.04% 99.79% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.04% 99.84% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.87% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.06% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::30720-32767 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 6793 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 1235 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 10095.547368 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 8796.441001 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5908.625766 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-4095 181 14.66% 14.66% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.17% 28.83% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-12287 552 44.70% 73.52% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::12288-16383 256 20.73% 94.25% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.57% 94.82% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::20480-24575 7 0.57% 95.38% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.27% 97.65% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::28672-32767 18 1.46% 99.11% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.24% 99.35% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.40% 99.76% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.16% 99.92% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walks 6817 # Table walker walks requested
> system.cpu1.itb.walker.walksShort 6817 # Table walker walks initiated with short descriptors
> system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4075 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2679 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting
> system.cpu1.itb.walker.walkWaitTime::samples 6754 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 138.510512 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 1194.021921 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-2047 6631 98.18% 98.18% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::2048-4095 35 0.52% 98.70% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 99.11% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::6144-8191 28 0.41% 99.53% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::8192-10239 11 0.16% 99.69% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::10240-12287 8 0.12% 99.81% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.87% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::14336-16383 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::26624-28671 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 6754 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 1229 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 9949.958503 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 8666.714001 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5833.930601 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-4095 208 16.92% 16.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.24% 31.16% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 520 42.31% 73.47% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 258 20.99% 94.47% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-20479 10 0.81% 95.28% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.24% 95.52% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.44% 97.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.30% 99.27% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.16% 99.43% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.41% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
1762,1773c1760,1770
< system.cpu1.itb.walker.walkCompletionTime::total 1235 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 18043801328 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.988843 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.105174 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 201557764 1.12% 1.12% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 17842013064 98.88% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 213500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::3 17000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 18043801328 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walkCompletionTime::total 1229 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 18026373328 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.989122 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.103762 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 196149764 1.09% 1.09% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 17830158064 98.91% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 65500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 18026373328 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 995 85.33% 85.33% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::1M 171 14.67% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 1166 # Table walker page sizes translated
1775,1776c1772,1773
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6863 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6863 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6817 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6817 # Table walker requests started/completed, data/inst
1778,1782c1775,1779
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 8028 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 10532607 # ITB inst hits
< system.cpu1.itb.inst_misses 6863 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1166 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1166 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 7983 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 45723303 # ITB inst hits
> system.cpu1.itb.inst_misses 6817 # ITB inst misses
1791c1788
< system.cpu1.itb.flush_entries 1195 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB
1795c1792
< system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 537 # Number of TLB faults due to permissions restrictions
1798,1802c1795,1799
< system.cpu1.itb.inst_accesses 10539470 # ITB inst accesses
< system.cpu1.itb.hits 10532607 # DTB hits
< system.cpu1.itb.misses 6863 # DTB misses
< system.cpu1.itb.accesses 10539470 # DTB accesses
< system.cpu1.numCycles 43132973 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 45730120 # ITB inst accesses
> system.cpu1.itb.hits 45723303 # DTB hits
> system.cpu1.itb.misses 6817 # DTB misses
> system.cpu1.itb.accesses 45730120 # DTB accesses
> system.cpu1.numCycles 113567718 # number of cpu cycles simulated
1805,1821c1802,1818
< system.cpu1.fetch.icacheStallCycles 9545781 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 31669827 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 6179090 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 3506930 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 31408441 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 995212 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 85708 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 38872 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 217286 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 331419 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 27804 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 10531999 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 133008 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 2352 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 42152917 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.913975 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.225517 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 35319893 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 84431 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 39920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 219438 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 325443 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 27387 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 45722696 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 133886 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 2307 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 112589057 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.268755 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.334526 # Number of instructions fetched each cycle (Total)
1823,1826c1820,1823
< system.cpu1.fetch.rateDist::0 24362526 57.80% 57.80% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 6315176 14.98% 72.78% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 2214119 5.25% 78.03% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 9261096 21.97% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 52059388 46.24% 46.24% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 15346880 13.63% 59.87% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 8047278 7.15% 67.02% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 37135511 32.98% 100.00% # Number of instructions fetched each cycle (Total)
1830,1876c1827,1873
< system.cpu1.fetch.rateDist::total 42152917 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.143257 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.734237 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 8274124 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 20645023 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 11553748 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 1337865 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 342157 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 880050 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 158552 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 30233981 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 1392367 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 342157 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 10058392 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 2609511 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 14923378 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 11073163 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 3146316 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 28748329 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 284293 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 329352 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 50565 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 19779 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 1931384 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 29150261 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 132893523 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 32973401 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 1672 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 25705063 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 3445198 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 453540 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 375844 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 3445196 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 5586646 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 4747027 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 699100 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 721726 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 27759685 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 627473 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 27258527 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 145234 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 2977146 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 6943190 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 53970 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 42152917 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.646658 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 0.966330 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 112589057 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.311003 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.016533 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 14201102 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 65884249 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 29361473 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 1323272 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 1818961 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 906595 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 159892 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 74422628 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 1448245 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 1818961 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 18946447 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 2582249 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 60294532 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 25904145 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 3042723 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 61245605 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 312742 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 326990 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 51393 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 18938 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 1837973 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 61569183 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 287884146 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 65513638 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 58022651 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 3546532 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 1914472 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 1838523 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 13613893 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 11512865 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 7756589 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 697877 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 945772 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 60208856 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 646860 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 59677362 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 148586 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 4522679 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 7282133 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 53722 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 112589057 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.530046 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 0.866401 # Number of insts issued each cycle
1878,1882c1875,1879
< system.cpu1.iq.issued_per_cycle::0 26379254 62.58% 62.58% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 7348926 17.43% 80.01% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 5684884 13.49% 93.50% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 2419597 5.74% 99.24% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 320238 0.76% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 76211299 67.69% 67.69% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 17665370 15.69% 83.38% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 14473056 12.85% 96.23% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 3891466 3.46% 99.69% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 347848 0.31% 100.00% # Number of insts issued each cycle
1890c1887
< system.cpu1.iq.issued_per_cycle::total 42152917 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 112589057 # Number of insts issued each cycle
1892,1922c1889,1919
< system.cpu1.iq.fu_full::IntAlu 2004888 32.52% 32.52% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 611 0.01% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 1891782 30.69% 63.22% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 2267092 36.78% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 3478019 44.85% 44.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 614 0.01% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.86% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 1940620 25.03% 69.89% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 2334930 30.11% 100.00% # attempts to use FU when none available
1926,1956c1923,1953
< system.cpu1.iq.FU_type_0::IntAlu 17154225 62.93% 62.93% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 35391 0.13% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 4079 0.01% 63.08% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 5491685 20.15% 83.22% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 4573079 16.78% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 40635841 68.09% 68.09% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 52797 0.09% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 4119 0.01% 68.19% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 11419177 19.13% 87.32% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 7565361 12.68% 100.00% # Type of FU issued
1959,1971c1956,1968
< system.cpu1.iq.FU_type_0::total 27258527 # Type of FU issued
< system.cpu1.iq.rate 0.631965 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 6164373 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.226145 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 102973934 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 31372858 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 26623969 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 5644 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 2050 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 33419259 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 3574 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 107638 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 59677362 # Type of FU issued
> system.cpu1.iq.rate 0.525478 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 7754183 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.129935 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 239840869 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 65386915 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 57545759 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 5681 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 67427880 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 3598 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 109848 # Number of loads that had data forwarded from stores
1973,1976c1970,1973
< system.cpu1.iew.lsq.thread0.squashedLoads 606025 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 849 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 10642 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 402770 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 624171 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 851 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 10604 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 419293 # Number of stores squashed
1979,1980c1976,1977
< system.cpu1.iew.lsq.thread0.rescheduledLoads 45923 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 97906 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 57328 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 95447 # Number of times an access to memory failed due to the cache being blocked
1982,1985c1979,1982
< system.cpu1.iew.iewSquashCycles 342157 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 666539 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 117242 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 28442190 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 1818961 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 659321 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 119824 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 60910908 # Number of instructions dispatched to IQ
1987,1998c1984,1995
< system.cpu1.iew.iewDispLoadInsts 5586646 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 4747027 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 329140 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 12736 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 94970 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 10642 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 72014 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 152187 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 224201 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 26920844 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 5360548 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 313188 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 11512865 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 7756589 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 325462 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 12815 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 97459 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 10604 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 81282 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 152799 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 234081 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 59327650 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 11286961 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 325473 # Number of squashed instructions skipped in execute
2000,2008c1997,2005
< system.cpu1.iew.exec_nop 55032 # number of nop insts executed
< system.cpu1.iew.exec_refs 9857010 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 4125375 # Number of branches executed
< system.cpu1.iew.exec_stores 4496462 # Number of stores executed
< system.cpu1.iew.exec_rate 0.624136 # Inst execution rate
< system.cpu1.iew.wb_sent 26746276 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 26625754 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 13483465 # num instructions producing a value
< system.cpu1.iew.wb_consumers 21315020 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 55192 # number of nop insts executed
> system.cpu1.iew.exec_refs 18774109 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 12866831 # Number of branches executed
> system.cpu1.iew.exec_stores 7487148 # Number of stores executed
> system.cpu1.iew.exec_rate 0.522399 # Inst execution rate
> system.cpu1.iew.wb_sent 59146208 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 57547543 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 28211344 # num instructions producing a value
> system.cpu1.iew.wb_consumers 43350974 # num instructions consuming a value
2010,2011c2007,2008
< system.cpu1.iew.wb_rate 0.617295 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.632580 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.506724 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.650766 # average fanout of values written-back
2013,2018c2010,2015
< system.cpu1.commit.commitSquashedInsts 2680688 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 573503 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 207406 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 41589167 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.611775 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.358099 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 4198450 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 593138 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 217301 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 110549070 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.509875 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.177384 # Number of insts commited each cycle
2020,2028c2017,2025
< system.cpu1.commit.committed_per_cycle::0 29454101 70.82% 70.82% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 7064012 16.99% 87.81% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 2119517 5.10% 92.90% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 873586 2.10% 95.00% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 770133 1.85% 96.86% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 442153 1.06% 97.92% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 274514 0.66% 98.58% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 148169 0.36% 98.93% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 442982 1.07% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 82464476 74.60% 74.60% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 15679600 14.18% 88.78% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 6499039 5.88% 94.66% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 896756 0.81% 95.47% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 2234307 2.02% 97.49% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 1661965 1.50% 98.99% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 498497 0.45% 99.44% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 155172 0.14% 99.58% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 459258 0.42% 100.00% # Number of insts commited each cycle
2032,2034c2029,2031
< system.cpu1.commit.committed_per_cycle::total 41589167 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 20860008 # Number of instructions committed
< system.cpu1.commit.committedOps 25443224 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 110549070 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 45875888 # Number of instructions committed
> system.cpu1.commit.committedOps 56366249 # Number of ops (including micro ops) committed
2036,2039c2033,2036
< system.cpu1.commit.refs 9324878 # Number of memory references committed
< system.cpu1.commit.loads 4980621 # Number of loads committed
< system.cpu1.commit.membars 230323 # Number of memory barriers committed
< system.cpu1.commit.branches 3917567 # Number of branches committed
---
> system.cpu1.commit.refs 18225990 # Number of memory references committed
> system.cpu1.commit.loads 10888694 # Number of loads committed
> system.cpu1.commit.membars 231720 # Number of memory barriers committed
> system.cpu1.commit.branches 12659864 # Number of branches committed
2041,2042c2038,2039
< system.cpu1.commit.int_insts 22363157 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 552505 # Number of function calls committed.
---
> system.cpu1.commit.int_insts 50354679 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 3453612 # Number of function calls committed.
2044,2074c2041,2071
< system.cpu1.commit.op_class_0::IntAlu 16079933 63.20% 63.20% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 34334 0.13% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.33% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 4079 0.02% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 4980621 19.58% 82.93% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 4344257 17.07% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 38084418 67.57% 67.57% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 51722 0.09% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.66% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.67% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.67% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.67% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.67% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 10888694 19.32% 86.98% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 7337296 13.02% 100.00% # Class of committed instruction
2077,2107c2074,2104
< system.cpu1.commit.op_class_0::total 25443224 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 442982 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 68115809 # The number of ROB reads
< system.cpu1.rob.rob_writes 56808236 # The number of ROB writes
< system.cpu1.timesIdled 67589 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 980056 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 5207108948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 20826795 # Number of Instructions Simulated
< system.cpu1.committedOps 25410011 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 2.071033 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 2.071033 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.482851 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.482851 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 30054591 # number of integer regfile reads
< system.cpu1.int_regfile_writes 16942565 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 1393 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 518 # number of floating regfile writes
< system.cpu1.cc_regfile_reads 96178951 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 9490884 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 81077063 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 422777 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 228827 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 478.548130 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 8439386 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 229141 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 36.830537 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 103436351500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.548130 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934664 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.934664 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
---
> system.cpu1.commit.op_class_0::total 56366249 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 459258 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 150434096 # The number of ROB reads
> system.cpu1.rob.rob_writes 123166009 # The number of ROB writes
> system.cpu1.timesIdled 67345 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 978661 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 5136638072 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 45842675 # Number of Instructions Simulated
> system.cpu1.committedOps 56333036 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 2.477336 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 2.477336 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.403659 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.403659 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 62490093 # number of integer regfile reads
> system.cpu1.int_regfile_writes 39068646 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
> system.cpu1.cc_regfile_reads 211116899 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 18233735 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 220514092 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 421035 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 227457 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 483.345523 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 17322126 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 227768 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 76.051623 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 89024511500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.345523 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.944034 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.944034 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
2109,2190c2106,2187
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 18658844 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 18658844 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 4567362 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 4567362 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3580643 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3580643 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63652 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 63652 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87547 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 87547 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79571 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 79571 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 8148005 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 8148005 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 8211657 # number of overall hits
< system.cpu1.dcache.overall_hits::total 8211657 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 253908 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 253908 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 480072 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 480072 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 36130 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 36130 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19184 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 19184 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23489 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23489 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 733980 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 733980 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 770110 # number of overall misses
< system.cpu1.dcache.overall_misses::total 770110 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4026677920 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 4026677920 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11127636122 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 11127636122 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 374723986 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 374723986 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547048827 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 547048827 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1003000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1003000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 15154314042 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 15154314042 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 15154314042 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 15154314042 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 4821270 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 4821270 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 4060715 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4060715 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99782 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 99782 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106731 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 106731 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103060 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 103060 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 8881985 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 8881985 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 8981767 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 8981767 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.052664 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.052664 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118224 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.118224 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.362089 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.362089 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179742 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179742 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227916 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227916 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.082637 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.082637 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.085741 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.085741 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15858.806812 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15858.806812 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23179.098389 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 23179.098389 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19533.151897 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19533.151897 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23289.574993 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23289.574993 # average StoreCondReq miss latency
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 36423981 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 36423981 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 10467087 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 10467087 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 6561195 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 6561195 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65021 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 65021 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88659 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 88659 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80691 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 80691 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 17028282 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 17028282 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 17093303 # number of overall hits
> system.cpu1.dcache.overall_hits::total 17093303 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 254533 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 254533 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 479063 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 479063 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35844 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 35844 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19098 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 19098 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23509 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23509 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 733596 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 733596 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 769440 # number of overall misses
> system.cpu1.dcache.overall_misses::total 769440 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3958996431 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3958996431 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10579018157 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 10579018157 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 370185734 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 370185734 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549251321 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 549251321 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 798500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 798500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 14538014588 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 14538014588 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 14538014588 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 14538014588 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 10721620 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 10721620 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 7040258 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 7040258 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100865 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 100865 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107757 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 107757 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104200 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 104200 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 17761878 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 17761878 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 17862743 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 17862743 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023740 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.023740 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.068046 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.068046 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.355366 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.355366 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177232 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177232 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225614 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225614 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041302 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043075 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.043075 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15553.961298 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15553.961298 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22082.728487 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 22082.728487 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19383.481726 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19383.481726 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23363.448934 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23363.448934 # average StoreCondReq miss latency
2193,2202c2190,2199
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20646.766999 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20646.766999 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19678.116168 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 19678.116168 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 1600979 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 49143 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.363636 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 32.577966 # average number of cycles each access was blocked
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19817.467091 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 19817.467091 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18894.279720 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 18894.279720 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 393 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 1480475 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 42 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 48784 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.357143 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 30.347552 # average number of cycles each access was blocked
2205,2276c2202,2279
< system.cpu1.dcache.writebacks::writebacks 137785 # number of writebacks
< system.cpu1.dcache.writebacks::total 137785 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 90105 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 90105 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375217 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 375217 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13775 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13775 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 465322 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 465322 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 465322 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 465322 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163803 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 163803 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104855 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 104855 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32523 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 32523 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5409 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5409 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23489 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23489 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 268658 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 268658 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 301181 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 301181 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2171865461 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2171865461 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2612489394 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2612489394 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 519825898 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 519825898 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98469253 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98469253 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 510672173 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 510672173 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 974500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 974500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4784354855 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4784354855 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5304180753 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5304180753 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 979094500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 979094500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848774501 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848774501 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827869001 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827869001 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033975 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033975 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025822 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025822 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.325941 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.325941 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050679 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050679 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227916 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227916 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030248 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.030248 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033532 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13259.009060 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13259.009060 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24915.258157 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24915.258157 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15983.331734 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15983.331734 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18204.705676 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18204.705676 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21740.907361 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21740.907361 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 138868 # number of writebacks
> system.cpu1.dcache.writebacks::total 138868 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91268 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 91268 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375164 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 375164 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13545 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13545 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 466432 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 466432 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 466432 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 466432 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163265 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 163265 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103899 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 103899 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32275 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 32275 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5553 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5553 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23509 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23509 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 267164 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 267164 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 299439 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 299439 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17059 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31400 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2133861458 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2133861458 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2484196176 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2484196176 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 503074190 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 503074190 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95947255 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95947255 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 512832179 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 512832179 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 777500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 777500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4618057634 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4618057634 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5121131824 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 5121131824 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2900210250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2900210250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2419067503 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2419067503 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5319277753 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5319277753 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015228 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015228 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014758 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014758 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319982 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319982 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051533 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051533 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225614 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225614 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015041 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.015041 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016763 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.016763 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13069.925936 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13069.925936 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23909.721711 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23909.721711 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15587.116654 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15587.116654 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17278.453989 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17278.453989 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21814.291505 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21814.291505 # average StoreCondReq mshr miss latency
2279,2288c2282,2291
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17808.346876 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17808.346876 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17611.272799 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17611.272799 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17285.478710 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17285.478710 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17102.420940 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17102.420940 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170010.566270 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170010.566270 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168681.926156 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168681.926156 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169403.750096 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169403.750096 # average overall mshr uncacheable latency
2290,2298c2293,2301
< system.cpu1.icache.tags.replacements 667401 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.527528 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 9840970 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 667913 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 14.733910 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 78865217000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.527528 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973687 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.973687 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 671809 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.529348 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 45027049 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 672321 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 66.972546 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 78856865000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.529348 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973690 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.973690 # Average percentage of cache occupancy
2300,2301c2303,2304
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
2303,2341c2306,2344
< system.cpu1.icache.tags.tag_accesses 21731377 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 21731377 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 9840970 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 9840970 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 9840970 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 9840970 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 9840970 # number of overall hits
< system.cpu1.icache.overall_hits::total 9840970 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 690756 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 690756 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 690756 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 690756 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 690756 # number of overall misses
< system.cpu1.icache.overall_misses::total 690756 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6328356335 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 6328356335 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 6328356335 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 6328356335 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 6328356335 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 6328356335 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 10531726 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 10531726 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 10531726 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 10531726 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 10531726 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 10531726 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065588 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.065588 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065588 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.065588 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065588 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.065588 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9161.493110 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9161.493110 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9161.493110 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9161.493110 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 590927 # number of cycles access was blocked
---
> system.cpu1.icache.tags.tag_accesses 92117192 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 92117192 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 45027049 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 45027049 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 45027049 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 45027049 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 45027049 # number of overall hits
> system.cpu1.icache.overall_hits::total 45027049 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 695384 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 695384 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 695384 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 695384 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 695384 # number of overall misses
> system.cpu1.icache.overall_misses::total 695384 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6371214084 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 6371214084 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 6371214084 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 6371214084 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 6371214084 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 6371214084 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 45722433 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 45722433 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 45722433 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 45722433 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 45722433 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 45722433 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015209 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.015209 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015209 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.015209 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015209 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.015209 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9162.152255 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 9162.152255 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 9162.152255 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 9162.152255 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 596666 # number of cycles access was blocked
2343c2346
< system.cpu1.icache.blocked::no_mshrs 49303 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 49414 # number of cycles access was blocked
2345c2348
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.985620 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.074837 # average number of cycles each access was blocked
2349,2386c2352,2393
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22831 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 22831 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 22831 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 22831 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 22831 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 22831 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 667925 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 667925 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 667925 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 667925 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 667925 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 667925 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5443930957 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5443930957 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5443930957 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5443930957 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5443930957 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5443930957 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8774500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8774500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8774500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 8774500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063420 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.063420 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.063420 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8150.512343 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23058 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 23058 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 23058 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 23058 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 23058 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 23058 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672326 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 672326 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 672326 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 672326 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 672326 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 672326 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.ReadReq_mshr_uncacheable::total 100 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses
> system.cpu1.icache.overall_mshr_uncacheable_misses::total 100 # number of overall MSHR uncacheable misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5482686465 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5482686465 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5482686465 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5482686465 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5482686465 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5482686465 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8677000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8677000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8677000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 8677000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014705 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.014705 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.014705 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8154.803570 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86770 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86770 # average overall mshr uncacheable latency
2388,2390c2395,2397
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 270002 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 271052 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 936 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 264317 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 265106 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 699 # number of redundant prefetches already in prefetch queue
2393,2398c2400,2405
< system.cpu1.l2cache.prefetcher.pfSpanPage 67932 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 66588 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15581.068012 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 931760 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 81198 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 11.475159 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 68110 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 61852 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15537.791452 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 937119 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 76426 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 12.261783 # Average number of references to valid blocks.
2400,2564c2407,2577
< system.cpu1.l2cache.tags.occ_blocks::writebacks 6676.895279 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 16.747734 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010823 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4682.837977 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2664.181165 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.395034 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.407525 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001022 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285818 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.162609 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093896 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.950993 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1283 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13300 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 906 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 364 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 471 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8616 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4213 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078308 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001648 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811768 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 18862163 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 18862163 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19502 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7394 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 645640 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.data 128208 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 800744 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 137784 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 137784 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2324 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 2324 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 1121 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38121 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 38121 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19502 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7394 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 645640 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 166329 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 838865 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19502 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7394 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 645640 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 166329 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 838865 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 440 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 275 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22267 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.data 73501 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 96483 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29168 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29168 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22368 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22368 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35878 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 35878 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 440 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 275 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 22267 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 109379 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 132361 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 440 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 275 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 22267 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 109379 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 132361 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9737996 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5511500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 907046728 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1743519842 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 2665816066 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555344240 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 555344240 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449490983 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449490983 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 955500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 955500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1553872219 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1553872219 # number of ReadExReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9737996 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5511500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 907046728 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3297392061 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 4219688285 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9737996 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5511500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 907046728 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3297392061 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 4219688285 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19942 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7669 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 667907 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201709 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 897227 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 137784 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 137784 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31492 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 31492 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23489 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23489 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73999 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 73999 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19942 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7669 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 667907 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 275708 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 971226 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19942 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7669 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 667907 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 275708 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 971226 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035859 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.033338 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.364391 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.107535 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926203 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926203 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952276 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952276 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484844 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484844 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035859 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033338 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.396720 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.136282 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035859 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033338 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.396720 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.136282 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20041.818182 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 40735.021691 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23721.035659 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27629.904398 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19039.503566 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19039.503566 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20095.269269 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20095.269269 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43309.889598 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43309.889598 # average ReadExReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 31880.148118 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 31880.148118 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 6612.049075 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.719968 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.202712 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4939.798550 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2550.027939 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1417.993208 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.403567 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000959 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000134 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301501 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.155641 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086547 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.948352 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1249 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 36 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13289 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 16 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 878 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 355 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8497 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4330 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076233 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002197 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811096 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 18910778 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 18910778 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19107 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7219 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 650283 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.data 128648 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 805257 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 138868 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 138868 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1925 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1925 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1050 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 1050 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38271 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 38271 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19107 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7219 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 650283 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 166919 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 843528 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19107 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7219 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 650283 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 166919 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 843528 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 427 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22038 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.data 72420 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 95161 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29112 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29112 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22458 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22458 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35228 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 35228 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 427 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 22038 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 107648 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 130389 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 427 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 22038 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 107648 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 130389 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9785994 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5538750 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 913296236 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1683125409 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 2611746389 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 548231087 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 548231087 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449027944 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449027944 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 763500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 763500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429440182 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1429440182 # number of ReadExReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9785994 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5538750 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 913296236 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3112565591 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 4041186571 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9785994 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5538750 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 913296236 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3112565591 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 4041186571 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19534 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7495 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 672321 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201068 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 900418 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 138868 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 138868 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31037 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 31037 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23508 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23508 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73499 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 73499 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19534 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7495 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 672321 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 274567 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 973917 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19534 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7495 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 672321 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 274567 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 973917 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036825 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.032779 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.360177 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.105685 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.937977 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937977 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955334 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955334 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.479299 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.479299 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036825 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032779 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392065 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.133881 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036825 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032779 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392065 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.133881 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20067.934783 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 41441.883837 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23241.168310 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27445.554261 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18831.790567 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18831.790567 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19994.119868 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19994.119868 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 763500 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 763500 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40576.819064 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40576.819064 # average ReadExReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 30993.309029 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 30993.309029 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 61 # number of cycles access was blocked
2566c2579
< system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
2568c2581
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 12.200000 # average number of cycles each access was blocked
2572,2573c2585,2586
< system.cpu1.l2cache.writebacks::writebacks 39082 # number of writebacks
< system.cpu1.l2cache.writebacks::total 39082 # number of writebacks
---
> system.cpu1.l2cache.writebacks::writebacks 35144 # number of writebacks
> system.cpu1.l2cache.writebacks::total 35144 # number of writebacks
2576,2580c2589,2593
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 149 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 867 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 867 # number of ReadExReq MSHR hits
---
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 141 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 736 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 736 # number of ReadExReq MSHR hits
2583,2585c2596,2598
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1016 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits
---
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 877 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 907 # number of demand (read+write) MSHR hits
2588,2653c2601,2676
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1016 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 1048 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 439 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22249 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 73352 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 96302 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 37405 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29168 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29168 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22368 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22368 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35011 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 35011 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 439 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22249 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108363 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 131313 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 439 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22249 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108363 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 168718 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3646000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 759958022 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1259838411 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 2030303933 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619373742 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484903709 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484903709 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 334604857 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 334604857 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 832000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 832000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1217604967 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1217604967 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3646000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 759958022 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2477443378 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 3247908900 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3646000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 759958022 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2477443378 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4867282642 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7975000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 934007000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941982000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811858998 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811858998 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7975000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1745865998 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1753840998 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.363653 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.107333 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 877 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 907 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 426 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 263 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22022 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72279 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 94990 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 36425 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29112 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29112 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22458 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22458 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34492 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 34492 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 426 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 263 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22022 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106771 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 129482 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 426 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 263 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22022 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106771 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 165907 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17159 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31500 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3664750 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 767719764 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1208019590 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1986398104 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1404338548 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484116716 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484116716 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 336604833 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 336604833 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 672500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 672500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121552915 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121552915 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3664750 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 767719764 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2329572505 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 3107951019 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3664750 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 767719764 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2329572505 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4512289567 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7885000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2763450750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2771335750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2311397498 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2311397498 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7885000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5074848248 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5082733248 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.359475 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.105495 # mshr miss rate for ReadReq accesses
2656,2670c2679,2695
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926203 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926203 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952276 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952276 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.473128 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.473128 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135203 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.937977 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937977 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955334 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955334 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.469285 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.469285 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132950 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for overall accesses
2672,2706c2697,2731
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173717 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 17175.242815 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21082.676715 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43292.975324 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16624.510045 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16624.510045 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.086955 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.086955 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34777.783182 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34777.783182 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24734.100203 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28848.626951 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16713.285878 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20911.654953 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38554.249774 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16629.455757 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14988.192760 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14988.192760 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 672500 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672500 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32516.320161 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32516.320161 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24002.958087 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27197.704539 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161993.712996 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161509.164287 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161174.081166 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161174.081166 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161619.370955 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048 # average overall mshr uncacheable latency
2708,2713c2733,2738
< system.cpu1.toL2Bus.trans_dist::ReadReq 1243272 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 949021 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 4907 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 4907 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 137784 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 47376 # Transaction distribution
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 1277963 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 964810 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 138868 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 45574 # Transaction distribution
2715,2736c2740,2761
< system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 75841 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43101 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 89718 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 96830 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 79934 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1336034 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 901614 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17159 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 43403 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2298210 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42747664 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29480945 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 79768 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 72339053 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 592219 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1674781 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 3.301785 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.459032 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 76215 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43067 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 89621 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 96319 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 79290 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1344847 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 942237 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16928 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42916 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2346928 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43030144 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29597157 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29980 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78136 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 72735417 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 628857 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1745350 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 1.328609 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.469708 # Request fanout histogram
2739,2742c2764,2765
< system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::3 1169358 69.82% 69.82% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::4 505423 30.18% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::1 1171812 67.14% 67.14% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 573538 32.86% 100.00% # Request fanout histogram
2744,2747c2767,2770
< system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::total 1674781 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 730243456 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::total 1745350 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 748369465 # Layer occupancy (ticks)
2749c2772
< system.cpu1.toL2Bus.snoopLayer0.occupancy 87400998 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 88425999 # Layer occupancy (ticks)
2751c2774
< system.cpu1.toL2Bus.respLayer0.occupancy 1002964345 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 1009581341 # Layer occupancy (ticks)
2753c2776
< system.cpu1.toL2Bus.respLayer1.occupancy 454923751 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 468876167 # Layer occupancy (ticks)
2755c2778
< system.cpu1.toL2Bus.respLayer2.occupancy 9604282 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 9538553 # Layer occupancy (ticks)
2757c2780
< system.cpu1.toL2Bus.respLayer3.occupancy 23499938 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 23419937 # Layer occupancy (ticks)
2854c2877
< system.iobus.reqLayer27.occupancy 198996708 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 198987475 # Layer occupancy (ticks)
2860c2883
< system.iobus.respLayer3.occupancy 36791507 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36777012 # Layer occupancy (ticks)
2863c2886
< system.iocache.tags.tagsinuse 14.446927 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.446991 # Cycle average of tags in use
2867,2870c2890,2893
< system.iocache.tags.warmup_cycle 254830116000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.446927 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.902933 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.902933 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 254817991000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.446991 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.902937 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.902937 # Average percentage of cache occupancy
2884,2891c2907,2914
< system.iocache.ReadReq_miss_latency::realview.ide 32290377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 32290377 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6656632824 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 6656632824 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 32290377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 32290377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 32290377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 32290377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 32304877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 32304877 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652654586 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 6652654586 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 32304877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 32304877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 32304877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 32304877 # number of overall miss cycles
2908,2916c2931,2939
< system.iocache.ReadReq_avg_miss_latency::realview.ide 128136.416667 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 128136.416667 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183763.052783 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 183763.052783 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 128136.416667 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 128136.416667 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 23055 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 128193.956349 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 128193.956349 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183653.229516 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 183653.229516 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 128193.956349 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 128193.956349 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 22817 # number of cycles access was blocked
2918c2941
< system.iocache.blocked::no_mshrs 3532 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3477 # number of cycles access was blocked
2920c2943
< system.iocache.avg_blocked_cycles::no_mshrs 6.527463 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.562266 # average number of cycles each access was blocked
2934,2941c2957,2964
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 19155377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 19155377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772970838 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772970838 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 19155377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 19155377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 19155377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 19155377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 19198877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 19198877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768982610 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768982610 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 19198877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 19198877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 19198877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 19198877 # number of overall MSHR miss cycles
2950,2957c2973,2980
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76013.400794 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 76013.400794 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131762.666685 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131762.666685 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76186.019841 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76186.019841 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131652.567635 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131652.567635 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency
2959,2963c2982,2986
< system.l2c.tags.replacements 136223 # number of replacements
< system.l2c.tags.tagsinuse 64041.513044 # Cycle average of tags in use
< system.l2c.tags.total_refs 356136 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 200557 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 1.775735 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 130801 # number of replacements
> system.l2c.tags.tagsinuse 64048.619051 # Cycle average of tags in use
> system.l2c.tags.total_refs 351623 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 195125 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 1.802040 # Average number of references to valid blocks.
2965,2982c2988,3005
< system.l2c.tags.occ_blocks::writebacks 12781.567033 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.527645 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 1.082100 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5930.123644 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 1752.659752 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33401.860992 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.992291 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903251 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 3387.143441 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 1822.858320 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4939.794575 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.195031 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000237 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000017 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.090487 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.026743 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.509672 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000122 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::writebacks 12682.907006 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.525676 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048604 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 5727.667382 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 1961.871644 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34750.097208 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.787095 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903255 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 3571.469043 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 1470.884658 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3857.457480 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.193526 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.087397 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.029936 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.530244 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy
2984,3050c3007,3073
< system.l2c.tags.occ_percent::cpu1.inst 0.051684 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.027815 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.075375 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.977196 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 31391 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 32916 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 6119 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 25156 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 4913 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 27508 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.478989 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.502258 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 5099427 # Number of tag accesses
< system.l2c.tags.data_accesses 5099427 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 187 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 89 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 32294 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 45191 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 42802 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 60 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 34 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 17148 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 11819 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7598 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 157222 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 232253 # number of Writeback hits
< system.l2c.Writeback_hits::total 232253 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 2477 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 788 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 3265 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 61 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 3656 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1776 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5432 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 187 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 32294 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 48847 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 42802 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 60 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 17148 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 13595 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 7598 # number of demand (read+write) hits
< system.l2c.demand_hits::total 162654 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 187 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 32294 # number of overall hits
< system.l2c.overall_hits::cpu0.data 48847 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 42802 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 60 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 17148 # number of overall hits
< system.l2c.overall_hits::cpu1.data 13595 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 7598 # number of overall hits
< system.l2c.overall_hits::total 162654 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 28 # number of ReadReq misses
---
> system.l2c.tags.occ_percent::cpu1.inst 0.054496 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.022444 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058860 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.977304 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 31466 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 32827 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 6139 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 25208 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 4937 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 27395 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.480133 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.500900 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 5006121 # Number of tag accesses
> system.l2c.tags.data_accesses 5006121 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 169 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 31569 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 45303 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 43197 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 16772 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 11005 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7251 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 155435 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 227479 # number of Writeback hits
> system.l2c.Writeback_hits::total 227479 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 2575 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 820 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 3395 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 3872 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 2196 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 6068 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 169 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 31569 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 49175 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 43197 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 16772 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 7251 # number of demand (read+write) hits
> system.l2c.demand_hits::total 161503 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 169 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 31569 # number of overall hits
> system.l2c.overall_hits::cpu0.data 49175 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 43197 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 16772 # number of overall hits
> system.l2c.overall_hits::cpu1.data 13201 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 7251 # number of overall hits
> system.l2c.overall_hits::total 161503 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses
3052,3055c3075,3078
< system.l2c.ReadReq_misses::cpu0.inst 17722 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 8264 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.inst 17327 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 8118 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
3057,3070c3080,3093
< system.l2c.ReadReq_misses::cpu1.inst 5101 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 2487 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 174741 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 8406 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3815 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 12221 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 945 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1142 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 2087 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11293 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 9270 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 20563 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu1.inst 5250 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 2138 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 171166 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 8455 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 3870 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 12325 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 920 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1168 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 2088 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 10724 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 8176 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 18900 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses
3072,3075c3095,3098
< system.l2c.demand_misses::cpu0.inst 17722 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 19557 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 17327 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 18842 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
3077,3081c3100,3104
< system.l2c.demand_misses::cpu1.inst 5101 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 11757 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) misses
< system.l2c.demand_misses::total 195304 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses
---
> system.l2c.demand_misses::cpu1.inst 5250 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 10314 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) misses
> system.l2c.demand_misses::total 190066 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses
3083,3086c3106,3109
< system.l2c.overall_misses::cpu0.inst 17722 # number of overall misses
< system.l2c.overall_misses::cpu0.data 19557 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 130446 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 17327 # number of overall misses
> system.l2c.overall_misses::cpu0.data 18842 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 128828 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
3088,3262c3111,3285
< system.l2c.overall_misses::cpu1.inst 5101 # number of overall misses
< system.l2c.overall_misses::cpu1.data 11757 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 10677 # number of overall misses
< system.l2c.overall_misses::total 195304 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2541750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 428750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 1457831781 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 749814704 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 937500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 434889757 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 222071664 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 18802084724 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 7178272 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 2845410 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 10023682 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1135970 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 748476 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 1884446 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1078166540 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 778316723 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1856483263 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 2541750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 428750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1457831781 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1827981244 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 937500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 434889757 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1000388387 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 20658567987 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 2541750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 428750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1457831781 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1827981244 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 937500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 434889757 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1000388387 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 20658567987 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 215 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 94 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 50016 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 53455 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 173248 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 70 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 22249 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 14306 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 18275 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 331963 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 232253 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 232253 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 10883 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 4603 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 15486 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 1194 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1203 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2397 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 14949 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 11046 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 25995 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 215 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 50016 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 68404 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173248 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 70 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 22249 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 25352 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18275 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 357958 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 215 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 50016 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 68404 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173248 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 70 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 22249 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 25352 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18275 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 357958 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.053191 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.354327 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.154597 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.028571 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.229269 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.173843 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.526387 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.772397 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828807 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.789164 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.791457 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.949293 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.870672 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.755435 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.839218 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.791037 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.053191 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.354327 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.285904 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.028571 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.229269 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.463750 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.545606 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.053191 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.354327 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.285904 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.028571 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.229269 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.463750 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.545606 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85750 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82261.131983 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 90732.660213 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93750 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85255.784552 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 89292.989144 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 107599.731740 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 853.946229 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 745.847969 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 820.201457 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1202.084656 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 655.408056 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 902.944897 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95472.110157 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83960.811543 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 90282.705004 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 105776.471485 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 105776.471485 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 1085 # number of cycles access was blocked
---
> system.l2c.overall_misses::cpu1.inst 5250 # number of overall misses
> system.l2c.overall_misses::cpu1.data 10314 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 9461 # number of overall misses
> system.l2c.overall_misses::total 190066 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2599500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 443500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 1426835542 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 735252946 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1206000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 97250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 448103000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 186224591 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 18394990666 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 7116778 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 2985907 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 10102685 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1350463 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1030967 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 2381430 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1037256751 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 678589231 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 1715845982 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 2599500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 443500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1426835542 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 1772509697 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 1206000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 97250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 448103000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 864813822 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 20110836648 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 2599500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 443500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1426835542 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 1772509697 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 1206000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 97250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 448103000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 864813822 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 20110836648 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 196 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 73 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 48896 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 53421 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 172025 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 79 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 34 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 22022 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 13143 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 16712 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 326601 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 227479 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 227479 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 11030 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 4690 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 15720 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 1175 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1266 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2441 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 14596 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 10372 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 24968 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 196 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 48896 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 68017 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 172025 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 79 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 22022 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 23515 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16712 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 351569 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 196 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 48896 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 68017 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 172025 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 79 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 34 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 22022 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 23515 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16712 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 351569 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.068493 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.354364 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.151963 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.029412 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.238398 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.162672 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.524083 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.766546 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.825160 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.784033 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.782979 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.922591 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.855387 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.734722 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.788276 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.756969 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.068493 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.354364 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.277019 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.029412 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.238398 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.438614 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.540622 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.068493 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.354364 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.277019 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.029412 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.238398 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.438614 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.540622 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88700 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82347.523634 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 90570.700419 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 97250 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85352.952381 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 87102.240879 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 107468.718472 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 841.724187 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 771.552196 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 819.690467 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1467.894565 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 882.677226 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1140.531609 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96722.934633 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82997.704379 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 90785.501693 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 105809.753707 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 105809.753707 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 234 # number of cycles access was blocked
3264c3287
< system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
3266c3289
< system.l2c.avg_blocked_cycles::no_mshrs 108.500000 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 117 # average number of cycles each access was blocked
3270,3281c3293,3304
< system.l2c.writebacks::writebacks 103197 # number of writebacks
< system.l2c.writebacks::total 103197 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu0.inst 16 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.inst 12 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 16 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 12 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 16 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 12 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 28 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 28 # number of ReadReq MSHR misses
---
> system.l2c.writebacks::writebacks 98707 # number of writebacks
> system.l2c.writebacks::total 98707 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses
3283,3286c3306,3309
< system.l2c.ReadReq_mshr_misses::cpu0.inst 17706 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 8264 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 17319 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 8118 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses
3288,3301c3311,3324
< system.l2c.ReadReq_mshr_misses::cpu1.inst 5089 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 2487 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 174713 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 8406 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 3815 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 12221 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 945 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1142 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 2087 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11293 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 9270 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 20563 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 28 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu1.inst 5241 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 2138 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 171149 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8455 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 3870 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 12325 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 920 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1168 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 2088 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 10724 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 8176 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 18900 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses
3303,3306c3326,3329
< system.l2c.demand_mshr_misses::cpu0.inst 17706 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 19557 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 17319 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 18842 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
3308,3312c3331,3335
< system.l2c.demand_mshr_misses::cpu1.inst 5089 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 11757 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 195276 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 28 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.inst 5241 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 10314 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 190049 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses
3314,3317c3337,3340
< system.l2c.overall_mshr_misses::cpu0.inst 17706 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 19557 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 17319 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 18842 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
3319,3364c3342,3400
< system.l2c.overall_mshr_misses::cpu1.inst 5089 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 11757 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 195276 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 365750 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1235097219 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 646670292 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 812500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 70500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370572993 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 190918836 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 16645401734 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 149850873 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 67813301 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 217664174 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16896440 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20270643 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 37167083 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 939052460 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 662623777 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 1601676237 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 365750 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1235097219 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 1585722752 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 812500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 70500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 370572993 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 853542613 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 18247077971 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 365750 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1235097219 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 1585722752 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 812500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 70500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 370572993 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 853542613 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 18247077971 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_misses::cpu1.inst 5241 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 10314 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 190049 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17055 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 38122 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 31055 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31396 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 69177 # number of overall MSHR uncacheable misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 380000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1209530708 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 633945550 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 84250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 381902000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 159442409 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 16282699204 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 150732427 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 68800353 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 219532780 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16443920 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20736167 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 37180087 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 905183749 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 576557769 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 1481741518 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 380000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1209530708 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 1539129299 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 84250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 381902000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 736000178 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 17764440722 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 380000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1209530708 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 1539129299 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 84250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 381902000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 736000178 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 17764440722 # number of overall MSHR miss cycles
3366,3372c3402,3408
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4804405000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5954500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 824214500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 5816053250 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3576332065 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 720875502 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4297207567 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3198370250 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5885000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430251250 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 5815985750 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2250411545 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2045879002 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4296290547 # number of WriteReq MSHR uncacheable cycles
3374,3474c3410,3510
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8380737065 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5954500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1545090002 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 10113260817 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154597 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173843 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.526303 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772397 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828807 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.789164 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791457 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949293 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.870672 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755435 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.839218 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.791037 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.545528 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.545528 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78251.487415 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76766.721351 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 95272.828776 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17826.656317 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17775.439318 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17810.668030 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17879.830688 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17750.125219 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17808.856253 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83153.498627 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71480.450593 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 77891.175266 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5448781795 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5885000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4476130252 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10112276297 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.151963 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.162672 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.524031 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.766546 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.825160 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.784033 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.782979 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.922591 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855387 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.734722 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.788276 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.756969 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.540574 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.540574 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78091.346391 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74575.495323 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 95137.565536 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17827.608161 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.868992 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.990264 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17873.826087 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17753.567637 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17806.555077 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84407.287300 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70518.318126 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 78399.022116 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606 # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115 # average overall mshr uncacheable latency
3476,3480c3512,3516
< system.membus.trans_dist::ReadReq 213069 # Transaction distribution
< system.membus.trans_dist::ReadResp 213068 # Transaction distribution
< system.membus.trans_dist::WriteReq 31079 # Transaction distribution
< system.membus.trans_dist::WriteResp 31079 # Transaction distribution
< system.membus.trans_dist::Writeback 139403 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 209523 # Transaction distribution
> system.membus.trans_dist::ReadResp 209522 # Transaction distribution
> system.membus.trans_dist::WriteReq 31055 # Transaction distribution
> system.membus.trans_dist::WriteResp 31055 # Transaction distribution
> system.membus.trans_dist::Writeback 134913 # Transaction distribution
3483c3519
< system.membus.trans_dist::UpgradeReq 77234 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 78034 # Transaction distribution
3485,3488c3521,3524
< system.membus.trans_dist::UpgradeResp 14409 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
< system.membus.trans_dist::ReadExReq 40484 # Transaction distribution
< system.membus.trans_dist::ReadExResp 20462 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 14508 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
> system.membus.trans_dist::ReadExReq 38508 # Transaction distribution
> system.membus.trans_dist::ReadExResp 18805 # Transaction distribution
3491,3493c3527,3529
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14202 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662750 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 784904 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14300 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648289 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 770541 # Packet count per connected master and slave (bytes)
3496c3532
< system.membus.pkt_count::total 893825 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 879462 # Packet count per connected master and slave (bytes)
3499,3501c3535,3537
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28404 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19143964 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 19335481 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28600 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18522228 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18713941 # Cumulative packet size per connected master and slave (bytes)
3504,3506c3540,3542
< system.membus.pkt_size::total 23971961 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 125081 # Total snoops (count)
< system.membus.snoop_fanout::samples 510035 # Request fanout histogram
---
> system.membus.pkt_size::total 23350421 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 125464 # Total snoops (count)
> system.membus.snoop_fanout::samples 569969 # Request fanout histogram
3511c3547
< system.membus.snoop_fanout::1 510035 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 569969 100.00% 100.00% # Request fanout histogram
3516,3517c3552,3553
< system.membus.snoop_fanout::total 510035 # Request fanout histogram
< system.membus.reqLayer0.occupancy 81680000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 569969 # Request fanout histogram
> system.membus.reqLayer0.occupancy 81685500 # Layer occupancy (ticks)
3521c3557
< system.membus.reqLayer2.occupancy 11944988 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 12047488 # Layer occupancy (ticks)
3523c3559
< system.membus.reqLayer5.occupancy 1164089698 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1135057072 # Layer occupancy (ticks)
3525c3561
< system.membus.respLayer2.occupancy 1154561869 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1127535962 # Layer occupancy (ticks)
3527c3563
< system.membus.respLayer3.occupancy 37506493 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 37496988 # Layer occupancy (ticks)
3560,3582c3596,3618
< system.toL2Bus.trans_dist::ReadReq 494432 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 494416 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 31079 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 31079 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 232253 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 80398 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 41961 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 122359 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 50963 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 50963 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1036150 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339974 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1376124 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31294456 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6755201 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 38049657 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 290334 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 898197 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.040648 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.197474 # Request fanout histogram
---
> system.toL2Bus.trans_dist::ReadReq 490298 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 490282 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 227479 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 81334 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 42004 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 123338 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 50269 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 50269 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 990291 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 371073 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1361364 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 30980096 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6355093 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 37335189 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 292587 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 958737 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.038087 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.191405 # Request fanout histogram
3585,3586c3621,3622
< system.toL2Bus.snoop_fanout::1 861687 95.94% 95.94% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 36510 4.06% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 922222 96.19% 96.19% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 36515 3.81% 100.00% # Request fanout histogram
3590,3591c3626,3627
< system.toL2Bus.snoop_fanout::total 898197 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 772973190 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 958737 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 763418418 # Layer occupancy (ticks)
3595c3631
< system.toL2Bus.respLayer0.occupancy 636594669 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 618495385 # Layer occupancy (ticks)
3597c3633
< system.toL2Bus.respLayer1.occupancy 265283017 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 276060555 # Layer occupancy (ticks)
3602c3638
< system.cpu1.kern.inst.quiesce 2748 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed